2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/cutils.h"
23 #include "exec/exec-all.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/cpus.h"
28 #include "qemu/error-report.h"
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
38 #if defined(CONFIG_KVM)
39 #include <linux/kvm_para.h>
42 #include "sysemu/sysemu.h"
43 #include "hw/qdev-properties.h"
44 #include "hw/i386/topology.h"
45 #ifndef CONFIG_USER_ONLY
46 #include "exec/address-spaces.h"
48 #include "hw/xen/xen.h"
49 #include "hw/i386/apic_internal.h"
53 /* Cache topology CPUID constants: */
55 /* CPUID Leaf 2 Descriptors */
57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
59 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
60 #define CPUID_2_L3_16MB_16WAY_64B 0x4d
63 /* CPUID Leaf 4 constants: */
66 #define CPUID_4_TYPE_DCACHE 1
67 #define CPUID_4_TYPE_ICACHE 2
68 #define CPUID_4_TYPE_UNIFIED 3
70 #define CPUID_4_LEVEL(l) ((l) << 5)
72 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73 #define CPUID_4_FULLY_ASSOC (1 << 9)
76 #define CPUID_4_NO_INVD_SHARING (1 << 0)
77 #define CPUID_4_INCLUSIVE (1 << 1)
78 #define CPUID_4_COMPLEX_IDX (1 << 2)
80 #define ASSOC_FULL 0xFF
82 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
97 /* Definitions of the hardcoded cache entries we expose: */
100 #define L1D_LINE_SIZE 64
101 #define L1D_ASSOCIATIVITY 8
103 #define L1D_PARTITIONS 1
104 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107 #define L1D_LINES_PER_TAG 1
108 #define L1D_SIZE_KB_AMD 64
109 #define L1D_ASSOCIATIVITY_AMD 2
111 /* L1 instruction cache: */
112 #define L1I_LINE_SIZE 64
113 #define L1I_ASSOCIATIVITY 8
115 #define L1I_PARTITIONS 1
116 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119 #define L1I_LINES_PER_TAG 1
120 #define L1I_SIZE_KB_AMD 64
121 #define L1I_ASSOCIATIVITY_AMD 2
123 /* Level 2 unified cache: */
124 #define L2_LINE_SIZE 64
125 #define L2_ASSOCIATIVITY 16
127 #define L2_PARTITIONS 1
128 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132 #define L2_LINES_PER_TAG 1
133 #define L2_SIZE_KB_AMD 512
135 /* Level 3 unified cache: */
136 #define L3_SIZE_KB 0 /* disabled */
137 #define L3_ASSOCIATIVITY 0 /* disabled */
138 #define L3_LINES_PER_TAG 0 /* disabled */
139 #define L3_LINE_SIZE 0 /* disabled */
140 #define L3_N_LINE_SIZE 64
141 #define L3_N_ASSOCIATIVITY 16
142 #define L3_N_SETS 16384
143 #define L3_N_PARTITIONS 1
144 #define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
145 #define L3_N_LINES_PER_TAG 1
146 #define L3_N_SIZE_KB_AMD 16384
148 /* TLB definitions: */
150 #define L1_DTLB_2M_ASSOC 1
151 #define L1_DTLB_2M_ENTRIES 255
152 #define L1_DTLB_4K_ASSOC 1
153 #define L1_DTLB_4K_ENTRIES 255
155 #define L1_ITLB_2M_ASSOC 1
156 #define L1_ITLB_2M_ENTRIES 255
157 #define L1_ITLB_4K_ASSOC 1
158 #define L1_ITLB_4K_ENTRIES 255
160 #define L2_DTLB_2M_ASSOC 0 /* disabled */
161 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
162 #define L2_DTLB_4K_ASSOC 4
163 #define L2_DTLB_4K_ENTRIES 512
165 #define L2_ITLB_2M_ASSOC 0 /* disabled */
166 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
167 #define L2_ITLB_4K_ASSOC 4
168 #define L2_ITLB_4K_ENTRIES 512
172 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
173 uint32_t vendor2
, uint32_t vendor3
)
176 for (i
= 0; i
< 4; i
++) {
177 dst
[i
] = vendor1
>> (8 * i
);
178 dst
[i
+ 4] = vendor2
>> (8 * i
);
179 dst
[i
+ 8] = vendor3
>> (8 * i
);
181 dst
[CPUID_VENDOR_SZ
] = '\0';
184 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
185 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
186 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
187 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
188 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
189 CPUID_PSE36 | CPUID_FXSR)
190 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
191 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
193 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
194 CPUID_PAE | CPUID_SEP | CPUID_APIC)
196 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
197 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
198 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
199 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
200 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
201 /* partly implemented:
202 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
204 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
205 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
206 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
207 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
208 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
209 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
211 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
212 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
213 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
214 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
215 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
218 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
220 #define TCG_EXT2_X86_64_FEATURES 0
223 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
224 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
225 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
226 TCG_EXT2_X86_64_FEATURES)
227 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
228 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
229 #define TCG_EXT4_FEATURES 0
230 #define TCG_SVM_FEATURES 0
231 #define TCG_KVM_FEATURES 0
232 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
233 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
234 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
235 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
238 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
239 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
240 CPUID_7_0_EBX_RDSEED */
241 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
243 #define TCG_7_0_EDX_FEATURES 0
244 #define TCG_APM_FEATURES 0
245 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
246 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
248 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
250 typedef struct FeatureWordInfo
{
251 /* feature flags names are taken from "Intel Processor Identification and
252 * the CPUID Instruction" and AMD's "CPUID Specification".
253 * In cases of disagreement between feature naming conventions,
254 * aliases may be added.
256 const char *feat_names
[32];
257 uint32_t cpuid_eax
; /* Input EAX for CPUID */
258 bool cpuid_needs_ecx
; /* CPUID instruction uses ECX as input */
259 uint32_t cpuid_ecx
; /* Input ECX value for CPUID */
260 int cpuid_reg
; /* output register (R_* constant) */
261 uint32_t tcg_features
; /* Feature flags supported by TCG */
262 uint32_t unmigratable_flags
; /* Feature flags known to be unmigratable */
263 uint32_t migratable_flags
; /* Feature flags known to be migratable */
266 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
269 "fpu", "vme", "de", "pse",
270 "tsc", "msr", "pae", "mce",
271 "cx8", "apic", NULL
, "sep",
272 "mtrr", "pge", "mca", "cmov",
273 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
274 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
275 "fxsr", "sse", "sse2", "ss",
276 "ht" /* Intel htt */, "tm", "ia64", "pbe",
278 .cpuid_eax
= 1, .cpuid_reg
= R_EDX
,
279 .tcg_features
= TCG_FEATURES
,
283 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
284 "ds-cpl", "vmx", "smx", "est",
285 "tm2", "ssse3", "cid", NULL
,
286 "fma", "cx16", "xtpr", "pdcm",
287 NULL
, "pcid", "dca", "sse4.1",
288 "sse4.2", "x2apic", "movbe", "popcnt",
289 "tsc-deadline", "aes", "xsave", "osxsave",
290 "avx", "f16c", "rdrand", "hypervisor",
292 .cpuid_eax
= 1, .cpuid_reg
= R_ECX
,
293 .tcg_features
= TCG_EXT_FEATURES
,
295 /* Feature names that are already defined on feature_name[] but
296 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
297 * names on feat_names below. They are copied automatically
298 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
300 [FEAT_8000_0001_EDX
] = {
302 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
303 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
304 NULL
/* cx8 */, NULL
/* apic */, NULL
, "syscall",
305 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
306 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
307 "nx", NULL
, "mmxext", NULL
/* mmx */,
308 NULL
/* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
309 NULL
, "lm", "3dnowext", "3dnow",
311 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_EDX
,
312 .tcg_features
= TCG_EXT2_FEATURES
,
314 [FEAT_8000_0001_ECX
] = {
316 "lahf-lm", "cmp-legacy", "svm", "extapic",
317 "cr8legacy", "abm", "sse4a", "misalignsse",
318 "3dnowprefetch", "osvw", "ibs", "xop",
319 "skinit", "wdt", NULL
, "lwp",
320 "fma4", "tce", NULL
, "nodeid-msr",
321 NULL
, "tbm", "topoext", "perfctr-core",
322 "perfctr-nb", NULL
, NULL
, NULL
,
323 NULL
, NULL
, NULL
, NULL
,
325 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_ECX
,
326 .tcg_features
= TCG_EXT3_FEATURES
,
328 [FEAT_C000_0001_EDX
] = {
330 NULL
, NULL
, "xstore", "xstore-en",
331 NULL
, NULL
, "xcrypt", "xcrypt-en",
332 "ace2", "ace2-en", "phe", "phe-en",
333 "pmm", "pmm-en", NULL
, NULL
,
334 NULL
, NULL
, NULL
, NULL
,
335 NULL
, NULL
, NULL
, NULL
,
336 NULL
, NULL
, NULL
, NULL
,
337 NULL
, NULL
, NULL
, NULL
,
339 .cpuid_eax
= 0xC0000001, .cpuid_reg
= R_EDX
,
340 .tcg_features
= TCG_EXT4_FEATURES
,
344 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
345 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
346 NULL
, NULL
, NULL
, NULL
,
347 NULL
, NULL
, NULL
, NULL
,
348 NULL
, NULL
, NULL
, NULL
,
349 NULL
, NULL
, NULL
, NULL
,
350 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
351 NULL
, NULL
, NULL
, NULL
,
353 .cpuid_eax
= KVM_CPUID_FEATURES
, .cpuid_reg
= R_EAX
,
354 .tcg_features
= TCG_KVM_FEATURES
,
356 [FEAT_HYPERV_EAX
] = {
358 NULL
/* hv_msr_vp_runtime_access */, NULL
/* hv_msr_time_refcount_access */,
359 NULL
/* hv_msr_synic_access */, NULL
/* hv_msr_stimer_access */,
360 NULL
/* hv_msr_apic_access */, NULL
/* hv_msr_hypercall_access */,
361 NULL
/* hv_vpindex_access */, NULL
/* hv_msr_reset_access */,
362 NULL
/* hv_msr_stats_access */, NULL
/* hv_reftsc_access */,
363 NULL
/* hv_msr_idle_access */, NULL
/* hv_msr_frequency_access */,
364 NULL
, NULL
, NULL
, NULL
,
365 NULL
, NULL
, NULL
, NULL
,
366 NULL
, NULL
, NULL
, NULL
,
367 NULL
, NULL
, NULL
, NULL
,
368 NULL
, NULL
, NULL
, NULL
,
370 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EAX
,
372 [FEAT_HYPERV_EBX
] = {
374 NULL
/* hv_create_partitions */, NULL
/* hv_access_partition_id */,
375 NULL
/* hv_access_memory_pool */, NULL
/* hv_adjust_message_buffers */,
376 NULL
/* hv_post_messages */, NULL
/* hv_signal_events */,
377 NULL
/* hv_create_port */, NULL
/* hv_connect_port */,
378 NULL
/* hv_access_stats */, NULL
, NULL
, NULL
/* hv_debugging */,
379 NULL
/* hv_cpu_power_management */, NULL
/* hv_configure_profiler */,
381 NULL
, NULL
, NULL
, NULL
,
382 NULL
, NULL
, NULL
, NULL
,
383 NULL
, NULL
, NULL
, NULL
,
384 NULL
, NULL
, NULL
, NULL
,
386 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EBX
,
388 [FEAT_HYPERV_EDX
] = {
390 NULL
/* hv_mwait */, NULL
/* hv_guest_debugging */,
391 NULL
/* hv_perf_monitor */, NULL
/* hv_cpu_dynamic_part */,
392 NULL
/* hv_hypercall_params_xmm */, NULL
/* hv_guest_idle_state */,
394 NULL
, NULL
, NULL
/* hv_guest_crash_msr */, NULL
,
395 NULL
, NULL
, NULL
, NULL
,
396 NULL
, NULL
, NULL
, NULL
,
397 NULL
, NULL
, NULL
, NULL
,
398 NULL
, NULL
, NULL
, NULL
,
399 NULL
, NULL
, NULL
, NULL
,
401 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EDX
,
405 "npt", "lbrv", "svm-lock", "nrip-save",
406 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
407 NULL
, NULL
, "pause-filter", NULL
,
408 "pfthreshold", NULL
, NULL
, NULL
,
409 NULL
, NULL
, NULL
, NULL
,
410 NULL
, NULL
, NULL
, NULL
,
411 NULL
, NULL
, NULL
, NULL
,
412 NULL
, NULL
, NULL
, NULL
,
414 .cpuid_eax
= 0x8000000A, .cpuid_reg
= R_EDX
,
415 .tcg_features
= TCG_SVM_FEATURES
,
419 "fsgsbase", "tsc-adjust", NULL
, "bmi1",
420 "hle", "avx2", NULL
, "smep",
421 "bmi2", "erms", "invpcid", "rtm",
422 NULL
, NULL
, "mpx", NULL
,
423 "avx512f", "avx512dq", "rdseed", "adx",
424 "smap", "avx512ifma", "pcommit", "clflushopt",
425 "clwb", NULL
, "avx512pf", "avx512er",
426 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
429 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
431 .tcg_features
= TCG_7_0_EBX_FEATURES
,
435 NULL
, "avx512vbmi", "umip", "pku",
436 "ospke", NULL
, NULL
, NULL
,
437 NULL
, NULL
, NULL
, NULL
,
438 NULL
, NULL
, NULL
, NULL
,
439 "la57", NULL
, NULL
, NULL
,
440 NULL
, NULL
, "rdpid", NULL
,
441 NULL
, NULL
, NULL
, NULL
,
442 NULL
, NULL
, NULL
, NULL
,
445 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
447 .tcg_features
= TCG_7_0_ECX_FEATURES
,
451 NULL
, NULL
, "avx512-4vnniw", "avx512-4fmaps",
452 NULL
, NULL
, NULL
, NULL
,
453 NULL
, NULL
, NULL
, NULL
,
454 NULL
, NULL
, NULL
, NULL
,
455 NULL
, NULL
, NULL
, NULL
,
456 NULL
, NULL
, NULL
, NULL
,
457 NULL
, NULL
, NULL
, NULL
,
458 NULL
, NULL
, NULL
, NULL
,
461 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
463 .tcg_features
= TCG_7_0_EDX_FEATURES
,
465 [FEAT_8000_0007_EDX
] = {
467 NULL
, NULL
, NULL
, NULL
,
468 NULL
, NULL
, NULL
, NULL
,
469 "invtsc", NULL
, NULL
, NULL
,
470 NULL
, NULL
, NULL
, NULL
,
471 NULL
, NULL
, NULL
, NULL
,
472 NULL
, NULL
, NULL
, NULL
,
473 NULL
, NULL
, NULL
, NULL
,
474 NULL
, NULL
, NULL
, NULL
,
476 .cpuid_eax
= 0x80000007,
478 .tcg_features
= TCG_APM_FEATURES
,
479 .unmigratable_flags
= CPUID_APM_INVTSC
,
483 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
484 NULL
, NULL
, NULL
, NULL
,
485 NULL
, NULL
, NULL
, NULL
,
486 NULL
, NULL
, NULL
, NULL
,
487 NULL
, NULL
, NULL
, NULL
,
488 NULL
, NULL
, NULL
, NULL
,
489 NULL
, NULL
, NULL
, NULL
,
490 NULL
, NULL
, NULL
, NULL
,
493 .cpuid_needs_ecx
= true, .cpuid_ecx
= 1,
495 .tcg_features
= TCG_XSAVE_FEATURES
,
499 NULL
, NULL
, "arat", NULL
,
500 NULL
, NULL
, NULL
, NULL
,
501 NULL
, NULL
, NULL
, NULL
,
502 NULL
, NULL
, NULL
, NULL
,
503 NULL
, NULL
, NULL
, NULL
,
504 NULL
, NULL
, NULL
, NULL
,
505 NULL
, NULL
, NULL
, NULL
,
506 NULL
, NULL
, NULL
, NULL
,
508 .cpuid_eax
= 6, .cpuid_reg
= R_EAX
,
509 .tcg_features
= TCG_6_EAX_FEATURES
,
511 [FEAT_XSAVE_COMP_LO
] = {
513 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
516 .migratable_flags
= XSTATE_FP_MASK
| XSTATE_SSE_MASK
|
517 XSTATE_YMM_MASK
| XSTATE_BNDREGS_MASK
| XSTATE_BNDCSR_MASK
|
518 XSTATE_OPMASK_MASK
| XSTATE_ZMM_Hi256_MASK
| XSTATE_Hi16_ZMM_MASK
|
521 [FEAT_XSAVE_COMP_HI
] = {
523 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
529 typedef struct X86RegisterInfo32
{
530 /* Name of register */
532 /* QAPI enum value register */
533 X86CPURegister32 qapi_enum
;
536 #define REGISTER(reg) \
537 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
538 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
550 typedef struct ExtSaveArea
{
551 uint32_t feature
, bits
;
552 uint32_t offset
, size
;
555 static const ExtSaveArea x86_ext_save_areas
[] = {
557 /* x87 FP state component is always enabled if XSAVE is supported */
558 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
559 /* x87 state is in the legacy region of the XSAVE area */
561 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
564 /* SSE state component is always enabled if XSAVE is supported */
565 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
566 /* SSE state is in the legacy region of the XSAVE area */
568 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
571 { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
572 .offset
= offsetof(X86XSaveArea
, avx_state
),
573 .size
= sizeof(XSaveAVX
) },
574 [XSTATE_BNDREGS_BIT
] =
575 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
576 .offset
= offsetof(X86XSaveArea
, bndreg_state
),
577 .size
= sizeof(XSaveBNDREG
) },
578 [XSTATE_BNDCSR_BIT
] =
579 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
580 .offset
= offsetof(X86XSaveArea
, bndcsr_state
),
581 .size
= sizeof(XSaveBNDCSR
) },
582 [XSTATE_OPMASK_BIT
] =
583 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
584 .offset
= offsetof(X86XSaveArea
, opmask_state
),
585 .size
= sizeof(XSaveOpmask
) },
586 [XSTATE_ZMM_Hi256_BIT
] =
587 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
588 .offset
= offsetof(X86XSaveArea
, zmm_hi256_state
),
589 .size
= sizeof(XSaveZMM_Hi256
) },
590 [XSTATE_Hi16_ZMM_BIT
] =
591 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
592 .offset
= offsetof(X86XSaveArea
, hi16_zmm_state
),
593 .size
= sizeof(XSaveHi16_ZMM
) },
595 { .feature
= FEAT_7_0_ECX
, .bits
= CPUID_7_0_ECX_PKU
,
596 .offset
= offsetof(X86XSaveArea
, pkru_state
),
597 .size
= sizeof(XSavePKRU
) },
600 static uint32_t xsave_area_size(uint64_t mask
)
605 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
606 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
607 if ((mask
>> i
) & 1) {
608 ret
= MAX(ret
, esa
->offset
+ esa
->size
);
614 static inline uint64_t x86_cpu_xsave_components(X86CPU
*cpu
)
616 return ((uint64_t)cpu
->env
.features
[FEAT_XSAVE_COMP_HI
]) << 32 |
617 cpu
->env
.features
[FEAT_XSAVE_COMP_LO
];
620 const char *get_register_name_32(unsigned int reg
)
622 if (reg
>= CPU_NB_REGS32
) {
625 return x86_reg_info_32
[reg
].name
;
629 * Returns the set of feature flags that are supported and migratable by
630 * QEMU, for a given FeatureWord.
632 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w
)
634 FeatureWordInfo
*wi
= &feature_word_info
[w
];
638 for (i
= 0; i
< 32; i
++) {
639 uint32_t f
= 1U << i
;
641 /* If the feature name is known, it is implicitly considered migratable,
642 * unless it is explicitly set in unmigratable_flags */
643 if ((wi
->migratable_flags
& f
) ||
644 (wi
->feat_names
[i
] && !(wi
->unmigratable_flags
& f
))) {
651 void host_cpuid(uint32_t function
, uint32_t count
,
652 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
658 : "=a"(vec
[0]), "=b"(vec
[1]),
659 "=c"(vec
[2]), "=d"(vec
[3])
660 : "0"(function
), "c"(count
) : "cc");
661 #elif defined(__i386__)
662 asm volatile("pusha \n\t"
664 "mov %%eax, 0(%2) \n\t"
665 "mov %%ebx, 4(%2) \n\t"
666 "mov %%ecx, 8(%2) \n\t"
667 "mov %%edx, 12(%2) \n\t"
669 : : "a"(function
), "c"(count
), "S"(vec
)
685 /* CPU class name definitions: */
687 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
688 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
690 /* Return type name for a given CPU model name
691 * Caller is responsible for freeing the returned string.
693 static char *x86_cpu_type_name(const char *model_name
)
695 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
698 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
703 if (cpu_model
== NULL
) {
707 typename
= x86_cpu_type_name(cpu_model
);
708 oc
= object_class_by_name(typename
);
713 static char *x86_cpu_class_get_model_name(X86CPUClass
*cc
)
715 const char *class_name
= object_class_get_name(OBJECT_CLASS(cc
));
716 assert(g_str_has_suffix(class_name
, X86_CPU_TYPE_SUFFIX
));
717 return g_strndup(class_name
,
718 strlen(class_name
) - strlen(X86_CPU_TYPE_SUFFIX
));
721 struct X86CPUDefinition
{
725 /* vendor is zero-terminated, 12 character ASCII string */
726 char vendor
[CPUID_VENDOR_SZ
+ 1];
730 FeatureWordArray features
;
734 static X86CPUDefinition builtin_x86_defs
[] = {
738 .vendor
= CPUID_VENDOR_AMD
,
742 .features
[FEAT_1_EDX
] =
744 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
746 .features
[FEAT_1_ECX
] =
747 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
748 .features
[FEAT_8000_0001_EDX
] =
749 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
750 .features
[FEAT_8000_0001_ECX
] =
751 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
,
752 .xlevel
= 0x8000000A,
753 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
758 .vendor
= CPUID_VENDOR_AMD
,
762 /* Missing: CPUID_HT */
763 .features
[FEAT_1_EDX
] =
765 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
766 CPUID_PSE36
| CPUID_VME
,
767 .features
[FEAT_1_ECX
] =
768 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
770 .features
[FEAT_8000_0001_EDX
] =
771 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
772 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
773 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
774 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
776 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
777 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
778 .features
[FEAT_8000_0001_ECX
] =
779 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
780 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
781 /* Missing: CPUID_SVM_LBRV */
782 .features
[FEAT_SVM
] =
784 .xlevel
= 0x8000001A,
785 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
790 .vendor
= CPUID_VENDOR_INTEL
,
794 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
795 .features
[FEAT_1_EDX
] =
797 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
798 CPUID_PSE36
| CPUID_VME
| CPUID_ACPI
| CPUID_SS
,
799 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
800 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
801 .features
[FEAT_1_ECX
] =
802 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
804 .features
[FEAT_8000_0001_EDX
] =
805 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
806 .features
[FEAT_8000_0001_ECX
] =
808 .xlevel
= 0x80000008,
809 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
814 .vendor
= CPUID_VENDOR_INTEL
,
818 /* Missing: CPUID_HT */
819 .features
[FEAT_1_EDX
] =
820 PPRO_FEATURES
| CPUID_VME
|
821 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
823 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
824 .features
[FEAT_1_ECX
] =
825 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
826 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
827 .features
[FEAT_8000_0001_EDX
] =
828 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
829 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
830 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
831 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
832 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
833 .features
[FEAT_8000_0001_ECX
] =
835 .xlevel
= 0x80000008,
836 .model_id
= "Common KVM processor"
841 .vendor
= CPUID_VENDOR_INTEL
,
845 .features
[FEAT_1_EDX
] =
847 .features
[FEAT_1_ECX
] =
849 .xlevel
= 0x80000004,
850 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
855 .vendor
= CPUID_VENDOR_INTEL
,
859 .features
[FEAT_1_EDX
] =
860 PPRO_FEATURES
| CPUID_VME
|
861 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
862 .features
[FEAT_1_ECX
] =
864 .features
[FEAT_8000_0001_ECX
] =
866 .xlevel
= 0x80000008,
867 .model_id
= "Common 32-bit KVM processor"
872 .vendor
= CPUID_VENDOR_INTEL
,
876 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
877 .features
[FEAT_1_EDX
] =
878 PPRO_FEATURES
| CPUID_VME
|
879 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_ACPI
|
881 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
882 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
883 .features
[FEAT_1_ECX
] =
884 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
885 .features
[FEAT_8000_0001_EDX
] =
887 .xlevel
= 0x80000008,
888 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
893 .vendor
= CPUID_VENDOR_INTEL
,
897 .features
[FEAT_1_EDX
] =
904 .vendor
= CPUID_VENDOR_INTEL
,
908 .features
[FEAT_1_EDX
] =
915 .vendor
= CPUID_VENDOR_INTEL
,
919 .features
[FEAT_1_EDX
] =
926 .vendor
= CPUID_VENDOR_INTEL
,
930 .features
[FEAT_1_EDX
] =
937 .vendor
= CPUID_VENDOR_AMD
,
941 .features
[FEAT_1_EDX
] =
942 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
944 .features
[FEAT_8000_0001_EDX
] =
945 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
946 .xlevel
= 0x80000008,
947 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
952 .vendor
= CPUID_VENDOR_INTEL
,
956 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
957 .features
[FEAT_1_EDX
] =
959 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
|
960 CPUID_ACPI
| CPUID_SS
,
961 /* Some CPUs got no CPUID_SEP */
962 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
964 .features
[FEAT_1_ECX
] =
965 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
967 .features
[FEAT_8000_0001_EDX
] =
969 .features
[FEAT_8000_0001_ECX
] =
971 .xlevel
= 0x80000008,
972 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
977 .vendor
= CPUID_VENDOR_INTEL
,
981 .features
[FEAT_1_EDX
] =
982 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
983 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
984 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
985 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
986 CPUID_DE
| CPUID_FP87
,
987 .features
[FEAT_1_ECX
] =
988 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
989 .features
[FEAT_8000_0001_EDX
] =
990 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
991 .features
[FEAT_8000_0001_ECX
] =
993 .xlevel
= 0x80000008,
994 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
999 .vendor
= CPUID_VENDOR_INTEL
,
1003 .features
[FEAT_1_EDX
] =
1004 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1005 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1006 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1007 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1008 CPUID_DE
| CPUID_FP87
,
1009 .features
[FEAT_1_ECX
] =
1010 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1012 .features
[FEAT_8000_0001_EDX
] =
1013 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1014 .features
[FEAT_8000_0001_ECX
] =
1016 .xlevel
= 0x80000008,
1017 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1022 .vendor
= CPUID_VENDOR_INTEL
,
1026 .features
[FEAT_1_EDX
] =
1027 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1028 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1029 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1030 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1031 CPUID_DE
| CPUID_FP87
,
1032 .features
[FEAT_1_ECX
] =
1033 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1034 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1035 .features
[FEAT_8000_0001_EDX
] =
1036 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1037 .features
[FEAT_8000_0001_ECX
] =
1039 .xlevel
= 0x80000008,
1040 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
1045 .vendor
= CPUID_VENDOR_INTEL
,
1049 .features
[FEAT_1_EDX
] =
1050 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1051 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1052 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1053 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1054 CPUID_DE
| CPUID_FP87
,
1055 .features
[FEAT_1_ECX
] =
1056 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1057 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1058 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1059 .features
[FEAT_8000_0001_EDX
] =
1060 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1061 .features
[FEAT_8000_0001_ECX
] =
1063 .features
[FEAT_6_EAX
] =
1065 .xlevel
= 0x80000008,
1066 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1069 .name
= "SandyBridge",
1071 .vendor
= CPUID_VENDOR_INTEL
,
1075 .features
[FEAT_1_EDX
] =
1076 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1077 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1078 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1079 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1080 CPUID_DE
| CPUID_FP87
,
1081 .features
[FEAT_1_ECX
] =
1082 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1083 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1084 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1085 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1087 .features
[FEAT_8000_0001_EDX
] =
1088 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1090 .features
[FEAT_8000_0001_ECX
] =
1092 .features
[FEAT_XSAVE
] =
1093 CPUID_XSAVE_XSAVEOPT
,
1094 .features
[FEAT_6_EAX
] =
1096 .xlevel
= 0x80000008,
1097 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
1100 .name
= "IvyBridge",
1102 .vendor
= CPUID_VENDOR_INTEL
,
1106 .features
[FEAT_1_EDX
] =
1107 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1108 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1109 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1110 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1111 CPUID_DE
| CPUID_FP87
,
1112 .features
[FEAT_1_ECX
] =
1113 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1114 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1115 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1116 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1117 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1118 .features
[FEAT_7_0_EBX
] =
1119 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
1121 .features
[FEAT_8000_0001_EDX
] =
1122 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1124 .features
[FEAT_8000_0001_ECX
] =
1126 .features
[FEAT_XSAVE
] =
1127 CPUID_XSAVE_XSAVEOPT
,
1128 .features
[FEAT_6_EAX
] =
1130 .xlevel
= 0x80000008,
1131 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1134 .name
= "Haswell-noTSX",
1136 .vendor
= CPUID_VENDOR_INTEL
,
1140 .features
[FEAT_1_EDX
] =
1141 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1142 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1143 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1144 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1145 CPUID_DE
| CPUID_FP87
,
1146 .features
[FEAT_1_ECX
] =
1147 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1148 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1149 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1150 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1151 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1152 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1153 .features
[FEAT_8000_0001_EDX
] =
1154 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1156 .features
[FEAT_8000_0001_ECX
] =
1157 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1158 .features
[FEAT_7_0_EBX
] =
1159 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1160 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1161 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
,
1162 .features
[FEAT_XSAVE
] =
1163 CPUID_XSAVE_XSAVEOPT
,
1164 .features
[FEAT_6_EAX
] =
1166 .xlevel
= 0x80000008,
1167 .model_id
= "Intel Core Processor (Haswell, no TSX)",
1171 .vendor
= CPUID_VENDOR_INTEL
,
1175 .features
[FEAT_1_EDX
] =
1176 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1177 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1178 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1179 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1180 CPUID_DE
| CPUID_FP87
,
1181 .features
[FEAT_1_ECX
] =
1182 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1183 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1184 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1185 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1186 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1187 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1188 .features
[FEAT_8000_0001_EDX
] =
1189 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1191 .features
[FEAT_8000_0001_ECX
] =
1192 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1193 .features
[FEAT_7_0_EBX
] =
1194 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1195 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1196 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1198 .features
[FEAT_XSAVE
] =
1199 CPUID_XSAVE_XSAVEOPT
,
1200 .features
[FEAT_6_EAX
] =
1202 .xlevel
= 0x80000008,
1203 .model_id
= "Intel Core Processor (Haswell)",
1206 .name
= "Broadwell-noTSX",
1208 .vendor
= CPUID_VENDOR_INTEL
,
1212 .features
[FEAT_1_EDX
] =
1213 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1214 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1215 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1216 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1217 CPUID_DE
| CPUID_FP87
,
1218 .features
[FEAT_1_ECX
] =
1219 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1220 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1221 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1222 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1223 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1224 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1225 .features
[FEAT_8000_0001_EDX
] =
1226 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1228 .features
[FEAT_8000_0001_ECX
] =
1229 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1230 .features
[FEAT_7_0_EBX
] =
1231 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1232 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1233 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1234 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1236 .features
[FEAT_XSAVE
] =
1237 CPUID_XSAVE_XSAVEOPT
,
1238 .features
[FEAT_6_EAX
] =
1240 .xlevel
= 0x80000008,
1241 .model_id
= "Intel Core Processor (Broadwell, no TSX)",
1244 .name
= "Broadwell",
1246 .vendor
= CPUID_VENDOR_INTEL
,
1250 .features
[FEAT_1_EDX
] =
1251 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1252 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1253 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1254 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1255 CPUID_DE
| CPUID_FP87
,
1256 .features
[FEAT_1_ECX
] =
1257 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1258 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1259 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1260 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1261 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1262 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1263 .features
[FEAT_8000_0001_EDX
] =
1264 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1266 .features
[FEAT_8000_0001_ECX
] =
1267 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1268 .features
[FEAT_7_0_EBX
] =
1269 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1270 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1271 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1272 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1274 .features
[FEAT_XSAVE
] =
1275 CPUID_XSAVE_XSAVEOPT
,
1276 .features
[FEAT_6_EAX
] =
1278 .xlevel
= 0x80000008,
1279 .model_id
= "Intel Core Processor (Broadwell)",
1282 .name
= "Skylake-Client",
1284 .vendor
= CPUID_VENDOR_INTEL
,
1288 .features
[FEAT_1_EDX
] =
1289 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1290 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1291 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1292 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1293 CPUID_DE
| CPUID_FP87
,
1294 .features
[FEAT_1_ECX
] =
1295 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1296 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1297 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1298 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1299 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1300 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1301 .features
[FEAT_8000_0001_EDX
] =
1302 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1304 .features
[FEAT_8000_0001_ECX
] =
1305 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1306 .features
[FEAT_7_0_EBX
] =
1307 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1308 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1309 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1310 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1311 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
,
1312 /* Missing: XSAVES (not supported by some Linux versions,
1313 * including v4.1 to v4.6).
1314 * KVM doesn't yet expose any XSAVES state save component,
1315 * and the only one defined in Skylake (processor tracing)
1316 * probably will block migration anyway.
1318 .features
[FEAT_XSAVE
] =
1319 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1320 CPUID_XSAVE_XGETBV1
,
1321 .features
[FEAT_6_EAX
] =
1323 .xlevel
= 0x80000008,
1324 .model_id
= "Intel Core Processor (Skylake)",
1327 .name
= "Opteron_G1",
1329 .vendor
= CPUID_VENDOR_AMD
,
1333 .features
[FEAT_1_EDX
] =
1334 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1335 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1336 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1337 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1338 CPUID_DE
| CPUID_FP87
,
1339 .features
[FEAT_1_ECX
] =
1341 .features
[FEAT_8000_0001_EDX
] =
1342 CPUID_EXT2_LM
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1343 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1344 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1345 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1346 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1347 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1348 .xlevel
= 0x80000008,
1349 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
1352 .name
= "Opteron_G2",
1354 .vendor
= CPUID_VENDOR_AMD
,
1358 .features
[FEAT_1_EDX
] =
1359 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1360 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1361 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1362 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1363 CPUID_DE
| CPUID_FP87
,
1364 .features
[FEAT_1_ECX
] =
1365 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
1366 /* Missing: CPUID_EXT2_RDTSCP */
1367 .features
[FEAT_8000_0001_EDX
] =
1368 CPUID_EXT2_LM
| CPUID_EXT2_FXSR
|
1369 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
1370 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
1371 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
1372 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
1373 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
1374 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1375 .features
[FEAT_8000_0001_ECX
] =
1376 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1377 .xlevel
= 0x80000008,
1378 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
1381 .name
= "Opteron_G3",
1383 .vendor
= CPUID_VENDOR_AMD
,
1387 .features
[FEAT_1_EDX
] =
1388 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1389 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1390 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1391 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1392 CPUID_DE
| CPUID_FP87
,
1393 .features
[FEAT_1_ECX
] =
1394 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
1396 /* Missing: CPUID_EXT2_RDTSCP */
1397 .features
[FEAT_8000_0001_EDX
] =
1398 CPUID_EXT2_LM
| CPUID_EXT2_FXSR
|
1399 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
1400 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
1401 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
1402 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
1403 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
1404 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1405 .features
[FEAT_8000_0001_ECX
] =
1406 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
1407 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1408 .xlevel
= 0x80000008,
1409 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
1412 .name
= "Opteron_G4",
1414 .vendor
= CPUID_VENDOR_AMD
,
1418 .features
[FEAT_1_EDX
] =
1419 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1420 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1421 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1422 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1423 CPUID_DE
| CPUID_FP87
,
1424 .features
[FEAT_1_ECX
] =
1425 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1426 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1427 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1429 /* Missing: CPUID_EXT2_RDTSCP */
1430 .features
[FEAT_8000_0001_EDX
] =
1432 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1433 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1434 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1435 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1436 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1437 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1438 .features
[FEAT_8000_0001_ECX
] =
1439 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1440 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1441 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1444 .xlevel
= 0x8000001A,
1445 .model_id
= "AMD Opteron 62xx class CPU",
1448 .name
= "Opteron_G5",
1450 .vendor
= CPUID_VENDOR_AMD
,
1454 .features
[FEAT_1_EDX
] =
1455 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1456 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1457 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1458 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1459 CPUID_DE
| CPUID_FP87
,
1460 .features
[FEAT_1_ECX
] =
1461 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
1462 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1463 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
1464 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1465 /* Missing: CPUID_EXT2_RDTSCP */
1466 .features
[FEAT_8000_0001_EDX
] =
1468 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1469 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1470 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1471 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1472 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1473 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1474 .features
[FEAT_8000_0001_ECX
] =
1475 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1476 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1477 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1480 .xlevel
= 0x8000001A,
1481 .model_id
= "AMD Opteron 63xx class CPU",
1485 typedef struct PropValue
{
1486 const char *prop
, *value
;
1489 /* KVM-specific features that are automatically added/removed
1490 * from all CPU models when KVM is enabled.
1492 static PropValue kvm_default_props
[] = {
1493 { "kvmclock", "on" },
1494 { "kvm-nopiodelay", "on" },
1495 { "kvm-asyncpf", "on" },
1496 { "kvm-steal-time", "on" },
1497 { "kvm-pv-eoi", "on" },
1498 { "kvmclock-stable-bit", "on" },
1501 { "monitor", "off" },
1506 /* TCG-specific defaults that override all CPU models when using TCG
1508 static PropValue tcg_default_props
[] = {
1514 void x86_cpu_change_kvm_default(const char *prop
, const char *value
)
1517 for (pv
= kvm_default_props
; pv
->prop
; pv
++) {
1518 if (!strcmp(pv
->prop
, prop
)) {
1524 /* It is valid to call this function only for properties that
1525 * are already present in the kvm_default_props table.
1530 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
1531 bool migratable_only
);
1535 static bool lmce_supported(void)
1539 if (kvm_ioctl(kvm_state
, KVM_X86_GET_MCE_CAP_SUPPORTED
, &mce_cap
) < 0) {
1543 return !!(mce_cap
& MCG_LMCE_P
);
1546 static int cpu_x86_fill_model_id(char *str
)
1548 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1551 for (i
= 0; i
< 3; i
++) {
1552 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
1553 memcpy(str
+ i
* 16 + 0, &eax
, 4);
1554 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
1555 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
1556 memcpy(str
+ i
* 16 + 12, &edx
, 4);
1561 static X86CPUDefinition host_cpudef
;
1563 static Property host_x86_cpu_properties
[] = {
1564 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
1565 DEFINE_PROP_BOOL("host-cache-info", X86CPU
, cache_info_passthrough
, false),
1566 DEFINE_PROP_END_OF_LIST()
1569 /* class_init for the "host" CPU model
1571 * This function may be called before KVM is initialized.
1573 static void host_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
1575 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1576 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1577 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1579 xcc
->kvm_required
= true;
1581 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
1582 x86_cpu_vendor_words2str(host_cpudef
.vendor
, ebx
, edx
, ecx
);
1584 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
1585 host_cpudef
.family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
1586 host_cpudef
.model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
1587 host_cpudef
.stepping
= eax
& 0x0F;
1589 cpu_x86_fill_model_id(host_cpudef
.model_id
);
1591 xcc
->cpu_def
= &host_cpudef
;
1592 xcc
->model_description
=
1593 "KVM processor with all supported host features "
1594 "(only available in KVM mode)";
1596 /* level, xlevel, xlevel2, and the feature words are initialized on
1597 * instance_init, because they require KVM to be initialized.
1600 dc
->props
= host_x86_cpu_properties
;
1601 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1602 dc
->cannot_destroy_with_object_finalize_yet
= true;
1605 static void host_x86_cpu_initfn(Object
*obj
)
1607 X86CPU
*cpu
= X86_CPU(obj
);
1608 CPUX86State
*env
= &cpu
->env
;
1609 KVMState
*s
= kvm_state
;
1611 /* We can't fill the features array here because we don't know yet if
1612 * "migratable" is true or false.
1614 cpu
->host_features
= true;
1616 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
1617 if (kvm_enabled()) {
1618 env
->cpuid_min_level
=
1619 kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
1620 env
->cpuid_min_xlevel
=
1621 kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
1622 env
->cpuid_min_xlevel2
=
1623 kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
1625 if (lmce_supported()) {
1626 object_property_set_bool(OBJECT(cpu
), true, "lmce", &error_abort
);
1630 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
1633 static const TypeInfo host_x86_cpu_type_info
= {
1634 .name
= X86_CPU_TYPE_NAME("host"),
1635 .parent
= TYPE_X86_CPU
,
1636 .instance_init
= host_x86_cpu_initfn
,
1637 .class_init
= host_x86_cpu_class_init
,
1642 static void report_unavailable_features(FeatureWord w
, uint32_t mask
)
1644 FeatureWordInfo
*f
= &feature_word_info
[w
];
1647 for (i
= 0; i
< 32; ++i
) {
1648 if ((1UL << i
) & mask
) {
1649 const char *reg
= get_register_name_32(f
->cpuid_reg
);
1651 fprintf(stderr
, "warning: %s doesn't support requested feature: "
1652 "CPUID.%02XH:%s%s%s [bit %d]\n",
1653 kvm_enabled() ? "host" : "TCG",
1655 f
->feat_names
[i
] ? "." : "",
1656 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
1661 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
,
1662 const char *name
, void *opaque
,
1665 X86CPU
*cpu
= X86_CPU(obj
);
1666 CPUX86State
*env
= &cpu
->env
;
1669 value
= (env
->cpuid_version
>> 8) & 0xf;
1671 value
+= (env
->cpuid_version
>> 20) & 0xff;
1673 visit_type_int(v
, name
, &value
, errp
);
1676 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
,
1677 const char *name
, void *opaque
,
1680 X86CPU
*cpu
= X86_CPU(obj
);
1681 CPUX86State
*env
= &cpu
->env
;
1682 const int64_t min
= 0;
1683 const int64_t max
= 0xff + 0xf;
1684 Error
*local_err
= NULL
;
1687 visit_type_int(v
, name
, &value
, &local_err
);
1689 error_propagate(errp
, local_err
);
1692 if (value
< min
|| value
> max
) {
1693 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1694 name
? name
: "null", value
, min
, max
);
1698 env
->cpuid_version
&= ~0xff00f00;
1700 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
1702 env
->cpuid_version
|= value
<< 8;
1706 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
,
1707 const char *name
, void *opaque
,
1710 X86CPU
*cpu
= X86_CPU(obj
);
1711 CPUX86State
*env
= &cpu
->env
;
1714 value
= (env
->cpuid_version
>> 4) & 0xf;
1715 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
1716 visit_type_int(v
, name
, &value
, errp
);
1719 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
,
1720 const char *name
, void *opaque
,
1723 X86CPU
*cpu
= X86_CPU(obj
);
1724 CPUX86State
*env
= &cpu
->env
;
1725 const int64_t min
= 0;
1726 const int64_t max
= 0xff;
1727 Error
*local_err
= NULL
;
1730 visit_type_int(v
, name
, &value
, &local_err
);
1732 error_propagate(errp
, local_err
);
1735 if (value
< min
|| value
> max
) {
1736 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1737 name
? name
: "null", value
, min
, max
);
1741 env
->cpuid_version
&= ~0xf00f0;
1742 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
1745 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
1746 const char *name
, void *opaque
,
1749 X86CPU
*cpu
= X86_CPU(obj
);
1750 CPUX86State
*env
= &cpu
->env
;
1753 value
= env
->cpuid_version
& 0xf;
1754 visit_type_int(v
, name
, &value
, errp
);
1757 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
1758 const char *name
, void *opaque
,
1761 X86CPU
*cpu
= X86_CPU(obj
);
1762 CPUX86State
*env
= &cpu
->env
;
1763 const int64_t min
= 0;
1764 const int64_t max
= 0xf;
1765 Error
*local_err
= NULL
;
1768 visit_type_int(v
, name
, &value
, &local_err
);
1770 error_propagate(errp
, local_err
);
1773 if (value
< min
|| value
> max
) {
1774 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1775 name
? name
: "null", value
, min
, max
);
1779 env
->cpuid_version
&= ~0xf;
1780 env
->cpuid_version
|= value
& 0xf;
1783 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
1785 X86CPU
*cpu
= X86_CPU(obj
);
1786 CPUX86State
*env
= &cpu
->env
;
1789 value
= g_malloc(CPUID_VENDOR_SZ
+ 1);
1790 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
1791 env
->cpuid_vendor3
);
1795 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
1798 X86CPU
*cpu
= X86_CPU(obj
);
1799 CPUX86State
*env
= &cpu
->env
;
1802 if (strlen(value
) != CPUID_VENDOR_SZ
) {
1803 error_setg(errp
, QERR_PROPERTY_VALUE_BAD
, "", "vendor", value
);
1807 env
->cpuid_vendor1
= 0;
1808 env
->cpuid_vendor2
= 0;
1809 env
->cpuid_vendor3
= 0;
1810 for (i
= 0; i
< 4; i
++) {
1811 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1812 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1813 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1817 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1819 X86CPU
*cpu
= X86_CPU(obj
);
1820 CPUX86State
*env
= &cpu
->env
;
1824 value
= g_malloc(48 + 1);
1825 for (i
= 0; i
< 48; i
++) {
1826 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1832 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1835 X86CPU
*cpu
= X86_CPU(obj
);
1836 CPUX86State
*env
= &cpu
->env
;
1839 if (model_id
== NULL
) {
1842 len
= strlen(model_id
);
1843 memset(env
->cpuid_model
, 0, 48);
1844 for (i
= 0; i
< 48; i
++) {
1848 c
= (uint8_t)model_id
[i
];
1850 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1854 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
1855 void *opaque
, Error
**errp
)
1857 X86CPU
*cpu
= X86_CPU(obj
);
1860 value
= cpu
->env
.tsc_khz
* 1000;
1861 visit_type_int(v
, name
, &value
, errp
);
1864 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
1865 void *opaque
, Error
**errp
)
1867 X86CPU
*cpu
= X86_CPU(obj
);
1868 const int64_t min
= 0;
1869 const int64_t max
= INT64_MAX
;
1870 Error
*local_err
= NULL
;
1873 visit_type_int(v
, name
, &value
, &local_err
);
1875 error_propagate(errp
, local_err
);
1878 if (value
< min
|| value
> max
) {
1879 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1880 name
? name
: "null", value
, min
, max
);
1884 cpu
->env
.tsc_khz
= cpu
->env
.user_tsc_khz
= value
/ 1000;
1887 /* Generic getter for "feature-words" and "filtered-features" properties */
1888 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
,
1889 const char *name
, void *opaque
,
1892 uint32_t *array
= (uint32_t *)opaque
;
1894 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
1895 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
1896 X86CPUFeatureWordInfoList
*list
= NULL
;
1898 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1899 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1900 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
1901 qwi
->cpuid_input_eax
= wi
->cpuid_eax
;
1902 qwi
->has_cpuid_input_ecx
= wi
->cpuid_needs_ecx
;
1903 qwi
->cpuid_input_ecx
= wi
->cpuid_ecx
;
1904 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid_reg
].qapi_enum
;
1905 qwi
->features
= array
[w
];
1907 /* List will be in reverse order, but order shouldn't matter */
1908 list_entries
[w
].next
= list
;
1909 list_entries
[w
].value
= &word_infos
[w
];
1910 list
= &list_entries
[w
];
1913 visit_type_X86CPUFeatureWordInfoList(v
, "feature-words", &list
, errp
);
1916 static void x86_get_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
1917 void *opaque
, Error
**errp
)
1919 X86CPU
*cpu
= X86_CPU(obj
);
1920 int64_t value
= cpu
->hyperv_spinlock_attempts
;
1922 visit_type_int(v
, name
, &value
, errp
);
1925 static void x86_set_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
1926 void *opaque
, Error
**errp
)
1928 const int64_t min
= 0xFFF;
1929 const int64_t max
= UINT_MAX
;
1930 X86CPU
*cpu
= X86_CPU(obj
);
1934 visit_type_int(v
, name
, &value
, &err
);
1936 error_propagate(errp
, err
);
1940 if (value
< min
|| value
> max
) {
1941 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
1942 " (minimum: %" PRId64
", maximum: %" PRId64
")",
1943 object_get_typename(obj
), name
? name
: "null",
1947 cpu
->hyperv_spinlock_attempts
= value
;
1950 static PropertyInfo qdev_prop_spinlocks
= {
1952 .get
= x86_get_hv_spinlocks
,
1953 .set
= x86_set_hv_spinlocks
,
1956 /* Convert all '_' in a feature string option name to '-', to make feature
1957 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1959 static inline void feat2prop(char *s
)
1961 while ((s
= strchr(s
, '_'))) {
1966 /* Return the feature property name for a feature flag bit */
1967 static const char *x86_cpu_feature_name(FeatureWord w
, int bitnr
)
1969 /* XSAVE components are automatically enabled by other features,
1970 * so return the original feature name instead
1972 if (w
== FEAT_XSAVE_COMP_LO
|| w
== FEAT_XSAVE_COMP_HI
) {
1973 int comp
= (w
== FEAT_XSAVE_COMP_HI
) ? bitnr
+ 32 : bitnr
;
1975 if (comp
< ARRAY_SIZE(x86_ext_save_areas
) &&
1976 x86_ext_save_areas
[comp
].bits
) {
1977 w
= x86_ext_save_areas
[comp
].feature
;
1978 bitnr
= ctz32(x86_ext_save_areas
[comp
].bits
);
1983 assert(w
< FEATURE_WORDS
);
1984 return feature_word_info
[w
].feat_names
[bitnr
];
1987 /* Compatibily hack to maintain legacy +-feat semantic,
1988 * where +-feat overwrites any feature set by
1989 * feat=on|feat even if the later is parsed after +-feat
1990 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
1992 static GList
*plus_features
, *minus_features
;
1994 static gint
compare_string(gconstpointer a
, gconstpointer b
)
1996 return g_strcmp0(a
, b
);
1999 /* Parse "+feature,-feature,feature=foo" CPU feature string
2001 static void x86_cpu_parse_featurestr(const char *typename
, char *features
,
2004 char *featurestr
; /* Single 'key=value" string being parsed */
2005 static bool cpu_globals_initialized
;
2006 bool ambiguous
= false;
2008 if (cpu_globals_initialized
) {
2011 cpu_globals_initialized
= true;
2017 for (featurestr
= strtok(features
, ",");
2019 featurestr
= strtok(NULL
, ",")) {
2021 const char *val
= NULL
;
2024 GlobalProperty
*prop
;
2026 /* Compatibility syntax: */
2027 if (featurestr
[0] == '+') {
2028 plus_features
= g_list_append(plus_features
,
2029 g_strdup(featurestr
+ 1));
2031 } else if (featurestr
[0] == '-') {
2032 minus_features
= g_list_append(minus_features
,
2033 g_strdup(featurestr
+ 1));
2037 eq
= strchr(featurestr
, '=');
2045 feat2prop(featurestr
);
2048 if (g_list_find_custom(plus_features
, name
, compare_string
)) {
2049 error_report("warning: Ambiguous CPU model string. "
2050 "Don't mix both \"+%s\" and \"%s=%s\"",
2054 if (g_list_find_custom(minus_features
, name
, compare_string
)) {
2055 error_report("warning: Ambiguous CPU model string. "
2056 "Don't mix both \"-%s\" and \"%s=%s\"",
2062 if (!strcmp(name
, "tsc-freq")) {
2066 tsc_freq
= qemu_strtosz_suffix_unit(val
, &err
,
2067 QEMU_STRTOSZ_DEFSUFFIX_B
, 1000);
2068 if (tsc_freq
< 0 || *err
) {
2069 error_setg(errp
, "bad numerical value %s", val
);
2072 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
2074 name
= "tsc-frequency";
2077 prop
= g_new0(typeof(*prop
), 1);
2078 prop
->driver
= typename
;
2079 prop
->property
= g_strdup(name
);
2080 prop
->value
= g_strdup(val
);
2081 prop
->errp
= &error_fatal
;
2082 qdev_prop_register_global(prop
);
2086 error_report("warning: Compatibility of ambiguous CPU model "
2087 "strings won't be kept on future QEMU versions");
2091 static void x86_cpu_load_features(X86CPU
*cpu
, Error
**errp
);
2092 static int x86_cpu_filter_features(X86CPU
*cpu
);
2094 /* Check for missing features that may prevent the CPU class from
2095 * running using the current machine and accelerator.
2097 static void x86_cpu_class_check_missing_features(X86CPUClass
*xcc
,
2098 strList
**missing_feats
)
2103 strList
**next
= missing_feats
;
2105 if (xcc
->kvm_required
&& !kvm_enabled()) {
2106 strList
*new = g_new0(strList
, 1);
2107 new->value
= g_strdup("kvm");;
2108 *missing_feats
= new;
2112 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
2114 x86_cpu_load_features(xc
, &err
);
2116 /* Errors at x86_cpu_load_features should never happen,
2117 * but in case it does, just report the model as not
2118 * runnable at all using the "type" property.
2120 strList
*new = g_new0(strList
, 1);
2121 new->value
= g_strdup("type");
2126 x86_cpu_filter_features(xc
);
2128 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2129 uint32_t filtered
= xc
->filtered_features
[w
];
2131 for (i
= 0; i
< 32; i
++) {
2132 if (filtered
& (1UL << i
)) {
2133 strList
*new = g_new0(strList
, 1);
2134 new->value
= g_strdup(x86_cpu_feature_name(w
, i
));
2141 object_unref(OBJECT(xc
));
2144 /* Print all cpuid feature names in featureset
2146 static void listflags(FILE *f
, fprintf_function print
, const char **featureset
)
2151 for (bit
= 0; bit
< 32; bit
++) {
2152 if (featureset
[bit
]) {
2153 print(f
, "%s%s", first
? "" : " ", featureset
[bit
]);
2159 /* Sort alphabetically by type name, listing kvm_required models last. */
2160 static gint
x86_cpu_list_compare(gconstpointer a
, gconstpointer b
)
2162 ObjectClass
*class_a
= (ObjectClass
*)a
;
2163 ObjectClass
*class_b
= (ObjectClass
*)b
;
2164 X86CPUClass
*cc_a
= X86_CPU_CLASS(class_a
);
2165 X86CPUClass
*cc_b
= X86_CPU_CLASS(class_b
);
2166 const char *name_a
, *name_b
;
2168 if (cc_a
->kvm_required
!= cc_b
->kvm_required
) {
2169 /* kvm_required items go last */
2170 return cc_a
->kvm_required
? 1 : -1;
2172 name_a
= object_class_get_name(class_a
);
2173 name_b
= object_class_get_name(class_b
);
2174 return strcmp(name_a
, name_b
);
2178 static GSList
*get_sorted_cpu_model_list(void)
2180 GSList
*list
= object_class_get_list(TYPE_X86_CPU
, false);
2181 list
= g_slist_sort(list
, x86_cpu_list_compare
);
2185 static void x86_cpu_list_entry(gpointer data
, gpointer user_data
)
2187 ObjectClass
*oc
= data
;
2188 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
2189 CPUListState
*s
= user_data
;
2190 char *name
= x86_cpu_class_get_model_name(cc
);
2191 const char *desc
= cc
->model_description
;
2193 desc
= cc
->cpu_def
->model_id
;
2196 (*s
->cpu_fprintf
)(s
->file
, "x86 %16s %-48s\n",
2201 /* list available CPU models and flags */
2202 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
2207 .cpu_fprintf
= cpu_fprintf
,
2211 (*cpu_fprintf
)(f
, "Available CPUs:\n");
2212 list
= get_sorted_cpu_model_list();
2213 g_slist_foreach(list
, x86_cpu_list_entry
, &s
);
2216 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
2217 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
2218 FeatureWordInfo
*fw
= &feature_word_info
[i
];
2220 (*cpu_fprintf
)(f
, " ");
2221 listflags(f
, cpu_fprintf
, fw
->feat_names
);
2222 (*cpu_fprintf
)(f
, "\n");
2226 static void x86_cpu_definition_entry(gpointer data
, gpointer user_data
)
2228 ObjectClass
*oc
= data
;
2229 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
2230 CpuDefinitionInfoList
**cpu_list
= user_data
;
2231 CpuDefinitionInfoList
*entry
;
2232 CpuDefinitionInfo
*info
;
2234 info
= g_malloc0(sizeof(*info
));
2235 info
->name
= x86_cpu_class_get_model_name(cc
);
2236 x86_cpu_class_check_missing_features(cc
, &info
->unavailable_features
);
2237 info
->has_unavailable_features
= true;
2238 info
->q_typename
= g_strdup(object_class_get_name(oc
));
2240 entry
= g_malloc0(sizeof(*entry
));
2241 entry
->value
= info
;
2242 entry
->next
= *cpu_list
;
2246 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
2248 CpuDefinitionInfoList
*cpu_list
= NULL
;
2249 GSList
*list
= get_sorted_cpu_model_list();
2250 g_slist_foreach(list
, x86_cpu_definition_entry
, &cpu_list
);
2255 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
2256 bool migratable_only
)
2258 FeatureWordInfo
*wi
= &feature_word_info
[w
];
2261 if (kvm_enabled()) {
2262 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid_eax
,
2265 } else if (tcg_enabled()) {
2266 r
= wi
->tcg_features
;
2270 if (migratable_only
) {
2271 r
&= x86_cpu_get_migratable_flags(w
);
2277 * Filters CPU feature words based on host availability of each feature.
2279 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2281 static int x86_cpu_filter_features(X86CPU
*cpu
)
2283 CPUX86State
*env
= &cpu
->env
;
2287 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2288 uint32_t host_feat
=
2289 x86_cpu_get_supported_feature_word(w
, false);
2290 uint32_t requested_features
= env
->features
[w
];
2291 env
->features
[w
] &= host_feat
;
2292 cpu
->filtered_features
[w
] = requested_features
& ~env
->features
[w
];
2293 if (cpu
->filtered_features
[w
]) {
2301 static void x86_cpu_report_filtered_features(X86CPU
*cpu
)
2305 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2306 report_unavailable_features(w
, cpu
->filtered_features
[w
]);
2310 static void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
)
2313 for (pv
= props
; pv
->prop
; pv
++) {
2317 object_property_parse(OBJECT(cpu
), pv
->value
, pv
->prop
,
2322 /* Load data from X86CPUDefinition
2324 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
)
2326 CPUX86State
*env
= &cpu
->env
;
2328 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
2331 /* CPU models only set _minimum_ values for level/xlevel: */
2332 object_property_set_int(OBJECT(cpu
), def
->level
, "min-level", errp
);
2333 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "min-xlevel", errp
);
2335 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
2336 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
2337 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
2338 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
2339 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2340 env
->features
[w
] = def
->features
[w
];
2343 /* Special cases not set in the X86CPUDefinition structs: */
2344 if (kvm_enabled()) {
2345 if (!kvm_irqchip_in_kernel()) {
2346 x86_cpu_change_kvm_default("x2apic", "off");
2349 x86_cpu_apply_props(cpu
, kvm_default_props
);
2350 } else if (tcg_enabled()) {
2351 x86_cpu_apply_props(cpu
, tcg_default_props
);
2354 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
2356 /* sysenter isn't supported in compatibility mode on AMD,
2357 * syscall isn't supported in compatibility mode on Intel.
2358 * Normally we advertise the actual CPU vendor, but you can
2359 * override this using the 'vendor' property if you want to use
2360 * KVM's sysenter/syscall emulation in compatibility mode and
2361 * when doing cross vendor migration
2363 vendor
= def
->vendor
;
2364 if (kvm_enabled()) {
2365 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
2366 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
2367 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
2368 vendor
= host_vendor
;
2371 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
2375 X86CPU
*cpu_x86_init(const char *cpu_model
)
2377 return X86_CPU(cpu_generic_init(TYPE_X86_CPU
, cpu_model
));
2380 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
2382 X86CPUDefinition
*cpudef
= data
;
2383 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2385 xcc
->cpu_def
= cpudef
;
2388 static void x86_register_cpudef_type(X86CPUDefinition
*def
)
2390 char *typename
= x86_cpu_type_name(def
->name
);
2393 .parent
= TYPE_X86_CPU
,
2394 .class_init
= x86_cpu_cpudef_class_init
,
2402 #if !defined(CONFIG_USER_ONLY)
2404 void cpu_clear_apic_feature(CPUX86State
*env
)
2406 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
2409 #endif /* !CONFIG_USER_ONLY */
2411 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
2412 uint32_t *eax
, uint32_t *ebx
,
2413 uint32_t *ecx
, uint32_t *edx
)
2415 X86CPU
*cpu
= x86_env_get_cpu(env
);
2416 CPUState
*cs
= CPU(cpu
);
2417 uint32_t pkg_offset
;
2419 /* test if maximum index reached */
2420 if (index
& 0x80000000) {
2421 if (index
> env
->cpuid_xlevel
) {
2422 if (env
->cpuid_xlevel2
> 0) {
2423 /* Handle the Centaur's CPUID instruction. */
2424 if (index
> env
->cpuid_xlevel2
) {
2425 index
= env
->cpuid_xlevel2
;
2426 } else if (index
< 0xC0000000) {
2427 index
= env
->cpuid_xlevel
;
2430 /* Intel documentation states that invalid EAX input will
2431 * return the same information as EAX=cpuid_level
2432 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2434 index
= env
->cpuid_level
;
2438 if (index
> env
->cpuid_level
)
2439 index
= env
->cpuid_level
;
2444 *eax
= env
->cpuid_level
;
2445 *ebx
= env
->cpuid_vendor1
;
2446 *edx
= env
->cpuid_vendor2
;
2447 *ecx
= env
->cpuid_vendor3
;
2450 *eax
= env
->cpuid_version
;
2451 *ebx
= (cpu
->apic_id
<< 24) |
2452 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2453 *ecx
= env
->features
[FEAT_1_ECX
];
2454 if ((*ecx
& CPUID_EXT_XSAVE
) && (env
->cr
[4] & CR4_OSXSAVE_MASK
)) {
2455 *ecx
|= CPUID_EXT_OSXSAVE
;
2457 *edx
= env
->features
[FEAT_1_EDX
];
2458 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2459 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
2464 /* cache info: needed for Pentium Pro compatibility */
2465 if (cpu
->cache_info_passthrough
) {
2466 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2469 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
2471 if (!cpu
->enable_l3_cache
) {
2474 *ecx
= L3_N_DESCRIPTOR
;
2476 *edx
= (L1D_DESCRIPTOR
<< 16) | \
2477 (L1I_DESCRIPTOR
<< 8) | \
2481 /* cache info: needed for Core compatibility */
2482 if (cpu
->cache_info_passthrough
) {
2483 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
2484 *eax
&= ~0xFC000000;
2488 case 0: /* L1 dcache info */
2489 *eax
|= CPUID_4_TYPE_DCACHE
| \
2490 CPUID_4_LEVEL(1) | \
2491 CPUID_4_SELF_INIT_LEVEL
;
2492 *ebx
= (L1D_LINE_SIZE
- 1) | \
2493 ((L1D_PARTITIONS
- 1) << 12) | \
2494 ((L1D_ASSOCIATIVITY
- 1) << 22);
2495 *ecx
= L1D_SETS
- 1;
2496 *edx
= CPUID_4_NO_INVD_SHARING
;
2498 case 1: /* L1 icache info */
2499 *eax
|= CPUID_4_TYPE_ICACHE
| \
2500 CPUID_4_LEVEL(1) | \
2501 CPUID_4_SELF_INIT_LEVEL
;
2502 *ebx
= (L1I_LINE_SIZE
- 1) | \
2503 ((L1I_PARTITIONS
- 1) << 12) | \
2504 ((L1I_ASSOCIATIVITY
- 1) << 22);
2505 *ecx
= L1I_SETS
- 1;
2506 *edx
= CPUID_4_NO_INVD_SHARING
;
2508 case 2: /* L2 cache info */
2509 *eax
|= CPUID_4_TYPE_UNIFIED
| \
2510 CPUID_4_LEVEL(2) | \
2511 CPUID_4_SELF_INIT_LEVEL
;
2512 if (cs
->nr_threads
> 1) {
2513 *eax
|= (cs
->nr_threads
- 1) << 14;
2515 *ebx
= (L2_LINE_SIZE
- 1) | \
2516 ((L2_PARTITIONS
- 1) << 12) | \
2517 ((L2_ASSOCIATIVITY
- 1) << 22);
2519 *edx
= CPUID_4_NO_INVD_SHARING
;
2521 case 3: /* L3 cache info */
2522 if (!cpu
->enable_l3_cache
) {
2529 *eax
|= CPUID_4_TYPE_UNIFIED
| \
2530 CPUID_4_LEVEL(3) | \
2531 CPUID_4_SELF_INIT_LEVEL
;
2532 pkg_offset
= apicid_pkg_offset(cs
->nr_cores
, cs
->nr_threads
);
2533 *eax
|= ((1 << pkg_offset
) - 1) << 14;
2534 *ebx
= (L3_N_LINE_SIZE
- 1) | \
2535 ((L3_N_PARTITIONS
- 1) << 12) | \
2536 ((L3_N_ASSOCIATIVITY
- 1) << 22);
2537 *ecx
= L3_N_SETS
- 1;
2538 *edx
= CPUID_4_INCLUSIVE
| CPUID_4_COMPLEX_IDX
;
2540 default: /* end of info */
2549 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2550 if ((*eax
& 31) && cs
->nr_cores
> 1) {
2551 *eax
|= (cs
->nr_cores
- 1) << 26;
2555 /* mwait info: needed for Core compatibility */
2556 *eax
= 0; /* Smallest monitor-line size in bytes */
2557 *ebx
= 0; /* Largest monitor-line size in bytes */
2558 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
2562 /* Thermal and Power Leaf */
2563 *eax
= env
->features
[FEAT_6_EAX
];
2569 /* Structured Extended Feature Flags Enumeration Leaf */
2571 *eax
= 0; /* Maximum ECX value for sub-leaves */
2572 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
2573 *ecx
= env
->features
[FEAT_7_0_ECX
]; /* Feature flags */
2574 if ((*ecx
& CPUID_7_0_ECX_PKU
) && env
->cr
[4] & CR4_PKE_MASK
) {
2575 *ecx
|= CPUID_7_0_ECX_OSPKE
;
2577 *edx
= env
->features
[FEAT_7_0_EDX
]; /* Feature flags */
2586 /* Direct Cache Access Information Leaf */
2587 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
2593 /* Architectural Performance Monitoring Leaf */
2594 if (kvm_enabled() && cpu
->enable_pmu
) {
2595 KVMState
*s
= cs
->kvm_state
;
2597 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
2598 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
2599 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
2600 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
2609 /* Extended Topology Enumeration Leaf */
2610 if (!cpu
->enable_cpuid_0xb
) {
2611 *eax
= *ebx
= *ecx
= *edx
= 0;
2615 *ecx
= count
& 0xff;
2616 *edx
= cpu
->apic_id
;
2620 *eax
= apicid_core_offset(cs
->nr_cores
, cs
->nr_threads
);
2621 *ebx
= cs
->nr_threads
;
2622 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
2625 *eax
= apicid_pkg_offset(cs
->nr_cores
, cs
->nr_threads
);
2626 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
2627 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
2632 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
2635 assert(!(*eax
& ~0x1f));
2636 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
2639 /* Processor Extended State */
2644 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
2649 *ecx
= xsave_area_size(x86_cpu_xsave_components(cpu
));
2650 *eax
= env
->features
[FEAT_XSAVE_COMP_LO
];
2651 *edx
= env
->features
[FEAT_XSAVE_COMP_HI
];
2653 } else if (count
== 1) {
2654 *eax
= env
->features
[FEAT_XSAVE
];
2655 } else if (count
< ARRAY_SIZE(x86_ext_save_areas
)) {
2656 if ((x86_cpu_xsave_components(cpu
) >> count
) & 1) {
2657 const ExtSaveArea
*esa
= &x86_ext_save_areas
[count
];
2665 *eax
= env
->cpuid_xlevel
;
2666 *ebx
= env
->cpuid_vendor1
;
2667 *edx
= env
->cpuid_vendor2
;
2668 *ecx
= env
->cpuid_vendor3
;
2671 *eax
= env
->cpuid_version
;
2673 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
2674 *edx
= env
->features
[FEAT_8000_0001_EDX
];
2676 /* The Linux kernel checks for the CMPLegacy bit and
2677 * discards multiple thread information if it is set.
2678 * So don't set it here for Intel to make Linux guests happy.
2680 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2681 if (env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
||
2682 env
->cpuid_vendor2
!= CPUID_VENDOR_INTEL_2
||
2683 env
->cpuid_vendor3
!= CPUID_VENDOR_INTEL_3
) {
2684 *ecx
|= 1 << 1; /* CmpLegacy bit */
2691 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
2692 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
2693 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
2694 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
2697 /* cache info (L1 cache) */
2698 if (cpu
->cache_info_passthrough
) {
2699 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2702 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
2703 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
2704 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
2705 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
2706 *ecx
= (L1D_SIZE_KB_AMD
<< 24) | (L1D_ASSOCIATIVITY_AMD
<< 16) | \
2707 (L1D_LINES_PER_TAG
<< 8) | (L1D_LINE_SIZE
);
2708 *edx
= (L1I_SIZE_KB_AMD
<< 24) | (L1I_ASSOCIATIVITY_AMD
<< 16) | \
2709 (L1I_LINES_PER_TAG
<< 8) | (L1I_LINE_SIZE
);
2712 /* cache info (L2 cache) */
2713 if (cpu
->cache_info_passthrough
) {
2714 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2717 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
2718 (L2_DTLB_2M_ENTRIES
<< 16) | \
2719 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
2720 (L2_ITLB_2M_ENTRIES
);
2721 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
2722 (L2_DTLB_4K_ENTRIES
<< 16) | \
2723 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
2724 (L2_ITLB_4K_ENTRIES
);
2725 *ecx
= (L2_SIZE_KB_AMD
<< 16) | \
2726 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY
) << 12) | \
2727 (L2_LINES_PER_TAG
<< 8) | (L2_LINE_SIZE
);
2728 if (!cpu
->enable_l3_cache
) {
2729 *edx
= ((L3_SIZE_KB
/ 512) << 18) | \
2730 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY
) << 12) | \
2731 (L3_LINES_PER_TAG
<< 8) | (L3_LINE_SIZE
);
2733 *edx
= ((L3_N_SIZE_KB_AMD
/ 512) << 18) | \
2734 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY
) << 12) | \
2735 (L3_N_LINES_PER_TAG
<< 8) | (L3_N_LINE_SIZE
);
2742 *edx
= env
->features
[FEAT_8000_0007_EDX
];
2745 /* virtual & phys address size in low 2 bytes. */
2746 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
2747 /* 64 bit processor */
2748 *eax
= cpu
->phys_bits
; /* configurable physical bits */
2749 if (env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
) {
2750 *eax
|= 0x00003900; /* 57 bits virtual */
2752 *eax
|= 0x00003000; /* 48 bits virtual */
2755 *eax
= cpu
->phys_bits
;
2760 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2761 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
2765 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
2766 *eax
= 0x00000001; /* SVM Revision */
2767 *ebx
= 0x00000010; /* nr of ASIDs */
2769 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
2778 *eax
= env
->cpuid_xlevel2
;
2784 /* Support for VIA CPU's CPUID instruction */
2785 *eax
= env
->cpuid_version
;
2788 *edx
= env
->features
[FEAT_C000_0001_EDX
];
2793 /* Reserved for the future, and now filled with zero */
2800 /* reserved values: zero */
2809 /* CPUClass::reset() */
2810 static void x86_cpu_reset(CPUState
*s
)
2812 X86CPU
*cpu
= X86_CPU(s
);
2813 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
2814 CPUX86State
*env
= &cpu
->env
;
2819 xcc
->parent_reset(s
);
2821 memset(env
, 0, offsetof(CPUX86State
, end_reset_fields
));
2825 env
->old_exception
= -1;
2827 /* init to reset state */
2829 env
->hflags2
|= HF2_GIF_MASK
;
2831 cpu_x86_update_cr0(env
, 0x60000010);
2832 env
->a20_mask
= ~0x0;
2833 env
->smbase
= 0x30000;
2835 env
->idt
.limit
= 0xffff;
2836 env
->gdt
.limit
= 0xffff;
2837 env
->ldt
.limit
= 0xffff;
2838 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
2839 env
->tr
.limit
= 0xffff;
2840 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
2842 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
2843 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
2844 DESC_R_MASK
| DESC_A_MASK
);
2845 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
2846 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2848 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
2849 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2851 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
2852 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2854 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
2855 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2857 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
2858 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2862 env
->regs
[R_EDX
] = env
->cpuid_version
;
2867 for (i
= 0; i
< 8; i
++) {
2870 cpu_set_fpuc(env
, 0x37f);
2872 env
->mxcsr
= 0x1f80;
2873 /* All units are in INIT state. */
2876 env
->pat
= 0x0007040600070406ULL
;
2877 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
2879 memset(env
->dr
, 0, sizeof(env
->dr
));
2880 env
->dr
[6] = DR6_FIXED_1
;
2881 env
->dr
[7] = DR7_FIXED_1
;
2882 cpu_breakpoint_remove_all(s
, BP_CPU
);
2883 cpu_watchpoint_remove_all(s
, BP_CPU
);
2886 xcr0
= XSTATE_FP_MASK
;
2888 #ifdef CONFIG_USER_ONLY
2889 /* Enable all the features for user-mode. */
2890 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
2891 xcr0
|= XSTATE_SSE_MASK
;
2893 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
2894 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
2895 if (env
->features
[esa
->feature
] & esa
->bits
) {
2900 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) {
2901 cr4
|= CR4_OSFXSR_MASK
| CR4_OSXSAVE_MASK
;
2903 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
) {
2904 cr4
|= CR4_FSGSBASE_MASK
;
2909 cpu_x86_update_cr4(env
, cr4
);
2912 * SDM 11.11.5 requires:
2913 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2914 * - IA32_MTRR_PHYSMASKn.V = 0
2915 * All other bits are undefined. For simplification, zero it all.
2917 env
->mtrr_deftype
= 0;
2918 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
2919 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
2921 #if !defined(CONFIG_USER_ONLY)
2922 /* We hard-wire the BSP to the first CPU. */
2923 apic_designate_bsp(cpu
->apic_state
, s
->cpu_index
== 0);
2925 s
->halted
= !cpu_is_bsp(cpu
);
2927 if (kvm_enabled()) {
2928 kvm_arch_reset_vcpu(cpu
);
2933 #ifndef CONFIG_USER_ONLY
2934 bool cpu_is_bsp(X86CPU
*cpu
)
2936 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
2939 /* TODO: remove me, when reset over QOM tree is implemented */
2940 static void x86_cpu_machine_reset_cb(void *opaque
)
2942 X86CPU
*cpu
= opaque
;
2943 cpu_reset(CPU(cpu
));
2947 static void mce_init(X86CPU
*cpu
)
2949 CPUX86State
*cenv
= &cpu
->env
;
2952 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
2953 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
2954 (CPUID_MCE
| CPUID_MCA
)) {
2955 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
|
2956 (cpu
->enable_lmce
? MCG_LMCE_P
: 0);
2957 cenv
->mcg_ctl
= ~(uint64_t)0;
2958 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
2959 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
2964 #ifndef CONFIG_USER_ONLY
2965 APICCommonClass
*apic_get_class(void)
2967 const char *apic_type
= "apic";
2969 if (kvm_apic_in_kernel()) {
2970 apic_type
= "kvm-apic";
2971 } else if (xen_enabled()) {
2972 apic_type
= "xen-apic";
2975 return APIC_COMMON_CLASS(object_class_by_name(apic_type
));
2978 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
2980 APICCommonState
*apic
;
2981 ObjectClass
*apic_class
= OBJECT_CLASS(apic_get_class());
2983 cpu
->apic_state
= DEVICE(object_new(object_class_get_name(apic_class
)));
2985 object_property_add_child(OBJECT(cpu
), "lapic",
2986 OBJECT(cpu
->apic_state
), &error_abort
);
2987 object_unref(OBJECT(cpu
->apic_state
));
2989 qdev_prop_set_uint32(cpu
->apic_state
, "id", cpu
->apic_id
);
2990 /* TODO: convert to link<> */
2991 apic
= APIC_COMMON(cpu
->apic_state
);
2993 apic
->apicbase
= APIC_DEFAULT_ADDRESS
| MSR_IA32_APICBASE_ENABLE
;
2996 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2998 APICCommonState
*apic
;
2999 static bool apic_mmio_map_once
;
3001 if (cpu
->apic_state
== NULL
) {
3004 object_property_set_bool(OBJECT(cpu
->apic_state
), true, "realized",
3007 /* Map APIC MMIO area */
3008 apic
= APIC_COMMON(cpu
->apic_state
);
3009 if (!apic_mmio_map_once
) {
3010 memory_region_add_subregion_overlap(get_system_memory(),
3012 MSR_IA32_APICBASE_BASE
,
3015 apic_mmio_map_once
= true;
3019 static void x86_cpu_machine_done(Notifier
*n
, void *unused
)
3021 X86CPU
*cpu
= container_of(n
, X86CPU
, machine_done
);
3022 MemoryRegion
*smram
=
3023 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
3026 cpu
->smram
= g_new(MemoryRegion
, 1);
3027 memory_region_init_alias(cpu
->smram
, OBJECT(cpu
), "smram",
3028 smram
, 0, 1ull << 32);
3029 memory_region_set_enabled(cpu
->smram
, false);
3030 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->smram
, 1);
3034 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
3039 /* Note: Only safe for use on x86(-64) hosts */
3040 static uint32_t x86_host_phys_bits(void)
3043 uint32_t host_phys_bits
;
3045 host_cpuid(0x80000000, 0, &eax
, NULL
, NULL
, NULL
);
3046 if (eax
>= 0x80000008) {
3047 host_cpuid(0x80000008, 0, &eax
, NULL
, NULL
, NULL
);
3048 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3049 * at 23:16 that can specify a maximum physical address bits for
3050 * the guest that can override this value; but I've not seen
3051 * anything with that set.
3053 host_phys_bits
= eax
& 0xff;
3055 /* It's an odd 64 bit machine that doesn't have the leaf for
3056 * physical address bits; fall back to 36 that's most older
3059 host_phys_bits
= 36;
3062 return host_phys_bits
;
3065 static void x86_cpu_adjust_level(X86CPU
*cpu
, uint32_t *min
, uint32_t value
)
3072 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3073 static void x86_cpu_adjust_feat_level(X86CPU
*cpu
, FeatureWord w
)
3075 CPUX86State
*env
= &cpu
->env
;
3076 FeatureWordInfo
*fi
= &feature_word_info
[w
];
3077 uint32_t eax
= fi
->cpuid_eax
;
3078 uint32_t region
= eax
& 0xF0000000;
3080 if (!env
->features
[w
]) {
3086 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, eax
);
3089 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, eax
);
3092 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel2
, eax
);
3097 /* Calculate XSAVE components based on the configured CPU feature flags */
3098 static void x86_cpu_enable_xsave_components(X86CPU
*cpu
)
3100 CPUX86State
*env
= &cpu
->env
;
3104 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
3109 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
3110 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
3111 if (env
->features
[esa
->feature
] & esa
->bits
) {
3112 mask
|= (1ULL << i
);
3116 env
->features
[FEAT_XSAVE_COMP_LO
] = mask
;
3117 env
->features
[FEAT_XSAVE_COMP_HI
] = mask
>> 32;
3120 /* Load CPUID data based on configured features */
3121 static void x86_cpu_load_features(X86CPU
*cpu
, Error
**errp
)
3123 CPUX86State
*env
= &cpu
->env
;
3126 Error
*local_err
= NULL
;
3128 /*TODO: cpu->host_features incorrectly overwrites features
3129 * set using "feat=on|off". Once we fix this, we can convert
3130 * plus_features & minus_features to global properties
3131 * inside x86_cpu_parse_featurestr() too.
3133 if (cpu
->host_features
) {
3134 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3136 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
);
3140 for (l
= plus_features
; l
; l
= l
->next
) {
3141 const char *prop
= l
->data
;
3142 object_property_set_bool(OBJECT(cpu
), true, prop
, &local_err
);
3148 for (l
= minus_features
; l
; l
= l
->next
) {
3149 const char *prop
= l
->data
;
3150 object_property_set_bool(OBJECT(cpu
), false, prop
, &local_err
);
3156 if (!kvm_enabled() || !cpu
->expose_kvm
) {
3157 env
->features
[FEAT_KVM
] = 0;
3160 x86_cpu_enable_xsave_components(cpu
);
3162 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3163 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_EBX
);
3164 if (cpu
->full_cpuid_auto_level
) {
3165 x86_cpu_adjust_feat_level(cpu
, FEAT_1_EDX
);
3166 x86_cpu_adjust_feat_level(cpu
, FEAT_1_ECX
);
3167 x86_cpu_adjust_feat_level(cpu
, FEAT_6_EAX
);
3168 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_ECX
);
3169 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_EDX
);
3170 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_ECX
);
3171 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0007_EDX
);
3172 x86_cpu_adjust_feat_level(cpu
, FEAT_C000_0001_EDX
);
3173 x86_cpu_adjust_feat_level(cpu
, FEAT_SVM
);
3174 x86_cpu_adjust_feat_level(cpu
, FEAT_XSAVE
);
3175 /* SVM requires CPUID[0x8000000A] */
3176 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
3177 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000000A);
3181 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3182 if (env
->cpuid_level
== UINT32_MAX
) {
3183 env
->cpuid_level
= env
->cpuid_min_level
;
3185 if (env
->cpuid_xlevel
== UINT32_MAX
) {
3186 env
->cpuid_xlevel
= env
->cpuid_min_xlevel
;
3188 if (env
->cpuid_xlevel2
== UINT32_MAX
) {
3189 env
->cpuid_xlevel2
= env
->cpuid_min_xlevel2
;
3193 if (local_err
!= NULL
) {
3194 error_propagate(errp
, local_err
);
3198 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3199 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3200 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3201 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3202 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3203 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3204 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
3206 CPUState
*cs
= CPU(dev
);
3207 X86CPU
*cpu
= X86_CPU(dev
);
3208 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
3209 CPUX86State
*env
= &cpu
->env
;
3210 Error
*local_err
= NULL
;
3211 static bool ht_warned
;
3213 if (xcc
->kvm_required
&& !kvm_enabled()) {
3214 char *name
= x86_cpu_class_get_model_name(xcc
);
3215 error_setg(&local_err
, "CPU model '%s' requires KVM", name
);
3220 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
3221 error_setg(errp
, "apic-id property was not initialized properly");
3225 x86_cpu_load_features(cpu
, &local_err
);
3230 if (x86_cpu_filter_features(cpu
) &&
3231 (cpu
->check_cpuid
|| cpu
->enforce_cpuid
)) {
3232 x86_cpu_report_filtered_features(cpu
);
3233 if (cpu
->enforce_cpuid
) {
3234 error_setg(&local_err
,
3236 "Host doesn't support requested features" :
3237 "TCG doesn't support requested features");
3242 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3245 if (IS_AMD_CPU(env
)) {
3246 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
3247 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
3248 & CPUID_EXT2_AMD_ALIASES
);
3251 /* For 64bit systems think about the number of physical bits to present.
3252 * ideally this should be the same as the host; anything other than matching
3253 * the host can cause incorrect guest behaviour.
3254 * QEMU used to pick the magic value of 40 bits that corresponds to
3255 * consumer AMD devices but nothing else.
3257 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
3258 if (kvm_enabled()) {
3259 uint32_t host_phys_bits
= x86_host_phys_bits();
3262 if (cpu
->host_phys_bits
) {
3263 /* The user asked for us to use the host physical bits */
3264 cpu
->phys_bits
= host_phys_bits
;
3267 /* Print a warning if the user set it to a value that's not the
3270 if (cpu
->phys_bits
!= host_phys_bits
&& cpu
->phys_bits
!= 0 &&
3272 error_report("Warning: Host physical bits (%u)"
3273 " does not match phys-bits property (%u)",
3274 host_phys_bits
, cpu
->phys_bits
);
3278 if (cpu
->phys_bits
&&
3279 (cpu
->phys_bits
> TARGET_PHYS_ADDR_SPACE_BITS
||
3280 cpu
->phys_bits
< 32)) {
3281 error_setg(errp
, "phys-bits should be between 32 and %u "
3283 TARGET_PHYS_ADDR_SPACE_BITS
, cpu
->phys_bits
);
3287 if (cpu
->phys_bits
&& cpu
->phys_bits
!= TCG_PHYS_ADDR_BITS
) {
3288 error_setg(errp
, "TCG only supports phys-bits=%u",
3289 TCG_PHYS_ADDR_BITS
);
3293 /* 0 means it was not explicitly set by the user (or by machine
3294 * compat_props or by the host code above). In this case, the default
3295 * is the value used by TCG (40).
3297 if (cpu
->phys_bits
== 0) {
3298 cpu
->phys_bits
= TCG_PHYS_ADDR_BITS
;
3301 /* For 32 bit systems don't use the user set value, but keep
3302 * phys_bits consistent with what we tell the guest.
3304 if (cpu
->phys_bits
!= 0) {
3305 error_setg(errp
, "phys-bits is not user-configurable in 32 bit");
3309 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
3310 cpu
->phys_bits
= 36;
3312 cpu
->phys_bits
= 32;
3315 cpu_exec_realizefn(cs
, &local_err
);
3316 if (local_err
!= NULL
) {
3317 error_propagate(errp
, local_err
);
3321 if (tcg_enabled()) {
3325 #ifndef CONFIG_USER_ONLY
3326 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
3328 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| smp_cpus
> 1) {
3329 x86_cpu_apic_create(cpu
, &local_err
);
3330 if (local_err
!= NULL
) {
3338 #ifndef CONFIG_USER_ONLY
3339 if (tcg_enabled()) {
3340 AddressSpace
*newas
= g_new(AddressSpace
, 1);
3342 cpu
->cpu_as_mem
= g_new(MemoryRegion
, 1);
3343 cpu
->cpu_as_root
= g_new(MemoryRegion
, 1);
3345 /* Outer container... */
3346 memory_region_init(cpu
->cpu_as_root
, OBJECT(cpu
), "memory", ~0ull);
3347 memory_region_set_enabled(cpu
->cpu_as_root
, true);
3349 /* ... with two regions inside: normal system memory with low
3352 memory_region_init_alias(cpu
->cpu_as_mem
, OBJECT(cpu
), "memory",
3353 get_system_memory(), 0, ~0ull);
3354 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->cpu_as_mem
, 0);
3355 memory_region_set_enabled(cpu
->cpu_as_mem
, true);
3356 address_space_init(newas
, cpu
->cpu_as_root
, "CPU");
3358 cpu_address_space_init(cs
, newas
, 0);
3360 /* ... SMRAM with higher priority, linked from /machine/smram. */
3361 cpu
->machine_done
.notify
= x86_cpu_machine_done
;
3362 qemu_add_machine_init_done_notifier(&cpu
->machine_done
);
3368 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3369 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3370 * based on inputs (sockets,cores,threads), it is still better to gives
3373 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3374 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3376 if (!IS_INTEL_CPU(env
) && cs
->nr_threads
> 1 && !ht_warned
) {
3377 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3378 " -smp options properly.");
3382 x86_cpu_apic_realize(cpu
, &local_err
);
3383 if (local_err
!= NULL
) {
3388 xcc
->parent_realize(dev
, &local_err
);
3391 if (local_err
!= NULL
) {
3392 error_propagate(errp
, local_err
);
3397 static void x86_cpu_unrealizefn(DeviceState
*dev
, Error
**errp
)
3399 X86CPU
*cpu
= X86_CPU(dev
);
3400 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
3401 Error
*local_err
= NULL
;
3403 #ifndef CONFIG_USER_ONLY
3404 cpu_remove_sync(CPU(dev
));
3405 qemu_unregister_reset(x86_cpu_machine_reset_cb
, dev
);
3408 if (cpu
->apic_state
) {
3409 object_unparent(OBJECT(cpu
->apic_state
));
3410 cpu
->apic_state
= NULL
;
3413 xcc
->parent_unrealize(dev
, &local_err
);
3414 if (local_err
!= NULL
) {
3415 error_propagate(errp
, local_err
);
3420 typedef struct BitProperty
{
3425 static void x86_cpu_get_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
3426 void *opaque
, Error
**errp
)
3428 BitProperty
*fp
= opaque
;
3429 bool value
= (*fp
->ptr
& fp
->mask
) == fp
->mask
;
3430 visit_type_bool(v
, name
, &value
, errp
);
3433 static void x86_cpu_set_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
3434 void *opaque
, Error
**errp
)
3436 DeviceState
*dev
= DEVICE(obj
);
3437 BitProperty
*fp
= opaque
;
3438 Error
*local_err
= NULL
;
3441 if (dev
->realized
) {
3442 qdev_prop_set_after_realize(dev
, name
, errp
);
3446 visit_type_bool(v
, name
, &value
, &local_err
);
3448 error_propagate(errp
, local_err
);
3453 *fp
->ptr
|= fp
->mask
;
3455 *fp
->ptr
&= ~fp
->mask
;
3459 static void x86_cpu_release_bit_prop(Object
*obj
, const char *name
,
3462 BitProperty
*prop
= opaque
;
3466 /* Register a boolean property to get/set a single bit in a uint32_t field.
3468 * The same property name can be registered multiple times to make it affect
3469 * multiple bits in the same FeatureWord. In that case, the getter will return
3470 * true only if all bits are set.
3472 static void x86_cpu_register_bit_prop(X86CPU
*cpu
,
3473 const char *prop_name
,
3479 uint32_t mask
= (1UL << bitnr
);
3481 op
= object_property_find(OBJECT(cpu
), prop_name
, NULL
);
3484 assert(fp
->ptr
== field
);
3487 fp
= g_new0(BitProperty
, 1);
3490 object_property_add(OBJECT(cpu
), prop_name
, "bool",
3491 x86_cpu_get_bit_prop
,
3492 x86_cpu_set_bit_prop
,
3493 x86_cpu_release_bit_prop
, fp
, &error_abort
);
3497 static void x86_cpu_register_feature_bit_props(X86CPU
*cpu
,
3501 FeatureWordInfo
*fi
= &feature_word_info
[w
];
3502 const char *name
= fi
->feat_names
[bitnr
];
3508 /* Property names should use "-" instead of "_".
3509 * Old names containing underscores are registered as aliases
3510 * using object_property_add_alias()
3512 assert(!strchr(name
, '_'));
3513 /* aliases don't use "|" delimiters anymore, they are registered
3514 * manually using object_property_add_alias() */
3515 assert(!strchr(name
, '|'));
3516 x86_cpu_register_bit_prop(cpu
, name
, &cpu
->env
.features
[w
], bitnr
);
3519 static void x86_cpu_initfn(Object
*obj
)
3521 CPUState
*cs
= CPU(obj
);
3522 X86CPU
*cpu
= X86_CPU(obj
);
3523 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
3524 CPUX86State
*env
= &cpu
->env
;
3529 object_property_add(obj
, "family", "int",
3530 x86_cpuid_version_get_family
,
3531 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
3532 object_property_add(obj
, "model", "int",
3533 x86_cpuid_version_get_model
,
3534 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
3535 object_property_add(obj
, "stepping", "int",
3536 x86_cpuid_version_get_stepping
,
3537 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
3538 object_property_add_str(obj
, "vendor",
3539 x86_cpuid_get_vendor
,
3540 x86_cpuid_set_vendor
, NULL
);
3541 object_property_add_str(obj
, "model-id",
3542 x86_cpuid_get_model_id
,
3543 x86_cpuid_set_model_id
, NULL
);
3544 object_property_add(obj
, "tsc-frequency", "int",
3545 x86_cpuid_get_tsc_freq
,
3546 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
3547 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
3548 x86_cpu_get_feature_words
,
3549 NULL
, NULL
, (void *)env
->features
, NULL
);
3550 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
3551 x86_cpu_get_feature_words
,
3552 NULL
, NULL
, (void *)cpu
->filtered_features
, NULL
);
3554 cpu
->hyperv_spinlock_attempts
= HYPERV_SPINLOCK_NEVER_RETRY
;
3556 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3559 for (bitnr
= 0; bitnr
< 32; bitnr
++) {
3560 x86_cpu_register_feature_bit_props(cpu
, w
, bitnr
);
3564 object_property_add_alias(obj
, "sse3", obj
, "pni", &error_abort
);
3565 object_property_add_alias(obj
, "pclmuldq", obj
, "pclmulqdq", &error_abort
);
3566 object_property_add_alias(obj
, "sse4-1", obj
, "sse4.1", &error_abort
);
3567 object_property_add_alias(obj
, "sse4-2", obj
, "sse4.2", &error_abort
);
3568 object_property_add_alias(obj
, "xd", obj
, "nx", &error_abort
);
3569 object_property_add_alias(obj
, "ffxsr", obj
, "fxsr-opt", &error_abort
);
3570 object_property_add_alias(obj
, "i64", obj
, "lm", &error_abort
);
3572 object_property_add_alias(obj
, "ds_cpl", obj
, "ds-cpl", &error_abort
);
3573 object_property_add_alias(obj
, "tsc_adjust", obj
, "tsc-adjust", &error_abort
);
3574 object_property_add_alias(obj
, "fxsr_opt", obj
, "fxsr-opt", &error_abort
);
3575 object_property_add_alias(obj
, "lahf_lm", obj
, "lahf-lm", &error_abort
);
3576 object_property_add_alias(obj
, "cmp_legacy", obj
, "cmp-legacy", &error_abort
);
3577 object_property_add_alias(obj
, "nodeid_msr", obj
, "nodeid-msr", &error_abort
);
3578 object_property_add_alias(obj
, "perfctr_core", obj
, "perfctr-core", &error_abort
);
3579 object_property_add_alias(obj
, "perfctr_nb", obj
, "perfctr-nb", &error_abort
);
3580 object_property_add_alias(obj
, "kvm_nopiodelay", obj
, "kvm-nopiodelay", &error_abort
);
3581 object_property_add_alias(obj
, "kvm_mmu", obj
, "kvm-mmu", &error_abort
);
3582 object_property_add_alias(obj
, "kvm_asyncpf", obj
, "kvm-asyncpf", &error_abort
);
3583 object_property_add_alias(obj
, "kvm_steal_time", obj
, "kvm-steal-time", &error_abort
);
3584 object_property_add_alias(obj
, "kvm_pv_eoi", obj
, "kvm-pv-eoi", &error_abort
);
3585 object_property_add_alias(obj
, "kvm_pv_unhalt", obj
, "kvm-pv-unhalt", &error_abort
);
3586 object_property_add_alias(obj
, "svm_lock", obj
, "svm-lock", &error_abort
);
3587 object_property_add_alias(obj
, "nrip_save", obj
, "nrip-save", &error_abort
);
3588 object_property_add_alias(obj
, "tsc_scale", obj
, "tsc-scale", &error_abort
);
3589 object_property_add_alias(obj
, "vmcb_clean", obj
, "vmcb-clean", &error_abort
);
3590 object_property_add_alias(obj
, "pause_filter", obj
, "pause-filter", &error_abort
);
3591 object_property_add_alias(obj
, "sse4_1", obj
, "sse4.1", &error_abort
);
3592 object_property_add_alias(obj
, "sse4_2", obj
, "sse4.2", &error_abort
);
3594 x86_cpu_load_def(cpu
, xcc
->cpu_def
, &error_abort
);
3597 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
3599 X86CPU
*cpu
= X86_CPU(cs
);
3601 return cpu
->apic_id
;
3604 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
3606 X86CPU
*cpu
= X86_CPU(cs
);
3608 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
3611 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
3613 X86CPU
*cpu
= X86_CPU(cs
);
3615 cpu
->env
.eip
= value
;
3618 static void x86_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
3620 X86CPU
*cpu
= X86_CPU(cs
);
3622 cpu
->env
.eip
= tb
->pc
- tb
->cs_base
;
3625 static bool x86_cpu_has_work(CPUState
*cs
)
3627 X86CPU
*cpu
= X86_CPU(cs
);
3628 CPUX86State
*env
= &cpu
->env
;
3630 return ((cs
->interrupt_request
& (CPU_INTERRUPT_HARD
|
3631 CPU_INTERRUPT_POLL
)) &&
3632 (env
->eflags
& IF_MASK
)) ||
3633 (cs
->interrupt_request
& (CPU_INTERRUPT_NMI
|
3634 CPU_INTERRUPT_INIT
|
3635 CPU_INTERRUPT_SIPI
|
3636 CPU_INTERRUPT_MCE
)) ||
3637 ((cs
->interrupt_request
& CPU_INTERRUPT_SMI
) &&
3638 !(env
->hflags
& HF_SMM_MASK
));
3641 static Property x86_cpu_properties
[] = {
3642 #ifdef CONFIG_USER_ONLY
3643 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3644 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, 0),
3645 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, 0),
3646 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, 0),
3647 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, 0),
3649 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, UNASSIGNED_APIC_ID
),
3650 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, -1),
3651 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, -1),
3652 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, -1),
3654 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
3655 { .name
= "hv-spinlocks", .info
= &qdev_prop_spinlocks
},
3656 DEFINE_PROP_BOOL("hv-relaxed", X86CPU
, hyperv_relaxed_timing
, false),
3657 DEFINE_PROP_BOOL("hv-vapic", X86CPU
, hyperv_vapic
, false),
3658 DEFINE_PROP_BOOL("hv-time", X86CPU
, hyperv_time
, false),
3659 DEFINE_PROP_BOOL("hv-crash", X86CPU
, hyperv_crash
, false),
3660 DEFINE_PROP_BOOL("hv-reset", X86CPU
, hyperv_reset
, false),
3661 DEFINE_PROP_BOOL("hv-vpindex", X86CPU
, hyperv_vpindex
, false),
3662 DEFINE_PROP_BOOL("hv-runtime", X86CPU
, hyperv_runtime
, false),
3663 DEFINE_PROP_BOOL("hv-synic", X86CPU
, hyperv_synic
, false),
3664 DEFINE_PROP_BOOL("hv-stimer", X86CPU
, hyperv_stimer
, false),
3665 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, true),
3666 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
3667 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
3668 DEFINE_PROP_UINT32("phys-bits", X86CPU
, phys_bits
, 0),
3669 DEFINE_PROP_BOOL("host-phys-bits", X86CPU
, host_phys_bits
, false),
3670 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU
, fill_mtrr_mask
, true),
3671 DEFINE_PROP_UINT32("level", X86CPU
, env
.cpuid_level
, UINT32_MAX
),
3672 DEFINE_PROP_UINT32("xlevel", X86CPU
, env
.cpuid_xlevel
, UINT32_MAX
),
3673 DEFINE_PROP_UINT32("xlevel2", X86CPU
, env
.cpuid_xlevel2
, UINT32_MAX
),
3674 DEFINE_PROP_UINT32("min-level", X86CPU
, env
.cpuid_min_level
, 0),
3675 DEFINE_PROP_UINT32("min-xlevel", X86CPU
, env
.cpuid_min_xlevel
, 0),
3676 DEFINE_PROP_UINT32("min-xlevel2", X86CPU
, env
.cpuid_min_xlevel2
, 0),
3677 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU
, full_cpuid_auto_level
, true),
3678 DEFINE_PROP_STRING("hv-vendor-id", X86CPU
, hyperv_vendor_id
),
3679 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU
, enable_cpuid_0xb
, true),
3680 DEFINE_PROP_BOOL("lmce", X86CPU
, enable_lmce
, false),
3681 DEFINE_PROP_BOOL("l3-cache", X86CPU
, enable_l3_cache
, true),
3682 DEFINE_PROP_END_OF_LIST()
3685 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
3687 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
3688 CPUClass
*cc
= CPU_CLASS(oc
);
3689 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3691 xcc
->parent_realize
= dc
->realize
;
3692 xcc
->parent_unrealize
= dc
->unrealize
;
3693 dc
->realize
= x86_cpu_realizefn
;
3694 dc
->unrealize
= x86_cpu_unrealizefn
;
3695 dc
->props
= x86_cpu_properties
;
3697 xcc
->parent_reset
= cc
->reset
;
3698 cc
->reset
= x86_cpu_reset
;
3699 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
3701 cc
->class_by_name
= x86_cpu_class_by_name
;
3702 cc
->parse_features
= x86_cpu_parse_featurestr
;
3703 cc
->has_work
= x86_cpu_has_work
;
3704 cc
->do_interrupt
= x86_cpu_do_interrupt
;
3705 cc
->cpu_exec_interrupt
= x86_cpu_exec_interrupt
;
3706 cc
->dump_state
= x86_cpu_dump_state
;
3707 cc
->set_pc
= x86_cpu_set_pc
;
3708 cc
->synchronize_from_tb
= x86_cpu_synchronize_from_tb
;
3709 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
3710 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
3711 cc
->get_arch_id
= x86_cpu_get_arch_id
;
3712 cc
->get_paging_enabled
= x86_cpu_get_paging_enabled
;
3713 #ifdef CONFIG_USER_ONLY
3714 cc
->handle_mmu_fault
= x86_cpu_handle_mmu_fault
;
3716 cc
->get_memory_mapping
= x86_cpu_get_memory_mapping
;
3717 cc
->get_phys_page_debug
= x86_cpu_get_phys_page_debug
;
3718 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
3719 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
3720 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
3721 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
3722 cc
->vmsd
= &vmstate_x86_cpu
;
3724 /* CPU_NB_REGS * 2 = general regs + xmm regs
3725 * 25 = eip, eflags, 6 seg regs, st[0-7], fctrl,...,fop, mxcsr.
3727 cc
->gdb_num_core_regs
= CPU_NB_REGS
* 2 + 25;
3728 #ifndef CONFIG_USER_ONLY
3729 cc
->debug_excp_handler
= breakpoint_handler
;
3731 cc
->cpu_exec_enter
= x86_cpu_exec_enter
;
3732 cc
->cpu_exec_exit
= x86_cpu_exec_exit
;
3734 dc
->cannot_instantiate_with_device_add_yet
= false;
3737 static const TypeInfo x86_cpu_type_info
= {
3738 .name
= TYPE_X86_CPU
,
3740 .instance_size
= sizeof(X86CPU
),
3741 .instance_init
= x86_cpu_initfn
,
3743 .class_size
= sizeof(X86CPUClass
),
3744 .class_init
= x86_cpu_common_class_init
,
3747 static void x86_cpu_register_types(void)
3751 type_register_static(&x86_cpu_type_info
);
3752 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
3753 x86_register_cpudef_type(&builtin_x86_defs
[i
]);
3756 type_register_static(&host_x86_cpu_type_info
);
3760 type_init(x86_cpu_register_types
)