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i386: Add missing cpu feature bits in EPYC model
[mirror_qemu.git] / target / i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
25
26 #include "cpu.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/hvf.h"
31 #include "sysemu/cpus.h"
32 #include "kvm_i386.h"
33 #include "sev_i386.h"
34
35 #include "qemu/error-report.h"
36 #include "qemu/module.h"
37 #include "qemu/option.h"
38 #include "qemu/config-file.h"
39 #include "qapi/error.h"
40 #include "qapi/qapi-visit-machine.h"
41 #include "qapi/qapi-visit-run-state.h"
42 #include "qapi/qmp/qdict.h"
43 #include "qapi/qmp/qerror.h"
44 #include "qapi/visitor.h"
45 #include "qom/qom-qobject.h"
46 #include "sysemu/arch_init.h"
47 #include "qapi/qapi-commands-machine-target.h"
48
49 #include "standard-headers/asm-x86/kvm_para.h"
50
51 #include "sysemu/sysemu.h"
52 #include "sysemu/tcg.h"
53 #include "hw/qdev-properties.h"
54 #include "hw/i386/topology.h"
55 #ifndef CONFIG_USER_ONLY
56 #include "exec/address-spaces.h"
57 #include "hw/xen/xen.h"
58 #include "hw/i386/apic_internal.h"
59 #include "hw/boards.h"
60 #endif
61
62 #include "disas/capstone.h"
63
64 /* Helpers for building CPUID[2] descriptors: */
65
66 struct CPUID2CacheDescriptorInfo {
67 enum CacheType type;
68 int level;
69 int size;
70 int line_size;
71 int associativity;
72 };
73
74 /*
75 * Known CPUID 2 cache descriptors.
76 * From Intel SDM Volume 2A, CPUID instruction
77 */
78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
80 .associativity = 4, .line_size = 32, },
81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
82 .associativity = 4, .line_size = 32, },
83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
84 .associativity = 4, .line_size = 64, },
85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
86 .associativity = 2, .line_size = 32, },
87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
88 .associativity = 4, .line_size = 32, },
89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
90 .associativity = 4, .line_size = 64, },
91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
92 .associativity = 6, .line_size = 64, },
93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
94 .associativity = 2, .line_size = 64, },
95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
96 .associativity = 8, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x22, 0x23 are not included
99 */
100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
101 .associativity = 16, .line_size = 64, },
102 /* lines per sector is not supported cpuid2_cache_descriptor(),
103 * so descriptors 0x25, 0x20 are not included
104 */
105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
106 .associativity = 8, .line_size = 64, },
107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
108 .associativity = 8, .line_size = 64, },
109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
110 .associativity = 4, .line_size = 32, },
111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
112 .associativity = 4, .line_size = 32, },
113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
114 .associativity = 4, .line_size = 32, },
115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
116 .associativity = 4, .line_size = 32, },
117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
118 .associativity = 4, .line_size = 32, },
119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
120 .associativity = 4, .line_size = 64, },
121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
122 .associativity = 8, .line_size = 64, },
123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
124 .associativity = 12, .line_size = 64, },
125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
127 .associativity = 12, .line_size = 64, },
128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
129 .associativity = 16, .line_size = 64, },
130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
131 .associativity = 12, .line_size = 64, },
132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
133 .associativity = 16, .line_size = 64, },
134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
135 .associativity = 24, .line_size = 64, },
136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
137 .associativity = 8, .line_size = 64, },
138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
139 .associativity = 4, .line_size = 64, },
140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
141 .associativity = 4, .line_size = 64, },
142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
143 .associativity = 4, .line_size = 64, },
144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
145 .associativity = 4, .line_size = 64, },
146 /* lines per sector is not supported cpuid2_cache_descriptor(),
147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
148 */
149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
150 .associativity = 8, .line_size = 64, },
151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
152 .associativity = 2, .line_size = 64, },
153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
154 .associativity = 8, .line_size = 64, },
155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
156 .associativity = 8, .line_size = 32, },
157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
158 .associativity = 8, .line_size = 32, },
159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
160 .associativity = 8, .line_size = 32, },
161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
162 .associativity = 8, .line_size = 32, },
163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
164 .associativity = 4, .line_size = 64, },
165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
166 .associativity = 8, .line_size = 64, },
167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
168 .associativity = 4, .line_size = 64, },
169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
170 .associativity = 4, .line_size = 64, },
171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
172 .associativity = 4, .line_size = 64, },
173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
174 .associativity = 8, .line_size = 64, },
175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
176 .associativity = 8, .line_size = 64, },
177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
178 .associativity = 8, .line_size = 64, },
179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
180 .associativity = 12, .line_size = 64, },
181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
182 .associativity = 12, .line_size = 64, },
183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
184 .associativity = 12, .line_size = 64, },
185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
186 .associativity = 16, .line_size = 64, },
187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
188 .associativity = 16, .line_size = 64, },
189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
190 .associativity = 16, .line_size = 64, },
191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
192 .associativity = 24, .line_size = 64, },
193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
194 .associativity = 24, .line_size = 64, },
195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
196 .associativity = 24, .line_size = 64, },
197 };
198
199 /*
200 * "CPUID leaf 2 does not report cache descriptor information,
201 * use CPUID leaf 4 to query cache parameters"
202 */
203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
204
205 /*
206 * Return a CPUID 2 cache descriptor for a given cache.
207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
208 */
209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
210 {
211 int i;
212
213 assert(cache->size > 0);
214 assert(cache->level > 0);
215 assert(cache->line_size > 0);
216 assert(cache->associativity > 0);
217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
219 if (d->level == cache->level && d->type == cache->type &&
220 d->size == cache->size && d->line_size == cache->line_size &&
221 d->associativity == cache->associativity) {
222 return i;
223 }
224 }
225
226 return CACHE_DESCRIPTOR_UNAVAILABLE;
227 }
228
229 /* CPUID Leaf 4 constants: */
230
231 /* EAX: */
232 #define CACHE_TYPE_D 1
233 #define CACHE_TYPE_I 2
234 #define CACHE_TYPE_UNIFIED 3
235
236 #define CACHE_LEVEL(l) (l << 5)
237
238 #define CACHE_SELF_INIT_LEVEL (1 << 8)
239
240 /* EDX: */
241 #define CACHE_NO_INVD_SHARING (1 << 0)
242 #define CACHE_INCLUSIVE (1 << 1)
243 #define CACHE_COMPLEX_IDX (1 << 2)
244
245 /* Encode CacheType for CPUID[4].EAX */
246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
249 0 /* Invalid value */)
250
251
252 /* Encode cache info for CPUID[4] */
253 static void encode_cache_cpuid4(CPUCacheInfo *cache,
254 int num_apic_ids, int num_cores,
255 uint32_t *eax, uint32_t *ebx,
256 uint32_t *ecx, uint32_t *edx)
257 {
258 assert(cache->size == cache->line_size * cache->associativity *
259 cache->partitions * cache->sets);
260
261 assert(num_apic_ids > 0);
262 *eax = CACHE_TYPE(cache->type) |
263 CACHE_LEVEL(cache->level) |
264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
265 ((num_cores - 1) << 26) |
266 ((num_apic_ids - 1) << 14);
267
268 assert(cache->line_size > 0);
269 assert(cache->partitions > 0);
270 assert(cache->associativity > 0);
271 /* We don't implement fully-associative caches */
272 assert(cache->associativity < cache->sets);
273 *ebx = (cache->line_size - 1) |
274 ((cache->partitions - 1) << 12) |
275 ((cache->associativity - 1) << 22);
276
277 assert(cache->sets > 0);
278 *ecx = cache->sets - 1;
279
280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
281 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
283 }
284
285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
287 {
288 assert(cache->size % 1024 == 0);
289 assert(cache->lines_per_tag > 0);
290 assert(cache->associativity > 0);
291 assert(cache->line_size > 0);
292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
293 (cache->lines_per_tag << 8) | (cache->line_size);
294 }
295
296 #define ASSOC_FULL 0xFF
297
298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
300 a == 2 ? 0x2 : \
301 a == 4 ? 0x4 : \
302 a == 8 ? 0x6 : \
303 a == 16 ? 0x8 : \
304 a == 32 ? 0xA : \
305 a == 48 ? 0xB : \
306 a == 64 ? 0xC : \
307 a == 96 ? 0xD : \
308 a == 128 ? 0xE : \
309 a == ASSOC_FULL ? 0xF : \
310 0 /* invalid value */)
311
312 /*
313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
314 * @l3 can be NULL.
315 */
316 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
317 CPUCacheInfo *l3,
318 uint32_t *ecx, uint32_t *edx)
319 {
320 assert(l2->size % 1024 == 0);
321 assert(l2->associativity > 0);
322 assert(l2->lines_per_tag > 0);
323 assert(l2->line_size > 0);
324 *ecx = ((l2->size / 1024) << 16) |
325 (AMD_ENC_ASSOC(l2->associativity) << 12) |
326 (l2->lines_per_tag << 8) | (l2->line_size);
327
328 if (l3) {
329 assert(l3->size % (512 * 1024) == 0);
330 assert(l3->associativity > 0);
331 assert(l3->lines_per_tag > 0);
332 assert(l3->line_size > 0);
333 *edx = ((l3->size / (512 * 1024)) << 18) |
334 (AMD_ENC_ASSOC(l3->associativity) << 12) |
335 (l3->lines_per_tag << 8) | (l3->line_size);
336 } else {
337 *edx = 0;
338 }
339 }
340
341 /*
342 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
343 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
344 * Define the constants to build the cpu topology. Right now, TOPOEXT
345 * feature is enabled only on EPYC. So, these constants are based on
346 * EPYC supported configurations. We may need to handle the cases if
347 * these values change in future.
348 */
349 /* Maximum core complexes in a node */
350 #define MAX_CCX 2
351 /* Maximum cores in a core complex */
352 #define MAX_CORES_IN_CCX 4
353 /* Maximum cores in a node */
354 #define MAX_CORES_IN_NODE 8
355 /* Maximum nodes in a socket */
356 #define MAX_NODES_PER_SOCKET 4
357
358 /*
359 * Figure out the number of nodes required to build this config.
360 * Max cores in a node is 8
361 */
362 static int nodes_in_socket(int nr_cores)
363 {
364 int nodes;
365
366 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
367
368 /* Hardware does not support config with 3 nodes, return 4 in that case */
369 return (nodes == 3) ? 4 : nodes;
370 }
371
372 /*
373 * Decide the number of cores in a core complex with the given nr_cores using
374 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
375 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
376 * L3 cache is shared across all cores in a core complex. So, this will also
377 * tell us how many cores are sharing the L3 cache.
378 */
379 static int cores_in_core_complex(int nr_cores)
380 {
381 int nodes;
382
383 /* Check if we can fit all the cores in one core complex */
384 if (nr_cores <= MAX_CORES_IN_CCX) {
385 return nr_cores;
386 }
387 /* Get the number of nodes required to build this config */
388 nodes = nodes_in_socket(nr_cores);
389
390 /*
391 * Divide the cores accros all the core complexes
392 * Return rounded up value
393 */
394 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
395 }
396
397 /* Encode cache info for CPUID[8000001D] */
398 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
399 uint32_t *eax, uint32_t *ebx,
400 uint32_t *ecx, uint32_t *edx)
401 {
402 uint32_t l3_cores;
403 assert(cache->size == cache->line_size * cache->associativity *
404 cache->partitions * cache->sets);
405
406 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
407 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
408
409 /* L3 is shared among multiple cores */
410 if (cache->level == 3) {
411 l3_cores = cores_in_core_complex(cs->nr_cores);
412 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
413 } else {
414 *eax |= ((cs->nr_threads - 1) << 14);
415 }
416
417 assert(cache->line_size > 0);
418 assert(cache->partitions > 0);
419 assert(cache->associativity > 0);
420 /* We don't implement fully-associative caches */
421 assert(cache->associativity < cache->sets);
422 *ebx = (cache->line_size - 1) |
423 ((cache->partitions - 1) << 12) |
424 ((cache->associativity - 1) << 22);
425
426 assert(cache->sets > 0);
427 *ecx = cache->sets - 1;
428
429 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
430 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
431 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
432 }
433
434 /* Data structure to hold the configuration info for a given core index */
435 struct core_topology {
436 /* core complex id of the current core index */
437 int ccx_id;
438 /*
439 * Adjusted core index for this core in the topology
440 * This can be 0,1,2,3 with max 4 cores in a core complex
441 */
442 int core_id;
443 /* Node id for this core index */
444 int node_id;
445 /* Number of nodes in this config */
446 int num_nodes;
447 };
448
449 /*
450 * Build the configuration closely match the EPYC hardware. Using the EPYC
451 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
452 * right now. This could change in future.
453 * nr_cores : Total number of cores in the config
454 * core_id : Core index of the current CPU
455 * topo : Data structure to hold all the config info for this core index
456 */
457 static void build_core_topology(int nr_cores, int core_id,
458 struct core_topology *topo)
459 {
460 int nodes, cores_in_ccx;
461
462 /* First get the number of nodes required */
463 nodes = nodes_in_socket(nr_cores);
464
465 cores_in_ccx = cores_in_core_complex(nr_cores);
466
467 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
468 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
469 topo->core_id = core_id % cores_in_ccx;
470 topo->num_nodes = nodes;
471 }
472
473 /* Encode cache info for CPUID[8000001E] */
474 static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
475 uint32_t *eax, uint32_t *ebx,
476 uint32_t *ecx, uint32_t *edx)
477 {
478 struct core_topology topo = {0};
479 unsigned long nodes;
480 int shift;
481
482 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
483 *eax = cpu->apic_id;
484 /*
485 * CPUID_Fn8000001E_EBX
486 * 31:16 Reserved
487 * 15:8 Threads per core (The number of threads per core is
488 * Threads per core + 1)
489 * 7:0 Core id (see bit decoding below)
490 * SMT:
491 * 4:3 node id
492 * 2 Core complex id
493 * 1:0 Core id
494 * Non SMT:
495 * 5:4 node id
496 * 3 Core complex id
497 * 1:0 Core id
498 */
499 if (cs->nr_threads - 1) {
500 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
501 (topo.ccx_id << 2) | topo.core_id;
502 } else {
503 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
504 }
505 /*
506 * CPUID_Fn8000001E_ECX
507 * 31:11 Reserved
508 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
509 * 7:0 Node id (see bit decoding below)
510 * 2 Socket id
511 * 1:0 Node id
512 */
513 if (topo.num_nodes <= 4) {
514 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
515 topo.node_id;
516 } else {
517 /*
518 * Node id fix up. Actual hardware supports up to 4 nodes. But with
519 * more than 32 cores, we may end up with more than 4 nodes.
520 * Node id is a combination of socket id and node id. Only requirement
521 * here is that this number should be unique accross the system.
522 * Shift the socket id to accommodate more nodes. We dont expect both
523 * socket id and node id to be big number at the same time. This is not
524 * an ideal config but we need to to support it. Max nodes we can have
525 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
526 * 5 bits for nodes. Find the left most set bit to represent the total
527 * number of nodes. find_last_bit returns last set bit(0 based). Left
528 * shift(+1) the socket id to represent all the nodes.
529 */
530 nodes = topo.num_nodes - 1;
531 shift = find_last_bit(&nodes, 8);
532 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
533 topo.node_id;
534 }
535 *edx = 0;
536 }
537
538 /*
539 * Definitions of the hardcoded cache entries we expose:
540 * These are legacy cache values. If there is a need to change any
541 * of these values please use builtin_x86_defs
542 */
543
544 /* L1 data cache: */
545 static CPUCacheInfo legacy_l1d_cache = {
546 .type = DATA_CACHE,
547 .level = 1,
548 .size = 32 * KiB,
549 .self_init = 1,
550 .line_size = 64,
551 .associativity = 8,
552 .sets = 64,
553 .partitions = 1,
554 .no_invd_sharing = true,
555 };
556
557 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
558 static CPUCacheInfo legacy_l1d_cache_amd = {
559 .type = DATA_CACHE,
560 .level = 1,
561 .size = 64 * KiB,
562 .self_init = 1,
563 .line_size = 64,
564 .associativity = 2,
565 .sets = 512,
566 .partitions = 1,
567 .lines_per_tag = 1,
568 .no_invd_sharing = true,
569 };
570
571 /* L1 instruction cache: */
572 static CPUCacheInfo legacy_l1i_cache = {
573 .type = INSTRUCTION_CACHE,
574 .level = 1,
575 .size = 32 * KiB,
576 .self_init = 1,
577 .line_size = 64,
578 .associativity = 8,
579 .sets = 64,
580 .partitions = 1,
581 .no_invd_sharing = true,
582 };
583
584 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
585 static CPUCacheInfo legacy_l1i_cache_amd = {
586 .type = INSTRUCTION_CACHE,
587 .level = 1,
588 .size = 64 * KiB,
589 .self_init = 1,
590 .line_size = 64,
591 .associativity = 2,
592 .sets = 512,
593 .partitions = 1,
594 .lines_per_tag = 1,
595 .no_invd_sharing = true,
596 };
597
598 /* Level 2 unified cache: */
599 static CPUCacheInfo legacy_l2_cache = {
600 .type = UNIFIED_CACHE,
601 .level = 2,
602 .size = 4 * MiB,
603 .self_init = 1,
604 .line_size = 64,
605 .associativity = 16,
606 .sets = 4096,
607 .partitions = 1,
608 .no_invd_sharing = true,
609 };
610
611 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
612 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
613 .type = UNIFIED_CACHE,
614 .level = 2,
615 .size = 2 * MiB,
616 .line_size = 64,
617 .associativity = 8,
618 };
619
620
621 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
622 static CPUCacheInfo legacy_l2_cache_amd = {
623 .type = UNIFIED_CACHE,
624 .level = 2,
625 .size = 512 * KiB,
626 .line_size = 64,
627 .lines_per_tag = 1,
628 .associativity = 16,
629 .sets = 512,
630 .partitions = 1,
631 };
632
633 /* Level 3 unified cache: */
634 static CPUCacheInfo legacy_l3_cache = {
635 .type = UNIFIED_CACHE,
636 .level = 3,
637 .size = 16 * MiB,
638 .line_size = 64,
639 .associativity = 16,
640 .sets = 16384,
641 .partitions = 1,
642 .lines_per_tag = 1,
643 .self_init = true,
644 .inclusive = true,
645 .complex_indexing = true,
646 };
647
648 /* TLB definitions: */
649
650 #define L1_DTLB_2M_ASSOC 1
651 #define L1_DTLB_2M_ENTRIES 255
652 #define L1_DTLB_4K_ASSOC 1
653 #define L1_DTLB_4K_ENTRIES 255
654
655 #define L1_ITLB_2M_ASSOC 1
656 #define L1_ITLB_2M_ENTRIES 255
657 #define L1_ITLB_4K_ASSOC 1
658 #define L1_ITLB_4K_ENTRIES 255
659
660 #define L2_DTLB_2M_ASSOC 0 /* disabled */
661 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
662 #define L2_DTLB_4K_ASSOC 4
663 #define L2_DTLB_4K_ENTRIES 512
664
665 #define L2_ITLB_2M_ASSOC 0 /* disabled */
666 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
667 #define L2_ITLB_4K_ASSOC 4
668 #define L2_ITLB_4K_ENTRIES 512
669
670 /* CPUID Leaf 0x14 constants: */
671 #define INTEL_PT_MAX_SUBLEAF 0x1
672 /*
673 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
674 * MSR can be accessed;
675 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
676 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
677 * of Intel PT MSRs across warm reset;
678 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
679 */
680 #define INTEL_PT_MINIMAL_EBX 0xf
681 /*
682 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
683 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
684 * accessed;
685 * bit[01]: ToPA tables can hold any number of output entries, up to the
686 * maximum allowed by the MaskOrTableOffset field of
687 * IA32_RTIT_OUTPUT_MASK_PTRS;
688 * bit[02]: Support Single-Range Output scheme;
689 */
690 #define INTEL_PT_MINIMAL_ECX 0x7
691 /* generated packets which contain IP payloads have LIP values */
692 #define INTEL_PT_IP_LIP (1 << 31)
693 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
694 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
695 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
696 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
697 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
698
699 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
700 uint32_t vendor2, uint32_t vendor3)
701 {
702 int i;
703 for (i = 0; i < 4; i++) {
704 dst[i] = vendor1 >> (8 * i);
705 dst[i + 4] = vendor2 >> (8 * i);
706 dst[i + 8] = vendor3 >> (8 * i);
707 }
708 dst[CPUID_VENDOR_SZ] = '\0';
709 }
710
711 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
712 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
713 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
714 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
715 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
716 CPUID_PSE36 | CPUID_FXSR)
717 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
718 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
719 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
720 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
721 CPUID_PAE | CPUID_SEP | CPUID_APIC)
722
723 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
724 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
725 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
726 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
727 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
728 /* partly implemented:
729 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
730 /* missing:
731 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
732 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
733 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
734 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
735 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
736 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
737 CPUID_EXT_RDRAND)
738 /* missing:
739 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
740 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
741 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
742 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
743 CPUID_EXT_F16C */
744
745 #ifdef TARGET_X86_64
746 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
747 #else
748 #define TCG_EXT2_X86_64_FEATURES 0
749 #endif
750
751 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
752 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
753 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
754 TCG_EXT2_X86_64_FEATURES)
755 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
756 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
757 #define TCG_EXT4_FEATURES 0
758 #define TCG_SVM_FEATURES CPUID_SVM_NPT
759 #define TCG_KVM_FEATURES 0
760 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
761 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
762 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
763 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
764 CPUID_7_0_EBX_ERMS)
765 /* missing:
766 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
767 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
768 CPUID_7_0_EBX_RDSEED */
769 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
770 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
771 CPUID_7_0_ECX_LA57)
772 #define TCG_7_0_EDX_FEATURES 0
773 #define TCG_7_1_EAX_FEATURES 0
774 #define TCG_APM_FEATURES 0
775 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
776 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
777 /* missing:
778 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
779
780 typedef enum FeatureWordType {
781 CPUID_FEATURE_WORD,
782 MSR_FEATURE_WORD,
783 } FeatureWordType;
784
785 typedef struct FeatureWordInfo {
786 FeatureWordType type;
787 /* feature flags names are taken from "Intel Processor Identification and
788 * the CPUID Instruction" and AMD's "CPUID Specification".
789 * In cases of disagreement between feature naming conventions,
790 * aliases may be added.
791 */
792 const char *feat_names[64];
793 union {
794 /* If type==CPUID_FEATURE_WORD */
795 struct {
796 uint32_t eax; /* Input EAX for CPUID */
797 bool needs_ecx; /* CPUID instruction uses ECX as input */
798 uint32_t ecx; /* Input ECX value for CPUID */
799 int reg; /* output register (R_* constant) */
800 } cpuid;
801 /* If type==MSR_FEATURE_WORD */
802 struct {
803 uint32_t index;
804 } msr;
805 };
806 uint64_t tcg_features; /* Feature flags supported by TCG */
807 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */
808 uint64_t migratable_flags; /* Feature flags known to be migratable */
809 /* Features that shouldn't be auto-enabled by "-cpu host" */
810 uint64_t no_autoenable_flags;
811 } FeatureWordInfo;
812
813 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
814 [FEAT_1_EDX] = {
815 .type = CPUID_FEATURE_WORD,
816 .feat_names = {
817 "fpu", "vme", "de", "pse",
818 "tsc", "msr", "pae", "mce",
819 "cx8", "apic", NULL, "sep",
820 "mtrr", "pge", "mca", "cmov",
821 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
822 NULL, "ds" /* Intel dts */, "acpi", "mmx",
823 "fxsr", "sse", "sse2", "ss",
824 "ht" /* Intel htt */, "tm", "ia64", "pbe",
825 },
826 .cpuid = {.eax = 1, .reg = R_EDX, },
827 .tcg_features = TCG_FEATURES,
828 },
829 [FEAT_1_ECX] = {
830 .type = CPUID_FEATURE_WORD,
831 .feat_names = {
832 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
833 "ds-cpl", "vmx", "smx", "est",
834 "tm2", "ssse3", "cid", NULL,
835 "fma", "cx16", "xtpr", "pdcm",
836 NULL, "pcid", "dca", "sse4.1",
837 "sse4.2", "x2apic", "movbe", "popcnt",
838 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
839 "avx", "f16c", "rdrand", "hypervisor",
840 },
841 .cpuid = { .eax = 1, .reg = R_ECX, },
842 .tcg_features = TCG_EXT_FEATURES,
843 },
844 /* Feature names that are already defined on feature_name[] but
845 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
846 * names on feat_names below. They are copied automatically
847 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
848 */
849 [FEAT_8000_0001_EDX] = {
850 .type = CPUID_FEATURE_WORD,
851 .feat_names = {
852 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
853 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
854 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
855 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
856 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
857 "nx", NULL, "mmxext", NULL /* mmx */,
858 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
859 NULL, "lm", "3dnowext", "3dnow",
860 },
861 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
862 .tcg_features = TCG_EXT2_FEATURES,
863 },
864 [FEAT_8000_0001_ECX] = {
865 .type = CPUID_FEATURE_WORD,
866 .feat_names = {
867 "lahf-lm", "cmp-legacy", "svm", "extapic",
868 "cr8legacy", "abm", "sse4a", "misalignsse",
869 "3dnowprefetch", "osvw", "ibs", "xop",
870 "skinit", "wdt", NULL, "lwp",
871 "fma4", "tce", NULL, "nodeid-msr",
872 NULL, "tbm", "topoext", "perfctr-core",
873 "perfctr-nb", NULL, NULL, NULL,
874 NULL, NULL, NULL, NULL,
875 },
876 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
877 .tcg_features = TCG_EXT3_FEATURES,
878 /*
879 * TOPOEXT is always allowed but can't be enabled blindly by
880 * "-cpu host", as it requires consistent cache topology info
881 * to be provided so it doesn't confuse guests.
882 */
883 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
884 },
885 [FEAT_C000_0001_EDX] = {
886 .type = CPUID_FEATURE_WORD,
887 .feat_names = {
888 NULL, NULL, "xstore", "xstore-en",
889 NULL, NULL, "xcrypt", "xcrypt-en",
890 "ace2", "ace2-en", "phe", "phe-en",
891 "pmm", "pmm-en", NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 NULL, NULL, NULL, NULL,
896 },
897 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
898 .tcg_features = TCG_EXT4_FEATURES,
899 },
900 [FEAT_KVM] = {
901 .type = CPUID_FEATURE_WORD,
902 .feat_names = {
903 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
904 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
905 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
906 "kvm-poll-control", "kvm-pv-sched-yield", NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 NULL, NULL, NULL, NULL,
909 "kvmclock-stable-bit", NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
911 },
912 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
913 .tcg_features = TCG_KVM_FEATURES,
914 },
915 [FEAT_KVM_HINTS] = {
916 .type = CPUID_FEATURE_WORD,
917 .feat_names = {
918 "kvm-hint-dedicated", NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 NULL, NULL, NULL, NULL,
924 NULL, NULL, NULL, NULL,
925 NULL, NULL, NULL, NULL,
926 },
927 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
928 .tcg_features = TCG_KVM_FEATURES,
929 /*
930 * KVM hints aren't auto-enabled by -cpu host, they need to be
931 * explicitly enabled in the command-line.
932 */
933 .no_autoenable_flags = ~0U,
934 },
935 /*
936 * .feat_names are commented out for Hyper-V enlightenments because we
937 * don't want to have two different ways for enabling them on QEMU command
938 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
939 * enabling several feature bits simultaneously, exposing these bits
940 * individually may just confuse guests.
941 */
942 [FEAT_HYPERV_EAX] = {
943 .type = CPUID_FEATURE_WORD,
944 .feat_names = {
945 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
946 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
947 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
948 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
949 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
950 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
951 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
952 NULL, NULL,
953 NULL, NULL, NULL, NULL,
954 NULL, NULL, NULL, NULL,
955 NULL, NULL, NULL, NULL,
956 NULL, NULL, NULL, NULL,
957 },
958 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
959 },
960 [FEAT_HYPERV_EBX] = {
961 .type = CPUID_FEATURE_WORD,
962 .feat_names = {
963 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
964 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
965 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
966 NULL /* hv_create_port */, NULL /* hv_connect_port */,
967 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
968 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
969 NULL, NULL,
970 NULL, NULL, NULL, NULL,
971 NULL, NULL, NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 NULL, NULL, NULL, NULL,
974 },
975 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
976 },
977 [FEAT_HYPERV_EDX] = {
978 .type = CPUID_FEATURE_WORD,
979 .feat_names = {
980 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
981 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
982 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
983 NULL, NULL,
984 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
985 NULL, NULL, NULL, NULL,
986 NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL,
990 },
991 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
992 },
993 [FEAT_HV_RECOMM_EAX] = {
994 .type = CPUID_FEATURE_WORD,
995 .feat_names = {
996 NULL /* hv_recommend_pv_as_switch */,
997 NULL /* hv_recommend_pv_tlbflush_local */,
998 NULL /* hv_recommend_pv_tlbflush_remote */,
999 NULL /* hv_recommend_msr_apic_access */,
1000 NULL /* hv_recommend_msr_reset */,
1001 NULL /* hv_recommend_relaxed_timing */,
1002 NULL /* hv_recommend_dma_remapping */,
1003 NULL /* hv_recommend_int_remapping */,
1004 NULL /* hv_recommend_x2apic_msrs */,
1005 NULL /* hv_recommend_autoeoi_deprecation */,
1006 NULL /* hv_recommend_pv_ipi */,
1007 NULL /* hv_recommend_ex_hypercalls */,
1008 NULL /* hv_hypervisor_is_nested */,
1009 NULL /* hv_recommend_int_mbec */,
1010 NULL /* hv_recommend_evmcs */,
1011 NULL,
1012 NULL, NULL, NULL, NULL,
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 NULL, NULL, NULL, NULL,
1016 },
1017 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1018 },
1019 [FEAT_HV_NESTED_EAX] = {
1020 .type = CPUID_FEATURE_WORD,
1021 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1022 },
1023 [FEAT_SVM] = {
1024 .type = CPUID_FEATURE_WORD,
1025 .feat_names = {
1026 "npt", "lbrv", "svm-lock", "nrip-save",
1027 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1028 NULL, NULL, "pause-filter", NULL,
1029 "pfthreshold", NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL,
1032 NULL, NULL, NULL, NULL,
1033 NULL, NULL, NULL, NULL,
1034 },
1035 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
1036 .tcg_features = TCG_SVM_FEATURES,
1037 },
1038 [FEAT_7_0_EBX] = {
1039 .type = CPUID_FEATURE_WORD,
1040 .feat_names = {
1041 "fsgsbase", "tsc-adjust", NULL, "bmi1",
1042 "hle", "avx2", NULL, "smep",
1043 "bmi2", "erms", "invpcid", "rtm",
1044 NULL, NULL, "mpx", NULL,
1045 "avx512f", "avx512dq", "rdseed", "adx",
1046 "smap", "avx512ifma", "pcommit", "clflushopt",
1047 "clwb", "intel-pt", "avx512pf", "avx512er",
1048 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1049 },
1050 .cpuid = {
1051 .eax = 7,
1052 .needs_ecx = true, .ecx = 0,
1053 .reg = R_EBX,
1054 },
1055 .tcg_features = TCG_7_0_EBX_FEATURES,
1056 },
1057 [FEAT_7_0_ECX] = {
1058 .type = CPUID_FEATURE_WORD,
1059 .feat_names = {
1060 NULL, "avx512vbmi", "umip", "pku",
1061 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
1062 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1063 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
1064 "la57", NULL, NULL, NULL,
1065 NULL, NULL, "rdpid", NULL,
1066 NULL, "cldemote", NULL, "movdiri",
1067 "movdir64b", NULL, NULL, NULL,
1068 },
1069 .cpuid = {
1070 .eax = 7,
1071 .needs_ecx = true, .ecx = 0,
1072 .reg = R_ECX,
1073 },
1074 .tcg_features = TCG_7_0_ECX_FEATURES,
1075 },
1076 [FEAT_7_0_EDX] = {
1077 .type = CPUID_FEATURE_WORD,
1078 .feat_names = {
1079 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1080 NULL, NULL, NULL, NULL,
1081 NULL, NULL, "md-clear", NULL,
1082 NULL, NULL, NULL, NULL,
1083 NULL, NULL, NULL /* pconfig */, NULL,
1084 NULL, NULL, NULL, NULL,
1085 NULL, NULL, "spec-ctrl", "stibp",
1086 NULL, "arch-capabilities", "core-capability", "ssbd",
1087 },
1088 .cpuid = {
1089 .eax = 7,
1090 .needs_ecx = true, .ecx = 0,
1091 .reg = R_EDX,
1092 },
1093 .tcg_features = TCG_7_0_EDX_FEATURES,
1094 },
1095 [FEAT_7_1_EAX] = {
1096 .type = CPUID_FEATURE_WORD,
1097 .feat_names = {
1098 NULL, NULL, NULL, NULL,
1099 NULL, "avx512-bf16", NULL, NULL,
1100 NULL, NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL,
1102 NULL, NULL, NULL, NULL,
1103 NULL, NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1106 },
1107 .cpuid = {
1108 .eax = 7,
1109 .needs_ecx = true, .ecx = 1,
1110 .reg = R_EAX,
1111 },
1112 .tcg_features = TCG_7_1_EAX_FEATURES,
1113 },
1114 [FEAT_8000_0007_EDX] = {
1115 .type = CPUID_FEATURE_WORD,
1116 .feat_names = {
1117 NULL, NULL, NULL, NULL,
1118 NULL, NULL, NULL, NULL,
1119 "invtsc", NULL, NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
1122 NULL, NULL, NULL, NULL,
1123 NULL, NULL, NULL, NULL,
1124 NULL, NULL, NULL, NULL,
1125 },
1126 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1127 .tcg_features = TCG_APM_FEATURES,
1128 .unmigratable_flags = CPUID_APM_INVTSC,
1129 },
1130 [FEAT_8000_0008_EBX] = {
1131 .type = CPUID_FEATURE_WORD,
1132 .feat_names = {
1133 "clzero", NULL, "xsaveerptr", NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, "wbnoinvd", NULL, NULL,
1136 "ibpb", NULL, NULL, NULL,
1137 NULL, NULL, NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1140 NULL, NULL, NULL, NULL,
1141 },
1142 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1143 .tcg_features = 0,
1144 .unmigratable_flags = 0,
1145 },
1146 [FEAT_XSAVE] = {
1147 .type = CPUID_FEATURE_WORD,
1148 .feat_names = {
1149 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 NULL, NULL, NULL, NULL,
1157 },
1158 .cpuid = {
1159 .eax = 0xd,
1160 .needs_ecx = true, .ecx = 1,
1161 .reg = R_EAX,
1162 },
1163 .tcg_features = TCG_XSAVE_FEATURES,
1164 },
1165 [FEAT_6_EAX] = {
1166 .type = CPUID_FEATURE_WORD,
1167 .feat_names = {
1168 NULL, NULL, "arat", NULL,
1169 NULL, NULL, NULL, NULL,
1170 NULL, NULL, NULL, NULL,
1171 NULL, NULL, NULL, NULL,
1172 NULL, NULL, NULL, NULL,
1173 NULL, NULL, NULL, NULL,
1174 NULL, NULL, NULL, NULL,
1175 NULL, NULL, NULL, NULL,
1176 },
1177 .cpuid = { .eax = 6, .reg = R_EAX, },
1178 .tcg_features = TCG_6_EAX_FEATURES,
1179 },
1180 [FEAT_XSAVE_COMP_LO] = {
1181 .type = CPUID_FEATURE_WORD,
1182 .cpuid = {
1183 .eax = 0xD,
1184 .needs_ecx = true, .ecx = 0,
1185 .reg = R_EAX,
1186 },
1187 .tcg_features = ~0U,
1188 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1189 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1190 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1191 XSTATE_PKRU_MASK,
1192 },
1193 [FEAT_XSAVE_COMP_HI] = {
1194 .type = CPUID_FEATURE_WORD,
1195 .cpuid = {
1196 .eax = 0xD,
1197 .needs_ecx = true, .ecx = 0,
1198 .reg = R_EDX,
1199 },
1200 .tcg_features = ~0U,
1201 },
1202 /*Below are MSR exposed features*/
1203 [FEAT_ARCH_CAPABILITIES] = {
1204 .type = MSR_FEATURE_WORD,
1205 .feat_names = {
1206 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1207 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1208 "taa-no", NULL, NULL, NULL,
1209 NULL, NULL, NULL, NULL,
1210 NULL, NULL, NULL, NULL,
1211 NULL, NULL, NULL, NULL,
1212 NULL, NULL, NULL, NULL,
1213 NULL, NULL, NULL, NULL,
1214 },
1215 .msr = {
1216 .index = MSR_IA32_ARCH_CAPABILITIES,
1217 },
1218 },
1219 [FEAT_CORE_CAPABILITY] = {
1220 .type = MSR_FEATURE_WORD,
1221 .feat_names = {
1222 NULL, NULL, NULL, NULL,
1223 NULL, "split-lock-detect", NULL, NULL,
1224 NULL, NULL, NULL, NULL,
1225 NULL, NULL, NULL, NULL,
1226 NULL, NULL, NULL, NULL,
1227 NULL, NULL, NULL, NULL,
1228 NULL, NULL, NULL, NULL,
1229 NULL, NULL, NULL, NULL,
1230 },
1231 .msr = {
1232 .index = MSR_IA32_CORE_CAPABILITY,
1233 },
1234 },
1235
1236 [FEAT_VMX_PROCBASED_CTLS] = {
1237 .type = MSR_FEATURE_WORD,
1238 .feat_names = {
1239 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1240 NULL, NULL, NULL, "vmx-hlt-exit",
1241 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1242 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1243 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1244 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1245 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1246 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1247 },
1248 .msr = {
1249 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1250 }
1251 },
1252
1253 [FEAT_VMX_SECONDARY_CTLS] = {
1254 .type = MSR_FEATURE_WORD,
1255 .feat_names = {
1256 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1257 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1258 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1259 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1260 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1261 "vmx-xsaves", NULL, NULL, NULL,
1262 NULL, NULL, NULL, NULL,
1263 NULL, NULL, NULL, NULL,
1264 },
1265 .msr = {
1266 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1267 }
1268 },
1269
1270 [FEAT_VMX_PINBASED_CTLS] = {
1271 .type = MSR_FEATURE_WORD,
1272 .feat_names = {
1273 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1274 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1275 NULL, NULL, NULL, NULL,
1276 NULL, NULL, NULL, NULL,
1277 NULL, NULL, NULL, NULL,
1278 NULL, NULL, NULL, NULL,
1279 NULL, NULL, NULL, NULL,
1280 NULL, NULL, NULL, NULL,
1281 },
1282 .msr = {
1283 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1284 }
1285 },
1286
1287 [FEAT_VMX_EXIT_CTLS] = {
1288 .type = MSR_FEATURE_WORD,
1289 /*
1290 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1291 * the LM CPUID bit.
1292 */
1293 .feat_names = {
1294 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1295 NULL, NULL, NULL, NULL,
1296 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1297 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1298 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1299 "vmx-exit-save-efer", "vmx-exit-load-efer",
1300 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1301 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1302 NULL, NULL, NULL, NULL,
1303 },
1304 .msr = {
1305 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1306 }
1307 },
1308
1309 [FEAT_VMX_ENTRY_CTLS] = {
1310 .type = MSR_FEATURE_WORD,
1311 .feat_names = {
1312 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1313 NULL, NULL, NULL, NULL,
1314 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1315 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1316 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1317 NULL, NULL, NULL, NULL,
1318 NULL, NULL, NULL, NULL,
1319 NULL, NULL, NULL, NULL,
1320 },
1321 .msr = {
1322 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1323 }
1324 },
1325
1326 [FEAT_VMX_MISC] = {
1327 .type = MSR_FEATURE_WORD,
1328 .feat_names = {
1329 NULL, NULL, NULL, NULL,
1330 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1331 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1332 NULL, NULL, NULL, NULL,
1333 NULL, NULL, NULL, NULL,
1334 NULL, NULL, NULL, NULL,
1335 NULL, NULL, NULL, NULL,
1336 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1337 },
1338 .msr = {
1339 .index = MSR_IA32_VMX_MISC,
1340 }
1341 },
1342
1343 [FEAT_VMX_EPT_VPID_CAPS] = {
1344 .type = MSR_FEATURE_WORD,
1345 .feat_names = {
1346 "vmx-ept-execonly", NULL, NULL, NULL,
1347 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1348 NULL, NULL, NULL, NULL,
1349 NULL, NULL, NULL, NULL,
1350 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1351 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1352 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1353 NULL, NULL, NULL, NULL,
1354 "vmx-invvpid", NULL, NULL, NULL,
1355 NULL, NULL, NULL, NULL,
1356 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1357 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1358 NULL, NULL, NULL, NULL,
1359 NULL, NULL, NULL, NULL,
1360 NULL, NULL, NULL, NULL,
1361 NULL, NULL, NULL, NULL,
1362 NULL, NULL, NULL, NULL,
1363 },
1364 .msr = {
1365 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1366 }
1367 },
1368
1369 [FEAT_VMX_BASIC] = {
1370 .type = MSR_FEATURE_WORD,
1371 .feat_names = {
1372 [54] = "vmx-ins-outs",
1373 [55] = "vmx-true-ctls",
1374 },
1375 .msr = {
1376 .index = MSR_IA32_VMX_BASIC,
1377 },
1378 /* Just to be safe - we don't support setting the MSEG version field. */
1379 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1380 },
1381
1382 [FEAT_VMX_VMFUNC] = {
1383 .type = MSR_FEATURE_WORD,
1384 .feat_names = {
1385 [0] = "vmx-eptp-switching",
1386 },
1387 .msr = {
1388 .index = MSR_IA32_VMX_VMFUNC,
1389 }
1390 },
1391
1392 };
1393
1394 typedef struct FeatureMask {
1395 FeatureWord index;
1396 uint64_t mask;
1397 } FeatureMask;
1398
1399 typedef struct FeatureDep {
1400 FeatureMask from, to;
1401 } FeatureDep;
1402
1403 static FeatureDep feature_dependencies[] = {
1404 {
1405 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
1406 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
1407 },
1408 {
1409 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
1410 .to = { FEAT_CORE_CAPABILITY, ~0ull },
1411 },
1412 {
1413 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1414 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1415 },
1416 {
1417 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1418 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1419 },
1420 {
1421 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1422 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1423 },
1424 {
1425 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1426 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1427 },
1428 {
1429 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1430 .to = { FEAT_VMX_MISC, ~0ull },
1431 },
1432 {
1433 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1434 .to = { FEAT_VMX_BASIC, ~0ull },
1435 },
1436 {
1437 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1438 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1439 },
1440 {
1441 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1442 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1443 },
1444 {
1445 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1446 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1447 },
1448 {
1449 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1450 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1451 },
1452 {
1453 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1454 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1455 },
1456 {
1457 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1458 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1459 },
1460 {
1461 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1462 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1463 },
1464 {
1465 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1466 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1467 },
1468 {
1469 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1470 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1471 },
1472 {
1473 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1474 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1475 },
1476 {
1477 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1478 .to = { FEAT_VMX_VMFUNC, ~0ull },
1479 },
1480 };
1481
1482 typedef struct X86RegisterInfo32 {
1483 /* Name of register */
1484 const char *name;
1485 /* QAPI enum value register */
1486 X86CPURegister32 qapi_enum;
1487 } X86RegisterInfo32;
1488
1489 #define REGISTER(reg) \
1490 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1491 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1492 REGISTER(EAX),
1493 REGISTER(ECX),
1494 REGISTER(EDX),
1495 REGISTER(EBX),
1496 REGISTER(ESP),
1497 REGISTER(EBP),
1498 REGISTER(ESI),
1499 REGISTER(EDI),
1500 };
1501 #undef REGISTER
1502
1503 typedef struct ExtSaveArea {
1504 uint32_t feature, bits;
1505 uint32_t offset, size;
1506 } ExtSaveArea;
1507
1508 static const ExtSaveArea x86_ext_save_areas[] = {
1509 [XSTATE_FP_BIT] = {
1510 /* x87 FP state component is always enabled if XSAVE is supported */
1511 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1512 /* x87 state is in the legacy region of the XSAVE area */
1513 .offset = 0,
1514 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1515 },
1516 [XSTATE_SSE_BIT] = {
1517 /* SSE state component is always enabled if XSAVE is supported */
1518 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1519 /* SSE state is in the legacy region of the XSAVE area */
1520 .offset = 0,
1521 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1522 },
1523 [XSTATE_YMM_BIT] =
1524 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1525 .offset = offsetof(X86XSaveArea, avx_state),
1526 .size = sizeof(XSaveAVX) },
1527 [XSTATE_BNDREGS_BIT] =
1528 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1529 .offset = offsetof(X86XSaveArea, bndreg_state),
1530 .size = sizeof(XSaveBNDREG) },
1531 [XSTATE_BNDCSR_BIT] =
1532 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1533 .offset = offsetof(X86XSaveArea, bndcsr_state),
1534 .size = sizeof(XSaveBNDCSR) },
1535 [XSTATE_OPMASK_BIT] =
1536 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1537 .offset = offsetof(X86XSaveArea, opmask_state),
1538 .size = sizeof(XSaveOpmask) },
1539 [XSTATE_ZMM_Hi256_BIT] =
1540 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1541 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1542 .size = sizeof(XSaveZMM_Hi256) },
1543 [XSTATE_Hi16_ZMM_BIT] =
1544 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1545 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1546 .size = sizeof(XSaveHi16_ZMM) },
1547 [XSTATE_PKRU_BIT] =
1548 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1549 .offset = offsetof(X86XSaveArea, pkru_state),
1550 .size = sizeof(XSavePKRU) },
1551 };
1552
1553 static uint32_t xsave_area_size(uint64_t mask)
1554 {
1555 int i;
1556 uint64_t ret = 0;
1557
1558 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1559 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1560 if ((mask >> i) & 1) {
1561 ret = MAX(ret, esa->offset + esa->size);
1562 }
1563 }
1564 return ret;
1565 }
1566
1567 static inline bool accel_uses_host_cpuid(void)
1568 {
1569 return kvm_enabled() || hvf_enabled();
1570 }
1571
1572 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1573 {
1574 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1575 cpu->env.features[FEAT_XSAVE_COMP_LO];
1576 }
1577
1578 const char *get_register_name_32(unsigned int reg)
1579 {
1580 if (reg >= CPU_NB_REGS32) {
1581 return NULL;
1582 }
1583 return x86_reg_info_32[reg].name;
1584 }
1585
1586 /*
1587 * Returns the set of feature flags that are supported and migratable by
1588 * QEMU, for a given FeatureWord.
1589 */
1590 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
1591 {
1592 FeatureWordInfo *wi = &feature_word_info[w];
1593 uint64_t r = 0;
1594 int i;
1595
1596 for (i = 0; i < 64; i++) {
1597 uint64_t f = 1ULL << i;
1598
1599 /* If the feature name is known, it is implicitly considered migratable,
1600 * unless it is explicitly set in unmigratable_flags */
1601 if ((wi->migratable_flags & f) ||
1602 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1603 r |= f;
1604 }
1605 }
1606 return r;
1607 }
1608
1609 void host_cpuid(uint32_t function, uint32_t count,
1610 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1611 {
1612 uint32_t vec[4];
1613
1614 #ifdef __x86_64__
1615 asm volatile("cpuid"
1616 : "=a"(vec[0]), "=b"(vec[1]),
1617 "=c"(vec[2]), "=d"(vec[3])
1618 : "0"(function), "c"(count) : "cc");
1619 #elif defined(__i386__)
1620 asm volatile("pusha \n\t"
1621 "cpuid \n\t"
1622 "mov %%eax, 0(%2) \n\t"
1623 "mov %%ebx, 4(%2) \n\t"
1624 "mov %%ecx, 8(%2) \n\t"
1625 "mov %%edx, 12(%2) \n\t"
1626 "popa"
1627 : : "a"(function), "c"(count), "S"(vec)
1628 : "memory", "cc");
1629 #else
1630 abort();
1631 #endif
1632
1633 if (eax)
1634 *eax = vec[0];
1635 if (ebx)
1636 *ebx = vec[1];
1637 if (ecx)
1638 *ecx = vec[2];
1639 if (edx)
1640 *edx = vec[3];
1641 }
1642
1643 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1644 {
1645 uint32_t eax, ebx, ecx, edx;
1646
1647 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1648 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1649
1650 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1651 if (family) {
1652 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1653 }
1654 if (model) {
1655 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1656 }
1657 if (stepping) {
1658 *stepping = eax & 0x0F;
1659 }
1660 }
1661
1662 /* CPU class name definitions: */
1663
1664 /* Return type name for a given CPU model name
1665 * Caller is responsible for freeing the returned string.
1666 */
1667 static char *x86_cpu_type_name(const char *model_name)
1668 {
1669 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1670 }
1671
1672 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1673 {
1674 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1675 return object_class_by_name(typename);
1676 }
1677
1678 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1679 {
1680 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1681 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1682 return g_strndup(class_name,
1683 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1684 }
1685
1686 typedef struct PropValue {
1687 const char *prop, *value;
1688 } PropValue;
1689
1690 typedef struct X86CPUVersionDefinition {
1691 X86CPUVersion version;
1692 const char *alias;
1693 const char *note;
1694 PropValue *props;
1695 } X86CPUVersionDefinition;
1696
1697 /* Base definition for a CPU model */
1698 typedef struct X86CPUDefinition {
1699 const char *name;
1700 uint32_t level;
1701 uint32_t xlevel;
1702 /* vendor is zero-terminated, 12 character ASCII string */
1703 char vendor[CPUID_VENDOR_SZ + 1];
1704 int family;
1705 int model;
1706 int stepping;
1707 FeatureWordArray features;
1708 const char *model_id;
1709 CPUCaches *cache_info;
1710 /*
1711 * Definitions for alternative versions of CPU model.
1712 * List is terminated by item with version == 0.
1713 * If NULL, version 1 will be registered automatically.
1714 */
1715 const X86CPUVersionDefinition *versions;
1716 } X86CPUDefinition;
1717
1718 /* Reference to a specific CPU model version */
1719 struct X86CPUModel {
1720 /* Base CPU definition */
1721 X86CPUDefinition *cpudef;
1722 /* CPU model version */
1723 X86CPUVersion version;
1724 const char *note;
1725 /*
1726 * If true, this is an alias CPU model.
1727 * This matters only for "-cpu help" and query-cpu-definitions
1728 */
1729 bool is_alias;
1730 };
1731
1732 /* Get full model name for CPU version */
1733 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1734 X86CPUVersion version)
1735 {
1736 assert(version > 0);
1737 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1738 }
1739
1740 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1741 {
1742 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1743 static const X86CPUVersionDefinition default_version_list[] = {
1744 { 1 },
1745 { /* end of list */ }
1746 };
1747
1748 return def->versions ?: default_version_list;
1749 }
1750
1751 static CPUCaches epyc_cache_info = {
1752 .l1d_cache = &(CPUCacheInfo) {
1753 .type = DATA_CACHE,
1754 .level = 1,
1755 .size = 32 * KiB,
1756 .line_size = 64,
1757 .associativity = 8,
1758 .partitions = 1,
1759 .sets = 64,
1760 .lines_per_tag = 1,
1761 .self_init = 1,
1762 .no_invd_sharing = true,
1763 },
1764 .l1i_cache = &(CPUCacheInfo) {
1765 .type = INSTRUCTION_CACHE,
1766 .level = 1,
1767 .size = 64 * KiB,
1768 .line_size = 64,
1769 .associativity = 4,
1770 .partitions = 1,
1771 .sets = 256,
1772 .lines_per_tag = 1,
1773 .self_init = 1,
1774 .no_invd_sharing = true,
1775 },
1776 .l2_cache = &(CPUCacheInfo) {
1777 .type = UNIFIED_CACHE,
1778 .level = 2,
1779 .size = 512 * KiB,
1780 .line_size = 64,
1781 .associativity = 8,
1782 .partitions = 1,
1783 .sets = 1024,
1784 .lines_per_tag = 1,
1785 },
1786 .l3_cache = &(CPUCacheInfo) {
1787 .type = UNIFIED_CACHE,
1788 .level = 3,
1789 .size = 8 * MiB,
1790 .line_size = 64,
1791 .associativity = 16,
1792 .partitions = 1,
1793 .sets = 8192,
1794 .lines_per_tag = 1,
1795 .self_init = true,
1796 .inclusive = true,
1797 .complex_indexing = true,
1798 },
1799 };
1800
1801 /* The following VMX features are not supported by KVM and are left out in the
1802 * CPU definitions:
1803 *
1804 * Dual-monitor support (all processors)
1805 * Entry to SMM
1806 * Deactivate dual-monitor treatment
1807 * Number of CR3-target values
1808 * Shutdown activity state
1809 * Wait-for-SIPI activity state
1810 * PAUSE-loop exiting (Westmere and newer)
1811 * EPT-violation #VE (Broadwell and newer)
1812 * Inject event with insn length=0 (Skylake and newer)
1813 * Conceal non-root operation from PT
1814 * Conceal VM exits from PT
1815 * Conceal VM entries from PT
1816 * Enable ENCLS exiting
1817 * Mode-based execute control (XS/XU)
1818 s TSC scaling (Skylake Server and newer)
1819 * GPA translation for PT (IceLake and newer)
1820 * User wait and pause
1821 * ENCLV exiting
1822 * Load IA32_RTIT_CTL
1823 * Clear IA32_RTIT_CTL
1824 * Advanced VM-exit information for EPT violations
1825 * Sub-page write permissions
1826 * PT in VMX operation
1827 */
1828
1829 static X86CPUDefinition builtin_x86_defs[] = {
1830 {
1831 .name = "qemu64",
1832 .level = 0xd,
1833 .vendor = CPUID_VENDOR_AMD,
1834 .family = 6,
1835 .model = 6,
1836 .stepping = 3,
1837 .features[FEAT_1_EDX] =
1838 PPRO_FEATURES |
1839 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1840 CPUID_PSE36,
1841 .features[FEAT_1_ECX] =
1842 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1843 .features[FEAT_8000_0001_EDX] =
1844 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1845 .features[FEAT_8000_0001_ECX] =
1846 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1847 .xlevel = 0x8000000A,
1848 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1849 },
1850 {
1851 .name = "phenom",
1852 .level = 5,
1853 .vendor = CPUID_VENDOR_AMD,
1854 .family = 16,
1855 .model = 2,
1856 .stepping = 3,
1857 /* Missing: CPUID_HT */
1858 .features[FEAT_1_EDX] =
1859 PPRO_FEATURES |
1860 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1861 CPUID_PSE36 | CPUID_VME,
1862 .features[FEAT_1_ECX] =
1863 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1864 CPUID_EXT_POPCNT,
1865 .features[FEAT_8000_0001_EDX] =
1866 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1867 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1868 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1869 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1870 CPUID_EXT3_CR8LEG,
1871 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1872 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1873 .features[FEAT_8000_0001_ECX] =
1874 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1875 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1876 /* Missing: CPUID_SVM_LBRV */
1877 .features[FEAT_SVM] =
1878 CPUID_SVM_NPT,
1879 .xlevel = 0x8000001A,
1880 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1881 },
1882 {
1883 .name = "core2duo",
1884 .level = 10,
1885 .vendor = CPUID_VENDOR_INTEL,
1886 .family = 6,
1887 .model = 15,
1888 .stepping = 11,
1889 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1890 .features[FEAT_1_EDX] =
1891 PPRO_FEATURES |
1892 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1893 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1894 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1895 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1896 .features[FEAT_1_ECX] =
1897 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1898 CPUID_EXT_CX16,
1899 .features[FEAT_8000_0001_EDX] =
1900 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1901 .features[FEAT_8000_0001_ECX] =
1902 CPUID_EXT3_LAHF_LM,
1903 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1904 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1905 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1906 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1907 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1908 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1909 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1910 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1911 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1912 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1913 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1914 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1915 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1916 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1917 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1918 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1919 .features[FEAT_VMX_SECONDARY_CTLS] =
1920 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
1921 .xlevel = 0x80000008,
1922 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1923 },
1924 {
1925 .name = "kvm64",
1926 .level = 0xd,
1927 .vendor = CPUID_VENDOR_INTEL,
1928 .family = 15,
1929 .model = 6,
1930 .stepping = 1,
1931 /* Missing: CPUID_HT */
1932 .features[FEAT_1_EDX] =
1933 PPRO_FEATURES | CPUID_VME |
1934 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1935 CPUID_PSE36,
1936 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1937 .features[FEAT_1_ECX] =
1938 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1939 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1940 .features[FEAT_8000_0001_EDX] =
1941 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1942 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1943 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1944 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1945 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1946 .features[FEAT_8000_0001_ECX] =
1947 0,
1948 /* VMX features from Cedar Mill/Prescott */
1949 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1950 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1951 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1952 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1953 VMX_PIN_BASED_NMI_EXITING,
1954 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1955 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1956 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1957 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1958 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1959 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1960 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1961 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
1962 .xlevel = 0x80000008,
1963 .model_id = "Common KVM processor"
1964 },
1965 {
1966 .name = "qemu32",
1967 .level = 4,
1968 .vendor = CPUID_VENDOR_INTEL,
1969 .family = 6,
1970 .model = 6,
1971 .stepping = 3,
1972 .features[FEAT_1_EDX] =
1973 PPRO_FEATURES,
1974 .features[FEAT_1_ECX] =
1975 CPUID_EXT_SSE3,
1976 .xlevel = 0x80000004,
1977 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1978 },
1979 {
1980 .name = "kvm32",
1981 .level = 5,
1982 .vendor = CPUID_VENDOR_INTEL,
1983 .family = 15,
1984 .model = 6,
1985 .stepping = 1,
1986 .features[FEAT_1_EDX] =
1987 PPRO_FEATURES | CPUID_VME |
1988 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1989 .features[FEAT_1_ECX] =
1990 CPUID_EXT_SSE3,
1991 .features[FEAT_8000_0001_ECX] =
1992 0,
1993 /* VMX features from Yonah */
1994 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1995 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1996 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1997 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1998 VMX_PIN_BASED_NMI_EXITING,
1999 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2000 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2001 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2002 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2003 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2004 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2005 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2006 .xlevel = 0x80000008,
2007 .model_id = "Common 32-bit KVM processor"
2008 },
2009 {
2010 .name = "coreduo",
2011 .level = 10,
2012 .vendor = CPUID_VENDOR_INTEL,
2013 .family = 6,
2014 .model = 14,
2015 .stepping = 8,
2016 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2017 .features[FEAT_1_EDX] =
2018 PPRO_FEATURES | CPUID_VME |
2019 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
2020 CPUID_SS,
2021 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
2022 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
2023 .features[FEAT_1_ECX] =
2024 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
2025 .features[FEAT_8000_0001_EDX] =
2026 CPUID_EXT2_NX,
2027 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2028 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2029 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2030 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2031 VMX_PIN_BASED_NMI_EXITING,
2032 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2033 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2034 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2035 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2036 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2037 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2038 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2039 .xlevel = 0x80000008,
2040 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2041 },
2042 {
2043 .name = "486",
2044 .level = 1,
2045 .vendor = CPUID_VENDOR_INTEL,
2046 .family = 4,
2047 .model = 8,
2048 .stepping = 0,
2049 .features[FEAT_1_EDX] =
2050 I486_FEATURES,
2051 .xlevel = 0,
2052 .model_id = "",
2053 },
2054 {
2055 .name = "pentium",
2056 .level = 1,
2057 .vendor = CPUID_VENDOR_INTEL,
2058 .family = 5,
2059 .model = 4,
2060 .stepping = 3,
2061 .features[FEAT_1_EDX] =
2062 PENTIUM_FEATURES,
2063 .xlevel = 0,
2064 .model_id = "",
2065 },
2066 {
2067 .name = "pentium2",
2068 .level = 2,
2069 .vendor = CPUID_VENDOR_INTEL,
2070 .family = 6,
2071 .model = 5,
2072 .stepping = 2,
2073 .features[FEAT_1_EDX] =
2074 PENTIUM2_FEATURES,
2075 .xlevel = 0,
2076 .model_id = "",
2077 },
2078 {
2079 .name = "pentium3",
2080 .level = 3,
2081 .vendor = CPUID_VENDOR_INTEL,
2082 .family = 6,
2083 .model = 7,
2084 .stepping = 3,
2085 .features[FEAT_1_EDX] =
2086 PENTIUM3_FEATURES,
2087 .xlevel = 0,
2088 .model_id = "",
2089 },
2090 {
2091 .name = "athlon",
2092 .level = 2,
2093 .vendor = CPUID_VENDOR_AMD,
2094 .family = 6,
2095 .model = 2,
2096 .stepping = 3,
2097 .features[FEAT_1_EDX] =
2098 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
2099 CPUID_MCA,
2100 .features[FEAT_8000_0001_EDX] =
2101 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
2102 .xlevel = 0x80000008,
2103 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
2104 },
2105 {
2106 .name = "n270",
2107 .level = 10,
2108 .vendor = CPUID_VENDOR_INTEL,
2109 .family = 6,
2110 .model = 28,
2111 .stepping = 2,
2112 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2113 .features[FEAT_1_EDX] =
2114 PPRO_FEATURES |
2115 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2116 CPUID_ACPI | CPUID_SS,
2117 /* Some CPUs got no CPUID_SEP */
2118 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2119 * CPUID_EXT_XTPR */
2120 .features[FEAT_1_ECX] =
2121 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
2122 CPUID_EXT_MOVBE,
2123 .features[FEAT_8000_0001_EDX] =
2124 CPUID_EXT2_NX,
2125 .features[FEAT_8000_0001_ECX] =
2126 CPUID_EXT3_LAHF_LM,
2127 .xlevel = 0x80000008,
2128 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2129 },
2130 {
2131 .name = "Conroe",
2132 .level = 10,
2133 .vendor = CPUID_VENDOR_INTEL,
2134 .family = 6,
2135 .model = 15,
2136 .stepping = 3,
2137 .features[FEAT_1_EDX] =
2138 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2139 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2140 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2141 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2142 CPUID_DE | CPUID_FP87,
2143 .features[FEAT_1_ECX] =
2144 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2145 .features[FEAT_8000_0001_EDX] =
2146 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2147 .features[FEAT_8000_0001_ECX] =
2148 CPUID_EXT3_LAHF_LM,
2149 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2150 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2151 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2152 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2153 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2154 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2155 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2156 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2157 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2158 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2159 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2160 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2161 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2162 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2163 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2164 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2165 .features[FEAT_VMX_SECONDARY_CTLS] =
2166 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
2167 .xlevel = 0x80000008,
2168 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2169 },
2170 {
2171 .name = "Penryn",
2172 .level = 10,
2173 .vendor = CPUID_VENDOR_INTEL,
2174 .family = 6,
2175 .model = 23,
2176 .stepping = 3,
2177 .features[FEAT_1_EDX] =
2178 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2179 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2180 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2181 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2182 CPUID_DE | CPUID_FP87,
2183 .features[FEAT_1_ECX] =
2184 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2185 CPUID_EXT_SSE3,
2186 .features[FEAT_8000_0001_EDX] =
2187 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2188 .features[FEAT_8000_0001_ECX] =
2189 CPUID_EXT3_LAHF_LM,
2190 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2191 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2192 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2193 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2194 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2195 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2196 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2197 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2198 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2199 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2200 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2201 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2202 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2203 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2204 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2205 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2206 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2207 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2208 .features[FEAT_VMX_SECONDARY_CTLS] =
2209 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2210 VMX_SECONDARY_EXEC_WBINVD_EXITING,
2211 .xlevel = 0x80000008,
2212 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2213 },
2214 {
2215 .name = "Nehalem",
2216 .level = 11,
2217 .vendor = CPUID_VENDOR_INTEL,
2218 .family = 6,
2219 .model = 26,
2220 .stepping = 3,
2221 .features[FEAT_1_EDX] =
2222 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2223 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2224 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2225 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2226 CPUID_DE | CPUID_FP87,
2227 .features[FEAT_1_ECX] =
2228 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2229 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2230 .features[FEAT_8000_0001_EDX] =
2231 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2232 .features[FEAT_8000_0001_ECX] =
2233 CPUID_EXT3_LAHF_LM,
2234 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2235 MSR_VMX_BASIC_TRUE_CTLS,
2236 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2237 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2238 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2239 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2240 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2241 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2242 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2243 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2244 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2245 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2246 .features[FEAT_VMX_EXIT_CTLS] =
2247 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2248 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2249 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2250 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2251 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2252 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2253 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2254 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2255 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2256 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2257 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2258 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2259 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2260 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2261 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2262 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2263 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2264 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2265 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2266 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2267 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2268 .features[FEAT_VMX_SECONDARY_CTLS] =
2269 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2270 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2271 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2272 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2273 VMX_SECONDARY_EXEC_ENABLE_VPID,
2274 .xlevel = 0x80000008,
2275 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
2276 .versions = (X86CPUVersionDefinition[]) {
2277 { .version = 1 },
2278 {
2279 .version = 2,
2280 .alias = "Nehalem-IBRS",
2281 .props = (PropValue[]) {
2282 { "spec-ctrl", "on" },
2283 { "model-id",
2284 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2285 { /* end of list */ }
2286 }
2287 },
2288 { /* end of list */ }
2289 }
2290 },
2291 {
2292 .name = "Westmere",
2293 .level = 11,
2294 .vendor = CPUID_VENDOR_INTEL,
2295 .family = 6,
2296 .model = 44,
2297 .stepping = 1,
2298 .features[FEAT_1_EDX] =
2299 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2300 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2301 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2302 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2303 CPUID_DE | CPUID_FP87,
2304 .features[FEAT_1_ECX] =
2305 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2306 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2307 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2308 .features[FEAT_8000_0001_EDX] =
2309 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2310 .features[FEAT_8000_0001_ECX] =
2311 CPUID_EXT3_LAHF_LM,
2312 .features[FEAT_6_EAX] =
2313 CPUID_6_EAX_ARAT,
2314 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2315 MSR_VMX_BASIC_TRUE_CTLS,
2316 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2317 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2318 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2319 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2320 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2321 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2322 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2323 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2324 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2325 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2326 .features[FEAT_VMX_EXIT_CTLS] =
2327 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2328 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2329 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2330 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2331 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2332 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2333 MSR_VMX_MISC_STORE_LMA,
2334 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2335 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2336 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2337 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2338 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2339 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2340 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2341 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2342 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2343 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2344 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2345 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2346 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2347 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2348 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2349 .features[FEAT_VMX_SECONDARY_CTLS] =
2350 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2351 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2352 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2353 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2354 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2355 .xlevel = 0x80000008,
2356 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2357 .versions = (X86CPUVersionDefinition[]) {
2358 { .version = 1 },
2359 {
2360 .version = 2,
2361 .alias = "Westmere-IBRS",
2362 .props = (PropValue[]) {
2363 { "spec-ctrl", "on" },
2364 { "model-id",
2365 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2366 { /* end of list */ }
2367 }
2368 },
2369 { /* end of list */ }
2370 }
2371 },
2372 {
2373 .name = "SandyBridge",
2374 .level = 0xd,
2375 .vendor = CPUID_VENDOR_INTEL,
2376 .family = 6,
2377 .model = 42,
2378 .stepping = 1,
2379 .features[FEAT_1_EDX] =
2380 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2381 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2382 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2383 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2384 CPUID_DE | CPUID_FP87,
2385 .features[FEAT_1_ECX] =
2386 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2387 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2388 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2389 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2390 CPUID_EXT_SSE3,
2391 .features[FEAT_8000_0001_EDX] =
2392 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2393 CPUID_EXT2_SYSCALL,
2394 .features[FEAT_8000_0001_ECX] =
2395 CPUID_EXT3_LAHF_LM,
2396 .features[FEAT_XSAVE] =
2397 CPUID_XSAVE_XSAVEOPT,
2398 .features[FEAT_6_EAX] =
2399 CPUID_6_EAX_ARAT,
2400 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2401 MSR_VMX_BASIC_TRUE_CTLS,
2402 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2403 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2404 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2405 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2406 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2407 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2408 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2409 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2410 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2411 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2412 .features[FEAT_VMX_EXIT_CTLS] =
2413 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2414 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2415 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2416 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2417 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2418 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2419 MSR_VMX_MISC_STORE_LMA,
2420 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2421 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2422 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2423 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2424 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2425 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2426 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2427 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2428 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2429 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2430 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2431 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2432 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2433 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2434 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2435 .features[FEAT_VMX_SECONDARY_CTLS] =
2436 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2437 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2438 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2439 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2440 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2441 .xlevel = 0x80000008,
2442 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
2443 .versions = (X86CPUVersionDefinition[]) {
2444 { .version = 1 },
2445 {
2446 .version = 2,
2447 .alias = "SandyBridge-IBRS",
2448 .props = (PropValue[]) {
2449 { "spec-ctrl", "on" },
2450 { "model-id",
2451 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2452 { /* end of list */ }
2453 }
2454 },
2455 { /* end of list */ }
2456 }
2457 },
2458 {
2459 .name = "IvyBridge",
2460 .level = 0xd,
2461 .vendor = CPUID_VENDOR_INTEL,
2462 .family = 6,
2463 .model = 58,
2464 .stepping = 9,
2465 .features[FEAT_1_EDX] =
2466 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2467 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2468 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2469 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2470 CPUID_DE | CPUID_FP87,
2471 .features[FEAT_1_ECX] =
2472 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2473 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2474 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2475 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2476 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2477 .features[FEAT_7_0_EBX] =
2478 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2479 CPUID_7_0_EBX_ERMS,
2480 .features[FEAT_8000_0001_EDX] =
2481 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2482 CPUID_EXT2_SYSCALL,
2483 .features[FEAT_8000_0001_ECX] =
2484 CPUID_EXT3_LAHF_LM,
2485 .features[FEAT_XSAVE] =
2486 CPUID_XSAVE_XSAVEOPT,
2487 .features[FEAT_6_EAX] =
2488 CPUID_6_EAX_ARAT,
2489 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2490 MSR_VMX_BASIC_TRUE_CTLS,
2491 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2492 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2493 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2494 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2495 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2496 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2497 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2498 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2499 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2500 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2501 .features[FEAT_VMX_EXIT_CTLS] =
2502 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2503 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2504 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2505 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2506 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2507 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2508 MSR_VMX_MISC_STORE_LMA,
2509 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2510 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2511 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2512 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2513 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2514 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2515 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2516 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2517 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2518 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2519 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2520 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2521 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2522 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2523 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2524 .features[FEAT_VMX_SECONDARY_CTLS] =
2525 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2526 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2527 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2528 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2529 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2530 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2531 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2532 VMX_SECONDARY_EXEC_RDRAND_EXITING,
2533 .xlevel = 0x80000008,
2534 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2535 .versions = (X86CPUVersionDefinition[]) {
2536 { .version = 1 },
2537 {
2538 .version = 2,
2539 .alias = "IvyBridge-IBRS",
2540 .props = (PropValue[]) {
2541 { "spec-ctrl", "on" },
2542 { "model-id",
2543 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2544 { /* end of list */ }
2545 }
2546 },
2547 { /* end of list */ }
2548 }
2549 },
2550 {
2551 .name = "Haswell",
2552 .level = 0xd,
2553 .vendor = CPUID_VENDOR_INTEL,
2554 .family = 6,
2555 .model = 60,
2556 .stepping = 4,
2557 .features[FEAT_1_EDX] =
2558 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2559 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2560 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2561 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2562 CPUID_DE | CPUID_FP87,
2563 .features[FEAT_1_ECX] =
2564 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2565 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2566 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2567 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2568 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2569 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2570 .features[FEAT_8000_0001_EDX] =
2571 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2572 CPUID_EXT2_SYSCALL,
2573 .features[FEAT_8000_0001_ECX] =
2574 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2575 .features[FEAT_7_0_EBX] =
2576 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2577 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2578 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2579 CPUID_7_0_EBX_RTM,
2580 .features[FEAT_XSAVE] =
2581 CPUID_XSAVE_XSAVEOPT,
2582 .features[FEAT_6_EAX] =
2583 CPUID_6_EAX_ARAT,
2584 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2585 MSR_VMX_BASIC_TRUE_CTLS,
2586 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2587 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2588 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2589 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2590 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2591 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2592 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2593 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2594 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2595 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2596 .features[FEAT_VMX_EXIT_CTLS] =
2597 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2598 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2599 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2600 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2601 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2602 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2603 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2604 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2605 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2606 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2607 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2608 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2609 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2610 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2611 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2612 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2613 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2614 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2615 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2616 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2617 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2618 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2619 .features[FEAT_VMX_SECONDARY_CTLS] =
2620 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2621 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2622 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2623 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2624 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2625 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2626 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2627 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2628 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2629 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2630 .xlevel = 0x80000008,
2631 .model_id = "Intel Core Processor (Haswell)",
2632 .versions = (X86CPUVersionDefinition[]) {
2633 { .version = 1 },
2634 {
2635 .version = 2,
2636 .alias = "Haswell-noTSX",
2637 .props = (PropValue[]) {
2638 { "hle", "off" },
2639 { "rtm", "off" },
2640 { "stepping", "1" },
2641 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2642 { /* end of list */ }
2643 },
2644 },
2645 {
2646 .version = 3,
2647 .alias = "Haswell-IBRS",
2648 .props = (PropValue[]) {
2649 /* Restore TSX features removed by -v2 above */
2650 { "hle", "on" },
2651 { "rtm", "on" },
2652 /*
2653 * Haswell and Haswell-IBRS had stepping=4 in
2654 * QEMU 4.0 and older
2655 */
2656 { "stepping", "4" },
2657 { "spec-ctrl", "on" },
2658 { "model-id",
2659 "Intel Core Processor (Haswell, IBRS)" },
2660 { /* end of list */ }
2661 }
2662 },
2663 {
2664 .version = 4,
2665 .alias = "Haswell-noTSX-IBRS",
2666 .props = (PropValue[]) {
2667 { "hle", "off" },
2668 { "rtm", "off" },
2669 /* spec-ctrl was already enabled by -v3 above */
2670 { "stepping", "1" },
2671 { "model-id",
2672 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2673 { /* end of list */ }
2674 }
2675 },
2676 { /* end of list */ }
2677 }
2678 },
2679 {
2680 .name = "Broadwell",
2681 .level = 0xd,
2682 .vendor = CPUID_VENDOR_INTEL,
2683 .family = 6,
2684 .model = 61,
2685 .stepping = 2,
2686 .features[FEAT_1_EDX] =
2687 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2688 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2689 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2690 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2691 CPUID_DE | CPUID_FP87,
2692 .features[FEAT_1_ECX] =
2693 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2694 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2695 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2696 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2697 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2698 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2699 .features[FEAT_8000_0001_EDX] =
2700 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2701 CPUID_EXT2_SYSCALL,
2702 .features[FEAT_8000_0001_ECX] =
2703 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2704 .features[FEAT_7_0_EBX] =
2705 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2706 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2707 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2708 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2709 CPUID_7_0_EBX_SMAP,
2710 .features[FEAT_XSAVE] =
2711 CPUID_XSAVE_XSAVEOPT,
2712 .features[FEAT_6_EAX] =
2713 CPUID_6_EAX_ARAT,
2714 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2715 MSR_VMX_BASIC_TRUE_CTLS,
2716 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2717 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2718 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2719 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2720 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2721 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2722 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2723 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2724 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2725 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2726 .features[FEAT_VMX_EXIT_CTLS] =
2727 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2728 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2729 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2730 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2731 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2732 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2733 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2734 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2735 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2736 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2737 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2738 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2739 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2740 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2741 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2742 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2743 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2744 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2745 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2746 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2747 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2748 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2749 .features[FEAT_VMX_SECONDARY_CTLS] =
2750 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2751 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2752 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2753 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2754 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2755 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2756 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2757 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2758 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2759 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2760 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2761 .xlevel = 0x80000008,
2762 .model_id = "Intel Core Processor (Broadwell)",
2763 .versions = (X86CPUVersionDefinition[]) {
2764 { .version = 1 },
2765 {
2766 .version = 2,
2767 .alias = "Broadwell-noTSX",
2768 .props = (PropValue[]) {
2769 { "hle", "off" },
2770 { "rtm", "off" },
2771 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2772 { /* end of list */ }
2773 },
2774 },
2775 {
2776 .version = 3,
2777 .alias = "Broadwell-IBRS",
2778 .props = (PropValue[]) {
2779 /* Restore TSX features removed by -v2 above */
2780 { "hle", "on" },
2781 { "rtm", "on" },
2782 { "spec-ctrl", "on" },
2783 { "model-id",
2784 "Intel Core Processor (Broadwell, IBRS)" },
2785 { /* end of list */ }
2786 }
2787 },
2788 {
2789 .version = 4,
2790 .alias = "Broadwell-noTSX-IBRS",
2791 .props = (PropValue[]) {
2792 { "hle", "off" },
2793 { "rtm", "off" },
2794 /* spec-ctrl was already enabled by -v3 above */
2795 { "model-id",
2796 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2797 { /* end of list */ }
2798 }
2799 },
2800 { /* end of list */ }
2801 }
2802 },
2803 {
2804 .name = "Skylake-Client",
2805 .level = 0xd,
2806 .vendor = CPUID_VENDOR_INTEL,
2807 .family = 6,
2808 .model = 94,
2809 .stepping = 3,
2810 .features[FEAT_1_EDX] =
2811 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2812 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2813 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2814 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2815 CPUID_DE | CPUID_FP87,
2816 .features[FEAT_1_ECX] =
2817 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2818 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2819 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2820 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2821 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2822 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2823 .features[FEAT_8000_0001_EDX] =
2824 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2825 CPUID_EXT2_SYSCALL,
2826 .features[FEAT_8000_0001_ECX] =
2827 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2828 .features[FEAT_7_0_EBX] =
2829 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2830 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2831 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2832 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2833 CPUID_7_0_EBX_SMAP,
2834 /* Missing: XSAVES (not supported by some Linux versions,
2835 * including v4.1 to v4.12).
2836 * KVM doesn't yet expose any XSAVES state save component,
2837 * and the only one defined in Skylake (processor tracing)
2838 * probably will block migration anyway.
2839 */
2840 .features[FEAT_XSAVE] =
2841 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2842 CPUID_XSAVE_XGETBV1,
2843 .features[FEAT_6_EAX] =
2844 CPUID_6_EAX_ARAT,
2845 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2846 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2847 MSR_VMX_BASIC_TRUE_CTLS,
2848 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2849 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2850 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2851 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2852 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2853 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2854 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2855 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2856 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2857 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2858 .features[FEAT_VMX_EXIT_CTLS] =
2859 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2860 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2861 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2862 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2863 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2864 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2865 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2866 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2867 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2868 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2869 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2870 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2871 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2872 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2873 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2874 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2875 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2876 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2877 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2878 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2879 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2880 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2881 .features[FEAT_VMX_SECONDARY_CTLS] =
2882 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2883 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2884 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2885 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2886 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2887 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2888 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2889 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2890 .xlevel = 0x80000008,
2891 .model_id = "Intel Core Processor (Skylake)",
2892 .versions = (X86CPUVersionDefinition[]) {
2893 { .version = 1 },
2894 {
2895 .version = 2,
2896 .alias = "Skylake-Client-IBRS",
2897 .props = (PropValue[]) {
2898 { "spec-ctrl", "on" },
2899 { "model-id",
2900 "Intel Core Processor (Skylake, IBRS)" },
2901 { /* end of list */ }
2902 }
2903 },
2904 {
2905 .version = 3,
2906 .alias = "Skylake-Client-noTSX-IBRS",
2907 .props = (PropValue[]) {
2908 { "hle", "off" },
2909 { "rtm", "off" },
2910 { "model-id",
2911 "Intel Core Processor (Skylake, IBRS, no TSX)" },
2912 { /* end of list */ }
2913 }
2914 },
2915 { /* end of list */ }
2916 }
2917 },
2918 {
2919 .name = "Skylake-Server",
2920 .level = 0xd,
2921 .vendor = CPUID_VENDOR_INTEL,
2922 .family = 6,
2923 .model = 85,
2924 .stepping = 4,
2925 .features[FEAT_1_EDX] =
2926 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2927 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2928 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2929 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2930 CPUID_DE | CPUID_FP87,
2931 .features[FEAT_1_ECX] =
2932 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2933 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2934 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2935 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2936 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2937 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2938 .features[FEAT_8000_0001_EDX] =
2939 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2940 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2941 .features[FEAT_8000_0001_ECX] =
2942 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2943 .features[FEAT_7_0_EBX] =
2944 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2945 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2946 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2947 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2948 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2949 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2950 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2951 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2952 .features[FEAT_7_0_ECX] =
2953 CPUID_7_0_ECX_PKU,
2954 /* Missing: XSAVES (not supported by some Linux versions,
2955 * including v4.1 to v4.12).
2956 * KVM doesn't yet expose any XSAVES state save component,
2957 * and the only one defined in Skylake (processor tracing)
2958 * probably will block migration anyway.
2959 */
2960 .features[FEAT_XSAVE] =
2961 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2962 CPUID_XSAVE_XGETBV1,
2963 .features[FEAT_6_EAX] =
2964 CPUID_6_EAX_ARAT,
2965 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2966 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2967 MSR_VMX_BASIC_TRUE_CTLS,
2968 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2969 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2970 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2971 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2972 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2973 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2974 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2975 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2976 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2977 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2978 .features[FEAT_VMX_EXIT_CTLS] =
2979 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2980 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2981 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2982 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2983 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2984 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2985 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2986 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2987 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2988 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2989 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2990 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2991 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2992 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2993 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2994 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2995 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2996 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2997 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2998 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2999 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3000 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3001 .features[FEAT_VMX_SECONDARY_CTLS] =
3002 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3003 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3004 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3005 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3006 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3007 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3008 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3009 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3010 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3011 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3012 .xlevel = 0x80000008,
3013 .model_id = "Intel Xeon Processor (Skylake)",
3014 .versions = (X86CPUVersionDefinition[]) {
3015 { .version = 1 },
3016 {
3017 .version = 2,
3018 .alias = "Skylake-Server-IBRS",
3019 .props = (PropValue[]) {
3020 /* clflushopt was not added to Skylake-Server-IBRS */
3021 /* TODO: add -v3 including clflushopt */
3022 { "clflushopt", "off" },
3023 { "spec-ctrl", "on" },
3024 { "model-id",
3025 "Intel Xeon Processor (Skylake, IBRS)" },
3026 { /* end of list */ }
3027 }
3028 },
3029 {
3030 .version = 3,
3031 .alias = "Skylake-Server-noTSX-IBRS",
3032 .props = (PropValue[]) {
3033 { "hle", "off" },
3034 { "rtm", "off" },
3035 { "model-id",
3036 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
3037 { /* end of list */ }
3038 }
3039 },
3040 { /* end of list */ }
3041 }
3042 },
3043 {
3044 .name = "Cascadelake-Server",
3045 .level = 0xd,
3046 .vendor = CPUID_VENDOR_INTEL,
3047 .family = 6,
3048 .model = 85,
3049 .stepping = 6,
3050 .features[FEAT_1_EDX] =
3051 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3052 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3053 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3054 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3055 CPUID_DE | CPUID_FP87,
3056 .features[FEAT_1_ECX] =
3057 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3058 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3059 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3060 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3061 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3062 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3063 .features[FEAT_8000_0001_EDX] =
3064 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3065 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3066 .features[FEAT_8000_0001_ECX] =
3067 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3068 .features[FEAT_7_0_EBX] =
3069 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3070 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3071 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3072 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3073 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3074 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3075 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3076 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3077 .features[FEAT_7_0_ECX] =
3078 CPUID_7_0_ECX_PKU |
3079 CPUID_7_0_ECX_AVX512VNNI,
3080 .features[FEAT_7_0_EDX] =
3081 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3082 /* Missing: XSAVES (not supported by some Linux versions,
3083 * including v4.1 to v4.12).
3084 * KVM doesn't yet expose any XSAVES state save component,
3085 * and the only one defined in Skylake (processor tracing)
3086 * probably will block migration anyway.
3087 */
3088 .features[FEAT_XSAVE] =
3089 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3090 CPUID_XSAVE_XGETBV1,
3091 .features[FEAT_6_EAX] =
3092 CPUID_6_EAX_ARAT,
3093 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3094 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3095 MSR_VMX_BASIC_TRUE_CTLS,
3096 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3097 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3098 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3099 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3100 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3101 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3102 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3103 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3104 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3105 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3106 .features[FEAT_VMX_EXIT_CTLS] =
3107 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3108 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3109 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3110 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3111 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3112 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3113 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3114 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3115 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3116 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3117 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3118 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3119 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3120 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3121 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3122 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3123 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3124 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3125 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3126 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3127 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3128 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3129 .features[FEAT_VMX_SECONDARY_CTLS] =
3130 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3131 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3132 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3133 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3134 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3135 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3136 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3137 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3138 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3139 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3140 .xlevel = 0x80000008,
3141 .model_id = "Intel Xeon Processor (Cascadelake)",
3142 .versions = (X86CPUVersionDefinition[]) {
3143 { .version = 1 },
3144 { .version = 2,
3145 .props = (PropValue[]) {
3146 { "arch-capabilities", "on" },
3147 { "rdctl-no", "on" },
3148 { "ibrs-all", "on" },
3149 { "skip-l1dfl-vmentry", "on" },
3150 { "mds-no", "on" },
3151 { /* end of list */ }
3152 },
3153 },
3154 { .version = 3,
3155 .alias = "Cascadelake-Server-noTSX",
3156 .props = (PropValue[]) {
3157 { "hle", "off" },
3158 { "rtm", "off" },
3159 { /* end of list */ }
3160 },
3161 },
3162 { /* end of list */ }
3163 }
3164 },
3165 {
3166 .name = "Cooperlake",
3167 .level = 0xd,
3168 .vendor = CPUID_VENDOR_INTEL,
3169 .family = 6,
3170 .model = 85,
3171 .stepping = 10,
3172 .features[FEAT_1_EDX] =
3173 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3174 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3175 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3176 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3177 CPUID_DE | CPUID_FP87,
3178 .features[FEAT_1_ECX] =
3179 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3180 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3181 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3182 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3183 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3184 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3185 .features[FEAT_8000_0001_EDX] =
3186 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3187 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3188 .features[FEAT_8000_0001_ECX] =
3189 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3190 .features[FEAT_7_0_EBX] =
3191 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3192 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3193 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3194 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3195 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3196 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3197 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3198 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3199 .features[FEAT_7_0_ECX] =
3200 CPUID_7_0_ECX_PKU |
3201 CPUID_7_0_ECX_AVX512VNNI,
3202 .features[FEAT_7_0_EDX] =
3203 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3204 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3205 .features[FEAT_ARCH_CAPABILITIES] =
3206 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
3207 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3208 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
3209 .features[FEAT_7_1_EAX] =
3210 CPUID_7_1_EAX_AVX512_BF16,
3211 /*
3212 * Missing: XSAVES (not supported by some Linux versions,
3213 * including v4.1 to v4.12).
3214 * KVM doesn't yet expose any XSAVES state save component,
3215 * and the only one defined in Skylake (processor tracing)
3216 * probably will block migration anyway.
3217 */
3218 .features[FEAT_XSAVE] =
3219 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3220 CPUID_XSAVE_XGETBV1,
3221 .features[FEAT_6_EAX] =
3222 CPUID_6_EAX_ARAT,
3223 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3224 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3225 MSR_VMX_BASIC_TRUE_CTLS,
3226 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3227 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3228 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3229 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3230 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3231 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3232 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3233 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3234 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3235 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3236 .features[FEAT_VMX_EXIT_CTLS] =
3237 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3238 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3239 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3240 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3241 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3242 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3243 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3244 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3245 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3246 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3247 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3248 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3249 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3250 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3251 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3252 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3253 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3254 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3255 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3256 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3257 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3258 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3259 .features[FEAT_VMX_SECONDARY_CTLS] =
3260 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3261 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3262 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3263 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3264 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3265 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3266 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3267 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3268 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3269 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3270 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3271 .xlevel = 0x80000008,
3272 .model_id = "Intel Xeon Processor (Cooperlake)",
3273 },
3274 {
3275 .name = "Icelake-Client",
3276 .level = 0xd,
3277 .vendor = CPUID_VENDOR_INTEL,
3278 .family = 6,
3279 .model = 126,
3280 .stepping = 0,
3281 .features[FEAT_1_EDX] =
3282 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3283 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3284 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3285 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3286 CPUID_DE | CPUID_FP87,
3287 .features[FEAT_1_ECX] =
3288 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3289 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3290 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3291 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3292 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3293 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3294 .features[FEAT_8000_0001_EDX] =
3295 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3296 CPUID_EXT2_SYSCALL,
3297 .features[FEAT_8000_0001_ECX] =
3298 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3299 .features[FEAT_8000_0008_EBX] =
3300 CPUID_8000_0008_EBX_WBNOINVD,
3301 .features[FEAT_7_0_EBX] =
3302 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3303 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3304 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3305 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3306 CPUID_7_0_EBX_SMAP,
3307 .features[FEAT_7_0_ECX] =
3308 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3309 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3310 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3311 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3312 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3313 .features[FEAT_7_0_EDX] =
3314 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3315 /* Missing: XSAVES (not supported by some Linux versions,
3316 * including v4.1 to v4.12).
3317 * KVM doesn't yet expose any XSAVES state save component,
3318 * and the only one defined in Skylake (processor tracing)
3319 * probably will block migration anyway.
3320 */
3321 .features[FEAT_XSAVE] =
3322 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3323 CPUID_XSAVE_XGETBV1,
3324 .features[FEAT_6_EAX] =
3325 CPUID_6_EAX_ARAT,
3326 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3327 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3328 MSR_VMX_BASIC_TRUE_CTLS,
3329 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3330 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3331 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3332 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3333 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3334 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3335 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3336 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3337 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3338 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3339 .features[FEAT_VMX_EXIT_CTLS] =
3340 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3341 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3342 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3343 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3344 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3345 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3346 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3347 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3348 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3349 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3350 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3351 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3352 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3353 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3354 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3355 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3356 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3357 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3358 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3359 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3360 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3361 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3362 .features[FEAT_VMX_SECONDARY_CTLS] =
3363 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3364 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3365 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3366 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3367 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3368 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3369 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3370 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3371 .xlevel = 0x80000008,
3372 .model_id = "Intel Core Processor (Icelake)",
3373 .versions = (X86CPUVersionDefinition[]) {
3374 { .version = 1 },
3375 {
3376 .version = 2,
3377 .alias = "Icelake-Client-noTSX",
3378 .props = (PropValue[]) {
3379 { "hle", "off" },
3380 { "rtm", "off" },
3381 { /* end of list */ }
3382 },
3383 },
3384 { /* end of list */ }
3385 }
3386 },
3387 {
3388 .name = "Icelake-Server",
3389 .level = 0xd,
3390 .vendor = CPUID_VENDOR_INTEL,
3391 .family = 6,
3392 .model = 134,
3393 .stepping = 0,
3394 .features[FEAT_1_EDX] =
3395 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3396 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3397 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3398 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3399 CPUID_DE | CPUID_FP87,
3400 .features[FEAT_1_ECX] =
3401 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3402 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3403 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3404 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3405 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3406 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3407 .features[FEAT_8000_0001_EDX] =
3408 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3409 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3410 .features[FEAT_8000_0001_ECX] =
3411 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3412 .features[FEAT_8000_0008_EBX] =
3413 CPUID_8000_0008_EBX_WBNOINVD,
3414 .features[FEAT_7_0_EBX] =
3415 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3416 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3417 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3418 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3419 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3420 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3421 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3422 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3423 .features[FEAT_7_0_ECX] =
3424 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3425 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3426 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3427 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3428 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3429 .features[FEAT_7_0_EDX] =
3430 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3431 /* Missing: XSAVES (not supported by some Linux versions,
3432 * including v4.1 to v4.12).
3433 * KVM doesn't yet expose any XSAVES state save component,
3434 * and the only one defined in Skylake (processor tracing)
3435 * probably will block migration anyway.
3436 */
3437 .features[FEAT_XSAVE] =
3438 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3439 CPUID_XSAVE_XGETBV1,
3440 .features[FEAT_6_EAX] =
3441 CPUID_6_EAX_ARAT,
3442 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3443 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3444 MSR_VMX_BASIC_TRUE_CTLS,
3445 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3446 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3447 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3448 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3449 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3450 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3451 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3452 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3453 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3454 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3455 .features[FEAT_VMX_EXIT_CTLS] =
3456 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3457 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3458 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3459 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3460 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3461 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3462 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3463 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3464 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3465 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3466 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3467 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3468 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3469 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3470 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3471 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3472 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3473 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3474 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3475 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3476 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3477 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3478 .features[FEAT_VMX_SECONDARY_CTLS] =
3479 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3480 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3481 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3482 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3483 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3484 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3485 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3486 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3487 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
3488 .xlevel = 0x80000008,
3489 .model_id = "Intel Xeon Processor (Icelake)",
3490 .versions = (X86CPUVersionDefinition[]) {
3491 { .version = 1 },
3492 {
3493 .version = 2,
3494 .alias = "Icelake-Server-noTSX",
3495 .props = (PropValue[]) {
3496 { "hle", "off" },
3497 { "rtm", "off" },
3498 { /* end of list */ }
3499 },
3500 },
3501 { /* end of list */ }
3502 }
3503 },
3504 {
3505 .name = "Denverton",
3506 .level = 21,
3507 .vendor = CPUID_VENDOR_INTEL,
3508 .family = 6,
3509 .model = 95,
3510 .stepping = 1,
3511 .features[FEAT_1_EDX] =
3512 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3513 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3514 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3515 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3516 CPUID_SSE | CPUID_SSE2,
3517 .features[FEAT_1_ECX] =
3518 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3519 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3520 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3521 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3522 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3523 .features[FEAT_8000_0001_EDX] =
3524 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3525 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3526 .features[FEAT_8000_0001_ECX] =
3527 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3528 .features[FEAT_7_0_EBX] =
3529 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3530 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3531 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3532 .features[FEAT_7_0_EDX] =
3533 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3534 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3535 /*
3536 * Missing: XSAVES (not supported by some Linux versions,
3537 * including v4.1 to v4.12).
3538 * KVM doesn't yet expose any XSAVES state save component,
3539 * and the only one defined in Skylake (processor tracing)
3540 * probably will block migration anyway.
3541 */
3542 .features[FEAT_XSAVE] =
3543 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3544 .features[FEAT_6_EAX] =
3545 CPUID_6_EAX_ARAT,
3546 .features[FEAT_ARCH_CAPABILITIES] =
3547 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
3548 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3549 MSR_VMX_BASIC_TRUE_CTLS,
3550 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3551 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3552 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3553 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3554 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3555 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3556 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3557 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3558 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3559 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3560 .features[FEAT_VMX_EXIT_CTLS] =
3561 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3562 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3563 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3564 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3565 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3566 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3567 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3568 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3569 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3570 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3571 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3572 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3573 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3574 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3575 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3576 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3577 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3578 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3579 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3580 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3581 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3582 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3583 .features[FEAT_VMX_SECONDARY_CTLS] =
3584 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3585 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3586 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3587 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3588 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3589 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3590 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3591 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3592 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3593 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3594 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3595 .xlevel = 0x80000008,
3596 .model_id = "Intel Atom Processor (Denverton)",
3597 .versions = (X86CPUVersionDefinition[]) {
3598 { .version = 1 },
3599 {
3600 .version = 2,
3601 .props = (PropValue[]) {
3602 { "monitor", "off" },
3603 { "mpx", "off" },
3604 { /* end of list */ },
3605 },
3606 },
3607 { /* end of list */ },
3608 },
3609 },
3610 {
3611 .name = "Snowridge",
3612 .level = 27,
3613 .vendor = CPUID_VENDOR_INTEL,
3614 .family = 6,
3615 .model = 134,
3616 .stepping = 1,
3617 .features[FEAT_1_EDX] =
3618 /* missing: CPUID_PN CPUID_IA64 */
3619 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3620 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3621 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3622 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3623 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3624 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3625 CPUID_MMX |
3626 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3627 .features[FEAT_1_ECX] =
3628 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3629 CPUID_EXT_SSSE3 |
3630 CPUID_EXT_CX16 |
3631 CPUID_EXT_SSE41 |
3632 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3633 CPUID_EXT_POPCNT |
3634 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3635 CPUID_EXT_RDRAND,
3636 .features[FEAT_8000_0001_EDX] =
3637 CPUID_EXT2_SYSCALL |
3638 CPUID_EXT2_NX |
3639 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3640 CPUID_EXT2_LM,
3641 .features[FEAT_8000_0001_ECX] =
3642 CPUID_EXT3_LAHF_LM |
3643 CPUID_EXT3_3DNOWPREFETCH,
3644 .features[FEAT_7_0_EBX] =
3645 CPUID_7_0_EBX_FSGSBASE |
3646 CPUID_7_0_EBX_SMEP |
3647 CPUID_7_0_EBX_ERMS |
3648 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
3649 CPUID_7_0_EBX_RDSEED |
3650 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3651 CPUID_7_0_EBX_CLWB |
3652 CPUID_7_0_EBX_SHA_NI,
3653 .features[FEAT_7_0_ECX] =
3654 CPUID_7_0_ECX_UMIP |
3655 /* missing bit 5 */
3656 CPUID_7_0_ECX_GFNI |
3657 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3658 CPUID_7_0_ECX_MOVDIR64B,
3659 .features[FEAT_7_0_EDX] =
3660 CPUID_7_0_EDX_SPEC_CTRL |
3661 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3662 CPUID_7_0_EDX_CORE_CAPABILITY,
3663 .features[FEAT_CORE_CAPABILITY] =
3664 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
3665 /*
3666 * Missing: XSAVES (not supported by some Linux versions,
3667 * including v4.1 to v4.12).
3668 * KVM doesn't yet expose any XSAVES state save component,
3669 * and the only one defined in Skylake (processor tracing)
3670 * probably will block migration anyway.
3671 */
3672 .features[FEAT_XSAVE] =
3673 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3674 CPUID_XSAVE_XGETBV1,
3675 .features[FEAT_6_EAX] =
3676 CPUID_6_EAX_ARAT,
3677 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3678 MSR_VMX_BASIC_TRUE_CTLS,
3679 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3680 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3681 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3682 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3683 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3684 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3685 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3686 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3687 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3688 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3689 .features[FEAT_VMX_EXIT_CTLS] =
3690 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3691 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3692 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3693 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3694 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3695 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3696 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3697 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3698 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3699 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3700 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3701 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3702 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3703 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3704 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3705 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3706 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3707 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3708 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3709 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3710 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3711 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3712 .features[FEAT_VMX_SECONDARY_CTLS] =
3713 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3714 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3715 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3716 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3717 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3718 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3719 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3720 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3721 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3722 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3723 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3724 .xlevel = 0x80000008,
3725 .model_id = "Intel Atom Processor (SnowRidge)",
3726 .versions = (X86CPUVersionDefinition[]) {
3727 { .version = 1 },
3728 {
3729 .version = 2,
3730 .props = (PropValue[]) {
3731 { "mpx", "off" },
3732 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3733 { /* end of list */ },
3734 },
3735 },
3736 { /* end of list */ },
3737 },
3738 },
3739 {
3740 .name = "KnightsMill",
3741 .level = 0xd,
3742 .vendor = CPUID_VENDOR_INTEL,
3743 .family = 6,
3744 .model = 133,
3745 .stepping = 0,
3746 .features[FEAT_1_EDX] =
3747 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3748 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3749 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3750 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3751 CPUID_PSE | CPUID_DE | CPUID_FP87,
3752 .features[FEAT_1_ECX] =
3753 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3754 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3755 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3756 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3757 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3758 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3759 .features[FEAT_8000_0001_EDX] =
3760 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3761 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3762 .features[FEAT_8000_0001_ECX] =
3763 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3764 .features[FEAT_7_0_EBX] =
3765 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3766 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3767 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3768 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3769 CPUID_7_0_EBX_AVX512ER,
3770 .features[FEAT_7_0_ECX] =
3771 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3772 .features[FEAT_7_0_EDX] =
3773 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3774 .features[FEAT_XSAVE] =
3775 CPUID_XSAVE_XSAVEOPT,
3776 .features[FEAT_6_EAX] =
3777 CPUID_6_EAX_ARAT,
3778 .xlevel = 0x80000008,
3779 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3780 },
3781 {
3782 .name = "Opteron_G1",
3783 .level = 5,
3784 .vendor = CPUID_VENDOR_AMD,
3785 .family = 15,
3786 .model = 6,
3787 .stepping = 1,
3788 .features[FEAT_1_EDX] =
3789 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3790 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3791 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3792 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3793 CPUID_DE | CPUID_FP87,
3794 .features[FEAT_1_ECX] =
3795 CPUID_EXT_SSE3,
3796 .features[FEAT_8000_0001_EDX] =
3797 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3798 .xlevel = 0x80000008,
3799 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3800 },
3801 {
3802 .name = "Opteron_G2",
3803 .level = 5,
3804 .vendor = CPUID_VENDOR_AMD,
3805 .family = 15,
3806 .model = 6,
3807 .stepping = 1,
3808 .features[FEAT_1_EDX] =
3809 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3810 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3811 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3812 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3813 CPUID_DE | CPUID_FP87,
3814 .features[FEAT_1_ECX] =
3815 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
3816 .features[FEAT_8000_0001_EDX] =
3817 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3818 .features[FEAT_8000_0001_ECX] =
3819 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3820 .xlevel = 0x80000008,
3821 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3822 },
3823 {
3824 .name = "Opteron_G3",
3825 .level = 5,
3826 .vendor = CPUID_VENDOR_AMD,
3827 .family = 16,
3828 .model = 2,
3829 .stepping = 3,
3830 .features[FEAT_1_EDX] =
3831 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3832 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3833 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3834 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3835 CPUID_DE | CPUID_FP87,
3836 .features[FEAT_1_ECX] =
3837 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3838 CPUID_EXT_SSE3,
3839 .features[FEAT_8000_0001_EDX] =
3840 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3841 CPUID_EXT2_RDTSCP,
3842 .features[FEAT_8000_0001_ECX] =
3843 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3844 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3845 .xlevel = 0x80000008,
3846 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3847 },
3848 {
3849 .name = "Opteron_G4",
3850 .level = 0xd,
3851 .vendor = CPUID_VENDOR_AMD,
3852 .family = 21,
3853 .model = 1,
3854 .stepping = 2,
3855 .features[FEAT_1_EDX] =
3856 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3857 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3858 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3859 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3860 CPUID_DE | CPUID_FP87,
3861 .features[FEAT_1_ECX] =
3862 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3863 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3864 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3865 CPUID_EXT_SSE3,
3866 .features[FEAT_8000_0001_EDX] =
3867 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3868 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3869 .features[FEAT_8000_0001_ECX] =
3870 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3871 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3872 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3873 CPUID_EXT3_LAHF_LM,
3874 .features[FEAT_SVM] =
3875 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3876 /* no xsaveopt! */
3877 .xlevel = 0x8000001A,
3878 .model_id = "AMD Opteron 62xx class CPU",
3879 },
3880 {
3881 .name = "Opteron_G5",
3882 .level = 0xd,
3883 .vendor = CPUID_VENDOR_AMD,
3884 .family = 21,
3885 .model = 2,
3886 .stepping = 0,
3887 .features[FEAT_1_EDX] =
3888 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3889 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3890 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3891 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3892 CPUID_DE | CPUID_FP87,
3893 .features[FEAT_1_ECX] =
3894 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
3895 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3896 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3897 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3898 .features[FEAT_8000_0001_EDX] =
3899 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3900 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3901 .features[FEAT_8000_0001_ECX] =
3902 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3903 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3904 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3905 CPUID_EXT3_LAHF_LM,
3906 .features[FEAT_SVM] =
3907 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3908 /* no xsaveopt! */
3909 .xlevel = 0x8000001A,
3910 .model_id = "AMD Opteron 63xx class CPU",
3911 },
3912 {
3913 .name = "EPYC",
3914 .level = 0xd,
3915 .vendor = CPUID_VENDOR_AMD,
3916 .family = 23,
3917 .model = 1,
3918 .stepping = 2,
3919 .features[FEAT_1_EDX] =
3920 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3921 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3922 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3923 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3924 CPUID_VME | CPUID_FP87,
3925 .features[FEAT_1_ECX] =
3926 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3927 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3928 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3929 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3930 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3931 .features[FEAT_8000_0001_EDX] =
3932 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3933 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3934 CPUID_EXT2_SYSCALL,
3935 .features[FEAT_8000_0001_ECX] =
3936 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3937 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
3938 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3939 CPUID_EXT3_TOPOEXT,
3940 .features[FEAT_7_0_EBX] =
3941 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3942 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3943 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3944 CPUID_7_0_EBX_SHA_NI,
3945 .features[FEAT_XSAVE] =
3946 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3947 CPUID_XSAVE_XGETBV1,
3948 .features[FEAT_6_EAX] =
3949 CPUID_6_EAX_ARAT,
3950 .features[FEAT_SVM] =
3951 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3952 .xlevel = 0x8000001E,
3953 .model_id = "AMD EPYC Processor",
3954 .cache_info = &epyc_cache_info,
3955 .versions = (X86CPUVersionDefinition[]) {
3956 { .version = 1 },
3957 {
3958 .version = 2,
3959 .alias = "EPYC-IBPB",
3960 .props = (PropValue[]) {
3961 { "ibpb", "on" },
3962 { "model-id",
3963 "AMD EPYC Processor (with IBPB)" },
3964 { /* end of list */ }
3965 }
3966 },
3967 {
3968 .version = 3,
3969 .props = (PropValue[]) {
3970 { "ibpb", "on" },
3971 { "perfctr-core", "on" },
3972 { "clzero", "on" },
3973 { "xsaveerptr", "on" },
3974 { "xsaves", "on" },
3975 { "model-id",
3976 "AMD EPYC Processor" },
3977 { /* end of list */ }
3978 }
3979 },
3980 { /* end of list */ }
3981 }
3982 },
3983 {
3984 .name = "Dhyana",
3985 .level = 0xd,
3986 .vendor = CPUID_VENDOR_HYGON,
3987 .family = 24,
3988 .model = 0,
3989 .stepping = 1,
3990 .features[FEAT_1_EDX] =
3991 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3992 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3993 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3994 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3995 CPUID_VME | CPUID_FP87,
3996 .features[FEAT_1_ECX] =
3997 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3998 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
3999 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4000 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4001 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
4002 .features[FEAT_8000_0001_EDX] =
4003 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4004 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4005 CPUID_EXT2_SYSCALL,
4006 .features[FEAT_8000_0001_ECX] =
4007 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4008 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4009 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4010 CPUID_EXT3_TOPOEXT,
4011 .features[FEAT_8000_0008_EBX] =
4012 CPUID_8000_0008_EBX_IBPB,
4013 .features[FEAT_7_0_EBX] =
4014 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4015 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4016 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
4017 /*
4018 * Missing: XSAVES (not supported by some Linux versions,
4019 * including v4.1 to v4.12).
4020 * KVM doesn't yet expose any XSAVES state save component.
4021 */
4022 .features[FEAT_XSAVE] =
4023 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4024 CPUID_XSAVE_XGETBV1,
4025 .features[FEAT_6_EAX] =
4026 CPUID_6_EAX_ARAT,
4027 .features[FEAT_SVM] =
4028 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4029 .xlevel = 0x8000001E,
4030 .model_id = "Hygon Dhyana Processor",
4031 .cache_info = &epyc_cache_info,
4032 },
4033 };
4034
4035 /* KVM-specific features that are automatically added/removed
4036 * from all CPU models when KVM is enabled.
4037 */
4038 static PropValue kvm_default_props[] = {
4039 { "kvmclock", "on" },
4040 { "kvm-nopiodelay", "on" },
4041 { "kvm-asyncpf", "on" },
4042 { "kvm-steal-time", "on" },
4043 { "kvm-pv-eoi", "on" },
4044 { "kvmclock-stable-bit", "on" },
4045 { "x2apic", "on" },
4046 { "acpi", "off" },
4047 { "monitor", "off" },
4048 { "svm", "off" },
4049 { NULL, NULL },
4050 };
4051
4052 /* TCG-specific defaults that override all CPU models when using TCG
4053 */
4054 static PropValue tcg_default_props[] = {
4055 { "vme", "off" },
4056 { NULL, NULL },
4057 };
4058
4059
4060 /*
4061 * We resolve CPU model aliases using -v1 when using "-machine
4062 * none", but this is just for compatibility while libvirt isn't
4063 * adapted to resolve CPU model versions before creating VMs.
4064 * See "Runnability guarantee of CPU models" at * qemu-deprecated.texi.
4065 */
4066 X86CPUVersion default_cpu_version = 1;
4067
4068 void x86_cpu_set_default_version(X86CPUVersion version)
4069 {
4070 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4071 assert(version != CPU_VERSION_AUTO);
4072 default_cpu_version = version;
4073 }
4074
4075 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4076 {
4077 int v = 0;
4078 const X86CPUVersionDefinition *vdef =
4079 x86_cpu_def_get_versions(model->cpudef);
4080 while (vdef->version) {
4081 v = vdef->version;
4082 vdef++;
4083 }
4084 return v;
4085 }
4086
4087 /* Return the actual version being used for a specific CPU model */
4088 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4089 {
4090 X86CPUVersion v = model->version;
4091 if (v == CPU_VERSION_AUTO) {
4092 v = default_cpu_version;
4093 }
4094 if (v == CPU_VERSION_LATEST) {
4095 return x86_cpu_model_last_version(model);
4096 }
4097 return v;
4098 }
4099
4100 void x86_cpu_change_kvm_default(const char *prop, const char *value)
4101 {
4102 PropValue *pv;
4103 for (pv = kvm_default_props; pv->prop; pv++) {
4104 if (!strcmp(pv->prop, prop)) {
4105 pv->value = value;
4106 break;
4107 }
4108 }
4109
4110 /* It is valid to call this function only for properties that
4111 * are already present in the kvm_default_props table.
4112 */
4113 assert(pv->prop);
4114 }
4115
4116 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
4117 bool migratable_only);
4118
4119 static bool lmce_supported(void)
4120 {
4121 uint64_t mce_cap = 0;
4122
4123 #ifdef CONFIG_KVM
4124 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
4125 return false;
4126 }
4127 #endif
4128
4129 return !!(mce_cap & MCG_LMCE_P);
4130 }
4131
4132 #define CPUID_MODEL_ID_SZ 48
4133
4134 /**
4135 * cpu_x86_fill_model_id:
4136 * Get CPUID model ID string from host CPU.
4137 *
4138 * @str should have at least CPUID_MODEL_ID_SZ bytes
4139 *
4140 * The function does NOT add a null terminator to the string
4141 * automatically.
4142 */
4143 static int cpu_x86_fill_model_id(char *str)
4144 {
4145 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
4146 int i;
4147
4148 for (i = 0; i < 3; i++) {
4149 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
4150 memcpy(str + i * 16 + 0, &eax, 4);
4151 memcpy(str + i * 16 + 4, &ebx, 4);
4152 memcpy(str + i * 16 + 8, &ecx, 4);
4153 memcpy(str + i * 16 + 12, &edx, 4);
4154 }
4155 return 0;
4156 }
4157
4158 static Property max_x86_cpu_properties[] = {
4159 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
4160 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
4161 DEFINE_PROP_END_OF_LIST()
4162 };
4163
4164 static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
4165 {
4166 DeviceClass *dc = DEVICE_CLASS(oc);
4167 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4168
4169 xcc->ordering = 9;
4170
4171 xcc->model_description =
4172 "Enables all features supported by the accelerator in the current host";
4173
4174 device_class_set_props(dc, max_x86_cpu_properties);
4175 }
4176
4177 static void max_x86_cpu_initfn(Object *obj)
4178 {
4179 X86CPU *cpu = X86_CPU(obj);
4180 CPUX86State *env = &cpu->env;
4181 KVMState *s = kvm_state;
4182
4183 /* We can't fill the features array here because we don't know yet if
4184 * "migratable" is true or false.
4185 */
4186 cpu->max_features = true;
4187
4188 if (accel_uses_host_cpuid()) {
4189 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
4190 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
4191 int family, model, stepping;
4192
4193 host_vendor_fms(vendor, &family, &model, &stepping);
4194 cpu_x86_fill_model_id(model_id);
4195
4196 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
4197 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
4198 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
4199 object_property_set_int(OBJECT(cpu), stepping, "stepping",
4200 &error_abort);
4201 object_property_set_str(OBJECT(cpu), model_id, "model-id",
4202 &error_abort);
4203
4204 if (kvm_enabled()) {
4205 env->cpuid_min_level =
4206 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
4207 env->cpuid_min_xlevel =
4208 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
4209 env->cpuid_min_xlevel2 =
4210 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
4211 } else {
4212 env->cpuid_min_level =
4213 hvf_get_supported_cpuid(0x0, 0, R_EAX);
4214 env->cpuid_min_xlevel =
4215 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
4216 env->cpuid_min_xlevel2 =
4217 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
4218 }
4219
4220 if (lmce_supported()) {
4221 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
4222 }
4223 } else {
4224 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
4225 "vendor", &error_abort);
4226 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
4227 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
4228 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
4229 object_property_set_str(OBJECT(cpu),
4230 "QEMU TCG CPU version " QEMU_HW_VERSION,
4231 "model-id", &error_abort);
4232 }
4233
4234 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
4235 }
4236
4237 static const TypeInfo max_x86_cpu_type_info = {
4238 .name = X86_CPU_TYPE_NAME("max"),
4239 .parent = TYPE_X86_CPU,
4240 .instance_init = max_x86_cpu_initfn,
4241 .class_init = max_x86_cpu_class_init,
4242 };
4243
4244 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
4245 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
4246 {
4247 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4248
4249 xcc->host_cpuid_required = true;
4250 xcc->ordering = 8;
4251
4252 #if defined(CONFIG_KVM)
4253 xcc->model_description =
4254 "KVM processor with all supported host features ";
4255 #elif defined(CONFIG_HVF)
4256 xcc->model_description =
4257 "HVF processor with all supported host features ";
4258 #endif
4259 }
4260
4261 static const TypeInfo host_x86_cpu_type_info = {
4262 .name = X86_CPU_TYPE_NAME("host"),
4263 .parent = X86_CPU_TYPE_NAME("max"),
4264 .class_init = host_x86_cpu_class_init,
4265 };
4266
4267 #endif
4268
4269 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4270 {
4271 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4272
4273 switch (f->type) {
4274 case CPUID_FEATURE_WORD:
4275 {
4276 const char *reg = get_register_name_32(f->cpuid.reg);
4277 assert(reg);
4278 return g_strdup_printf("CPUID.%02XH:%s",
4279 f->cpuid.eax, reg);
4280 }
4281 case MSR_FEATURE_WORD:
4282 return g_strdup_printf("MSR(%02XH)",
4283 f->msr.index);
4284 }
4285
4286 return NULL;
4287 }
4288
4289 static bool x86_cpu_have_filtered_features(X86CPU *cpu)
4290 {
4291 FeatureWord w;
4292
4293 for (w = 0; w < FEATURE_WORDS; w++) {
4294 if (cpu->filtered_features[w]) {
4295 return true;
4296 }
4297 }
4298
4299 return false;
4300 }
4301
4302 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
4303 const char *verbose_prefix)
4304 {
4305 CPUX86State *env = &cpu->env;
4306 FeatureWordInfo *f = &feature_word_info[w];
4307 int i;
4308
4309 if (!cpu->force_features) {
4310 env->features[w] &= ~mask;
4311 }
4312 cpu->filtered_features[w] |= mask;
4313
4314 if (!verbose_prefix) {
4315 return;
4316 }
4317
4318 for (i = 0; i < 64; ++i) {
4319 if ((1ULL << i) & mask) {
4320 g_autofree char *feat_word_str = feature_word_description(f, i);
4321 warn_report("%s: %s%s%s [bit %d]",
4322 verbose_prefix,
4323 feat_word_str,
4324 f->feat_names[i] ? "." : "",
4325 f->feat_names[i] ? f->feat_names[i] : "", i);
4326 }
4327 }
4328 }
4329
4330 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4331 const char *name, void *opaque,
4332 Error **errp)
4333 {
4334 X86CPU *cpu = X86_CPU(obj);
4335 CPUX86State *env = &cpu->env;
4336 int64_t value;
4337
4338 value = (env->cpuid_version >> 8) & 0xf;
4339 if (value == 0xf) {
4340 value += (env->cpuid_version >> 20) & 0xff;
4341 }
4342 visit_type_int(v, name, &value, errp);
4343 }
4344
4345 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4346 const char *name, void *opaque,
4347 Error **errp)
4348 {
4349 X86CPU *cpu = X86_CPU(obj);
4350 CPUX86State *env = &cpu->env;
4351 const int64_t min = 0;
4352 const int64_t max = 0xff + 0xf;
4353 Error *local_err = NULL;
4354 int64_t value;
4355
4356 visit_type_int(v, name, &value, &local_err);
4357 if (local_err) {
4358 error_propagate(errp, local_err);
4359 return;
4360 }
4361 if (value < min || value > max) {
4362 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4363 name ? name : "null", value, min, max);
4364 return;
4365 }
4366
4367 env->cpuid_version &= ~0xff00f00;
4368 if (value > 0x0f) {
4369 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
4370 } else {
4371 env->cpuid_version |= value << 8;
4372 }
4373 }
4374
4375 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4376 const char *name, void *opaque,
4377 Error **errp)
4378 {
4379 X86CPU *cpu = X86_CPU(obj);
4380 CPUX86State *env = &cpu->env;
4381 int64_t value;
4382
4383 value = (env->cpuid_version >> 4) & 0xf;
4384 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
4385 visit_type_int(v, name, &value, errp);
4386 }
4387
4388 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4389 const char *name, void *opaque,
4390 Error **errp)
4391 {
4392 X86CPU *cpu = X86_CPU(obj);
4393 CPUX86State *env = &cpu->env;
4394 const int64_t min = 0;
4395 const int64_t max = 0xff;
4396 Error *local_err = NULL;
4397 int64_t value;
4398
4399 visit_type_int(v, name, &value, &local_err);
4400 if (local_err) {
4401 error_propagate(errp, local_err);
4402 return;
4403 }
4404 if (value < min || value > max) {
4405 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4406 name ? name : "null", value, min, max);
4407 return;
4408 }
4409
4410 env->cpuid_version &= ~0xf00f0;
4411 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
4412 }
4413
4414 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
4415 const char *name, void *opaque,
4416 Error **errp)
4417 {
4418 X86CPU *cpu = X86_CPU(obj);
4419 CPUX86State *env = &cpu->env;
4420 int64_t value;
4421
4422 value = env->cpuid_version & 0xf;
4423 visit_type_int(v, name, &value, errp);
4424 }
4425
4426 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
4427 const char *name, void *opaque,
4428 Error **errp)
4429 {
4430 X86CPU *cpu = X86_CPU(obj);
4431 CPUX86State *env = &cpu->env;
4432 const int64_t min = 0;
4433 const int64_t max = 0xf;
4434 Error *local_err = NULL;
4435 int64_t value;
4436
4437 visit_type_int(v, name, &value, &local_err);
4438 if (local_err) {
4439 error_propagate(errp, local_err);
4440 return;
4441 }
4442 if (value < min || value > max) {
4443 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4444 name ? name : "null", value, min, max);
4445 return;
4446 }
4447
4448 env->cpuid_version &= ~0xf;
4449 env->cpuid_version |= value & 0xf;
4450 }
4451
4452 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4453 {
4454 X86CPU *cpu = X86_CPU(obj);
4455 CPUX86State *env = &cpu->env;
4456 char *value;
4457
4458 value = g_malloc(CPUID_VENDOR_SZ + 1);
4459 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4460 env->cpuid_vendor3);
4461 return value;
4462 }
4463
4464 static void x86_cpuid_set_vendor(Object *obj, const char *value,
4465 Error **errp)
4466 {
4467 X86CPU *cpu = X86_CPU(obj);
4468 CPUX86State *env = &cpu->env;
4469 int i;
4470
4471 if (strlen(value) != CPUID_VENDOR_SZ) {
4472 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
4473 return;
4474 }
4475
4476 env->cpuid_vendor1 = 0;
4477 env->cpuid_vendor2 = 0;
4478 env->cpuid_vendor3 = 0;
4479 for (i = 0; i < 4; i++) {
4480 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4481 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4482 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4483 }
4484 }
4485
4486 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4487 {
4488 X86CPU *cpu = X86_CPU(obj);
4489 CPUX86State *env = &cpu->env;
4490 char *value;
4491 int i;
4492
4493 value = g_malloc(48 + 1);
4494 for (i = 0; i < 48; i++) {
4495 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4496 }
4497 value[48] = '\0';
4498 return value;
4499 }
4500
4501 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4502 Error **errp)
4503 {
4504 X86CPU *cpu = X86_CPU(obj);
4505 CPUX86State *env = &cpu->env;
4506 int c, len, i;
4507
4508 if (model_id == NULL) {
4509 model_id = "";
4510 }
4511 len = strlen(model_id);
4512 memset(env->cpuid_model, 0, 48);
4513 for (i = 0; i < 48; i++) {
4514 if (i >= len) {
4515 c = '\0';
4516 } else {
4517 c = (uint8_t)model_id[i];
4518 }
4519 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4520 }
4521 }
4522
4523 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4524 void *opaque, Error **errp)
4525 {
4526 X86CPU *cpu = X86_CPU(obj);
4527 int64_t value;
4528
4529 value = cpu->env.tsc_khz * 1000;
4530 visit_type_int(v, name, &value, errp);
4531 }
4532
4533 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4534 void *opaque, Error **errp)
4535 {
4536 X86CPU *cpu = X86_CPU(obj);
4537 const int64_t min = 0;
4538 const int64_t max = INT64_MAX;
4539 Error *local_err = NULL;
4540 int64_t value;
4541
4542 visit_type_int(v, name, &value, &local_err);
4543 if (local_err) {
4544 error_propagate(errp, local_err);
4545 return;
4546 }
4547 if (value < min || value > max) {
4548 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4549 name ? name : "null", value, min, max);
4550 return;
4551 }
4552
4553 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
4554 }
4555
4556 /* Generic getter for "feature-words" and "filtered-features" properties */
4557 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4558 const char *name, void *opaque,
4559 Error **errp)
4560 {
4561 uint64_t *array = (uint64_t *)opaque;
4562 FeatureWord w;
4563 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4564 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4565 X86CPUFeatureWordInfoList *list = NULL;
4566
4567 for (w = 0; w < FEATURE_WORDS; w++) {
4568 FeatureWordInfo *wi = &feature_word_info[w];
4569 /*
4570 * We didn't have MSR features when "feature-words" was
4571 * introduced. Therefore skipped other type entries.
4572 */
4573 if (wi->type != CPUID_FEATURE_WORD) {
4574 continue;
4575 }
4576 X86CPUFeatureWordInfo *qwi = &word_infos[w];
4577 qwi->cpuid_input_eax = wi->cpuid.eax;
4578 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4579 qwi->cpuid_input_ecx = wi->cpuid.ecx;
4580 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
4581 qwi->features = array[w];
4582
4583 /* List will be in reverse order, but order shouldn't matter */
4584 list_entries[w].next = list;
4585 list_entries[w].value = &word_infos[w];
4586 list = &list_entries[w];
4587 }
4588
4589 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
4590 }
4591
4592 /* Convert all '_' in a feature string option name to '-', to make feature
4593 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4594 */
4595 static inline void feat2prop(char *s)
4596 {
4597 while ((s = strchr(s, '_'))) {
4598 *s = '-';
4599 }
4600 }
4601
4602 /* Return the feature property name for a feature flag bit */
4603 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4604 {
4605 const char *name;
4606 /* XSAVE components are automatically enabled by other features,
4607 * so return the original feature name instead
4608 */
4609 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4610 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4611
4612 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4613 x86_ext_save_areas[comp].bits) {
4614 w = x86_ext_save_areas[comp].feature;
4615 bitnr = ctz32(x86_ext_save_areas[comp].bits);
4616 }
4617 }
4618
4619 assert(bitnr < 64);
4620 assert(w < FEATURE_WORDS);
4621 name = feature_word_info[w].feat_names[bitnr];
4622 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4623 return name;
4624 }
4625
4626 /* Compatibily hack to maintain legacy +-feat semantic,
4627 * where +-feat overwrites any feature set by
4628 * feat=on|feat even if the later is parsed after +-feat
4629 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4630 */
4631 static GList *plus_features, *minus_features;
4632
4633 static gint compare_string(gconstpointer a, gconstpointer b)
4634 {
4635 return g_strcmp0(a, b);
4636 }
4637
4638 /* Parse "+feature,-feature,feature=foo" CPU feature string
4639 */
4640 static void x86_cpu_parse_featurestr(const char *typename, char *features,
4641 Error **errp)
4642 {
4643 char *featurestr; /* Single 'key=value" string being parsed */
4644 static bool cpu_globals_initialized;
4645 bool ambiguous = false;
4646
4647 if (cpu_globals_initialized) {
4648 return;
4649 }
4650 cpu_globals_initialized = true;
4651
4652 if (!features) {
4653 return;
4654 }
4655
4656 for (featurestr = strtok(features, ",");
4657 featurestr;
4658 featurestr = strtok(NULL, ",")) {
4659 const char *name;
4660 const char *val = NULL;
4661 char *eq = NULL;
4662 char num[32];
4663 GlobalProperty *prop;
4664
4665 /* Compatibility syntax: */
4666 if (featurestr[0] == '+') {
4667 plus_features = g_list_append(plus_features,
4668 g_strdup(featurestr + 1));
4669 continue;
4670 } else if (featurestr[0] == '-') {
4671 minus_features = g_list_append(minus_features,
4672 g_strdup(featurestr + 1));
4673 continue;
4674 }
4675
4676 eq = strchr(featurestr, '=');
4677 if (eq) {
4678 *eq++ = 0;
4679 val = eq;
4680 } else {
4681 val = "on";
4682 }
4683
4684 feat2prop(featurestr);
4685 name = featurestr;
4686
4687 if (g_list_find_custom(plus_features, name, compare_string)) {
4688 warn_report("Ambiguous CPU model string. "
4689 "Don't mix both \"+%s\" and \"%s=%s\"",
4690 name, name, val);
4691 ambiguous = true;
4692 }
4693 if (g_list_find_custom(minus_features, name, compare_string)) {
4694 warn_report("Ambiguous CPU model string. "
4695 "Don't mix both \"-%s\" and \"%s=%s\"",
4696 name, name, val);
4697 ambiguous = true;
4698 }
4699
4700 /* Special case: */
4701 if (!strcmp(name, "tsc-freq")) {
4702 int ret;
4703 uint64_t tsc_freq;
4704
4705 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
4706 if (ret < 0 || tsc_freq > INT64_MAX) {
4707 error_setg(errp, "bad numerical value %s", val);
4708 return;
4709 }
4710 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4711 val = num;
4712 name = "tsc-frequency";
4713 }
4714
4715 prop = g_new0(typeof(*prop), 1);
4716 prop->driver = typename;
4717 prop->property = g_strdup(name);
4718 prop->value = g_strdup(val);
4719 qdev_prop_register_global(prop);
4720 }
4721
4722 if (ambiguous) {
4723 warn_report("Compatibility of ambiguous CPU model "
4724 "strings won't be kept on future QEMU versions");
4725 }
4726 }
4727
4728 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
4729 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
4730
4731 /* Build a list with the name of all features on a feature word array */
4732 static void x86_cpu_list_feature_names(FeatureWordArray features,
4733 strList **feat_names)
4734 {
4735 FeatureWord w;
4736 strList **next = feat_names;
4737
4738 for (w = 0; w < FEATURE_WORDS; w++) {
4739 uint64_t filtered = features[w];
4740 int i;
4741 for (i = 0; i < 64; i++) {
4742 if (filtered & (1ULL << i)) {
4743 strList *new = g_new0(strList, 1);
4744 new->value = g_strdup(x86_cpu_feature_name(w, i));
4745 *next = new;
4746 next = &new->next;
4747 }
4748 }
4749 }
4750 }
4751
4752 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4753 const char *name, void *opaque,
4754 Error **errp)
4755 {
4756 X86CPU *xc = X86_CPU(obj);
4757 strList *result = NULL;
4758
4759 x86_cpu_list_feature_names(xc->filtered_features, &result);
4760 visit_type_strList(v, "unavailable-features", &result, errp);
4761 }
4762
4763 /* Check for missing features that may prevent the CPU class from
4764 * running using the current machine and accelerator.
4765 */
4766 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
4767 strList **missing_feats)
4768 {
4769 X86CPU *xc;
4770 Error *err = NULL;
4771 strList **next = missing_feats;
4772
4773 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
4774 strList *new = g_new0(strList, 1);
4775 new->value = g_strdup("kvm");
4776 *missing_feats = new;
4777 return;
4778 }
4779
4780 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
4781
4782 x86_cpu_expand_features(xc, &err);
4783 if (err) {
4784 /* Errors at x86_cpu_expand_features should never happen,
4785 * but in case it does, just report the model as not
4786 * runnable at all using the "type" property.
4787 */
4788 strList *new = g_new0(strList, 1);
4789 new->value = g_strdup("type");
4790 *next = new;
4791 next = &new->next;
4792 }
4793
4794 x86_cpu_filter_features(xc, false);
4795
4796 x86_cpu_list_feature_names(xc->filtered_features, next);
4797
4798 object_unref(OBJECT(xc));
4799 }
4800
4801 /* Print all cpuid feature names in featureset
4802 */
4803 static void listflags(GList *features)
4804 {
4805 size_t len = 0;
4806 GList *tmp;
4807
4808 for (tmp = features; tmp; tmp = tmp->next) {
4809 const char *name = tmp->data;
4810 if ((len + strlen(name) + 1) >= 75) {
4811 qemu_printf("\n");
4812 len = 0;
4813 }
4814 qemu_printf("%s%s", len == 0 ? " " : " ", name);
4815 len += strlen(name) + 1;
4816 }
4817 qemu_printf("\n");
4818 }
4819
4820 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
4821 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4822 {
4823 ObjectClass *class_a = (ObjectClass *)a;
4824 ObjectClass *class_b = (ObjectClass *)b;
4825 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4826 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
4827 int ret;
4828
4829 if (cc_a->ordering != cc_b->ordering) {
4830 ret = cc_a->ordering - cc_b->ordering;
4831 } else {
4832 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4833 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
4834 ret = strcmp(name_a, name_b);
4835 }
4836 return ret;
4837 }
4838
4839 static GSList *get_sorted_cpu_model_list(void)
4840 {
4841 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4842 list = g_slist_sort(list, x86_cpu_list_compare);
4843 return list;
4844 }
4845
4846 static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4847 {
4848 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
4849 char *r = object_property_get_str(obj, "model-id", &error_abort);
4850 object_unref(obj);
4851 return r;
4852 }
4853
4854 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4855 {
4856 X86CPUVersion version;
4857
4858 if (!cc->model || !cc->model->is_alias) {
4859 return NULL;
4860 }
4861 version = x86_cpu_model_resolve_version(cc->model);
4862 if (version <= 0) {
4863 return NULL;
4864 }
4865 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4866 }
4867
4868 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4869 {
4870 ObjectClass *oc = data;
4871 X86CPUClass *cc = X86_CPU_CLASS(oc);
4872 g_autofree char *name = x86_cpu_class_get_model_name(cc);
4873 g_autofree char *desc = g_strdup(cc->model_description);
4874 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
4875 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
4876
4877 if (!desc && alias_of) {
4878 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4879 desc = g_strdup("(alias configured by machine type)");
4880 } else {
4881 desc = g_strdup_printf("(alias of %s)", alias_of);
4882 }
4883 }
4884 if (!desc && cc->model && cc->model->note) {
4885 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4886 }
4887 if (!desc) {
4888 desc = g_strdup_printf("%s", model_id);
4889 }
4890
4891 qemu_printf("x86 %-20s %-58s\n", name, desc);
4892 }
4893
4894 /* list available CPU models and flags */
4895 void x86_cpu_list(void)
4896 {
4897 int i, j;
4898 GSList *list;
4899 GList *names = NULL;
4900
4901 qemu_printf("Available CPUs:\n");
4902 list = get_sorted_cpu_model_list();
4903 g_slist_foreach(list, x86_cpu_list_entry, NULL);
4904 g_slist_free(list);
4905
4906 names = NULL;
4907 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4908 FeatureWordInfo *fw = &feature_word_info[i];
4909 for (j = 0; j < 64; j++) {
4910 if (fw->feat_names[j]) {
4911 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4912 }
4913 }
4914 }
4915
4916 names = g_list_sort(names, (GCompareFunc)strcmp);
4917
4918 qemu_printf("\nRecognized CPUID flags:\n");
4919 listflags(names);
4920 qemu_printf("\n");
4921 g_list_free(names);
4922 }
4923
4924 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4925 {
4926 ObjectClass *oc = data;
4927 X86CPUClass *cc = X86_CPU_CLASS(oc);
4928 CpuDefinitionInfoList **cpu_list = user_data;
4929 CpuDefinitionInfoList *entry;
4930 CpuDefinitionInfo *info;
4931
4932 info = g_malloc0(sizeof(*info));
4933 info->name = x86_cpu_class_get_model_name(cc);
4934 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4935 info->has_unavailable_features = true;
4936 info->q_typename = g_strdup(object_class_get_name(oc));
4937 info->migration_safe = cc->migration_safe;
4938 info->has_migration_safe = true;
4939 info->q_static = cc->static_model;
4940 /*
4941 * Old machine types won't report aliases, so that alias translation
4942 * doesn't break compatibility with previous QEMU versions.
4943 */
4944 if (default_cpu_version != CPU_VERSION_LEGACY) {
4945 info->alias_of = x86_cpu_class_get_alias_of(cc);
4946 info->has_alias_of = !!info->alias_of;
4947 }
4948
4949 entry = g_malloc0(sizeof(*entry));
4950 entry->value = info;
4951 entry->next = *cpu_list;
4952 *cpu_list = entry;
4953 }
4954
4955 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
4956 {
4957 CpuDefinitionInfoList *cpu_list = NULL;
4958 GSList *list = get_sorted_cpu_model_list();
4959 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
4960 g_slist_free(list);
4961 return cpu_list;
4962 }
4963
4964 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
4965 bool migratable_only)
4966 {
4967 FeatureWordInfo *wi = &feature_word_info[w];
4968 uint64_t r = 0;
4969
4970 if (kvm_enabled()) {
4971 switch (wi->type) {
4972 case CPUID_FEATURE_WORD:
4973 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
4974 wi->cpuid.ecx,
4975 wi->cpuid.reg);
4976 break;
4977 case MSR_FEATURE_WORD:
4978 r = kvm_arch_get_supported_msr_feature(kvm_state,
4979 wi->msr.index);
4980 break;
4981 }
4982 } else if (hvf_enabled()) {
4983 if (wi->type != CPUID_FEATURE_WORD) {
4984 return 0;
4985 }
4986 r = hvf_get_supported_cpuid(wi->cpuid.eax,
4987 wi->cpuid.ecx,
4988 wi->cpuid.reg);
4989 } else if (tcg_enabled()) {
4990 r = wi->tcg_features;
4991 } else {
4992 return ~0;
4993 }
4994 if (migratable_only) {
4995 r &= x86_cpu_get_migratable_flags(w);
4996 }
4997 return r;
4998 }
4999
5000 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5001 {
5002 PropValue *pv;
5003 for (pv = props; pv->prop; pv++) {
5004 if (!pv->value) {
5005 continue;
5006 }
5007 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
5008 &error_abort);
5009 }
5010 }
5011
5012 /* Apply properties for the CPU model version specified in model */
5013 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5014 {
5015 const X86CPUVersionDefinition *vdef;
5016 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5017
5018 if (version == CPU_VERSION_LEGACY) {
5019 return;
5020 }
5021
5022 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5023 PropValue *p;
5024
5025 for (p = vdef->props; p && p->prop; p++) {
5026 object_property_parse(OBJECT(cpu), p->value, p->prop,
5027 &error_abort);
5028 }
5029
5030 if (vdef->version == version) {
5031 break;
5032 }
5033 }
5034
5035 /*
5036 * If we reached the end of the list, version number was invalid
5037 */
5038 assert(vdef->version == version);
5039 }
5040
5041 /* Load data from X86CPUDefinition into a X86CPU object
5042 */
5043 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model, Error **errp)
5044 {
5045 X86CPUDefinition *def = model->cpudef;
5046 CPUX86State *env = &cpu->env;
5047 const char *vendor;
5048 char host_vendor[CPUID_VENDOR_SZ + 1];
5049 FeatureWord w;
5050
5051 /*NOTE: any property set by this function should be returned by
5052 * x86_cpu_static_props(), so static expansion of
5053 * query-cpu-model-expansion is always complete.
5054 */
5055
5056 /* CPU models only set _minimum_ values for level/xlevel: */
5057 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
5058 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
5059
5060 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
5061 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
5062 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
5063 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
5064 for (w = 0; w < FEATURE_WORDS; w++) {
5065 env->features[w] = def->features[w];
5066 }
5067
5068 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5069 cpu->legacy_cache = !def->cache_info;
5070
5071 /* Special cases not set in the X86CPUDefinition structs: */
5072 /* TODO: in-kernel irqchip for hvf */
5073 if (kvm_enabled()) {
5074 if (!kvm_irqchip_in_kernel()) {
5075 x86_cpu_change_kvm_default("x2apic", "off");
5076 }
5077
5078 x86_cpu_apply_props(cpu, kvm_default_props);
5079 } else if (tcg_enabled()) {
5080 x86_cpu_apply_props(cpu, tcg_default_props);
5081 }
5082
5083 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
5084
5085 /* sysenter isn't supported in compatibility mode on AMD,
5086 * syscall isn't supported in compatibility mode on Intel.
5087 * Normally we advertise the actual CPU vendor, but you can
5088 * override this using the 'vendor' property if you want to use
5089 * KVM's sysenter/syscall emulation in compatibility mode and
5090 * when doing cross vendor migration
5091 */
5092 vendor = def->vendor;
5093 if (accel_uses_host_cpuid()) {
5094 uint32_t ebx = 0, ecx = 0, edx = 0;
5095 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
5096 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
5097 vendor = host_vendor;
5098 }
5099
5100 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
5101
5102 x86_cpu_apply_version_props(cpu, model);
5103 }
5104
5105 #ifndef CONFIG_USER_ONLY
5106 /* Return a QDict containing keys for all properties that can be included
5107 * in static expansion of CPU models. All properties set by x86_cpu_load_model()
5108 * must be included in the dictionary.
5109 */
5110 static QDict *x86_cpu_static_props(void)
5111 {
5112 FeatureWord w;
5113 int i;
5114 static const char *props[] = {
5115 "min-level",
5116 "min-xlevel",
5117 "family",
5118 "model",
5119 "stepping",
5120 "model-id",
5121 "vendor",
5122 "lmce",
5123 NULL,
5124 };
5125 static QDict *d;
5126
5127 if (d) {
5128 return d;
5129 }
5130
5131 d = qdict_new();
5132 for (i = 0; props[i]; i++) {
5133 qdict_put_null(d, props[i]);
5134 }
5135
5136 for (w = 0; w < FEATURE_WORDS; w++) {
5137 FeatureWordInfo *fi = &feature_word_info[w];
5138 int bit;
5139 for (bit = 0; bit < 64; bit++) {
5140 if (!fi->feat_names[bit]) {
5141 continue;
5142 }
5143 qdict_put_null(d, fi->feat_names[bit]);
5144 }
5145 }
5146
5147 return d;
5148 }
5149
5150 /* Add an entry to @props dict, with the value for property. */
5151 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
5152 {
5153 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
5154 &error_abort);
5155
5156 qdict_put_obj(props, prop, value);
5157 }
5158
5159 /* Convert CPU model data from X86CPU object to a property dictionary
5160 * that can recreate exactly the same CPU model.
5161 */
5162 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
5163 {
5164 QDict *sprops = x86_cpu_static_props();
5165 const QDictEntry *e;
5166
5167 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
5168 const char *prop = qdict_entry_key(e);
5169 x86_cpu_expand_prop(cpu, props, prop);
5170 }
5171 }
5172
5173 /* Convert CPU model data from X86CPU object to a property dictionary
5174 * that can recreate exactly the same CPU model, including every
5175 * writeable QOM property.
5176 */
5177 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
5178 {
5179 ObjectPropertyIterator iter;
5180 ObjectProperty *prop;
5181
5182 object_property_iter_init(&iter, OBJECT(cpu));
5183 while ((prop = object_property_iter_next(&iter))) {
5184 /* skip read-only or write-only properties */
5185 if (!prop->get || !prop->set) {
5186 continue;
5187 }
5188
5189 /* "hotplugged" is the only property that is configurable
5190 * on the command-line but will be set differently on CPUs
5191 * created using "-cpu ... -smp ..." and by CPUs created
5192 * on the fly by x86_cpu_from_model() for querying. Skip it.
5193 */
5194 if (!strcmp(prop->name, "hotplugged")) {
5195 continue;
5196 }
5197 x86_cpu_expand_prop(cpu, props, prop->name);
5198 }
5199 }
5200
5201 static void object_apply_props(Object *obj, QDict *props, Error **errp)
5202 {
5203 const QDictEntry *prop;
5204 Error *err = NULL;
5205
5206 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
5207 object_property_set_qobject(obj, qdict_entry_value(prop),
5208 qdict_entry_key(prop), &err);
5209 if (err) {
5210 break;
5211 }
5212 }
5213
5214 error_propagate(errp, err);
5215 }
5216
5217 /* Create X86CPU object according to model+props specification */
5218 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
5219 {
5220 X86CPU *xc = NULL;
5221 X86CPUClass *xcc;
5222 Error *err = NULL;
5223
5224 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
5225 if (xcc == NULL) {
5226 error_setg(&err, "CPU model '%s' not found", model);
5227 goto out;
5228 }
5229
5230 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
5231 if (props) {
5232 object_apply_props(OBJECT(xc), props, &err);
5233 if (err) {
5234 goto out;
5235 }
5236 }
5237
5238 x86_cpu_expand_features(xc, &err);
5239 if (err) {
5240 goto out;
5241 }
5242
5243 out:
5244 if (err) {
5245 error_propagate(errp, err);
5246 object_unref(OBJECT(xc));
5247 xc = NULL;
5248 }
5249 return xc;
5250 }
5251
5252 CpuModelExpansionInfo *
5253 qmp_query_cpu_model_expansion(CpuModelExpansionType type,
5254 CpuModelInfo *model,
5255 Error **errp)
5256 {
5257 X86CPU *xc = NULL;
5258 Error *err = NULL;
5259 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
5260 QDict *props = NULL;
5261 const char *base_name;
5262
5263 xc = x86_cpu_from_model(model->name,
5264 model->has_props ?
5265 qobject_to(QDict, model->props) :
5266 NULL, &err);
5267 if (err) {
5268 goto out;
5269 }
5270
5271 props = qdict_new();
5272 ret->model = g_new0(CpuModelInfo, 1);
5273 ret->model->props = QOBJECT(props);
5274 ret->model->has_props = true;
5275
5276 switch (type) {
5277 case CPU_MODEL_EXPANSION_TYPE_STATIC:
5278 /* Static expansion will be based on "base" only */
5279 base_name = "base";
5280 x86_cpu_to_dict(xc, props);
5281 break;
5282 case CPU_MODEL_EXPANSION_TYPE_FULL:
5283 /* As we don't return every single property, full expansion needs
5284 * to keep the original model name+props, and add extra
5285 * properties on top of that.
5286 */
5287 base_name = model->name;
5288 x86_cpu_to_dict_full(xc, props);
5289 break;
5290 default:
5291 error_setg(&err, "Unsupported expansion type");
5292 goto out;
5293 }
5294
5295 x86_cpu_to_dict(xc, props);
5296
5297 ret->model->name = g_strdup(base_name);
5298
5299 out:
5300 object_unref(OBJECT(xc));
5301 if (err) {
5302 error_propagate(errp, err);
5303 qapi_free_CpuModelExpansionInfo(ret);
5304 ret = NULL;
5305 }
5306 return ret;
5307 }
5308 #endif /* !CONFIG_USER_ONLY */
5309
5310 static gchar *x86_gdb_arch_name(CPUState *cs)
5311 {
5312 #ifdef TARGET_X86_64
5313 return g_strdup("i386:x86-64");
5314 #else
5315 return g_strdup("i386");
5316 #endif
5317 }
5318
5319 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5320 {
5321 X86CPUModel *model = data;
5322 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5323
5324 xcc->model = model;
5325 xcc->migration_safe = true;
5326 }
5327
5328 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
5329 {
5330 g_autofree char *typename = x86_cpu_type_name(name);
5331 TypeInfo ti = {
5332 .name = typename,
5333 .parent = TYPE_X86_CPU,
5334 .class_init = x86_cpu_cpudef_class_init,
5335 .class_data = model,
5336 };
5337
5338 type_register(&ti);
5339 }
5340
5341 static void x86_register_cpudef_types(X86CPUDefinition *def)
5342 {
5343 X86CPUModel *m;
5344 const X86CPUVersionDefinition *vdef;
5345
5346 /* AMD aliases are handled at runtime based on CPUID vendor, so
5347 * they shouldn't be set on the CPU model table.
5348 */
5349 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
5350 /* catch mistakes instead of silently truncating model_id when too long */
5351 assert(def->model_id && strlen(def->model_id) <= 48);
5352
5353 /* Unversioned model: */
5354 m = g_new0(X86CPUModel, 1);
5355 m->cpudef = def;
5356 m->version = CPU_VERSION_AUTO;
5357 m->is_alias = true;
5358 x86_register_cpu_model_type(def->name, m);
5359
5360 /* Versioned models: */
5361
5362 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5363 X86CPUModel *m = g_new0(X86CPUModel, 1);
5364 g_autofree char *name =
5365 x86_cpu_versioned_model_name(def, vdef->version);
5366 m->cpudef = def;
5367 m->version = vdef->version;
5368 m->note = vdef->note;
5369 x86_register_cpu_model_type(name, m);
5370
5371 if (vdef->alias) {
5372 X86CPUModel *am = g_new0(X86CPUModel, 1);
5373 am->cpudef = def;
5374 am->version = vdef->version;
5375 am->is_alias = true;
5376 x86_register_cpu_model_type(vdef->alias, am);
5377 }
5378 }
5379
5380 }
5381
5382 #if !defined(CONFIG_USER_ONLY)
5383
5384 void cpu_clear_apic_feature(CPUX86State *env)
5385 {
5386 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
5387 }
5388
5389 #endif /* !CONFIG_USER_ONLY */
5390
5391 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5392 uint32_t *eax, uint32_t *ebx,
5393 uint32_t *ecx, uint32_t *edx)
5394 {
5395 X86CPU *cpu = env_archcpu(env);
5396 CPUState *cs = env_cpu(env);
5397 uint32_t die_offset;
5398 uint32_t limit;
5399 uint32_t signature[3];
5400
5401 /* Calculate & apply limits for different index ranges */
5402 if (index >= 0xC0000000) {
5403 limit = env->cpuid_xlevel2;
5404 } else if (index >= 0x80000000) {
5405 limit = env->cpuid_xlevel;
5406 } else if (index >= 0x40000000) {
5407 limit = 0x40000001;
5408 } else {
5409 limit = env->cpuid_level;
5410 }
5411
5412 if (index > limit) {
5413 /* Intel documentation states that invalid EAX input will
5414 * return the same information as EAX=cpuid_level
5415 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5416 */
5417 index = env->cpuid_level;
5418 }
5419
5420 switch(index) {
5421 case 0:
5422 *eax = env->cpuid_level;
5423 *ebx = env->cpuid_vendor1;
5424 *edx = env->cpuid_vendor2;
5425 *ecx = env->cpuid_vendor3;
5426 break;
5427 case 1:
5428 *eax = env->cpuid_version;
5429 *ebx = (cpu->apic_id << 24) |
5430 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
5431 *ecx = env->features[FEAT_1_ECX];
5432 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5433 *ecx |= CPUID_EXT_OSXSAVE;
5434 }
5435 *edx = env->features[FEAT_1_EDX];
5436 if (cs->nr_cores * cs->nr_threads > 1) {
5437 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
5438 *edx |= CPUID_HT;
5439 }
5440 break;
5441 case 2:
5442 /* cache info: needed for Pentium Pro compatibility */
5443 if (cpu->cache_info_passthrough) {
5444 host_cpuid(index, 0, eax, ebx, ecx, edx);
5445 break;
5446 }
5447 *eax = 1; /* Number of CPUID[EAX=2] calls required */
5448 *ebx = 0;
5449 if (!cpu->enable_l3_cache) {
5450 *ecx = 0;
5451 } else {
5452 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
5453 }
5454 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5455 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5456 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
5457 break;
5458 case 4:
5459 /* cache info: needed for Core compatibility */
5460 if (cpu->cache_info_passthrough) {
5461 host_cpuid(index, count, eax, ebx, ecx, edx);
5462 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
5463 *eax &= ~0xFC000000;
5464 if ((*eax & 31) && cs->nr_cores > 1) {
5465 *eax |= (cs->nr_cores - 1) << 26;
5466 }
5467 } else {
5468 *eax = 0;
5469 switch (count) {
5470 case 0: /* L1 dcache info */
5471 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5472 1, cs->nr_cores,
5473 eax, ebx, ecx, edx);
5474 break;
5475 case 1: /* L1 icache info */
5476 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5477 1, cs->nr_cores,
5478 eax, ebx, ecx, edx);
5479 break;
5480 case 2: /* L2 cache info */
5481 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5482 cs->nr_threads, cs->nr_cores,
5483 eax, ebx, ecx, edx);
5484 break;
5485 case 3: /* L3 cache info */
5486 die_offset = apicid_die_offset(env->nr_dies,
5487 cs->nr_cores, cs->nr_threads);
5488 if (cpu->enable_l3_cache) {
5489 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
5490 (1 << die_offset), cs->nr_cores,
5491 eax, ebx, ecx, edx);
5492 break;
5493 }
5494 /* fall through */
5495 default: /* end of info */
5496 *eax = *ebx = *ecx = *edx = 0;
5497 break;
5498 }
5499 }
5500 break;
5501 case 5:
5502 /* MONITOR/MWAIT Leaf */
5503 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5504 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5505 *ecx = cpu->mwait.ecx; /* flags */
5506 *edx = cpu->mwait.edx; /* mwait substates */
5507 break;
5508 case 6:
5509 /* Thermal and Power Leaf */
5510 *eax = env->features[FEAT_6_EAX];
5511 *ebx = 0;
5512 *ecx = 0;
5513 *edx = 0;
5514 break;
5515 case 7:
5516 /* Structured Extended Feature Flags Enumeration Leaf */
5517 if (count == 0) {
5518 /* Maximum ECX value for sub-leaves */
5519 *eax = env->cpuid_level_func7;
5520 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
5521 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
5522 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5523 *ecx |= CPUID_7_0_ECX_OSPKE;
5524 }
5525 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
5526 } else if (count == 1) {
5527 *eax = env->features[FEAT_7_1_EAX];
5528 *ebx = 0;
5529 *ecx = 0;
5530 *edx = 0;
5531 } else {
5532 *eax = 0;
5533 *ebx = 0;
5534 *ecx = 0;
5535 *edx = 0;
5536 }
5537 break;
5538 case 9:
5539 /* Direct Cache Access Information Leaf */
5540 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5541 *ebx = 0;
5542 *ecx = 0;
5543 *edx = 0;
5544 break;
5545 case 0xA:
5546 /* Architectural Performance Monitoring Leaf */
5547 if (kvm_enabled() && cpu->enable_pmu) {
5548 KVMState *s = cs->kvm_state;
5549
5550 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5551 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5552 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5553 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
5554 } else if (hvf_enabled() && cpu->enable_pmu) {
5555 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5556 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5557 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5558 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
5559 } else {
5560 *eax = 0;
5561 *ebx = 0;
5562 *ecx = 0;
5563 *edx = 0;
5564 }
5565 break;
5566 case 0xB:
5567 /* Extended Topology Enumeration Leaf */
5568 if (!cpu->enable_cpuid_0xb) {
5569 *eax = *ebx = *ecx = *edx = 0;
5570 break;
5571 }
5572
5573 *ecx = count & 0xff;
5574 *edx = cpu->apic_id;
5575
5576 switch (count) {
5577 case 0:
5578 *eax = apicid_core_offset(env->nr_dies,
5579 cs->nr_cores, cs->nr_threads);
5580 *ebx = cs->nr_threads;
5581 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5582 break;
5583 case 1:
5584 *eax = apicid_pkg_offset(env->nr_dies,
5585 cs->nr_cores, cs->nr_threads);
5586 *ebx = cs->nr_cores * cs->nr_threads;
5587 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5588 break;
5589 default:
5590 *eax = 0;
5591 *ebx = 0;
5592 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5593 }
5594
5595 assert(!(*eax & ~0x1f));
5596 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5597 break;
5598 case 0x1F:
5599 /* V2 Extended Topology Enumeration Leaf */
5600 if (env->nr_dies < 2) {
5601 *eax = *ebx = *ecx = *edx = 0;
5602 break;
5603 }
5604
5605 *ecx = count & 0xff;
5606 *edx = cpu->apic_id;
5607 switch (count) {
5608 case 0:
5609 *eax = apicid_core_offset(env->nr_dies, cs->nr_cores,
5610 cs->nr_threads);
5611 *ebx = cs->nr_threads;
5612 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5613 break;
5614 case 1:
5615 *eax = apicid_die_offset(env->nr_dies, cs->nr_cores,
5616 cs->nr_threads);
5617 *ebx = cs->nr_cores * cs->nr_threads;
5618 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5619 break;
5620 case 2:
5621 *eax = apicid_pkg_offset(env->nr_dies, cs->nr_cores,
5622 cs->nr_threads);
5623 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5624 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5625 break;
5626 default:
5627 *eax = 0;
5628 *ebx = 0;
5629 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5630 }
5631 assert(!(*eax & ~0x1f));
5632 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5633 break;
5634 case 0xD: {
5635 /* Processor Extended State */
5636 *eax = 0;
5637 *ebx = 0;
5638 *ecx = 0;
5639 *edx = 0;
5640 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
5641 break;
5642 }
5643
5644 if (count == 0) {
5645 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5646 *eax = env->features[FEAT_XSAVE_COMP_LO];
5647 *edx = env->features[FEAT_XSAVE_COMP_HI];
5648 /*
5649 * The initial value of xcr0 and ebx == 0, On host without kvm
5650 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5651 * even through guest update xcr0, this will crash some legacy guest
5652 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5653 */
5654 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
5655 } else if (count == 1) {
5656 *eax = env->features[FEAT_XSAVE];
5657 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
5658 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5659 const ExtSaveArea *esa = &x86_ext_save_areas[count];
5660 *eax = esa->size;
5661 *ebx = esa->offset;
5662 }
5663 }
5664 break;
5665 }
5666 case 0x14: {
5667 /* Intel Processor Trace Enumeration */
5668 *eax = 0;
5669 *ebx = 0;
5670 *ecx = 0;
5671 *edx = 0;
5672 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5673 !kvm_enabled()) {
5674 break;
5675 }
5676
5677 if (count == 0) {
5678 *eax = INTEL_PT_MAX_SUBLEAF;
5679 *ebx = INTEL_PT_MINIMAL_EBX;
5680 *ecx = INTEL_PT_MINIMAL_ECX;
5681 } else if (count == 1) {
5682 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5683 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5684 }
5685 break;
5686 }
5687 case 0x40000000:
5688 /*
5689 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5690 * set here, but we restrict to TCG none the less.
5691 */
5692 if (tcg_enabled() && cpu->expose_tcg) {
5693 memcpy(signature, "TCGTCGTCGTCG", 12);
5694 *eax = 0x40000001;
5695 *ebx = signature[0];
5696 *ecx = signature[1];
5697 *edx = signature[2];
5698 } else {
5699 *eax = 0;
5700 *ebx = 0;
5701 *ecx = 0;
5702 *edx = 0;
5703 }
5704 break;
5705 case 0x40000001:
5706 *eax = 0;
5707 *ebx = 0;
5708 *ecx = 0;
5709 *edx = 0;
5710 break;
5711 case 0x80000000:
5712 *eax = env->cpuid_xlevel;
5713 *ebx = env->cpuid_vendor1;
5714 *edx = env->cpuid_vendor2;
5715 *ecx = env->cpuid_vendor3;
5716 break;
5717 case 0x80000001:
5718 *eax = env->cpuid_version;
5719 *ebx = 0;
5720 *ecx = env->features[FEAT_8000_0001_ECX];
5721 *edx = env->features[FEAT_8000_0001_EDX];
5722
5723 /* The Linux kernel checks for the CMPLegacy bit and
5724 * discards multiple thread information if it is set.
5725 * So don't set it here for Intel to make Linux guests happy.
5726 */
5727 if (cs->nr_cores * cs->nr_threads > 1) {
5728 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5729 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5730 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
5731 *ecx |= 1 << 1; /* CmpLegacy bit */
5732 }
5733 }
5734 break;
5735 case 0x80000002:
5736 case 0x80000003:
5737 case 0x80000004:
5738 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5739 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5740 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5741 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5742 break;
5743 case 0x80000005:
5744 /* cache info (L1 cache) */
5745 if (cpu->cache_info_passthrough) {
5746 host_cpuid(index, 0, eax, ebx, ecx, edx);
5747 break;
5748 }
5749 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
5750 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
5751 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
5752 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
5753 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5754 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
5755 break;
5756 case 0x80000006:
5757 /* cache info (L2 cache) */
5758 if (cpu->cache_info_passthrough) {
5759 host_cpuid(index, 0, eax, ebx, ecx, edx);
5760 break;
5761 }
5762 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
5763 (L2_DTLB_2M_ENTRIES << 16) | \
5764 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
5765 (L2_ITLB_2M_ENTRIES);
5766 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
5767 (L2_DTLB_4K_ENTRIES << 16) | \
5768 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
5769 (L2_ITLB_4K_ENTRIES);
5770 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5771 cpu->enable_l3_cache ?
5772 env->cache_info_amd.l3_cache : NULL,
5773 ecx, edx);
5774 break;
5775 case 0x80000007:
5776 *eax = 0;
5777 *ebx = 0;
5778 *ecx = 0;
5779 *edx = env->features[FEAT_8000_0007_EDX];
5780 break;
5781 case 0x80000008:
5782 /* virtual & phys address size in low 2 bytes. */
5783 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
5784 /* 64 bit processor */
5785 *eax = cpu->phys_bits; /* configurable physical bits */
5786 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5787 *eax |= 0x00003900; /* 57 bits virtual */
5788 } else {
5789 *eax |= 0x00003000; /* 48 bits virtual */
5790 }
5791 } else {
5792 *eax = cpu->phys_bits;
5793 }
5794 *ebx = env->features[FEAT_8000_0008_EBX];
5795 *ecx = 0;
5796 *edx = 0;
5797 if (cs->nr_cores * cs->nr_threads > 1) {
5798 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
5799 }
5800 break;
5801 case 0x8000000A:
5802 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5803 *eax = 0x00000001; /* SVM Revision */
5804 *ebx = 0x00000010; /* nr of ASIDs */
5805 *ecx = 0;
5806 *edx = env->features[FEAT_SVM]; /* optional features */
5807 } else {
5808 *eax = 0;
5809 *ebx = 0;
5810 *ecx = 0;
5811 *edx = 0;
5812 }
5813 break;
5814 case 0x8000001D:
5815 *eax = 0;
5816 if (cpu->cache_info_passthrough) {
5817 host_cpuid(index, count, eax, ebx, ecx, edx);
5818 break;
5819 }
5820 switch (count) {
5821 case 0: /* L1 dcache info */
5822 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
5823 eax, ebx, ecx, edx);
5824 break;
5825 case 1: /* L1 icache info */
5826 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
5827 eax, ebx, ecx, edx);
5828 break;
5829 case 2: /* L2 cache info */
5830 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
5831 eax, ebx, ecx, edx);
5832 break;
5833 case 3: /* L3 cache info */
5834 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
5835 eax, ebx, ecx, edx);
5836 break;
5837 default: /* end of info */
5838 *eax = *ebx = *ecx = *edx = 0;
5839 break;
5840 }
5841 break;
5842 case 0x8000001E:
5843 assert(cpu->core_id <= 255);
5844 encode_topo_cpuid8000001e(cs, cpu,
5845 eax, ebx, ecx, edx);
5846 break;
5847 case 0xC0000000:
5848 *eax = env->cpuid_xlevel2;
5849 *ebx = 0;
5850 *ecx = 0;
5851 *edx = 0;
5852 break;
5853 case 0xC0000001:
5854 /* Support for VIA CPU's CPUID instruction */
5855 *eax = env->cpuid_version;
5856 *ebx = 0;
5857 *ecx = 0;
5858 *edx = env->features[FEAT_C000_0001_EDX];
5859 break;
5860 case 0xC0000002:
5861 case 0xC0000003:
5862 case 0xC0000004:
5863 /* Reserved for the future, and now filled with zero */
5864 *eax = 0;
5865 *ebx = 0;
5866 *ecx = 0;
5867 *edx = 0;
5868 break;
5869 case 0x8000001F:
5870 *eax = sev_enabled() ? 0x2 : 0;
5871 *ebx = sev_get_cbit_position();
5872 *ebx |= sev_get_reduced_phys_bits() << 6;
5873 *ecx = 0;
5874 *edx = 0;
5875 break;
5876 default:
5877 /* reserved values: zero */
5878 *eax = 0;
5879 *ebx = 0;
5880 *ecx = 0;
5881 *edx = 0;
5882 break;
5883 }
5884 }
5885
5886 /* CPUClass::reset() */
5887 static void x86_cpu_reset(CPUState *s)
5888 {
5889 X86CPU *cpu = X86_CPU(s);
5890 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5891 CPUX86State *env = &cpu->env;
5892 target_ulong cr4;
5893 uint64_t xcr0;
5894 int i;
5895
5896 xcc->parent_reset(s);
5897
5898 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
5899
5900 env->old_exception = -1;
5901
5902 /* init to reset state */
5903
5904 env->hflags2 |= HF2_GIF_MASK;
5905
5906 cpu_x86_update_cr0(env, 0x60000010);
5907 env->a20_mask = ~0x0;
5908 env->smbase = 0x30000;
5909 env->msr_smi_count = 0;
5910
5911 env->idt.limit = 0xffff;
5912 env->gdt.limit = 0xffff;
5913 env->ldt.limit = 0xffff;
5914 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
5915 env->tr.limit = 0xffff;
5916 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
5917
5918 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
5919 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
5920 DESC_R_MASK | DESC_A_MASK);
5921 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
5922 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5923 DESC_A_MASK);
5924 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
5925 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5926 DESC_A_MASK);
5927 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
5928 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5929 DESC_A_MASK);
5930 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
5931 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5932 DESC_A_MASK);
5933 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
5934 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5935 DESC_A_MASK);
5936
5937 env->eip = 0xfff0;
5938 env->regs[R_EDX] = env->cpuid_version;
5939
5940 env->eflags = 0x2;
5941
5942 /* FPU init */
5943 for (i = 0; i < 8; i++) {
5944 env->fptags[i] = 1;
5945 }
5946 cpu_set_fpuc(env, 0x37f);
5947
5948 env->mxcsr = 0x1f80;
5949 /* All units are in INIT state. */
5950 env->xstate_bv = 0;
5951
5952 env->pat = 0x0007040600070406ULL;
5953 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
5954 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
5955 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
5956 }
5957
5958 memset(env->dr, 0, sizeof(env->dr));
5959 env->dr[6] = DR6_FIXED_1;
5960 env->dr[7] = DR7_FIXED_1;
5961 cpu_breakpoint_remove_all(s, BP_CPU);
5962 cpu_watchpoint_remove_all(s, BP_CPU);
5963
5964 cr4 = 0;
5965 xcr0 = XSTATE_FP_MASK;
5966
5967 #ifdef CONFIG_USER_ONLY
5968 /* Enable all the features for user-mode. */
5969 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
5970 xcr0 |= XSTATE_SSE_MASK;
5971 }
5972 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
5973 const ExtSaveArea *esa = &x86_ext_save_areas[i];
5974 if (env->features[esa->feature] & esa->bits) {
5975 xcr0 |= 1ull << i;
5976 }
5977 }
5978
5979 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
5980 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
5981 }
5982 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
5983 cr4 |= CR4_FSGSBASE_MASK;
5984 }
5985 #endif
5986
5987 env->xcr0 = xcr0;
5988 cpu_x86_update_cr4(env, cr4);
5989
5990 /*
5991 * SDM 11.11.5 requires:
5992 * - IA32_MTRR_DEF_TYPE MSR.E = 0
5993 * - IA32_MTRR_PHYSMASKn.V = 0
5994 * All other bits are undefined. For simplification, zero it all.
5995 */
5996 env->mtrr_deftype = 0;
5997 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
5998 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
5999
6000 env->interrupt_injected = -1;
6001 env->exception_nr = -1;
6002 env->exception_pending = 0;
6003 env->exception_injected = 0;
6004 env->exception_has_payload = false;
6005 env->exception_payload = 0;
6006 env->nmi_injected = false;
6007 #if !defined(CONFIG_USER_ONLY)
6008 /* We hard-wire the BSP to the first CPU. */
6009 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
6010
6011 s->halted = !cpu_is_bsp(cpu);
6012
6013 if (kvm_enabled()) {
6014 kvm_arch_reset_vcpu(cpu);
6015 }
6016 else if (hvf_enabled()) {
6017 hvf_reset_vcpu(s);
6018 }
6019 #endif
6020 }
6021
6022 #ifndef CONFIG_USER_ONLY
6023 bool cpu_is_bsp(X86CPU *cpu)
6024 {
6025 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
6026 }
6027
6028 /* TODO: remove me, when reset over QOM tree is implemented */
6029 static void x86_cpu_machine_reset_cb(void *opaque)
6030 {
6031 X86CPU *cpu = opaque;
6032 cpu_reset(CPU(cpu));
6033 }
6034 #endif
6035
6036 static void mce_init(X86CPU *cpu)
6037 {
6038 CPUX86State *cenv = &cpu->env;
6039 unsigned int bank;
6040
6041 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
6042 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
6043 (CPUID_MCE | CPUID_MCA)) {
6044 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
6045 (cpu->enable_lmce ? MCG_LMCE_P : 0);
6046 cenv->mcg_ctl = ~(uint64_t)0;
6047 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
6048 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
6049 }
6050 }
6051 }
6052
6053 #ifndef CONFIG_USER_ONLY
6054 APICCommonClass *apic_get_class(void)
6055 {
6056 const char *apic_type = "apic";
6057
6058 /* TODO: in-kernel irqchip for hvf */
6059 if (kvm_apic_in_kernel()) {
6060 apic_type = "kvm-apic";
6061 } else if (xen_enabled()) {
6062 apic_type = "xen-apic";
6063 }
6064
6065 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
6066 }
6067
6068 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
6069 {
6070 APICCommonState *apic;
6071 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
6072
6073 cpu->apic_state = DEVICE(object_new_with_class(apic_class));
6074
6075 object_property_add_child(OBJECT(cpu), "lapic",
6076 OBJECT(cpu->apic_state), &error_abort);
6077 object_unref(OBJECT(cpu->apic_state));
6078
6079 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
6080 /* TODO: convert to link<> */
6081 apic = APIC_COMMON(cpu->apic_state);
6082 apic->cpu = cpu;
6083 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
6084 }
6085
6086 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6087 {
6088 APICCommonState *apic;
6089 static bool apic_mmio_map_once;
6090
6091 if (cpu->apic_state == NULL) {
6092 return;
6093 }
6094 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
6095 errp);
6096
6097 /* Map APIC MMIO area */
6098 apic = APIC_COMMON(cpu->apic_state);
6099 if (!apic_mmio_map_once) {
6100 memory_region_add_subregion_overlap(get_system_memory(),
6101 apic->apicbase &
6102 MSR_IA32_APICBASE_BASE,
6103 &apic->io_memory,
6104 0x1000);
6105 apic_mmio_map_once = true;
6106 }
6107 }
6108
6109 static void x86_cpu_machine_done(Notifier *n, void *unused)
6110 {
6111 X86CPU *cpu = container_of(n, X86CPU, machine_done);
6112 MemoryRegion *smram =
6113 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
6114
6115 if (smram) {
6116 cpu->smram = g_new(MemoryRegion, 1);
6117 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
6118 smram, 0, 1ull << 32);
6119 memory_region_set_enabled(cpu->smram, true);
6120 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
6121 }
6122 }
6123 #else
6124 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6125 {
6126 }
6127 #endif
6128
6129 /* Note: Only safe for use on x86(-64) hosts */
6130 static uint32_t x86_host_phys_bits(void)
6131 {
6132 uint32_t eax;
6133 uint32_t host_phys_bits;
6134
6135 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
6136 if (eax >= 0x80000008) {
6137 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
6138 /* Note: According to AMD doc 25481 rev 2.34 they have a field
6139 * at 23:16 that can specify a maximum physical address bits for
6140 * the guest that can override this value; but I've not seen
6141 * anything with that set.
6142 */
6143 host_phys_bits = eax & 0xff;
6144 } else {
6145 /* It's an odd 64 bit machine that doesn't have the leaf for
6146 * physical address bits; fall back to 36 that's most older
6147 * Intel.
6148 */
6149 host_phys_bits = 36;
6150 }
6151
6152 return host_phys_bits;
6153 }
6154
6155 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
6156 {
6157 if (*min < value) {
6158 *min = value;
6159 }
6160 }
6161
6162 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6163 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
6164 {
6165 CPUX86State *env = &cpu->env;
6166 FeatureWordInfo *fi = &feature_word_info[w];
6167 uint32_t eax = fi->cpuid.eax;
6168 uint32_t region = eax & 0xF0000000;
6169
6170 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
6171 if (!env->features[w]) {
6172 return;
6173 }
6174
6175 switch (region) {
6176 case 0x00000000:
6177 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
6178 break;
6179 case 0x80000000:
6180 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
6181 break;
6182 case 0xC0000000:
6183 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
6184 break;
6185 }
6186
6187 if (eax == 7) {
6188 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
6189 fi->cpuid.ecx);
6190 }
6191 }
6192
6193 /* Calculate XSAVE components based on the configured CPU feature flags */
6194 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
6195 {
6196 CPUX86State *env = &cpu->env;
6197 int i;
6198 uint64_t mask;
6199
6200 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
6201 return;
6202 }
6203
6204 mask = 0;
6205 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6206 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6207 if (env->features[esa->feature] & esa->bits) {
6208 mask |= (1ULL << i);
6209 }
6210 }
6211
6212 env->features[FEAT_XSAVE_COMP_LO] = mask;
6213 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
6214 }
6215
6216 /***** Steps involved on loading and filtering CPUID data
6217 *
6218 * When initializing and realizing a CPU object, the steps
6219 * involved in setting up CPUID data are:
6220 *
6221 * 1) Loading CPU model definition (X86CPUDefinition). This is
6222 * implemented by x86_cpu_load_model() and should be completely
6223 * transparent, as it is done automatically by instance_init.
6224 * No code should need to look at X86CPUDefinition structs
6225 * outside instance_init.
6226 *
6227 * 2) CPU expansion. This is done by realize before CPUID
6228 * filtering, and will make sure host/accelerator data is
6229 * loaded for CPU models that depend on host capabilities
6230 * (e.g. "host"). Done by x86_cpu_expand_features().
6231 *
6232 * 3) CPUID filtering. This initializes extra data related to
6233 * CPUID, and checks if the host supports all capabilities
6234 * required by the CPU. Runnability of a CPU model is
6235 * determined at this step. Done by x86_cpu_filter_features().
6236 *
6237 * Some operations don't require all steps to be performed.
6238 * More precisely:
6239 *
6240 * - CPU instance creation (instance_init) will run only CPU
6241 * model loading. CPU expansion can't run at instance_init-time
6242 * because host/accelerator data may be not available yet.
6243 * - CPU realization will perform both CPU model expansion and CPUID
6244 * filtering, and return an error in case one of them fails.
6245 * - query-cpu-definitions needs to run all 3 steps. It needs
6246 * to run CPUID filtering, as the 'unavailable-features'
6247 * field is set based on the filtering results.
6248 * - The query-cpu-model-expansion QMP command only needs to run
6249 * CPU model loading and CPU expansion. It should not filter
6250 * any CPUID data based on host capabilities.
6251 */
6252
6253 /* Expand CPU configuration data, based on configured features
6254 * and host/accelerator capabilities when appropriate.
6255 */
6256 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
6257 {
6258 CPUX86State *env = &cpu->env;
6259 FeatureWord w;
6260 int i;
6261 GList *l;
6262 Error *local_err = NULL;
6263
6264 for (l = plus_features; l; l = l->next) {
6265 const char *prop = l->data;
6266 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
6267 if (local_err) {
6268 goto out;
6269 }
6270 }
6271
6272 for (l = minus_features; l; l = l->next) {
6273 const char *prop = l->data;
6274 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
6275 if (local_err) {
6276 goto out;
6277 }
6278 }
6279
6280 /*TODO: Now cpu->max_features doesn't overwrite features
6281 * set using QOM properties, and we can convert
6282 * plus_features & minus_features to global properties
6283 * inside x86_cpu_parse_featurestr() too.
6284 */
6285 if (cpu->max_features) {
6286 for (w = 0; w < FEATURE_WORDS; w++) {
6287 /* Override only features that weren't set explicitly
6288 * by the user.
6289 */
6290 env->features[w] |=
6291 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
6292 ~env->user_features[w] & \
6293 ~feature_word_info[w].no_autoenable_flags;
6294 }
6295 }
6296
6297 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6298 FeatureDep *d = &feature_dependencies[i];
6299 if (!(env->features[d->from.index] & d->from.mask)) {
6300 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
6301
6302 /* Not an error unless the dependent feature was added explicitly. */
6303 mark_unavailable_features(cpu, d->to.index,
6304 unavailable_features & env->user_features[d->to.index],
6305 "This feature depends on other features that were not requested");
6306
6307 env->user_features[d->to.index] |= unavailable_features;
6308 env->features[d->to.index] &= ~unavailable_features;
6309 }
6310 }
6311
6312 if (!kvm_enabled() || !cpu->expose_kvm) {
6313 env->features[FEAT_KVM] = 0;
6314 }
6315
6316 x86_cpu_enable_xsave_components(cpu);
6317
6318 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6319 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6320 if (cpu->full_cpuid_auto_level) {
6321 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6322 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6323 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6324 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
6325 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
6326 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6327 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6328 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
6329 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
6330 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6331 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6332 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
6333
6334 /* Intel Processor Trace requires CPUID[0x14] */
6335 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6336 kvm_enabled() && cpu->intel_pt_auto_level) {
6337 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6338 }
6339
6340 /* CPU topology with multi-dies support requires CPUID[0x1F] */
6341 if (env->nr_dies > 1) {
6342 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6343 }
6344
6345 /* SVM requires CPUID[0x8000000A] */
6346 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6347 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6348 }
6349
6350 /* SEV requires CPUID[0x8000001F] */
6351 if (sev_enabled()) {
6352 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6353 }
6354 }
6355
6356 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
6357 if (env->cpuid_level_func7 == UINT32_MAX) {
6358 env->cpuid_level_func7 = env->cpuid_min_level_func7;
6359 }
6360 if (env->cpuid_level == UINT32_MAX) {
6361 env->cpuid_level = env->cpuid_min_level;
6362 }
6363 if (env->cpuid_xlevel == UINT32_MAX) {
6364 env->cpuid_xlevel = env->cpuid_min_xlevel;
6365 }
6366 if (env->cpuid_xlevel2 == UINT32_MAX) {
6367 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
6368 }
6369
6370 out:
6371 if (local_err != NULL) {
6372 error_propagate(errp, local_err);
6373 }
6374 }
6375
6376 /*
6377 * Finishes initialization of CPUID data, filters CPU feature
6378 * words based on host availability of each feature.
6379 *
6380 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6381 */
6382 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
6383 {
6384 CPUX86State *env = &cpu->env;
6385 FeatureWord w;
6386 const char *prefix = NULL;
6387
6388 if (verbose) {
6389 prefix = accel_uses_host_cpuid()
6390 ? "host doesn't support requested feature"
6391 : "TCG doesn't support requested feature";
6392 }
6393
6394 for (w = 0; w < FEATURE_WORDS; w++) {
6395 uint64_t host_feat =
6396 x86_cpu_get_supported_feature_word(w, false);
6397 uint64_t requested_features = env->features[w];
6398 uint64_t unavailable_features = requested_features & ~host_feat;
6399 mark_unavailable_features(cpu, w, unavailable_features, prefix);
6400 }
6401
6402 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6403 kvm_enabled()) {
6404 KVMState *s = CPU(cpu)->kvm_state;
6405 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6406 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6407 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6408 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6409 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6410
6411 if (!eax_0 ||
6412 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6413 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6414 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6415 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6416 INTEL_PT_ADDR_RANGES_NUM) ||
6417 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
6418 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
6419 (ecx_0 & INTEL_PT_IP_LIP)) {
6420 /*
6421 * Processor Trace capabilities aren't configurable, so if the
6422 * host can't emulate the capabilities we report on
6423 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6424 */
6425 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
6426 }
6427 }
6428 }
6429
6430 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6431 {
6432 CPUState *cs = CPU(dev);
6433 X86CPU *cpu = X86_CPU(dev);
6434 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6435 CPUX86State *env = &cpu->env;
6436 Error *local_err = NULL;
6437 static bool ht_warned;
6438
6439 if (xcc->host_cpuid_required) {
6440 if (!accel_uses_host_cpuid()) {
6441 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6442 error_setg(&local_err, "CPU model '%s' requires KVM", name);
6443 goto out;
6444 }
6445 }
6446
6447 if (cpu->max_features && accel_uses_host_cpuid()) {
6448 if (enable_cpu_pm) {
6449 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
6450 &cpu->mwait.ecx, &cpu->mwait.edx);
6451 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
6452 }
6453 if (kvm_enabled() && cpu->ucode_rev == 0) {
6454 cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,
6455 MSR_IA32_UCODE_REV);
6456 }
6457 }
6458
6459 if (cpu->ucode_rev == 0) {
6460 /* The default is the same as KVM's. */
6461 if (IS_AMD_CPU(env)) {
6462 cpu->ucode_rev = 0x01000065;
6463 } else {
6464 cpu->ucode_rev = 0x100000000ULL;
6465 }
6466 }
6467
6468 /* mwait extended info: needed for Core compatibility */
6469 /* We always wake on interrupt even if host does not have the capability */
6470 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6471
6472 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6473 error_setg(errp, "apic-id property was not initialized properly");
6474 return;
6475 }
6476
6477 x86_cpu_expand_features(cpu, &local_err);
6478 if (local_err) {
6479 goto out;
6480 }
6481
6482 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6483
6484 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6485 error_setg(&local_err,
6486 accel_uses_host_cpuid() ?
6487 "Host doesn't support requested features" :
6488 "TCG doesn't support requested features");
6489 goto out;
6490 }
6491
6492 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6493 * CPUID[1].EDX.
6494 */
6495 if (IS_AMD_CPU(env)) {
6496 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6497 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
6498 & CPUID_EXT2_AMD_ALIASES);
6499 }
6500
6501 /* For 64bit systems think about the number of physical bits to present.
6502 * ideally this should be the same as the host; anything other than matching
6503 * the host can cause incorrect guest behaviour.
6504 * QEMU used to pick the magic value of 40 bits that corresponds to
6505 * consumer AMD devices but nothing else.
6506 */
6507 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6508 if (accel_uses_host_cpuid()) {
6509 uint32_t host_phys_bits = x86_host_phys_bits();
6510 static bool warned;
6511
6512 /* Print a warning if the user set it to a value that's not the
6513 * host value.
6514 */
6515 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
6516 !warned) {
6517 warn_report("Host physical bits (%u)"
6518 " does not match phys-bits property (%u)",
6519 host_phys_bits, cpu->phys_bits);
6520 warned = true;
6521 }
6522
6523 if (cpu->host_phys_bits) {
6524 /* The user asked for us to use the host physical bits */
6525 cpu->phys_bits = host_phys_bits;
6526 if (cpu->host_phys_bits_limit &&
6527 cpu->phys_bits > cpu->host_phys_bits_limit) {
6528 cpu->phys_bits = cpu->host_phys_bits_limit;
6529 }
6530 }
6531
6532 if (cpu->phys_bits &&
6533 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6534 cpu->phys_bits < 32)) {
6535 error_setg(errp, "phys-bits should be between 32 and %u "
6536 " (but is %u)",
6537 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6538 return;
6539 }
6540 } else {
6541 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
6542 error_setg(errp, "TCG only supports phys-bits=%u",
6543 TCG_PHYS_ADDR_BITS);
6544 return;
6545 }
6546 }
6547 /* 0 means it was not explicitly set by the user (or by machine
6548 * compat_props or by the host code above). In this case, the default
6549 * is the value used by TCG (40).
6550 */
6551 if (cpu->phys_bits == 0) {
6552 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6553 }
6554 } else {
6555 /* For 32 bit systems don't use the user set value, but keep
6556 * phys_bits consistent with what we tell the guest.
6557 */
6558 if (cpu->phys_bits != 0) {
6559 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6560 return;
6561 }
6562
6563 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6564 cpu->phys_bits = 36;
6565 } else {
6566 cpu->phys_bits = 32;
6567 }
6568 }
6569
6570 /* Cache information initialization */
6571 if (!cpu->legacy_cache) {
6572 if (!xcc->model || !xcc->model->cpudef->cache_info) {
6573 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6574 error_setg(errp,
6575 "CPU model '%s' doesn't support legacy-cache=off", name);
6576 return;
6577 }
6578 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
6579 *xcc->model->cpudef->cache_info;
6580 } else {
6581 /* Build legacy cache information */
6582 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6583 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6584 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6585 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6586
6587 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6588 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6589 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6590 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6591
6592 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6593 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6594 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6595 env->cache_info_amd.l3_cache = &legacy_l3_cache;
6596 }
6597
6598
6599 cpu_exec_realizefn(cs, &local_err);
6600 if (local_err != NULL) {
6601 error_propagate(errp, local_err);
6602 return;
6603 }
6604
6605 #ifndef CONFIG_USER_ONLY
6606 MachineState *ms = MACHINE(qdev_get_machine());
6607 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
6608
6609 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
6610 x86_cpu_apic_create(cpu, &local_err);
6611 if (local_err != NULL) {
6612 goto out;
6613 }
6614 }
6615 #endif
6616
6617 mce_init(cpu);
6618
6619 #ifndef CONFIG_USER_ONLY
6620 if (tcg_enabled()) {
6621 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
6622 cpu->cpu_as_root = g_new(MemoryRegion, 1);
6623
6624 /* Outer container... */
6625 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
6626 memory_region_set_enabled(cpu->cpu_as_root, true);
6627
6628 /* ... with two regions inside: normal system memory with low
6629 * priority, and...
6630 */
6631 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
6632 get_system_memory(), 0, ~0ull);
6633 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
6634 memory_region_set_enabled(cpu->cpu_as_mem, true);
6635
6636 cs->num_ases = 2;
6637 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
6638 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
6639
6640 /* ... SMRAM with higher priority, linked from /machine/smram. */
6641 cpu->machine_done.notify = x86_cpu_machine_done;
6642 qemu_add_machine_init_done_notifier(&cpu->machine_done);
6643 }
6644 #endif
6645
6646 qemu_init_vcpu(cs);
6647
6648 /*
6649 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6650 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6651 * based on inputs (sockets,cores,threads), it is still better to give
6652 * users a warning.
6653 *
6654 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6655 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6656 */
6657 if (IS_AMD_CPU(env) &&
6658 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6659 cs->nr_threads > 1 && !ht_warned) {
6660 warn_report("This family of AMD CPU doesn't support "
6661 "hyperthreading(%d)",
6662 cs->nr_threads);
6663 error_printf("Please configure -smp options properly"
6664 " or try enabling topoext feature.\n");
6665 ht_warned = true;
6666 }
6667
6668 x86_cpu_apic_realize(cpu, &local_err);
6669 if (local_err != NULL) {
6670 goto out;
6671 }
6672 cpu_reset(cs);
6673
6674 xcc->parent_realize(dev, &local_err);
6675
6676 out:
6677 if (local_err != NULL) {
6678 error_propagate(errp, local_err);
6679 return;
6680 }
6681 }
6682
6683 static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
6684 {
6685 X86CPU *cpu = X86_CPU(dev);
6686 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6687 Error *local_err = NULL;
6688
6689 #ifndef CONFIG_USER_ONLY
6690 cpu_remove_sync(CPU(dev));
6691 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6692 #endif
6693
6694 if (cpu->apic_state) {
6695 object_unparent(OBJECT(cpu->apic_state));
6696 cpu->apic_state = NULL;
6697 }
6698
6699 xcc->parent_unrealize(dev, &local_err);
6700 if (local_err != NULL) {
6701 error_propagate(errp, local_err);
6702 return;
6703 }
6704 }
6705
6706 typedef struct BitProperty {
6707 FeatureWord w;
6708 uint64_t mask;
6709 } BitProperty;
6710
6711 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6712 void *opaque, Error **errp)
6713 {
6714 X86CPU *cpu = X86_CPU(obj);
6715 BitProperty *fp = opaque;
6716 uint64_t f = cpu->env.features[fp->w];
6717 bool value = (f & fp->mask) == fp->mask;
6718 visit_type_bool(v, name, &value, errp);
6719 }
6720
6721 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6722 void *opaque, Error **errp)
6723 {
6724 DeviceState *dev = DEVICE(obj);
6725 X86CPU *cpu = X86_CPU(obj);
6726 BitProperty *fp = opaque;
6727 Error *local_err = NULL;
6728 bool value;
6729
6730 if (dev->realized) {
6731 qdev_prop_set_after_realize(dev, name, errp);
6732 return;
6733 }
6734
6735 visit_type_bool(v, name, &value, &local_err);
6736 if (local_err) {
6737 error_propagate(errp, local_err);
6738 return;
6739 }
6740
6741 if (value) {
6742 cpu->env.features[fp->w] |= fp->mask;
6743 } else {
6744 cpu->env.features[fp->w] &= ~fp->mask;
6745 }
6746 cpu->env.user_features[fp->w] |= fp->mask;
6747 }
6748
6749 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
6750 void *opaque)
6751 {
6752 BitProperty *prop = opaque;
6753 g_free(prop);
6754 }
6755
6756 /* Register a boolean property to get/set a single bit in a uint32_t field.
6757 *
6758 * The same property name can be registered multiple times to make it affect
6759 * multiple bits in the same FeatureWord. In that case, the getter will return
6760 * true only if all bits are set.
6761 */
6762 static void x86_cpu_register_bit_prop(X86CPU *cpu,
6763 const char *prop_name,
6764 FeatureWord w,
6765 int bitnr)
6766 {
6767 BitProperty *fp;
6768 ObjectProperty *op;
6769 uint64_t mask = (1ULL << bitnr);
6770
6771 op = object_property_find(OBJECT(cpu), prop_name, NULL);
6772 if (op) {
6773 fp = op->opaque;
6774 assert(fp->w == w);
6775 fp->mask |= mask;
6776 } else {
6777 fp = g_new0(BitProperty, 1);
6778 fp->w = w;
6779 fp->mask = mask;
6780 object_property_add(OBJECT(cpu), prop_name, "bool",
6781 x86_cpu_get_bit_prop,
6782 x86_cpu_set_bit_prop,
6783 x86_cpu_release_bit_prop, fp, &error_abort);
6784 }
6785 }
6786
6787 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
6788 FeatureWord w,
6789 int bitnr)
6790 {
6791 FeatureWordInfo *fi = &feature_word_info[w];
6792 const char *name = fi->feat_names[bitnr];
6793
6794 if (!name) {
6795 return;
6796 }
6797
6798 /* Property names should use "-" instead of "_".
6799 * Old names containing underscores are registered as aliases
6800 * using object_property_add_alias()
6801 */
6802 assert(!strchr(name, '_'));
6803 /* aliases don't use "|" delimiters anymore, they are registered
6804 * manually using object_property_add_alias() */
6805 assert(!strchr(name, '|'));
6806 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
6807 }
6808
6809 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
6810 {
6811 X86CPU *cpu = X86_CPU(cs);
6812 CPUX86State *env = &cpu->env;
6813 GuestPanicInformation *panic_info = NULL;
6814
6815 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
6816 panic_info = g_malloc0(sizeof(GuestPanicInformation));
6817
6818 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
6819
6820 assert(HV_CRASH_PARAMS >= 5);
6821 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
6822 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
6823 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
6824 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
6825 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
6826 }
6827
6828 return panic_info;
6829 }
6830 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
6831 const char *name, void *opaque,
6832 Error **errp)
6833 {
6834 CPUState *cs = CPU(obj);
6835 GuestPanicInformation *panic_info;
6836
6837 if (!cs->crash_occurred) {
6838 error_setg(errp, "No crash occured");
6839 return;
6840 }
6841
6842 panic_info = x86_cpu_get_crash_info(cs);
6843 if (panic_info == NULL) {
6844 error_setg(errp, "No crash information");
6845 return;
6846 }
6847
6848 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
6849 errp);
6850 qapi_free_GuestPanicInformation(panic_info);
6851 }
6852
6853 static void x86_cpu_initfn(Object *obj)
6854 {
6855 X86CPU *cpu = X86_CPU(obj);
6856 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
6857 CPUX86State *env = &cpu->env;
6858 FeatureWord w;
6859
6860 env->nr_dies = 1;
6861 cpu_set_cpustate_pointers(cpu);
6862
6863 object_property_add(obj, "family", "int",
6864 x86_cpuid_version_get_family,
6865 x86_cpuid_version_set_family, NULL, NULL, NULL);
6866 object_property_add(obj, "model", "int",
6867 x86_cpuid_version_get_model,
6868 x86_cpuid_version_set_model, NULL, NULL, NULL);
6869 object_property_add(obj, "stepping", "int",
6870 x86_cpuid_version_get_stepping,
6871 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
6872 object_property_add_str(obj, "vendor",
6873 x86_cpuid_get_vendor,
6874 x86_cpuid_set_vendor, NULL);
6875 object_property_add_str(obj, "model-id",
6876 x86_cpuid_get_model_id,
6877 x86_cpuid_set_model_id, NULL);
6878 object_property_add(obj, "tsc-frequency", "int",
6879 x86_cpuid_get_tsc_freq,
6880 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
6881 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6882 x86_cpu_get_feature_words,
6883 NULL, NULL, (void *)env->features, NULL);
6884 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6885 x86_cpu_get_feature_words,
6886 NULL, NULL, (void *)cpu->filtered_features, NULL);
6887 /*
6888 * The "unavailable-features" property has the same semantics as
6889 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
6890 * QMP command: they list the features that would have prevented the
6891 * CPU from running if the "enforce" flag was set.
6892 */
6893 object_property_add(obj, "unavailable-features", "strList",
6894 x86_cpu_get_unavailable_features,
6895 NULL, NULL, NULL, &error_abort);
6896
6897 object_property_add(obj, "crash-information", "GuestPanicInformation",
6898 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
6899
6900 for (w = 0; w < FEATURE_WORDS; w++) {
6901 int bitnr;
6902
6903 for (bitnr = 0; bitnr < 64; bitnr++) {
6904 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
6905 }
6906 }
6907
6908 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
6909 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
6910 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
6911 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
6912 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
6913 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
6914 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
6915
6916 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
6917 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
6918 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
6919 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
6920 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
6921 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
6922 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
6923 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
6924 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
6925 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
6926 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
6927 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
6928 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
6929 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
6930 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control",
6931 &error_abort);
6932 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
6933 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
6934 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
6935 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
6936 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
6937 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
6938 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
6939
6940 if (xcc->model) {
6941 x86_cpu_load_model(cpu, xcc->model, &error_abort);
6942 }
6943 }
6944
6945 static int64_t x86_cpu_get_arch_id(CPUState *cs)
6946 {
6947 X86CPU *cpu = X86_CPU(cs);
6948
6949 return cpu->apic_id;
6950 }
6951
6952 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
6953 {
6954 X86CPU *cpu = X86_CPU(cs);
6955
6956 return cpu->env.cr[0] & CR0_PG_MASK;
6957 }
6958
6959 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
6960 {
6961 X86CPU *cpu = X86_CPU(cs);
6962
6963 cpu->env.eip = value;
6964 }
6965
6966 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
6967 {
6968 X86CPU *cpu = X86_CPU(cs);
6969
6970 cpu->env.eip = tb->pc - tb->cs_base;
6971 }
6972
6973 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
6974 {
6975 X86CPU *cpu = X86_CPU(cs);
6976 CPUX86State *env = &cpu->env;
6977
6978 #if !defined(CONFIG_USER_ONLY)
6979 if (interrupt_request & CPU_INTERRUPT_POLL) {
6980 return CPU_INTERRUPT_POLL;
6981 }
6982 #endif
6983 if (interrupt_request & CPU_INTERRUPT_SIPI) {
6984 return CPU_INTERRUPT_SIPI;
6985 }
6986
6987 if (env->hflags2 & HF2_GIF_MASK) {
6988 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
6989 !(env->hflags & HF_SMM_MASK)) {
6990 return CPU_INTERRUPT_SMI;
6991 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
6992 !(env->hflags2 & HF2_NMI_MASK)) {
6993 return CPU_INTERRUPT_NMI;
6994 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
6995 return CPU_INTERRUPT_MCE;
6996 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
6997 (((env->hflags2 & HF2_VINTR_MASK) &&
6998 (env->hflags2 & HF2_HIF_MASK)) ||
6999 (!(env->hflags2 & HF2_VINTR_MASK) &&
7000 (env->eflags & IF_MASK &&
7001 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
7002 return CPU_INTERRUPT_HARD;
7003 #if !defined(CONFIG_USER_ONLY)
7004 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
7005 (env->eflags & IF_MASK) &&
7006 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
7007 return CPU_INTERRUPT_VIRQ;
7008 #endif
7009 }
7010 }
7011
7012 return 0;
7013 }
7014
7015 static bool x86_cpu_has_work(CPUState *cs)
7016 {
7017 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
7018 }
7019
7020 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
7021 {
7022 X86CPU *cpu = X86_CPU(cs);
7023 CPUX86State *env = &cpu->env;
7024
7025 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
7026 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
7027 : bfd_mach_i386_i8086);
7028 info->print_insn = print_insn_i386;
7029
7030 info->cap_arch = CS_ARCH_X86;
7031 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
7032 : env->hflags & HF_CS32_MASK ? CS_MODE_32
7033 : CS_MODE_16);
7034 info->cap_insn_unit = 1;
7035 info->cap_insn_split = 8;
7036 }
7037
7038 void x86_update_hflags(CPUX86State *env)
7039 {
7040 uint32_t hflags;
7041 #define HFLAG_COPY_MASK \
7042 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7043 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7044 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7045 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7046
7047 hflags = env->hflags & HFLAG_COPY_MASK;
7048 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
7049 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
7050 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
7051 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
7052 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
7053
7054 if (env->cr[4] & CR4_OSFXSR_MASK) {
7055 hflags |= HF_OSFXSR_MASK;
7056 }
7057
7058 if (env->efer & MSR_EFER_LMA) {
7059 hflags |= HF_LMA_MASK;
7060 }
7061
7062 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
7063 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
7064 } else {
7065 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
7066 (DESC_B_SHIFT - HF_CS32_SHIFT);
7067 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
7068 (DESC_B_SHIFT - HF_SS32_SHIFT);
7069 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
7070 !(hflags & HF_CS32_MASK)) {
7071 hflags |= HF_ADDSEG_MASK;
7072 } else {
7073 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
7074 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
7075 }
7076 }
7077 env->hflags = hflags;
7078 }
7079
7080 static Property x86_cpu_properties[] = {
7081 #ifdef CONFIG_USER_ONLY
7082 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7083 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
7084 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
7085 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
7086 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
7087 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
7088 #else
7089 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
7090 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
7091 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
7092 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
7093 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
7094 #endif
7095 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
7096 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
7097
7098 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
7099 HYPERV_SPINLOCK_NEVER_RETRY),
7100 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
7101 HYPERV_FEAT_RELAXED, 0),
7102 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
7103 HYPERV_FEAT_VAPIC, 0),
7104 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
7105 HYPERV_FEAT_TIME, 0),
7106 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
7107 HYPERV_FEAT_CRASH, 0),
7108 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
7109 HYPERV_FEAT_RESET, 0),
7110 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
7111 HYPERV_FEAT_VPINDEX, 0),
7112 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
7113 HYPERV_FEAT_RUNTIME, 0),
7114 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
7115 HYPERV_FEAT_SYNIC, 0),
7116 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
7117 HYPERV_FEAT_STIMER, 0),
7118 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
7119 HYPERV_FEAT_FREQUENCIES, 0),
7120 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
7121 HYPERV_FEAT_REENLIGHTENMENT, 0),
7122 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
7123 HYPERV_FEAT_TLBFLUSH, 0),
7124 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
7125 HYPERV_FEAT_EVMCS, 0),
7126 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
7127 HYPERV_FEAT_IPI, 0),
7128 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
7129 HYPERV_FEAT_STIMER_DIRECT, 0),
7130 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
7131 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
7132 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
7133
7134 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
7135 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
7136 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
7137 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
7138 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
7139 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
7140 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
7141 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
7142 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
7143 UINT32_MAX),
7144 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
7145 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
7146 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
7147 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
7148 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
7149 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
7150 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
7151 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
7152 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
7153 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
7154 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
7155 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
7156 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
7157 false),
7158 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
7159 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
7160 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
7161 true),
7162 /*
7163 * lecacy_cache defaults to true unless the CPU model provides its
7164 * own cache information (see x86_cpu_load_def()).
7165 */
7166 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
7167
7168 /*
7169 * From "Requirements for Implementing the Microsoft
7170 * Hypervisor Interface":
7171 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7172 *
7173 * "Starting with Windows Server 2012 and Windows 8, if
7174 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7175 * the hypervisor imposes no specific limit to the number of VPs.
7176 * In this case, Windows Server 2012 guest VMs may use more than
7177 * 64 VPs, up to the maximum supported number of processors applicable
7178 * to the specific Windows version being used."
7179 */
7180 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
7181 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
7182 false),
7183 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
7184 true),
7185 DEFINE_PROP_END_OF_LIST()
7186 };
7187
7188 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
7189 {
7190 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7191 CPUClass *cc = CPU_CLASS(oc);
7192 DeviceClass *dc = DEVICE_CLASS(oc);
7193
7194 device_class_set_parent_realize(dc, x86_cpu_realizefn,
7195 &xcc->parent_realize);
7196 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
7197 &xcc->parent_unrealize);
7198 device_class_set_props(dc, x86_cpu_properties);
7199
7200 cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset);
7201 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
7202
7203 cc->class_by_name = x86_cpu_class_by_name;
7204 cc->parse_features = x86_cpu_parse_featurestr;
7205 cc->has_work = x86_cpu_has_work;
7206 #ifdef CONFIG_TCG
7207 cc->do_interrupt = x86_cpu_do_interrupt;
7208 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
7209 #endif
7210 cc->dump_state = x86_cpu_dump_state;
7211 cc->get_crash_info = x86_cpu_get_crash_info;
7212 cc->set_pc = x86_cpu_set_pc;
7213 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
7214 cc->gdb_read_register = x86_cpu_gdb_read_register;
7215 cc->gdb_write_register = x86_cpu_gdb_write_register;
7216 cc->get_arch_id = x86_cpu_get_arch_id;
7217 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7218 #ifndef CONFIG_USER_ONLY
7219 cc->asidx_from_attrs = x86_asidx_from_attrs;
7220 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
7221 cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
7222 cc->write_elf64_note = x86_cpu_write_elf64_note;
7223 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
7224 cc->write_elf32_note = x86_cpu_write_elf32_note;
7225 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
7226 cc->vmsd = &vmstate_x86_cpu;
7227 #endif
7228 cc->gdb_arch_name = x86_gdb_arch_name;
7229 #ifdef TARGET_X86_64
7230 cc->gdb_core_xml_file = "i386-64bit.xml";
7231 cc->gdb_num_core_regs = 66;
7232 #else
7233 cc->gdb_core_xml_file = "i386-32bit.xml";
7234 cc->gdb_num_core_regs = 50;
7235 #endif
7236 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
7237 cc->debug_excp_handler = breakpoint_handler;
7238 #endif
7239 cc->cpu_exec_enter = x86_cpu_exec_enter;
7240 cc->cpu_exec_exit = x86_cpu_exec_exit;
7241 #ifdef CONFIG_TCG
7242 cc->tcg_initialize = tcg_x86_init;
7243 cc->tlb_fill = x86_cpu_tlb_fill;
7244 #endif
7245 cc->disas_set_info = x86_disas_set_info;
7246
7247 dc->user_creatable = true;
7248 }
7249
7250 static const TypeInfo x86_cpu_type_info = {
7251 .name = TYPE_X86_CPU,
7252 .parent = TYPE_CPU,
7253 .instance_size = sizeof(X86CPU),
7254 .instance_init = x86_cpu_initfn,
7255 .abstract = true,
7256 .class_size = sizeof(X86CPUClass),
7257 .class_init = x86_cpu_common_class_init,
7258 };
7259
7260
7261 /* "base" CPU model, used by query-cpu-model-expansion */
7262 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7263 {
7264 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7265
7266 xcc->static_model = true;
7267 xcc->migration_safe = true;
7268 xcc->model_description = "base CPU model type with no features enabled";
7269 xcc->ordering = 8;
7270 }
7271
7272 static const TypeInfo x86_base_cpu_type_info = {
7273 .name = X86_CPU_TYPE_NAME("base"),
7274 .parent = TYPE_X86_CPU,
7275 .class_init = x86_cpu_base_class_init,
7276 };
7277
7278 static void x86_cpu_register_types(void)
7279 {
7280 int i;
7281
7282 type_register_static(&x86_cpu_type_info);
7283 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
7284 x86_register_cpudef_types(&builtin_x86_defs[i]);
7285 }
7286 type_register_static(&max_x86_cpu_type_info);
7287 type_register_static(&x86_base_cpu_type_info);
7288 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
7289 type_register_static(&host_x86_cpu_type_info);
7290 #endif
7291 }
7292
7293 type_init(x86_cpu_register_types)
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