2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
26 #include "exec/exec-all.h"
27 #include "sysemu/kvm.h"
28 #include "sysemu/hvf.h"
29 #include "sysemu/cpus.h"
33 #include "qemu/error-report.h"
34 #include "qemu/option.h"
35 #include "qemu/config-file.h"
36 #include "qapi/error.h"
37 #include "qapi/qapi-visit-misc.h"
38 #include "qapi/qapi-visit-run-state.h"
39 #include "qapi/qmp/qdict.h"
40 #include "qapi/qmp/qerror.h"
41 #include "qapi/visitor.h"
42 #include "qom/qom-qobject.h"
43 #include "sysemu/arch_init.h"
45 #include "standard-headers/asm-x86/kvm_para.h"
47 #include "sysemu/sysemu.h"
48 #include "hw/qdev-properties.h"
49 #include "hw/i386/topology.h"
50 #ifndef CONFIG_USER_ONLY
51 #include "exec/address-spaces.h"
53 #include "hw/xen/xen.h"
54 #include "hw/i386/apic_internal.h"
57 #include "disas/capstone.h"
59 /* Helpers for building CPUID[2] descriptors: */
61 struct CPUID2CacheDescriptorInfo
{
70 * Known CPUID 2 cache descriptors.
71 * From Intel SDM Volume 2A, CPUID instruction
73 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors
[] = {
74 [0x06] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 8 * KiB
,
75 .associativity
= 4, .line_size
= 32, },
76 [0x08] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 16 * KiB
,
77 .associativity
= 4, .line_size
= 32, },
78 [0x09] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 32 * KiB
,
79 .associativity
= 4, .line_size
= 64, },
80 [0x0A] = { .level
= 1, .type
= DATA_CACHE
, .size
= 8 * KiB
,
81 .associativity
= 2, .line_size
= 32, },
82 [0x0C] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
83 .associativity
= 4, .line_size
= 32, },
84 [0x0D] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
85 .associativity
= 4, .line_size
= 64, },
86 [0x0E] = { .level
= 1, .type
= DATA_CACHE
, .size
= 24 * KiB
,
87 .associativity
= 6, .line_size
= 64, },
88 [0x1D] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 128 * KiB
,
89 .associativity
= 2, .line_size
= 64, },
90 [0x21] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
91 .associativity
= 8, .line_size
= 64, },
92 /* lines per sector is not supported cpuid2_cache_descriptor(),
93 * so descriptors 0x22, 0x23 are not included
95 [0x24] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
96 .associativity
= 16, .line_size
= 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x25, 0x20 are not included
100 [0x2C] = { .level
= 1, .type
= DATA_CACHE
, .size
= 32 * KiB
,
101 .associativity
= 8, .line_size
= 64, },
102 [0x30] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 32 * KiB
,
103 .associativity
= 8, .line_size
= 64, },
104 [0x41] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 128 * KiB
,
105 .associativity
= 4, .line_size
= 32, },
106 [0x42] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
107 .associativity
= 4, .line_size
= 32, },
108 [0x43] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
109 .associativity
= 4, .line_size
= 32, },
110 [0x44] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
111 .associativity
= 4, .line_size
= 32, },
112 [0x45] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
113 .associativity
= 4, .line_size
= 32, },
114 [0x46] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
115 .associativity
= 4, .line_size
= 64, },
116 [0x47] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
117 .associativity
= 8, .line_size
= 64, },
118 [0x48] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 3 * MiB
,
119 .associativity
= 12, .line_size
= 64, },
120 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
121 [0x4A] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
122 .associativity
= 12, .line_size
= 64, },
123 [0x4B] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
124 .associativity
= 16, .line_size
= 64, },
125 [0x4C] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 12 * MiB
,
126 .associativity
= 12, .line_size
= 64, },
127 [0x4D] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 16 * MiB
,
128 .associativity
= 16, .line_size
= 64, },
129 [0x4E] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
130 .associativity
= 24, .line_size
= 64, },
131 [0x60] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
132 .associativity
= 8, .line_size
= 64, },
133 [0x66] = { .level
= 1, .type
= DATA_CACHE
, .size
= 8 * KiB
,
134 .associativity
= 4, .line_size
= 64, },
135 [0x67] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
136 .associativity
= 4, .line_size
= 64, },
137 [0x68] = { .level
= 1, .type
= DATA_CACHE
, .size
= 32 * KiB
,
138 .associativity
= 4, .line_size
= 64, },
139 [0x78] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
140 .associativity
= 4, .line_size
= 64, },
141 /* lines per sector is not supported cpuid2_cache_descriptor(),
142 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
144 [0x7D] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
145 .associativity
= 8, .line_size
= 64, },
146 [0x7F] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
147 .associativity
= 2, .line_size
= 64, },
148 [0x80] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
149 .associativity
= 8, .line_size
= 64, },
150 [0x82] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
151 .associativity
= 8, .line_size
= 32, },
152 [0x83] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
153 .associativity
= 8, .line_size
= 32, },
154 [0x84] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
155 .associativity
= 8, .line_size
= 32, },
156 [0x85] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
157 .associativity
= 8, .line_size
= 32, },
158 [0x86] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
159 .associativity
= 4, .line_size
= 64, },
160 [0x87] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
161 .associativity
= 8, .line_size
= 64, },
162 [0xD0] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
163 .associativity
= 4, .line_size
= 64, },
164 [0xD1] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
165 .associativity
= 4, .line_size
= 64, },
166 [0xD2] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
167 .associativity
= 4, .line_size
= 64, },
168 [0xD6] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
169 .associativity
= 8, .line_size
= 64, },
170 [0xD7] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
171 .associativity
= 8, .line_size
= 64, },
172 [0xD8] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
173 .associativity
= 8, .line_size
= 64, },
174 [0xDC] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1.5 * MiB
,
175 .associativity
= 12, .line_size
= 64, },
176 [0xDD] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 3 * MiB
,
177 .associativity
= 12, .line_size
= 64, },
178 [0xDE] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
179 .associativity
= 12, .line_size
= 64, },
180 [0xE2] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
181 .associativity
= 16, .line_size
= 64, },
182 [0xE3] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
183 .associativity
= 16, .line_size
= 64, },
184 [0xE4] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
185 .associativity
= 16, .line_size
= 64, },
186 [0xEA] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 12 * MiB
,
187 .associativity
= 24, .line_size
= 64, },
188 [0xEB] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 18 * MiB
,
189 .associativity
= 24, .line_size
= 64, },
190 [0xEC] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 24 * MiB
,
191 .associativity
= 24, .line_size
= 64, },
195 * "CPUID leaf 2 does not report cache descriptor information,
196 * use CPUID leaf 4 to query cache parameters"
198 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
201 * Return a CPUID 2 cache descriptor for a given cache.
202 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
204 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo
*cache
)
208 assert(cache
->size
> 0);
209 assert(cache
->level
> 0);
210 assert(cache
->line_size
> 0);
211 assert(cache
->associativity
> 0);
212 for (i
= 0; i
< ARRAY_SIZE(cpuid2_cache_descriptors
); i
++) {
213 struct CPUID2CacheDescriptorInfo
*d
= &cpuid2_cache_descriptors
[i
];
214 if (d
->level
== cache
->level
&& d
->type
== cache
->type
&&
215 d
->size
== cache
->size
&& d
->line_size
== cache
->line_size
&&
216 d
->associativity
== cache
->associativity
) {
221 return CACHE_DESCRIPTOR_UNAVAILABLE
;
224 /* CPUID Leaf 4 constants: */
227 #define CACHE_TYPE_D 1
228 #define CACHE_TYPE_I 2
229 #define CACHE_TYPE_UNIFIED 3
231 #define CACHE_LEVEL(l) (l << 5)
233 #define CACHE_SELF_INIT_LEVEL (1 << 8)
236 #define CACHE_NO_INVD_SHARING (1 << 0)
237 #define CACHE_INCLUSIVE (1 << 1)
238 #define CACHE_COMPLEX_IDX (1 << 2)
240 /* Encode CacheType for CPUID[4].EAX */
241 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
242 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
243 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
244 0 /* Invalid value */)
247 /* Encode cache info for CPUID[4] */
248 static void encode_cache_cpuid4(CPUCacheInfo
*cache
,
249 int num_apic_ids
, int num_cores
,
250 uint32_t *eax
, uint32_t *ebx
,
251 uint32_t *ecx
, uint32_t *edx
)
253 assert(cache
->size
== cache
->line_size
* cache
->associativity
*
254 cache
->partitions
* cache
->sets
);
256 assert(num_apic_ids
> 0);
257 *eax
= CACHE_TYPE(cache
->type
) |
258 CACHE_LEVEL(cache
->level
) |
259 (cache
->self_init
? CACHE_SELF_INIT_LEVEL
: 0) |
260 ((num_cores
- 1) << 26) |
261 ((num_apic_ids
- 1) << 14);
263 assert(cache
->line_size
> 0);
264 assert(cache
->partitions
> 0);
265 assert(cache
->associativity
> 0);
266 /* We don't implement fully-associative caches */
267 assert(cache
->associativity
< cache
->sets
);
268 *ebx
= (cache
->line_size
- 1) |
269 ((cache
->partitions
- 1) << 12) |
270 ((cache
->associativity
- 1) << 22);
272 assert(cache
->sets
> 0);
273 *ecx
= cache
->sets
- 1;
275 *edx
= (cache
->no_invd_sharing
? CACHE_NO_INVD_SHARING
: 0) |
276 (cache
->inclusive
? CACHE_INCLUSIVE
: 0) |
277 (cache
->complex_indexing
? CACHE_COMPLEX_IDX
: 0);
280 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
281 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo
*cache
)
283 assert(cache
->size
% 1024 == 0);
284 assert(cache
->lines_per_tag
> 0);
285 assert(cache
->associativity
> 0);
286 assert(cache
->line_size
> 0);
287 return ((cache
->size
/ 1024) << 24) | (cache
->associativity
<< 16) |
288 (cache
->lines_per_tag
<< 8) | (cache
->line_size
);
291 #define ASSOC_FULL 0xFF
293 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
294 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
304 a == ASSOC_FULL ? 0xF : \
305 0 /* invalid value */)
308 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
311 static void encode_cache_cpuid80000006(CPUCacheInfo
*l2
,
313 uint32_t *ecx
, uint32_t *edx
)
315 assert(l2
->size
% 1024 == 0);
316 assert(l2
->associativity
> 0);
317 assert(l2
->lines_per_tag
> 0);
318 assert(l2
->line_size
> 0);
319 *ecx
= ((l2
->size
/ 1024) << 16) |
320 (AMD_ENC_ASSOC(l2
->associativity
) << 12) |
321 (l2
->lines_per_tag
<< 8) | (l2
->line_size
);
324 assert(l3
->size
% (512 * 1024) == 0);
325 assert(l3
->associativity
> 0);
326 assert(l3
->lines_per_tag
> 0);
327 assert(l3
->line_size
> 0);
328 *edx
= ((l3
->size
/ (512 * 1024)) << 18) |
329 (AMD_ENC_ASSOC(l3
->associativity
) << 12) |
330 (l3
->lines_per_tag
<< 8) | (l3
->line_size
);
337 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
338 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
339 * Define the constants to build the cpu topology. Right now, TOPOEXT
340 * feature is enabled only on EPYC. So, these constants are based on
341 * EPYC supported configurations. We may need to handle the cases if
342 * these values change in future.
344 /* Maximum core complexes in a node */
346 /* Maximum cores in a core complex */
347 #define MAX_CORES_IN_CCX 4
348 /* Maximum cores in a node */
349 #define MAX_CORES_IN_NODE 8
350 /* Maximum nodes in a socket */
351 #define MAX_NODES_PER_SOCKET 4
354 * Figure out the number of nodes required to build this config.
355 * Max cores in a node is 8
357 static int nodes_in_socket(int nr_cores
)
361 nodes
= DIV_ROUND_UP(nr_cores
, MAX_CORES_IN_NODE
);
363 /* Hardware does not support config with 3 nodes, return 4 in that case */
364 return (nodes
== 3) ? 4 : nodes
;
368 * Decide the number of cores in a core complex with the given nr_cores using
369 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
370 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
371 * L3 cache is shared across all cores in a core complex. So, this will also
372 * tell us how many cores are sharing the L3 cache.
374 static int cores_in_core_complex(int nr_cores
)
378 /* Check if we can fit all the cores in one core complex */
379 if (nr_cores
<= MAX_CORES_IN_CCX
) {
382 /* Get the number of nodes required to build this config */
383 nodes
= nodes_in_socket(nr_cores
);
386 * Divide the cores accros all the core complexes
387 * Return rounded up value
389 return DIV_ROUND_UP(nr_cores
, nodes
* MAX_CCX
);
392 /* Encode cache info for CPUID[8000001D] */
393 static void encode_cache_cpuid8000001d(CPUCacheInfo
*cache
, CPUState
*cs
,
394 uint32_t *eax
, uint32_t *ebx
,
395 uint32_t *ecx
, uint32_t *edx
)
398 assert(cache
->size
== cache
->line_size
* cache
->associativity
*
399 cache
->partitions
* cache
->sets
);
401 *eax
= CACHE_TYPE(cache
->type
) | CACHE_LEVEL(cache
->level
) |
402 (cache
->self_init
? CACHE_SELF_INIT_LEVEL
: 0);
404 /* L3 is shared among multiple cores */
405 if (cache
->level
== 3) {
406 l3_cores
= cores_in_core_complex(cs
->nr_cores
);
407 *eax
|= ((l3_cores
* cs
->nr_threads
) - 1) << 14;
409 *eax
|= ((cs
->nr_threads
- 1) << 14);
412 assert(cache
->line_size
> 0);
413 assert(cache
->partitions
> 0);
414 assert(cache
->associativity
> 0);
415 /* We don't implement fully-associative caches */
416 assert(cache
->associativity
< cache
->sets
);
417 *ebx
= (cache
->line_size
- 1) |
418 ((cache
->partitions
- 1) << 12) |
419 ((cache
->associativity
- 1) << 22);
421 assert(cache
->sets
> 0);
422 *ecx
= cache
->sets
- 1;
424 *edx
= (cache
->no_invd_sharing
? CACHE_NO_INVD_SHARING
: 0) |
425 (cache
->inclusive
? CACHE_INCLUSIVE
: 0) |
426 (cache
->complex_indexing
? CACHE_COMPLEX_IDX
: 0);
429 /* Data structure to hold the configuration info for a given core index */
430 struct core_topology
{
431 /* core complex id of the current core index */
434 * Adjusted core index for this core in the topology
435 * This can be 0,1,2,3 with max 4 cores in a core complex
438 /* Node id for this core index */
440 /* Number of nodes in this config */
445 * Build the configuration closely match the EPYC hardware. Using the EPYC
446 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
447 * right now. This could change in future.
448 * nr_cores : Total number of cores in the config
449 * core_id : Core index of the current CPU
450 * topo : Data structure to hold all the config info for this core index
452 static void build_core_topology(int nr_cores
, int core_id
,
453 struct core_topology
*topo
)
455 int nodes
, cores_in_ccx
;
457 /* First get the number of nodes required */
458 nodes
= nodes_in_socket(nr_cores
);
460 cores_in_ccx
= cores_in_core_complex(nr_cores
);
462 topo
->node_id
= core_id
/ (cores_in_ccx
* MAX_CCX
);
463 topo
->ccx_id
= (core_id
% (cores_in_ccx
* MAX_CCX
)) / cores_in_ccx
;
464 topo
->core_id
= core_id
% cores_in_ccx
;
465 topo
->num_nodes
= nodes
;
468 /* Encode cache info for CPUID[8000001E] */
469 static void encode_topo_cpuid8000001e(CPUState
*cs
, X86CPU
*cpu
,
470 uint32_t *eax
, uint32_t *ebx
,
471 uint32_t *ecx
, uint32_t *edx
)
473 struct core_topology topo
= {0};
477 build_core_topology(cs
->nr_cores
, cpu
->core_id
, &topo
);
480 * CPUID_Fn8000001E_EBX
482 * 15:8 Threads per core (The number of threads per core is
483 * Threads per core + 1)
484 * 7:0 Core id (see bit decoding below)
494 if (cs
->nr_threads
- 1) {
495 *ebx
= ((cs
->nr_threads
- 1) << 8) | (topo
.node_id
<< 3) |
496 (topo
.ccx_id
<< 2) | topo
.core_id
;
498 *ebx
= (topo
.node_id
<< 4) | (topo
.ccx_id
<< 3) | topo
.core_id
;
501 * CPUID_Fn8000001E_ECX
503 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
504 * 7:0 Node id (see bit decoding below)
508 if (topo
.num_nodes
<= 4) {
509 *ecx
= ((topo
.num_nodes
- 1) << 8) | (cpu
->socket_id
<< 2) |
513 * Node id fix up. Actual hardware supports up to 4 nodes. But with
514 * more than 32 cores, we may end up with more than 4 nodes.
515 * Node id is a combination of socket id and node id. Only requirement
516 * here is that this number should be unique accross the system.
517 * Shift the socket id to accommodate more nodes. We dont expect both
518 * socket id and node id to be big number at the same time. This is not
519 * an ideal config but we need to to support it. Max nodes we can have
520 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
521 * 5 bits for nodes. Find the left most set bit to represent the total
522 * number of nodes. find_last_bit returns last set bit(0 based). Left
523 * shift(+1) the socket id to represent all the nodes.
525 nodes
= topo
.num_nodes
- 1;
526 shift
= find_last_bit(&nodes
, 8);
527 *ecx
= ((topo
.num_nodes
- 1) << 8) | (cpu
->socket_id
<< (shift
+ 1)) |
534 * Definitions of the hardcoded cache entries we expose:
535 * These are legacy cache values. If there is a need to change any
536 * of these values please use builtin_x86_defs
540 static CPUCacheInfo legacy_l1d_cache
= {
549 .no_invd_sharing
= true,
552 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
553 static CPUCacheInfo legacy_l1d_cache_amd
= {
563 .no_invd_sharing
= true,
566 /* L1 instruction cache: */
567 static CPUCacheInfo legacy_l1i_cache
= {
568 .type
= INSTRUCTION_CACHE
,
576 .no_invd_sharing
= true,
579 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
580 static CPUCacheInfo legacy_l1i_cache_amd
= {
581 .type
= INSTRUCTION_CACHE
,
590 .no_invd_sharing
= true,
593 /* Level 2 unified cache: */
594 static CPUCacheInfo legacy_l2_cache
= {
595 .type
= UNIFIED_CACHE
,
603 .no_invd_sharing
= true,
606 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
607 static CPUCacheInfo legacy_l2_cache_cpuid2
= {
608 .type
= UNIFIED_CACHE
,
616 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
617 static CPUCacheInfo legacy_l2_cache_amd
= {
618 .type
= UNIFIED_CACHE
,
628 /* Level 3 unified cache: */
629 static CPUCacheInfo legacy_l3_cache
= {
630 .type
= UNIFIED_CACHE
,
640 .complex_indexing
= true,
643 /* TLB definitions: */
645 #define L1_DTLB_2M_ASSOC 1
646 #define L1_DTLB_2M_ENTRIES 255
647 #define L1_DTLB_4K_ASSOC 1
648 #define L1_DTLB_4K_ENTRIES 255
650 #define L1_ITLB_2M_ASSOC 1
651 #define L1_ITLB_2M_ENTRIES 255
652 #define L1_ITLB_4K_ASSOC 1
653 #define L1_ITLB_4K_ENTRIES 255
655 #define L2_DTLB_2M_ASSOC 0 /* disabled */
656 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
657 #define L2_DTLB_4K_ASSOC 4
658 #define L2_DTLB_4K_ENTRIES 512
660 #define L2_ITLB_2M_ASSOC 0 /* disabled */
661 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
662 #define L2_ITLB_4K_ASSOC 4
663 #define L2_ITLB_4K_ENTRIES 512
665 /* CPUID Leaf 0x14 constants: */
666 #define INTEL_PT_MAX_SUBLEAF 0x1
668 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
669 * MSR can be accessed;
670 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
671 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
672 * of Intel PT MSRs across warm reset;
673 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
675 #define INTEL_PT_MINIMAL_EBX 0xf
677 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
678 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
680 * bit[01]: ToPA tables can hold any number of output entries, up to the
681 * maximum allowed by the MaskOrTableOffset field of
682 * IA32_RTIT_OUTPUT_MASK_PTRS;
683 * bit[02]: Support Single-Range Output scheme;
685 #define INTEL_PT_MINIMAL_ECX 0x7
686 /* generated packets which contain IP payloads have LIP values */
687 #define INTEL_PT_IP_LIP (1 << 31)
688 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
689 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
690 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
691 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
692 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
694 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
695 uint32_t vendor2
, uint32_t vendor3
)
698 for (i
= 0; i
< 4; i
++) {
699 dst
[i
] = vendor1
>> (8 * i
);
700 dst
[i
+ 4] = vendor2
>> (8 * i
);
701 dst
[i
+ 8] = vendor3
>> (8 * i
);
703 dst
[CPUID_VENDOR_SZ
] = '\0';
706 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
707 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
708 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
709 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
710 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
711 CPUID_PSE36 | CPUID_FXSR)
712 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
713 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
714 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
715 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
716 CPUID_PAE | CPUID_SEP | CPUID_APIC)
718 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
719 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
720 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
721 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
722 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
723 /* partly implemented:
724 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
726 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
727 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
728 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
729 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
730 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
731 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
733 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
734 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
735 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
736 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
737 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
740 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
742 #define TCG_EXT2_X86_64_FEATURES 0
745 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
746 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
747 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
748 TCG_EXT2_X86_64_FEATURES)
749 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
750 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
751 #define TCG_EXT4_FEATURES 0
752 #define TCG_SVM_FEATURES CPUID_SVM_NPT
753 #define TCG_KVM_FEATURES 0
754 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
755 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
756 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
757 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
760 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
761 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
762 CPUID_7_0_EBX_RDSEED */
763 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
764 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
766 #define TCG_7_0_EDX_FEATURES 0
767 #define TCG_APM_FEATURES 0
768 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
769 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
771 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
773 typedef enum FeatureWordType
{
778 typedef struct FeatureWordInfo
{
779 FeatureWordType type
;
780 /* feature flags names are taken from "Intel Processor Identification and
781 * the CPUID Instruction" and AMD's "CPUID Specification".
782 * In cases of disagreement between feature naming conventions,
783 * aliases may be added.
785 const char *feat_names
[32];
787 /* If type==CPUID_FEATURE_WORD */
789 uint32_t eax
; /* Input EAX for CPUID */
790 bool needs_ecx
; /* CPUID instruction uses ECX as input */
791 uint32_t ecx
; /* Input ECX value for CPUID */
792 int reg
; /* output register (R_* constant) */
794 /* If type==MSR_FEATURE_WORD */
797 struct { /*CPUID that enumerate this MSR*/
798 FeatureWord cpuid_class
;
803 uint32_t tcg_features
; /* Feature flags supported by TCG */
804 uint32_t unmigratable_flags
; /* Feature flags known to be unmigratable */
805 uint32_t migratable_flags
; /* Feature flags known to be migratable */
806 /* Features that shouldn't be auto-enabled by "-cpu host" */
807 uint32_t no_autoenable_flags
;
810 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
812 .type
= CPUID_FEATURE_WORD
,
814 "fpu", "vme", "de", "pse",
815 "tsc", "msr", "pae", "mce",
816 "cx8", "apic", NULL
, "sep",
817 "mtrr", "pge", "mca", "cmov",
818 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
819 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
820 "fxsr", "sse", "sse2", "ss",
821 "ht" /* Intel htt */, "tm", "ia64", "pbe",
823 .cpuid
= {.eax
= 1, .reg
= R_EDX
, },
824 .tcg_features
= TCG_FEATURES
,
827 .type
= CPUID_FEATURE_WORD
,
829 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
830 "ds-cpl", "vmx", "smx", "est",
831 "tm2", "ssse3", "cid", NULL
,
832 "fma", "cx16", "xtpr", "pdcm",
833 NULL
, "pcid", "dca", "sse4.1",
834 "sse4.2", "x2apic", "movbe", "popcnt",
835 "tsc-deadline", "aes", "xsave", NULL
/* osxsave */,
836 "avx", "f16c", "rdrand", "hypervisor",
838 .cpuid
= { .eax
= 1, .reg
= R_ECX
, },
839 .tcg_features
= TCG_EXT_FEATURES
,
841 /* Feature names that are already defined on feature_name[] but
842 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
843 * names on feat_names below. They are copied automatically
844 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
846 [FEAT_8000_0001_EDX
] = {
847 .type
= CPUID_FEATURE_WORD
,
849 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
850 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
851 NULL
/* cx8 */, NULL
/* apic */, NULL
, "syscall",
852 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
853 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
854 "nx", NULL
, "mmxext", NULL
/* mmx */,
855 NULL
/* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
856 NULL
, "lm", "3dnowext", "3dnow",
858 .cpuid
= { .eax
= 0x80000001, .reg
= R_EDX
, },
859 .tcg_features
= TCG_EXT2_FEATURES
,
861 [FEAT_8000_0001_ECX
] = {
862 .type
= CPUID_FEATURE_WORD
,
864 "lahf-lm", "cmp-legacy", "svm", "extapic",
865 "cr8legacy", "abm", "sse4a", "misalignsse",
866 "3dnowprefetch", "osvw", "ibs", "xop",
867 "skinit", "wdt", NULL
, "lwp",
868 "fma4", "tce", NULL
, "nodeid-msr",
869 NULL
, "tbm", "topoext", "perfctr-core",
870 "perfctr-nb", NULL
, NULL
, NULL
,
871 NULL
, NULL
, NULL
, NULL
,
873 .cpuid
= { .eax
= 0x80000001, .reg
= R_ECX
, },
874 .tcg_features
= TCG_EXT3_FEATURES
,
876 * TOPOEXT is always allowed but can't be enabled blindly by
877 * "-cpu host", as it requires consistent cache topology info
878 * to be provided so it doesn't confuse guests.
880 .no_autoenable_flags
= CPUID_EXT3_TOPOEXT
,
882 [FEAT_C000_0001_EDX
] = {
883 .type
= CPUID_FEATURE_WORD
,
885 NULL
, NULL
, "xstore", "xstore-en",
886 NULL
, NULL
, "xcrypt", "xcrypt-en",
887 "ace2", "ace2-en", "phe", "phe-en",
888 "pmm", "pmm-en", NULL
, NULL
,
889 NULL
, NULL
, NULL
, NULL
,
890 NULL
, NULL
, NULL
, NULL
,
891 NULL
, NULL
, NULL
, NULL
,
892 NULL
, NULL
, NULL
, NULL
,
894 .cpuid
= { .eax
= 0xC0000001, .reg
= R_EDX
, },
895 .tcg_features
= TCG_EXT4_FEATURES
,
898 .type
= CPUID_FEATURE_WORD
,
900 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
901 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
902 NULL
, "kvm-pv-tlb-flush", NULL
, "kvm-pv-ipi",
903 NULL
, NULL
, NULL
, NULL
,
904 NULL
, NULL
, NULL
, NULL
,
905 NULL
, NULL
, NULL
, NULL
,
906 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
907 NULL
, NULL
, NULL
, NULL
,
909 .cpuid
= { .eax
= KVM_CPUID_FEATURES
, .reg
= R_EAX
, },
910 .tcg_features
= TCG_KVM_FEATURES
,
913 .type
= CPUID_FEATURE_WORD
,
915 "kvm-hint-dedicated", NULL
, NULL
, NULL
,
916 NULL
, NULL
, NULL
, NULL
,
917 NULL
, NULL
, NULL
, NULL
,
918 NULL
, NULL
, NULL
, NULL
,
919 NULL
, NULL
, NULL
, NULL
,
920 NULL
, NULL
, NULL
, NULL
,
921 NULL
, NULL
, NULL
, NULL
,
922 NULL
, NULL
, NULL
, NULL
,
924 .cpuid
= { .eax
= KVM_CPUID_FEATURES
, .reg
= R_EDX
, },
925 .tcg_features
= TCG_KVM_FEATURES
,
927 * KVM hints aren't auto-enabled by -cpu host, they need to be
928 * explicitly enabled in the command-line.
930 .no_autoenable_flags
= ~0U,
933 * .feat_names are commented out for Hyper-V enlightenments because we
934 * don't want to have two different ways for enabling them on QEMU command
935 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
936 * enabling several feature bits simultaneously, exposing these bits
937 * individually may just confuse guests.
939 [FEAT_HYPERV_EAX
] = {
940 .type
= CPUID_FEATURE_WORD
,
942 NULL
/* hv_msr_vp_runtime_access */, NULL
/* hv_msr_time_refcount_access */,
943 NULL
/* hv_msr_synic_access */, NULL
/* hv_msr_stimer_access */,
944 NULL
/* hv_msr_apic_access */, NULL
/* hv_msr_hypercall_access */,
945 NULL
/* hv_vpindex_access */, NULL
/* hv_msr_reset_access */,
946 NULL
/* hv_msr_stats_access */, NULL
/* hv_reftsc_access */,
947 NULL
/* hv_msr_idle_access */, NULL
/* hv_msr_frequency_access */,
948 NULL
/* hv_msr_debug_access */, NULL
/* hv_msr_reenlightenment_access */,
950 NULL
, NULL
, NULL
, NULL
,
951 NULL
, NULL
, NULL
, NULL
,
952 NULL
, NULL
, NULL
, NULL
,
953 NULL
, NULL
, NULL
, NULL
,
955 .cpuid
= { .eax
= 0x40000003, .reg
= R_EAX
, },
957 [FEAT_HYPERV_EBX
] = {
958 .type
= CPUID_FEATURE_WORD
,
960 NULL
/* hv_create_partitions */, NULL
/* hv_access_partition_id */,
961 NULL
/* hv_access_memory_pool */, NULL
/* hv_adjust_message_buffers */,
962 NULL
/* hv_post_messages */, NULL
/* hv_signal_events */,
963 NULL
/* hv_create_port */, NULL
/* hv_connect_port */,
964 NULL
/* hv_access_stats */, NULL
, NULL
, NULL
/* hv_debugging */,
965 NULL
/* hv_cpu_power_management */, NULL
/* hv_configure_profiler */,
967 NULL
, NULL
, NULL
, NULL
,
968 NULL
, NULL
, NULL
, NULL
,
969 NULL
, NULL
, NULL
, NULL
,
970 NULL
, NULL
, NULL
, NULL
,
972 .cpuid
= { .eax
= 0x40000003, .reg
= R_EBX
, },
974 [FEAT_HYPERV_EDX
] = {
975 .type
= CPUID_FEATURE_WORD
,
977 NULL
/* hv_mwait */, NULL
/* hv_guest_debugging */,
978 NULL
/* hv_perf_monitor */, NULL
/* hv_cpu_dynamic_part */,
979 NULL
/* hv_hypercall_params_xmm */, NULL
/* hv_guest_idle_state */,
981 NULL
, NULL
, NULL
/* hv_guest_crash_msr */, NULL
,
982 NULL
, NULL
, NULL
, NULL
,
983 NULL
, NULL
, NULL
, NULL
,
984 NULL
, NULL
, NULL
, NULL
,
985 NULL
, NULL
, NULL
, NULL
,
986 NULL
, NULL
, NULL
, NULL
,
988 .cpuid
= { .eax
= 0x40000003, .reg
= R_EDX
, },
990 [FEAT_HV_RECOMM_EAX
] = {
991 .type
= CPUID_FEATURE_WORD
,
993 NULL
/* hv_recommend_pv_as_switch */,
994 NULL
/* hv_recommend_pv_tlbflush_local */,
995 NULL
/* hv_recommend_pv_tlbflush_remote */,
996 NULL
/* hv_recommend_msr_apic_access */,
997 NULL
/* hv_recommend_msr_reset */,
998 NULL
/* hv_recommend_relaxed_timing */,
999 NULL
/* hv_recommend_dma_remapping */,
1000 NULL
/* hv_recommend_int_remapping */,
1001 NULL
/* hv_recommend_x2apic_msrs */,
1002 NULL
/* hv_recommend_autoeoi_deprecation */,
1003 NULL
/* hv_recommend_pv_ipi */,
1004 NULL
/* hv_recommend_ex_hypercalls */,
1005 NULL
/* hv_hypervisor_is_nested */,
1006 NULL
/* hv_recommend_int_mbec */,
1007 NULL
/* hv_recommend_evmcs */,
1009 NULL
, NULL
, NULL
, NULL
,
1010 NULL
, NULL
, NULL
, NULL
,
1011 NULL
, NULL
, NULL
, NULL
,
1012 NULL
, NULL
, NULL
, NULL
,
1014 .cpuid
= { .eax
= 0x40000004, .reg
= R_EAX
, },
1016 [FEAT_HV_NESTED_EAX
] = {
1017 .type
= CPUID_FEATURE_WORD
,
1018 .cpuid
= { .eax
= 0x4000000A, .reg
= R_EAX
, },
1021 .type
= CPUID_FEATURE_WORD
,
1023 "npt", "lbrv", "svm-lock", "nrip-save",
1024 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1025 NULL
, NULL
, "pause-filter", NULL
,
1026 "pfthreshold", NULL
, NULL
, NULL
,
1027 NULL
, NULL
, NULL
, NULL
,
1028 NULL
, NULL
, NULL
, NULL
,
1029 NULL
, NULL
, NULL
, NULL
,
1030 NULL
, NULL
, NULL
, NULL
,
1032 .cpuid
= { .eax
= 0x8000000A, .reg
= R_EDX
, },
1033 .tcg_features
= TCG_SVM_FEATURES
,
1036 .type
= CPUID_FEATURE_WORD
,
1038 "fsgsbase", "tsc-adjust", NULL
, "bmi1",
1039 "hle", "avx2", NULL
, "smep",
1040 "bmi2", "erms", "invpcid", "rtm",
1041 NULL
, NULL
, "mpx", NULL
,
1042 "avx512f", "avx512dq", "rdseed", "adx",
1043 "smap", "avx512ifma", "pcommit", "clflushopt",
1044 "clwb", "intel-pt", "avx512pf", "avx512er",
1045 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1049 .needs_ecx
= true, .ecx
= 0,
1052 .tcg_features
= TCG_7_0_EBX_FEATURES
,
1055 .type
= CPUID_FEATURE_WORD
,
1057 NULL
, "avx512vbmi", "umip", "pku",
1058 NULL
/* ospke */, NULL
, "avx512vbmi2", NULL
,
1059 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1060 "avx512bitalg", NULL
, "avx512-vpopcntdq", NULL
,
1061 "la57", NULL
, NULL
, NULL
,
1062 NULL
, NULL
, "rdpid", NULL
,
1063 NULL
, "cldemote", NULL
, "movdiri",
1064 "movdir64b", NULL
, NULL
, NULL
,
1068 .needs_ecx
= true, .ecx
= 0,
1071 .tcg_features
= TCG_7_0_ECX_FEATURES
,
1074 .type
= CPUID_FEATURE_WORD
,
1076 NULL
, NULL
, "avx512-4vnniw", "avx512-4fmaps",
1077 NULL
, NULL
, NULL
, NULL
,
1078 NULL
, NULL
, NULL
, NULL
,
1079 NULL
, NULL
, NULL
, NULL
,
1080 NULL
, NULL
, "pconfig", NULL
,
1081 NULL
, NULL
, NULL
, NULL
,
1082 NULL
, NULL
, "spec-ctrl", "stibp",
1083 NULL
, "arch-capabilities", NULL
, "ssbd",
1087 .needs_ecx
= true, .ecx
= 0,
1090 .tcg_features
= TCG_7_0_EDX_FEATURES
,
1091 .unmigratable_flags
= CPUID_7_0_EDX_ARCH_CAPABILITIES
,
1093 [FEAT_8000_0007_EDX
] = {
1094 .type
= CPUID_FEATURE_WORD
,
1096 NULL
, NULL
, NULL
, NULL
,
1097 NULL
, NULL
, NULL
, NULL
,
1098 "invtsc", NULL
, NULL
, NULL
,
1099 NULL
, NULL
, NULL
, NULL
,
1100 NULL
, NULL
, NULL
, NULL
,
1101 NULL
, NULL
, NULL
, NULL
,
1102 NULL
, NULL
, NULL
, NULL
,
1103 NULL
, NULL
, NULL
, NULL
,
1105 .cpuid
= { .eax
= 0x80000007, .reg
= R_EDX
, },
1106 .tcg_features
= TCG_APM_FEATURES
,
1107 .unmigratable_flags
= CPUID_APM_INVTSC
,
1109 [FEAT_8000_0008_EBX
] = {
1110 .type
= CPUID_FEATURE_WORD
,
1112 NULL
, NULL
, NULL
, NULL
,
1113 NULL
, NULL
, NULL
, NULL
,
1114 NULL
, "wbnoinvd", NULL
, NULL
,
1115 "ibpb", NULL
, NULL
, NULL
,
1116 NULL
, NULL
, NULL
, NULL
,
1117 NULL
, NULL
, NULL
, NULL
,
1118 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL
,
1119 NULL
, NULL
, NULL
, NULL
,
1121 .cpuid
= { .eax
= 0x80000008, .reg
= R_EBX
, },
1123 .unmigratable_flags
= 0,
1126 .type
= CPUID_FEATURE_WORD
,
1128 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1129 NULL
, NULL
, NULL
, NULL
,
1130 NULL
, NULL
, NULL
, NULL
,
1131 NULL
, NULL
, NULL
, NULL
,
1132 NULL
, NULL
, NULL
, NULL
,
1133 NULL
, NULL
, NULL
, NULL
,
1134 NULL
, NULL
, NULL
, NULL
,
1135 NULL
, NULL
, NULL
, NULL
,
1139 .needs_ecx
= true, .ecx
= 1,
1142 .tcg_features
= TCG_XSAVE_FEATURES
,
1145 .type
= CPUID_FEATURE_WORD
,
1147 NULL
, NULL
, "arat", NULL
,
1148 NULL
, NULL
, NULL
, NULL
,
1149 NULL
, NULL
, NULL
, NULL
,
1150 NULL
, NULL
, NULL
, NULL
,
1151 NULL
, NULL
, NULL
, NULL
,
1152 NULL
, NULL
, NULL
, NULL
,
1153 NULL
, NULL
, NULL
, NULL
,
1154 NULL
, NULL
, NULL
, NULL
,
1156 .cpuid
= { .eax
= 6, .reg
= R_EAX
, },
1157 .tcg_features
= TCG_6_EAX_FEATURES
,
1159 [FEAT_XSAVE_COMP_LO
] = {
1160 .type
= CPUID_FEATURE_WORD
,
1163 .needs_ecx
= true, .ecx
= 0,
1166 .tcg_features
= ~0U,
1167 .migratable_flags
= XSTATE_FP_MASK
| XSTATE_SSE_MASK
|
1168 XSTATE_YMM_MASK
| XSTATE_BNDREGS_MASK
| XSTATE_BNDCSR_MASK
|
1169 XSTATE_OPMASK_MASK
| XSTATE_ZMM_Hi256_MASK
| XSTATE_Hi16_ZMM_MASK
|
1172 [FEAT_XSAVE_COMP_HI
] = {
1173 .type
= CPUID_FEATURE_WORD
,
1176 .needs_ecx
= true, .ecx
= 0,
1179 .tcg_features
= ~0U,
1181 /*Below are MSR exposed features*/
1182 [FEAT_ARCH_CAPABILITIES
] = {
1183 .type
= MSR_FEATURE_WORD
,
1185 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1186 "ssb-no", NULL
, NULL
, NULL
,
1187 NULL
, NULL
, NULL
, NULL
,
1188 NULL
, NULL
, NULL
, NULL
,
1189 NULL
, NULL
, NULL
, NULL
,
1190 NULL
, NULL
, NULL
, NULL
,
1191 NULL
, NULL
, NULL
, NULL
,
1192 NULL
, NULL
, NULL
, NULL
,
1195 .index
= MSR_IA32_ARCH_CAPABILITIES
,
1198 CPUID_7_0_EDX_ARCH_CAPABILITIES
1204 typedef struct X86RegisterInfo32
{
1205 /* Name of register */
1207 /* QAPI enum value register */
1208 X86CPURegister32 qapi_enum
;
1209 } X86RegisterInfo32
;
1211 #define REGISTER(reg) \
1212 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1213 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
1225 typedef struct ExtSaveArea
{
1226 uint32_t feature
, bits
;
1227 uint32_t offset
, size
;
1230 static const ExtSaveArea x86_ext_save_areas
[] = {
1232 /* x87 FP state component is always enabled if XSAVE is supported */
1233 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
1234 /* x87 state is in the legacy region of the XSAVE area */
1236 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
1238 [XSTATE_SSE_BIT
] = {
1239 /* SSE state component is always enabled if XSAVE is supported */
1240 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
1241 /* SSE state is in the legacy region of the XSAVE area */
1243 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
1246 { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
1247 .offset
= offsetof(X86XSaveArea
, avx_state
),
1248 .size
= sizeof(XSaveAVX
) },
1249 [XSTATE_BNDREGS_BIT
] =
1250 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
1251 .offset
= offsetof(X86XSaveArea
, bndreg_state
),
1252 .size
= sizeof(XSaveBNDREG
) },
1253 [XSTATE_BNDCSR_BIT
] =
1254 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
1255 .offset
= offsetof(X86XSaveArea
, bndcsr_state
),
1256 .size
= sizeof(XSaveBNDCSR
) },
1257 [XSTATE_OPMASK_BIT
] =
1258 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1259 .offset
= offsetof(X86XSaveArea
, opmask_state
),
1260 .size
= sizeof(XSaveOpmask
) },
1261 [XSTATE_ZMM_Hi256_BIT
] =
1262 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1263 .offset
= offsetof(X86XSaveArea
, zmm_hi256_state
),
1264 .size
= sizeof(XSaveZMM_Hi256
) },
1265 [XSTATE_Hi16_ZMM_BIT
] =
1266 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1267 .offset
= offsetof(X86XSaveArea
, hi16_zmm_state
),
1268 .size
= sizeof(XSaveHi16_ZMM
) },
1270 { .feature
= FEAT_7_0_ECX
, .bits
= CPUID_7_0_ECX_PKU
,
1271 .offset
= offsetof(X86XSaveArea
, pkru_state
),
1272 .size
= sizeof(XSavePKRU
) },
1275 static uint32_t xsave_area_size(uint64_t mask
)
1280 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
1281 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
1282 if ((mask
>> i
) & 1) {
1283 ret
= MAX(ret
, esa
->offset
+ esa
->size
);
1289 static inline bool accel_uses_host_cpuid(void)
1291 return kvm_enabled() || hvf_enabled();
1294 static inline uint64_t x86_cpu_xsave_components(X86CPU
*cpu
)
1296 return ((uint64_t)cpu
->env
.features
[FEAT_XSAVE_COMP_HI
]) << 32 |
1297 cpu
->env
.features
[FEAT_XSAVE_COMP_LO
];
1300 const char *get_register_name_32(unsigned int reg
)
1302 if (reg
>= CPU_NB_REGS32
) {
1305 return x86_reg_info_32
[reg
].name
;
1309 * Returns the set of feature flags that are supported and migratable by
1310 * QEMU, for a given FeatureWord.
1312 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w
)
1314 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1318 for (i
= 0; i
< 32; i
++) {
1319 uint32_t f
= 1U << i
;
1321 /* If the feature name is known, it is implicitly considered migratable,
1322 * unless it is explicitly set in unmigratable_flags */
1323 if ((wi
->migratable_flags
& f
) ||
1324 (wi
->feat_names
[i
] && !(wi
->unmigratable_flags
& f
))) {
1331 void host_cpuid(uint32_t function
, uint32_t count
,
1332 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
1337 asm volatile("cpuid"
1338 : "=a"(vec
[0]), "=b"(vec
[1]),
1339 "=c"(vec
[2]), "=d"(vec
[3])
1340 : "0"(function
), "c"(count
) : "cc");
1341 #elif defined(__i386__)
1342 asm volatile("pusha \n\t"
1344 "mov %%eax, 0(%2) \n\t"
1345 "mov %%ebx, 4(%2) \n\t"
1346 "mov %%ecx, 8(%2) \n\t"
1347 "mov %%edx, 12(%2) \n\t"
1349 : : "a"(function
), "c"(count
), "S"(vec
)
1365 void host_vendor_fms(char *vendor
, int *family
, int *model
, int *stepping
)
1367 uint32_t eax
, ebx
, ecx
, edx
;
1369 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
1370 x86_cpu_vendor_words2str(vendor
, ebx
, edx
, ecx
);
1372 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
1374 *family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
1377 *model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
1380 *stepping
= eax
& 0x0F;
1384 /* CPU class name definitions: */
1386 /* Return type name for a given CPU model name
1387 * Caller is responsible for freeing the returned string.
1389 static char *x86_cpu_type_name(const char *model_name
)
1391 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
1394 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
1397 char *typename
= x86_cpu_type_name(cpu_model
);
1398 oc
= object_class_by_name(typename
);
1403 static char *x86_cpu_class_get_model_name(X86CPUClass
*cc
)
1405 const char *class_name
= object_class_get_name(OBJECT_CLASS(cc
));
1406 assert(g_str_has_suffix(class_name
, X86_CPU_TYPE_SUFFIX
));
1407 return g_strndup(class_name
,
1408 strlen(class_name
) - strlen(X86_CPU_TYPE_SUFFIX
));
1411 struct X86CPUDefinition
{
1415 /* vendor is zero-terminated, 12 character ASCII string */
1416 char vendor
[CPUID_VENDOR_SZ
+ 1];
1420 FeatureWordArray features
;
1421 const char *model_id
;
1422 CPUCaches
*cache_info
;
1425 static CPUCaches epyc_cache_info
= {
1426 .l1d_cache
= &(CPUCacheInfo
) {
1436 .no_invd_sharing
= true,
1438 .l1i_cache
= &(CPUCacheInfo
) {
1439 .type
= INSTRUCTION_CACHE
,
1448 .no_invd_sharing
= true,
1450 .l2_cache
= &(CPUCacheInfo
) {
1451 .type
= UNIFIED_CACHE
,
1460 .l3_cache
= &(CPUCacheInfo
) {
1461 .type
= UNIFIED_CACHE
,
1465 .associativity
= 16,
1471 .complex_indexing
= true,
1475 static X86CPUDefinition builtin_x86_defs
[] = {
1479 .vendor
= CPUID_VENDOR_AMD
,
1483 .features
[FEAT_1_EDX
] =
1485 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
1487 .features
[FEAT_1_ECX
] =
1488 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
1489 .features
[FEAT_8000_0001_EDX
] =
1490 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1491 .features
[FEAT_8000_0001_ECX
] =
1492 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
,
1493 .xlevel
= 0x8000000A,
1494 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
1499 .vendor
= CPUID_VENDOR_AMD
,
1503 /* Missing: CPUID_HT */
1504 .features
[FEAT_1_EDX
] =
1506 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
1507 CPUID_PSE36
| CPUID_VME
,
1508 .features
[FEAT_1_ECX
] =
1509 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
1511 .features
[FEAT_8000_0001_EDX
] =
1512 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
1513 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
1514 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
1515 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1517 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1518 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1519 .features
[FEAT_8000_0001_ECX
] =
1520 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
1521 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
1522 /* Missing: CPUID_SVM_LBRV */
1523 .features
[FEAT_SVM
] =
1525 .xlevel
= 0x8000001A,
1526 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
1531 .vendor
= CPUID_VENDOR_INTEL
,
1535 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1536 .features
[FEAT_1_EDX
] =
1538 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
1539 CPUID_PSE36
| CPUID_VME
| CPUID_ACPI
| CPUID_SS
,
1540 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1541 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1542 .features
[FEAT_1_ECX
] =
1543 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
1545 .features
[FEAT_8000_0001_EDX
] =
1546 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1547 .features
[FEAT_8000_0001_ECX
] =
1549 .xlevel
= 0x80000008,
1550 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1555 .vendor
= CPUID_VENDOR_INTEL
,
1559 /* Missing: CPUID_HT */
1560 .features
[FEAT_1_EDX
] =
1561 PPRO_FEATURES
| CPUID_VME
|
1562 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
1564 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1565 .features
[FEAT_1_ECX
] =
1566 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
1567 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1568 .features
[FEAT_8000_0001_EDX
] =
1569 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1570 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1571 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1572 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1573 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1574 .features
[FEAT_8000_0001_ECX
] =
1576 .xlevel
= 0x80000008,
1577 .model_id
= "Common KVM processor"
1582 .vendor
= CPUID_VENDOR_INTEL
,
1586 .features
[FEAT_1_EDX
] =
1588 .features
[FEAT_1_ECX
] =
1590 .xlevel
= 0x80000004,
1591 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
1596 .vendor
= CPUID_VENDOR_INTEL
,
1600 .features
[FEAT_1_EDX
] =
1601 PPRO_FEATURES
| CPUID_VME
|
1602 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
1603 .features
[FEAT_1_ECX
] =
1605 .features
[FEAT_8000_0001_ECX
] =
1607 .xlevel
= 0x80000008,
1608 .model_id
= "Common 32-bit KVM processor"
1613 .vendor
= CPUID_VENDOR_INTEL
,
1617 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1618 .features
[FEAT_1_EDX
] =
1619 PPRO_FEATURES
| CPUID_VME
|
1620 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_ACPI
|
1622 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
1623 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
1624 .features
[FEAT_1_ECX
] =
1625 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
1626 .features
[FEAT_8000_0001_EDX
] =
1628 .xlevel
= 0x80000008,
1629 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1634 .vendor
= CPUID_VENDOR_INTEL
,
1638 .features
[FEAT_1_EDX
] =
1646 .vendor
= CPUID_VENDOR_INTEL
,
1650 .features
[FEAT_1_EDX
] =
1658 .vendor
= CPUID_VENDOR_INTEL
,
1662 .features
[FEAT_1_EDX
] =
1670 .vendor
= CPUID_VENDOR_INTEL
,
1674 .features
[FEAT_1_EDX
] =
1682 .vendor
= CPUID_VENDOR_AMD
,
1686 .features
[FEAT_1_EDX
] =
1687 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
1689 .features
[FEAT_8000_0001_EDX
] =
1690 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
1691 .xlevel
= 0x80000008,
1692 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
1697 .vendor
= CPUID_VENDOR_INTEL
,
1701 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1702 .features
[FEAT_1_EDX
] =
1704 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
|
1705 CPUID_ACPI
| CPUID_SS
,
1706 /* Some CPUs got no CPUID_SEP */
1707 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1709 .features
[FEAT_1_ECX
] =
1710 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
1712 .features
[FEAT_8000_0001_EDX
] =
1714 .features
[FEAT_8000_0001_ECX
] =
1716 .xlevel
= 0x80000008,
1717 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1722 .vendor
= CPUID_VENDOR_INTEL
,
1726 .features
[FEAT_1_EDX
] =
1727 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1728 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1729 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1730 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1731 CPUID_DE
| CPUID_FP87
,
1732 .features
[FEAT_1_ECX
] =
1733 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1734 .features
[FEAT_8000_0001_EDX
] =
1735 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1736 .features
[FEAT_8000_0001_ECX
] =
1738 .xlevel
= 0x80000008,
1739 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1744 .vendor
= CPUID_VENDOR_INTEL
,
1748 .features
[FEAT_1_EDX
] =
1749 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1750 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1751 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1752 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1753 CPUID_DE
| CPUID_FP87
,
1754 .features
[FEAT_1_ECX
] =
1755 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1757 .features
[FEAT_8000_0001_EDX
] =
1758 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1759 .features
[FEAT_8000_0001_ECX
] =
1761 .xlevel
= 0x80000008,
1762 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1767 .vendor
= CPUID_VENDOR_INTEL
,
1771 .features
[FEAT_1_EDX
] =
1772 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1773 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1774 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1775 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1776 CPUID_DE
| CPUID_FP87
,
1777 .features
[FEAT_1_ECX
] =
1778 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1779 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1780 .features
[FEAT_8000_0001_EDX
] =
1781 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1782 .features
[FEAT_8000_0001_ECX
] =
1784 .xlevel
= 0x80000008,
1785 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
1788 .name
= "Nehalem-IBRS",
1790 .vendor
= CPUID_VENDOR_INTEL
,
1794 .features
[FEAT_1_EDX
] =
1795 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1796 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1797 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1798 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1799 CPUID_DE
| CPUID_FP87
,
1800 .features
[FEAT_1_ECX
] =
1801 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1802 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1803 .features
[FEAT_7_0_EDX
] =
1804 CPUID_7_0_EDX_SPEC_CTRL
,
1805 .features
[FEAT_8000_0001_EDX
] =
1806 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1807 .features
[FEAT_8000_0001_ECX
] =
1809 .xlevel
= 0x80000008,
1810 .model_id
= "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1815 .vendor
= CPUID_VENDOR_INTEL
,
1819 .features
[FEAT_1_EDX
] =
1820 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1821 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1822 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1823 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1824 CPUID_DE
| CPUID_FP87
,
1825 .features
[FEAT_1_ECX
] =
1826 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1827 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1828 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1829 .features
[FEAT_8000_0001_EDX
] =
1830 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1831 .features
[FEAT_8000_0001_ECX
] =
1833 .features
[FEAT_6_EAX
] =
1835 .xlevel
= 0x80000008,
1836 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1839 .name
= "Westmere-IBRS",
1841 .vendor
= CPUID_VENDOR_INTEL
,
1845 .features
[FEAT_1_EDX
] =
1846 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1847 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1848 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1849 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1850 CPUID_DE
| CPUID_FP87
,
1851 .features
[FEAT_1_ECX
] =
1852 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1853 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1854 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1855 .features
[FEAT_8000_0001_EDX
] =
1856 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1857 .features
[FEAT_8000_0001_ECX
] =
1859 .features
[FEAT_7_0_EDX
] =
1860 CPUID_7_0_EDX_SPEC_CTRL
,
1861 .features
[FEAT_6_EAX
] =
1863 .xlevel
= 0x80000008,
1864 .model_id
= "Westmere E56xx/L56xx/X56xx (IBRS update)",
1867 .name
= "SandyBridge",
1869 .vendor
= CPUID_VENDOR_INTEL
,
1873 .features
[FEAT_1_EDX
] =
1874 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1875 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1876 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1877 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1878 CPUID_DE
| CPUID_FP87
,
1879 .features
[FEAT_1_ECX
] =
1880 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1881 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1882 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1883 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1885 .features
[FEAT_8000_0001_EDX
] =
1886 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1888 .features
[FEAT_8000_0001_ECX
] =
1890 .features
[FEAT_XSAVE
] =
1891 CPUID_XSAVE_XSAVEOPT
,
1892 .features
[FEAT_6_EAX
] =
1894 .xlevel
= 0x80000008,
1895 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
1898 .name
= "SandyBridge-IBRS",
1900 .vendor
= CPUID_VENDOR_INTEL
,
1904 .features
[FEAT_1_EDX
] =
1905 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1906 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1907 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1908 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1909 CPUID_DE
| CPUID_FP87
,
1910 .features
[FEAT_1_ECX
] =
1911 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1912 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1913 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1914 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1916 .features
[FEAT_8000_0001_EDX
] =
1917 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1919 .features
[FEAT_8000_0001_ECX
] =
1921 .features
[FEAT_7_0_EDX
] =
1922 CPUID_7_0_EDX_SPEC_CTRL
,
1923 .features
[FEAT_XSAVE
] =
1924 CPUID_XSAVE_XSAVEOPT
,
1925 .features
[FEAT_6_EAX
] =
1927 .xlevel
= 0x80000008,
1928 .model_id
= "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1931 .name
= "IvyBridge",
1933 .vendor
= CPUID_VENDOR_INTEL
,
1937 .features
[FEAT_1_EDX
] =
1938 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1939 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1940 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1941 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1942 CPUID_DE
| CPUID_FP87
,
1943 .features
[FEAT_1_ECX
] =
1944 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1945 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1946 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1947 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1948 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1949 .features
[FEAT_7_0_EBX
] =
1950 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
1952 .features
[FEAT_8000_0001_EDX
] =
1953 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1955 .features
[FEAT_8000_0001_ECX
] =
1957 .features
[FEAT_XSAVE
] =
1958 CPUID_XSAVE_XSAVEOPT
,
1959 .features
[FEAT_6_EAX
] =
1961 .xlevel
= 0x80000008,
1962 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1965 .name
= "IvyBridge-IBRS",
1967 .vendor
= CPUID_VENDOR_INTEL
,
1971 .features
[FEAT_1_EDX
] =
1972 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1973 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1974 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1975 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1976 CPUID_DE
| CPUID_FP87
,
1977 .features
[FEAT_1_ECX
] =
1978 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1979 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1980 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1981 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1982 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1983 .features
[FEAT_7_0_EBX
] =
1984 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
1986 .features
[FEAT_8000_0001_EDX
] =
1987 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1989 .features
[FEAT_8000_0001_ECX
] =
1991 .features
[FEAT_7_0_EDX
] =
1992 CPUID_7_0_EDX_SPEC_CTRL
,
1993 .features
[FEAT_XSAVE
] =
1994 CPUID_XSAVE_XSAVEOPT
,
1995 .features
[FEAT_6_EAX
] =
1997 .xlevel
= 0x80000008,
1998 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
2001 .name
= "Haswell-noTSX",
2003 .vendor
= CPUID_VENDOR_INTEL
,
2007 .features
[FEAT_1_EDX
] =
2008 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2009 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2010 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2011 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2012 CPUID_DE
| CPUID_FP87
,
2013 .features
[FEAT_1_ECX
] =
2014 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2015 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2016 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2017 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2018 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2019 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2020 .features
[FEAT_8000_0001_EDX
] =
2021 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2023 .features
[FEAT_8000_0001_ECX
] =
2024 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
2025 .features
[FEAT_7_0_EBX
] =
2026 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2027 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2028 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
,
2029 .features
[FEAT_XSAVE
] =
2030 CPUID_XSAVE_XSAVEOPT
,
2031 .features
[FEAT_6_EAX
] =
2033 .xlevel
= 0x80000008,
2034 .model_id
= "Intel Core Processor (Haswell, no TSX)",
2037 .name
= "Haswell-noTSX-IBRS",
2039 .vendor
= CPUID_VENDOR_INTEL
,
2043 .features
[FEAT_1_EDX
] =
2044 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2045 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2046 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2047 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2048 CPUID_DE
| CPUID_FP87
,
2049 .features
[FEAT_1_ECX
] =
2050 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2051 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2052 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2053 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2054 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2055 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2056 .features
[FEAT_8000_0001_EDX
] =
2057 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2059 .features
[FEAT_8000_0001_ECX
] =
2060 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
2061 .features
[FEAT_7_0_EDX
] =
2062 CPUID_7_0_EDX_SPEC_CTRL
,
2063 .features
[FEAT_7_0_EBX
] =
2064 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2065 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2066 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
,
2067 .features
[FEAT_XSAVE
] =
2068 CPUID_XSAVE_XSAVEOPT
,
2069 .features
[FEAT_6_EAX
] =
2071 .xlevel
= 0x80000008,
2072 .model_id
= "Intel Core Processor (Haswell, no TSX, IBRS)",
2077 .vendor
= CPUID_VENDOR_INTEL
,
2081 .features
[FEAT_1_EDX
] =
2082 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2083 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2084 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2085 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2086 CPUID_DE
| CPUID_FP87
,
2087 .features
[FEAT_1_ECX
] =
2088 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2089 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2090 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2091 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2092 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2093 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2094 .features
[FEAT_8000_0001_EDX
] =
2095 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2097 .features
[FEAT_8000_0001_ECX
] =
2098 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
2099 .features
[FEAT_7_0_EBX
] =
2100 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2101 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2102 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2104 .features
[FEAT_XSAVE
] =
2105 CPUID_XSAVE_XSAVEOPT
,
2106 .features
[FEAT_6_EAX
] =
2108 .xlevel
= 0x80000008,
2109 .model_id
= "Intel Core Processor (Haswell)",
2112 .name
= "Haswell-IBRS",
2114 .vendor
= CPUID_VENDOR_INTEL
,
2118 .features
[FEAT_1_EDX
] =
2119 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2120 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2121 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2122 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2123 CPUID_DE
| CPUID_FP87
,
2124 .features
[FEAT_1_ECX
] =
2125 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2126 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2127 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2128 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2129 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2130 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2131 .features
[FEAT_8000_0001_EDX
] =
2132 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2134 .features
[FEAT_8000_0001_ECX
] =
2135 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
2136 .features
[FEAT_7_0_EDX
] =
2137 CPUID_7_0_EDX_SPEC_CTRL
,
2138 .features
[FEAT_7_0_EBX
] =
2139 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2140 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2141 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2143 .features
[FEAT_XSAVE
] =
2144 CPUID_XSAVE_XSAVEOPT
,
2145 .features
[FEAT_6_EAX
] =
2147 .xlevel
= 0x80000008,
2148 .model_id
= "Intel Core Processor (Haswell, IBRS)",
2151 .name
= "Broadwell-noTSX",
2153 .vendor
= CPUID_VENDOR_INTEL
,
2157 .features
[FEAT_1_EDX
] =
2158 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2159 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2160 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2161 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2162 CPUID_DE
| CPUID_FP87
,
2163 .features
[FEAT_1_ECX
] =
2164 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2165 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2166 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2167 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2168 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2169 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2170 .features
[FEAT_8000_0001_EDX
] =
2171 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2173 .features
[FEAT_8000_0001_ECX
] =
2174 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2175 .features
[FEAT_7_0_EBX
] =
2176 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2177 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2178 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2179 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2181 .features
[FEAT_XSAVE
] =
2182 CPUID_XSAVE_XSAVEOPT
,
2183 .features
[FEAT_6_EAX
] =
2185 .xlevel
= 0x80000008,
2186 .model_id
= "Intel Core Processor (Broadwell, no TSX)",
2189 .name
= "Broadwell-noTSX-IBRS",
2191 .vendor
= CPUID_VENDOR_INTEL
,
2195 .features
[FEAT_1_EDX
] =
2196 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2197 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2198 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2199 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2200 CPUID_DE
| CPUID_FP87
,
2201 .features
[FEAT_1_ECX
] =
2202 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2203 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2204 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2205 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2206 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2207 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2208 .features
[FEAT_8000_0001_EDX
] =
2209 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2211 .features
[FEAT_8000_0001_ECX
] =
2212 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2213 .features
[FEAT_7_0_EDX
] =
2214 CPUID_7_0_EDX_SPEC_CTRL
,
2215 .features
[FEAT_7_0_EBX
] =
2216 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2217 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2218 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2219 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2221 .features
[FEAT_XSAVE
] =
2222 CPUID_XSAVE_XSAVEOPT
,
2223 .features
[FEAT_6_EAX
] =
2225 .xlevel
= 0x80000008,
2226 .model_id
= "Intel Core Processor (Broadwell, no TSX, IBRS)",
2229 .name
= "Broadwell",
2231 .vendor
= CPUID_VENDOR_INTEL
,
2235 .features
[FEAT_1_EDX
] =
2236 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2237 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2238 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2239 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2240 CPUID_DE
| CPUID_FP87
,
2241 .features
[FEAT_1_ECX
] =
2242 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2243 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2244 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2245 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2246 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2247 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2248 .features
[FEAT_8000_0001_EDX
] =
2249 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2251 .features
[FEAT_8000_0001_ECX
] =
2252 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2253 .features
[FEAT_7_0_EBX
] =
2254 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2255 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2256 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2257 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2259 .features
[FEAT_XSAVE
] =
2260 CPUID_XSAVE_XSAVEOPT
,
2261 .features
[FEAT_6_EAX
] =
2263 .xlevel
= 0x80000008,
2264 .model_id
= "Intel Core Processor (Broadwell)",
2267 .name
= "Broadwell-IBRS",
2269 .vendor
= CPUID_VENDOR_INTEL
,
2273 .features
[FEAT_1_EDX
] =
2274 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2275 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2276 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2277 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2278 CPUID_DE
| CPUID_FP87
,
2279 .features
[FEAT_1_ECX
] =
2280 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2281 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2282 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2283 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2284 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2285 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2286 .features
[FEAT_8000_0001_EDX
] =
2287 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2289 .features
[FEAT_8000_0001_ECX
] =
2290 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2291 .features
[FEAT_7_0_EDX
] =
2292 CPUID_7_0_EDX_SPEC_CTRL
,
2293 .features
[FEAT_7_0_EBX
] =
2294 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2295 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2296 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2297 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2299 .features
[FEAT_XSAVE
] =
2300 CPUID_XSAVE_XSAVEOPT
,
2301 .features
[FEAT_6_EAX
] =
2303 .xlevel
= 0x80000008,
2304 .model_id
= "Intel Core Processor (Broadwell, IBRS)",
2307 .name
= "Skylake-Client",
2309 .vendor
= CPUID_VENDOR_INTEL
,
2313 .features
[FEAT_1_EDX
] =
2314 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2315 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2316 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2317 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2318 CPUID_DE
| CPUID_FP87
,
2319 .features
[FEAT_1_ECX
] =
2320 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2321 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2322 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2323 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2324 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2325 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2326 .features
[FEAT_8000_0001_EDX
] =
2327 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2329 .features
[FEAT_8000_0001_ECX
] =
2330 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2331 .features
[FEAT_7_0_EBX
] =
2332 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2333 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2334 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2335 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2337 /* Missing: XSAVES (not supported by some Linux versions,
2338 * including v4.1 to v4.12).
2339 * KVM doesn't yet expose any XSAVES state save component,
2340 * and the only one defined in Skylake (processor tracing)
2341 * probably will block migration anyway.
2343 .features
[FEAT_XSAVE
] =
2344 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2345 CPUID_XSAVE_XGETBV1
,
2346 .features
[FEAT_6_EAX
] =
2348 .xlevel
= 0x80000008,
2349 .model_id
= "Intel Core Processor (Skylake)",
2352 .name
= "Skylake-Client-IBRS",
2354 .vendor
= CPUID_VENDOR_INTEL
,
2358 .features
[FEAT_1_EDX
] =
2359 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2360 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2361 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2362 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2363 CPUID_DE
| CPUID_FP87
,
2364 .features
[FEAT_1_ECX
] =
2365 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2366 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2367 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2368 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2369 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2370 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2371 .features
[FEAT_8000_0001_EDX
] =
2372 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2374 .features
[FEAT_8000_0001_ECX
] =
2375 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2376 .features
[FEAT_7_0_EDX
] =
2377 CPUID_7_0_EDX_SPEC_CTRL
,
2378 .features
[FEAT_7_0_EBX
] =
2379 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2380 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2381 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2382 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2384 /* Missing: XSAVES (not supported by some Linux versions,
2385 * including v4.1 to v4.12).
2386 * KVM doesn't yet expose any XSAVES state save component,
2387 * and the only one defined in Skylake (processor tracing)
2388 * probably will block migration anyway.
2390 .features
[FEAT_XSAVE
] =
2391 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2392 CPUID_XSAVE_XGETBV1
,
2393 .features
[FEAT_6_EAX
] =
2395 .xlevel
= 0x80000008,
2396 .model_id
= "Intel Core Processor (Skylake, IBRS)",
2399 .name
= "Skylake-Server",
2401 .vendor
= CPUID_VENDOR_INTEL
,
2405 .features
[FEAT_1_EDX
] =
2406 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2407 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2408 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2409 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2410 CPUID_DE
| CPUID_FP87
,
2411 .features
[FEAT_1_ECX
] =
2412 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2413 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2414 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2415 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2416 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2417 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2418 .features
[FEAT_8000_0001_EDX
] =
2419 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
2420 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2421 .features
[FEAT_8000_0001_ECX
] =
2422 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2423 .features
[FEAT_7_0_EBX
] =
2424 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2425 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2426 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2427 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2428 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
2429 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
2430 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
2431 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
2432 .features
[FEAT_7_0_ECX
] =
2434 /* Missing: XSAVES (not supported by some Linux versions,
2435 * including v4.1 to v4.12).
2436 * KVM doesn't yet expose any XSAVES state save component,
2437 * and the only one defined in Skylake (processor tracing)
2438 * probably will block migration anyway.
2440 .features
[FEAT_XSAVE
] =
2441 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2442 CPUID_XSAVE_XGETBV1
,
2443 .features
[FEAT_6_EAX
] =
2445 .xlevel
= 0x80000008,
2446 .model_id
= "Intel Xeon Processor (Skylake)",
2449 .name
= "Skylake-Server-IBRS",
2451 .vendor
= CPUID_VENDOR_INTEL
,
2455 .features
[FEAT_1_EDX
] =
2456 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2457 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2458 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2459 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2460 CPUID_DE
| CPUID_FP87
,
2461 .features
[FEAT_1_ECX
] =
2462 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2463 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2464 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2465 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2466 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2467 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2468 .features
[FEAT_8000_0001_EDX
] =
2469 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
2470 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2471 .features
[FEAT_8000_0001_ECX
] =
2472 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2473 .features
[FEAT_7_0_EDX
] =
2474 CPUID_7_0_EDX_SPEC_CTRL
,
2475 .features
[FEAT_7_0_EBX
] =
2476 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2477 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2478 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2479 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2480 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
2481 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
2482 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
2483 CPUID_7_0_EBX_AVX512VL
,
2484 .features
[FEAT_7_0_ECX
] =
2486 /* Missing: XSAVES (not supported by some Linux versions,
2487 * including v4.1 to v4.12).
2488 * KVM doesn't yet expose any XSAVES state save component,
2489 * and the only one defined in Skylake (processor tracing)
2490 * probably will block migration anyway.
2492 .features
[FEAT_XSAVE
] =
2493 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2494 CPUID_XSAVE_XGETBV1
,
2495 .features
[FEAT_6_EAX
] =
2497 .xlevel
= 0x80000008,
2498 .model_id
= "Intel Xeon Processor (Skylake, IBRS)",
2501 .name
= "Cascadelake-Server",
2503 .vendor
= CPUID_VENDOR_INTEL
,
2507 .features
[FEAT_1_EDX
] =
2508 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2509 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2510 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2511 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2512 CPUID_DE
| CPUID_FP87
,
2513 .features
[FEAT_1_ECX
] =
2514 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2515 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2516 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2517 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2518 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2519 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2520 .features
[FEAT_8000_0001_EDX
] =
2521 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
2522 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2523 .features
[FEAT_8000_0001_ECX
] =
2524 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2525 .features
[FEAT_7_0_EBX
] =
2526 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2527 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2528 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2529 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2530 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
2531 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
2532 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
2533 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
|
2534 CPUID_7_0_EBX_INTEL_PT
,
2535 .features
[FEAT_7_0_ECX
] =
2536 CPUID_7_0_ECX_PKU
| CPUID_7_0_ECX_OSPKE
|
2537 CPUID_7_0_ECX_AVX512VNNI
,
2538 .features
[FEAT_7_0_EDX
] =
2539 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
2540 /* Missing: XSAVES (not supported by some Linux versions,
2541 * including v4.1 to v4.12).
2542 * KVM doesn't yet expose any XSAVES state save component,
2543 * and the only one defined in Skylake (processor tracing)
2544 * probably will block migration anyway.
2546 .features
[FEAT_XSAVE
] =
2547 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2548 CPUID_XSAVE_XGETBV1
,
2549 .features
[FEAT_6_EAX
] =
2551 .xlevel
= 0x80000008,
2552 .model_id
= "Intel Xeon Processor (Cascadelake)",
2555 .name
= "Icelake-Client",
2557 .vendor
= CPUID_VENDOR_INTEL
,
2561 .features
[FEAT_1_EDX
] =
2562 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2563 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2564 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2565 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2566 CPUID_DE
| CPUID_FP87
,
2567 .features
[FEAT_1_ECX
] =
2568 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2569 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2570 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2571 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2572 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2573 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2574 .features
[FEAT_8000_0001_EDX
] =
2575 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2577 .features
[FEAT_8000_0001_ECX
] =
2578 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2579 .features
[FEAT_8000_0008_EBX
] =
2580 CPUID_8000_0008_EBX_WBNOINVD
,
2581 .features
[FEAT_7_0_EBX
] =
2582 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2583 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2584 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2585 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2586 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_INTEL_PT
,
2587 .features
[FEAT_7_0_ECX
] =
2588 CPUID_7_0_ECX_VBMI
| CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_PKU
|
2589 CPUID_7_0_ECX_OSPKE
| CPUID_7_0_ECX_VBMI2
| CPUID_7_0_ECX_GFNI
|
2590 CPUID_7_0_ECX_VAES
| CPUID_7_0_ECX_VPCLMULQDQ
|
2591 CPUID_7_0_ECX_AVX512VNNI
| CPUID_7_0_ECX_AVX512BITALG
|
2592 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
,
2593 .features
[FEAT_7_0_EDX
] =
2594 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
2595 /* Missing: XSAVES (not supported by some Linux versions,
2596 * including v4.1 to v4.12).
2597 * KVM doesn't yet expose any XSAVES state save component,
2598 * and the only one defined in Skylake (processor tracing)
2599 * probably will block migration anyway.
2601 .features
[FEAT_XSAVE
] =
2602 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2603 CPUID_XSAVE_XGETBV1
,
2604 .features
[FEAT_6_EAX
] =
2606 .xlevel
= 0x80000008,
2607 .model_id
= "Intel Core Processor (Icelake)",
2610 .name
= "Icelake-Server",
2612 .vendor
= CPUID_VENDOR_INTEL
,
2616 .features
[FEAT_1_EDX
] =
2617 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2618 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2619 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2620 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2621 CPUID_DE
| CPUID_FP87
,
2622 .features
[FEAT_1_ECX
] =
2623 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2624 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2625 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2626 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2627 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2628 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2629 .features
[FEAT_8000_0001_EDX
] =
2630 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
2631 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2632 .features
[FEAT_8000_0001_ECX
] =
2633 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2634 .features
[FEAT_8000_0008_EBX
] =
2635 CPUID_8000_0008_EBX_WBNOINVD
,
2636 .features
[FEAT_7_0_EBX
] =
2637 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2638 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2639 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2640 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2641 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
2642 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
2643 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
2644 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
|
2645 CPUID_7_0_EBX_INTEL_PT
,
2646 .features
[FEAT_7_0_ECX
] =
2647 CPUID_7_0_ECX_VBMI
| CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_PKU
|
2648 CPUID_7_0_ECX_OSPKE
| CPUID_7_0_ECX_VBMI2
| CPUID_7_0_ECX_GFNI
|
2649 CPUID_7_0_ECX_VAES
| CPUID_7_0_ECX_VPCLMULQDQ
|
2650 CPUID_7_0_ECX_AVX512VNNI
| CPUID_7_0_ECX_AVX512BITALG
|
2651 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
| CPUID_7_0_ECX_LA57
,
2652 .features
[FEAT_7_0_EDX
] =
2653 CPUID_7_0_EDX_PCONFIG
| CPUID_7_0_EDX_SPEC_CTRL
|
2654 CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
2655 /* Missing: XSAVES (not supported by some Linux versions,
2656 * including v4.1 to v4.12).
2657 * KVM doesn't yet expose any XSAVES state save component,
2658 * and the only one defined in Skylake (processor tracing)
2659 * probably will block migration anyway.
2661 .features
[FEAT_XSAVE
] =
2662 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2663 CPUID_XSAVE_XGETBV1
,
2664 .features
[FEAT_6_EAX
] =
2666 .xlevel
= 0x80000008,
2667 .model_id
= "Intel Xeon Processor (Icelake)",
2670 .name
= "KnightsMill",
2672 .vendor
= CPUID_VENDOR_INTEL
,
2676 .features
[FEAT_1_EDX
] =
2677 CPUID_VME
| CPUID_SS
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
|
2678 CPUID_MMX
| CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
|
2679 CPUID_MCA
| CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
|
2680 CPUID_CX8
| CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
|
2681 CPUID_PSE
| CPUID_DE
| CPUID_FP87
,
2682 .features
[FEAT_1_ECX
] =
2683 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2684 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2685 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2686 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2687 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2688 CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2689 .features
[FEAT_8000_0001_EDX
] =
2690 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
2691 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2692 .features
[FEAT_8000_0001_ECX
] =
2693 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2694 .features
[FEAT_7_0_EBX
] =
2695 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
2696 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
|
2697 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_AVX512F
|
2698 CPUID_7_0_EBX_AVX512CD
| CPUID_7_0_EBX_AVX512PF
|
2699 CPUID_7_0_EBX_AVX512ER
,
2700 .features
[FEAT_7_0_ECX
] =
2701 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
,
2702 .features
[FEAT_7_0_EDX
] =
2703 CPUID_7_0_EDX_AVX512_4VNNIW
| CPUID_7_0_EDX_AVX512_4FMAPS
,
2704 .features
[FEAT_XSAVE
] =
2705 CPUID_XSAVE_XSAVEOPT
,
2706 .features
[FEAT_6_EAX
] =
2708 .xlevel
= 0x80000008,
2709 .model_id
= "Intel Xeon Phi Processor (Knights Mill)",
2712 .name
= "Opteron_G1",
2714 .vendor
= CPUID_VENDOR_AMD
,
2718 .features
[FEAT_1_EDX
] =
2719 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2720 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2721 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2722 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2723 CPUID_DE
| CPUID_FP87
,
2724 .features
[FEAT_1_ECX
] =
2726 .features
[FEAT_8000_0001_EDX
] =
2727 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2728 .xlevel
= 0x80000008,
2729 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
2732 .name
= "Opteron_G2",
2734 .vendor
= CPUID_VENDOR_AMD
,
2738 .features
[FEAT_1_EDX
] =
2739 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2740 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2741 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2742 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2743 CPUID_DE
| CPUID_FP87
,
2744 .features
[FEAT_1_ECX
] =
2745 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
2746 .features
[FEAT_8000_0001_EDX
] =
2747 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2748 .features
[FEAT_8000_0001_ECX
] =
2749 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
2750 .xlevel
= 0x80000008,
2751 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
2754 .name
= "Opteron_G3",
2756 .vendor
= CPUID_VENDOR_AMD
,
2760 .features
[FEAT_1_EDX
] =
2761 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2762 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2763 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2764 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2765 CPUID_DE
| CPUID_FP87
,
2766 .features
[FEAT_1_ECX
] =
2767 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
2769 .features
[FEAT_8000_0001_EDX
] =
2770 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
|
2772 .features
[FEAT_8000_0001_ECX
] =
2773 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
2774 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
2775 .xlevel
= 0x80000008,
2776 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
2779 .name
= "Opteron_G4",
2781 .vendor
= CPUID_VENDOR_AMD
,
2785 .features
[FEAT_1_EDX
] =
2786 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2787 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2788 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2789 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2790 CPUID_DE
| CPUID_FP87
,
2791 .features
[FEAT_1_ECX
] =
2792 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2793 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2794 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
2796 .features
[FEAT_8000_0001_EDX
] =
2797 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
2798 CPUID_EXT2_SYSCALL
| CPUID_EXT2_RDTSCP
,
2799 .features
[FEAT_8000_0001_ECX
] =
2800 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
2801 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
2802 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
2805 .xlevel
= 0x8000001A,
2806 .model_id
= "AMD Opteron 62xx class CPU",
2809 .name
= "Opteron_G5",
2811 .vendor
= CPUID_VENDOR_AMD
,
2815 .features
[FEAT_1_EDX
] =
2816 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2817 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2818 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2819 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2820 CPUID_DE
| CPUID_FP87
,
2821 .features
[FEAT_1_ECX
] =
2822 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
2823 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
2824 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
2825 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
2826 .features
[FEAT_8000_0001_EDX
] =
2827 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
2828 CPUID_EXT2_SYSCALL
| CPUID_EXT2_RDTSCP
,
2829 .features
[FEAT_8000_0001_ECX
] =
2830 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
2831 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
2832 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
2835 .xlevel
= 0x8000001A,
2836 .model_id
= "AMD Opteron 63xx class CPU",
2841 .vendor
= CPUID_VENDOR_AMD
,
2845 .features
[FEAT_1_EDX
] =
2846 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
2847 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
2848 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
2849 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
2850 CPUID_VME
| CPUID_FP87
,
2851 .features
[FEAT_1_ECX
] =
2852 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
2853 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
2854 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2855 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
2856 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
2857 .features
[FEAT_8000_0001_EDX
] =
2858 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
2859 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
2861 .features
[FEAT_8000_0001_ECX
] =
2862 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
2863 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
2864 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
2866 .features
[FEAT_7_0_EBX
] =
2867 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
2868 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
2869 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
2870 CPUID_7_0_EBX_SHA_NI
,
2871 /* Missing: XSAVES (not supported by some Linux versions,
2872 * including v4.1 to v4.12).
2873 * KVM doesn't yet expose any XSAVES state save component.
2875 .features
[FEAT_XSAVE
] =
2876 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2877 CPUID_XSAVE_XGETBV1
,
2878 .features
[FEAT_6_EAX
] =
2880 .xlevel
= 0x8000001E,
2881 .model_id
= "AMD EPYC Processor",
2882 .cache_info
= &epyc_cache_info
,
2885 .name
= "EPYC-IBPB",
2887 .vendor
= CPUID_VENDOR_AMD
,
2891 .features
[FEAT_1_EDX
] =
2892 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
2893 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
2894 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
2895 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
2896 CPUID_VME
| CPUID_FP87
,
2897 .features
[FEAT_1_ECX
] =
2898 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
2899 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
2900 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2901 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
2902 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
2903 .features
[FEAT_8000_0001_EDX
] =
2904 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
2905 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
2907 .features
[FEAT_8000_0001_ECX
] =
2908 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
2909 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
2910 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
2912 .features
[FEAT_8000_0008_EBX
] =
2913 CPUID_8000_0008_EBX_IBPB
,
2914 .features
[FEAT_7_0_EBX
] =
2915 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
2916 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
2917 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
2918 CPUID_7_0_EBX_SHA_NI
,
2919 /* Missing: XSAVES (not supported by some Linux versions,
2920 * including v4.1 to v4.12).
2921 * KVM doesn't yet expose any XSAVES state save component.
2923 .features
[FEAT_XSAVE
] =
2924 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2925 CPUID_XSAVE_XGETBV1
,
2926 .features
[FEAT_6_EAX
] =
2928 .xlevel
= 0x8000001E,
2929 .model_id
= "AMD EPYC Processor (with IBPB)",
2930 .cache_info
= &epyc_cache_info
,
2934 typedef struct PropValue
{
2935 const char *prop
, *value
;
2938 /* KVM-specific features that are automatically added/removed
2939 * from all CPU models when KVM is enabled.
2941 static PropValue kvm_default_props
[] = {
2942 { "kvmclock", "on" },
2943 { "kvm-nopiodelay", "on" },
2944 { "kvm-asyncpf", "on" },
2945 { "kvm-steal-time", "on" },
2946 { "kvm-pv-eoi", "on" },
2947 { "kvmclock-stable-bit", "on" },
2950 { "monitor", "off" },
2955 /* TCG-specific defaults that override all CPU models when using TCG
2957 static PropValue tcg_default_props
[] = {
2963 void x86_cpu_change_kvm_default(const char *prop
, const char *value
)
2966 for (pv
= kvm_default_props
; pv
->prop
; pv
++) {
2967 if (!strcmp(pv
->prop
, prop
)) {
2973 /* It is valid to call this function only for properties that
2974 * are already present in the kvm_default_props table.
2979 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
2980 bool migratable_only
);
2982 static bool lmce_supported(void)
2984 uint64_t mce_cap
= 0;
2987 if (kvm_ioctl(kvm_state
, KVM_X86_GET_MCE_CAP_SUPPORTED
, &mce_cap
) < 0) {
2992 return !!(mce_cap
& MCG_LMCE_P
);
2995 #define CPUID_MODEL_ID_SZ 48
2998 * cpu_x86_fill_model_id:
2999 * Get CPUID model ID string from host CPU.
3001 * @str should have at least CPUID_MODEL_ID_SZ bytes
3003 * The function does NOT add a null terminator to the string
3006 static int cpu_x86_fill_model_id(char *str
)
3008 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
3011 for (i
= 0; i
< 3; i
++) {
3012 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
3013 memcpy(str
+ i
* 16 + 0, &eax
, 4);
3014 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
3015 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
3016 memcpy(str
+ i
* 16 + 12, &edx
, 4);
3021 static Property max_x86_cpu_properties
[] = {
3022 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
3023 DEFINE_PROP_BOOL("host-cache-info", X86CPU
, cache_info_passthrough
, false),
3024 DEFINE_PROP_END_OF_LIST()
3027 static void max_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
3029 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3030 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
3034 xcc
->model_description
=
3035 "Enables all features supported by the accelerator in the current host";
3037 dc
->props
= max_x86_cpu_properties
;
3040 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
);
3042 static void max_x86_cpu_initfn(Object
*obj
)
3044 X86CPU
*cpu
= X86_CPU(obj
);
3045 CPUX86State
*env
= &cpu
->env
;
3046 KVMState
*s
= kvm_state
;
3048 /* We can't fill the features array here because we don't know yet if
3049 * "migratable" is true or false.
3051 cpu
->max_features
= true;
3053 if (accel_uses_host_cpuid()) {
3054 char vendor
[CPUID_VENDOR_SZ
+ 1] = { 0 };
3055 char model_id
[CPUID_MODEL_ID_SZ
+ 1] = { 0 };
3056 int family
, model
, stepping
;
3057 X86CPUDefinition host_cpudef
= { };
3058 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
3060 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
3061 x86_cpu_vendor_words2str(host_cpudef
.vendor
, ebx
, edx
, ecx
);
3063 host_vendor_fms(vendor
, &family
, &model
, &stepping
);
3065 cpu_x86_fill_model_id(model_id
);
3067 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", &error_abort
);
3068 object_property_set_int(OBJECT(cpu
), family
, "family", &error_abort
);
3069 object_property_set_int(OBJECT(cpu
), model
, "model", &error_abort
);
3070 object_property_set_int(OBJECT(cpu
), stepping
, "stepping",
3072 object_property_set_str(OBJECT(cpu
), model_id
, "model-id",
3075 if (kvm_enabled()) {
3076 env
->cpuid_min_level
=
3077 kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
3078 env
->cpuid_min_xlevel
=
3079 kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
3080 env
->cpuid_min_xlevel2
=
3081 kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
3083 env
->cpuid_min_level
=
3084 hvf_get_supported_cpuid(0x0, 0, R_EAX
);
3085 env
->cpuid_min_xlevel
=
3086 hvf_get_supported_cpuid(0x80000000, 0, R_EAX
);
3087 env
->cpuid_min_xlevel2
=
3088 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX
);
3091 if (lmce_supported()) {
3092 object_property_set_bool(OBJECT(cpu
), true, "lmce", &error_abort
);
3095 object_property_set_str(OBJECT(cpu
), CPUID_VENDOR_AMD
,
3096 "vendor", &error_abort
);
3097 object_property_set_int(OBJECT(cpu
), 6, "family", &error_abort
);
3098 object_property_set_int(OBJECT(cpu
), 6, "model", &error_abort
);
3099 object_property_set_int(OBJECT(cpu
), 3, "stepping", &error_abort
);
3100 object_property_set_str(OBJECT(cpu
),
3101 "QEMU TCG CPU version " QEMU_HW_VERSION
,
3102 "model-id", &error_abort
);
3105 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
3108 static const TypeInfo max_x86_cpu_type_info
= {
3109 .name
= X86_CPU_TYPE_NAME("max"),
3110 .parent
= TYPE_X86_CPU
,
3111 .instance_init
= max_x86_cpu_initfn
,
3112 .class_init
= max_x86_cpu_class_init
,
3115 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3116 static void host_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
3118 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
3120 xcc
->host_cpuid_required
= true;
3123 #if defined(CONFIG_KVM)
3124 xcc
->model_description
=
3125 "KVM processor with all supported host features ";
3126 #elif defined(CONFIG_HVF)
3127 xcc
->model_description
=
3128 "HVF processor with all supported host features ";
3132 static const TypeInfo host_x86_cpu_type_info
= {
3133 .name
= X86_CPU_TYPE_NAME("host"),
3134 .parent
= X86_CPU_TYPE_NAME("max"),
3135 .class_init
= host_x86_cpu_class_init
,
3140 static char *feature_word_description(FeatureWordInfo
*f
, uint32_t bit
)
3142 assert(f
->type
== CPUID_FEATURE_WORD
|| f
->type
== MSR_FEATURE_WORD
);
3145 case CPUID_FEATURE_WORD
:
3147 const char *reg
= get_register_name_32(f
->cpuid
.reg
);
3149 return g_strdup_printf("CPUID.%02XH:%s",
3152 case MSR_FEATURE_WORD
:
3153 return g_strdup_printf("MSR(%02XH)",
3160 static void report_unavailable_features(FeatureWord w
, uint32_t mask
)
3162 FeatureWordInfo
*f
= &feature_word_info
[w
];
3164 char *feat_word_str
;
3166 for (i
= 0; i
< 32; ++i
) {
3167 if ((1UL << i
) & mask
) {
3168 feat_word_str
= feature_word_description(f
, i
);
3169 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
3170 accel_uses_host_cpuid() ? "host" : "TCG",
3172 f
->feat_names
[i
] ? "." : "",
3173 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
3174 g_free(feat_word_str
);
3179 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
,
3180 const char *name
, void *opaque
,
3183 X86CPU
*cpu
= X86_CPU(obj
);
3184 CPUX86State
*env
= &cpu
->env
;
3187 value
= (env
->cpuid_version
>> 8) & 0xf;
3189 value
+= (env
->cpuid_version
>> 20) & 0xff;
3191 visit_type_int(v
, name
, &value
, errp
);
3194 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
,
3195 const char *name
, void *opaque
,
3198 X86CPU
*cpu
= X86_CPU(obj
);
3199 CPUX86State
*env
= &cpu
->env
;
3200 const int64_t min
= 0;
3201 const int64_t max
= 0xff + 0xf;
3202 Error
*local_err
= NULL
;
3205 visit_type_int(v
, name
, &value
, &local_err
);
3207 error_propagate(errp
, local_err
);
3210 if (value
< min
|| value
> max
) {
3211 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
3212 name
? name
: "null", value
, min
, max
);
3216 env
->cpuid_version
&= ~0xff00f00;
3218 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
3220 env
->cpuid_version
|= value
<< 8;
3224 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
,
3225 const char *name
, void *opaque
,
3228 X86CPU
*cpu
= X86_CPU(obj
);
3229 CPUX86State
*env
= &cpu
->env
;
3232 value
= (env
->cpuid_version
>> 4) & 0xf;
3233 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
3234 visit_type_int(v
, name
, &value
, errp
);
3237 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
,
3238 const char *name
, void *opaque
,
3241 X86CPU
*cpu
= X86_CPU(obj
);
3242 CPUX86State
*env
= &cpu
->env
;
3243 const int64_t min
= 0;
3244 const int64_t max
= 0xff;
3245 Error
*local_err
= NULL
;
3248 visit_type_int(v
, name
, &value
, &local_err
);
3250 error_propagate(errp
, local_err
);
3253 if (value
< min
|| value
> max
) {
3254 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
3255 name
? name
: "null", value
, min
, max
);
3259 env
->cpuid_version
&= ~0xf00f0;
3260 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
3263 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
3264 const char *name
, void *opaque
,
3267 X86CPU
*cpu
= X86_CPU(obj
);
3268 CPUX86State
*env
= &cpu
->env
;
3271 value
= env
->cpuid_version
& 0xf;
3272 visit_type_int(v
, name
, &value
, errp
);
3275 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
3276 const char *name
, void *opaque
,
3279 X86CPU
*cpu
= X86_CPU(obj
);
3280 CPUX86State
*env
= &cpu
->env
;
3281 const int64_t min
= 0;
3282 const int64_t max
= 0xf;
3283 Error
*local_err
= NULL
;
3286 visit_type_int(v
, name
, &value
, &local_err
);
3288 error_propagate(errp
, local_err
);
3291 if (value
< min
|| value
> max
) {
3292 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
3293 name
? name
: "null", value
, min
, max
);
3297 env
->cpuid_version
&= ~0xf;
3298 env
->cpuid_version
|= value
& 0xf;
3301 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
3303 X86CPU
*cpu
= X86_CPU(obj
);
3304 CPUX86State
*env
= &cpu
->env
;
3307 value
= g_malloc(CPUID_VENDOR_SZ
+ 1);
3308 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
3309 env
->cpuid_vendor3
);
3313 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
3316 X86CPU
*cpu
= X86_CPU(obj
);
3317 CPUX86State
*env
= &cpu
->env
;
3320 if (strlen(value
) != CPUID_VENDOR_SZ
) {
3321 error_setg(errp
, QERR_PROPERTY_VALUE_BAD
, "", "vendor", value
);
3325 env
->cpuid_vendor1
= 0;
3326 env
->cpuid_vendor2
= 0;
3327 env
->cpuid_vendor3
= 0;
3328 for (i
= 0; i
< 4; i
++) {
3329 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
3330 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
3331 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
3335 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
3337 X86CPU
*cpu
= X86_CPU(obj
);
3338 CPUX86State
*env
= &cpu
->env
;
3342 value
= g_malloc(48 + 1);
3343 for (i
= 0; i
< 48; i
++) {
3344 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
3350 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
3353 X86CPU
*cpu
= X86_CPU(obj
);
3354 CPUX86State
*env
= &cpu
->env
;
3357 if (model_id
== NULL
) {
3360 len
= strlen(model_id
);
3361 memset(env
->cpuid_model
, 0, 48);
3362 for (i
= 0; i
< 48; i
++) {
3366 c
= (uint8_t)model_id
[i
];
3368 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
3372 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
3373 void *opaque
, Error
**errp
)
3375 X86CPU
*cpu
= X86_CPU(obj
);
3378 value
= cpu
->env
.tsc_khz
* 1000;
3379 visit_type_int(v
, name
, &value
, errp
);
3382 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
3383 void *opaque
, Error
**errp
)
3385 X86CPU
*cpu
= X86_CPU(obj
);
3386 const int64_t min
= 0;
3387 const int64_t max
= INT64_MAX
;
3388 Error
*local_err
= NULL
;
3391 visit_type_int(v
, name
, &value
, &local_err
);
3393 error_propagate(errp
, local_err
);
3396 if (value
< min
|| value
> max
) {
3397 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
3398 name
? name
: "null", value
, min
, max
);
3402 cpu
->env
.tsc_khz
= cpu
->env
.user_tsc_khz
= value
/ 1000;
3405 /* Generic getter for "feature-words" and "filtered-features" properties */
3406 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
,
3407 const char *name
, void *opaque
,
3410 uint32_t *array
= (uint32_t *)opaque
;
3412 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
3413 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
3414 X86CPUFeatureWordInfoList
*list
= NULL
;
3416 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3417 FeatureWordInfo
*wi
= &feature_word_info
[w
];
3419 * We didn't have MSR features when "feature-words" was
3420 * introduced. Therefore skipped other type entries.
3422 if (wi
->type
!= CPUID_FEATURE_WORD
) {
3425 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
3426 qwi
->cpuid_input_eax
= wi
->cpuid
.eax
;
3427 qwi
->has_cpuid_input_ecx
= wi
->cpuid
.needs_ecx
;
3428 qwi
->cpuid_input_ecx
= wi
->cpuid
.ecx
;
3429 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid
.reg
].qapi_enum
;
3430 qwi
->features
= array
[w
];
3432 /* List will be in reverse order, but order shouldn't matter */
3433 list_entries
[w
].next
= list
;
3434 list_entries
[w
].value
= &word_infos
[w
];
3435 list
= &list_entries
[w
];
3438 visit_type_X86CPUFeatureWordInfoList(v
, "feature-words", &list
, errp
);
3441 static void x86_get_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
3442 void *opaque
, Error
**errp
)
3444 X86CPU
*cpu
= X86_CPU(obj
);
3445 int64_t value
= cpu
->hyperv_spinlock_attempts
;
3447 visit_type_int(v
, name
, &value
, errp
);
3450 static void x86_set_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
3451 void *opaque
, Error
**errp
)
3453 const int64_t min
= 0xFFF;
3454 const int64_t max
= UINT_MAX
;
3455 X86CPU
*cpu
= X86_CPU(obj
);
3459 visit_type_int(v
, name
, &value
, &err
);
3461 error_propagate(errp
, err
);
3465 if (value
< min
|| value
> max
) {
3466 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
3467 " (minimum: %" PRId64
", maximum: %" PRId64
")",
3468 object_get_typename(obj
), name
? name
: "null",
3472 cpu
->hyperv_spinlock_attempts
= value
;
3475 static const PropertyInfo qdev_prop_spinlocks
= {
3477 .get
= x86_get_hv_spinlocks
,
3478 .set
= x86_set_hv_spinlocks
,
3481 /* Convert all '_' in a feature string option name to '-', to make feature
3482 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3484 static inline void feat2prop(char *s
)
3486 while ((s
= strchr(s
, '_'))) {
3491 /* Return the feature property name for a feature flag bit */
3492 static const char *x86_cpu_feature_name(FeatureWord w
, int bitnr
)
3494 /* XSAVE components are automatically enabled by other features,
3495 * so return the original feature name instead
3497 if (w
== FEAT_XSAVE_COMP_LO
|| w
== FEAT_XSAVE_COMP_HI
) {
3498 int comp
= (w
== FEAT_XSAVE_COMP_HI
) ? bitnr
+ 32 : bitnr
;
3500 if (comp
< ARRAY_SIZE(x86_ext_save_areas
) &&
3501 x86_ext_save_areas
[comp
].bits
) {
3502 w
= x86_ext_save_areas
[comp
].feature
;
3503 bitnr
= ctz32(x86_ext_save_areas
[comp
].bits
);
3508 assert(w
< FEATURE_WORDS
);
3509 return feature_word_info
[w
].feat_names
[bitnr
];
3512 /* Compatibily hack to maintain legacy +-feat semantic,
3513 * where +-feat overwrites any feature set by
3514 * feat=on|feat even if the later is parsed after +-feat
3515 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3517 static GList
*plus_features
, *minus_features
;
3519 static gint
compare_string(gconstpointer a
, gconstpointer b
)
3521 return g_strcmp0(a
, b
);
3524 /* Parse "+feature,-feature,feature=foo" CPU feature string
3526 static void x86_cpu_parse_featurestr(const char *typename
, char *features
,
3529 char *featurestr
; /* Single 'key=value" string being parsed */
3530 static bool cpu_globals_initialized
;
3531 bool ambiguous
= false;
3533 if (cpu_globals_initialized
) {
3536 cpu_globals_initialized
= true;
3542 for (featurestr
= strtok(features
, ",");
3544 featurestr
= strtok(NULL
, ",")) {
3546 const char *val
= NULL
;
3549 GlobalProperty
*prop
;
3551 /* Compatibility syntax: */
3552 if (featurestr
[0] == '+') {
3553 plus_features
= g_list_append(plus_features
,
3554 g_strdup(featurestr
+ 1));
3556 } else if (featurestr
[0] == '-') {
3557 minus_features
= g_list_append(minus_features
,
3558 g_strdup(featurestr
+ 1));
3562 eq
= strchr(featurestr
, '=');
3570 feat2prop(featurestr
);
3573 if (g_list_find_custom(plus_features
, name
, compare_string
)) {
3574 warn_report("Ambiguous CPU model string. "
3575 "Don't mix both \"+%s\" and \"%s=%s\"",
3579 if (g_list_find_custom(minus_features
, name
, compare_string
)) {
3580 warn_report("Ambiguous CPU model string. "
3581 "Don't mix both \"-%s\" and \"%s=%s\"",
3587 if (!strcmp(name
, "tsc-freq")) {
3591 ret
= qemu_strtosz_metric(val
, NULL
, &tsc_freq
);
3592 if (ret
< 0 || tsc_freq
> INT64_MAX
) {
3593 error_setg(errp
, "bad numerical value %s", val
);
3596 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
3598 name
= "tsc-frequency";
3601 prop
= g_new0(typeof(*prop
), 1);
3602 prop
->driver
= typename
;
3603 prop
->property
= g_strdup(name
);
3604 prop
->value
= g_strdup(val
);
3605 qdev_prop_register_global(prop
);
3609 warn_report("Compatibility of ambiguous CPU model "
3610 "strings won't be kept on future QEMU versions");
3614 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
);
3615 static int x86_cpu_filter_features(X86CPU
*cpu
);
3617 /* Check for missing features that may prevent the CPU class from
3618 * running using the current machine and accelerator.
3620 static void x86_cpu_class_check_missing_features(X86CPUClass
*xcc
,
3621 strList
**missing_feats
)
3626 strList
**next
= missing_feats
;
3628 if (xcc
->host_cpuid_required
&& !accel_uses_host_cpuid()) {
3629 strList
*new = g_new0(strList
, 1);
3630 new->value
= g_strdup("kvm");
3631 *missing_feats
= new;
3635 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
3637 x86_cpu_expand_features(xc
, &err
);
3639 /* Errors at x86_cpu_expand_features should never happen,
3640 * but in case it does, just report the model as not
3641 * runnable at all using the "type" property.
3643 strList
*new = g_new0(strList
, 1);
3644 new->value
= g_strdup("type");
3649 x86_cpu_filter_features(xc
);
3651 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3652 uint32_t filtered
= xc
->filtered_features
[w
];
3654 for (i
= 0; i
< 32; i
++) {
3655 if (filtered
& (1UL << i
)) {
3656 strList
*new = g_new0(strList
, 1);
3657 new->value
= g_strdup(x86_cpu_feature_name(w
, i
));
3664 object_unref(OBJECT(xc
));
3667 /* Print all cpuid feature names in featureset
3669 static void listflags(FILE *f
, fprintf_function print
, GList
*features
)
3674 for (tmp
= features
; tmp
; tmp
= tmp
->next
) {
3675 const char *name
= tmp
->data
;
3676 if ((len
+ strlen(name
) + 1) >= 75) {
3680 print(f
, "%s%s", len
== 0 ? " " : " ", name
);
3681 len
+= strlen(name
) + 1;
3686 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
3687 static gint
x86_cpu_list_compare(gconstpointer a
, gconstpointer b
)
3689 ObjectClass
*class_a
= (ObjectClass
*)a
;
3690 ObjectClass
*class_b
= (ObjectClass
*)b
;
3691 X86CPUClass
*cc_a
= X86_CPU_CLASS(class_a
);
3692 X86CPUClass
*cc_b
= X86_CPU_CLASS(class_b
);
3693 char *name_a
, *name_b
;
3696 if (cc_a
->ordering
!= cc_b
->ordering
) {
3697 ret
= cc_a
->ordering
- cc_b
->ordering
;
3699 name_a
= x86_cpu_class_get_model_name(cc_a
);
3700 name_b
= x86_cpu_class_get_model_name(cc_b
);
3701 ret
= strcmp(name_a
, name_b
);
3708 static GSList
*get_sorted_cpu_model_list(void)
3710 GSList
*list
= object_class_get_list(TYPE_X86_CPU
, false);
3711 list
= g_slist_sort(list
, x86_cpu_list_compare
);
3715 static void x86_cpu_list_entry(gpointer data
, gpointer user_data
)
3717 ObjectClass
*oc
= data
;
3718 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
3719 CPUListState
*s
= user_data
;
3720 char *name
= x86_cpu_class_get_model_name(cc
);
3721 const char *desc
= cc
->model_description
;
3722 if (!desc
&& cc
->cpu_def
) {
3723 desc
= cc
->cpu_def
->model_id
;
3726 (*s
->cpu_fprintf
)(s
->file
, "x86 %-20s %-48s\n",
3731 /* list available CPU models and flags */
3732 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
3737 .cpu_fprintf
= cpu_fprintf
,
3740 GList
*names
= NULL
;
3742 (*cpu_fprintf
)(f
, "Available CPUs:\n");
3743 list
= get_sorted_cpu_model_list();
3744 g_slist_foreach(list
, x86_cpu_list_entry
, &s
);
3748 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
3749 FeatureWordInfo
*fw
= &feature_word_info
[i
];
3750 for (j
= 0; j
< 32; j
++) {
3751 if (fw
->feat_names
[j
]) {
3752 names
= g_list_append(names
, (gpointer
)fw
->feat_names
[j
]);
3757 names
= g_list_sort(names
, (GCompareFunc
)strcmp
);
3759 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
3760 listflags(f
, cpu_fprintf
, names
);
3761 (*cpu_fprintf
)(f
, "\n");
3765 static void x86_cpu_definition_entry(gpointer data
, gpointer user_data
)
3767 ObjectClass
*oc
= data
;
3768 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
3769 CpuDefinitionInfoList
**cpu_list
= user_data
;
3770 CpuDefinitionInfoList
*entry
;
3771 CpuDefinitionInfo
*info
;
3773 info
= g_malloc0(sizeof(*info
));
3774 info
->name
= x86_cpu_class_get_model_name(cc
);
3775 x86_cpu_class_check_missing_features(cc
, &info
->unavailable_features
);
3776 info
->has_unavailable_features
= true;
3777 info
->q_typename
= g_strdup(object_class_get_name(oc
));
3778 info
->migration_safe
= cc
->migration_safe
;
3779 info
->has_migration_safe
= true;
3780 info
->q_static
= cc
->static_model
;
3782 entry
= g_malloc0(sizeof(*entry
));
3783 entry
->value
= info
;
3784 entry
->next
= *cpu_list
;
3788 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
3790 CpuDefinitionInfoList
*cpu_list
= NULL
;
3791 GSList
*list
= get_sorted_cpu_model_list();
3792 g_slist_foreach(list
, x86_cpu_definition_entry
, &cpu_list
);
3797 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
3798 bool migratable_only
)
3800 FeatureWordInfo
*wi
= &feature_word_info
[w
];
3803 if (kvm_enabled()) {
3805 case CPUID_FEATURE_WORD
:
3806 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid
.eax
,
3810 case MSR_FEATURE_WORD
:
3811 r
= kvm_arch_get_supported_msr_feature(kvm_state
,
3815 } else if (hvf_enabled()) {
3816 if (wi
->type
!= CPUID_FEATURE_WORD
) {
3819 r
= hvf_get_supported_cpuid(wi
->cpuid
.eax
,
3822 } else if (tcg_enabled()) {
3823 r
= wi
->tcg_features
;
3827 if (migratable_only
) {
3828 r
&= x86_cpu_get_migratable_flags(w
);
3833 static void x86_cpu_report_filtered_features(X86CPU
*cpu
)
3837 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3838 report_unavailable_features(w
, cpu
->filtered_features
[w
]);
3842 static void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
)
3845 for (pv
= props
; pv
->prop
; pv
++) {
3849 object_property_parse(OBJECT(cpu
), pv
->value
, pv
->prop
,
3854 /* Load data from X86CPUDefinition into a X86CPU object
3856 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
)
3858 CPUX86State
*env
= &cpu
->env
;
3860 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
3863 /*NOTE: any property set by this function should be returned by
3864 * x86_cpu_static_props(), so static expansion of
3865 * query-cpu-model-expansion is always complete.
3868 /* CPU models only set _minimum_ values for level/xlevel: */
3869 object_property_set_uint(OBJECT(cpu
), def
->level
, "min-level", errp
);
3870 object_property_set_uint(OBJECT(cpu
), def
->xlevel
, "min-xlevel", errp
);
3872 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
3873 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
3874 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
3875 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
3876 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3877 env
->features
[w
] = def
->features
[w
];
3880 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3881 cpu
->legacy_cache
= !def
->cache_info
;
3883 /* Special cases not set in the X86CPUDefinition structs: */
3884 /* TODO: in-kernel irqchip for hvf */
3885 if (kvm_enabled()) {
3886 if (!kvm_irqchip_in_kernel()) {
3887 x86_cpu_change_kvm_default("x2apic", "off");
3890 x86_cpu_apply_props(cpu
, kvm_default_props
);
3891 } else if (tcg_enabled()) {
3892 x86_cpu_apply_props(cpu
, tcg_default_props
);
3895 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
3897 /* sysenter isn't supported in compatibility mode on AMD,
3898 * syscall isn't supported in compatibility mode on Intel.
3899 * Normally we advertise the actual CPU vendor, but you can
3900 * override this using the 'vendor' property if you want to use
3901 * KVM's sysenter/syscall emulation in compatibility mode and
3902 * when doing cross vendor migration
3904 vendor
= def
->vendor
;
3905 if (accel_uses_host_cpuid()) {
3906 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
3907 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
3908 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
3909 vendor
= host_vendor
;
3912 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
3916 /* Return a QDict containing keys for all properties that can be included
3917 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3918 * must be included in the dictionary.
3920 static QDict
*x86_cpu_static_props(void)
3924 static const char *props
[] = {
3942 for (i
= 0; props
[i
]; i
++) {
3943 qdict_put_null(d
, props
[i
]);
3946 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3947 FeatureWordInfo
*fi
= &feature_word_info
[w
];
3949 for (bit
= 0; bit
< 32; bit
++) {
3950 if (!fi
->feat_names
[bit
]) {
3953 qdict_put_null(d
, fi
->feat_names
[bit
]);
3960 /* Add an entry to @props dict, with the value for property. */
3961 static void x86_cpu_expand_prop(X86CPU
*cpu
, QDict
*props
, const char *prop
)
3963 QObject
*value
= object_property_get_qobject(OBJECT(cpu
), prop
,
3966 qdict_put_obj(props
, prop
, value
);
3969 /* Convert CPU model data from X86CPU object to a property dictionary
3970 * that can recreate exactly the same CPU model.
3972 static void x86_cpu_to_dict(X86CPU
*cpu
, QDict
*props
)
3974 QDict
*sprops
= x86_cpu_static_props();
3975 const QDictEntry
*e
;
3977 for (e
= qdict_first(sprops
); e
; e
= qdict_next(sprops
, e
)) {
3978 const char *prop
= qdict_entry_key(e
);
3979 x86_cpu_expand_prop(cpu
, props
, prop
);
3983 /* Convert CPU model data from X86CPU object to a property dictionary
3984 * that can recreate exactly the same CPU model, including every
3985 * writeable QOM property.
3987 static void x86_cpu_to_dict_full(X86CPU
*cpu
, QDict
*props
)
3989 ObjectPropertyIterator iter
;
3990 ObjectProperty
*prop
;
3992 object_property_iter_init(&iter
, OBJECT(cpu
));
3993 while ((prop
= object_property_iter_next(&iter
))) {
3994 /* skip read-only or write-only properties */
3995 if (!prop
->get
|| !prop
->set
) {
3999 /* "hotplugged" is the only property that is configurable
4000 * on the command-line but will be set differently on CPUs
4001 * created using "-cpu ... -smp ..." and by CPUs created
4002 * on the fly by x86_cpu_from_model() for querying. Skip it.
4004 if (!strcmp(prop
->name
, "hotplugged")) {
4007 x86_cpu_expand_prop(cpu
, props
, prop
->name
);
4011 static void object_apply_props(Object
*obj
, QDict
*props
, Error
**errp
)
4013 const QDictEntry
*prop
;
4016 for (prop
= qdict_first(props
); prop
; prop
= qdict_next(props
, prop
)) {
4017 object_property_set_qobject(obj
, qdict_entry_value(prop
),
4018 qdict_entry_key(prop
), &err
);
4024 error_propagate(errp
, err
);
4027 /* Create X86CPU object according to model+props specification */
4028 static X86CPU
*x86_cpu_from_model(const char *model
, QDict
*props
, Error
**errp
)
4034 xcc
= X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU
, model
));
4036 error_setg(&err
, "CPU model '%s' not found", model
);
4040 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
4042 object_apply_props(OBJECT(xc
), props
, &err
);
4048 x86_cpu_expand_features(xc
, &err
);
4055 error_propagate(errp
, err
);
4056 object_unref(OBJECT(xc
));
4062 CpuModelExpansionInfo
*
4063 arch_query_cpu_model_expansion(CpuModelExpansionType type
,
4064 CpuModelInfo
*model
,
4069 CpuModelExpansionInfo
*ret
= g_new0(CpuModelExpansionInfo
, 1);
4070 QDict
*props
= NULL
;
4071 const char *base_name
;
4073 xc
= x86_cpu_from_model(model
->name
,
4075 qobject_to(QDict
, model
->props
) :
4081 props
= qdict_new();
4082 ret
->model
= g_new0(CpuModelInfo
, 1);
4083 ret
->model
->props
= QOBJECT(props
);
4084 ret
->model
->has_props
= true;
4087 case CPU_MODEL_EXPANSION_TYPE_STATIC
:
4088 /* Static expansion will be based on "base" only */
4090 x86_cpu_to_dict(xc
, props
);
4092 case CPU_MODEL_EXPANSION_TYPE_FULL
:
4093 /* As we don't return every single property, full expansion needs
4094 * to keep the original model name+props, and add extra
4095 * properties on top of that.
4097 base_name
= model
->name
;
4098 x86_cpu_to_dict_full(xc
, props
);
4101 error_setg(&err
, "Unsupported expansion type");
4105 x86_cpu_to_dict(xc
, props
);
4107 ret
->model
->name
= g_strdup(base_name
);
4110 object_unref(OBJECT(xc
));
4112 error_propagate(errp
, err
);
4113 qapi_free_CpuModelExpansionInfo(ret
);
4119 static gchar
*x86_gdb_arch_name(CPUState
*cs
)
4121 #ifdef TARGET_X86_64
4122 return g_strdup("i386:x86-64");
4124 return g_strdup("i386");
4128 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
4130 X86CPUDefinition
*cpudef
= data
;
4131 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
4133 xcc
->cpu_def
= cpudef
;
4134 xcc
->migration_safe
= true;
4137 static void x86_register_cpudef_type(X86CPUDefinition
*def
)
4139 char *typename
= x86_cpu_type_name(def
->name
);
4142 .parent
= TYPE_X86_CPU
,
4143 .class_init
= x86_cpu_cpudef_class_init
,
4147 /* AMD aliases are handled at runtime based on CPUID vendor, so
4148 * they shouldn't be set on the CPU model table.
4150 assert(!(def
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_AMD_ALIASES
));
4151 /* catch mistakes instead of silently truncating model_id when too long */
4152 assert(def
->model_id
&& strlen(def
->model_id
) <= 48);
4159 #if !defined(CONFIG_USER_ONLY)
4161 void cpu_clear_apic_feature(CPUX86State
*env
)
4163 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
4166 #endif /* !CONFIG_USER_ONLY */
4168 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
4169 uint32_t *eax
, uint32_t *ebx
,
4170 uint32_t *ecx
, uint32_t *edx
)
4172 X86CPU
*cpu
= x86_env_get_cpu(env
);
4173 CPUState
*cs
= CPU(cpu
);
4174 uint32_t pkg_offset
;
4176 uint32_t signature
[3];
4178 /* Calculate & apply limits for different index ranges */
4179 if (index
>= 0xC0000000) {
4180 limit
= env
->cpuid_xlevel2
;
4181 } else if (index
>= 0x80000000) {
4182 limit
= env
->cpuid_xlevel
;
4183 } else if (index
>= 0x40000000) {
4186 limit
= env
->cpuid_level
;
4189 if (index
> limit
) {
4190 /* Intel documentation states that invalid EAX input will
4191 * return the same information as EAX=cpuid_level
4192 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4194 index
= env
->cpuid_level
;
4199 *eax
= env
->cpuid_level
;
4200 *ebx
= env
->cpuid_vendor1
;
4201 *edx
= env
->cpuid_vendor2
;
4202 *ecx
= env
->cpuid_vendor3
;
4205 *eax
= env
->cpuid_version
;
4206 *ebx
= (cpu
->apic_id
<< 24) |
4207 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
4208 *ecx
= env
->features
[FEAT_1_ECX
];
4209 if ((*ecx
& CPUID_EXT_XSAVE
) && (env
->cr
[4] & CR4_OSXSAVE_MASK
)) {
4210 *ecx
|= CPUID_EXT_OSXSAVE
;
4212 *edx
= env
->features
[FEAT_1_EDX
];
4213 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
4214 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
4219 /* cache info: needed for Pentium Pro compatibility */
4220 if (cpu
->cache_info_passthrough
) {
4221 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
4224 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
4226 if (!cpu
->enable_l3_cache
) {
4229 *ecx
= cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l3_cache
);
4231 *edx
= (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l1d_cache
) << 16) |
4232 (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l1i_cache
) << 8) |
4233 (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l2_cache
));
4236 /* cache info: needed for Core compatibility */
4237 if (cpu
->cache_info_passthrough
) {
4238 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
4239 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
4240 *eax
&= ~0xFC000000;
4241 if ((*eax
& 31) && cs
->nr_cores
> 1) {
4242 *eax
|= (cs
->nr_cores
- 1) << 26;
4247 case 0: /* L1 dcache info */
4248 encode_cache_cpuid4(env
->cache_info_cpuid4
.l1d_cache
,
4250 eax
, ebx
, ecx
, edx
);
4252 case 1: /* L1 icache info */
4253 encode_cache_cpuid4(env
->cache_info_cpuid4
.l1i_cache
,
4255 eax
, ebx
, ecx
, edx
);
4257 case 2: /* L2 cache info */
4258 encode_cache_cpuid4(env
->cache_info_cpuid4
.l2_cache
,
4259 cs
->nr_threads
, cs
->nr_cores
,
4260 eax
, ebx
, ecx
, edx
);
4262 case 3: /* L3 cache info */
4263 pkg_offset
= apicid_pkg_offset(cs
->nr_cores
, cs
->nr_threads
);
4264 if (cpu
->enable_l3_cache
) {
4265 encode_cache_cpuid4(env
->cache_info_cpuid4
.l3_cache
,
4266 (1 << pkg_offset
), cs
->nr_cores
,
4267 eax
, ebx
, ecx
, edx
);
4271 default: /* end of info */
4272 *eax
= *ebx
= *ecx
= *edx
= 0;
4278 /* MONITOR/MWAIT Leaf */
4279 *eax
= cpu
->mwait
.eax
; /* Smallest monitor-line size in bytes */
4280 *ebx
= cpu
->mwait
.ebx
; /* Largest monitor-line size in bytes */
4281 *ecx
= cpu
->mwait
.ecx
; /* flags */
4282 *edx
= cpu
->mwait
.edx
; /* mwait substates */
4285 /* Thermal and Power Leaf */
4286 *eax
= env
->features
[FEAT_6_EAX
];
4292 /* Structured Extended Feature Flags Enumeration Leaf */
4294 *eax
= 0; /* Maximum ECX value for sub-leaves */
4295 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
4296 *ecx
= env
->features
[FEAT_7_0_ECX
]; /* Feature flags */
4297 if ((*ecx
& CPUID_7_0_ECX_PKU
) && env
->cr
[4] & CR4_PKE_MASK
) {
4298 *ecx
|= CPUID_7_0_ECX_OSPKE
;
4300 *edx
= env
->features
[FEAT_7_0_EDX
]; /* Feature flags */
4309 /* Direct Cache Access Information Leaf */
4310 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
4316 /* Architectural Performance Monitoring Leaf */
4317 if (kvm_enabled() && cpu
->enable_pmu
) {
4318 KVMState
*s
= cs
->kvm_state
;
4320 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
4321 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
4322 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
4323 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
4324 } else if (hvf_enabled() && cpu
->enable_pmu
) {
4325 *eax
= hvf_get_supported_cpuid(0xA, count
, R_EAX
);
4326 *ebx
= hvf_get_supported_cpuid(0xA, count
, R_EBX
);
4327 *ecx
= hvf_get_supported_cpuid(0xA, count
, R_ECX
);
4328 *edx
= hvf_get_supported_cpuid(0xA, count
, R_EDX
);
4337 /* Extended Topology Enumeration Leaf */
4338 if (!cpu
->enable_cpuid_0xb
) {
4339 *eax
= *ebx
= *ecx
= *edx
= 0;
4343 *ecx
= count
& 0xff;
4344 *edx
= cpu
->apic_id
;
4348 *eax
= apicid_core_offset(cs
->nr_cores
, cs
->nr_threads
);
4349 *ebx
= cs
->nr_threads
;
4350 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
4353 *eax
= apicid_pkg_offset(cs
->nr_cores
, cs
->nr_threads
);
4354 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
4355 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
4360 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
4363 assert(!(*eax
& ~0x1f));
4364 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
4367 /* Processor Extended State */
4372 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
4377 *ecx
= xsave_area_size(x86_cpu_xsave_components(cpu
));
4378 *eax
= env
->features
[FEAT_XSAVE_COMP_LO
];
4379 *edx
= env
->features
[FEAT_XSAVE_COMP_HI
];
4380 *ebx
= xsave_area_size(env
->xcr0
);
4381 } else if (count
== 1) {
4382 *eax
= env
->features
[FEAT_XSAVE
];
4383 } else if (count
< ARRAY_SIZE(x86_ext_save_areas
)) {
4384 if ((x86_cpu_xsave_components(cpu
) >> count
) & 1) {
4385 const ExtSaveArea
*esa
= &x86_ext_save_areas
[count
];
4393 /* Intel Processor Trace Enumeration */
4398 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) ||
4404 *eax
= INTEL_PT_MAX_SUBLEAF
;
4405 *ebx
= INTEL_PT_MINIMAL_EBX
;
4406 *ecx
= INTEL_PT_MINIMAL_ECX
;
4407 } else if (count
== 1) {
4408 *eax
= INTEL_PT_MTC_BITMAP
| INTEL_PT_ADDR_RANGES_NUM
;
4409 *ebx
= INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
;
4415 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4416 * set here, but we restrict to TCG none the less.
4418 if (tcg_enabled() && cpu
->expose_tcg
) {
4419 memcpy(signature
, "TCGTCGTCGTCG", 12);
4421 *ebx
= signature
[0];
4422 *ecx
= signature
[1];
4423 *edx
= signature
[2];
4438 *eax
= env
->cpuid_xlevel
;
4439 *ebx
= env
->cpuid_vendor1
;
4440 *edx
= env
->cpuid_vendor2
;
4441 *ecx
= env
->cpuid_vendor3
;
4444 *eax
= env
->cpuid_version
;
4446 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
4447 *edx
= env
->features
[FEAT_8000_0001_EDX
];
4449 /* The Linux kernel checks for the CMPLegacy bit and
4450 * discards multiple thread information if it is set.
4451 * So don't set it here for Intel to make Linux guests happy.
4453 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
4454 if (env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
||
4455 env
->cpuid_vendor2
!= CPUID_VENDOR_INTEL_2
||
4456 env
->cpuid_vendor3
!= CPUID_VENDOR_INTEL_3
) {
4457 *ecx
|= 1 << 1; /* CmpLegacy bit */
4464 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
4465 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
4466 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
4467 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
4470 /* cache info (L1 cache) */
4471 if (cpu
->cache_info_passthrough
) {
4472 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
4475 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
4476 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
4477 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
4478 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
4479 *ecx
= encode_cache_cpuid80000005(env
->cache_info_amd
.l1d_cache
);
4480 *edx
= encode_cache_cpuid80000005(env
->cache_info_amd
.l1i_cache
);
4483 /* cache info (L2 cache) */
4484 if (cpu
->cache_info_passthrough
) {
4485 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
4488 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
4489 (L2_DTLB_2M_ENTRIES
<< 16) | \
4490 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
4491 (L2_ITLB_2M_ENTRIES
);
4492 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
4493 (L2_DTLB_4K_ENTRIES
<< 16) | \
4494 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
4495 (L2_ITLB_4K_ENTRIES
);
4496 encode_cache_cpuid80000006(env
->cache_info_amd
.l2_cache
,
4497 cpu
->enable_l3_cache
?
4498 env
->cache_info_amd
.l3_cache
: NULL
,
4505 *edx
= env
->features
[FEAT_8000_0007_EDX
];
4508 /* virtual & phys address size in low 2 bytes. */
4509 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
4510 /* 64 bit processor */
4511 *eax
= cpu
->phys_bits
; /* configurable physical bits */
4512 if (env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
) {
4513 *eax
|= 0x00003900; /* 57 bits virtual */
4515 *eax
|= 0x00003000; /* 48 bits virtual */
4518 *eax
= cpu
->phys_bits
;
4520 *ebx
= env
->features
[FEAT_8000_0008_EBX
];
4523 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
4524 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
4528 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
4529 *eax
= 0x00000001; /* SVM Revision */
4530 *ebx
= 0x00000010; /* nr of ASIDs */
4532 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
4543 case 0: /* L1 dcache info */
4544 encode_cache_cpuid8000001d(env
->cache_info_amd
.l1d_cache
, cs
,
4545 eax
, ebx
, ecx
, edx
);
4547 case 1: /* L1 icache info */
4548 encode_cache_cpuid8000001d(env
->cache_info_amd
.l1i_cache
, cs
,
4549 eax
, ebx
, ecx
, edx
);
4551 case 2: /* L2 cache info */
4552 encode_cache_cpuid8000001d(env
->cache_info_amd
.l2_cache
, cs
,
4553 eax
, ebx
, ecx
, edx
);
4555 case 3: /* L3 cache info */
4556 encode_cache_cpuid8000001d(env
->cache_info_amd
.l3_cache
, cs
,
4557 eax
, ebx
, ecx
, edx
);
4559 default: /* end of info */
4560 *eax
= *ebx
= *ecx
= *edx
= 0;
4565 assert(cpu
->core_id
<= 255);
4566 encode_topo_cpuid8000001e(cs
, cpu
,
4567 eax
, ebx
, ecx
, edx
);
4570 *eax
= env
->cpuid_xlevel2
;
4576 /* Support for VIA CPU's CPUID instruction */
4577 *eax
= env
->cpuid_version
;
4580 *edx
= env
->features
[FEAT_C000_0001_EDX
];
4585 /* Reserved for the future, and now filled with zero */
4592 *eax
= sev_enabled() ? 0x2 : 0;
4593 *ebx
= sev_get_cbit_position();
4594 *ebx
|= sev_get_reduced_phys_bits() << 6;
4599 /* reserved values: zero */
4608 /* CPUClass::reset() */
4609 static void x86_cpu_reset(CPUState
*s
)
4611 X86CPU
*cpu
= X86_CPU(s
);
4612 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
4613 CPUX86State
*env
= &cpu
->env
;
4618 xcc
->parent_reset(s
);
4620 memset(env
, 0, offsetof(CPUX86State
, end_reset_fields
));
4622 env
->old_exception
= -1;
4624 /* init to reset state */
4626 env
->hflags2
|= HF2_GIF_MASK
;
4628 cpu_x86_update_cr0(env
, 0x60000010);
4629 env
->a20_mask
= ~0x0;
4630 env
->smbase
= 0x30000;
4631 env
->msr_smi_count
= 0;
4633 env
->idt
.limit
= 0xffff;
4634 env
->gdt
.limit
= 0xffff;
4635 env
->ldt
.limit
= 0xffff;
4636 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
4637 env
->tr
.limit
= 0xffff;
4638 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
4640 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
4641 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
4642 DESC_R_MASK
| DESC_A_MASK
);
4643 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
4644 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
4646 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
4647 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
4649 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
4650 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
4652 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
4653 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
4655 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
4656 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
4660 env
->regs
[R_EDX
] = env
->cpuid_version
;
4665 for (i
= 0; i
< 8; i
++) {
4668 cpu_set_fpuc(env
, 0x37f);
4670 env
->mxcsr
= 0x1f80;
4671 /* All units are in INIT state. */
4674 env
->pat
= 0x0007040600070406ULL
;
4675 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
4677 memset(env
->dr
, 0, sizeof(env
->dr
));
4678 env
->dr
[6] = DR6_FIXED_1
;
4679 env
->dr
[7] = DR7_FIXED_1
;
4680 cpu_breakpoint_remove_all(s
, BP_CPU
);
4681 cpu_watchpoint_remove_all(s
, BP_CPU
);
4684 xcr0
= XSTATE_FP_MASK
;
4686 #ifdef CONFIG_USER_ONLY
4687 /* Enable all the features for user-mode. */
4688 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
4689 xcr0
|= XSTATE_SSE_MASK
;
4691 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
4692 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
4693 if (env
->features
[esa
->feature
] & esa
->bits
) {
4698 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) {
4699 cr4
|= CR4_OSFXSR_MASK
| CR4_OSXSAVE_MASK
;
4701 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
) {
4702 cr4
|= CR4_FSGSBASE_MASK
;
4707 cpu_x86_update_cr4(env
, cr4
);
4710 * SDM 11.11.5 requires:
4711 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4712 * - IA32_MTRR_PHYSMASKn.V = 0
4713 * All other bits are undefined. For simplification, zero it all.
4715 env
->mtrr_deftype
= 0;
4716 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
4717 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
4719 env
->interrupt_injected
= -1;
4720 env
->exception_injected
= -1;
4721 env
->nmi_injected
= false;
4722 #if !defined(CONFIG_USER_ONLY)
4723 /* We hard-wire the BSP to the first CPU. */
4724 apic_designate_bsp(cpu
->apic_state
, s
->cpu_index
== 0);
4726 s
->halted
= !cpu_is_bsp(cpu
);
4728 if (kvm_enabled()) {
4729 kvm_arch_reset_vcpu(cpu
);
4731 else if (hvf_enabled()) {
4737 #ifndef CONFIG_USER_ONLY
4738 bool cpu_is_bsp(X86CPU
*cpu
)
4740 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
4743 /* TODO: remove me, when reset over QOM tree is implemented */
4744 static void x86_cpu_machine_reset_cb(void *opaque
)
4746 X86CPU
*cpu
= opaque
;
4747 cpu_reset(CPU(cpu
));
4751 static void mce_init(X86CPU
*cpu
)
4753 CPUX86State
*cenv
= &cpu
->env
;
4756 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
4757 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
4758 (CPUID_MCE
| CPUID_MCA
)) {
4759 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
|
4760 (cpu
->enable_lmce
? MCG_LMCE_P
: 0);
4761 cenv
->mcg_ctl
= ~(uint64_t)0;
4762 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
4763 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
4768 #ifndef CONFIG_USER_ONLY
4769 APICCommonClass
*apic_get_class(void)
4771 const char *apic_type
= "apic";
4773 /* TODO: in-kernel irqchip for hvf */
4774 if (kvm_apic_in_kernel()) {
4775 apic_type
= "kvm-apic";
4776 } else if (xen_enabled()) {
4777 apic_type
= "xen-apic";
4780 return APIC_COMMON_CLASS(object_class_by_name(apic_type
));
4783 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
4785 APICCommonState
*apic
;
4786 ObjectClass
*apic_class
= OBJECT_CLASS(apic_get_class());
4788 cpu
->apic_state
= DEVICE(object_new(object_class_get_name(apic_class
)));
4790 object_property_add_child(OBJECT(cpu
), "lapic",
4791 OBJECT(cpu
->apic_state
), &error_abort
);
4792 object_unref(OBJECT(cpu
->apic_state
));
4794 qdev_prop_set_uint32(cpu
->apic_state
, "id", cpu
->apic_id
);
4795 /* TODO: convert to link<> */
4796 apic
= APIC_COMMON(cpu
->apic_state
);
4798 apic
->apicbase
= APIC_DEFAULT_ADDRESS
| MSR_IA32_APICBASE_ENABLE
;
4801 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
4803 APICCommonState
*apic
;
4804 static bool apic_mmio_map_once
;
4806 if (cpu
->apic_state
== NULL
) {
4809 object_property_set_bool(OBJECT(cpu
->apic_state
), true, "realized",
4812 /* Map APIC MMIO area */
4813 apic
= APIC_COMMON(cpu
->apic_state
);
4814 if (!apic_mmio_map_once
) {
4815 memory_region_add_subregion_overlap(get_system_memory(),
4817 MSR_IA32_APICBASE_BASE
,
4820 apic_mmio_map_once
= true;
4824 static void x86_cpu_machine_done(Notifier
*n
, void *unused
)
4826 X86CPU
*cpu
= container_of(n
, X86CPU
, machine_done
);
4827 MemoryRegion
*smram
=
4828 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
4831 cpu
->smram
= g_new(MemoryRegion
, 1);
4832 memory_region_init_alias(cpu
->smram
, OBJECT(cpu
), "smram",
4833 smram
, 0, 1ull << 32);
4834 memory_region_set_enabled(cpu
->smram
, true);
4835 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->smram
, 1);
4839 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
4844 /* Note: Only safe for use on x86(-64) hosts */
4845 static uint32_t x86_host_phys_bits(void)
4848 uint32_t host_phys_bits
;
4850 host_cpuid(0x80000000, 0, &eax
, NULL
, NULL
, NULL
);
4851 if (eax
>= 0x80000008) {
4852 host_cpuid(0x80000008, 0, &eax
, NULL
, NULL
, NULL
);
4853 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4854 * at 23:16 that can specify a maximum physical address bits for
4855 * the guest that can override this value; but I've not seen
4856 * anything with that set.
4858 host_phys_bits
= eax
& 0xff;
4860 /* It's an odd 64 bit machine that doesn't have the leaf for
4861 * physical address bits; fall back to 36 that's most older
4864 host_phys_bits
= 36;
4867 return host_phys_bits
;
4870 static void x86_cpu_adjust_level(X86CPU
*cpu
, uint32_t *min
, uint32_t value
)
4877 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4878 static void x86_cpu_adjust_feat_level(X86CPU
*cpu
, FeatureWord w
)
4880 CPUX86State
*env
= &cpu
->env
;
4881 FeatureWordInfo
*fi
= &feature_word_info
[w
];
4882 uint32_t eax
= fi
->cpuid
.eax
;
4883 uint32_t region
= eax
& 0xF0000000;
4885 assert(feature_word_info
[w
].type
== CPUID_FEATURE_WORD
);
4886 if (!env
->features
[w
]) {
4892 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, eax
);
4895 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, eax
);
4898 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel2
, eax
);
4903 /* Calculate XSAVE components based on the configured CPU feature flags */
4904 static void x86_cpu_enable_xsave_components(X86CPU
*cpu
)
4906 CPUX86State
*env
= &cpu
->env
;
4910 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
4915 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
4916 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
4917 if (env
->features
[esa
->feature
] & esa
->bits
) {
4918 mask
|= (1ULL << i
);
4922 env
->features
[FEAT_XSAVE_COMP_LO
] = mask
;
4923 env
->features
[FEAT_XSAVE_COMP_HI
] = mask
>> 32;
4926 /***** Steps involved on loading and filtering CPUID data
4928 * When initializing and realizing a CPU object, the steps
4929 * involved in setting up CPUID data are:
4931 * 1) Loading CPU model definition (X86CPUDefinition). This is
4932 * implemented by x86_cpu_load_def() and should be completely
4933 * transparent, as it is done automatically by instance_init.
4934 * No code should need to look at X86CPUDefinition structs
4935 * outside instance_init.
4937 * 2) CPU expansion. This is done by realize before CPUID
4938 * filtering, and will make sure host/accelerator data is
4939 * loaded for CPU models that depend on host capabilities
4940 * (e.g. "host"). Done by x86_cpu_expand_features().
4942 * 3) CPUID filtering. This initializes extra data related to
4943 * CPUID, and checks if the host supports all capabilities
4944 * required by the CPU. Runnability of a CPU model is
4945 * determined at this step. Done by x86_cpu_filter_features().
4947 * Some operations don't require all steps to be performed.
4950 * - CPU instance creation (instance_init) will run only CPU
4951 * model loading. CPU expansion can't run at instance_init-time
4952 * because host/accelerator data may be not available yet.
4953 * - CPU realization will perform both CPU model expansion and CPUID
4954 * filtering, and return an error in case one of them fails.
4955 * - query-cpu-definitions needs to run all 3 steps. It needs
4956 * to run CPUID filtering, as the 'unavailable-features'
4957 * field is set based on the filtering results.
4958 * - The query-cpu-model-expansion QMP command only needs to run
4959 * CPU model loading and CPU expansion. It should not filter
4960 * any CPUID data based on host capabilities.
4963 /* Expand CPU configuration data, based on configured features
4964 * and host/accelerator capabilities when appropriate.
4966 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
)
4968 CPUX86State
*env
= &cpu
->env
;
4971 Error
*local_err
= NULL
;
4973 /*TODO: Now cpu->max_features doesn't overwrite features
4974 * set using QOM properties, and we can convert
4975 * plus_features & minus_features to global properties
4976 * inside x86_cpu_parse_featurestr() too.
4978 if (cpu
->max_features
) {
4979 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
4980 /* Override only features that weren't set explicitly
4984 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
) &
4985 ~env
->user_features
[w
] & \
4986 ~feature_word_info
[w
].no_autoenable_flags
;
4990 for (l
= plus_features
; l
; l
= l
->next
) {
4991 const char *prop
= l
->data
;
4992 object_property_set_bool(OBJECT(cpu
), true, prop
, &local_err
);
4998 for (l
= minus_features
; l
; l
= l
->next
) {
4999 const char *prop
= l
->data
;
5000 object_property_set_bool(OBJECT(cpu
), false, prop
, &local_err
);
5006 if (!kvm_enabled() || !cpu
->expose_kvm
) {
5007 env
->features
[FEAT_KVM
] = 0;
5010 x86_cpu_enable_xsave_components(cpu
);
5012 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
5013 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_EBX
);
5014 if (cpu
->full_cpuid_auto_level
) {
5015 x86_cpu_adjust_feat_level(cpu
, FEAT_1_EDX
);
5016 x86_cpu_adjust_feat_level(cpu
, FEAT_1_ECX
);
5017 x86_cpu_adjust_feat_level(cpu
, FEAT_6_EAX
);
5018 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_ECX
);
5019 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_EDX
);
5020 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_ECX
);
5021 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0007_EDX
);
5022 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0008_EBX
);
5023 x86_cpu_adjust_feat_level(cpu
, FEAT_C000_0001_EDX
);
5024 x86_cpu_adjust_feat_level(cpu
, FEAT_SVM
);
5025 x86_cpu_adjust_feat_level(cpu
, FEAT_XSAVE
);
5026 /* SVM requires CPUID[0x8000000A] */
5027 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
5028 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000000A);
5031 /* SEV requires CPUID[0x8000001F] */
5032 if (sev_enabled()) {
5033 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000001F);
5037 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
5038 if (env
->cpuid_level
== UINT32_MAX
) {
5039 env
->cpuid_level
= env
->cpuid_min_level
;
5041 if (env
->cpuid_xlevel
== UINT32_MAX
) {
5042 env
->cpuid_xlevel
= env
->cpuid_min_xlevel
;
5044 if (env
->cpuid_xlevel2
== UINT32_MAX
) {
5045 env
->cpuid_xlevel2
= env
->cpuid_min_xlevel2
;
5049 if (local_err
!= NULL
) {
5050 error_propagate(errp
, local_err
);
5055 * Finishes initialization of CPUID data, filters CPU feature
5056 * words based on host availability of each feature.
5058 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5060 static int x86_cpu_filter_features(X86CPU
*cpu
)
5062 CPUX86State
*env
= &cpu
->env
;
5066 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5067 uint32_t host_feat
=
5068 x86_cpu_get_supported_feature_word(w
, false);
5069 uint32_t requested_features
= env
->features
[w
];
5070 env
->features
[w
] &= host_feat
;
5071 cpu
->filtered_features
[w
] = requested_features
& ~env
->features
[w
];
5072 if (cpu
->filtered_features
[w
]) {
5077 if ((env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) &&
5079 KVMState
*s
= CPU(cpu
)->kvm_state
;
5080 uint32_t eax_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_EAX
);
5081 uint32_t ebx_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_EBX
);
5082 uint32_t ecx_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_ECX
);
5083 uint32_t eax_1
= kvm_arch_get_supported_cpuid(s
, 0x14, 1, R_EAX
);
5084 uint32_t ebx_1
= kvm_arch_get_supported_cpuid(s
, 0x14, 1, R_EBX
);
5087 ((ebx_0
& INTEL_PT_MINIMAL_EBX
) != INTEL_PT_MINIMAL_EBX
) ||
5088 ((ecx_0
& INTEL_PT_MINIMAL_ECX
) != INTEL_PT_MINIMAL_ECX
) ||
5089 ((eax_1
& INTEL_PT_MTC_BITMAP
) != INTEL_PT_MTC_BITMAP
) ||
5090 ((eax_1
& INTEL_PT_ADDR_RANGES_NUM_MASK
) <
5091 INTEL_PT_ADDR_RANGES_NUM
) ||
5092 ((ebx_1
& (INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
)) !=
5093 (INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
)) ||
5094 (ecx_0
& INTEL_PT_IP_LIP
)) {
5096 * Processor Trace capabilities aren't configurable, so if the
5097 * host can't emulate the capabilities we report on
5098 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5100 env
->features
[FEAT_7_0_EBX
] &= ~CPUID_7_0_EBX_INTEL_PT
;
5101 cpu
->filtered_features
[FEAT_7_0_EBX
] |= CPUID_7_0_EBX_INTEL_PT
;
5109 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
5110 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
5111 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
5112 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
5113 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
5114 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
5115 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
5117 CPUState
*cs
= CPU(dev
);
5118 X86CPU
*cpu
= X86_CPU(dev
);
5119 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
5120 CPUX86State
*env
= &cpu
->env
;
5121 Error
*local_err
= NULL
;
5122 static bool ht_warned
;
5124 if (xcc
->host_cpuid_required
) {
5125 if (!accel_uses_host_cpuid()) {
5126 char *name
= x86_cpu_class_get_model_name(xcc
);
5127 error_setg(&local_err
, "CPU model '%s' requires KVM", name
);
5132 if (enable_cpu_pm
) {
5133 host_cpuid(5, 0, &cpu
->mwait
.eax
, &cpu
->mwait
.ebx
,
5134 &cpu
->mwait
.ecx
, &cpu
->mwait
.edx
);
5135 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_MONITOR
;
5139 /* mwait extended info: needed for Core compatibility */
5140 /* We always wake on interrupt even if host does not have the capability */
5141 cpu
->mwait
.ecx
|= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
5143 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
5144 error_setg(errp
, "apic-id property was not initialized properly");
5148 x86_cpu_expand_features(cpu
, &local_err
);
5153 if (x86_cpu_filter_features(cpu
) &&
5154 (cpu
->check_cpuid
|| cpu
->enforce_cpuid
)) {
5155 x86_cpu_report_filtered_features(cpu
);
5156 if (cpu
->enforce_cpuid
) {
5157 error_setg(&local_err
,
5158 accel_uses_host_cpuid() ?
5159 "Host doesn't support requested features" :
5160 "TCG doesn't support requested features");
5165 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5168 if (IS_AMD_CPU(env
)) {
5169 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
5170 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
5171 & CPUID_EXT2_AMD_ALIASES
);
5174 /* For 64bit systems think about the number of physical bits to present.
5175 * ideally this should be the same as the host; anything other than matching
5176 * the host can cause incorrect guest behaviour.
5177 * QEMU used to pick the magic value of 40 bits that corresponds to
5178 * consumer AMD devices but nothing else.
5180 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
5181 if (accel_uses_host_cpuid()) {
5182 uint32_t host_phys_bits
= x86_host_phys_bits();
5185 if (cpu
->host_phys_bits
) {
5186 /* The user asked for us to use the host physical bits */
5187 cpu
->phys_bits
= host_phys_bits
;
5188 if (cpu
->host_phys_bits_limit
&&
5189 cpu
->phys_bits
> cpu
->host_phys_bits_limit
) {
5190 cpu
->phys_bits
= cpu
->host_phys_bits_limit
;
5194 /* Print a warning if the user set it to a value that's not the
5197 if (cpu
->phys_bits
!= host_phys_bits
&& cpu
->phys_bits
!= 0 &&
5199 warn_report("Host physical bits (%u)"
5200 " does not match phys-bits property (%u)",
5201 host_phys_bits
, cpu
->phys_bits
);
5205 if (cpu
->phys_bits
&&
5206 (cpu
->phys_bits
> TARGET_PHYS_ADDR_SPACE_BITS
||
5207 cpu
->phys_bits
< 32)) {
5208 error_setg(errp
, "phys-bits should be between 32 and %u "
5210 TARGET_PHYS_ADDR_SPACE_BITS
, cpu
->phys_bits
);
5214 if (cpu
->phys_bits
&& cpu
->phys_bits
!= TCG_PHYS_ADDR_BITS
) {
5215 error_setg(errp
, "TCG only supports phys-bits=%u",
5216 TCG_PHYS_ADDR_BITS
);
5220 /* 0 means it was not explicitly set by the user (or by machine
5221 * compat_props or by the host code above). In this case, the default
5222 * is the value used by TCG (40).
5224 if (cpu
->phys_bits
== 0) {
5225 cpu
->phys_bits
= TCG_PHYS_ADDR_BITS
;
5228 /* For 32 bit systems don't use the user set value, but keep
5229 * phys_bits consistent with what we tell the guest.
5231 if (cpu
->phys_bits
!= 0) {
5232 error_setg(errp
, "phys-bits is not user-configurable in 32 bit");
5236 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
5237 cpu
->phys_bits
= 36;
5239 cpu
->phys_bits
= 32;
5243 /* Cache information initialization */
5244 if (!cpu
->legacy_cache
) {
5245 if (!xcc
->cpu_def
|| !xcc
->cpu_def
->cache_info
) {
5246 char *name
= x86_cpu_class_get_model_name(xcc
);
5248 "CPU model '%s' doesn't support legacy-cache=off", name
);
5252 env
->cache_info_cpuid2
= env
->cache_info_cpuid4
= env
->cache_info_amd
=
5253 *xcc
->cpu_def
->cache_info
;
5255 /* Build legacy cache information */
5256 env
->cache_info_cpuid2
.l1d_cache
= &legacy_l1d_cache
;
5257 env
->cache_info_cpuid2
.l1i_cache
= &legacy_l1i_cache
;
5258 env
->cache_info_cpuid2
.l2_cache
= &legacy_l2_cache_cpuid2
;
5259 env
->cache_info_cpuid2
.l3_cache
= &legacy_l3_cache
;
5261 env
->cache_info_cpuid4
.l1d_cache
= &legacy_l1d_cache
;
5262 env
->cache_info_cpuid4
.l1i_cache
= &legacy_l1i_cache
;
5263 env
->cache_info_cpuid4
.l2_cache
= &legacy_l2_cache
;
5264 env
->cache_info_cpuid4
.l3_cache
= &legacy_l3_cache
;
5266 env
->cache_info_amd
.l1d_cache
= &legacy_l1d_cache_amd
;
5267 env
->cache_info_amd
.l1i_cache
= &legacy_l1i_cache_amd
;
5268 env
->cache_info_amd
.l2_cache
= &legacy_l2_cache_amd
;
5269 env
->cache_info_amd
.l3_cache
= &legacy_l3_cache
;
5273 cpu_exec_realizefn(cs
, &local_err
);
5274 if (local_err
!= NULL
) {
5275 error_propagate(errp
, local_err
);
5279 #ifndef CONFIG_USER_ONLY
5280 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
5282 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| smp_cpus
> 1) {
5283 x86_cpu_apic_create(cpu
, &local_err
);
5284 if (local_err
!= NULL
) {
5292 #ifndef CONFIG_USER_ONLY
5293 if (tcg_enabled()) {
5294 cpu
->cpu_as_mem
= g_new(MemoryRegion
, 1);
5295 cpu
->cpu_as_root
= g_new(MemoryRegion
, 1);
5297 /* Outer container... */
5298 memory_region_init(cpu
->cpu_as_root
, OBJECT(cpu
), "memory", ~0ull);
5299 memory_region_set_enabled(cpu
->cpu_as_root
, true);
5301 /* ... with two regions inside: normal system memory with low
5304 memory_region_init_alias(cpu
->cpu_as_mem
, OBJECT(cpu
), "memory",
5305 get_system_memory(), 0, ~0ull);
5306 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->cpu_as_mem
, 0);
5307 memory_region_set_enabled(cpu
->cpu_as_mem
, true);
5310 cpu_address_space_init(cs
, 0, "cpu-memory", cs
->memory
);
5311 cpu_address_space_init(cs
, 1, "cpu-smm", cpu
->cpu_as_root
);
5313 /* ... SMRAM with higher priority, linked from /machine/smram. */
5314 cpu
->machine_done
.notify
= x86_cpu_machine_done
;
5315 qemu_add_machine_init_done_notifier(&cpu
->machine_done
);
5322 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5323 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5324 * based on inputs (sockets,cores,threads), it is still better to give
5327 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5328 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5330 if (IS_AMD_CPU(env
) &&
5331 !(env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_TOPOEXT
) &&
5332 cs
->nr_threads
> 1 && !ht_warned
) {
5333 warn_report("This family of AMD CPU doesn't support "
5334 "hyperthreading(%d)",
5336 error_printf("Please configure -smp options properly"
5337 " or try enabling topoext feature.\n");
5341 x86_cpu_apic_realize(cpu
, &local_err
);
5342 if (local_err
!= NULL
) {
5347 xcc
->parent_realize(dev
, &local_err
);
5350 if (local_err
!= NULL
) {
5351 error_propagate(errp
, local_err
);
5356 static void x86_cpu_unrealizefn(DeviceState
*dev
, Error
**errp
)
5358 X86CPU
*cpu
= X86_CPU(dev
);
5359 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
5360 Error
*local_err
= NULL
;
5362 #ifndef CONFIG_USER_ONLY
5363 cpu_remove_sync(CPU(dev
));
5364 qemu_unregister_reset(x86_cpu_machine_reset_cb
, dev
);
5367 if (cpu
->apic_state
) {
5368 object_unparent(OBJECT(cpu
->apic_state
));
5369 cpu
->apic_state
= NULL
;
5372 xcc
->parent_unrealize(dev
, &local_err
);
5373 if (local_err
!= NULL
) {
5374 error_propagate(errp
, local_err
);
5379 typedef struct BitProperty
{
5384 static void x86_cpu_get_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
5385 void *opaque
, Error
**errp
)
5387 X86CPU
*cpu
= X86_CPU(obj
);
5388 BitProperty
*fp
= opaque
;
5389 uint32_t f
= cpu
->env
.features
[fp
->w
];
5390 bool value
= (f
& fp
->mask
) == fp
->mask
;
5391 visit_type_bool(v
, name
, &value
, errp
);
5394 static void x86_cpu_set_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
5395 void *opaque
, Error
**errp
)
5397 DeviceState
*dev
= DEVICE(obj
);
5398 X86CPU
*cpu
= X86_CPU(obj
);
5399 BitProperty
*fp
= opaque
;
5400 Error
*local_err
= NULL
;
5403 if (dev
->realized
) {
5404 qdev_prop_set_after_realize(dev
, name
, errp
);
5408 visit_type_bool(v
, name
, &value
, &local_err
);
5410 error_propagate(errp
, local_err
);
5415 cpu
->env
.features
[fp
->w
] |= fp
->mask
;
5417 cpu
->env
.features
[fp
->w
] &= ~fp
->mask
;
5419 cpu
->env
.user_features
[fp
->w
] |= fp
->mask
;
5422 static void x86_cpu_release_bit_prop(Object
*obj
, const char *name
,
5425 BitProperty
*prop
= opaque
;
5429 /* Register a boolean property to get/set a single bit in a uint32_t field.
5431 * The same property name can be registered multiple times to make it affect
5432 * multiple bits in the same FeatureWord. In that case, the getter will return
5433 * true only if all bits are set.
5435 static void x86_cpu_register_bit_prop(X86CPU
*cpu
,
5436 const char *prop_name
,
5442 uint32_t mask
= (1UL << bitnr
);
5444 op
= object_property_find(OBJECT(cpu
), prop_name
, NULL
);
5450 fp
= g_new0(BitProperty
, 1);
5453 object_property_add(OBJECT(cpu
), prop_name
, "bool",
5454 x86_cpu_get_bit_prop
,
5455 x86_cpu_set_bit_prop
,
5456 x86_cpu_release_bit_prop
, fp
, &error_abort
);
5460 static void x86_cpu_register_feature_bit_props(X86CPU
*cpu
,
5464 FeatureWordInfo
*fi
= &feature_word_info
[w
];
5465 const char *name
= fi
->feat_names
[bitnr
];
5471 /* Property names should use "-" instead of "_".
5472 * Old names containing underscores are registered as aliases
5473 * using object_property_add_alias()
5475 assert(!strchr(name
, '_'));
5476 /* aliases don't use "|" delimiters anymore, they are registered
5477 * manually using object_property_add_alias() */
5478 assert(!strchr(name
, '|'));
5479 x86_cpu_register_bit_prop(cpu
, name
, w
, bitnr
);
5482 static GuestPanicInformation
*x86_cpu_get_crash_info(CPUState
*cs
)
5484 X86CPU
*cpu
= X86_CPU(cs
);
5485 CPUX86State
*env
= &cpu
->env
;
5486 GuestPanicInformation
*panic_info
= NULL
;
5488 if (env
->features
[FEAT_HYPERV_EDX
] & HV_GUEST_CRASH_MSR_AVAILABLE
) {
5489 panic_info
= g_malloc0(sizeof(GuestPanicInformation
));
5491 panic_info
->type
= GUEST_PANIC_INFORMATION_TYPE_HYPER_V
;
5493 assert(HV_CRASH_PARAMS
>= 5);
5494 panic_info
->u
.hyper_v
.arg1
= env
->msr_hv_crash_params
[0];
5495 panic_info
->u
.hyper_v
.arg2
= env
->msr_hv_crash_params
[1];
5496 panic_info
->u
.hyper_v
.arg3
= env
->msr_hv_crash_params
[2];
5497 panic_info
->u
.hyper_v
.arg4
= env
->msr_hv_crash_params
[3];
5498 panic_info
->u
.hyper_v
.arg5
= env
->msr_hv_crash_params
[4];
5503 static void x86_cpu_get_crash_info_qom(Object
*obj
, Visitor
*v
,
5504 const char *name
, void *opaque
,
5507 CPUState
*cs
= CPU(obj
);
5508 GuestPanicInformation
*panic_info
;
5510 if (!cs
->crash_occurred
) {
5511 error_setg(errp
, "No crash occured");
5515 panic_info
= x86_cpu_get_crash_info(cs
);
5516 if (panic_info
== NULL
) {
5517 error_setg(errp
, "No crash information");
5521 visit_type_GuestPanicInformation(v
, "crash-information", &panic_info
,
5523 qapi_free_GuestPanicInformation(panic_info
);
5526 static void x86_cpu_initfn(Object
*obj
)
5528 CPUState
*cs
= CPU(obj
);
5529 X86CPU
*cpu
= X86_CPU(obj
);
5530 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
5531 CPUX86State
*env
= &cpu
->env
;
5536 object_property_add(obj
, "family", "int",
5537 x86_cpuid_version_get_family
,
5538 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
5539 object_property_add(obj
, "model", "int",
5540 x86_cpuid_version_get_model
,
5541 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
5542 object_property_add(obj
, "stepping", "int",
5543 x86_cpuid_version_get_stepping
,
5544 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
5545 object_property_add_str(obj
, "vendor",
5546 x86_cpuid_get_vendor
,
5547 x86_cpuid_set_vendor
, NULL
);
5548 object_property_add_str(obj
, "model-id",
5549 x86_cpuid_get_model_id
,
5550 x86_cpuid_set_model_id
, NULL
);
5551 object_property_add(obj
, "tsc-frequency", "int",
5552 x86_cpuid_get_tsc_freq
,
5553 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
5554 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
5555 x86_cpu_get_feature_words
,
5556 NULL
, NULL
, (void *)env
->features
, NULL
);
5557 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
5558 x86_cpu_get_feature_words
,
5559 NULL
, NULL
, (void *)cpu
->filtered_features
, NULL
);
5561 object_property_add(obj
, "crash-information", "GuestPanicInformation",
5562 x86_cpu_get_crash_info_qom
, NULL
, NULL
, NULL
, NULL
);
5564 cpu
->hyperv_spinlock_attempts
= HYPERV_SPINLOCK_NEVER_RETRY
;
5566 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5569 for (bitnr
= 0; bitnr
< 32; bitnr
++) {
5570 x86_cpu_register_feature_bit_props(cpu
, w
, bitnr
);
5574 object_property_add_alias(obj
, "sse3", obj
, "pni", &error_abort
);
5575 object_property_add_alias(obj
, "pclmuldq", obj
, "pclmulqdq", &error_abort
);
5576 object_property_add_alias(obj
, "sse4-1", obj
, "sse4.1", &error_abort
);
5577 object_property_add_alias(obj
, "sse4-2", obj
, "sse4.2", &error_abort
);
5578 object_property_add_alias(obj
, "xd", obj
, "nx", &error_abort
);
5579 object_property_add_alias(obj
, "ffxsr", obj
, "fxsr-opt", &error_abort
);
5580 object_property_add_alias(obj
, "i64", obj
, "lm", &error_abort
);
5582 object_property_add_alias(obj
, "ds_cpl", obj
, "ds-cpl", &error_abort
);
5583 object_property_add_alias(obj
, "tsc_adjust", obj
, "tsc-adjust", &error_abort
);
5584 object_property_add_alias(obj
, "fxsr_opt", obj
, "fxsr-opt", &error_abort
);
5585 object_property_add_alias(obj
, "lahf_lm", obj
, "lahf-lm", &error_abort
);
5586 object_property_add_alias(obj
, "cmp_legacy", obj
, "cmp-legacy", &error_abort
);
5587 object_property_add_alias(obj
, "nodeid_msr", obj
, "nodeid-msr", &error_abort
);
5588 object_property_add_alias(obj
, "perfctr_core", obj
, "perfctr-core", &error_abort
);
5589 object_property_add_alias(obj
, "perfctr_nb", obj
, "perfctr-nb", &error_abort
);
5590 object_property_add_alias(obj
, "kvm_nopiodelay", obj
, "kvm-nopiodelay", &error_abort
);
5591 object_property_add_alias(obj
, "kvm_mmu", obj
, "kvm-mmu", &error_abort
);
5592 object_property_add_alias(obj
, "kvm_asyncpf", obj
, "kvm-asyncpf", &error_abort
);
5593 object_property_add_alias(obj
, "kvm_steal_time", obj
, "kvm-steal-time", &error_abort
);
5594 object_property_add_alias(obj
, "kvm_pv_eoi", obj
, "kvm-pv-eoi", &error_abort
);
5595 object_property_add_alias(obj
, "kvm_pv_unhalt", obj
, "kvm-pv-unhalt", &error_abort
);
5596 object_property_add_alias(obj
, "svm_lock", obj
, "svm-lock", &error_abort
);
5597 object_property_add_alias(obj
, "nrip_save", obj
, "nrip-save", &error_abort
);
5598 object_property_add_alias(obj
, "tsc_scale", obj
, "tsc-scale", &error_abort
);
5599 object_property_add_alias(obj
, "vmcb_clean", obj
, "vmcb-clean", &error_abort
);
5600 object_property_add_alias(obj
, "pause_filter", obj
, "pause-filter", &error_abort
);
5601 object_property_add_alias(obj
, "sse4_1", obj
, "sse4.1", &error_abort
);
5602 object_property_add_alias(obj
, "sse4_2", obj
, "sse4.2", &error_abort
);
5605 x86_cpu_load_def(cpu
, xcc
->cpu_def
, &error_abort
);
5609 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
5611 X86CPU
*cpu
= X86_CPU(cs
);
5613 return cpu
->apic_id
;
5616 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
5618 X86CPU
*cpu
= X86_CPU(cs
);
5620 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
5623 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
5625 X86CPU
*cpu
= X86_CPU(cs
);
5627 cpu
->env
.eip
= value
;
5630 static void x86_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
5632 X86CPU
*cpu
= X86_CPU(cs
);
5634 cpu
->env
.eip
= tb
->pc
- tb
->cs_base
;
5637 int x86_cpu_pending_interrupt(CPUState
*cs
, int interrupt_request
)
5639 X86CPU
*cpu
= X86_CPU(cs
);
5640 CPUX86State
*env
= &cpu
->env
;
5642 #if !defined(CONFIG_USER_ONLY)
5643 if (interrupt_request
& CPU_INTERRUPT_POLL
) {
5644 return CPU_INTERRUPT_POLL
;
5647 if (interrupt_request
& CPU_INTERRUPT_SIPI
) {
5648 return CPU_INTERRUPT_SIPI
;
5651 if (env
->hflags2
& HF2_GIF_MASK
) {
5652 if ((interrupt_request
& CPU_INTERRUPT_SMI
) &&
5653 !(env
->hflags
& HF_SMM_MASK
)) {
5654 return CPU_INTERRUPT_SMI
;
5655 } else if ((interrupt_request
& CPU_INTERRUPT_NMI
) &&
5656 !(env
->hflags2
& HF2_NMI_MASK
)) {
5657 return CPU_INTERRUPT_NMI
;
5658 } else if (interrupt_request
& CPU_INTERRUPT_MCE
) {
5659 return CPU_INTERRUPT_MCE
;
5660 } else if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
5661 (((env
->hflags2
& HF2_VINTR_MASK
) &&
5662 (env
->hflags2
& HF2_HIF_MASK
)) ||
5663 (!(env
->hflags2
& HF2_VINTR_MASK
) &&
5664 (env
->eflags
& IF_MASK
&&
5665 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
))))) {
5666 return CPU_INTERRUPT_HARD
;
5667 #if !defined(CONFIG_USER_ONLY)
5668 } else if ((interrupt_request
& CPU_INTERRUPT_VIRQ
) &&
5669 (env
->eflags
& IF_MASK
) &&
5670 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
5671 return CPU_INTERRUPT_VIRQ
;
5679 static bool x86_cpu_has_work(CPUState
*cs
)
5681 return x86_cpu_pending_interrupt(cs
, cs
->interrupt_request
) != 0;
5684 static void x86_disas_set_info(CPUState
*cs
, disassemble_info
*info
)
5686 X86CPU
*cpu
= X86_CPU(cs
);
5687 CPUX86State
*env
= &cpu
->env
;
5689 info
->mach
= (env
->hflags
& HF_CS64_MASK
? bfd_mach_x86_64
5690 : env
->hflags
& HF_CS32_MASK
? bfd_mach_i386_i386
5691 : bfd_mach_i386_i8086
);
5692 info
->print_insn
= print_insn_i386
;
5694 info
->cap_arch
= CS_ARCH_X86
;
5695 info
->cap_mode
= (env
->hflags
& HF_CS64_MASK
? CS_MODE_64
5696 : env
->hflags
& HF_CS32_MASK
? CS_MODE_32
5698 info
->cap_insn_unit
= 1;
5699 info
->cap_insn_split
= 8;
5702 void x86_update_hflags(CPUX86State
*env
)
5705 #define HFLAG_COPY_MASK \
5706 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5707 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5708 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5709 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5711 hflags
= env
->hflags
& HFLAG_COPY_MASK
;
5712 hflags
|= (env
->segs
[R_SS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
5713 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
5714 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
5715 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
5716 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
5718 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
5719 hflags
|= HF_OSFXSR_MASK
;
5722 if (env
->efer
& MSR_EFER_LMA
) {
5723 hflags
|= HF_LMA_MASK
;
5726 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
5727 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
5729 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
5730 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
5731 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
5732 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
5733 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
5734 !(hflags
& HF_CS32_MASK
)) {
5735 hflags
|= HF_ADDSEG_MASK
;
5737 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
5738 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
5741 env
->hflags
= hflags
;
5744 static Property x86_cpu_properties
[] = {
5745 #ifdef CONFIG_USER_ONLY
5746 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5747 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, 0),
5748 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, 0),
5749 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, 0),
5750 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, 0),
5752 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, UNASSIGNED_APIC_ID
),
5753 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, -1),
5754 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, -1),
5755 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, -1),
5757 DEFINE_PROP_INT32("node-id", X86CPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
5758 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
5759 { .name
= "hv-spinlocks", .info
= &qdev_prop_spinlocks
},
5760 DEFINE_PROP_BOOL("hv-relaxed", X86CPU
, hyperv_relaxed_timing
, false),
5761 DEFINE_PROP_BOOL("hv-vapic", X86CPU
, hyperv_vapic
, false),
5762 DEFINE_PROP_BOOL("hv-time", X86CPU
, hyperv_time
, false),
5763 DEFINE_PROP_BOOL("hv-crash", X86CPU
, hyperv_crash
, false),
5764 DEFINE_PROP_BOOL("hv-reset", X86CPU
, hyperv_reset
, false),
5765 DEFINE_PROP_BOOL("hv-vpindex", X86CPU
, hyperv_vpindex
, false),
5766 DEFINE_PROP_BOOL("hv-runtime", X86CPU
, hyperv_runtime
, false),
5767 DEFINE_PROP_BOOL("hv-synic", X86CPU
, hyperv_synic
, false),
5768 DEFINE_PROP_BOOL("hv-stimer", X86CPU
, hyperv_stimer
, false),
5769 DEFINE_PROP_BOOL("hv-frequencies", X86CPU
, hyperv_frequencies
, false),
5770 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU
, hyperv_reenlightenment
, false),
5771 DEFINE_PROP_BOOL("hv-tlbflush", X86CPU
, hyperv_tlbflush
, false),
5772 DEFINE_PROP_BOOL("hv-evmcs", X86CPU
, hyperv_evmcs
, false),
5773 DEFINE_PROP_BOOL("hv-ipi", X86CPU
, hyperv_ipi
, false),
5774 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, true),
5775 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
5776 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
5777 DEFINE_PROP_UINT32("phys-bits", X86CPU
, phys_bits
, 0),
5778 DEFINE_PROP_BOOL("host-phys-bits", X86CPU
, host_phys_bits
, false),
5779 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU
, host_phys_bits_limit
, 0),
5780 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU
, fill_mtrr_mask
, true),
5781 DEFINE_PROP_UINT32("level", X86CPU
, env
.cpuid_level
, UINT32_MAX
),
5782 DEFINE_PROP_UINT32("xlevel", X86CPU
, env
.cpuid_xlevel
, UINT32_MAX
),
5783 DEFINE_PROP_UINT32("xlevel2", X86CPU
, env
.cpuid_xlevel2
, UINT32_MAX
),
5784 DEFINE_PROP_UINT32("min-level", X86CPU
, env
.cpuid_min_level
, 0),
5785 DEFINE_PROP_UINT32("min-xlevel", X86CPU
, env
.cpuid_min_xlevel
, 0),
5786 DEFINE_PROP_UINT32("min-xlevel2", X86CPU
, env
.cpuid_min_xlevel2
, 0),
5787 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU
, full_cpuid_auto_level
, true),
5788 DEFINE_PROP_STRING("hv-vendor-id", X86CPU
, hyperv_vendor_id
),
5789 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU
, enable_cpuid_0xb
, true),
5790 DEFINE_PROP_BOOL("lmce", X86CPU
, enable_lmce
, false),
5791 DEFINE_PROP_BOOL("l3-cache", X86CPU
, enable_l3_cache
, true),
5792 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU
, kvm_no_smi_migration
,
5794 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU
, vmware_cpuid_freq
, true),
5795 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU
, expose_tcg
, true),
5796 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU
, migrate_smi_count
,
5799 * lecacy_cache defaults to true unless the CPU model provides its
5800 * own cache information (see x86_cpu_load_def()).
5802 DEFINE_PROP_BOOL("legacy-cache", X86CPU
, legacy_cache
, true),
5805 * From "Requirements for Implementing the Microsoft
5806 * Hypervisor Interface":
5807 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5809 * "Starting with Windows Server 2012 and Windows 8, if
5810 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5811 * the hypervisor imposes no specific limit to the number of VPs.
5812 * In this case, Windows Server 2012 guest VMs may use more than
5813 * 64 VPs, up to the maximum supported number of processors applicable
5814 * to the specific Windows version being used."
5816 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU
, hv_max_vps
, -1),
5817 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU
, hyperv_synic_kvm_only
,
5819 DEFINE_PROP_END_OF_LIST()
5822 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
5824 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
5825 CPUClass
*cc
= CPU_CLASS(oc
);
5826 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5828 device_class_set_parent_realize(dc
, x86_cpu_realizefn
,
5829 &xcc
->parent_realize
);
5830 device_class_set_parent_unrealize(dc
, x86_cpu_unrealizefn
,
5831 &xcc
->parent_unrealize
);
5832 dc
->props
= x86_cpu_properties
;
5834 xcc
->parent_reset
= cc
->reset
;
5835 cc
->reset
= x86_cpu_reset
;
5836 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
5838 cc
->class_by_name
= x86_cpu_class_by_name
;
5839 cc
->parse_features
= x86_cpu_parse_featurestr
;
5840 cc
->has_work
= x86_cpu_has_work
;
5842 cc
->do_interrupt
= x86_cpu_do_interrupt
;
5843 cc
->cpu_exec_interrupt
= x86_cpu_exec_interrupt
;
5845 cc
->dump_state
= x86_cpu_dump_state
;
5846 cc
->get_crash_info
= x86_cpu_get_crash_info
;
5847 cc
->set_pc
= x86_cpu_set_pc
;
5848 cc
->synchronize_from_tb
= x86_cpu_synchronize_from_tb
;
5849 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
5850 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
5851 cc
->get_arch_id
= x86_cpu_get_arch_id
;
5852 cc
->get_paging_enabled
= x86_cpu_get_paging_enabled
;
5853 #ifdef CONFIG_USER_ONLY
5854 cc
->handle_mmu_fault
= x86_cpu_handle_mmu_fault
;
5856 cc
->asidx_from_attrs
= x86_asidx_from_attrs
;
5857 cc
->get_memory_mapping
= x86_cpu_get_memory_mapping
;
5858 cc
->get_phys_page_debug
= x86_cpu_get_phys_page_debug
;
5859 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
5860 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
5861 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
5862 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
5863 cc
->vmsd
= &vmstate_x86_cpu
;
5865 cc
->gdb_arch_name
= x86_gdb_arch_name
;
5866 #ifdef TARGET_X86_64
5867 cc
->gdb_core_xml_file
= "i386-64bit.xml";
5868 cc
->gdb_num_core_regs
= 57;
5870 cc
->gdb_core_xml_file
= "i386-32bit.xml";
5871 cc
->gdb_num_core_regs
= 41;
5873 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
5874 cc
->debug_excp_handler
= breakpoint_handler
;
5876 cc
->cpu_exec_enter
= x86_cpu_exec_enter
;
5877 cc
->cpu_exec_exit
= x86_cpu_exec_exit
;
5879 cc
->tcg_initialize
= tcg_x86_init
;
5881 cc
->disas_set_info
= x86_disas_set_info
;
5883 dc
->user_creatable
= true;
5886 static const TypeInfo x86_cpu_type_info
= {
5887 .name
= TYPE_X86_CPU
,
5889 .instance_size
= sizeof(X86CPU
),
5890 .instance_init
= x86_cpu_initfn
,
5892 .class_size
= sizeof(X86CPUClass
),
5893 .class_init
= x86_cpu_common_class_init
,
5897 /* "base" CPU model, used by query-cpu-model-expansion */
5898 static void x86_cpu_base_class_init(ObjectClass
*oc
, void *data
)
5900 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
5902 xcc
->static_model
= true;
5903 xcc
->migration_safe
= true;
5904 xcc
->model_description
= "base CPU model type with no features enabled";
5908 static const TypeInfo x86_base_cpu_type_info
= {
5909 .name
= X86_CPU_TYPE_NAME("base"),
5910 .parent
= TYPE_X86_CPU
,
5911 .class_init
= x86_cpu_base_class_init
,
5914 static void x86_cpu_register_types(void)
5918 type_register_static(&x86_cpu_type_info
);
5919 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
5920 x86_register_cpudef_type(&builtin_x86_defs
[i
]);
5922 type_register_static(&max_x86_cpu_type_info
);
5923 type_register_static(&x86_base_cpu_type_info
);
5924 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
5925 type_register_static(&host_x86_cpu_type_info
);
5929 type_init(x86_cpu_register_types
)