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target/i386: Add new property note to versioned CPU models
[mirror_qemu.git] / target / i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
25
26 #include "cpu.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/hvf.h"
31 #include "sysemu/cpus.h"
32 #include "kvm_i386.h"
33 #include "sev_i386.h"
34
35 #include "qemu/error-report.h"
36 #include "qemu/module.h"
37 #include "qemu/option.h"
38 #include "qemu/config-file.h"
39 #include "qapi/error.h"
40 #include "qapi/qapi-visit-machine.h"
41 #include "qapi/qapi-visit-run-state.h"
42 #include "qapi/qmp/qdict.h"
43 #include "qapi/qmp/qerror.h"
44 #include "qapi/visitor.h"
45 #include "qom/qom-qobject.h"
46 #include "sysemu/arch_init.h"
47 #include "qapi/qapi-commands-machine-target.h"
48
49 #include "standard-headers/asm-x86/kvm_para.h"
50
51 #include "sysemu/sysemu.h"
52 #include "sysemu/tcg.h"
53 #include "hw/qdev-properties.h"
54 #include "hw/i386/topology.h"
55 #ifndef CONFIG_USER_ONLY
56 #include "exec/address-spaces.h"
57 #include "hw/xen/xen.h"
58 #include "hw/i386/apic_internal.h"
59 #include "hw/boards.h"
60 #endif
61
62 #include "disas/capstone.h"
63
64 /* Helpers for building CPUID[2] descriptors: */
65
66 struct CPUID2CacheDescriptorInfo {
67 enum CacheType type;
68 int level;
69 int size;
70 int line_size;
71 int associativity;
72 };
73
74 /*
75 * Known CPUID 2 cache descriptors.
76 * From Intel SDM Volume 2A, CPUID instruction
77 */
78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
80 .associativity = 4, .line_size = 32, },
81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
82 .associativity = 4, .line_size = 32, },
83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
84 .associativity = 4, .line_size = 64, },
85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
86 .associativity = 2, .line_size = 32, },
87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
88 .associativity = 4, .line_size = 32, },
89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
90 .associativity = 4, .line_size = 64, },
91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
92 .associativity = 6, .line_size = 64, },
93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
94 .associativity = 2, .line_size = 64, },
95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
96 .associativity = 8, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x22, 0x23 are not included
99 */
100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
101 .associativity = 16, .line_size = 64, },
102 /* lines per sector is not supported cpuid2_cache_descriptor(),
103 * so descriptors 0x25, 0x20 are not included
104 */
105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
106 .associativity = 8, .line_size = 64, },
107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
108 .associativity = 8, .line_size = 64, },
109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
110 .associativity = 4, .line_size = 32, },
111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
112 .associativity = 4, .line_size = 32, },
113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
114 .associativity = 4, .line_size = 32, },
115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
116 .associativity = 4, .line_size = 32, },
117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
118 .associativity = 4, .line_size = 32, },
119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
120 .associativity = 4, .line_size = 64, },
121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
122 .associativity = 8, .line_size = 64, },
123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
124 .associativity = 12, .line_size = 64, },
125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
127 .associativity = 12, .line_size = 64, },
128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
129 .associativity = 16, .line_size = 64, },
130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
131 .associativity = 12, .line_size = 64, },
132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
133 .associativity = 16, .line_size = 64, },
134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
135 .associativity = 24, .line_size = 64, },
136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
137 .associativity = 8, .line_size = 64, },
138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
139 .associativity = 4, .line_size = 64, },
140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
141 .associativity = 4, .line_size = 64, },
142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
143 .associativity = 4, .line_size = 64, },
144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
145 .associativity = 4, .line_size = 64, },
146 /* lines per sector is not supported cpuid2_cache_descriptor(),
147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
148 */
149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
150 .associativity = 8, .line_size = 64, },
151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
152 .associativity = 2, .line_size = 64, },
153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
154 .associativity = 8, .line_size = 64, },
155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
156 .associativity = 8, .line_size = 32, },
157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
158 .associativity = 8, .line_size = 32, },
159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
160 .associativity = 8, .line_size = 32, },
161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
162 .associativity = 8, .line_size = 32, },
163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
164 .associativity = 4, .line_size = 64, },
165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
166 .associativity = 8, .line_size = 64, },
167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
168 .associativity = 4, .line_size = 64, },
169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
170 .associativity = 4, .line_size = 64, },
171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
172 .associativity = 4, .line_size = 64, },
173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
174 .associativity = 8, .line_size = 64, },
175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
176 .associativity = 8, .line_size = 64, },
177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
178 .associativity = 8, .line_size = 64, },
179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
180 .associativity = 12, .line_size = 64, },
181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
182 .associativity = 12, .line_size = 64, },
183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
184 .associativity = 12, .line_size = 64, },
185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
186 .associativity = 16, .line_size = 64, },
187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
188 .associativity = 16, .line_size = 64, },
189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
190 .associativity = 16, .line_size = 64, },
191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
192 .associativity = 24, .line_size = 64, },
193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
194 .associativity = 24, .line_size = 64, },
195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
196 .associativity = 24, .line_size = 64, },
197 };
198
199 /*
200 * "CPUID leaf 2 does not report cache descriptor information,
201 * use CPUID leaf 4 to query cache parameters"
202 */
203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
204
205 /*
206 * Return a CPUID 2 cache descriptor for a given cache.
207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
208 */
209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
210 {
211 int i;
212
213 assert(cache->size > 0);
214 assert(cache->level > 0);
215 assert(cache->line_size > 0);
216 assert(cache->associativity > 0);
217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
219 if (d->level == cache->level && d->type == cache->type &&
220 d->size == cache->size && d->line_size == cache->line_size &&
221 d->associativity == cache->associativity) {
222 return i;
223 }
224 }
225
226 return CACHE_DESCRIPTOR_UNAVAILABLE;
227 }
228
229 /* CPUID Leaf 4 constants: */
230
231 /* EAX: */
232 #define CACHE_TYPE_D 1
233 #define CACHE_TYPE_I 2
234 #define CACHE_TYPE_UNIFIED 3
235
236 #define CACHE_LEVEL(l) (l << 5)
237
238 #define CACHE_SELF_INIT_LEVEL (1 << 8)
239
240 /* EDX: */
241 #define CACHE_NO_INVD_SHARING (1 << 0)
242 #define CACHE_INCLUSIVE (1 << 1)
243 #define CACHE_COMPLEX_IDX (1 << 2)
244
245 /* Encode CacheType for CPUID[4].EAX */
246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
249 0 /* Invalid value */)
250
251
252 /* Encode cache info for CPUID[4] */
253 static void encode_cache_cpuid4(CPUCacheInfo *cache,
254 int num_apic_ids, int num_cores,
255 uint32_t *eax, uint32_t *ebx,
256 uint32_t *ecx, uint32_t *edx)
257 {
258 assert(cache->size == cache->line_size * cache->associativity *
259 cache->partitions * cache->sets);
260
261 assert(num_apic_ids > 0);
262 *eax = CACHE_TYPE(cache->type) |
263 CACHE_LEVEL(cache->level) |
264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
265 ((num_cores - 1) << 26) |
266 ((num_apic_ids - 1) << 14);
267
268 assert(cache->line_size > 0);
269 assert(cache->partitions > 0);
270 assert(cache->associativity > 0);
271 /* We don't implement fully-associative caches */
272 assert(cache->associativity < cache->sets);
273 *ebx = (cache->line_size - 1) |
274 ((cache->partitions - 1) << 12) |
275 ((cache->associativity - 1) << 22);
276
277 assert(cache->sets > 0);
278 *ecx = cache->sets - 1;
279
280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
281 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
283 }
284
285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
287 {
288 assert(cache->size % 1024 == 0);
289 assert(cache->lines_per_tag > 0);
290 assert(cache->associativity > 0);
291 assert(cache->line_size > 0);
292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
293 (cache->lines_per_tag << 8) | (cache->line_size);
294 }
295
296 #define ASSOC_FULL 0xFF
297
298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
300 a == 2 ? 0x2 : \
301 a == 4 ? 0x4 : \
302 a == 8 ? 0x6 : \
303 a == 16 ? 0x8 : \
304 a == 32 ? 0xA : \
305 a == 48 ? 0xB : \
306 a == 64 ? 0xC : \
307 a == 96 ? 0xD : \
308 a == 128 ? 0xE : \
309 a == ASSOC_FULL ? 0xF : \
310 0 /* invalid value */)
311
312 /*
313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
314 * @l3 can be NULL.
315 */
316 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
317 CPUCacheInfo *l3,
318 uint32_t *ecx, uint32_t *edx)
319 {
320 assert(l2->size % 1024 == 0);
321 assert(l2->associativity > 0);
322 assert(l2->lines_per_tag > 0);
323 assert(l2->line_size > 0);
324 *ecx = ((l2->size / 1024) << 16) |
325 (AMD_ENC_ASSOC(l2->associativity) << 12) |
326 (l2->lines_per_tag << 8) | (l2->line_size);
327
328 if (l3) {
329 assert(l3->size % (512 * 1024) == 0);
330 assert(l3->associativity > 0);
331 assert(l3->lines_per_tag > 0);
332 assert(l3->line_size > 0);
333 *edx = ((l3->size / (512 * 1024)) << 18) |
334 (AMD_ENC_ASSOC(l3->associativity) << 12) |
335 (l3->lines_per_tag << 8) | (l3->line_size);
336 } else {
337 *edx = 0;
338 }
339 }
340
341 /*
342 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
343 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
344 * Define the constants to build the cpu topology. Right now, TOPOEXT
345 * feature is enabled only on EPYC. So, these constants are based on
346 * EPYC supported configurations. We may need to handle the cases if
347 * these values change in future.
348 */
349 /* Maximum core complexes in a node */
350 #define MAX_CCX 2
351 /* Maximum cores in a core complex */
352 #define MAX_CORES_IN_CCX 4
353 /* Maximum cores in a node */
354 #define MAX_CORES_IN_NODE 8
355 /* Maximum nodes in a socket */
356 #define MAX_NODES_PER_SOCKET 4
357
358 /*
359 * Figure out the number of nodes required to build this config.
360 * Max cores in a node is 8
361 */
362 static int nodes_in_socket(int nr_cores)
363 {
364 int nodes;
365
366 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
367
368 /* Hardware does not support config with 3 nodes, return 4 in that case */
369 return (nodes == 3) ? 4 : nodes;
370 }
371
372 /*
373 * Decide the number of cores in a core complex with the given nr_cores using
374 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
375 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
376 * L3 cache is shared across all cores in a core complex. So, this will also
377 * tell us how many cores are sharing the L3 cache.
378 */
379 static int cores_in_core_complex(int nr_cores)
380 {
381 int nodes;
382
383 /* Check if we can fit all the cores in one core complex */
384 if (nr_cores <= MAX_CORES_IN_CCX) {
385 return nr_cores;
386 }
387 /* Get the number of nodes required to build this config */
388 nodes = nodes_in_socket(nr_cores);
389
390 /*
391 * Divide the cores accros all the core complexes
392 * Return rounded up value
393 */
394 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
395 }
396
397 /* Encode cache info for CPUID[8000001D] */
398 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
399 uint32_t *eax, uint32_t *ebx,
400 uint32_t *ecx, uint32_t *edx)
401 {
402 uint32_t l3_cores;
403 assert(cache->size == cache->line_size * cache->associativity *
404 cache->partitions * cache->sets);
405
406 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
407 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
408
409 /* L3 is shared among multiple cores */
410 if (cache->level == 3) {
411 l3_cores = cores_in_core_complex(cs->nr_cores);
412 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
413 } else {
414 *eax |= ((cs->nr_threads - 1) << 14);
415 }
416
417 assert(cache->line_size > 0);
418 assert(cache->partitions > 0);
419 assert(cache->associativity > 0);
420 /* We don't implement fully-associative caches */
421 assert(cache->associativity < cache->sets);
422 *ebx = (cache->line_size - 1) |
423 ((cache->partitions - 1) << 12) |
424 ((cache->associativity - 1) << 22);
425
426 assert(cache->sets > 0);
427 *ecx = cache->sets - 1;
428
429 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
430 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
431 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
432 }
433
434 /* Data structure to hold the configuration info for a given core index */
435 struct core_topology {
436 /* core complex id of the current core index */
437 int ccx_id;
438 /*
439 * Adjusted core index for this core in the topology
440 * This can be 0,1,2,3 with max 4 cores in a core complex
441 */
442 int core_id;
443 /* Node id for this core index */
444 int node_id;
445 /* Number of nodes in this config */
446 int num_nodes;
447 };
448
449 /*
450 * Build the configuration closely match the EPYC hardware. Using the EPYC
451 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
452 * right now. This could change in future.
453 * nr_cores : Total number of cores in the config
454 * core_id : Core index of the current CPU
455 * topo : Data structure to hold all the config info for this core index
456 */
457 static void build_core_topology(int nr_cores, int core_id,
458 struct core_topology *topo)
459 {
460 int nodes, cores_in_ccx;
461
462 /* First get the number of nodes required */
463 nodes = nodes_in_socket(nr_cores);
464
465 cores_in_ccx = cores_in_core_complex(nr_cores);
466
467 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
468 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
469 topo->core_id = core_id % cores_in_ccx;
470 topo->num_nodes = nodes;
471 }
472
473 /* Encode cache info for CPUID[8000001E] */
474 static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
475 uint32_t *eax, uint32_t *ebx,
476 uint32_t *ecx, uint32_t *edx)
477 {
478 struct core_topology topo = {0};
479 unsigned long nodes;
480 int shift;
481
482 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
483 *eax = cpu->apic_id;
484 /*
485 * CPUID_Fn8000001E_EBX
486 * 31:16 Reserved
487 * 15:8 Threads per core (The number of threads per core is
488 * Threads per core + 1)
489 * 7:0 Core id (see bit decoding below)
490 * SMT:
491 * 4:3 node id
492 * 2 Core complex id
493 * 1:0 Core id
494 * Non SMT:
495 * 5:4 node id
496 * 3 Core complex id
497 * 1:0 Core id
498 */
499 if (cs->nr_threads - 1) {
500 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
501 (topo.ccx_id << 2) | topo.core_id;
502 } else {
503 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
504 }
505 /*
506 * CPUID_Fn8000001E_ECX
507 * 31:11 Reserved
508 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
509 * 7:0 Node id (see bit decoding below)
510 * 2 Socket id
511 * 1:0 Node id
512 */
513 if (topo.num_nodes <= 4) {
514 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
515 topo.node_id;
516 } else {
517 /*
518 * Node id fix up. Actual hardware supports up to 4 nodes. But with
519 * more than 32 cores, we may end up with more than 4 nodes.
520 * Node id is a combination of socket id and node id. Only requirement
521 * here is that this number should be unique accross the system.
522 * Shift the socket id to accommodate more nodes. We dont expect both
523 * socket id and node id to be big number at the same time. This is not
524 * an ideal config but we need to to support it. Max nodes we can have
525 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
526 * 5 bits for nodes. Find the left most set bit to represent the total
527 * number of nodes. find_last_bit returns last set bit(0 based). Left
528 * shift(+1) the socket id to represent all the nodes.
529 */
530 nodes = topo.num_nodes - 1;
531 shift = find_last_bit(&nodes, 8);
532 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
533 topo.node_id;
534 }
535 *edx = 0;
536 }
537
538 /*
539 * Definitions of the hardcoded cache entries we expose:
540 * These are legacy cache values. If there is a need to change any
541 * of these values please use builtin_x86_defs
542 */
543
544 /* L1 data cache: */
545 static CPUCacheInfo legacy_l1d_cache = {
546 .type = DATA_CACHE,
547 .level = 1,
548 .size = 32 * KiB,
549 .self_init = 1,
550 .line_size = 64,
551 .associativity = 8,
552 .sets = 64,
553 .partitions = 1,
554 .no_invd_sharing = true,
555 };
556
557 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
558 static CPUCacheInfo legacy_l1d_cache_amd = {
559 .type = DATA_CACHE,
560 .level = 1,
561 .size = 64 * KiB,
562 .self_init = 1,
563 .line_size = 64,
564 .associativity = 2,
565 .sets = 512,
566 .partitions = 1,
567 .lines_per_tag = 1,
568 .no_invd_sharing = true,
569 };
570
571 /* L1 instruction cache: */
572 static CPUCacheInfo legacy_l1i_cache = {
573 .type = INSTRUCTION_CACHE,
574 .level = 1,
575 .size = 32 * KiB,
576 .self_init = 1,
577 .line_size = 64,
578 .associativity = 8,
579 .sets = 64,
580 .partitions = 1,
581 .no_invd_sharing = true,
582 };
583
584 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
585 static CPUCacheInfo legacy_l1i_cache_amd = {
586 .type = INSTRUCTION_CACHE,
587 .level = 1,
588 .size = 64 * KiB,
589 .self_init = 1,
590 .line_size = 64,
591 .associativity = 2,
592 .sets = 512,
593 .partitions = 1,
594 .lines_per_tag = 1,
595 .no_invd_sharing = true,
596 };
597
598 /* Level 2 unified cache: */
599 static CPUCacheInfo legacy_l2_cache = {
600 .type = UNIFIED_CACHE,
601 .level = 2,
602 .size = 4 * MiB,
603 .self_init = 1,
604 .line_size = 64,
605 .associativity = 16,
606 .sets = 4096,
607 .partitions = 1,
608 .no_invd_sharing = true,
609 };
610
611 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
612 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
613 .type = UNIFIED_CACHE,
614 .level = 2,
615 .size = 2 * MiB,
616 .line_size = 64,
617 .associativity = 8,
618 };
619
620
621 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
622 static CPUCacheInfo legacy_l2_cache_amd = {
623 .type = UNIFIED_CACHE,
624 .level = 2,
625 .size = 512 * KiB,
626 .line_size = 64,
627 .lines_per_tag = 1,
628 .associativity = 16,
629 .sets = 512,
630 .partitions = 1,
631 };
632
633 /* Level 3 unified cache: */
634 static CPUCacheInfo legacy_l3_cache = {
635 .type = UNIFIED_CACHE,
636 .level = 3,
637 .size = 16 * MiB,
638 .line_size = 64,
639 .associativity = 16,
640 .sets = 16384,
641 .partitions = 1,
642 .lines_per_tag = 1,
643 .self_init = true,
644 .inclusive = true,
645 .complex_indexing = true,
646 };
647
648 /* TLB definitions: */
649
650 #define L1_DTLB_2M_ASSOC 1
651 #define L1_DTLB_2M_ENTRIES 255
652 #define L1_DTLB_4K_ASSOC 1
653 #define L1_DTLB_4K_ENTRIES 255
654
655 #define L1_ITLB_2M_ASSOC 1
656 #define L1_ITLB_2M_ENTRIES 255
657 #define L1_ITLB_4K_ASSOC 1
658 #define L1_ITLB_4K_ENTRIES 255
659
660 #define L2_DTLB_2M_ASSOC 0 /* disabled */
661 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
662 #define L2_DTLB_4K_ASSOC 4
663 #define L2_DTLB_4K_ENTRIES 512
664
665 #define L2_ITLB_2M_ASSOC 0 /* disabled */
666 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
667 #define L2_ITLB_4K_ASSOC 4
668 #define L2_ITLB_4K_ENTRIES 512
669
670 /* CPUID Leaf 0x14 constants: */
671 #define INTEL_PT_MAX_SUBLEAF 0x1
672 /*
673 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
674 * MSR can be accessed;
675 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
676 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
677 * of Intel PT MSRs across warm reset;
678 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
679 */
680 #define INTEL_PT_MINIMAL_EBX 0xf
681 /*
682 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
683 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
684 * accessed;
685 * bit[01]: ToPA tables can hold any number of output entries, up to the
686 * maximum allowed by the MaskOrTableOffset field of
687 * IA32_RTIT_OUTPUT_MASK_PTRS;
688 * bit[02]: Support Single-Range Output scheme;
689 */
690 #define INTEL_PT_MINIMAL_ECX 0x7
691 /* generated packets which contain IP payloads have LIP values */
692 #define INTEL_PT_IP_LIP (1 << 31)
693 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
694 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
695 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
696 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
697 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
698
699 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
700 uint32_t vendor2, uint32_t vendor3)
701 {
702 int i;
703 for (i = 0; i < 4; i++) {
704 dst[i] = vendor1 >> (8 * i);
705 dst[i + 4] = vendor2 >> (8 * i);
706 dst[i + 8] = vendor3 >> (8 * i);
707 }
708 dst[CPUID_VENDOR_SZ] = '\0';
709 }
710
711 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
712 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
713 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
714 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
715 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
716 CPUID_PSE36 | CPUID_FXSR)
717 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
718 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
719 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
720 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
721 CPUID_PAE | CPUID_SEP | CPUID_APIC)
722
723 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
724 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
725 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
726 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
727 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
728 /* partly implemented:
729 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
730 /* missing:
731 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
732 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
733 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
734 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
735 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
736 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
737 CPUID_EXT_RDRAND)
738 /* missing:
739 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
740 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
741 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
742 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
743 CPUID_EXT_F16C */
744
745 #ifdef TARGET_X86_64
746 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
747 #else
748 #define TCG_EXT2_X86_64_FEATURES 0
749 #endif
750
751 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
752 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
753 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
754 TCG_EXT2_X86_64_FEATURES)
755 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
756 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
757 #define TCG_EXT4_FEATURES 0
758 #define TCG_SVM_FEATURES CPUID_SVM_NPT
759 #define TCG_KVM_FEATURES 0
760 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
761 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
762 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
763 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
764 CPUID_7_0_EBX_ERMS)
765 /* missing:
766 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
767 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
768 CPUID_7_0_EBX_RDSEED */
769 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
770 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
771 CPUID_7_0_ECX_LA57)
772 #define TCG_7_0_EDX_FEATURES 0
773 #define TCG_7_1_EAX_FEATURES 0
774 #define TCG_APM_FEATURES 0
775 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
776 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
777 /* missing:
778 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
779
780 typedef enum FeatureWordType {
781 CPUID_FEATURE_WORD,
782 MSR_FEATURE_WORD,
783 } FeatureWordType;
784
785 typedef struct FeatureWordInfo {
786 FeatureWordType type;
787 /* feature flags names are taken from "Intel Processor Identification and
788 * the CPUID Instruction" and AMD's "CPUID Specification".
789 * In cases of disagreement between feature naming conventions,
790 * aliases may be added.
791 */
792 const char *feat_names[64];
793 union {
794 /* If type==CPUID_FEATURE_WORD */
795 struct {
796 uint32_t eax; /* Input EAX for CPUID */
797 bool needs_ecx; /* CPUID instruction uses ECX as input */
798 uint32_t ecx; /* Input ECX value for CPUID */
799 int reg; /* output register (R_* constant) */
800 } cpuid;
801 /* If type==MSR_FEATURE_WORD */
802 struct {
803 uint32_t index;
804 } msr;
805 };
806 uint64_t tcg_features; /* Feature flags supported by TCG */
807 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */
808 uint64_t migratable_flags; /* Feature flags known to be migratable */
809 /* Features that shouldn't be auto-enabled by "-cpu host" */
810 uint64_t no_autoenable_flags;
811 } FeatureWordInfo;
812
813 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
814 [FEAT_1_EDX] = {
815 .type = CPUID_FEATURE_WORD,
816 .feat_names = {
817 "fpu", "vme", "de", "pse",
818 "tsc", "msr", "pae", "mce",
819 "cx8", "apic", NULL, "sep",
820 "mtrr", "pge", "mca", "cmov",
821 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
822 NULL, "ds" /* Intel dts */, "acpi", "mmx",
823 "fxsr", "sse", "sse2", "ss",
824 "ht" /* Intel htt */, "tm", "ia64", "pbe",
825 },
826 .cpuid = {.eax = 1, .reg = R_EDX, },
827 .tcg_features = TCG_FEATURES,
828 },
829 [FEAT_1_ECX] = {
830 .type = CPUID_FEATURE_WORD,
831 .feat_names = {
832 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
833 "ds-cpl", "vmx", "smx", "est",
834 "tm2", "ssse3", "cid", NULL,
835 "fma", "cx16", "xtpr", "pdcm",
836 NULL, "pcid", "dca", "sse4.1",
837 "sse4.2", "x2apic", "movbe", "popcnt",
838 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
839 "avx", "f16c", "rdrand", "hypervisor",
840 },
841 .cpuid = { .eax = 1, .reg = R_ECX, },
842 .tcg_features = TCG_EXT_FEATURES,
843 },
844 /* Feature names that are already defined on feature_name[] but
845 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
846 * names on feat_names below. They are copied automatically
847 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
848 */
849 [FEAT_8000_0001_EDX] = {
850 .type = CPUID_FEATURE_WORD,
851 .feat_names = {
852 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
853 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
854 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
855 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
856 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
857 "nx", NULL, "mmxext", NULL /* mmx */,
858 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
859 NULL, "lm", "3dnowext", "3dnow",
860 },
861 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
862 .tcg_features = TCG_EXT2_FEATURES,
863 },
864 [FEAT_8000_0001_ECX] = {
865 .type = CPUID_FEATURE_WORD,
866 .feat_names = {
867 "lahf-lm", "cmp-legacy", "svm", "extapic",
868 "cr8legacy", "abm", "sse4a", "misalignsse",
869 "3dnowprefetch", "osvw", "ibs", "xop",
870 "skinit", "wdt", NULL, "lwp",
871 "fma4", "tce", NULL, "nodeid-msr",
872 NULL, "tbm", "topoext", "perfctr-core",
873 "perfctr-nb", NULL, NULL, NULL,
874 NULL, NULL, NULL, NULL,
875 },
876 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
877 .tcg_features = TCG_EXT3_FEATURES,
878 /*
879 * TOPOEXT is always allowed but can't be enabled blindly by
880 * "-cpu host", as it requires consistent cache topology info
881 * to be provided so it doesn't confuse guests.
882 */
883 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
884 },
885 [FEAT_C000_0001_EDX] = {
886 .type = CPUID_FEATURE_WORD,
887 .feat_names = {
888 NULL, NULL, "xstore", "xstore-en",
889 NULL, NULL, "xcrypt", "xcrypt-en",
890 "ace2", "ace2-en", "phe", "phe-en",
891 "pmm", "pmm-en", NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 NULL, NULL, NULL, NULL,
896 },
897 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
898 .tcg_features = TCG_EXT4_FEATURES,
899 },
900 [FEAT_KVM] = {
901 .type = CPUID_FEATURE_WORD,
902 .feat_names = {
903 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
904 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
905 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
906 "kvm-poll-control", "kvm-pv-sched-yield", NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 NULL, NULL, NULL, NULL,
909 "kvmclock-stable-bit", NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
911 },
912 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
913 .tcg_features = TCG_KVM_FEATURES,
914 },
915 [FEAT_KVM_HINTS] = {
916 .type = CPUID_FEATURE_WORD,
917 .feat_names = {
918 "kvm-hint-dedicated", NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 NULL, NULL, NULL, NULL,
924 NULL, NULL, NULL, NULL,
925 NULL, NULL, NULL, NULL,
926 },
927 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
928 .tcg_features = TCG_KVM_FEATURES,
929 /*
930 * KVM hints aren't auto-enabled by -cpu host, they need to be
931 * explicitly enabled in the command-line.
932 */
933 .no_autoenable_flags = ~0U,
934 },
935 /*
936 * .feat_names are commented out for Hyper-V enlightenments because we
937 * don't want to have two different ways for enabling them on QEMU command
938 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
939 * enabling several feature bits simultaneously, exposing these bits
940 * individually may just confuse guests.
941 */
942 [FEAT_HYPERV_EAX] = {
943 .type = CPUID_FEATURE_WORD,
944 .feat_names = {
945 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
946 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
947 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
948 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
949 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
950 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
951 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
952 NULL, NULL,
953 NULL, NULL, NULL, NULL,
954 NULL, NULL, NULL, NULL,
955 NULL, NULL, NULL, NULL,
956 NULL, NULL, NULL, NULL,
957 },
958 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
959 },
960 [FEAT_HYPERV_EBX] = {
961 .type = CPUID_FEATURE_WORD,
962 .feat_names = {
963 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
964 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
965 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
966 NULL /* hv_create_port */, NULL /* hv_connect_port */,
967 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
968 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
969 NULL, NULL,
970 NULL, NULL, NULL, NULL,
971 NULL, NULL, NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 NULL, NULL, NULL, NULL,
974 },
975 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
976 },
977 [FEAT_HYPERV_EDX] = {
978 .type = CPUID_FEATURE_WORD,
979 .feat_names = {
980 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
981 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
982 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
983 NULL, NULL,
984 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
985 NULL, NULL, NULL, NULL,
986 NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL,
990 },
991 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
992 },
993 [FEAT_HV_RECOMM_EAX] = {
994 .type = CPUID_FEATURE_WORD,
995 .feat_names = {
996 NULL /* hv_recommend_pv_as_switch */,
997 NULL /* hv_recommend_pv_tlbflush_local */,
998 NULL /* hv_recommend_pv_tlbflush_remote */,
999 NULL /* hv_recommend_msr_apic_access */,
1000 NULL /* hv_recommend_msr_reset */,
1001 NULL /* hv_recommend_relaxed_timing */,
1002 NULL /* hv_recommend_dma_remapping */,
1003 NULL /* hv_recommend_int_remapping */,
1004 NULL /* hv_recommend_x2apic_msrs */,
1005 NULL /* hv_recommend_autoeoi_deprecation */,
1006 NULL /* hv_recommend_pv_ipi */,
1007 NULL /* hv_recommend_ex_hypercalls */,
1008 NULL /* hv_hypervisor_is_nested */,
1009 NULL /* hv_recommend_int_mbec */,
1010 NULL /* hv_recommend_evmcs */,
1011 NULL,
1012 NULL, NULL, NULL, NULL,
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 NULL, NULL, NULL, NULL,
1016 },
1017 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1018 },
1019 [FEAT_HV_NESTED_EAX] = {
1020 .type = CPUID_FEATURE_WORD,
1021 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1022 },
1023 [FEAT_SVM] = {
1024 .type = CPUID_FEATURE_WORD,
1025 .feat_names = {
1026 "npt", "lbrv", "svm-lock", "nrip-save",
1027 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1028 NULL, NULL, "pause-filter", NULL,
1029 "pfthreshold", NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL,
1032 NULL, NULL, NULL, NULL,
1033 NULL, NULL, NULL, NULL,
1034 },
1035 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
1036 .tcg_features = TCG_SVM_FEATURES,
1037 },
1038 [FEAT_7_0_EBX] = {
1039 .type = CPUID_FEATURE_WORD,
1040 .feat_names = {
1041 "fsgsbase", "tsc-adjust", NULL, "bmi1",
1042 "hle", "avx2", NULL, "smep",
1043 "bmi2", "erms", "invpcid", "rtm",
1044 NULL, NULL, "mpx", NULL,
1045 "avx512f", "avx512dq", "rdseed", "adx",
1046 "smap", "avx512ifma", "pcommit", "clflushopt",
1047 "clwb", "intel-pt", "avx512pf", "avx512er",
1048 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1049 },
1050 .cpuid = {
1051 .eax = 7,
1052 .needs_ecx = true, .ecx = 0,
1053 .reg = R_EBX,
1054 },
1055 .tcg_features = TCG_7_0_EBX_FEATURES,
1056 },
1057 [FEAT_7_0_ECX] = {
1058 .type = CPUID_FEATURE_WORD,
1059 .feat_names = {
1060 NULL, "avx512vbmi", "umip", "pku",
1061 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
1062 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1063 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
1064 "la57", NULL, NULL, NULL,
1065 NULL, NULL, "rdpid", NULL,
1066 NULL, "cldemote", NULL, "movdiri",
1067 "movdir64b", NULL, NULL, NULL,
1068 },
1069 .cpuid = {
1070 .eax = 7,
1071 .needs_ecx = true, .ecx = 0,
1072 .reg = R_ECX,
1073 },
1074 .tcg_features = TCG_7_0_ECX_FEATURES,
1075 },
1076 [FEAT_7_0_EDX] = {
1077 .type = CPUID_FEATURE_WORD,
1078 .feat_names = {
1079 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1080 NULL, NULL, NULL, NULL,
1081 NULL, NULL, "md-clear", NULL,
1082 NULL, NULL, NULL, NULL,
1083 NULL, NULL, NULL /* pconfig */, NULL,
1084 NULL, NULL, NULL, NULL,
1085 NULL, NULL, "spec-ctrl", "stibp",
1086 NULL, "arch-capabilities", "core-capability", "ssbd",
1087 },
1088 .cpuid = {
1089 .eax = 7,
1090 .needs_ecx = true, .ecx = 0,
1091 .reg = R_EDX,
1092 },
1093 .tcg_features = TCG_7_0_EDX_FEATURES,
1094 },
1095 [FEAT_7_1_EAX] = {
1096 .type = CPUID_FEATURE_WORD,
1097 .feat_names = {
1098 NULL, NULL, NULL, NULL,
1099 NULL, "avx512-bf16", NULL, NULL,
1100 NULL, NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL,
1102 NULL, NULL, NULL, NULL,
1103 NULL, NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1106 },
1107 .cpuid = {
1108 .eax = 7,
1109 .needs_ecx = true, .ecx = 1,
1110 .reg = R_EAX,
1111 },
1112 .tcg_features = TCG_7_1_EAX_FEATURES,
1113 },
1114 [FEAT_8000_0007_EDX] = {
1115 .type = CPUID_FEATURE_WORD,
1116 .feat_names = {
1117 NULL, NULL, NULL, NULL,
1118 NULL, NULL, NULL, NULL,
1119 "invtsc", NULL, NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
1122 NULL, NULL, NULL, NULL,
1123 NULL, NULL, NULL, NULL,
1124 NULL, NULL, NULL, NULL,
1125 },
1126 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1127 .tcg_features = TCG_APM_FEATURES,
1128 .unmigratable_flags = CPUID_APM_INVTSC,
1129 },
1130 [FEAT_8000_0008_EBX] = {
1131 .type = CPUID_FEATURE_WORD,
1132 .feat_names = {
1133 "clzero", NULL, "xsaveerptr", NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, "wbnoinvd", NULL, NULL,
1136 "ibpb", NULL, NULL, NULL,
1137 NULL, NULL, NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1140 NULL, NULL, NULL, NULL,
1141 },
1142 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1143 .tcg_features = 0,
1144 .unmigratable_flags = 0,
1145 },
1146 [FEAT_XSAVE] = {
1147 .type = CPUID_FEATURE_WORD,
1148 .feat_names = {
1149 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 NULL, NULL, NULL, NULL,
1157 },
1158 .cpuid = {
1159 .eax = 0xd,
1160 .needs_ecx = true, .ecx = 1,
1161 .reg = R_EAX,
1162 },
1163 .tcg_features = TCG_XSAVE_FEATURES,
1164 },
1165 [FEAT_6_EAX] = {
1166 .type = CPUID_FEATURE_WORD,
1167 .feat_names = {
1168 NULL, NULL, "arat", NULL,
1169 NULL, NULL, NULL, NULL,
1170 NULL, NULL, NULL, NULL,
1171 NULL, NULL, NULL, NULL,
1172 NULL, NULL, NULL, NULL,
1173 NULL, NULL, NULL, NULL,
1174 NULL, NULL, NULL, NULL,
1175 NULL, NULL, NULL, NULL,
1176 },
1177 .cpuid = { .eax = 6, .reg = R_EAX, },
1178 .tcg_features = TCG_6_EAX_FEATURES,
1179 },
1180 [FEAT_XSAVE_COMP_LO] = {
1181 .type = CPUID_FEATURE_WORD,
1182 .cpuid = {
1183 .eax = 0xD,
1184 .needs_ecx = true, .ecx = 0,
1185 .reg = R_EAX,
1186 },
1187 .tcg_features = ~0U,
1188 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1189 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1190 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1191 XSTATE_PKRU_MASK,
1192 },
1193 [FEAT_XSAVE_COMP_HI] = {
1194 .type = CPUID_FEATURE_WORD,
1195 .cpuid = {
1196 .eax = 0xD,
1197 .needs_ecx = true, .ecx = 0,
1198 .reg = R_EDX,
1199 },
1200 .tcg_features = ~0U,
1201 },
1202 /*Below are MSR exposed features*/
1203 [FEAT_ARCH_CAPABILITIES] = {
1204 .type = MSR_FEATURE_WORD,
1205 .feat_names = {
1206 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1207 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1208 "taa-no", NULL, NULL, NULL,
1209 NULL, NULL, NULL, NULL,
1210 NULL, NULL, NULL, NULL,
1211 NULL, NULL, NULL, NULL,
1212 NULL, NULL, NULL, NULL,
1213 NULL, NULL, NULL, NULL,
1214 },
1215 .msr = {
1216 .index = MSR_IA32_ARCH_CAPABILITIES,
1217 },
1218 },
1219 [FEAT_CORE_CAPABILITY] = {
1220 .type = MSR_FEATURE_WORD,
1221 .feat_names = {
1222 NULL, NULL, NULL, NULL,
1223 NULL, "split-lock-detect", NULL, NULL,
1224 NULL, NULL, NULL, NULL,
1225 NULL, NULL, NULL, NULL,
1226 NULL, NULL, NULL, NULL,
1227 NULL, NULL, NULL, NULL,
1228 NULL, NULL, NULL, NULL,
1229 NULL, NULL, NULL, NULL,
1230 },
1231 .msr = {
1232 .index = MSR_IA32_CORE_CAPABILITY,
1233 },
1234 },
1235
1236 [FEAT_VMX_PROCBASED_CTLS] = {
1237 .type = MSR_FEATURE_WORD,
1238 .feat_names = {
1239 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1240 NULL, NULL, NULL, "vmx-hlt-exit",
1241 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1242 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1243 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1244 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1245 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1246 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1247 },
1248 .msr = {
1249 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1250 }
1251 },
1252
1253 [FEAT_VMX_SECONDARY_CTLS] = {
1254 .type = MSR_FEATURE_WORD,
1255 .feat_names = {
1256 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1257 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1258 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1259 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1260 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1261 "vmx-xsaves", NULL, NULL, NULL,
1262 NULL, NULL, NULL, NULL,
1263 NULL, NULL, NULL, NULL,
1264 },
1265 .msr = {
1266 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1267 }
1268 },
1269
1270 [FEAT_VMX_PINBASED_CTLS] = {
1271 .type = MSR_FEATURE_WORD,
1272 .feat_names = {
1273 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1274 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1275 NULL, NULL, NULL, NULL,
1276 NULL, NULL, NULL, NULL,
1277 NULL, NULL, NULL, NULL,
1278 NULL, NULL, NULL, NULL,
1279 NULL, NULL, NULL, NULL,
1280 NULL, NULL, NULL, NULL,
1281 },
1282 .msr = {
1283 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1284 }
1285 },
1286
1287 [FEAT_VMX_EXIT_CTLS] = {
1288 .type = MSR_FEATURE_WORD,
1289 /*
1290 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1291 * the LM CPUID bit.
1292 */
1293 .feat_names = {
1294 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1295 NULL, NULL, NULL, NULL,
1296 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1297 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1298 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1299 "vmx-exit-save-efer", "vmx-exit-load-efer",
1300 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1301 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1302 NULL, NULL, NULL, NULL,
1303 },
1304 .msr = {
1305 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1306 }
1307 },
1308
1309 [FEAT_VMX_ENTRY_CTLS] = {
1310 .type = MSR_FEATURE_WORD,
1311 .feat_names = {
1312 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1313 NULL, NULL, NULL, NULL,
1314 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1315 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1316 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1317 NULL, NULL, NULL, NULL,
1318 NULL, NULL, NULL, NULL,
1319 NULL, NULL, NULL, NULL,
1320 },
1321 .msr = {
1322 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1323 }
1324 },
1325
1326 [FEAT_VMX_MISC] = {
1327 .type = MSR_FEATURE_WORD,
1328 .feat_names = {
1329 NULL, NULL, NULL, NULL,
1330 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1331 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1332 NULL, NULL, NULL, NULL,
1333 NULL, NULL, NULL, NULL,
1334 NULL, NULL, NULL, NULL,
1335 NULL, NULL, NULL, NULL,
1336 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1337 },
1338 .msr = {
1339 .index = MSR_IA32_VMX_MISC,
1340 }
1341 },
1342
1343 [FEAT_VMX_EPT_VPID_CAPS] = {
1344 .type = MSR_FEATURE_WORD,
1345 .feat_names = {
1346 "vmx-ept-execonly", NULL, NULL, NULL,
1347 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1348 NULL, NULL, NULL, NULL,
1349 NULL, NULL, NULL, NULL,
1350 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1351 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1352 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1353 NULL, NULL, NULL, NULL,
1354 "vmx-invvpid", NULL, NULL, NULL,
1355 NULL, NULL, NULL, NULL,
1356 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1357 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1358 NULL, NULL, NULL, NULL,
1359 NULL, NULL, NULL, NULL,
1360 NULL, NULL, NULL, NULL,
1361 NULL, NULL, NULL, NULL,
1362 NULL, NULL, NULL, NULL,
1363 },
1364 .msr = {
1365 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1366 }
1367 },
1368
1369 [FEAT_VMX_BASIC] = {
1370 .type = MSR_FEATURE_WORD,
1371 .feat_names = {
1372 [54] = "vmx-ins-outs",
1373 [55] = "vmx-true-ctls",
1374 },
1375 .msr = {
1376 .index = MSR_IA32_VMX_BASIC,
1377 },
1378 /* Just to be safe - we don't support setting the MSEG version field. */
1379 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1380 },
1381
1382 [FEAT_VMX_VMFUNC] = {
1383 .type = MSR_FEATURE_WORD,
1384 .feat_names = {
1385 [0] = "vmx-eptp-switching",
1386 },
1387 .msr = {
1388 .index = MSR_IA32_VMX_VMFUNC,
1389 }
1390 },
1391
1392 };
1393
1394 typedef struct FeatureMask {
1395 FeatureWord index;
1396 uint64_t mask;
1397 } FeatureMask;
1398
1399 typedef struct FeatureDep {
1400 FeatureMask from, to;
1401 } FeatureDep;
1402
1403 static FeatureDep feature_dependencies[] = {
1404 {
1405 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
1406 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
1407 },
1408 {
1409 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
1410 .to = { FEAT_CORE_CAPABILITY, ~0ull },
1411 },
1412 {
1413 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1414 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1415 },
1416 {
1417 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1418 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1419 },
1420 {
1421 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1422 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1423 },
1424 {
1425 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1426 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1427 },
1428 {
1429 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1430 .to = { FEAT_VMX_MISC, ~0ull },
1431 },
1432 {
1433 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1434 .to = { FEAT_VMX_BASIC, ~0ull },
1435 },
1436 {
1437 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1438 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1439 },
1440 {
1441 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1442 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1443 },
1444 {
1445 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1446 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1447 },
1448 {
1449 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1450 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1451 },
1452 {
1453 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1454 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1455 },
1456 {
1457 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1458 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1459 },
1460 {
1461 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1462 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1463 },
1464 {
1465 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1466 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1467 },
1468 {
1469 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1470 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1471 },
1472 {
1473 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1474 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1475 },
1476 {
1477 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1478 .to = { FEAT_VMX_VMFUNC, ~0ull },
1479 },
1480 };
1481
1482 typedef struct X86RegisterInfo32 {
1483 /* Name of register */
1484 const char *name;
1485 /* QAPI enum value register */
1486 X86CPURegister32 qapi_enum;
1487 } X86RegisterInfo32;
1488
1489 #define REGISTER(reg) \
1490 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1491 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1492 REGISTER(EAX),
1493 REGISTER(ECX),
1494 REGISTER(EDX),
1495 REGISTER(EBX),
1496 REGISTER(ESP),
1497 REGISTER(EBP),
1498 REGISTER(ESI),
1499 REGISTER(EDI),
1500 };
1501 #undef REGISTER
1502
1503 typedef struct ExtSaveArea {
1504 uint32_t feature, bits;
1505 uint32_t offset, size;
1506 } ExtSaveArea;
1507
1508 static const ExtSaveArea x86_ext_save_areas[] = {
1509 [XSTATE_FP_BIT] = {
1510 /* x87 FP state component is always enabled if XSAVE is supported */
1511 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1512 /* x87 state is in the legacy region of the XSAVE area */
1513 .offset = 0,
1514 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1515 },
1516 [XSTATE_SSE_BIT] = {
1517 /* SSE state component is always enabled if XSAVE is supported */
1518 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1519 /* SSE state is in the legacy region of the XSAVE area */
1520 .offset = 0,
1521 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1522 },
1523 [XSTATE_YMM_BIT] =
1524 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1525 .offset = offsetof(X86XSaveArea, avx_state),
1526 .size = sizeof(XSaveAVX) },
1527 [XSTATE_BNDREGS_BIT] =
1528 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1529 .offset = offsetof(X86XSaveArea, bndreg_state),
1530 .size = sizeof(XSaveBNDREG) },
1531 [XSTATE_BNDCSR_BIT] =
1532 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1533 .offset = offsetof(X86XSaveArea, bndcsr_state),
1534 .size = sizeof(XSaveBNDCSR) },
1535 [XSTATE_OPMASK_BIT] =
1536 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1537 .offset = offsetof(X86XSaveArea, opmask_state),
1538 .size = sizeof(XSaveOpmask) },
1539 [XSTATE_ZMM_Hi256_BIT] =
1540 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1541 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1542 .size = sizeof(XSaveZMM_Hi256) },
1543 [XSTATE_Hi16_ZMM_BIT] =
1544 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1545 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1546 .size = sizeof(XSaveHi16_ZMM) },
1547 [XSTATE_PKRU_BIT] =
1548 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1549 .offset = offsetof(X86XSaveArea, pkru_state),
1550 .size = sizeof(XSavePKRU) },
1551 };
1552
1553 static uint32_t xsave_area_size(uint64_t mask)
1554 {
1555 int i;
1556 uint64_t ret = 0;
1557
1558 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1559 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1560 if ((mask >> i) & 1) {
1561 ret = MAX(ret, esa->offset + esa->size);
1562 }
1563 }
1564 return ret;
1565 }
1566
1567 static inline bool accel_uses_host_cpuid(void)
1568 {
1569 return kvm_enabled() || hvf_enabled();
1570 }
1571
1572 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1573 {
1574 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1575 cpu->env.features[FEAT_XSAVE_COMP_LO];
1576 }
1577
1578 const char *get_register_name_32(unsigned int reg)
1579 {
1580 if (reg >= CPU_NB_REGS32) {
1581 return NULL;
1582 }
1583 return x86_reg_info_32[reg].name;
1584 }
1585
1586 /*
1587 * Returns the set of feature flags that are supported and migratable by
1588 * QEMU, for a given FeatureWord.
1589 */
1590 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
1591 {
1592 FeatureWordInfo *wi = &feature_word_info[w];
1593 uint64_t r = 0;
1594 int i;
1595
1596 for (i = 0; i < 64; i++) {
1597 uint64_t f = 1ULL << i;
1598
1599 /* If the feature name is known, it is implicitly considered migratable,
1600 * unless it is explicitly set in unmigratable_flags */
1601 if ((wi->migratable_flags & f) ||
1602 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1603 r |= f;
1604 }
1605 }
1606 return r;
1607 }
1608
1609 void host_cpuid(uint32_t function, uint32_t count,
1610 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1611 {
1612 uint32_t vec[4];
1613
1614 #ifdef __x86_64__
1615 asm volatile("cpuid"
1616 : "=a"(vec[0]), "=b"(vec[1]),
1617 "=c"(vec[2]), "=d"(vec[3])
1618 : "0"(function), "c"(count) : "cc");
1619 #elif defined(__i386__)
1620 asm volatile("pusha \n\t"
1621 "cpuid \n\t"
1622 "mov %%eax, 0(%2) \n\t"
1623 "mov %%ebx, 4(%2) \n\t"
1624 "mov %%ecx, 8(%2) \n\t"
1625 "mov %%edx, 12(%2) \n\t"
1626 "popa"
1627 : : "a"(function), "c"(count), "S"(vec)
1628 : "memory", "cc");
1629 #else
1630 abort();
1631 #endif
1632
1633 if (eax)
1634 *eax = vec[0];
1635 if (ebx)
1636 *ebx = vec[1];
1637 if (ecx)
1638 *ecx = vec[2];
1639 if (edx)
1640 *edx = vec[3];
1641 }
1642
1643 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1644 {
1645 uint32_t eax, ebx, ecx, edx;
1646
1647 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1648 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1649
1650 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1651 if (family) {
1652 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1653 }
1654 if (model) {
1655 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1656 }
1657 if (stepping) {
1658 *stepping = eax & 0x0F;
1659 }
1660 }
1661
1662 /* CPU class name definitions: */
1663
1664 /* Return type name for a given CPU model name
1665 * Caller is responsible for freeing the returned string.
1666 */
1667 static char *x86_cpu_type_name(const char *model_name)
1668 {
1669 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1670 }
1671
1672 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1673 {
1674 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1675 return object_class_by_name(typename);
1676 }
1677
1678 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1679 {
1680 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1681 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1682 return g_strndup(class_name,
1683 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1684 }
1685
1686 typedef struct PropValue {
1687 const char *prop, *value;
1688 } PropValue;
1689
1690 typedef struct X86CPUVersionDefinition {
1691 X86CPUVersion version;
1692 const char *alias;
1693 const char *note;
1694 PropValue *props;
1695 } X86CPUVersionDefinition;
1696
1697 /* Base definition for a CPU model */
1698 typedef struct X86CPUDefinition {
1699 const char *name;
1700 uint32_t level;
1701 uint32_t xlevel;
1702 /* vendor is zero-terminated, 12 character ASCII string */
1703 char vendor[CPUID_VENDOR_SZ + 1];
1704 int family;
1705 int model;
1706 int stepping;
1707 FeatureWordArray features;
1708 const char *model_id;
1709 CPUCaches *cache_info;
1710 /*
1711 * Definitions for alternative versions of CPU model.
1712 * List is terminated by item with version == 0.
1713 * If NULL, version 1 will be registered automatically.
1714 */
1715 const X86CPUVersionDefinition *versions;
1716 } X86CPUDefinition;
1717
1718 /* Reference to a specific CPU model version */
1719 struct X86CPUModel {
1720 /* Base CPU definition */
1721 X86CPUDefinition *cpudef;
1722 /* CPU model version */
1723 X86CPUVersion version;
1724 const char *note;
1725 /*
1726 * If true, this is an alias CPU model.
1727 * This matters only for "-cpu help" and query-cpu-definitions
1728 */
1729 bool is_alias;
1730 };
1731
1732 /* Get full model name for CPU version */
1733 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1734 X86CPUVersion version)
1735 {
1736 assert(version > 0);
1737 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1738 }
1739
1740 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1741 {
1742 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1743 static const X86CPUVersionDefinition default_version_list[] = {
1744 { 1 },
1745 { /* end of list */ }
1746 };
1747
1748 return def->versions ?: default_version_list;
1749 }
1750
1751 static CPUCaches epyc_cache_info = {
1752 .l1d_cache = &(CPUCacheInfo) {
1753 .type = DATA_CACHE,
1754 .level = 1,
1755 .size = 32 * KiB,
1756 .line_size = 64,
1757 .associativity = 8,
1758 .partitions = 1,
1759 .sets = 64,
1760 .lines_per_tag = 1,
1761 .self_init = 1,
1762 .no_invd_sharing = true,
1763 },
1764 .l1i_cache = &(CPUCacheInfo) {
1765 .type = INSTRUCTION_CACHE,
1766 .level = 1,
1767 .size = 64 * KiB,
1768 .line_size = 64,
1769 .associativity = 4,
1770 .partitions = 1,
1771 .sets = 256,
1772 .lines_per_tag = 1,
1773 .self_init = 1,
1774 .no_invd_sharing = true,
1775 },
1776 .l2_cache = &(CPUCacheInfo) {
1777 .type = UNIFIED_CACHE,
1778 .level = 2,
1779 .size = 512 * KiB,
1780 .line_size = 64,
1781 .associativity = 8,
1782 .partitions = 1,
1783 .sets = 1024,
1784 .lines_per_tag = 1,
1785 },
1786 .l3_cache = &(CPUCacheInfo) {
1787 .type = UNIFIED_CACHE,
1788 .level = 3,
1789 .size = 8 * MiB,
1790 .line_size = 64,
1791 .associativity = 16,
1792 .partitions = 1,
1793 .sets = 8192,
1794 .lines_per_tag = 1,
1795 .self_init = true,
1796 .inclusive = true,
1797 .complex_indexing = true,
1798 },
1799 };
1800
1801 /* The following VMX features are not supported by KVM and are left out in the
1802 * CPU definitions:
1803 *
1804 * Dual-monitor support (all processors)
1805 * Entry to SMM
1806 * Deactivate dual-monitor treatment
1807 * Number of CR3-target values
1808 * Shutdown activity state
1809 * Wait-for-SIPI activity state
1810 * PAUSE-loop exiting (Westmere and newer)
1811 * EPT-violation #VE (Broadwell and newer)
1812 * Inject event with insn length=0 (Skylake and newer)
1813 * Conceal non-root operation from PT
1814 * Conceal VM exits from PT
1815 * Conceal VM entries from PT
1816 * Enable ENCLS exiting
1817 * Mode-based execute control (XS/XU)
1818 s TSC scaling (Skylake Server and newer)
1819 * GPA translation for PT (IceLake and newer)
1820 * User wait and pause
1821 * ENCLV exiting
1822 * Load IA32_RTIT_CTL
1823 * Clear IA32_RTIT_CTL
1824 * Advanced VM-exit information for EPT violations
1825 * Sub-page write permissions
1826 * PT in VMX operation
1827 */
1828
1829 static X86CPUDefinition builtin_x86_defs[] = {
1830 {
1831 .name = "qemu64",
1832 .level = 0xd,
1833 .vendor = CPUID_VENDOR_AMD,
1834 .family = 6,
1835 .model = 6,
1836 .stepping = 3,
1837 .features[FEAT_1_EDX] =
1838 PPRO_FEATURES |
1839 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1840 CPUID_PSE36,
1841 .features[FEAT_1_ECX] =
1842 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1843 .features[FEAT_8000_0001_EDX] =
1844 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1845 .features[FEAT_8000_0001_ECX] =
1846 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1847 .xlevel = 0x8000000A,
1848 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1849 },
1850 {
1851 .name = "phenom",
1852 .level = 5,
1853 .vendor = CPUID_VENDOR_AMD,
1854 .family = 16,
1855 .model = 2,
1856 .stepping = 3,
1857 /* Missing: CPUID_HT */
1858 .features[FEAT_1_EDX] =
1859 PPRO_FEATURES |
1860 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1861 CPUID_PSE36 | CPUID_VME,
1862 .features[FEAT_1_ECX] =
1863 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1864 CPUID_EXT_POPCNT,
1865 .features[FEAT_8000_0001_EDX] =
1866 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1867 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1868 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1869 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1870 CPUID_EXT3_CR8LEG,
1871 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1872 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1873 .features[FEAT_8000_0001_ECX] =
1874 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1875 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1876 /* Missing: CPUID_SVM_LBRV */
1877 .features[FEAT_SVM] =
1878 CPUID_SVM_NPT,
1879 .xlevel = 0x8000001A,
1880 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1881 },
1882 {
1883 .name = "core2duo",
1884 .level = 10,
1885 .vendor = CPUID_VENDOR_INTEL,
1886 .family = 6,
1887 .model = 15,
1888 .stepping = 11,
1889 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1890 .features[FEAT_1_EDX] =
1891 PPRO_FEATURES |
1892 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1893 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1894 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1895 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1896 .features[FEAT_1_ECX] =
1897 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1898 CPUID_EXT_CX16,
1899 .features[FEAT_8000_0001_EDX] =
1900 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1901 .features[FEAT_8000_0001_ECX] =
1902 CPUID_EXT3_LAHF_LM,
1903 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1904 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1905 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1906 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1907 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1908 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1909 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1910 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1911 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1912 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1913 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1914 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1915 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1916 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1917 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1918 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1919 .features[FEAT_VMX_SECONDARY_CTLS] =
1920 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
1921 .xlevel = 0x80000008,
1922 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1923 },
1924 {
1925 .name = "kvm64",
1926 .level = 0xd,
1927 .vendor = CPUID_VENDOR_INTEL,
1928 .family = 15,
1929 .model = 6,
1930 .stepping = 1,
1931 /* Missing: CPUID_HT */
1932 .features[FEAT_1_EDX] =
1933 PPRO_FEATURES | CPUID_VME |
1934 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1935 CPUID_PSE36,
1936 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1937 .features[FEAT_1_ECX] =
1938 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1939 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1940 .features[FEAT_8000_0001_EDX] =
1941 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1942 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1943 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1944 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1945 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1946 .features[FEAT_8000_0001_ECX] =
1947 0,
1948 /* VMX features from Cedar Mill/Prescott */
1949 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1950 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1951 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1952 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1953 VMX_PIN_BASED_NMI_EXITING,
1954 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1955 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1956 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1957 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1958 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1959 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1960 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1961 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
1962 .xlevel = 0x80000008,
1963 .model_id = "Common KVM processor"
1964 },
1965 {
1966 .name = "qemu32",
1967 .level = 4,
1968 .vendor = CPUID_VENDOR_INTEL,
1969 .family = 6,
1970 .model = 6,
1971 .stepping = 3,
1972 .features[FEAT_1_EDX] =
1973 PPRO_FEATURES,
1974 .features[FEAT_1_ECX] =
1975 CPUID_EXT_SSE3,
1976 .xlevel = 0x80000004,
1977 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1978 },
1979 {
1980 .name = "kvm32",
1981 .level = 5,
1982 .vendor = CPUID_VENDOR_INTEL,
1983 .family = 15,
1984 .model = 6,
1985 .stepping = 1,
1986 .features[FEAT_1_EDX] =
1987 PPRO_FEATURES | CPUID_VME |
1988 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1989 .features[FEAT_1_ECX] =
1990 CPUID_EXT_SSE3,
1991 .features[FEAT_8000_0001_ECX] =
1992 0,
1993 /* VMX features from Yonah */
1994 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1995 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1996 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1997 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1998 VMX_PIN_BASED_NMI_EXITING,
1999 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2000 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2001 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2002 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2003 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2004 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2005 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2006 .xlevel = 0x80000008,
2007 .model_id = "Common 32-bit KVM processor"
2008 },
2009 {
2010 .name = "coreduo",
2011 .level = 10,
2012 .vendor = CPUID_VENDOR_INTEL,
2013 .family = 6,
2014 .model = 14,
2015 .stepping = 8,
2016 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2017 .features[FEAT_1_EDX] =
2018 PPRO_FEATURES | CPUID_VME |
2019 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
2020 CPUID_SS,
2021 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
2022 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
2023 .features[FEAT_1_ECX] =
2024 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
2025 .features[FEAT_8000_0001_EDX] =
2026 CPUID_EXT2_NX,
2027 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2028 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2029 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2030 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2031 VMX_PIN_BASED_NMI_EXITING,
2032 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2033 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2034 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2035 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2036 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2037 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2038 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2039 .xlevel = 0x80000008,
2040 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2041 },
2042 {
2043 .name = "486",
2044 .level = 1,
2045 .vendor = CPUID_VENDOR_INTEL,
2046 .family = 4,
2047 .model = 8,
2048 .stepping = 0,
2049 .features[FEAT_1_EDX] =
2050 I486_FEATURES,
2051 .xlevel = 0,
2052 .model_id = "",
2053 },
2054 {
2055 .name = "pentium",
2056 .level = 1,
2057 .vendor = CPUID_VENDOR_INTEL,
2058 .family = 5,
2059 .model = 4,
2060 .stepping = 3,
2061 .features[FEAT_1_EDX] =
2062 PENTIUM_FEATURES,
2063 .xlevel = 0,
2064 .model_id = "",
2065 },
2066 {
2067 .name = "pentium2",
2068 .level = 2,
2069 .vendor = CPUID_VENDOR_INTEL,
2070 .family = 6,
2071 .model = 5,
2072 .stepping = 2,
2073 .features[FEAT_1_EDX] =
2074 PENTIUM2_FEATURES,
2075 .xlevel = 0,
2076 .model_id = "",
2077 },
2078 {
2079 .name = "pentium3",
2080 .level = 3,
2081 .vendor = CPUID_VENDOR_INTEL,
2082 .family = 6,
2083 .model = 7,
2084 .stepping = 3,
2085 .features[FEAT_1_EDX] =
2086 PENTIUM3_FEATURES,
2087 .xlevel = 0,
2088 .model_id = "",
2089 },
2090 {
2091 .name = "athlon",
2092 .level = 2,
2093 .vendor = CPUID_VENDOR_AMD,
2094 .family = 6,
2095 .model = 2,
2096 .stepping = 3,
2097 .features[FEAT_1_EDX] =
2098 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
2099 CPUID_MCA,
2100 .features[FEAT_8000_0001_EDX] =
2101 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
2102 .xlevel = 0x80000008,
2103 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
2104 },
2105 {
2106 .name = "n270",
2107 .level = 10,
2108 .vendor = CPUID_VENDOR_INTEL,
2109 .family = 6,
2110 .model = 28,
2111 .stepping = 2,
2112 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2113 .features[FEAT_1_EDX] =
2114 PPRO_FEATURES |
2115 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2116 CPUID_ACPI | CPUID_SS,
2117 /* Some CPUs got no CPUID_SEP */
2118 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2119 * CPUID_EXT_XTPR */
2120 .features[FEAT_1_ECX] =
2121 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
2122 CPUID_EXT_MOVBE,
2123 .features[FEAT_8000_0001_EDX] =
2124 CPUID_EXT2_NX,
2125 .features[FEAT_8000_0001_ECX] =
2126 CPUID_EXT3_LAHF_LM,
2127 .xlevel = 0x80000008,
2128 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2129 },
2130 {
2131 .name = "Conroe",
2132 .level = 10,
2133 .vendor = CPUID_VENDOR_INTEL,
2134 .family = 6,
2135 .model = 15,
2136 .stepping = 3,
2137 .features[FEAT_1_EDX] =
2138 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2139 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2140 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2141 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2142 CPUID_DE | CPUID_FP87,
2143 .features[FEAT_1_ECX] =
2144 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2145 .features[FEAT_8000_0001_EDX] =
2146 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2147 .features[FEAT_8000_0001_ECX] =
2148 CPUID_EXT3_LAHF_LM,
2149 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2150 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2151 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2152 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2153 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2154 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2155 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2156 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2157 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2158 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2159 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2160 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2161 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2162 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2163 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2164 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2165 .features[FEAT_VMX_SECONDARY_CTLS] =
2166 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
2167 .xlevel = 0x80000008,
2168 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2169 },
2170 {
2171 .name = "Penryn",
2172 .level = 10,
2173 .vendor = CPUID_VENDOR_INTEL,
2174 .family = 6,
2175 .model = 23,
2176 .stepping = 3,
2177 .features[FEAT_1_EDX] =
2178 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2179 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2180 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2181 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2182 CPUID_DE | CPUID_FP87,
2183 .features[FEAT_1_ECX] =
2184 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2185 CPUID_EXT_SSE3,
2186 .features[FEAT_8000_0001_EDX] =
2187 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2188 .features[FEAT_8000_0001_ECX] =
2189 CPUID_EXT3_LAHF_LM,
2190 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2191 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2192 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2193 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2194 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2195 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2196 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2197 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2198 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2199 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2200 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2201 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2202 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2203 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2204 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2205 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2206 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2207 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2208 .features[FEAT_VMX_SECONDARY_CTLS] =
2209 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2210 VMX_SECONDARY_EXEC_WBINVD_EXITING,
2211 .xlevel = 0x80000008,
2212 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2213 },
2214 {
2215 .name = "Nehalem",
2216 .level = 11,
2217 .vendor = CPUID_VENDOR_INTEL,
2218 .family = 6,
2219 .model = 26,
2220 .stepping = 3,
2221 .features[FEAT_1_EDX] =
2222 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2223 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2224 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2225 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2226 CPUID_DE | CPUID_FP87,
2227 .features[FEAT_1_ECX] =
2228 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2229 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2230 .features[FEAT_8000_0001_EDX] =
2231 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2232 .features[FEAT_8000_0001_ECX] =
2233 CPUID_EXT3_LAHF_LM,
2234 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2235 MSR_VMX_BASIC_TRUE_CTLS,
2236 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2237 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2238 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2239 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2240 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2241 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2242 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2243 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2244 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2245 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2246 .features[FEAT_VMX_EXIT_CTLS] =
2247 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2248 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2249 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2250 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2251 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2252 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2253 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2254 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2255 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2256 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2257 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2258 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2259 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2260 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2261 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2262 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2263 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2264 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2265 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2266 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2267 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2268 .features[FEAT_VMX_SECONDARY_CTLS] =
2269 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2270 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2271 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2272 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2273 VMX_SECONDARY_EXEC_ENABLE_VPID,
2274 .xlevel = 0x80000008,
2275 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
2276 .versions = (X86CPUVersionDefinition[]) {
2277 { .version = 1 },
2278 {
2279 .version = 2,
2280 .alias = "Nehalem-IBRS",
2281 .props = (PropValue[]) {
2282 { "spec-ctrl", "on" },
2283 { "model-id",
2284 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2285 { /* end of list */ }
2286 }
2287 },
2288 { /* end of list */ }
2289 }
2290 },
2291 {
2292 .name = "Westmere",
2293 .level = 11,
2294 .vendor = CPUID_VENDOR_INTEL,
2295 .family = 6,
2296 .model = 44,
2297 .stepping = 1,
2298 .features[FEAT_1_EDX] =
2299 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2300 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2301 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2302 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2303 CPUID_DE | CPUID_FP87,
2304 .features[FEAT_1_ECX] =
2305 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2306 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2307 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2308 .features[FEAT_8000_0001_EDX] =
2309 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2310 .features[FEAT_8000_0001_ECX] =
2311 CPUID_EXT3_LAHF_LM,
2312 .features[FEAT_6_EAX] =
2313 CPUID_6_EAX_ARAT,
2314 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2315 MSR_VMX_BASIC_TRUE_CTLS,
2316 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2317 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2318 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2319 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2320 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2321 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2322 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2323 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2324 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2325 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2326 .features[FEAT_VMX_EXIT_CTLS] =
2327 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2328 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2329 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2330 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2331 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2332 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2333 MSR_VMX_MISC_STORE_LMA,
2334 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2335 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2336 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2337 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2338 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2339 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2340 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2341 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2342 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2343 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2344 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2345 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2346 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2347 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2348 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2349 .features[FEAT_VMX_SECONDARY_CTLS] =
2350 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2351 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2352 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2353 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2354 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2355 .xlevel = 0x80000008,
2356 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2357 .versions = (X86CPUVersionDefinition[]) {
2358 { .version = 1 },
2359 {
2360 .version = 2,
2361 .alias = "Westmere-IBRS",
2362 .props = (PropValue[]) {
2363 { "spec-ctrl", "on" },
2364 { "model-id",
2365 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2366 { /* end of list */ }
2367 }
2368 },
2369 { /* end of list */ }
2370 }
2371 },
2372 {
2373 .name = "SandyBridge",
2374 .level = 0xd,
2375 .vendor = CPUID_VENDOR_INTEL,
2376 .family = 6,
2377 .model = 42,
2378 .stepping = 1,
2379 .features[FEAT_1_EDX] =
2380 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2381 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2382 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2383 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2384 CPUID_DE | CPUID_FP87,
2385 .features[FEAT_1_ECX] =
2386 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2387 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2388 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2389 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2390 CPUID_EXT_SSE3,
2391 .features[FEAT_8000_0001_EDX] =
2392 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2393 CPUID_EXT2_SYSCALL,
2394 .features[FEAT_8000_0001_ECX] =
2395 CPUID_EXT3_LAHF_LM,
2396 .features[FEAT_XSAVE] =
2397 CPUID_XSAVE_XSAVEOPT,
2398 .features[FEAT_6_EAX] =
2399 CPUID_6_EAX_ARAT,
2400 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2401 MSR_VMX_BASIC_TRUE_CTLS,
2402 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2403 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2404 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2405 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2406 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2407 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2408 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2409 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2410 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2411 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2412 .features[FEAT_VMX_EXIT_CTLS] =
2413 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2414 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2415 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2416 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2417 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2418 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2419 MSR_VMX_MISC_STORE_LMA,
2420 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2421 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2422 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2423 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2424 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2425 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2426 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2427 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2428 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2429 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2430 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2431 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2432 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2433 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2434 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2435 .features[FEAT_VMX_SECONDARY_CTLS] =
2436 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2437 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2438 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2439 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2440 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2441 .xlevel = 0x80000008,
2442 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
2443 .versions = (X86CPUVersionDefinition[]) {
2444 { .version = 1 },
2445 {
2446 .version = 2,
2447 .alias = "SandyBridge-IBRS",
2448 .props = (PropValue[]) {
2449 { "spec-ctrl", "on" },
2450 { "model-id",
2451 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2452 { /* end of list */ }
2453 }
2454 },
2455 { /* end of list */ }
2456 }
2457 },
2458 {
2459 .name = "IvyBridge",
2460 .level = 0xd,
2461 .vendor = CPUID_VENDOR_INTEL,
2462 .family = 6,
2463 .model = 58,
2464 .stepping = 9,
2465 .features[FEAT_1_EDX] =
2466 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2467 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2468 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2469 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2470 CPUID_DE | CPUID_FP87,
2471 .features[FEAT_1_ECX] =
2472 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2473 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2474 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2475 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2476 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2477 .features[FEAT_7_0_EBX] =
2478 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2479 CPUID_7_0_EBX_ERMS,
2480 .features[FEAT_8000_0001_EDX] =
2481 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2482 CPUID_EXT2_SYSCALL,
2483 .features[FEAT_8000_0001_ECX] =
2484 CPUID_EXT3_LAHF_LM,
2485 .features[FEAT_XSAVE] =
2486 CPUID_XSAVE_XSAVEOPT,
2487 .features[FEAT_6_EAX] =
2488 CPUID_6_EAX_ARAT,
2489 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2490 MSR_VMX_BASIC_TRUE_CTLS,
2491 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2492 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2493 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2494 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2495 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2496 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2497 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2498 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2499 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2500 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2501 .features[FEAT_VMX_EXIT_CTLS] =
2502 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2503 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2504 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2505 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2506 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2507 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2508 MSR_VMX_MISC_STORE_LMA,
2509 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2510 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2511 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2512 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2513 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2514 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2515 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2516 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2517 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2518 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2519 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2520 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2521 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2522 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2523 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2524 .features[FEAT_VMX_SECONDARY_CTLS] =
2525 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2526 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2527 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2528 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2529 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2530 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2531 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2532 VMX_SECONDARY_EXEC_RDRAND_EXITING,
2533 .xlevel = 0x80000008,
2534 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2535 .versions = (X86CPUVersionDefinition[]) {
2536 { .version = 1 },
2537 {
2538 .version = 2,
2539 .alias = "IvyBridge-IBRS",
2540 .props = (PropValue[]) {
2541 { "spec-ctrl", "on" },
2542 { "model-id",
2543 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2544 { /* end of list */ }
2545 }
2546 },
2547 { /* end of list */ }
2548 }
2549 },
2550 {
2551 .name = "Haswell",
2552 .level = 0xd,
2553 .vendor = CPUID_VENDOR_INTEL,
2554 .family = 6,
2555 .model = 60,
2556 .stepping = 4,
2557 .features[FEAT_1_EDX] =
2558 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2559 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2560 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2561 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2562 CPUID_DE | CPUID_FP87,
2563 .features[FEAT_1_ECX] =
2564 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2565 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2566 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2567 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2568 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2569 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2570 .features[FEAT_8000_0001_EDX] =
2571 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2572 CPUID_EXT2_SYSCALL,
2573 .features[FEAT_8000_0001_ECX] =
2574 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2575 .features[FEAT_7_0_EBX] =
2576 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2577 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2578 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2579 CPUID_7_0_EBX_RTM,
2580 .features[FEAT_XSAVE] =
2581 CPUID_XSAVE_XSAVEOPT,
2582 .features[FEAT_6_EAX] =
2583 CPUID_6_EAX_ARAT,
2584 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2585 MSR_VMX_BASIC_TRUE_CTLS,
2586 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2587 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2588 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2589 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2590 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2591 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2592 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2593 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2594 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2595 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2596 .features[FEAT_VMX_EXIT_CTLS] =
2597 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2598 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2599 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2600 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2601 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2602 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2603 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2604 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2605 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2606 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2607 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2608 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2609 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2610 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2611 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2612 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2613 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2614 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2615 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2616 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2617 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2618 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2619 .features[FEAT_VMX_SECONDARY_CTLS] =
2620 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2621 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2622 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2623 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2624 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2625 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2626 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2627 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2628 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2629 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2630 .xlevel = 0x80000008,
2631 .model_id = "Intel Core Processor (Haswell)",
2632 .versions = (X86CPUVersionDefinition[]) {
2633 { .version = 1 },
2634 {
2635 .version = 2,
2636 .alias = "Haswell-noTSX",
2637 .props = (PropValue[]) {
2638 { "hle", "off" },
2639 { "rtm", "off" },
2640 { "stepping", "1" },
2641 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2642 { /* end of list */ }
2643 },
2644 },
2645 {
2646 .version = 3,
2647 .alias = "Haswell-IBRS",
2648 .props = (PropValue[]) {
2649 /* Restore TSX features removed by -v2 above */
2650 { "hle", "on" },
2651 { "rtm", "on" },
2652 /*
2653 * Haswell and Haswell-IBRS had stepping=4 in
2654 * QEMU 4.0 and older
2655 */
2656 { "stepping", "4" },
2657 { "spec-ctrl", "on" },
2658 { "model-id",
2659 "Intel Core Processor (Haswell, IBRS)" },
2660 { /* end of list */ }
2661 }
2662 },
2663 {
2664 .version = 4,
2665 .alias = "Haswell-noTSX-IBRS",
2666 .props = (PropValue[]) {
2667 { "hle", "off" },
2668 { "rtm", "off" },
2669 /* spec-ctrl was already enabled by -v3 above */
2670 { "stepping", "1" },
2671 { "model-id",
2672 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2673 { /* end of list */ }
2674 }
2675 },
2676 { /* end of list */ }
2677 }
2678 },
2679 {
2680 .name = "Broadwell",
2681 .level = 0xd,
2682 .vendor = CPUID_VENDOR_INTEL,
2683 .family = 6,
2684 .model = 61,
2685 .stepping = 2,
2686 .features[FEAT_1_EDX] =
2687 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2688 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2689 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2690 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2691 CPUID_DE | CPUID_FP87,
2692 .features[FEAT_1_ECX] =
2693 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2694 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2695 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2696 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2697 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2698 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2699 .features[FEAT_8000_0001_EDX] =
2700 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2701 CPUID_EXT2_SYSCALL,
2702 .features[FEAT_8000_0001_ECX] =
2703 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2704 .features[FEAT_7_0_EBX] =
2705 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2706 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2707 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2708 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2709 CPUID_7_0_EBX_SMAP,
2710 .features[FEAT_XSAVE] =
2711 CPUID_XSAVE_XSAVEOPT,
2712 .features[FEAT_6_EAX] =
2713 CPUID_6_EAX_ARAT,
2714 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2715 MSR_VMX_BASIC_TRUE_CTLS,
2716 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2717 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2718 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2719 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2720 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2721 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2722 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2723 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2724 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2725 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2726 .features[FEAT_VMX_EXIT_CTLS] =
2727 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2728 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2729 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2730 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2731 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2732 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2733 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2734 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2735 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2736 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2737 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2738 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2739 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2740 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2741 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2742 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2743 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2744 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2745 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2746 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2747 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2748 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2749 .features[FEAT_VMX_SECONDARY_CTLS] =
2750 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2751 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2752 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2753 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2754 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2755 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2756 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2757 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2758 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2759 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2760 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2761 .xlevel = 0x80000008,
2762 .model_id = "Intel Core Processor (Broadwell)",
2763 .versions = (X86CPUVersionDefinition[]) {
2764 { .version = 1 },
2765 {
2766 .version = 2,
2767 .alias = "Broadwell-noTSX",
2768 .props = (PropValue[]) {
2769 { "hle", "off" },
2770 { "rtm", "off" },
2771 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2772 { /* end of list */ }
2773 },
2774 },
2775 {
2776 .version = 3,
2777 .alias = "Broadwell-IBRS",
2778 .props = (PropValue[]) {
2779 /* Restore TSX features removed by -v2 above */
2780 { "hle", "on" },
2781 { "rtm", "on" },
2782 { "spec-ctrl", "on" },
2783 { "model-id",
2784 "Intel Core Processor (Broadwell, IBRS)" },
2785 { /* end of list */ }
2786 }
2787 },
2788 {
2789 .version = 4,
2790 .alias = "Broadwell-noTSX-IBRS",
2791 .props = (PropValue[]) {
2792 { "hle", "off" },
2793 { "rtm", "off" },
2794 /* spec-ctrl was already enabled by -v3 above */
2795 { "model-id",
2796 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2797 { /* end of list */ }
2798 }
2799 },
2800 { /* end of list */ }
2801 }
2802 },
2803 {
2804 .name = "Skylake-Client",
2805 .level = 0xd,
2806 .vendor = CPUID_VENDOR_INTEL,
2807 .family = 6,
2808 .model = 94,
2809 .stepping = 3,
2810 .features[FEAT_1_EDX] =
2811 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2812 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2813 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2814 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2815 CPUID_DE | CPUID_FP87,
2816 .features[FEAT_1_ECX] =
2817 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2818 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2819 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2820 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2821 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2822 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2823 .features[FEAT_8000_0001_EDX] =
2824 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2825 CPUID_EXT2_SYSCALL,
2826 .features[FEAT_8000_0001_ECX] =
2827 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2828 .features[FEAT_7_0_EBX] =
2829 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2830 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2831 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2832 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2833 CPUID_7_0_EBX_SMAP,
2834 /* Missing: XSAVES (not supported by some Linux versions,
2835 * including v4.1 to v4.12).
2836 * KVM doesn't yet expose any XSAVES state save component,
2837 * and the only one defined in Skylake (processor tracing)
2838 * probably will block migration anyway.
2839 */
2840 .features[FEAT_XSAVE] =
2841 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2842 CPUID_XSAVE_XGETBV1,
2843 .features[FEAT_6_EAX] =
2844 CPUID_6_EAX_ARAT,
2845 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2846 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2847 MSR_VMX_BASIC_TRUE_CTLS,
2848 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2849 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2850 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2851 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2852 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2853 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2854 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2855 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2856 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2857 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2858 .features[FEAT_VMX_EXIT_CTLS] =
2859 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2860 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2861 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2862 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2863 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2864 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2865 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2866 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2867 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2868 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2869 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2870 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2871 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2872 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2873 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2874 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2875 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2876 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2877 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2878 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2879 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2880 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2881 .features[FEAT_VMX_SECONDARY_CTLS] =
2882 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2883 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2884 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2885 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2886 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2887 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2888 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2889 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2890 .xlevel = 0x80000008,
2891 .model_id = "Intel Core Processor (Skylake)",
2892 .versions = (X86CPUVersionDefinition[]) {
2893 { .version = 1 },
2894 {
2895 .version = 2,
2896 .alias = "Skylake-Client-IBRS",
2897 .props = (PropValue[]) {
2898 { "spec-ctrl", "on" },
2899 { "model-id",
2900 "Intel Core Processor (Skylake, IBRS)" },
2901 { /* end of list */ }
2902 }
2903 },
2904 {
2905 .version = 3,
2906 .alias = "Skylake-Client-noTSX-IBRS",
2907 .props = (PropValue[]) {
2908 { "hle", "off" },
2909 { "rtm", "off" },
2910 { "model-id",
2911 "Intel Core Processor (Skylake, IBRS, no TSX)" },
2912 { /* end of list */ }
2913 }
2914 },
2915 { /* end of list */ }
2916 }
2917 },
2918 {
2919 .name = "Skylake-Server",
2920 .level = 0xd,
2921 .vendor = CPUID_VENDOR_INTEL,
2922 .family = 6,
2923 .model = 85,
2924 .stepping = 4,
2925 .features[FEAT_1_EDX] =
2926 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2927 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2928 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2929 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2930 CPUID_DE | CPUID_FP87,
2931 .features[FEAT_1_ECX] =
2932 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2933 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2934 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2935 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2936 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2937 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2938 .features[FEAT_8000_0001_EDX] =
2939 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2940 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2941 .features[FEAT_8000_0001_ECX] =
2942 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2943 .features[FEAT_7_0_EBX] =
2944 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2945 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2946 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2947 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2948 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2949 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2950 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2951 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2952 .features[FEAT_7_0_ECX] =
2953 CPUID_7_0_ECX_PKU,
2954 /* Missing: XSAVES (not supported by some Linux versions,
2955 * including v4.1 to v4.12).
2956 * KVM doesn't yet expose any XSAVES state save component,
2957 * and the only one defined in Skylake (processor tracing)
2958 * probably will block migration anyway.
2959 */
2960 .features[FEAT_XSAVE] =
2961 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2962 CPUID_XSAVE_XGETBV1,
2963 .features[FEAT_6_EAX] =
2964 CPUID_6_EAX_ARAT,
2965 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2966 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2967 MSR_VMX_BASIC_TRUE_CTLS,
2968 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2969 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2970 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2971 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2972 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2973 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2974 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2975 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2976 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2977 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2978 .features[FEAT_VMX_EXIT_CTLS] =
2979 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2980 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2981 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2982 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2983 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2984 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2985 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2986 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2987 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2988 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2989 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2990 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2991 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2992 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2993 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2994 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2995 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2996 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2997 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2998 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2999 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3000 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3001 .features[FEAT_VMX_SECONDARY_CTLS] =
3002 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3003 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3004 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3005 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3006 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3007 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3008 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3009 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3010 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3011 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3012 .xlevel = 0x80000008,
3013 .model_id = "Intel Xeon Processor (Skylake)",
3014 .versions = (X86CPUVersionDefinition[]) {
3015 { .version = 1 },
3016 {
3017 .version = 2,
3018 .alias = "Skylake-Server-IBRS",
3019 .props = (PropValue[]) {
3020 /* clflushopt was not added to Skylake-Server-IBRS */
3021 /* TODO: add -v3 including clflushopt */
3022 { "clflushopt", "off" },
3023 { "spec-ctrl", "on" },
3024 { "model-id",
3025 "Intel Xeon Processor (Skylake, IBRS)" },
3026 { /* end of list */ }
3027 }
3028 },
3029 {
3030 .version = 3,
3031 .alias = "Skylake-Server-noTSX-IBRS",
3032 .props = (PropValue[]) {
3033 { "hle", "off" },
3034 { "rtm", "off" },
3035 { "model-id",
3036 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
3037 { /* end of list */ }
3038 }
3039 },
3040 { /* end of list */ }
3041 }
3042 },
3043 {
3044 .name = "Cascadelake-Server",
3045 .level = 0xd,
3046 .vendor = CPUID_VENDOR_INTEL,
3047 .family = 6,
3048 .model = 85,
3049 .stepping = 6,
3050 .features[FEAT_1_EDX] =
3051 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3052 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3053 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3054 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3055 CPUID_DE | CPUID_FP87,
3056 .features[FEAT_1_ECX] =
3057 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3058 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3059 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3060 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3061 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3062 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3063 .features[FEAT_8000_0001_EDX] =
3064 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3065 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3066 .features[FEAT_8000_0001_ECX] =
3067 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3068 .features[FEAT_7_0_EBX] =
3069 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3070 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3071 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3072 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3073 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3074 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3075 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3076 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3077 .features[FEAT_7_0_ECX] =
3078 CPUID_7_0_ECX_PKU |
3079 CPUID_7_0_ECX_AVX512VNNI,
3080 .features[FEAT_7_0_EDX] =
3081 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3082 /* Missing: XSAVES (not supported by some Linux versions,
3083 * including v4.1 to v4.12).
3084 * KVM doesn't yet expose any XSAVES state save component,
3085 * and the only one defined in Skylake (processor tracing)
3086 * probably will block migration anyway.
3087 */
3088 .features[FEAT_XSAVE] =
3089 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3090 CPUID_XSAVE_XGETBV1,
3091 .features[FEAT_6_EAX] =
3092 CPUID_6_EAX_ARAT,
3093 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3094 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3095 MSR_VMX_BASIC_TRUE_CTLS,
3096 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3097 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3098 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3099 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3100 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3101 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3102 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3103 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3104 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3105 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3106 .features[FEAT_VMX_EXIT_CTLS] =
3107 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3108 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3109 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3110 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3111 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3112 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3113 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3114 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3115 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3116 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3117 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3118 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3119 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3120 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3121 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3122 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3123 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3124 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3125 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3126 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3127 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3128 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3129 .features[FEAT_VMX_SECONDARY_CTLS] =
3130 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3131 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3132 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3133 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3134 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3135 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3136 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3137 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3138 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3139 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3140 .xlevel = 0x80000008,
3141 .model_id = "Intel Xeon Processor (Cascadelake)",
3142 .versions = (X86CPUVersionDefinition[]) {
3143 { .version = 1 },
3144 { .version = 2,
3145 .props = (PropValue[]) {
3146 { "arch-capabilities", "on" },
3147 { "rdctl-no", "on" },
3148 { "ibrs-all", "on" },
3149 { "skip-l1dfl-vmentry", "on" },
3150 { "mds-no", "on" },
3151 { /* end of list */ }
3152 },
3153 },
3154 { .version = 3,
3155 .alias = "Cascadelake-Server-noTSX",
3156 .props = (PropValue[]) {
3157 { "hle", "off" },
3158 { "rtm", "off" },
3159 { /* end of list */ }
3160 },
3161 },
3162 { /* end of list */ }
3163 }
3164 },
3165 {
3166 .name = "Cooperlake",
3167 .level = 0xd,
3168 .vendor = CPUID_VENDOR_INTEL,
3169 .family = 6,
3170 .model = 85,
3171 .stepping = 10,
3172 .features[FEAT_1_EDX] =
3173 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3174 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3175 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3176 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3177 CPUID_DE | CPUID_FP87,
3178 .features[FEAT_1_ECX] =
3179 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3180 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3181 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3182 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3183 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3184 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3185 .features[FEAT_8000_0001_EDX] =
3186 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3187 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3188 .features[FEAT_8000_0001_ECX] =
3189 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3190 .features[FEAT_7_0_EBX] =
3191 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3192 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3193 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3194 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3195 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3196 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3197 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3198 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3199 .features[FEAT_7_0_ECX] =
3200 CPUID_7_0_ECX_PKU |
3201 CPUID_7_0_ECX_AVX512VNNI,
3202 .features[FEAT_7_0_EDX] =
3203 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3204 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3205 .features[FEAT_ARCH_CAPABILITIES] =
3206 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
3207 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3208 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
3209 .features[FEAT_7_1_EAX] =
3210 CPUID_7_1_EAX_AVX512_BF16,
3211 /*
3212 * Missing: XSAVES (not supported by some Linux versions,
3213 * including v4.1 to v4.12).
3214 * KVM doesn't yet expose any XSAVES state save component,
3215 * and the only one defined in Skylake (processor tracing)
3216 * probably will block migration anyway.
3217 */
3218 .features[FEAT_XSAVE] =
3219 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3220 CPUID_XSAVE_XGETBV1,
3221 .features[FEAT_6_EAX] =
3222 CPUID_6_EAX_ARAT,
3223 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3224 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3225 MSR_VMX_BASIC_TRUE_CTLS,
3226 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3227 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3228 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3229 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3230 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3231 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3232 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3233 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3234 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3235 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3236 .features[FEAT_VMX_EXIT_CTLS] =
3237 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3238 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3239 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3240 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3241 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3242 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3243 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3244 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3245 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3246 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3247 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3248 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3249 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3250 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3251 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3252 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3253 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3254 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3255 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3256 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3257 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3258 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3259 .features[FEAT_VMX_SECONDARY_CTLS] =
3260 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3261 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3262 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3263 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3264 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3265 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3266 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3267 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3268 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3269 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3270 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3271 .xlevel = 0x80000008,
3272 .model_id = "Intel Xeon Processor (Cooperlake)",
3273 },
3274 {
3275 .name = "Icelake-Client",
3276 .level = 0xd,
3277 .vendor = CPUID_VENDOR_INTEL,
3278 .family = 6,
3279 .model = 126,
3280 .stepping = 0,
3281 .features[FEAT_1_EDX] =
3282 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3283 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3284 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3285 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3286 CPUID_DE | CPUID_FP87,
3287 .features[FEAT_1_ECX] =
3288 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3289 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3290 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3291 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3292 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3293 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3294 .features[FEAT_8000_0001_EDX] =
3295 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3296 CPUID_EXT2_SYSCALL,
3297 .features[FEAT_8000_0001_ECX] =
3298 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3299 .features[FEAT_8000_0008_EBX] =
3300 CPUID_8000_0008_EBX_WBNOINVD,
3301 .features[FEAT_7_0_EBX] =
3302 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3303 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3304 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3305 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3306 CPUID_7_0_EBX_SMAP,
3307 .features[FEAT_7_0_ECX] =
3308 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3309 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3310 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3311 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3312 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3313 .features[FEAT_7_0_EDX] =
3314 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3315 /* Missing: XSAVES (not supported by some Linux versions,
3316 * including v4.1 to v4.12).
3317 * KVM doesn't yet expose any XSAVES state save component,
3318 * and the only one defined in Skylake (processor tracing)
3319 * probably will block migration anyway.
3320 */
3321 .features[FEAT_XSAVE] =
3322 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3323 CPUID_XSAVE_XGETBV1,
3324 .features[FEAT_6_EAX] =
3325 CPUID_6_EAX_ARAT,
3326 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3327 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3328 MSR_VMX_BASIC_TRUE_CTLS,
3329 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3330 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3331 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3332 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3333 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3334 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3335 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3336 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3337 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3338 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3339 .features[FEAT_VMX_EXIT_CTLS] =
3340 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3341 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3342 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3343 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3344 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3345 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3346 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3347 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3348 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3349 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3350 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3351 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3352 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3353 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3354 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3355 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3356 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3357 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3358 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3359 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3360 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3361 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3362 .features[FEAT_VMX_SECONDARY_CTLS] =
3363 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3364 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3365 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3366 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3367 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3368 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3369 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3370 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3371 .xlevel = 0x80000008,
3372 .model_id = "Intel Core Processor (Icelake)",
3373 .versions = (X86CPUVersionDefinition[]) {
3374 { .version = 1 },
3375 {
3376 .version = 2,
3377 .alias = "Icelake-Client-noTSX",
3378 .props = (PropValue[]) {
3379 { "hle", "off" },
3380 { "rtm", "off" },
3381 { /* end of list */ }
3382 },
3383 },
3384 { /* end of list */ }
3385 }
3386 },
3387 {
3388 .name = "Icelake-Server",
3389 .level = 0xd,
3390 .vendor = CPUID_VENDOR_INTEL,
3391 .family = 6,
3392 .model = 134,
3393 .stepping = 0,
3394 .features[FEAT_1_EDX] =
3395 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3396 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3397 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3398 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3399 CPUID_DE | CPUID_FP87,
3400 .features[FEAT_1_ECX] =
3401 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3402 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3403 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3404 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3405 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3406 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3407 .features[FEAT_8000_0001_EDX] =
3408 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3409 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3410 .features[FEAT_8000_0001_ECX] =
3411 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3412 .features[FEAT_8000_0008_EBX] =
3413 CPUID_8000_0008_EBX_WBNOINVD,
3414 .features[FEAT_7_0_EBX] =
3415 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3416 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3417 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3418 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3419 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3420 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3421 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3422 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3423 .features[FEAT_7_0_ECX] =
3424 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3425 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3426 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3427 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3428 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3429 .features[FEAT_7_0_EDX] =
3430 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3431 /* Missing: XSAVES (not supported by some Linux versions,
3432 * including v4.1 to v4.12).
3433 * KVM doesn't yet expose any XSAVES state save component,
3434 * and the only one defined in Skylake (processor tracing)
3435 * probably will block migration anyway.
3436 */
3437 .features[FEAT_XSAVE] =
3438 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3439 CPUID_XSAVE_XGETBV1,
3440 .features[FEAT_6_EAX] =
3441 CPUID_6_EAX_ARAT,
3442 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3443 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3444 MSR_VMX_BASIC_TRUE_CTLS,
3445 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3446 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3447 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3448 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3449 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3450 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3451 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3452 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3453 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3454 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3455 .features[FEAT_VMX_EXIT_CTLS] =
3456 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3457 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3458 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3459 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3460 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3461 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3462 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3463 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3464 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3465 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3466 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3467 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3468 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3469 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3470 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3471 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3472 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3473 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3474 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3475 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3476 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3477 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3478 .features[FEAT_VMX_SECONDARY_CTLS] =
3479 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3480 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3481 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3482 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3483 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3484 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3485 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3486 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3487 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
3488 .xlevel = 0x80000008,
3489 .model_id = "Intel Xeon Processor (Icelake)",
3490 .versions = (X86CPUVersionDefinition[]) {
3491 { .version = 1 },
3492 {
3493 .version = 2,
3494 .alias = "Icelake-Server-noTSX",
3495 .props = (PropValue[]) {
3496 { "hle", "off" },
3497 { "rtm", "off" },
3498 { /* end of list */ }
3499 },
3500 },
3501 { /* end of list */ }
3502 }
3503 },
3504 {
3505 .name = "Denverton",
3506 .level = 21,
3507 .vendor = CPUID_VENDOR_INTEL,
3508 .family = 6,
3509 .model = 95,
3510 .stepping = 1,
3511 .features[FEAT_1_EDX] =
3512 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3513 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3514 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3515 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3516 CPUID_SSE | CPUID_SSE2,
3517 .features[FEAT_1_ECX] =
3518 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3519 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3520 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3521 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3522 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3523 .features[FEAT_8000_0001_EDX] =
3524 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3525 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3526 .features[FEAT_8000_0001_ECX] =
3527 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3528 .features[FEAT_7_0_EBX] =
3529 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3530 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3531 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3532 .features[FEAT_7_0_EDX] =
3533 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3534 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3535 /*
3536 * Missing: XSAVES (not supported by some Linux versions,
3537 * including v4.1 to v4.12).
3538 * KVM doesn't yet expose any XSAVES state save component,
3539 * and the only one defined in Skylake (processor tracing)
3540 * probably will block migration anyway.
3541 */
3542 .features[FEAT_XSAVE] =
3543 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3544 .features[FEAT_6_EAX] =
3545 CPUID_6_EAX_ARAT,
3546 .features[FEAT_ARCH_CAPABILITIES] =
3547 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
3548 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3549 MSR_VMX_BASIC_TRUE_CTLS,
3550 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3551 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3552 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3553 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3554 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3555 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3556 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3557 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3558 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3559 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3560 .features[FEAT_VMX_EXIT_CTLS] =
3561 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3562 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3563 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3564 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3565 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3566 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3567 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3568 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3569 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3570 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3571 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3572 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3573 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3574 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3575 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3576 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3577 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3578 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3579 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3580 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3581 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3582 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3583 .features[FEAT_VMX_SECONDARY_CTLS] =
3584 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3585 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3586 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3587 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3588 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3589 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3590 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3591 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3592 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3593 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3594 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3595 .xlevel = 0x80000008,
3596 .model_id = "Intel Atom Processor (Denverton)",
3597 .versions = (X86CPUVersionDefinition[]) {
3598 { .version = 1 },
3599 {
3600 .version = 2,
3601 .props = (PropValue[]) {
3602 { "monitor", "off" },
3603 { "mpx", "off" },
3604 { /* end of list */ },
3605 },
3606 },
3607 { /* end of list */ },
3608 },
3609 },
3610 {
3611 .name = "Snowridge",
3612 .level = 27,
3613 .vendor = CPUID_VENDOR_INTEL,
3614 .family = 6,
3615 .model = 134,
3616 .stepping = 1,
3617 .features[FEAT_1_EDX] =
3618 /* missing: CPUID_PN CPUID_IA64 */
3619 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3620 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3621 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3622 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3623 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3624 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3625 CPUID_MMX |
3626 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3627 .features[FEAT_1_ECX] =
3628 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3629 CPUID_EXT_SSSE3 |
3630 CPUID_EXT_CX16 |
3631 CPUID_EXT_SSE41 |
3632 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3633 CPUID_EXT_POPCNT |
3634 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3635 CPUID_EXT_RDRAND,
3636 .features[FEAT_8000_0001_EDX] =
3637 CPUID_EXT2_SYSCALL |
3638 CPUID_EXT2_NX |
3639 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3640 CPUID_EXT2_LM,
3641 .features[FEAT_8000_0001_ECX] =
3642 CPUID_EXT3_LAHF_LM |
3643 CPUID_EXT3_3DNOWPREFETCH,
3644 .features[FEAT_7_0_EBX] =
3645 CPUID_7_0_EBX_FSGSBASE |
3646 CPUID_7_0_EBX_SMEP |
3647 CPUID_7_0_EBX_ERMS |
3648 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
3649 CPUID_7_0_EBX_RDSEED |
3650 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3651 CPUID_7_0_EBX_CLWB |
3652 CPUID_7_0_EBX_SHA_NI,
3653 .features[FEAT_7_0_ECX] =
3654 CPUID_7_0_ECX_UMIP |
3655 /* missing bit 5 */
3656 CPUID_7_0_ECX_GFNI |
3657 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3658 CPUID_7_0_ECX_MOVDIR64B,
3659 .features[FEAT_7_0_EDX] =
3660 CPUID_7_0_EDX_SPEC_CTRL |
3661 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3662 CPUID_7_0_EDX_CORE_CAPABILITY,
3663 .features[FEAT_CORE_CAPABILITY] =
3664 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
3665 /*
3666 * Missing: XSAVES (not supported by some Linux versions,
3667 * including v4.1 to v4.12).
3668 * KVM doesn't yet expose any XSAVES state save component,
3669 * and the only one defined in Skylake (processor tracing)
3670 * probably will block migration anyway.
3671 */
3672 .features[FEAT_XSAVE] =
3673 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3674 CPUID_XSAVE_XGETBV1,
3675 .features[FEAT_6_EAX] =
3676 CPUID_6_EAX_ARAT,
3677 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3678 MSR_VMX_BASIC_TRUE_CTLS,
3679 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3680 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3681 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3682 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3683 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3684 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3685 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3686 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3687 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3688 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3689 .features[FEAT_VMX_EXIT_CTLS] =
3690 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3691 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3692 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3693 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3694 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3695 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3696 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3697 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3698 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3699 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3700 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3701 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3702 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3703 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3704 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3705 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3706 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3707 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3708 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3709 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3710 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3711 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3712 .features[FEAT_VMX_SECONDARY_CTLS] =
3713 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3714 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3715 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3716 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3717 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3718 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3719 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3720 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3721 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3722 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3723 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3724 .xlevel = 0x80000008,
3725 .model_id = "Intel Atom Processor (SnowRidge)",
3726 .versions = (X86CPUVersionDefinition[]) {
3727 { .version = 1 },
3728 {
3729 .version = 2,
3730 .props = (PropValue[]) {
3731 { "mpx", "off" },
3732 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3733 { /* end of list */ },
3734 },
3735 },
3736 { /* end of list */ },
3737 },
3738 },
3739 {
3740 .name = "KnightsMill",
3741 .level = 0xd,
3742 .vendor = CPUID_VENDOR_INTEL,
3743 .family = 6,
3744 .model = 133,
3745 .stepping = 0,
3746 .features[FEAT_1_EDX] =
3747 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3748 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3749 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3750 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3751 CPUID_PSE | CPUID_DE | CPUID_FP87,
3752 .features[FEAT_1_ECX] =
3753 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3754 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3755 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3756 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3757 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3758 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3759 .features[FEAT_8000_0001_EDX] =
3760 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3761 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3762 .features[FEAT_8000_0001_ECX] =
3763 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3764 .features[FEAT_7_0_EBX] =
3765 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3766 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3767 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3768 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3769 CPUID_7_0_EBX_AVX512ER,
3770 .features[FEAT_7_0_ECX] =
3771 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3772 .features[FEAT_7_0_EDX] =
3773 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3774 .features[FEAT_XSAVE] =
3775 CPUID_XSAVE_XSAVEOPT,
3776 .features[FEAT_6_EAX] =
3777 CPUID_6_EAX_ARAT,
3778 .xlevel = 0x80000008,
3779 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3780 },
3781 {
3782 .name = "Opteron_G1",
3783 .level = 5,
3784 .vendor = CPUID_VENDOR_AMD,
3785 .family = 15,
3786 .model = 6,
3787 .stepping = 1,
3788 .features[FEAT_1_EDX] =
3789 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3790 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3791 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3792 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3793 CPUID_DE | CPUID_FP87,
3794 .features[FEAT_1_ECX] =
3795 CPUID_EXT_SSE3,
3796 .features[FEAT_8000_0001_EDX] =
3797 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3798 .xlevel = 0x80000008,
3799 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3800 },
3801 {
3802 .name = "Opteron_G2",
3803 .level = 5,
3804 .vendor = CPUID_VENDOR_AMD,
3805 .family = 15,
3806 .model = 6,
3807 .stepping = 1,
3808 .features[FEAT_1_EDX] =
3809 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3810 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3811 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3812 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3813 CPUID_DE | CPUID_FP87,
3814 .features[FEAT_1_ECX] =
3815 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
3816 .features[FEAT_8000_0001_EDX] =
3817 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3818 .features[FEAT_8000_0001_ECX] =
3819 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3820 .xlevel = 0x80000008,
3821 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3822 },
3823 {
3824 .name = "Opteron_G3",
3825 .level = 5,
3826 .vendor = CPUID_VENDOR_AMD,
3827 .family = 16,
3828 .model = 2,
3829 .stepping = 3,
3830 .features[FEAT_1_EDX] =
3831 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3832 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3833 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3834 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3835 CPUID_DE | CPUID_FP87,
3836 .features[FEAT_1_ECX] =
3837 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3838 CPUID_EXT_SSE3,
3839 .features[FEAT_8000_0001_EDX] =
3840 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3841 CPUID_EXT2_RDTSCP,
3842 .features[FEAT_8000_0001_ECX] =
3843 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3844 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3845 .xlevel = 0x80000008,
3846 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3847 },
3848 {
3849 .name = "Opteron_G4",
3850 .level = 0xd,
3851 .vendor = CPUID_VENDOR_AMD,
3852 .family = 21,
3853 .model = 1,
3854 .stepping = 2,
3855 .features[FEAT_1_EDX] =
3856 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3857 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3858 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3859 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3860 CPUID_DE | CPUID_FP87,
3861 .features[FEAT_1_ECX] =
3862 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3863 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3864 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3865 CPUID_EXT_SSE3,
3866 .features[FEAT_8000_0001_EDX] =
3867 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3868 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3869 .features[FEAT_8000_0001_ECX] =
3870 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3871 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3872 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3873 CPUID_EXT3_LAHF_LM,
3874 .features[FEAT_SVM] =
3875 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3876 /* no xsaveopt! */
3877 .xlevel = 0x8000001A,
3878 .model_id = "AMD Opteron 62xx class CPU",
3879 },
3880 {
3881 .name = "Opteron_G5",
3882 .level = 0xd,
3883 .vendor = CPUID_VENDOR_AMD,
3884 .family = 21,
3885 .model = 2,
3886 .stepping = 0,
3887 .features[FEAT_1_EDX] =
3888 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3889 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3890 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3891 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3892 CPUID_DE | CPUID_FP87,
3893 .features[FEAT_1_ECX] =
3894 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
3895 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3896 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3897 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3898 .features[FEAT_8000_0001_EDX] =
3899 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3900 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3901 .features[FEAT_8000_0001_ECX] =
3902 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3903 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3904 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3905 CPUID_EXT3_LAHF_LM,
3906 .features[FEAT_SVM] =
3907 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3908 /* no xsaveopt! */
3909 .xlevel = 0x8000001A,
3910 .model_id = "AMD Opteron 63xx class CPU",
3911 },
3912 {
3913 .name = "EPYC",
3914 .level = 0xd,
3915 .vendor = CPUID_VENDOR_AMD,
3916 .family = 23,
3917 .model = 1,
3918 .stepping = 2,
3919 .features[FEAT_1_EDX] =
3920 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3921 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3922 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3923 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3924 CPUID_VME | CPUID_FP87,
3925 .features[FEAT_1_ECX] =
3926 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3927 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3928 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3929 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3930 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3931 .features[FEAT_8000_0001_EDX] =
3932 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3933 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3934 CPUID_EXT2_SYSCALL,
3935 .features[FEAT_8000_0001_ECX] =
3936 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3937 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
3938 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3939 CPUID_EXT3_TOPOEXT,
3940 .features[FEAT_7_0_EBX] =
3941 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3942 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3943 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3944 CPUID_7_0_EBX_SHA_NI,
3945 /* Missing: XSAVES (not supported by some Linux versions,
3946 * including v4.1 to v4.12).
3947 * KVM doesn't yet expose any XSAVES state save component.
3948 */
3949 .features[FEAT_XSAVE] =
3950 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3951 CPUID_XSAVE_XGETBV1,
3952 .features[FEAT_6_EAX] =
3953 CPUID_6_EAX_ARAT,
3954 .features[FEAT_SVM] =
3955 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3956 .xlevel = 0x8000001E,
3957 .model_id = "AMD EPYC Processor",
3958 .cache_info = &epyc_cache_info,
3959 .versions = (X86CPUVersionDefinition[]) {
3960 { .version = 1 },
3961 {
3962 .version = 2,
3963 .alias = "EPYC-IBPB",
3964 .props = (PropValue[]) {
3965 { "ibpb", "on" },
3966 { "model-id",
3967 "AMD EPYC Processor (with IBPB)" },
3968 { /* end of list */ }
3969 }
3970 },
3971 { /* end of list */ }
3972 }
3973 },
3974 {
3975 .name = "Dhyana",
3976 .level = 0xd,
3977 .vendor = CPUID_VENDOR_HYGON,
3978 .family = 24,
3979 .model = 0,
3980 .stepping = 1,
3981 .features[FEAT_1_EDX] =
3982 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3983 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3984 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3985 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3986 CPUID_VME | CPUID_FP87,
3987 .features[FEAT_1_ECX] =
3988 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3989 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
3990 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3991 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3992 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
3993 .features[FEAT_8000_0001_EDX] =
3994 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3995 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3996 CPUID_EXT2_SYSCALL,
3997 .features[FEAT_8000_0001_ECX] =
3998 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3999 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4000 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4001 CPUID_EXT3_TOPOEXT,
4002 .features[FEAT_8000_0008_EBX] =
4003 CPUID_8000_0008_EBX_IBPB,
4004 .features[FEAT_7_0_EBX] =
4005 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4006 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4007 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
4008 /*
4009 * Missing: XSAVES (not supported by some Linux versions,
4010 * including v4.1 to v4.12).
4011 * KVM doesn't yet expose any XSAVES state save component.
4012 */
4013 .features[FEAT_XSAVE] =
4014 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4015 CPUID_XSAVE_XGETBV1,
4016 .features[FEAT_6_EAX] =
4017 CPUID_6_EAX_ARAT,
4018 .features[FEAT_SVM] =
4019 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4020 .xlevel = 0x8000001E,
4021 .model_id = "Hygon Dhyana Processor",
4022 .cache_info = &epyc_cache_info,
4023 },
4024 };
4025
4026 /* KVM-specific features that are automatically added/removed
4027 * from all CPU models when KVM is enabled.
4028 */
4029 static PropValue kvm_default_props[] = {
4030 { "kvmclock", "on" },
4031 { "kvm-nopiodelay", "on" },
4032 { "kvm-asyncpf", "on" },
4033 { "kvm-steal-time", "on" },
4034 { "kvm-pv-eoi", "on" },
4035 { "kvmclock-stable-bit", "on" },
4036 { "x2apic", "on" },
4037 { "acpi", "off" },
4038 { "monitor", "off" },
4039 { "svm", "off" },
4040 { NULL, NULL },
4041 };
4042
4043 /* TCG-specific defaults that override all CPU models when using TCG
4044 */
4045 static PropValue tcg_default_props[] = {
4046 { "vme", "off" },
4047 { NULL, NULL },
4048 };
4049
4050
4051 /*
4052 * We resolve CPU model aliases using -v1 when using "-machine
4053 * none", but this is just for compatibility while libvirt isn't
4054 * adapted to resolve CPU model versions before creating VMs.
4055 * See "Runnability guarantee of CPU models" at * qemu-deprecated.texi.
4056 */
4057 X86CPUVersion default_cpu_version = 1;
4058
4059 void x86_cpu_set_default_version(X86CPUVersion version)
4060 {
4061 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4062 assert(version != CPU_VERSION_AUTO);
4063 default_cpu_version = version;
4064 }
4065
4066 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4067 {
4068 int v = 0;
4069 const X86CPUVersionDefinition *vdef =
4070 x86_cpu_def_get_versions(model->cpudef);
4071 while (vdef->version) {
4072 v = vdef->version;
4073 vdef++;
4074 }
4075 return v;
4076 }
4077
4078 /* Return the actual version being used for a specific CPU model */
4079 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4080 {
4081 X86CPUVersion v = model->version;
4082 if (v == CPU_VERSION_AUTO) {
4083 v = default_cpu_version;
4084 }
4085 if (v == CPU_VERSION_LATEST) {
4086 return x86_cpu_model_last_version(model);
4087 }
4088 return v;
4089 }
4090
4091 void x86_cpu_change_kvm_default(const char *prop, const char *value)
4092 {
4093 PropValue *pv;
4094 for (pv = kvm_default_props; pv->prop; pv++) {
4095 if (!strcmp(pv->prop, prop)) {
4096 pv->value = value;
4097 break;
4098 }
4099 }
4100
4101 /* It is valid to call this function only for properties that
4102 * are already present in the kvm_default_props table.
4103 */
4104 assert(pv->prop);
4105 }
4106
4107 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
4108 bool migratable_only);
4109
4110 static bool lmce_supported(void)
4111 {
4112 uint64_t mce_cap = 0;
4113
4114 #ifdef CONFIG_KVM
4115 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
4116 return false;
4117 }
4118 #endif
4119
4120 return !!(mce_cap & MCG_LMCE_P);
4121 }
4122
4123 #define CPUID_MODEL_ID_SZ 48
4124
4125 /**
4126 * cpu_x86_fill_model_id:
4127 * Get CPUID model ID string from host CPU.
4128 *
4129 * @str should have at least CPUID_MODEL_ID_SZ bytes
4130 *
4131 * The function does NOT add a null terminator to the string
4132 * automatically.
4133 */
4134 static int cpu_x86_fill_model_id(char *str)
4135 {
4136 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
4137 int i;
4138
4139 for (i = 0; i < 3; i++) {
4140 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
4141 memcpy(str + i * 16 + 0, &eax, 4);
4142 memcpy(str + i * 16 + 4, &ebx, 4);
4143 memcpy(str + i * 16 + 8, &ecx, 4);
4144 memcpy(str + i * 16 + 12, &edx, 4);
4145 }
4146 return 0;
4147 }
4148
4149 static Property max_x86_cpu_properties[] = {
4150 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
4151 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
4152 DEFINE_PROP_END_OF_LIST()
4153 };
4154
4155 static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
4156 {
4157 DeviceClass *dc = DEVICE_CLASS(oc);
4158 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4159
4160 xcc->ordering = 9;
4161
4162 xcc->model_description =
4163 "Enables all features supported by the accelerator in the current host";
4164
4165 device_class_set_props(dc, max_x86_cpu_properties);
4166 }
4167
4168 static void max_x86_cpu_initfn(Object *obj)
4169 {
4170 X86CPU *cpu = X86_CPU(obj);
4171 CPUX86State *env = &cpu->env;
4172 KVMState *s = kvm_state;
4173
4174 /* We can't fill the features array here because we don't know yet if
4175 * "migratable" is true or false.
4176 */
4177 cpu->max_features = true;
4178
4179 if (accel_uses_host_cpuid()) {
4180 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
4181 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
4182 int family, model, stepping;
4183
4184 host_vendor_fms(vendor, &family, &model, &stepping);
4185 cpu_x86_fill_model_id(model_id);
4186
4187 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
4188 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
4189 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
4190 object_property_set_int(OBJECT(cpu), stepping, "stepping",
4191 &error_abort);
4192 object_property_set_str(OBJECT(cpu), model_id, "model-id",
4193 &error_abort);
4194
4195 if (kvm_enabled()) {
4196 env->cpuid_min_level =
4197 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
4198 env->cpuid_min_xlevel =
4199 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
4200 env->cpuid_min_xlevel2 =
4201 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
4202 } else {
4203 env->cpuid_min_level =
4204 hvf_get_supported_cpuid(0x0, 0, R_EAX);
4205 env->cpuid_min_xlevel =
4206 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
4207 env->cpuid_min_xlevel2 =
4208 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
4209 }
4210
4211 if (lmce_supported()) {
4212 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
4213 }
4214 } else {
4215 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
4216 "vendor", &error_abort);
4217 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
4218 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
4219 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
4220 object_property_set_str(OBJECT(cpu),
4221 "QEMU TCG CPU version " QEMU_HW_VERSION,
4222 "model-id", &error_abort);
4223 }
4224
4225 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
4226 }
4227
4228 static const TypeInfo max_x86_cpu_type_info = {
4229 .name = X86_CPU_TYPE_NAME("max"),
4230 .parent = TYPE_X86_CPU,
4231 .instance_init = max_x86_cpu_initfn,
4232 .class_init = max_x86_cpu_class_init,
4233 };
4234
4235 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
4236 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
4237 {
4238 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4239
4240 xcc->host_cpuid_required = true;
4241 xcc->ordering = 8;
4242
4243 #if defined(CONFIG_KVM)
4244 xcc->model_description =
4245 "KVM processor with all supported host features ";
4246 #elif defined(CONFIG_HVF)
4247 xcc->model_description =
4248 "HVF processor with all supported host features ";
4249 #endif
4250 }
4251
4252 static const TypeInfo host_x86_cpu_type_info = {
4253 .name = X86_CPU_TYPE_NAME("host"),
4254 .parent = X86_CPU_TYPE_NAME("max"),
4255 .class_init = host_x86_cpu_class_init,
4256 };
4257
4258 #endif
4259
4260 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4261 {
4262 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4263
4264 switch (f->type) {
4265 case CPUID_FEATURE_WORD:
4266 {
4267 const char *reg = get_register_name_32(f->cpuid.reg);
4268 assert(reg);
4269 return g_strdup_printf("CPUID.%02XH:%s",
4270 f->cpuid.eax, reg);
4271 }
4272 case MSR_FEATURE_WORD:
4273 return g_strdup_printf("MSR(%02XH)",
4274 f->msr.index);
4275 }
4276
4277 return NULL;
4278 }
4279
4280 static bool x86_cpu_have_filtered_features(X86CPU *cpu)
4281 {
4282 FeatureWord w;
4283
4284 for (w = 0; w < FEATURE_WORDS; w++) {
4285 if (cpu->filtered_features[w]) {
4286 return true;
4287 }
4288 }
4289
4290 return false;
4291 }
4292
4293 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
4294 const char *verbose_prefix)
4295 {
4296 CPUX86State *env = &cpu->env;
4297 FeatureWordInfo *f = &feature_word_info[w];
4298 int i;
4299
4300 if (!cpu->force_features) {
4301 env->features[w] &= ~mask;
4302 }
4303 cpu->filtered_features[w] |= mask;
4304
4305 if (!verbose_prefix) {
4306 return;
4307 }
4308
4309 for (i = 0; i < 64; ++i) {
4310 if ((1ULL << i) & mask) {
4311 g_autofree char *feat_word_str = feature_word_description(f, i);
4312 warn_report("%s: %s%s%s [bit %d]",
4313 verbose_prefix,
4314 feat_word_str,
4315 f->feat_names[i] ? "." : "",
4316 f->feat_names[i] ? f->feat_names[i] : "", i);
4317 }
4318 }
4319 }
4320
4321 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4322 const char *name, void *opaque,
4323 Error **errp)
4324 {
4325 X86CPU *cpu = X86_CPU(obj);
4326 CPUX86State *env = &cpu->env;
4327 int64_t value;
4328
4329 value = (env->cpuid_version >> 8) & 0xf;
4330 if (value == 0xf) {
4331 value += (env->cpuid_version >> 20) & 0xff;
4332 }
4333 visit_type_int(v, name, &value, errp);
4334 }
4335
4336 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4337 const char *name, void *opaque,
4338 Error **errp)
4339 {
4340 X86CPU *cpu = X86_CPU(obj);
4341 CPUX86State *env = &cpu->env;
4342 const int64_t min = 0;
4343 const int64_t max = 0xff + 0xf;
4344 Error *local_err = NULL;
4345 int64_t value;
4346
4347 visit_type_int(v, name, &value, &local_err);
4348 if (local_err) {
4349 error_propagate(errp, local_err);
4350 return;
4351 }
4352 if (value < min || value > max) {
4353 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4354 name ? name : "null", value, min, max);
4355 return;
4356 }
4357
4358 env->cpuid_version &= ~0xff00f00;
4359 if (value > 0x0f) {
4360 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
4361 } else {
4362 env->cpuid_version |= value << 8;
4363 }
4364 }
4365
4366 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4367 const char *name, void *opaque,
4368 Error **errp)
4369 {
4370 X86CPU *cpu = X86_CPU(obj);
4371 CPUX86State *env = &cpu->env;
4372 int64_t value;
4373
4374 value = (env->cpuid_version >> 4) & 0xf;
4375 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
4376 visit_type_int(v, name, &value, errp);
4377 }
4378
4379 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4380 const char *name, void *opaque,
4381 Error **errp)
4382 {
4383 X86CPU *cpu = X86_CPU(obj);
4384 CPUX86State *env = &cpu->env;
4385 const int64_t min = 0;
4386 const int64_t max = 0xff;
4387 Error *local_err = NULL;
4388 int64_t value;
4389
4390 visit_type_int(v, name, &value, &local_err);
4391 if (local_err) {
4392 error_propagate(errp, local_err);
4393 return;
4394 }
4395 if (value < min || value > max) {
4396 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4397 name ? name : "null", value, min, max);
4398 return;
4399 }
4400
4401 env->cpuid_version &= ~0xf00f0;
4402 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
4403 }
4404
4405 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
4406 const char *name, void *opaque,
4407 Error **errp)
4408 {
4409 X86CPU *cpu = X86_CPU(obj);
4410 CPUX86State *env = &cpu->env;
4411 int64_t value;
4412
4413 value = env->cpuid_version & 0xf;
4414 visit_type_int(v, name, &value, errp);
4415 }
4416
4417 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
4418 const char *name, void *opaque,
4419 Error **errp)
4420 {
4421 X86CPU *cpu = X86_CPU(obj);
4422 CPUX86State *env = &cpu->env;
4423 const int64_t min = 0;
4424 const int64_t max = 0xf;
4425 Error *local_err = NULL;
4426 int64_t value;
4427
4428 visit_type_int(v, name, &value, &local_err);
4429 if (local_err) {
4430 error_propagate(errp, local_err);
4431 return;
4432 }
4433 if (value < min || value > max) {
4434 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4435 name ? name : "null", value, min, max);
4436 return;
4437 }
4438
4439 env->cpuid_version &= ~0xf;
4440 env->cpuid_version |= value & 0xf;
4441 }
4442
4443 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4444 {
4445 X86CPU *cpu = X86_CPU(obj);
4446 CPUX86State *env = &cpu->env;
4447 char *value;
4448
4449 value = g_malloc(CPUID_VENDOR_SZ + 1);
4450 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4451 env->cpuid_vendor3);
4452 return value;
4453 }
4454
4455 static void x86_cpuid_set_vendor(Object *obj, const char *value,
4456 Error **errp)
4457 {
4458 X86CPU *cpu = X86_CPU(obj);
4459 CPUX86State *env = &cpu->env;
4460 int i;
4461
4462 if (strlen(value) != CPUID_VENDOR_SZ) {
4463 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
4464 return;
4465 }
4466
4467 env->cpuid_vendor1 = 0;
4468 env->cpuid_vendor2 = 0;
4469 env->cpuid_vendor3 = 0;
4470 for (i = 0; i < 4; i++) {
4471 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4472 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4473 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4474 }
4475 }
4476
4477 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4478 {
4479 X86CPU *cpu = X86_CPU(obj);
4480 CPUX86State *env = &cpu->env;
4481 char *value;
4482 int i;
4483
4484 value = g_malloc(48 + 1);
4485 for (i = 0; i < 48; i++) {
4486 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4487 }
4488 value[48] = '\0';
4489 return value;
4490 }
4491
4492 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4493 Error **errp)
4494 {
4495 X86CPU *cpu = X86_CPU(obj);
4496 CPUX86State *env = &cpu->env;
4497 int c, len, i;
4498
4499 if (model_id == NULL) {
4500 model_id = "";
4501 }
4502 len = strlen(model_id);
4503 memset(env->cpuid_model, 0, 48);
4504 for (i = 0; i < 48; i++) {
4505 if (i >= len) {
4506 c = '\0';
4507 } else {
4508 c = (uint8_t)model_id[i];
4509 }
4510 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4511 }
4512 }
4513
4514 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4515 void *opaque, Error **errp)
4516 {
4517 X86CPU *cpu = X86_CPU(obj);
4518 int64_t value;
4519
4520 value = cpu->env.tsc_khz * 1000;
4521 visit_type_int(v, name, &value, errp);
4522 }
4523
4524 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4525 void *opaque, Error **errp)
4526 {
4527 X86CPU *cpu = X86_CPU(obj);
4528 const int64_t min = 0;
4529 const int64_t max = INT64_MAX;
4530 Error *local_err = NULL;
4531 int64_t value;
4532
4533 visit_type_int(v, name, &value, &local_err);
4534 if (local_err) {
4535 error_propagate(errp, local_err);
4536 return;
4537 }
4538 if (value < min || value > max) {
4539 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4540 name ? name : "null", value, min, max);
4541 return;
4542 }
4543
4544 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
4545 }
4546
4547 /* Generic getter for "feature-words" and "filtered-features" properties */
4548 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4549 const char *name, void *opaque,
4550 Error **errp)
4551 {
4552 uint64_t *array = (uint64_t *)opaque;
4553 FeatureWord w;
4554 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4555 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4556 X86CPUFeatureWordInfoList *list = NULL;
4557
4558 for (w = 0; w < FEATURE_WORDS; w++) {
4559 FeatureWordInfo *wi = &feature_word_info[w];
4560 /*
4561 * We didn't have MSR features when "feature-words" was
4562 * introduced. Therefore skipped other type entries.
4563 */
4564 if (wi->type != CPUID_FEATURE_WORD) {
4565 continue;
4566 }
4567 X86CPUFeatureWordInfo *qwi = &word_infos[w];
4568 qwi->cpuid_input_eax = wi->cpuid.eax;
4569 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4570 qwi->cpuid_input_ecx = wi->cpuid.ecx;
4571 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
4572 qwi->features = array[w];
4573
4574 /* List will be in reverse order, but order shouldn't matter */
4575 list_entries[w].next = list;
4576 list_entries[w].value = &word_infos[w];
4577 list = &list_entries[w];
4578 }
4579
4580 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
4581 }
4582
4583 /* Convert all '_' in a feature string option name to '-', to make feature
4584 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4585 */
4586 static inline void feat2prop(char *s)
4587 {
4588 while ((s = strchr(s, '_'))) {
4589 *s = '-';
4590 }
4591 }
4592
4593 /* Return the feature property name for a feature flag bit */
4594 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4595 {
4596 const char *name;
4597 /* XSAVE components are automatically enabled by other features,
4598 * so return the original feature name instead
4599 */
4600 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4601 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4602
4603 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4604 x86_ext_save_areas[comp].bits) {
4605 w = x86_ext_save_areas[comp].feature;
4606 bitnr = ctz32(x86_ext_save_areas[comp].bits);
4607 }
4608 }
4609
4610 assert(bitnr < 64);
4611 assert(w < FEATURE_WORDS);
4612 name = feature_word_info[w].feat_names[bitnr];
4613 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4614 return name;
4615 }
4616
4617 /* Compatibily hack to maintain legacy +-feat semantic,
4618 * where +-feat overwrites any feature set by
4619 * feat=on|feat even if the later is parsed after +-feat
4620 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4621 */
4622 static GList *plus_features, *minus_features;
4623
4624 static gint compare_string(gconstpointer a, gconstpointer b)
4625 {
4626 return g_strcmp0(a, b);
4627 }
4628
4629 /* Parse "+feature,-feature,feature=foo" CPU feature string
4630 */
4631 static void x86_cpu_parse_featurestr(const char *typename, char *features,
4632 Error **errp)
4633 {
4634 char *featurestr; /* Single 'key=value" string being parsed */
4635 static bool cpu_globals_initialized;
4636 bool ambiguous = false;
4637
4638 if (cpu_globals_initialized) {
4639 return;
4640 }
4641 cpu_globals_initialized = true;
4642
4643 if (!features) {
4644 return;
4645 }
4646
4647 for (featurestr = strtok(features, ",");
4648 featurestr;
4649 featurestr = strtok(NULL, ",")) {
4650 const char *name;
4651 const char *val = NULL;
4652 char *eq = NULL;
4653 char num[32];
4654 GlobalProperty *prop;
4655
4656 /* Compatibility syntax: */
4657 if (featurestr[0] == '+') {
4658 plus_features = g_list_append(plus_features,
4659 g_strdup(featurestr + 1));
4660 continue;
4661 } else if (featurestr[0] == '-') {
4662 minus_features = g_list_append(minus_features,
4663 g_strdup(featurestr + 1));
4664 continue;
4665 }
4666
4667 eq = strchr(featurestr, '=');
4668 if (eq) {
4669 *eq++ = 0;
4670 val = eq;
4671 } else {
4672 val = "on";
4673 }
4674
4675 feat2prop(featurestr);
4676 name = featurestr;
4677
4678 if (g_list_find_custom(plus_features, name, compare_string)) {
4679 warn_report("Ambiguous CPU model string. "
4680 "Don't mix both \"+%s\" and \"%s=%s\"",
4681 name, name, val);
4682 ambiguous = true;
4683 }
4684 if (g_list_find_custom(minus_features, name, compare_string)) {
4685 warn_report("Ambiguous CPU model string. "
4686 "Don't mix both \"-%s\" and \"%s=%s\"",
4687 name, name, val);
4688 ambiguous = true;
4689 }
4690
4691 /* Special case: */
4692 if (!strcmp(name, "tsc-freq")) {
4693 int ret;
4694 uint64_t tsc_freq;
4695
4696 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
4697 if (ret < 0 || tsc_freq > INT64_MAX) {
4698 error_setg(errp, "bad numerical value %s", val);
4699 return;
4700 }
4701 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4702 val = num;
4703 name = "tsc-frequency";
4704 }
4705
4706 prop = g_new0(typeof(*prop), 1);
4707 prop->driver = typename;
4708 prop->property = g_strdup(name);
4709 prop->value = g_strdup(val);
4710 qdev_prop_register_global(prop);
4711 }
4712
4713 if (ambiguous) {
4714 warn_report("Compatibility of ambiguous CPU model "
4715 "strings won't be kept on future QEMU versions");
4716 }
4717 }
4718
4719 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
4720 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
4721
4722 /* Build a list with the name of all features on a feature word array */
4723 static void x86_cpu_list_feature_names(FeatureWordArray features,
4724 strList **feat_names)
4725 {
4726 FeatureWord w;
4727 strList **next = feat_names;
4728
4729 for (w = 0; w < FEATURE_WORDS; w++) {
4730 uint64_t filtered = features[w];
4731 int i;
4732 for (i = 0; i < 64; i++) {
4733 if (filtered & (1ULL << i)) {
4734 strList *new = g_new0(strList, 1);
4735 new->value = g_strdup(x86_cpu_feature_name(w, i));
4736 *next = new;
4737 next = &new->next;
4738 }
4739 }
4740 }
4741 }
4742
4743 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4744 const char *name, void *opaque,
4745 Error **errp)
4746 {
4747 X86CPU *xc = X86_CPU(obj);
4748 strList *result = NULL;
4749
4750 x86_cpu_list_feature_names(xc->filtered_features, &result);
4751 visit_type_strList(v, "unavailable-features", &result, errp);
4752 }
4753
4754 /* Check for missing features that may prevent the CPU class from
4755 * running using the current machine and accelerator.
4756 */
4757 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
4758 strList **missing_feats)
4759 {
4760 X86CPU *xc;
4761 Error *err = NULL;
4762 strList **next = missing_feats;
4763
4764 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
4765 strList *new = g_new0(strList, 1);
4766 new->value = g_strdup("kvm");
4767 *missing_feats = new;
4768 return;
4769 }
4770
4771 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
4772
4773 x86_cpu_expand_features(xc, &err);
4774 if (err) {
4775 /* Errors at x86_cpu_expand_features should never happen,
4776 * but in case it does, just report the model as not
4777 * runnable at all using the "type" property.
4778 */
4779 strList *new = g_new0(strList, 1);
4780 new->value = g_strdup("type");
4781 *next = new;
4782 next = &new->next;
4783 }
4784
4785 x86_cpu_filter_features(xc, false);
4786
4787 x86_cpu_list_feature_names(xc->filtered_features, next);
4788
4789 object_unref(OBJECT(xc));
4790 }
4791
4792 /* Print all cpuid feature names in featureset
4793 */
4794 static void listflags(GList *features)
4795 {
4796 size_t len = 0;
4797 GList *tmp;
4798
4799 for (tmp = features; tmp; tmp = tmp->next) {
4800 const char *name = tmp->data;
4801 if ((len + strlen(name) + 1) >= 75) {
4802 qemu_printf("\n");
4803 len = 0;
4804 }
4805 qemu_printf("%s%s", len == 0 ? " " : " ", name);
4806 len += strlen(name) + 1;
4807 }
4808 qemu_printf("\n");
4809 }
4810
4811 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
4812 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4813 {
4814 ObjectClass *class_a = (ObjectClass *)a;
4815 ObjectClass *class_b = (ObjectClass *)b;
4816 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4817 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
4818 int ret;
4819
4820 if (cc_a->ordering != cc_b->ordering) {
4821 ret = cc_a->ordering - cc_b->ordering;
4822 } else {
4823 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4824 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
4825 ret = strcmp(name_a, name_b);
4826 }
4827 return ret;
4828 }
4829
4830 static GSList *get_sorted_cpu_model_list(void)
4831 {
4832 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4833 list = g_slist_sort(list, x86_cpu_list_compare);
4834 return list;
4835 }
4836
4837 static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4838 {
4839 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
4840 char *r = object_property_get_str(obj, "model-id", &error_abort);
4841 object_unref(obj);
4842 return r;
4843 }
4844
4845 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4846 {
4847 X86CPUVersion version;
4848
4849 if (!cc->model || !cc->model->is_alias) {
4850 return NULL;
4851 }
4852 version = x86_cpu_model_resolve_version(cc->model);
4853 if (version <= 0) {
4854 return NULL;
4855 }
4856 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4857 }
4858
4859 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4860 {
4861 ObjectClass *oc = data;
4862 X86CPUClass *cc = X86_CPU_CLASS(oc);
4863 g_autofree char *name = x86_cpu_class_get_model_name(cc);
4864 g_autofree char *desc = g_strdup(cc->model_description);
4865 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
4866 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
4867
4868 if (!desc && alias_of) {
4869 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4870 desc = g_strdup("(alias configured by machine type)");
4871 } else {
4872 desc = g_strdup_printf("(alias of %s)", alias_of);
4873 }
4874 }
4875 if (!desc && cc->model && cc->model->note) {
4876 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4877 }
4878 if (!desc) {
4879 desc = g_strdup_printf("%s", model_id);
4880 }
4881
4882 qemu_printf("x86 %-20s %-58s\n", name, desc);
4883 }
4884
4885 /* list available CPU models and flags */
4886 void x86_cpu_list(void)
4887 {
4888 int i, j;
4889 GSList *list;
4890 GList *names = NULL;
4891
4892 qemu_printf("Available CPUs:\n");
4893 list = get_sorted_cpu_model_list();
4894 g_slist_foreach(list, x86_cpu_list_entry, NULL);
4895 g_slist_free(list);
4896
4897 names = NULL;
4898 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4899 FeatureWordInfo *fw = &feature_word_info[i];
4900 for (j = 0; j < 64; j++) {
4901 if (fw->feat_names[j]) {
4902 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4903 }
4904 }
4905 }
4906
4907 names = g_list_sort(names, (GCompareFunc)strcmp);
4908
4909 qemu_printf("\nRecognized CPUID flags:\n");
4910 listflags(names);
4911 qemu_printf("\n");
4912 g_list_free(names);
4913 }
4914
4915 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4916 {
4917 ObjectClass *oc = data;
4918 X86CPUClass *cc = X86_CPU_CLASS(oc);
4919 CpuDefinitionInfoList **cpu_list = user_data;
4920 CpuDefinitionInfoList *entry;
4921 CpuDefinitionInfo *info;
4922
4923 info = g_malloc0(sizeof(*info));
4924 info->name = x86_cpu_class_get_model_name(cc);
4925 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4926 info->has_unavailable_features = true;
4927 info->q_typename = g_strdup(object_class_get_name(oc));
4928 info->migration_safe = cc->migration_safe;
4929 info->has_migration_safe = true;
4930 info->q_static = cc->static_model;
4931 /*
4932 * Old machine types won't report aliases, so that alias translation
4933 * doesn't break compatibility with previous QEMU versions.
4934 */
4935 if (default_cpu_version != CPU_VERSION_LEGACY) {
4936 info->alias_of = x86_cpu_class_get_alias_of(cc);
4937 info->has_alias_of = !!info->alias_of;
4938 }
4939
4940 entry = g_malloc0(sizeof(*entry));
4941 entry->value = info;
4942 entry->next = *cpu_list;
4943 *cpu_list = entry;
4944 }
4945
4946 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
4947 {
4948 CpuDefinitionInfoList *cpu_list = NULL;
4949 GSList *list = get_sorted_cpu_model_list();
4950 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
4951 g_slist_free(list);
4952 return cpu_list;
4953 }
4954
4955 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
4956 bool migratable_only)
4957 {
4958 FeatureWordInfo *wi = &feature_word_info[w];
4959 uint64_t r = 0;
4960
4961 if (kvm_enabled()) {
4962 switch (wi->type) {
4963 case CPUID_FEATURE_WORD:
4964 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
4965 wi->cpuid.ecx,
4966 wi->cpuid.reg);
4967 break;
4968 case MSR_FEATURE_WORD:
4969 r = kvm_arch_get_supported_msr_feature(kvm_state,
4970 wi->msr.index);
4971 break;
4972 }
4973 } else if (hvf_enabled()) {
4974 if (wi->type != CPUID_FEATURE_WORD) {
4975 return 0;
4976 }
4977 r = hvf_get_supported_cpuid(wi->cpuid.eax,
4978 wi->cpuid.ecx,
4979 wi->cpuid.reg);
4980 } else if (tcg_enabled()) {
4981 r = wi->tcg_features;
4982 } else {
4983 return ~0;
4984 }
4985 if (migratable_only) {
4986 r &= x86_cpu_get_migratable_flags(w);
4987 }
4988 return r;
4989 }
4990
4991 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
4992 {
4993 PropValue *pv;
4994 for (pv = props; pv->prop; pv++) {
4995 if (!pv->value) {
4996 continue;
4997 }
4998 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
4999 &error_abort);
5000 }
5001 }
5002
5003 /* Apply properties for the CPU model version specified in model */
5004 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5005 {
5006 const X86CPUVersionDefinition *vdef;
5007 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5008
5009 if (version == CPU_VERSION_LEGACY) {
5010 return;
5011 }
5012
5013 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5014 PropValue *p;
5015
5016 for (p = vdef->props; p && p->prop; p++) {
5017 object_property_parse(OBJECT(cpu), p->value, p->prop,
5018 &error_abort);
5019 }
5020
5021 if (vdef->version == version) {
5022 break;
5023 }
5024 }
5025
5026 /*
5027 * If we reached the end of the list, version number was invalid
5028 */
5029 assert(vdef->version == version);
5030 }
5031
5032 /* Load data from X86CPUDefinition into a X86CPU object
5033 */
5034 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model, Error **errp)
5035 {
5036 X86CPUDefinition *def = model->cpudef;
5037 CPUX86State *env = &cpu->env;
5038 const char *vendor;
5039 char host_vendor[CPUID_VENDOR_SZ + 1];
5040 FeatureWord w;
5041
5042 /*NOTE: any property set by this function should be returned by
5043 * x86_cpu_static_props(), so static expansion of
5044 * query-cpu-model-expansion is always complete.
5045 */
5046
5047 /* CPU models only set _minimum_ values for level/xlevel: */
5048 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
5049 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
5050
5051 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
5052 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
5053 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
5054 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
5055 for (w = 0; w < FEATURE_WORDS; w++) {
5056 env->features[w] = def->features[w];
5057 }
5058
5059 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5060 cpu->legacy_cache = !def->cache_info;
5061
5062 /* Special cases not set in the X86CPUDefinition structs: */
5063 /* TODO: in-kernel irqchip for hvf */
5064 if (kvm_enabled()) {
5065 if (!kvm_irqchip_in_kernel()) {
5066 x86_cpu_change_kvm_default("x2apic", "off");
5067 }
5068
5069 x86_cpu_apply_props(cpu, kvm_default_props);
5070 } else if (tcg_enabled()) {
5071 x86_cpu_apply_props(cpu, tcg_default_props);
5072 }
5073
5074 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
5075
5076 /* sysenter isn't supported in compatibility mode on AMD,
5077 * syscall isn't supported in compatibility mode on Intel.
5078 * Normally we advertise the actual CPU vendor, but you can
5079 * override this using the 'vendor' property if you want to use
5080 * KVM's sysenter/syscall emulation in compatibility mode and
5081 * when doing cross vendor migration
5082 */
5083 vendor = def->vendor;
5084 if (accel_uses_host_cpuid()) {
5085 uint32_t ebx = 0, ecx = 0, edx = 0;
5086 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
5087 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
5088 vendor = host_vendor;
5089 }
5090
5091 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
5092
5093 x86_cpu_apply_version_props(cpu, model);
5094 }
5095
5096 #ifndef CONFIG_USER_ONLY
5097 /* Return a QDict containing keys for all properties that can be included
5098 * in static expansion of CPU models. All properties set by x86_cpu_load_model()
5099 * must be included in the dictionary.
5100 */
5101 static QDict *x86_cpu_static_props(void)
5102 {
5103 FeatureWord w;
5104 int i;
5105 static const char *props[] = {
5106 "min-level",
5107 "min-xlevel",
5108 "family",
5109 "model",
5110 "stepping",
5111 "model-id",
5112 "vendor",
5113 "lmce",
5114 NULL,
5115 };
5116 static QDict *d;
5117
5118 if (d) {
5119 return d;
5120 }
5121
5122 d = qdict_new();
5123 for (i = 0; props[i]; i++) {
5124 qdict_put_null(d, props[i]);
5125 }
5126
5127 for (w = 0; w < FEATURE_WORDS; w++) {
5128 FeatureWordInfo *fi = &feature_word_info[w];
5129 int bit;
5130 for (bit = 0; bit < 64; bit++) {
5131 if (!fi->feat_names[bit]) {
5132 continue;
5133 }
5134 qdict_put_null(d, fi->feat_names[bit]);
5135 }
5136 }
5137
5138 return d;
5139 }
5140
5141 /* Add an entry to @props dict, with the value for property. */
5142 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
5143 {
5144 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
5145 &error_abort);
5146
5147 qdict_put_obj(props, prop, value);
5148 }
5149
5150 /* Convert CPU model data from X86CPU object to a property dictionary
5151 * that can recreate exactly the same CPU model.
5152 */
5153 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
5154 {
5155 QDict *sprops = x86_cpu_static_props();
5156 const QDictEntry *e;
5157
5158 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
5159 const char *prop = qdict_entry_key(e);
5160 x86_cpu_expand_prop(cpu, props, prop);
5161 }
5162 }
5163
5164 /* Convert CPU model data from X86CPU object to a property dictionary
5165 * that can recreate exactly the same CPU model, including every
5166 * writeable QOM property.
5167 */
5168 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
5169 {
5170 ObjectPropertyIterator iter;
5171 ObjectProperty *prop;
5172
5173 object_property_iter_init(&iter, OBJECT(cpu));
5174 while ((prop = object_property_iter_next(&iter))) {
5175 /* skip read-only or write-only properties */
5176 if (!prop->get || !prop->set) {
5177 continue;
5178 }
5179
5180 /* "hotplugged" is the only property that is configurable
5181 * on the command-line but will be set differently on CPUs
5182 * created using "-cpu ... -smp ..." and by CPUs created
5183 * on the fly by x86_cpu_from_model() for querying. Skip it.
5184 */
5185 if (!strcmp(prop->name, "hotplugged")) {
5186 continue;
5187 }
5188 x86_cpu_expand_prop(cpu, props, prop->name);
5189 }
5190 }
5191
5192 static void object_apply_props(Object *obj, QDict *props, Error **errp)
5193 {
5194 const QDictEntry *prop;
5195 Error *err = NULL;
5196
5197 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
5198 object_property_set_qobject(obj, qdict_entry_value(prop),
5199 qdict_entry_key(prop), &err);
5200 if (err) {
5201 break;
5202 }
5203 }
5204
5205 error_propagate(errp, err);
5206 }
5207
5208 /* Create X86CPU object according to model+props specification */
5209 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
5210 {
5211 X86CPU *xc = NULL;
5212 X86CPUClass *xcc;
5213 Error *err = NULL;
5214
5215 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
5216 if (xcc == NULL) {
5217 error_setg(&err, "CPU model '%s' not found", model);
5218 goto out;
5219 }
5220
5221 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
5222 if (props) {
5223 object_apply_props(OBJECT(xc), props, &err);
5224 if (err) {
5225 goto out;
5226 }
5227 }
5228
5229 x86_cpu_expand_features(xc, &err);
5230 if (err) {
5231 goto out;
5232 }
5233
5234 out:
5235 if (err) {
5236 error_propagate(errp, err);
5237 object_unref(OBJECT(xc));
5238 xc = NULL;
5239 }
5240 return xc;
5241 }
5242
5243 CpuModelExpansionInfo *
5244 qmp_query_cpu_model_expansion(CpuModelExpansionType type,
5245 CpuModelInfo *model,
5246 Error **errp)
5247 {
5248 X86CPU *xc = NULL;
5249 Error *err = NULL;
5250 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
5251 QDict *props = NULL;
5252 const char *base_name;
5253
5254 xc = x86_cpu_from_model(model->name,
5255 model->has_props ?
5256 qobject_to(QDict, model->props) :
5257 NULL, &err);
5258 if (err) {
5259 goto out;
5260 }
5261
5262 props = qdict_new();
5263 ret->model = g_new0(CpuModelInfo, 1);
5264 ret->model->props = QOBJECT(props);
5265 ret->model->has_props = true;
5266
5267 switch (type) {
5268 case CPU_MODEL_EXPANSION_TYPE_STATIC:
5269 /* Static expansion will be based on "base" only */
5270 base_name = "base";
5271 x86_cpu_to_dict(xc, props);
5272 break;
5273 case CPU_MODEL_EXPANSION_TYPE_FULL:
5274 /* As we don't return every single property, full expansion needs
5275 * to keep the original model name+props, and add extra
5276 * properties on top of that.
5277 */
5278 base_name = model->name;
5279 x86_cpu_to_dict_full(xc, props);
5280 break;
5281 default:
5282 error_setg(&err, "Unsupported expansion type");
5283 goto out;
5284 }
5285
5286 x86_cpu_to_dict(xc, props);
5287
5288 ret->model->name = g_strdup(base_name);
5289
5290 out:
5291 object_unref(OBJECT(xc));
5292 if (err) {
5293 error_propagate(errp, err);
5294 qapi_free_CpuModelExpansionInfo(ret);
5295 ret = NULL;
5296 }
5297 return ret;
5298 }
5299 #endif /* !CONFIG_USER_ONLY */
5300
5301 static gchar *x86_gdb_arch_name(CPUState *cs)
5302 {
5303 #ifdef TARGET_X86_64
5304 return g_strdup("i386:x86-64");
5305 #else
5306 return g_strdup("i386");
5307 #endif
5308 }
5309
5310 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5311 {
5312 X86CPUModel *model = data;
5313 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5314
5315 xcc->model = model;
5316 xcc->migration_safe = true;
5317 }
5318
5319 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
5320 {
5321 g_autofree char *typename = x86_cpu_type_name(name);
5322 TypeInfo ti = {
5323 .name = typename,
5324 .parent = TYPE_X86_CPU,
5325 .class_init = x86_cpu_cpudef_class_init,
5326 .class_data = model,
5327 };
5328
5329 type_register(&ti);
5330 }
5331
5332 static void x86_register_cpudef_types(X86CPUDefinition *def)
5333 {
5334 X86CPUModel *m;
5335 const X86CPUVersionDefinition *vdef;
5336
5337 /* AMD aliases are handled at runtime based on CPUID vendor, so
5338 * they shouldn't be set on the CPU model table.
5339 */
5340 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
5341 /* catch mistakes instead of silently truncating model_id when too long */
5342 assert(def->model_id && strlen(def->model_id) <= 48);
5343
5344 /* Unversioned model: */
5345 m = g_new0(X86CPUModel, 1);
5346 m->cpudef = def;
5347 m->version = CPU_VERSION_AUTO;
5348 m->is_alias = true;
5349 x86_register_cpu_model_type(def->name, m);
5350
5351 /* Versioned models: */
5352
5353 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5354 X86CPUModel *m = g_new0(X86CPUModel, 1);
5355 g_autofree char *name =
5356 x86_cpu_versioned_model_name(def, vdef->version);
5357 m->cpudef = def;
5358 m->version = vdef->version;
5359 m->note = vdef->note;
5360 x86_register_cpu_model_type(name, m);
5361
5362 if (vdef->alias) {
5363 X86CPUModel *am = g_new0(X86CPUModel, 1);
5364 am->cpudef = def;
5365 am->version = vdef->version;
5366 am->is_alias = true;
5367 x86_register_cpu_model_type(vdef->alias, am);
5368 }
5369 }
5370
5371 }
5372
5373 #if !defined(CONFIG_USER_ONLY)
5374
5375 void cpu_clear_apic_feature(CPUX86State *env)
5376 {
5377 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
5378 }
5379
5380 #endif /* !CONFIG_USER_ONLY */
5381
5382 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5383 uint32_t *eax, uint32_t *ebx,
5384 uint32_t *ecx, uint32_t *edx)
5385 {
5386 X86CPU *cpu = env_archcpu(env);
5387 CPUState *cs = env_cpu(env);
5388 uint32_t die_offset;
5389 uint32_t limit;
5390 uint32_t signature[3];
5391
5392 /* Calculate & apply limits for different index ranges */
5393 if (index >= 0xC0000000) {
5394 limit = env->cpuid_xlevel2;
5395 } else if (index >= 0x80000000) {
5396 limit = env->cpuid_xlevel;
5397 } else if (index >= 0x40000000) {
5398 limit = 0x40000001;
5399 } else {
5400 limit = env->cpuid_level;
5401 }
5402
5403 if (index > limit) {
5404 /* Intel documentation states that invalid EAX input will
5405 * return the same information as EAX=cpuid_level
5406 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5407 */
5408 index = env->cpuid_level;
5409 }
5410
5411 switch(index) {
5412 case 0:
5413 *eax = env->cpuid_level;
5414 *ebx = env->cpuid_vendor1;
5415 *edx = env->cpuid_vendor2;
5416 *ecx = env->cpuid_vendor3;
5417 break;
5418 case 1:
5419 *eax = env->cpuid_version;
5420 *ebx = (cpu->apic_id << 24) |
5421 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
5422 *ecx = env->features[FEAT_1_ECX];
5423 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5424 *ecx |= CPUID_EXT_OSXSAVE;
5425 }
5426 *edx = env->features[FEAT_1_EDX];
5427 if (cs->nr_cores * cs->nr_threads > 1) {
5428 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
5429 *edx |= CPUID_HT;
5430 }
5431 break;
5432 case 2:
5433 /* cache info: needed for Pentium Pro compatibility */
5434 if (cpu->cache_info_passthrough) {
5435 host_cpuid(index, 0, eax, ebx, ecx, edx);
5436 break;
5437 }
5438 *eax = 1; /* Number of CPUID[EAX=2] calls required */
5439 *ebx = 0;
5440 if (!cpu->enable_l3_cache) {
5441 *ecx = 0;
5442 } else {
5443 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
5444 }
5445 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5446 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5447 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
5448 break;
5449 case 4:
5450 /* cache info: needed for Core compatibility */
5451 if (cpu->cache_info_passthrough) {
5452 host_cpuid(index, count, eax, ebx, ecx, edx);
5453 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
5454 *eax &= ~0xFC000000;
5455 if ((*eax & 31) && cs->nr_cores > 1) {
5456 *eax |= (cs->nr_cores - 1) << 26;
5457 }
5458 } else {
5459 *eax = 0;
5460 switch (count) {
5461 case 0: /* L1 dcache info */
5462 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5463 1, cs->nr_cores,
5464 eax, ebx, ecx, edx);
5465 break;
5466 case 1: /* L1 icache info */
5467 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5468 1, cs->nr_cores,
5469 eax, ebx, ecx, edx);
5470 break;
5471 case 2: /* L2 cache info */
5472 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5473 cs->nr_threads, cs->nr_cores,
5474 eax, ebx, ecx, edx);
5475 break;
5476 case 3: /* L3 cache info */
5477 die_offset = apicid_die_offset(env->nr_dies,
5478 cs->nr_cores, cs->nr_threads);
5479 if (cpu->enable_l3_cache) {
5480 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
5481 (1 << die_offset), cs->nr_cores,
5482 eax, ebx, ecx, edx);
5483 break;
5484 }
5485 /* fall through */
5486 default: /* end of info */
5487 *eax = *ebx = *ecx = *edx = 0;
5488 break;
5489 }
5490 }
5491 break;
5492 case 5:
5493 /* MONITOR/MWAIT Leaf */
5494 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5495 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5496 *ecx = cpu->mwait.ecx; /* flags */
5497 *edx = cpu->mwait.edx; /* mwait substates */
5498 break;
5499 case 6:
5500 /* Thermal and Power Leaf */
5501 *eax = env->features[FEAT_6_EAX];
5502 *ebx = 0;
5503 *ecx = 0;
5504 *edx = 0;
5505 break;
5506 case 7:
5507 /* Structured Extended Feature Flags Enumeration Leaf */
5508 if (count == 0) {
5509 /* Maximum ECX value for sub-leaves */
5510 *eax = env->cpuid_level_func7;
5511 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
5512 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
5513 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5514 *ecx |= CPUID_7_0_ECX_OSPKE;
5515 }
5516 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
5517 } else if (count == 1) {
5518 *eax = env->features[FEAT_7_1_EAX];
5519 *ebx = 0;
5520 *ecx = 0;
5521 *edx = 0;
5522 } else {
5523 *eax = 0;
5524 *ebx = 0;
5525 *ecx = 0;
5526 *edx = 0;
5527 }
5528 break;
5529 case 9:
5530 /* Direct Cache Access Information Leaf */
5531 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5532 *ebx = 0;
5533 *ecx = 0;
5534 *edx = 0;
5535 break;
5536 case 0xA:
5537 /* Architectural Performance Monitoring Leaf */
5538 if (kvm_enabled() && cpu->enable_pmu) {
5539 KVMState *s = cs->kvm_state;
5540
5541 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5542 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5543 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5544 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
5545 } else if (hvf_enabled() && cpu->enable_pmu) {
5546 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5547 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5548 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5549 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
5550 } else {
5551 *eax = 0;
5552 *ebx = 0;
5553 *ecx = 0;
5554 *edx = 0;
5555 }
5556 break;
5557 case 0xB:
5558 /* Extended Topology Enumeration Leaf */
5559 if (!cpu->enable_cpuid_0xb) {
5560 *eax = *ebx = *ecx = *edx = 0;
5561 break;
5562 }
5563
5564 *ecx = count & 0xff;
5565 *edx = cpu->apic_id;
5566
5567 switch (count) {
5568 case 0:
5569 *eax = apicid_core_offset(env->nr_dies,
5570 cs->nr_cores, cs->nr_threads);
5571 *ebx = cs->nr_threads;
5572 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5573 break;
5574 case 1:
5575 *eax = apicid_pkg_offset(env->nr_dies,
5576 cs->nr_cores, cs->nr_threads);
5577 *ebx = cs->nr_cores * cs->nr_threads;
5578 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5579 break;
5580 default:
5581 *eax = 0;
5582 *ebx = 0;
5583 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5584 }
5585
5586 assert(!(*eax & ~0x1f));
5587 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5588 break;
5589 case 0x1F:
5590 /* V2 Extended Topology Enumeration Leaf */
5591 if (env->nr_dies < 2) {
5592 *eax = *ebx = *ecx = *edx = 0;
5593 break;
5594 }
5595
5596 *ecx = count & 0xff;
5597 *edx = cpu->apic_id;
5598 switch (count) {
5599 case 0:
5600 *eax = apicid_core_offset(env->nr_dies, cs->nr_cores,
5601 cs->nr_threads);
5602 *ebx = cs->nr_threads;
5603 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5604 break;
5605 case 1:
5606 *eax = apicid_die_offset(env->nr_dies, cs->nr_cores,
5607 cs->nr_threads);
5608 *ebx = cs->nr_cores * cs->nr_threads;
5609 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5610 break;
5611 case 2:
5612 *eax = apicid_pkg_offset(env->nr_dies, cs->nr_cores,
5613 cs->nr_threads);
5614 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5615 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5616 break;
5617 default:
5618 *eax = 0;
5619 *ebx = 0;
5620 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5621 }
5622 assert(!(*eax & ~0x1f));
5623 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5624 break;
5625 case 0xD: {
5626 /* Processor Extended State */
5627 *eax = 0;
5628 *ebx = 0;
5629 *ecx = 0;
5630 *edx = 0;
5631 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
5632 break;
5633 }
5634
5635 if (count == 0) {
5636 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5637 *eax = env->features[FEAT_XSAVE_COMP_LO];
5638 *edx = env->features[FEAT_XSAVE_COMP_HI];
5639 /*
5640 * The initial value of xcr0 and ebx == 0, On host without kvm
5641 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5642 * even through guest update xcr0, this will crash some legacy guest
5643 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5644 */
5645 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
5646 } else if (count == 1) {
5647 *eax = env->features[FEAT_XSAVE];
5648 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
5649 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5650 const ExtSaveArea *esa = &x86_ext_save_areas[count];
5651 *eax = esa->size;
5652 *ebx = esa->offset;
5653 }
5654 }
5655 break;
5656 }
5657 case 0x14: {
5658 /* Intel Processor Trace Enumeration */
5659 *eax = 0;
5660 *ebx = 0;
5661 *ecx = 0;
5662 *edx = 0;
5663 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5664 !kvm_enabled()) {
5665 break;
5666 }
5667
5668 if (count == 0) {
5669 *eax = INTEL_PT_MAX_SUBLEAF;
5670 *ebx = INTEL_PT_MINIMAL_EBX;
5671 *ecx = INTEL_PT_MINIMAL_ECX;
5672 } else if (count == 1) {
5673 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5674 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5675 }
5676 break;
5677 }
5678 case 0x40000000:
5679 /*
5680 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5681 * set here, but we restrict to TCG none the less.
5682 */
5683 if (tcg_enabled() && cpu->expose_tcg) {
5684 memcpy(signature, "TCGTCGTCGTCG", 12);
5685 *eax = 0x40000001;
5686 *ebx = signature[0];
5687 *ecx = signature[1];
5688 *edx = signature[2];
5689 } else {
5690 *eax = 0;
5691 *ebx = 0;
5692 *ecx = 0;
5693 *edx = 0;
5694 }
5695 break;
5696 case 0x40000001:
5697 *eax = 0;
5698 *ebx = 0;
5699 *ecx = 0;
5700 *edx = 0;
5701 break;
5702 case 0x80000000:
5703 *eax = env->cpuid_xlevel;
5704 *ebx = env->cpuid_vendor1;
5705 *edx = env->cpuid_vendor2;
5706 *ecx = env->cpuid_vendor3;
5707 break;
5708 case 0x80000001:
5709 *eax = env->cpuid_version;
5710 *ebx = 0;
5711 *ecx = env->features[FEAT_8000_0001_ECX];
5712 *edx = env->features[FEAT_8000_0001_EDX];
5713
5714 /* The Linux kernel checks for the CMPLegacy bit and
5715 * discards multiple thread information if it is set.
5716 * So don't set it here for Intel to make Linux guests happy.
5717 */
5718 if (cs->nr_cores * cs->nr_threads > 1) {
5719 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5720 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5721 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
5722 *ecx |= 1 << 1; /* CmpLegacy bit */
5723 }
5724 }
5725 break;
5726 case 0x80000002:
5727 case 0x80000003:
5728 case 0x80000004:
5729 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5730 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5731 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5732 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5733 break;
5734 case 0x80000005:
5735 /* cache info (L1 cache) */
5736 if (cpu->cache_info_passthrough) {
5737 host_cpuid(index, 0, eax, ebx, ecx, edx);
5738 break;
5739 }
5740 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
5741 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
5742 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
5743 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
5744 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5745 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
5746 break;
5747 case 0x80000006:
5748 /* cache info (L2 cache) */
5749 if (cpu->cache_info_passthrough) {
5750 host_cpuid(index, 0, eax, ebx, ecx, edx);
5751 break;
5752 }
5753 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
5754 (L2_DTLB_2M_ENTRIES << 16) | \
5755 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
5756 (L2_ITLB_2M_ENTRIES);
5757 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
5758 (L2_DTLB_4K_ENTRIES << 16) | \
5759 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
5760 (L2_ITLB_4K_ENTRIES);
5761 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5762 cpu->enable_l3_cache ?
5763 env->cache_info_amd.l3_cache : NULL,
5764 ecx, edx);
5765 break;
5766 case 0x80000007:
5767 *eax = 0;
5768 *ebx = 0;
5769 *ecx = 0;
5770 *edx = env->features[FEAT_8000_0007_EDX];
5771 break;
5772 case 0x80000008:
5773 /* virtual & phys address size in low 2 bytes. */
5774 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
5775 /* 64 bit processor */
5776 *eax = cpu->phys_bits; /* configurable physical bits */
5777 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5778 *eax |= 0x00003900; /* 57 bits virtual */
5779 } else {
5780 *eax |= 0x00003000; /* 48 bits virtual */
5781 }
5782 } else {
5783 *eax = cpu->phys_bits;
5784 }
5785 *ebx = env->features[FEAT_8000_0008_EBX];
5786 *ecx = 0;
5787 *edx = 0;
5788 if (cs->nr_cores * cs->nr_threads > 1) {
5789 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
5790 }
5791 break;
5792 case 0x8000000A:
5793 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5794 *eax = 0x00000001; /* SVM Revision */
5795 *ebx = 0x00000010; /* nr of ASIDs */
5796 *ecx = 0;
5797 *edx = env->features[FEAT_SVM]; /* optional features */
5798 } else {
5799 *eax = 0;
5800 *ebx = 0;
5801 *ecx = 0;
5802 *edx = 0;
5803 }
5804 break;
5805 case 0x8000001D:
5806 *eax = 0;
5807 if (cpu->cache_info_passthrough) {
5808 host_cpuid(index, count, eax, ebx, ecx, edx);
5809 break;
5810 }
5811 switch (count) {
5812 case 0: /* L1 dcache info */
5813 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
5814 eax, ebx, ecx, edx);
5815 break;
5816 case 1: /* L1 icache info */
5817 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
5818 eax, ebx, ecx, edx);
5819 break;
5820 case 2: /* L2 cache info */
5821 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
5822 eax, ebx, ecx, edx);
5823 break;
5824 case 3: /* L3 cache info */
5825 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
5826 eax, ebx, ecx, edx);
5827 break;
5828 default: /* end of info */
5829 *eax = *ebx = *ecx = *edx = 0;
5830 break;
5831 }
5832 break;
5833 case 0x8000001E:
5834 assert(cpu->core_id <= 255);
5835 encode_topo_cpuid8000001e(cs, cpu,
5836 eax, ebx, ecx, edx);
5837 break;
5838 case 0xC0000000:
5839 *eax = env->cpuid_xlevel2;
5840 *ebx = 0;
5841 *ecx = 0;
5842 *edx = 0;
5843 break;
5844 case 0xC0000001:
5845 /* Support for VIA CPU's CPUID instruction */
5846 *eax = env->cpuid_version;
5847 *ebx = 0;
5848 *ecx = 0;
5849 *edx = env->features[FEAT_C000_0001_EDX];
5850 break;
5851 case 0xC0000002:
5852 case 0xC0000003:
5853 case 0xC0000004:
5854 /* Reserved for the future, and now filled with zero */
5855 *eax = 0;
5856 *ebx = 0;
5857 *ecx = 0;
5858 *edx = 0;
5859 break;
5860 case 0x8000001F:
5861 *eax = sev_enabled() ? 0x2 : 0;
5862 *ebx = sev_get_cbit_position();
5863 *ebx |= sev_get_reduced_phys_bits() << 6;
5864 *ecx = 0;
5865 *edx = 0;
5866 break;
5867 default:
5868 /* reserved values: zero */
5869 *eax = 0;
5870 *ebx = 0;
5871 *ecx = 0;
5872 *edx = 0;
5873 break;
5874 }
5875 }
5876
5877 /* CPUClass::reset() */
5878 static void x86_cpu_reset(CPUState *s)
5879 {
5880 X86CPU *cpu = X86_CPU(s);
5881 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5882 CPUX86State *env = &cpu->env;
5883 target_ulong cr4;
5884 uint64_t xcr0;
5885 int i;
5886
5887 xcc->parent_reset(s);
5888
5889 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
5890
5891 env->old_exception = -1;
5892
5893 /* init to reset state */
5894
5895 env->hflags2 |= HF2_GIF_MASK;
5896
5897 cpu_x86_update_cr0(env, 0x60000010);
5898 env->a20_mask = ~0x0;
5899 env->smbase = 0x30000;
5900 env->msr_smi_count = 0;
5901
5902 env->idt.limit = 0xffff;
5903 env->gdt.limit = 0xffff;
5904 env->ldt.limit = 0xffff;
5905 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
5906 env->tr.limit = 0xffff;
5907 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
5908
5909 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
5910 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
5911 DESC_R_MASK | DESC_A_MASK);
5912 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
5913 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5914 DESC_A_MASK);
5915 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
5916 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5917 DESC_A_MASK);
5918 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
5919 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5920 DESC_A_MASK);
5921 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
5922 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5923 DESC_A_MASK);
5924 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
5925 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5926 DESC_A_MASK);
5927
5928 env->eip = 0xfff0;
5929 env->regs[R_EDX] = env->cpuid_version;
5930
5931 env->eflags = 0x2;
5932
5933 /* FPU init */
5934 for (i = 0; i < 8; i++) {
5935 env->fptags[i] = 1;
5936 }
5937 cpu_set_fpuc(env, 0x37f);
5938
5939 env->mxcsr = 0x1f80;
5940 /* All units are in INIT state. */
5941 env->xstate_bv = 0;
5942
5943 env->pat = 0x0007040600070406ULL;
5944 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
5945 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
5946 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
5947 }
5948
5949 memset(env->dr, 0, sizeof(env->dr));
5950 env->dr[6] = DR6_FIXED_1;
5951 env->dr[7] = DR7_FIXED_1;
5952 cpu_breakpoint_remove_all(s, BP_CPU);
5953 cpu_watchpoint_remove_all(s, BP_CPU);
5954
5955 cr4 = 0;
5956 xcr0 = XSTATE_FP_MASK;
5957
5958 #ifdef CONFIG_USER_ONLY
5959 /* Enable all the features for user-mode. */
5960 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
5961 xcr0 |= XSTATE_SSE_MASK;
5962 }
5963 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
5964 const ExtSaveArea *esa = &x86_ext_save_areas[i];
5965 if (env->features[esa->feature] & esa->bits) {
5966 xcr0 |= 1ull << i;
5967 }
5968 }
5969
5970 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
5971 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
5972 }
5973 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
5974 cr4 |= CR4_FSGSBASE_MASK;
5975 }
5976 #endif
5977
5978 env->xcr0 = xcr0;
5979 cpu_x86_update_cr4(env, cr4);
5980
5981 /*
5982 * SDM 11.11.5 requires:
5983 * - IA32_MTRR_DEF_TYPE MSR.E = 0
5984 * - IA32_MTRR_PHYSMASKn.V = 0
5985 * All other bits are undefined. For simplification, zero it all.
5986 */
5987 env->mtrr_deftype = 0;
5988 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
5989 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
5990
5991 env->interrupt_injected = -1;
5992 env->exception_nr = -1;
5993 env->exception_pending = 0;
5994 env->exception_injected = 0;
5995 env->exception_has_payload = false;
5996 env->exception_payload = 0;
5997 env->nmi_injected = false;
5998 #if !defined(CONFIG_USER_ONLY)
5999 /* We hard-wire the BSP to the first CPU. */
6000 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
6001
6002 s->halted = !cpu_is_bsp(cpu);
6003
6004 if (kvm_enabled()) {
6005 kvm_arch_reset_vcpu(cpu);
6006 }
6007 else if (hvf_enabled()) {
6008 hvf_reset_vcpu(s);
6009 }
6010 #endif
6011 }
6012
6013 #ifndef CONFIG_USER_ONLY
6014 bool cpu_is_bsp(X86CPU *cpu)
6015 {
6016 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
6017 }
6018
6019 /* TODO: remove me, when reset over QOM tree is implemented */
6020 static void x86_cpu_machine_reset_cb(void *opaque)
6021 {
6022 X86CPU *cpu = opaque;
6023 cpu_reset(CPU(cpu));
6024 }
6025 #endif
6026
6027 static void mce_init(X86CPU *cpu)
6028 {
6029 CPUX86State *cenv = &cpu->env;
6030 unsigned int bank;
6031
6032 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
6033 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
6034 (CPUID_MCE | CPUID_MCA)) {
6035 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
6036 (cpu->enable_lmce ? MCG_LMCE_P : 0);
6037 cenv->mcg_ctl = ~(uint64_t)0;
6038 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
6039 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
6040 }
6041 }
6042 }
6043
6044 #ifndef CONFIG_USER_ONLY
6045 APICCommonClass *apic_get_class(void)
6046 {
6047 const char *apic_type = "apic";
6048
6049 /* TODO: in-kernel irqchip for hvf */
6050 if (kvm_apic_in_kernel()) {
6051 apic_type = "kvm-apic";
6052 } else if (xen_enabled()) {
6053 apic_type = "xen-apic";
6054 }
6055
6056 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
6057 }
6058
6059 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
6060 {
6061 APICCommonState *apic;
6062 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
6063
6064 cpu->apic_state = DEVICE(object_new_with_class(apic_class));
6065
6066 object_property_add_child(OBJECT(cpu), "lapic",
6067 OBJECT(cpu->apic_state), &error_abort);
6068 object_unref(OBJECT(cpu->apic_state));
6069
6070 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
6071 /* TODO: convert to link<> */
6072 apic = APIC_COMMON(cpu->apic_state);
6073 apic->cpu = cpu;
6074 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
6075 }
6076
6077 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6078 {
6079 APICCommonState *apic;
6080 static bool apic_mmio_map_once;
6081
6082 if (cpu->apic_state == NULL) {
6083 return;
6084 }
6085 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
6086 errp);
6087
6088 /* Map APIC MMIO area */
6089 apic = APIC_COMMON(cpu->apic_state);
6090 if (!apic_mmio_map_once) {
6091 memory_region_add_subregion_overlap(get_system_memory(),
6092 apic->apicbase &
6093 MSR_IA32_APICBASE_BASE,
6094 &apic->io_memory,
6095 0x1000);
6096 apic_mmio_map_once = true;
6097 }
6098 }
6099
6100 static void x86_cpu_machine_done(Notifier *n, void *unused)
6101 {
6102 X86CPU *cpu = container_of(n, X86CPU, machine_done);
6103 MemoryRegion *smram =
6104 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
6105
6106 if (smram) {
6107 cpu->smram = g_new(MemoryRegion, 1);
6108 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
6109 smram, 0, 1ull << 32);
6110 memory_region_set_enabled(cpu->smram, true);
6111 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
6112 }
6113 }
6114 #else
6115 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6116 {
6117 }
6118 #endif
6119
6120 /* Note: Only safe for use on x86(-64) hosts */
6121 static uint32_t x86_host_phys_bits(void)
6122 {
6123 uint32_t eax;
6124 uint32_t host_phys_bits;
6125
6126 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
6127 if (eax >= 0x80000008) {
6128 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
6129 /* Note: According to AMD doc 25481 rev 2.34 they have a field
6130 * at 23:16 that can specify a maximum physical address bits for
6131 * the guest that can override this value; but I've not seen
6132 * anything with that set.
6133 */
6134 host_phys_bits = eax & 0xff;
6135 } else {
6136 /* It's an odd 64 bit machine that doesn't have the leaf for
6137 * physical address bits; fall back to 36 that's most older
6138 * Intel.
6139 */
6140 host_phys_bits = 36;
6141 }
6142
6143 return host_phys_bits;
6144 }
6145
6146 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
6147 {
6148 if (*min < value) {
6149 *min = value;
6150 }
6151 }
6152
6153 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6154 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
6155 {
6156 CPUX86State *env = &cpu->env;
6157 FeatureWordInfo *fi = &feature_word_info[w];
6158 uint32_t eax = fi->cpuid.eax;
6159 uint32_t region = eax & 0xF0000000;
6160
6161 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
6162 if (!env->features[w]) {
6163 return;
6164 }
6165
6166 switch (region) {
6167 case 0x00000000:
6168 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
6169 break;
6170 case 0x80000000:
6171 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
6172 break;
6173 case 0xC0000000:
6174 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
6175 break;
6176 }
6177
6178 if (eax == 7) {
6179 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
6180 fi->cpuid.ecx);
6181 }
6182 }
6183
6184 /* Calculate XSAVE components based on the configured CPU feature flags */
6185 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
6186 {
6187 CPUX86State *env = &cpu->env;
6188 int i;
6189 uint64_t mask;
6190
6191 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
6192 return;
6193 }
6194
6195 mask = 0;
6196 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6197 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6198 if (env->features[esa->feature] & esa->bits) {
6199 mask |= (1ULL << i);
6200 }
6201 }
6202
6203 env->features[FEAT_XSAVE_COMP_LO] = mask;
6204 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
6205 }
6206
6207 /***** Steps involved on loading and filtering CPUID data
6208 *
6209 * When initializing and realizing a CPU object, the steps
6210 * involved in setting up CPUID data are:
6211 *
6212 * 1) Loading CPU model definition (X86CPUDefinition). This is
6213 * implemented by x86_cpu_load_model() and should be completely
6214 * transparent, as it is done automatically by instance_init.
6215 * No code should need to look at X86CPUDefinition structs
6216 * outside instance_init.
6217 *
6218 * 2) CPU expansion. This is done by realize before CPUID
6219 * filtering, and will make sure host/accelerator data is
6220 * loaded for CPU models that depend on host capabilities
6221 * (e.g. "host"). Done by x86_cpu_expand_features().
6222 *
6223 * 3) CPUID filtering. This initializes extra data related to
6224 * CPUID, and checks if the host supports all capabilities
6225 * required by the CPU. Runnability of a CPU model is
6226 * determined at this step. Done by x86_cpu_filter_features().
6227 *
6228 * Some operations don't require all steps to be performed.
6229 * More precisely:
6230 *
6231 * - CPU instance creation (instance_init) will run only CPU
6232 * model loading. CPU expansion can't run at instance_init-time
6233 * because host/accelerator data may be not available yet.
6234 * - CPU realization will perform both CPU model expansion and CPUID
6235 * filtering, and return an error in case one of them fails.
6236 * - query-cpu-definitions needs to run all 3 steps. It needs
6237 * to run CPUID filtering, as the 'unavailable-features'
6238 * field is set based on the filtering results.
6239 * - The query-cpu-model-expansion QMP command only needs to run
6240 * CPU model loading and CPU expansion. It should not filter
6241 * any CPUID data based on host capabilities.
6242 */
6243
6244 /* Expand CPU configuration data, based on configured features
6245 * and host/accelerator capabilities when appropriate.
6246 */
6247 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
6248 {
6249 CPUX86State *env = &cpu->env;
6250 FeatureWord w;
6251 int i;
6252 GList *l;
6253 Error *local_err = NULL;
6254
6255 for (l = plus_features; l; l = l->next) {
6256 const char *prop = l->data;
6257 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
6258 if (local_err) {
6259 goto out;
6260 }
6261 }
6262
6263 for (l = minus_features; l; l = l->next) {
6264 const char *prop = l->data;
6265 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
6266 if (local_err) {
6267 goto out;
6268 }
6269 }
6270
6271 /*TODO: Now cpu->max_features doesn't overwrite features
6272 * set using QOM properties, and we can convert
6273 * plus_features & minus_features to global properties
6274 * inside x86_cpu_parse_featurestr() too.
6275 */
6276 if (cpu->max_features) {
6277 for (w = 0; w < FEATURE_WORDS; w++) {
6278 /* Override only features that weren't set explicitly
6279 * by the user.
6280 */
6281 env->features[w] |=
6282 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
6283 ~env->user_features[w] & \
6284 ~feature_word_info[w].no_autoenable_flags;
6285 }
6286 }
6287
6288 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6289 FeatureDep *d = &feature_dependencies[i];
6290 if (!(env->features[d->from.index] & d->from.mask)) {
6291 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
6292
6293 /* Not an error unless the dependent feature was added explicitly. */
6294 mark_unavailable_features(cpu, d->to.index,
6295 unavailable_features & env->user_features[d->to.index],
6296 "This feature depends on other features that were not requested");
6297
6298 env->user_features[d->to.index] |= unavailable_features;
6299 env->features[d->to.index] &= ~unavailable_features;
6300 }
6301 }
6302
6303 if (!kvm_enabled() || !cpu->expose_kvm) {
6304 env->features[FEAT_KVM] = 0;
6305 }
6306
6307 x86_cpu_enable_xsave_components(cpu);
6308
6309 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6310 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6311 if (cpu->full_cpuid_auto_level) {
6312 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6313 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6314 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6315 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
6316 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
6317 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6318 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6319 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
6320 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
6321 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6322 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6323 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
6324
6325 /* Intel Processor Trace requires CPUID[0x14] */
6326 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6327 kvm_enabled() && cpu->intel_pt_auto_level) {
6328 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6329 }
6330
6331 /* CPU topology with multi-dies support requires CPUID[0x1F] */
6332 if (env->nr_dies > 1) {
6333 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6334 }
6335
6336 /* SVM requires CPUID[0x8000000A] */
6337 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6338 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6339 }
6340
6341 /* SEV requires CPUID[0x8000001F] */
6342 if (sev_enabled()) {
6343 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6344 }
6345 }
6346
6347 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
6348 if (env->cpuid_level_func7 == UINT32_MAX) {
6349 env->cpuid_level_func7 = env->cpuid_min_level_func7;
6350 }
6351 if (env->cpuid_level == UINT32_MAX) {
6352 env->cpuid_level = env->cpuid_min_level;
6353 }
6354 if (env->cpuid_xlevel == UINT32_MAX) {
6355 env->cpuid_xlevel = env->cpuid_min_xlevel;
6356 }
6357 if (env->cpuid_xlevel2 == UINT32_MAX) {
6358 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
6359 }
6360
6361 out:
6362 if (local_err != NULL) {
6363 error_propagate(errp, local_err);
6364 }
6365 }
6366
6367 /*
6368 * Finishes initialization of CPUID data, filters CPU feature
6369 * words based on host availability of each feature.
6370 *
6371 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6372 */
6373 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
6374 {
6375 CPUX86State *env = &cpu->env;
6376 FeatureWord w;
6377 const char *prefix = NULL;
6378
6379 if (verbose) {
6380 prefix = accel_uses_host_cpuid()
6381 ? "host doesn't support requested feature"
6382 : "TCG doesn't support requested feature";
6383 }
6384
6385 for (w = 0; w < FEATURE_WORDS; w++) {
6386 uint64_t host_feat =
6387 x86_cpu_get_supported_feature_word(w, false);
6388 uint64_t requested_features = env->features[w];
6389 uint64_t unavailable_features = requested_features & ~host_feat;
6390 mark_unavailable_features(cpu, w, unavailable_features, prefix);
6391 }
6392
6393 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6394 kvm_enabled()) {
6395 KVMState *s = CPU(cpu)->kvm_state;
6396 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6397 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6398 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6399 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6400 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6401
6402 if (!eax_0 ||
6403 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6404 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6405 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6406 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6407 INTEL_PT_ADDR_RANGES_NUM) ||
6408 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
6409 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
6410 (ecx_0 & INTEL_PT_IP_LIP)) {
6411 /*
6412 * Processor Trace capabilities aren't configurable, so if the
6413 * host can't emulate the capabilities we report on
6414 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6415 */
6416 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
6417 }
6418 }
6419 }
6420
6421 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6422 {
6423 CPUState *cs = CPU(dev);
6424 X86CPU *cpu = X86_CPU(dev);
6425 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6426 CPUX86State *env = &cpu->env;
6427 Error *local_err = NULL;
6428 static bool ht_warned;
6429
6430 if (xcc->host_cpuid_required) {
6431 if (!accel_uses_host_cpuid()) {
6432 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6433 error_setg(&local_err, "CPU model '%s' requires KVM", name);
6434 goto out;
6435 }
6436 }
6437
6438 if (cpu->max_features && accel_uses_host_cpuid()) {
6439 if (enable_cpu_pm) {
6440 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
6441 &cpu->mwait.ecx, &cpu->mwait.edx);
6442 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
6443 }
6444 if (kvm_enabled() && cpu->ucode_rev == 0) {
6445 cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,
6446 MSR_IA32_UCODE_REV);
6447 }
6448 }
6449
6450 if (cpu->ucode_rev == 0) {
6451 /* The default is the same as KVM's. */
6452 if (IS_AMD_CPU(env)) {
6453 cpu->ucode_rev = 0x01000065;
6454 } else {
6455 cpu->ucode_rev = 0x100000000ULL;
6456 }
6457 }
6458
6459 /* mwait extended info: needed for Core compatibility */
6460 /* We always wake on interrupt even if host does not have the capability */
6461 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6462
6463 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6464 error_setg(errp, "apic-id property was not initialized properly");
6465 return;
6466 }
6467
6468 x86_cpu_expand_features(cpu, &local_err);
6469 if (local_err) {
6470 goto out;
6471 }
6472
6473 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6474
6475 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6476 error_setg(&local_err,
6477 accel_uses_host_cpuid() ?
6478 "Host doesn't support requested features" :
6479 "TCG doesn't support requested features");
6480 goto out;
6481 }
6482
6483 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6484 * CPUID[1].EDX.
6485 */
6486 if (IS_AMD_CPU(env)) {
6487 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6488 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
6489 & CPUID_EXT2_AMD_ALIASES);
6490 }
6491
6492 /* For 64bit systems think about the number of physical bits to present.
6493 * ideally this should be the same as the host; anything other than matching
6494 * the host can cause incorrect guest behaviour.
6495 * QEMU used to pick the magic value of 40 bits that corresponds to
6496 * consumer AMD devices but nothing else.
6497 */
6498 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6499 if (accel_uses_host_cpuid()) {
6500 uint32_t host_phys_bits = x86_host_phys_bits();
6501 static bool warned;
6502
6503 /* Print a warning if the user set it to a value that's not the
6504 * host value.
6505 */
6506 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
6507 !warned) {
6508 warn_report("Host physical bits (%u)"
6509 " does not match phys-bits property (%u)",
6510 host_phys_bits, cpu->phys_bits);
6511 warned = true;
6512 }
6513
6514 if (cpu->host_phys_bits) {
6515 /* The user asked for us to use the host physical bits */
6516 cpu->phys_bits = host_phys_bits;
6517 if (cpu->host_phys_bits_limit &&
6518 cpu->phys_bits > cpu->host_phys_bits_limit) {
6519 cpu->phys_bits = cpu->host_phys_bits_limit;
6520 }
6521 }
6522
6523 if (cpu->phys_bits &&
6524 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6525 cpu->phys_bits < 32)) {
6526 error_setg(errp, "phys-bits should be between 32 and %u "
6527 " (but is %u)",
6528 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6529 return;
6530 }
6531 } else {
6532 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
6533 error_setg(errp, "TCG only supports phys-bits=%u",
6534 TCG_PHYS_ADDR_BITS);
6535 return;
6536 }
6537 }
6538 /* 0 means it was not explicitly set by the user (or by machine
6539 * compat_props or by the host code above). In this case, the default
6540 * is the value used by TCG (40).
6541 */
6542 if (cpu->phys_bits == 0) {
6543 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6544 }
6545 } else {
6546 /* For 32 bit systems don't use the user set value, but keep
6547 * phys_bits consistent with what we tell the guest.
6548 */
6549 if (cpu->phys_bits != 0) {
6550 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6551 return;
6552 }
6553
6554 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6555 cpu->phys_bits = 36;
6556 } else {
6557 cpu->phys_bits = 32;
6558 }
6559 }
6560
6561 /* Cache information initialization */
6562 if (!cpu->legacy_cache) {
6563 if (!xcc->model || !xcc->model->cpudef->cache_info) {
6564 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6565 error_setg(errp,
6566 "CPU model '%s' doesn't support legacy-cache=off", name);
6567 return;
6568 }
6569 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
6570 *xcc->model->cpudef->cache_info;
6571 } else {
6572 /* Build legacy cache information */
6573 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6574 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6575 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6576 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6577
6578 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6579 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6580 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6581 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6582
6583 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6584 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6585 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6586 env->cache_info_amd.l3_cache = &legacy_l3_cache;
6587 }
6588
6589
6590 cpu_exec_realizefn(cs, &local_err);
6591 if (local_err != NULL) {
6592 error_propagate(errp, local_err);
6593 return;
6594 }
6595
6596 #ifndef CONFIG_USER_ONLY
6597 MachineState *ms = MACHINE(qdev_get_machine());
6598 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
6599
6600 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
6601 x86_cpu_apic_create(cpu, &local_err);
6602 if (local_err != NULL) {
6603 goto out;
6604 }
6605 }
6606 #endif
6607
6608 mce_init(cpu);
6609
6610 #ifndef CONFIG_USER_ONLY
6611 if (tcg_enabled()) {
6612 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
6613 cpu->cpu_as_root = g_new(MemoryRegion, 1);
6614
6615 /* Outer container... */
6616 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
6617 memory_region_set_enabled(cpu->cpu_as_root, true);
6618
6619 /* ... with two regions inside: normal system memory with low
6620 * priority, and...
6621 */
6622 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
6623 get_system_memory(), 0, ~0ull);
6624 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
6625 memory_region_set_enabled(cpu->cpu_as_mem, true);
6626
6627 cs->num_ases = 2;
6628 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
6629 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
6630
6631 /* ... SMRAM with higher priority, linked from /machine/smram. */
6632 cpu->machine_done.notify = x86_cpu_machine_done;
6633 qemu_add_machine_init_done_notifier(&cpu->machine_done);
6634 }
6635 #endif
6636
6637 qemu_init_vcpu(cs);
6638
6639 /*
6640 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6641 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6642 * based on inputs (sockets,cores,threads), it is still better to give
6643 * users a warning.
6644 *
6645 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6646 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6647 */
6648 if (IS_AMD_CPU(env) &&
6649 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6650 cs->nr_threads > 1 && !ht_warned) {
6651 warn_report("This family of AMD CPU doesn't support "
6652 "hyperthreading(%d)",
6653 cs->nr_threads);
6654 error_printf("Please configure -smp options properly"
6655 " or try enabling topoext feature.\n");
6656 ht_warned = true;
6657 }
6658
6659 x86_cpu_apic_realize(cpu, &local_err);
6660 if (local_err != NULL) {
6661 goto out;
6662 }
6663 cpu_reset(cs);
6664
6665 xcc->parent_realize(dev, &local_err);
6666
6667 out:
6668 if (local_err != NULL) {
6669 error_propagate(errp, local_err);
6670 return;
6671 }
6672 }
6673
6674 static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
6675 {
6676 X86CPU *cpu = X86_CPU(dev);
6677 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6678 Error *local_err = NULL;
6679
6680 #ifndef CONFIG_USER_ONLY
6681 cpu_remove_sync(CPU(dev));
6682 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6683 #endif
6684
6685 if (cpu->apic_state) {
6686 object_unparent(OBJECT(cpu->apic_state));
6687 cpu->apic_state = NULL;
6688 }
6689
6690 xcc->parent_unrealize(dev, &local_err);
6691 if (local_err != NULL) {
6692 error_propagate(errp, local_err);
6693 return;
6694 }
6695 }
6696
6697 typedef struct BitProperty {
6698 FeatureWord w;
6699 uint64_t mask;
6700 } BitProperty;
6701
6702 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6703 void *opaque, Error **errp)
6704 {
6705 X86CPU *cpu = X86_CPU(obj);
6706 BitProperty *fp = opaque;
6707 uint64_t f = cpu->env.features[fp->w];
6708 bool value = (f & fp->mask) == fp->mask;
6709 visit_type_bool(v, name, &value, errp);
6710 }
6711
6712 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6713 void *opaque, Error **errp)
6714 {
6715 DeviceState *dev = DEVICE(obj);
6716 X86CPU *cpu = X86_CPU(obj);
6717 BitProperty *fp = opaque;
6718 Error *local_err = NULL;
6719 bool value;
6720
6721 if (dev->realized) {
6722 qdev_prop_set_after_realize(dev, name, errp);
6723 return;
6724 }
6725
6726 visit_type_bool(v, name, &value, &local_err);
6727 if (local_err) {
6728 error_propagate(errp, local_err);
6729 return;
6730 }
6731
6732 if (value) {
6733 cpu->env.features[fp->w] |= fp->mask;
6734 } else {
6735 cpu->env.features[fp->w] &= ~fp->mask;
6736 }
6737 cpu->env.user_features[fp->w] |= fp->mask;
6738 }
6739
6740 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
6741 void *opaque)
6742 {
6743 BitProperty *prop = opaque;
6744 g_free(prop);
6745 }
6746
6747 /* Register a boolean property to get/set a single bit in a uint32_t field.
6748 *
6749 * The same property name can be registered multiple times to make it affect
6750 * multiple bits in the same FeatureWord. In that case, the getter will return
6751 * true only if all bits are set.
6752 */
6753 static void x86_cpu_register_bit_prop(X86CPU *cpu,
6754 const char *prop_name,
6755 FeatureWord w,
6756 int bitnr)
6757 {
6758 BitProperty *fp;
6759 ObjectProperty *op;
6760 uint64_t mask = (1ULL << bitnr);
6761
6762 op = object_property_find(OBJECT(cpu), prop_name, NULL);
6763 if (op) {
6764 fp = op->opaque;
6765 assert(fp->w == w);
6766 fp->mask |= mask;
6767 } else {
6768 fp = g_new0(BitProperty, 1);
6769 fp->w = w;
6770 fp->mask = mask;
6771 object_property_add(OBJECT(cpu), prop_name, "bool",
6772 x86_cpu_get_bit_prop,
6773 x86_cpu_set_bit_prop,
6774 x86_cpu_release_bit_prop, fp, &error_abort);
6775 }
6776 }
6777
6778 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
6779 FeatureWord w,
6780 int bitnr)
6781 {
6782 FeatureWordInfo *fi = &feature_word_info[w];
6783 const char *name = fi->feat_names[bitnr];
6784
6785 if (!name) {
6786 return;
6787 }
6788
6789 /* Property names should use "-" instead of "_".
6790 * Old names containing underscores are registered as aliases
6791 * using object_property_add_alias()
6792 */
6793 assert(!strchr(name, '_'));
6794 /* aliases don't use "|" delimiters anymore, they are registered
6795 * manually using object_property_add_alias() */
6796 assert(!strchr(name, '|'));
6797 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
6798 }
6799
6800 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
6801 {
6802 X86CPU *cpu = X86_CPU(cs);
6803 CPUX86State *env = &cpu->env;
6804 GuestPanicInformation *panic_info = NULL;
6805
6806 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
6807 panic_info = g_malloc0(sizeof(GuestPanicInformation));
6808
6809 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
6810
6811 assert(HV_CRASH_PARAMS >= 5);
6812 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
6813 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
6814 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
6815 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
6816 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
6817 }
6818
6819 return panic_info;
6820 }
6821 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
6822 const char *name, void *opaque,
6823 Error **errp)
6824 {
6825 CPUState *cs = CPU(obj);
6826 GuestPanicInformation *panic_info;
6827
6828 if (!cs->crash_occurred) {
6829 error_setg(errp, "No crash occured");
6830 return;
6831 }
6832
6833 panic_info = x86_cpu_get_crash_info(cs);
6834 if (panic_info == NULL) {
6835 error_setg(errp, "No crash information");
6836 return;
6837 }
6838
6839 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
6840 errp);
6841 qapi_free_GuestPanicInformation(panic_info);
6842 }
6843
6844 static void x86_cpu_initfn(Object *obj)
6845 {
6846 X86CPU *cpu = X86_CPU(obj);
6847 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
6848 CPUX86State *env = &cpu->env;
6849 FeatureWord w;
6850
6851 env->nr_dies = 1;
6852 cpu_set_cpustate_pointers(cpu);
6853
6854 object_property_add(obj, "family", "int",
6855 x86_cpuid_version_get_family,
6856 x86_cpuid_version_set_family, NULL, NULL, NULL);
6857 object_property_add(obj, "model", "int",
6858 x86_cpuid_version_get_model,
6859 x86_cpuid_version_set_model, NULL, NULL, NULL);
6860 object_property_add(obj, "stepping", "int",
6861 x86_cpuid_version_get_stepping,
6862 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
6863 object_property_add_str(obj, "vendor",
6864 x86_cpuid_get_vendor,
6865 x86_cpuid_set_vendor, NULL);
6866 object_property_add_str(obj, "model-id",
6867 x86_cpuid_get_model_id,
6868 x86_cpuid_set_model_id, NULL);
6869 object_property_add(obj, "tsc-frequency", "int",
6870 x86_cpuid_get_tsc_freq,
6871 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
6872 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6873 x86_cpu_get_feature_words,
6874 NULL, NULL, (void *)env->features, NULL);
6875 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6876 x86_cpu_get_feature_words,
6877 NULL, NULL, (void *)cpu->filtered_features, NULL);
6878 /*
6879 * The "unavailable-features" property has the same semantics as
6880 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
6881 * QMP command: they list the features that would have prevented the
6882 * CPU from running if the "enforce" flag was set.
6883 */
6884 object_property_add(obj, "unavailable-features", "strList",
6885 x86_cpu_get_unavailable_features,
6886 NULL, NULL, NULL, &error_abort);
6887
6888 object_property_add(obj, "crash-information", "GuestPanicInformation",
6889 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
6890
6891 for (w = 0; w < FEATURE_WORDS; w++) {
6892 int bitnr;
6893
6894 for (bitnr = 0; bitnr < 64; bitnr++) {
6895 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
6896 }
6897 }
6898
6899 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
6900 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
6901 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
6902 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
6903 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
6904 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
6905 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
6906
6907 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
6908 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
6909 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
6910 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
6911 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
6912 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
6913 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
6914 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
6915 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
6916 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
6917 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
6918 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
6919 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
6920 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
6921 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control",
6922 &error_abort);
6923 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
6924 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
6925 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
6926 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
6927 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
6928 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
6929 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
6930
6931 if (xcc->model) {
6932 x86_cpu_load_model(cpu, xcc->model, &error_abort);
6933 }
6934 }
6935
6936 static int64_t x86_cpu_get_arch_id(CPUState *cs)
6937 {
6938 X86CPU *cpu = X86_CPU(cs);
6939
6940 return cpu->apic_id;
6941 }
6942
6943 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
6944 {
6945 X86CPU *cpu = X86_CPU(cs);
6946
6947 return cpu->env.cr[0] & CR0_PG_MASK;
6948 }
6949
6950 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
6951 {
6952 X86CPU *cpu = X86_CPU(cs);
6953
6954 cpu->env.eip = value;
6955 }
6956
6957 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
6958 {
6959 X86CPU *cpu = X86_CPU(cs);
6960
6961 cpu->env.eip = tb->pc - tb->cs_base;
6962 }
6963
6964 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
6965 {
6966 X86CPU *cpu = X86_CPU(cs);
6967 CPUX86State *env = &cpu->env;
6968
6969 #if !defined(CONFIG_USER_ONLY)
6970 if (interrupt_request & CPU_INTERRUPT_POLL) {
6971 return CPU_INTERRUPT_POLL;
6972 }
6973 #endif
6974 if (interrupt_request & CPU_INTERRUPT_SIPI) {
6975 return CPU_INTERRUPT_SIPI;
6976 }
6977
6978 if (env->hflags2 & HF2_GIF_MASK) {
6979 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
6980 !(env->hflags & HF_SMM_MASK)) {
6981 return CPU_INTERRUPT_SMI;
6982 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
6983 !(env->hflags2 & HF2_NMI_MASK)) {
6984 return CPU_INTERRUPT_NMI;
6985 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
6986 return CPU_INTERRUPT_MCE;
6987 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
6988 (((env->hflags2 & HF2_VINTR_MASK) &&
6989 (env->hflags2 & HF2_HIF_MASK)) ||
6990 (!(env->hflags2 & HF2_VINTR_MASK) &&
6991 (env->eflags & IF_MASK &&
6992 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
6993 return CPU_INTERRUPT_HARD;
6994 #if !defined(CONFIG_USER_ONLY)
6995 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
6996 (env->eflags & IF_MASK) &&
6997 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
6998 return CPU_INTERRUPT_VIRQ;
6999 #endif
7000 }
7001 }
7002
7003 return 0;
7004 }
7005
7006 static bool x86_cpu_has_work(CPUState *cs)
7007 {
7008 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
7009 }
7010
7011 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
7012 {
7013 X86CPU *cpu = X86_CPU(cs);
7014 CPUX86State *env = &cpu->env;
7015
7016 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
7017 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
7018 : bfd_mach_i386_i8086);
7019 info->print_insn = print_insn_i386;
7020
7021 info->cap_arch = CS_ARCH_X86;
7022 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
7023 : env->hflags & HF_CS32_MASK ? CS_MODE_32
7024 : CS_MODE_16);
7025 info->cap_insn_unit = 1;
7026 info->cap_insn_split = 8;
7027 }
7028
7029 void x86_update_hflags(CPUX86State *env)
7030 {
7031 uint32_t hflags;
7032 #define HFLAG_COPY_MASK \
7033 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7034 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7035 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7036 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7037
7038 hflags = env->hflags & HFLAG_COPY_MASK;
7039 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
7040 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
7041 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
7042 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
7043 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
7044
7045 if (env->cr[4] & CR4_OSFXSR_MASK) {
7046 hflags |= HF_OSFXSR_MASK;
7047 }
7048
7049 if (env->efer & MSR_EFER_LMA) {
7050 hflags |= HF_LMA_MASK;
7051 }
7052
7053 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
7054 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
7055 } else {
7056 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
7057 (DESC_B_SHIFT - HF_CS32_SHIFT);
7058 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
7059 (DESC_B_SHIFT - HF_SS32_SHIFT);
7060 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
7061 !(hflags & HF_CS32_MASK)) {
7062 hflags |= HF_ADDSEG_MASK;
7063 } else {
7064 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
7065 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
7066 }
7067 }
7068 env->hflags = hflags;
7069 }
7070
7071 static Property x86_cpu_properties[] = {
7072 #ifdef CONFIG_USER_ONLY
7073 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7074 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
7075 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
7076 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
7077 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
7078 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
7079 #else
7080 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
7081 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
7082 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
7083 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
7084 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
7085 #endif
7086 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
7087 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
7088
7089 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
7090 HYPERV_SPINLOCK_NEVER_RETRY),
7091 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
7092 HYPERV_FEAT_RELAXED, 0),
7093 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
7094 HYPERV_FEAT_VAPIC, 0),
7095 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
7096 HYPERV_FEAT_TIME, 0),
7097 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
7098 HYPERV_FEAT_CRASH, 0),
7099 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
7100 HYPERV_FEAT_RESET, 0),
7101 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
7102 HYPERV_FEAT_VPINDEX, 0),
7103 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
7104 HYPERV_FEAT_RUNTIME, 0),
7105 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
7106 HYPERV_FEAT_SYNIC, 0),
7107 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
7108 HYPERV_FEAT_STIMER, 0),
7109 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
7110 HYPERV_FEAT_FREQUENCIES, 0),
7111 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
7112 HYPERV_FEAT_REENLIGHTENMENT, 0),
7113 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
7114 HYPERV_FEAT_TLBFLUSH, 0),
7115 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
7116 HYPERV_FEAT_EVMCS, 0),
7117 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
7118 HYPERV_FEAT_IPI, 0),
7119 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
7120 HYPERV_FEAT_STIMER_DIRECT, 0),
7121 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
7122 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
7123 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
7124
7125 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
7126 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
7127 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
7128 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
7129 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
7130 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
7131 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
7132 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
7133 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
7134 UINT32_MAX),
7135 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
7136 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
7137 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
7138 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
7139 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
7140 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
7141 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
7142 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
7143 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
7144 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
7145 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
7146 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
7147 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
7148 false),
7149 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
7150 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
7151 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
7152 true),
7153 /*
7154 * lecacy_cache defaults to true unless the CPU model provides its
7155 * own cache information (see x86_cpu_load_def()).
7156 */
7157 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
7158
7159 /*
7160 * From "Requirements for Implementing the Microsoft
7161 * Hypervisor Interface":
7162 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7163 *
7164 * "Starting with Windows Server 2012 and Windows 8, if
7165 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7166 * the hypervisor imposes no specific limit to the number of VPs.
7167 * In this case, Windows Server 2012 guest VMs may use more than
7168 * 64 VPs, up to the maximum supported number of processors applicable
7169 * to the specific Windows version being used."
7170 */
7171 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
7172 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
7173 false),
7174 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
7175 true),
7176 DEFINE_PROP_END_OF_LIST()
7177 };
7178
7179 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
7180 {
7181 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7182 CPUClass *cc = CPU_CLASS(oc);
7183 DeviceClass *dc = DEVICE_CLASS(oc);
7184
7185 device_class_set_parent_realize(dc, x86_cpu_realizefn,
7186 &xcc->parent_realize);
7187 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
7188 &xcc->parent_unrealize);
7189 device_class_set_props(dc, x86_cpu_properties);
7190
7191 cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset);
7192 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
7193
7194 cc->class_by_name = x86_cpu_class_by_name;
7195 cc->parse_features = x86_cpu_parse_featurestr;
7196 cc->has_work = x86_cpu_has_work;
7197 #ifdef CONFIG_TCG
7198 cc->do_interrupt = x86_cpu_do_interrupt;
7199 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
7200 #endif
7201 cc->dump_state = x86_cpu_dump_state;
7202 cc->get_crash_info = x86_cpu_get_crash_info;
7203 cc->set_pc = x86_cpu_set_pc;
7204 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
7205 cc->gdb_read_register = x86_cpu_gdb_read_register;
7206 cc->gdb_write_register = x86_cpu_gdb_write_register;
7207 cc->get_arch_id = x86_cpu_get_arch_id;
7208 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7209 #ifndef CONFIG_USER_ONLY
7210 cc->asidx_from_attrs = x86_asidx_from_attrs;
7211 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
7212 cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
7213 cc->write_elf64_note = x86_cpu_write_elf64_note;
7214 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
7215 cc->write_elf32_note = x86_cpu_write_elf32_note;
7216 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
7217 cc->vmsd = &vmstate_x86_cpu;
7218 #endif
7219 cc->gdb_arch_name = x86_gdb_arch_name;
7220 #ifdef TARGET_X86_64
7221 cc->gdb_core_xml_file = "i386-64bit.xml";
7222 cc->gdb_num_core_regs = 66;
7223 #else
7224 cc->gdb_core_xml_file = "i386-32bit.xml";
7225 cc->gdb_num_core_regs = 50;
7226 #endif
7227 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
7228 cc->debug_excp_handler = breakpoint_handler;
7229 #endif
7230 cc->cpu_exec_enter = x86_cpu_exec_enter;
7231 cc->cpu_exec_exit = x86_cpu_exec_exit;
7232 #ifdef CONFIG_TCG
7233 cc->tcg_initialize = tcg_x86_init;
7234 cc->tlb_fill = x86_cpu_tlb_fill;
7235 #endif
7236 cc->disas_set_info = x86_disas_set_info;
7237
7238 dc->user_creatable = true;
7239 }
7240
7241 static const TypeInfo x86_cpu_type_info = {
7242 .name = TYPE_X86_CPU,
7243 .parent = TYPE_CPU,
7244 .instance_size = sizeof(X86CPU),
7245 .instance_init = x86_cpu_initfn,
7246 .abstract = true,
7247 .class_size = sizeof(X86CPUClass),
7248 .class_init = x86_cpu_common_class_init,
7249 };
7250
7251
7252 /* "base" CPU model, used by query-cpu-model-expansion */
7253 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7254 {
7255 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7256
7257 xcc->static_model = true;
7258 xcc->migration_safe = true;
7259 xcc->model_description = "base CPU model type with no features enabled";
7260 xcc->ordering = 8;
7261 }
7262
7263 static const TypeInfo x86_base_cpu_type_info = {
7264 .name = X86_CPU_TYPE_NAME("base"),
7265 .parent = TYPE_X86_CPU,
7266 .class_init = x86_cpu_base_class_init,
7267 };
7268
7269 static void x86_cpu_register_types(void)
7270 {
7271 int i;
7272
7273 type_register_static(&x86_cpu_type_info);
7274 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
7275 x86_register_cpudef_types(&builtin_x86_defs[i]);
7276 }
7277 type_register_static(&max_x86_cpu_type_info);
7278 type_register_static(&x86_base_cpu_type_info);
7279 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
7280 type_register_static(&host_x86_cpu_type_info);
7281 #endif
7282 }
7283
7284 type_init(x86_cpu_register_types)
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