2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "sysemu/tcg.h"
25 #include "kvm/hyperv-proto.h"
26 #include "exec/cpu-defs.h"
27 #include "qapi/qapi-types-common.h"
28 #include "qemu/cpu-float.h"
30 #define XEN_NR_VIRQS 24
32 /* The x86 has a strong memory model with some store-after-load re-ordering */
33 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
35 #define KVM_HAVE_MCE_INJECTION 1
37 /* support for self modifying code even if the modified instruction is
38 close to the modifying instruction */
39 #define TARGET_HAS_PRECISE_SMC
42 #define I386_ELF_MACHINE EM_X86_64
43 #define ELF_MACHINE_UNAME "x86_64"
45 #define I386_ELF_MACHINE EM_386
46 #define ELF_MACHINE_UNAME "i686"
88 /* segment descriptor fields */
89 #define DESC_G_SHIFT 23
90 #define DESC_G_MASK (1 << DESC_G_SHIFT)
91 #define DESC_B_SHIFT 22
92 #define DESC_B_MASK (1 << DESC_B_SHIFT)
93 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
94 #define DESC_L_MASK (1 << DESC_L_SHIFT)
95 #define DESC_AVL_SHIFT 20
96 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
97 #define DESC_P_SHIFT 15
98 #define DESC_P_MASK (1 << DESC_P_SHIFT)
99 #define DESC_DPL_SHIFT 13
100 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
101 #define DESC_S_SHIFT 12
102 #define DESC_S_MASK (1 << DESC_S_SHIFT)
103 #define DESC_TYPE_SHIFT 8
104 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
105 #define DESC_A_MASK (1 << 8)
107 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
108 #define DESC_C_MASK (1 << 10) /* code: conforming */
109 #define DESC_R_MASK (1 << 9) /* code: readable */
111 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
112 #define DESC_W_MASK (1 << 9) /* data: writable */
114 #define DESC_TSS_BUSY_MASK (1 << 9)
125 #define IOPL_SHIFT 12
128 #define TF_MASK 0x00000100
129 #define IF_MASK 0x00000200
130 #define DF_MASK 0x00000400
131 #define IOPL_MASK 0x00003000
132 #define NT_MASK 0x00004000
133 #define RF_MASK 0x00010000
134 #define VM_MASK 0x00020000
135 #define AC_MASK 0x00040000
136 #define VIF_MASK 0x00080000
137 #define VIP_MASK 0x00100000
138 #define ID_MASK 0x00200000
140 /* hidden flags - used internally by qemu to represent additional cpu
141 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
142 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
143 positions to ease oring with eflags. */
145 #define HF_CPL_SHIFT 0
146 /* true if hardware interrupts must be disabled for next instruction */
147 #define HF_INHIBIT_IRQ_SHIFT 3
148 /* 16 or 32 segments */
149 #define HF_CS32_SHIFT 4
150 #define HF_SS32_SHIFT 5
151 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
152 #define HF_ADDSEG_SHIFT 6
153 /* copy of CR0.PE (protected mode) */
154 #define HF_PE_SHIFT 7
155 #define HF_TF_SHIFT 8 /* must be same as eflags */
156 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
157 #define HF_EM_SHIFT 10
158 #define HF_TS_SHIFT 11
159 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
160 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
161 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
162 #define HF_RF_SHIFT 16 /* must be same as eflags */
163 #define HF_VM_SHIFT 17 /* must be same as eflags */
164 #define HF_AC_SHIFT 18 /* must be same as eflags */
165 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
166 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
167 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */
168 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
169 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
170 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
171 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
172 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
173 #define HF_UMIP_SHIFT 27 /* CR4.UMIP */
174 #define HF_AVX_EN_SHIFT 28 /* AVX Enabled (CR4+XCR0) */
176 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
177 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
178 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
179 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
180 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
181 #define HF_PE_MASK (1 << HF_PE_SHIFT)
182 #define HF_TF_MASK (1 << HF_TF_SHIFT)
183 #define HF_MP_MASK (1 << HF_MP_SHIFT)
184 #define HF_EM_MASK (1 << HF_EM_SHIFT)
185 #define HF_TS_MASK (1 << HF_TS_SHIFT)
186 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
187 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
188 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
189 #define HF_RF_MASK (1 << HF_RF_SHIFT)
190 #define HF_VM_MASK (1 << HF_VM_SHIFT)
191 #define HF_AC_MASK (1 << HF_AC_SHIFT)
192 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
193 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
194 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
195 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
196 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
197 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
198 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
199 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
200 #define HF_UMIP_MASK (1 << HF_UMIP_SHIFT)
201 #define HF_AVX_EN_MASK (1 << HF_AVX_EN_SHIFT)
205 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
206 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
207 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
208 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
209 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
210 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
211 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */
212 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */
213 #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/
215 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
216 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
217 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
218 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
219 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
220 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
221 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
222 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
223 #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT)
225 #define CR0_PE_SHIFT 0
226 #define CR0_MP_SHIFT 1
228 #define CR0_PE_MASK (1U << 0)
229 #define CR0_MP_MASK (1U << 1)
230 #define CR0_EM_MASK (1U << 2)
231 #define CR0_TS_MASK (1U << 3)
232 #define CR0_ET_MASK (1U << 4)
233 #define CR0_NE_MASK (1U << 5)
234 #define CR0_WP_MASK (1U << 16)
235 #define CR0_AM_MASK (1U << 18)
236 #define CR0_NW_MASK (1U << 29)
237 #define CR0_CD_MASK (1U << 30)
238 #define CR0_PG_MASK (1U << 31)
240 #define CR4_VME_MASK (1U << 0)
241 #define CR4_PVI_MASK (1U << 1)
242 #define CR4_TSD_MASK (1U << 2)
243 #define CR4_DE_MASK (1U << 3)
244 #define CR4_PSE_MASK (1U << 4)
245 #define CR4_PAE_MASK (1U << 5)
246 #define CR4_MCE_MASK (1U << 6)
247 #define CR4_PGE_MASK (1U << 7)
248 #define CR4_PCE_MASK (1U << 8)
249 #define CR4_OSFXSR_SHIFT 9
250 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
251 #define CR4_OSXMMEXCPT_MASK (1U << 10)
252 #define CR4_UMIP_MASK (1U << 11)
253 #define CR4_LA57_MASK (1U << 12)
254 #define CR4_VMXE_MASK (1U << 13)
255 #define CR4_SMXE_MASK (1U << 14)
256 #define CR4_FSGSBASE_MASK (1U << 16)
257 #define CR4_PCIDE_MASK (1U << 17)
258 #define CR4_OSXSAVE_MASK (1U << 18)
259 #define CR4_SMEP_MASK (1U << 20)
260 #define CR4_SMAP_MASK (1U << 21)
261 #define CR4_PKE_MASK (1U << 22)
262 #define CR4_PKS_MASK (1U << 24)
264 #define CR4_RESERVED_MASK \
265 (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
266 | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
267 | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
268 | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
270 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
271 | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK))
273 #define DR6_BD (1 << 13)
274 #define DR6_BS (1 << 14)
275 #define DR6_BT (1 << 15)
276 #define DR6_FIXED_1 0xffff0ff0
278 #define DR7_GD (1 << 13)
279 #define DR7_TYPE_SHIFT 16
280 #define DR7_LEN_SHIFT 18
281 #define DR7_FIXED_1 0x00000400
282 #define DR7_GLOBAL_BP_MASK 0xaa
283 #define DR7_LOCAL_BP_MASK 0x55
285 #define DR7_TYPE_BP_INST 0x0
286 #define DR7_TYPE_DATA_WR 0x1
287 #define DR7_TYPE_IO_RW 0x2
288 #define DR7_TYPE_DATA_RW 0x3
290 #define DR_RESERVED_MASK 0xffffffff00000000ULL
292 #define PG_PRESENT_BIT 0
294 #define PG_USER_BIT 2
297 #define PG_ACCESSED_BIT 5
298 #define PG_DIRTY_BIT 6
300 #define PG_GLOBAL_BIT 8
301 #define PG_PSE_PAT_BIT 12
302 #define PG_PKRU_BIT 59
305 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
306 #define PG_RW_MASK (1 << PG_RW_BIT)
307 #define PG_USER_MASK (1 << PG_USER_BIT)
308 #define PG_PWT_MASK (1 << PG_PWT_BIT)
309 #define PG_PCD_MASK (1 << PG_PCD_BIT)
310 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
311 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
312 #define PG_PSE_MASK (1 << PG_PSE_BIT)
313 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
314 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
315 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
316 #define PG_HI_USER_MASK 0x7ff0000000000000LL
317 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
318 #define PG_NX_MASK (1ULL << PG_NX_BIT)
320 #define PG_ERROR_W_BIT 1
322 #define PG_ERROR_P_MASK 0x01
323 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
324 #define PG_ERROR_U_MASK 0x04
325 #define PG_ERROR_RSVD_MASK 0x08
326 #define PG_ERROR_I_D_MASK 0x10
327 #define PG_ERROR_PK_MASK 0x20
329 #define PG_MODE_PAE (1 << 0)
330 #define PG_MODE_LMA (1 << 1)
331 #define PG_MODE_NXE (1 << 2)
332 #define PG_MODE_PSE (1 << 3)
333 #define PG_MODE_LA57 (1 << 4)
334 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
336 /* Bits of CR4 that do not affect the NPT page format. */
337 #define PG_MODE_WP (1 << 16)
338 #define PG_MODE_PKE (1 << 17)
339 #define PG_MODE_PKS (1 << 18)
340 #define PG_MODE_SMEP (1 << 19)
342 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
343 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
344 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
346 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
347 #define MCE_BANKS_DEF 10
349 #define MCG_CAP_BANKS_MASK 0xff
351 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
352 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
353 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
354 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */
356 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
358 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
359 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
360 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
361 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
362 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
363 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
364 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
365 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
366 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
368 /* MISC register defines */
369 #define MCM_ADDR_SEGOFF 0 /* segment offset */
370 #define MCM_ADDR_LINEAR 1 /* linear address */
371 #define MCM_ADDR_PHYS 2 /* physical address */
372 #define MCM_ADDR_MEM 3 /* memory address */
373 #define MCM_ADDR_GENERIC 7 /* generic */
375 #define MSR_IA32_TSC 0x10
376 #define MSR_IA32_APICBASE 0x1b
377 #define MSR_IA32_APICBASE_BSP (1<<8)
378 #define MSR_IA32_APICBASE_ENABLE (1<<11)
379 #define MSR_IA32_APICBASE_EXTD (1 << 10)
380 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
381 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
382 #define MSR_TSC_ADJUST 0x0000003b
383 #define MSR_IA32_SPEC_CTRL 0x48
384 #define MSR_VIRT_SSBD 0xc001011f
385 #define MSR_IA32_PRED_CMD 0x49
386 #define MSR_IA32_UCODE_REV 0x8b
387 #define MSR_IA32_CORE_CAPABILITY 0xcf
389 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
390 #define ARCH_CAP_TSX_CTRL_MSR (1<<7)
392 #define MSR_IA32_PERF_CAPABILITIES 0x345
393 #define PERF_CAP_LBR_FMT 0x3f
395 #define MSR_IA32_TSX_CTRL 0x122
396 #define MSR_IA32_TSCDEADLINE 0x6e0
397 #define MSR_IA32_PKRS 0x6e1
398 #define MSR_ARCH_LBR_CTL 0x000014ce
399 #define MSR_ARCH_LBR_DEPTH 0x000014cf
400 #define MSR_ARCH_LBR_FROM_0 0x00001500
401 #define MSR_ARCH_LBR_TO_0 0x00001600
402 #define MSR_ARCH_LBR_INFO_0 0x00001200
404 #define FEATURE_CONTROL_LOCKED (1<<0)
405 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1)
406 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
407 #define FEATURE_CONTROL_SGX_LC (1ULL << 17)
408 #define FEATURE_CONTROL_SGX (1ULL << 18)
409 #define FEATURE_CONTROL_LMCE (1<<20)
411 #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c
412 #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d
413 #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e
414 #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f
416 #define MSR_P6_PERFCTR0 0xc1
418 #define MSR_IA32_SMBASE 0x9e
419 #define MSR_SMI_COUNT 0x34
420 #define MSR_CORE_THREAD_COUNT 0x35
421 #define MSR_MTRRcap 0xfe
422 #define MSR_MTRRcap_VCNT 8
423 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
424 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
426 #define MSR_IA32_SYSENTER_CS 0x174
427 #define MSR_IA32_SYSENTER_ESP 0x175
428 #define MSR_IA32_SYSENTER_EIP 0x176
430 #define MSR_MCG_CAP 0x179
431 #define MSR_MCG_STATUS 0x17a
432 #define MSR_MCG_CTL 0x17b
433 #define MSR_MCG_EXT_CTL 0x4d0
435 #define MSR_P6_EVNTSEL0 0x186
437 #define MSR_IA32_PERF_STATUS 0x198
439 #define MSR_IA32_MISC_ENABLE 0x1a0
440 /* Indicates good rep/movs microcode on some processors: */
441 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
442 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
444 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
445 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
447 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
449 #define MSR_MTRRfix64K_00000 0x250
450 #define MSR_MTRRfix16K_80000 0x258
451 #define MSR_MTRRfix16K_A0000 0x259
452 #define MSR_MTRRfix4K_C0000 0x268
453 #define MSR_MTRRfix4K_C8000 0x269
454 #define MSR_MTRRfix4K_D0000 0x26a
455 #define MSR_MTRRfix4K_D8000 0x26b
456 #define MSR_MTRRfix4K_E0000 0x26c
457 #define MSR_MTRRfix4K_E8000 0x26d
458 #define MSR_MTRRfix4K_F0000 0x26e
459 #define MSR_MTRRfix4K_F8000 0x26f
461 #define MSR_PAT 0x277
463 #define MSR_MTRRdefType 0x2ff
465 #define MSR_CORE_PERF_FIXED_CTR0 0x309
466 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
467 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
468 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
469 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
470 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
471 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
473 #define MSR_MC0_CTL 0x400
474 #define MSR_MC0_STATUS 0x401
475 #define MSR_MC0_ADDR 0x402
476 #define MSR_MC0_MISC 0x403
478 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560
479 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561
480 #define MSR_IA32_RTIT_CTL 0x570
481 #define MSR_IA32_RTIT_STATUS 0x571
482 #define MSR_IA32_RTIT_CR3_MATCH 0x572
483 #define MSR_IA32_RTIT_ADDR0_A 0x580
484 #define MSR_IA32_RTIT_ADDR0_B 0x581
485 #define MSR_IA32_RTIT_ADDR1_A 0x582
486 #define MSR_IA32_RTIT_ADDR1_B 0x583
487 #define MSR_IA32_RTIT_ADDR2_A 0x584
488 #define MSR_IA32_RTIT_ADDR2_B 0x585
489 #define MSR_IA32_RTIT_ADDR3_A 0x586
490 #define MSR_IA32_RTIT_ADDR3_B 0x587
491 #define MAX_RTIT_ADDRS 8
493 #define MSR_EFER 0xc0000080
495 #define MSR_EFER_SCE (1 << 0)
496 #define MSR_EFER_LME (1 << 8)
497 #define MSR_EFER_LMA (1 << 10)
498 #define MSR_EFER_NXE (1 << 11)
499 #define MSR_EFER_SVME (1 << 12)
500 #define MSR_EFER_FFXSR (1 << 14)
502 #define MSR_EFER_RESERVED\
503 (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\
504 | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\
507 #define MSR_STAR 0xc0000081
508 #define MSR_LSTAR 0xc0000082
509 #define MSR_CSTAR 0xc0000083
510 #define MSR_FMASK 0xc0000084
511 #define MSR_FSBASE 0xc0000100
512 #define MSR_GSBASE 0xc0000101
513 #define MSR_KERNELGSBASE 0xc0000102
514 #define MSR_TSC_AUX 0xc0000103
515 #define MSR_AMD64_TSC_RATIO 0xc0000104
517 #define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL
519 #define MSR_VM_HSAVE_PA 0xc0010117
521 #define MSR_IA32_XFD 0x000001c4
522 #define MSR_IA32_XFD_ERR 0x000001c5
524 #define MSR_IA32_BNDCFGS 0x00000d90
525 #define MSR_IA32_XSS 0x00000da0
526 #define MSR_IA32_UMWAIT_CONTROL 0xe1
528 #define MSR_IA32_VMX_BASIC 0x00000480
529 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
530 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
531 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
532 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
533 #define MSR_IA32_VMX_MISC 0x00000485
534 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
535 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
536 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
537 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
538 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
539 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
540 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
541 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
542 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
543 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
544 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
545 #define MSR_IA32_VMX_VMFUNC 0x00000491
547 #define XSTATE_FP_BIT 0
548 #define XSTATE_SSE_BIT 1
549 #define XSTATE_YMM_BIT 2
550 #define XSTATE_BNDREGS_BIT 3
551 #define XSTATE_BNDCSR_BIT 4
552 #define XSTATE_OPMASK_BIT 5
553 #define XSTATE_ZMM_Hi256_BIT 6
554 #define XSTATE_Hi16_ZMM_BIT 7
555 #define XSTATE_PKRU_BIT 9
556 #define XSTATE_ARCH_LBR_BIT 15
557 #define XSTATE_XTILE_CFG_BIT 17
558 #define XSTATE_XTILE_DATA_BIT 18
560 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
561 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
562 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
563 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
564 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
565 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
566 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
567 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
568 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
569 #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT)
570 #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT)
571 #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT)
573 #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK)
575 #define ESA_FEATURE_ALIGN64_BIT 1
576 #define ESA_FEATURE_XFD_BIT 2
578 #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT)
579 #define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT)
582 /* CPUID feature bits available in XCR0 */
583 #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \
584 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \
585 XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \
586 XSTATE_ZMM_Hi256_MASK | \
587 XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
588 XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK)
590 /* CPUID feature words */
591 typedef enum FeatureWord
{
592 FEAT_1_EDX
, /* CPUID[1].EDX */
593 FEAT_1_ECX
, /* CPUID[1].ECX */
594 FEAT_7_0_EBX
, /* CPUID[EAX=7,ECX=0].EBX */
595 FEAT_7_0_ECX
, /* CPUID[EAX=7,ECX=0].ECX */
596 FEAT_7_0_EDX
, /* CPUID[EAX=7,ECX=0].EDX */
597 FEAT_7_1_EAX
, /* CPUID[EAX=7,ECX=1].EAX */
598 FEAT_8000_0001_EDX
, /* CPUID[8000_0001].EDX */
599 FEAT_8000_0001_ECX
, /* CPUID[8000_0001].ECX */
600 FEAT_8000_0007_EDX
, /* CPUID[8000_0007].EDX */
601 FEAT_8000_0008_EBX
, /* CPUID[8000_0008].EBX */
602 FEAT_C000_0001_EDX
, /* CPUID[C000_0001].EDX */
603 FEAT_KVM
, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
604 FEAT_KVM_HINTS
, /* CPUID[4000_0001].EDX */
605 FEAT_SVM
, /* CPUID[8000_000A].EDX */
606 FEAT_XSAVE
, /* CPUID[EAX=0xd,ECX=1].EAX */
607 FEAT_6_EAX
, /* CPUID[6].EAX */
608 FEAT_XSAVE_XCR0_LO
, /* CPUID[EAX=0xd,ECX=0].EAX */
609 FEAT_XSAVE_XCR0_HI
, /* CPUID[EAX=0xd,ECX=0].EDX */
610 FEAT_ARCH_CAPABILITIES
,
611 FEAT_CORE_CAPABILITY
,
612 FEAT_PERF_CAPABILITIES
,
613 FEAT_VMX_PROCBASED_CTLS
,
614 FEAT_VMX_SECONDARY_CTLS
,
615 FEAT_VMX_PINBASED_CTLS
,
619 FEAT_VMX_EPT_VPID_CAPS
,
623 FEAT_SGX_12_0_EAX
, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
624 FEAT_SGX_12_0_EBX
, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
625 FEAT_SGX_12_1_EAX
, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
626 FEAT_XSAVE_XSS_LO
, /* CPUID[EAX=0xd,ECX=1].ECX */
627 FEAT_XSAVE_XSS_HI
, /* CPUID[EAX=0xd,ECX=1].EDX */
631 typedef uint64_t FeatureWordArray
[FEATURE_WORDS
];
632 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w
,
633 bool migratable_only
);
635 /* cpuid_features bits */
636 #define CPUID_FP87 (1U << 0)
637 #define CPUID_VME (1U << 1)
638 #define CPUID_DE (1U << 2)
639 #define CPUID_PSE (1U << 3)
640 #define CPUID_TSC (1U << 4)
641 #define CPUID_MSR (1U << 5)
642 #define CPUID_PAE (1U << 6)
643 #define CPUID_MCE (1U << 7)
644 #define CPUID_CX8 (1U << 8)
645 #define CPUID_APIC (1U << 9)
646 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
647 #define CPUID_MTRR (1U << 12)
648 #define CPUID_PGE (1U << 13)
649 #define CPUID_MCA (1U << 14)
650 #define CPUID_CMOV (1U << 15)
651 #define CPUID_PAT (1U << 16)
652 #define CPUID_PSE36 (1U << 17)
653 #define CPUID_PN (1U << 18)
654 #define CPUID_CLFLUSH (1U << 19)
655 #define CPUID_DTS (1U << 21)
656 #define CPUID_ACPI (1U << 22)
657 #define CPUID_MMX (1U << 23)
658 #define CPUID_FXSR (1U << 24)
659 #define CPUID_SSE (1U << 25)
660 #define CPUID_SSE2 (1U << 26)
661 #define CPUID_SS (1U << 27)
662 #define CPUID_HT (1U << 28)
663 #define CPUID_TM (1U << 29)
664 #define CPUID_IA64 (1U << 30)
665 #define CPUID_PBE (1U << 31)
667 #define CPUID_EXT_SSE3 (1U << 0)
668 #define CPUID_EXT_PCLMULQDQ (1U << 1)
669 #define CPUID_EXT_DTES64 (1U << 2)
670 #define CPUID_EXT_MONITOR (1U << 3)
671 #define CPUID_EXT_DSCPL (1U << 4)
672 #define CPUID_EXT_VMX (1U << 5)
673 #define CPUID_EXT_SMX (1U << 6)
674 #define CPUID_EXT_EST (1U << 7)
675 #define CPUID_EXT_TM2 (1U << 8)
676 #define CPUID_EXT_SSSE3 (1U << 9)
677 #define CPUID_EXT_CID (1U << 10)
678 #define CPUID_EXT_FMA (1U << 12)
679 #define CPUID_EXT_CX16 (1U << 13)
680 #define CPUID_EXT_XTPR (1U << 14)
681 #define CPUID_EXT_PDCM (1U << 15)
682 #define CPUID_EXT_PCID (1U << 17)
683 #define CPUID_EXT_DCA (1U << 18)
684 #define CPUID_EXT_SSE41 (1U << 19)
685 #define CPUID_EXT_SSE42 (1U << 20)
686 #define CPUID_EXT_X2APIC (1U << 21)
687 #define CPUID_EXT_MOVBE (1U << 22)
688 #define CPUID_EXT_POPCNT (1U << 23)
689 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
690 #define CPUID_EXT_AES (1U << 25)
691 #define CPUID_EXT_XSAVE (1U << 26)
692 #define CPUID_EXT_OSXSAVE (1U << 27)
693 #define CPUID_EXT_AVX (1U << 28)
694 #define CPUID_EXT_F16C (1U << 29)
695 #define CPUID_EXT_RDRAND (1U << 30)
696 #define CPUID_EXT_HYPERVISOR (1U << 31)
698 #define CPUID_EXT2_FPU (1U << 0)
699 #define CPUID_EXT2_VME (1U << 1)
700 #define CPUID_EXT2_DE (1U << 2)
701 #define CPUID_EXT2_PSE (1U << 3)
702 #define CPUID_EXT2_TSC (1U << 4)
703 #define CPUID_EXT2_MSR (1U << 5)
704 #define CPUID_EXT2_PAE (1U << 6)
705 #define CPUID_EXT2_MCE (1U << 7)
706 #define CPUID_EXT2_CX8 (1U << 8)
707 #define CPUID_EXT2_APIC (1U << 9)
708 #define CPUID_EXT2_SYSCALL (1U << 11)
709 #define CPUID_EXT2_MTRR (1U << 12)
710 #define CPUID_EXT2_PGE (1U << 13)
711 #define CPUID_EXT2_MCA (1U << 14)
712 #define CPUID_EXT2_CMOV (1U << 15)
713 #define CPUID_EXT2_PAT (1U << 16)
714 #define CPUID_EXT2_PSE36 (1U << 17)
715 #define CPUID_EXT2_MP (1U << 19)
716 #define CPUID_EXT2_NX (1U << 20)
717 #define CPUID_EXT2_MMXEXT (1U << 22)
718 #define CPUID_EXT2_MMX (1U << 23)
719 #define CPUID_EXT2_FXSR (1U << 24)
720 #define CPUID_EXT2_FFXSR (1U << 25)
721 #define CPUID_EXT2_PDPE1GB (1U << 26)
722 #define CPUID_EXT2_RDTSCP (1U << 27)
723 #define CPUID_EXT2_LM (1U << 29)
724 #define CPUID_EXT2_3DNOWEXT (1U << 30)
725 #define CPUID_EXT2_3DNOW (1U << 31)
727 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
728 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
729 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
730 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
731 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
732 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
733 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
734 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
735 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
736 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
738 #define CPUID_EXT3_LAHF_LM (1U << 0)
739 #define CPUID_EXT3_CMP_LEG (1U << 1)
740 #define CPUID_EXT3_SVM (1U << 2)
741 #define CPUID_EXT3_EXTAPIC (1U << 3)
742 #define CPUID_EXT3_CR8LEG (1U << 4)
743 #define CPUID_EXT3_ABM (1U << 5)
744 #define CPUID_EXT3_SSE4A (1U << 6)
745 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
746 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
747 #define CPUID_EXT3_OSVW (1U << 9)
748 #define CPUID_EXT3_IBS (1U << 10)
749 #define CPUID_EXT3_XOP (1U << 11)
750 #define CPUID_EXT3_SKINIT (1U << 12)
751 #define CPUID_EXT3_WDT (1U << 13)
752 #define CPUID_EXT3_LWP (1U << 15)
753 #define CPUID_EXT3_FMA4 (1U << 16)
754 #define CPUID_EXT3_TCE (1U << 17)
755 #define CPUID_EXT3_NODEID (1U << 19)
756 #define CPUID_EXT3_TBM (1U << 21)
757 #define CPUID_EXT3_TOPOEXT (1U << 22)
758 #define CPUID_EXT3_PERFCORE (1U << 23)
759 #define CPUID_EXT3_PERFNB (1U << 24)
761 #define CPUID_SVM_NPT (1U << 0)
762 #define CPUID_SVM_LBRV (1U << 1)
763 #define CPUID_SVM_SVMLOCK (1U << 2)
764 #define CPUID_SVM_NRIPSAVE (1U << 3)
765 #define CPUID_SVM_TSCSCALE (1U << 4)
766 #define CPUID_SVM_VMCBCLEAN (1U << 5)
767 #define CPUID_SVM_FLUSHASID (1U << 6)
768 #define CPUID_SVM_DECODEASSIST (1U << 7)
769 #define CPUID_SVM_PAUSEFILTER (1U << 10)
770 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
771 #define CPUID_SVM_AVIC (1U << 13)
772 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
773 #define CPUID_SVM_VGIF (1U << 16)
774 #define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
776 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
777 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
779 #define CPUID_7_0_EBX_SGX (1U << 2)
780 /* 1st Group of Advanced Bit Manipulation Extensions */
781 #define CPUID_7_0_EBX_BMI1 (1U << 3)
782 /* Hardware Lock Elision */
783 #define CPUID_7_0_EBX_HLE (1U << 4)
784 /* Intel Advanced Vector Extensions 2 */
785 #define CPUID_7_0_EBX_AVX2 (1U << 5)
786 /* Supervisor-mode Execution Prevention */
787 #define CPUID_7_0_EBX_SMEP (1U << 7)
788 /* 2nd Group of Advanced Bit Manipulation Extensions */
789 #define CPUID_7_0_EBX_BMI2 (1U << 8)
790 /* Enhanced REP MOVSB/STOSB */
791 #define CPUID_7_0_EBX_ERMS (1U << 9)
792 /* Invalidate Process-Context Identifier */
793 #define CPUID_7_0_EBX_INVPCID (1U << 10)
794 /* Restricted Transactional Memory */
795 #define CPUID_7_0_EBX_RTM (1U << 11)
796 /* Memory Protection Extension */
797 #define CPUID_7_0_EBX_MPX (1U << 14)
798 /* AVX-512 Foundation */
799 #define CPUID_7_0_EBX_AVX512F (1U << 16)
800 /* AVX-512 Doubleword & Quadword Instruction */
801 #define CPUID_7_0_EBX_AVX512DQ (1U << 17)
802 /* Read Random SEED */
803 #define CPUID_7_0_EBX_RDSEED (1U << 18)
804 /* ADCX and ADOX instructions */
805 #define CPUID_7_0_EBX_ADX (1U << 19)
806 /* Supervisor Mode Access Prevention */
807 #define CPUID_7_0_EBX_SMAP (1U << 20)
808 /* AVX-512 Integer Fused Multiply Add */
809 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
810 /* Persistent Commit */
811 #define CPUID_7_0_EBX_PCOMMIT (1U << 22)
812 /* Flush a Cache Line Optimized */
813 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
814 /* Cache Line Write Back */
815 #define CPUID_7_0_EBX_CLWB (1U << 24)
816 /* Intel Processor Trace */
817 #define CPUID_7_0_EBX_INTEL_PT (1U << 25)
818 /* AVX-512 Prefetch */
819 #define CPUID_7_0_EBX_AVX512PF (1U << 26)
820 /* AVX-512 Exponential and Reciprocal */
821 #define CPUID_7_0_EBX_AVX512ER (1U << 27)
822 /* AVX-512 Conflict Detection */
823 #define CPUID_7_0_EBX_AVX512CD (1U << 28)
824 /* SHA1/SHA256 Instruction Extensions */
825 #define CPUID_7_0_EBX_SHA_NI (1U << 29)
826 /* AVX-512 Byte and Word Instructions */
827 #define CPUID_7_0_EBX_AVX512BW (1U << 30)
828 /* AVX-512 Vector Length Extensions */
829 #define CPUID_7_0_EBX_AVX512VL (1U << 31)
831 /* AVX-512 Vector Byte Manipulation Instruction */
832 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
833 /* User-Mode Instruction Prevention */
834 #define CPUID_7_0_ECX_UMIP (1U << 2)
835 /* Protection Keys for User-mode Pages */
836 #define CPUID_7_0_ECX_PKU (1U << 3)
837 /* OS Enable Protection Keys */
838 #define CPUID_7_0_ECX_OSPKE (1U << 4)
839 /* UMONITOR/UMWAIT/TPAUSE Instructions */
840 #define CPUID_7_0_ECX_WAITPKG (1U << 5)
841 /* Additional AVX-512 Vector Byte Manipulation Instruction */
842 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
843 /* Galois Field New Instructions */
844 #define CPUID_7_0_ECX_GFNI (1U << 8)
845 /* Vector AES Instructions */
846 #define CPUID_7_0_ECX_VAES (1U << 9)
847 /* Carry-Less Multiplication Quadword */
848 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
849 /* Vector Neural Network Instructions */
850 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
851 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
852 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
853 /* POPCNT for vectors of DW/QW */
854 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
855 /* 5-level Page Tables */
856 #define CPUID_7_0_ECX_LA57 (1U << 16)
857 /* Read Processor ID */
858 #define CPUID_7_0_ECX_RDPID (1U << 22)
859 /* Bus Lock Debug Exception */
860 #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24)
861 /* Cache Line Demote Instruction */
862 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
863 /* Move Doubleword as Direct Store Instruction */
864 #define CPUID_7_0_ECX_MOVDIRI (1U << 27)
865 /* Move 64 Bytes as Direct Store Instruction */
866 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
867 /* Support SGX Launch Control */
868 #define CPUID_7_0_ECX_SGX_LC (1U << 30)
869 /* Protection Keys for Supervisor-mode Pages */
870 #define CPUID_7_0_ECX_PKS (1U << 31)
872 /* AVX512 Neural Network Instructions */
873 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
874 /* AVX512 Multiply Accumulation Single Precision */
875 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
876 /* Fast Short Rep Mov */
877 #define CPUID_7_0_EDX_FSRM (1U << 4)
878 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
879 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
880 /* SERIALIZE instruction */
881 #define CPUID_7_0_EDX_SERIALIZE (1U << 14)
882 /* TSX Suspend Load Address Tracking instruction */
883 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
884 /* Architectural LBRs */
885 #define CPUID_7_0_EDX_ARCH_LBR (1U << 19)
886 /* AMX_BF16 instruction */
887 #define CPUID_7_0_EDX_AMX_BF16 (1U << 22)
888 /* AVX512_FP16 instruction */
889 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
890 /* AMX tile (two-dimensional register) */
891 #define CPUID_7_0_EDX_AMX_TILE (1U << 24)
892 /* AMX_INT8 instruction */
893 #define CPUID_7_0_EDX_AMX_INT8 (1U << 25)
894 /* Speculation Control */
895 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
896 /* Single Thread Indirect Branch Predictors */
897 #define CPUID_7_0_EDX_STIBP (1U << 27)
898 /* Arch Capabilities */
899 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
900 /* Core Capability */
901 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
902 /* Speculative Store Bypass Disable */
903 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
905 /* AVX VNNI Instruction */
906 #define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
907 /* AVX512 BFloat16 Instruction */
908 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
909 /* Fast Zero REP MOVS */
910 #define CPUID_7_1_EAX_FZRM (1U << 10)
911 /* Fast Short REP STOS */
912 #define CPUID_7_1_EAX_FSRS (1U << 11)
913 /* Fast Short REP CMPS/SCAS */
914 #define CPUID_7_1_EAX_FSRC (1U << 12)
916 /* XFD Extend Feature Disabled */
917 #define CPUID_D_1_EAX_XFD (1U << 4)
919 /* Packets which contain IP payload have LIP values */
920 #define CPUID_14_0_ECX_LIP (1U << 31)
922 /* CLZERO instruction */
923 #define CPUID_8000_0008_EBX_CLZERO (1U << 0)
924 /* Always save/restore FP error pointers */
925 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
926 /* Write back and do not invalidate cache */
927 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
928 /* Indirect Branch Prediction Barrier */
929 #define CPUID_8000_0008_EBX_IBPB (1U << 12)
930 /* Indirect Branch Restricted Speculation */
931 #define CPUID_8000_0008_EBX_IBRS (1U << 14)
932 /* Single Thread Indirect Branch Predictors */
933 #define CPUID_8000_0008_EBX_STIBP (1U << 15)
934 /* Speculative Store Bypass Disable */
935 #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
937 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
938 #define CPUID_XSAVE_XSAVEC (1U << 1)
939 #define CPUID_XSAVE_XGETBV1 (1U << 2)
940 #define CPUID_XSAVE_XSAVES (1U << 3)
942 #define CPUID_6_EAX_ARAT (1U << 2)
944 /* CPUID[0x80000007].EDX flags: */
945 #define CPUID_APM_INVTSC (1U << 8)
947 #define CPUID_VENDOR_SZ 12
949 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
950 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
951 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
952 #define CPUID_VENDOR_INTEL "GenuineIntel"
954 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
955 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
956 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
957 #define CPUID_VENDOR_AMD "AuthenticAMD"
959 #define CPUID_VENDOR_VIA "CentaurHauls"
961 #define CPUID_VENDOR_HYGON "HygonGenuine"
963 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
964 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
965 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
966 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
967 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
968 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
970 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
971 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
973 /* CPUID[0xB].ECX level types */
974 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
975 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
976 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
977 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
979 /* MSR Feature Bits */
980 #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
981 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
982 #define MSR_ARCH_CAP_RSBA (1U << 2)
983 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
984 #define MSR_ARCH_CAP_SSB_NO (1U << 4)
985 #define MSR_ARCH_CAP_MDS_NO (1U << 5)
986 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
987 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
988 #define MSR_ARCH_CAP_TAA_NO (1U << 8)
990 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
992 /* VMX MSR features */
993 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
994 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
995 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
996 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
997 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
998 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
1000 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
1001 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
1002 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
1003 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
1004 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
1005 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
1006 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
1007 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
1009 #define MSR_VMX_EPT_EXECONLY (1ULL << 0)
1010 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
1011 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
1012 #define MSR_VMX_EPT_UC (1ULL << 8)
1013 #define MSR_VMX_EPT_WB (1ULL << 14)
1014 #define MSR_VMX_EPT_2MB (1ULL << 16)
1015 #define MSR_VMX_EPT_1GB (1ULL << 17)
1016 #define MSR_VMX_EPT_INVEPT (1ULL << 20)
1017 #define MSR_VMX_EPT_AD_BITS (1ULL << 21)
1018 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
1019 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
1020 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
1021 #define MSR_VMX_EPT_INVVPID (1ULL << 32)
1022 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
1023 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
1024 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
1025 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
1027 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
1031 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
1032 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
1033 #define VMX_CPU_BASED_HLT_EXITING 0x00000080
1034 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
1035 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
1036 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
1037 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
1038 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
1039 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
1040 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
1041 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
1042 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000
1043 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
1044 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
1045 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
1046 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
1047 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
1048 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
1049 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
1050 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
1051 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
1053 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1054 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
1055 #define VMX_SECONDARY_EXEC_DESC 0x00000004
1056 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
1057 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
1058 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
1059 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
1060 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
1061 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
1062 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
1063 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
1064 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
1065 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
1066 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
1067 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
1068 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
1069 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
1070 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
1071 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000
1072 #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000
1074 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
1075 #define VMX_PIN_BASED_NMI_EXITING 0x00000008
1076 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
1077 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
1078 #define VMX_PIN_BASED_POSTED_INTR 0x00000080
1080 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
1081 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
1082 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
1083 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
1084 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
1085 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
1086 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
1087 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
1088 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
1089 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
1090 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
1091 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
1092 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000
1094 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
1095 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200
1096 #define VMX_VM_ENTRY_SMM 0x00000400
1097 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
1098 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
1099 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
1100 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
1101 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
1102 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
1103 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
1104 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000
1106 /* Supported Hyper-V Enlightenments */
1107 #define HYPERV_FEAT_RELAXED 0
1108 #define HYPERV_FEAT_VAPIC 1
1109 #define HYPERV_FEAT_TIME 2
1110 #define HYPERV_FEAT_CRASH 3
1111 #define HYPERV_FEAT_RESET 4
1112 #define HYPERV_FEAT_VPINDEX 5
1113 #define HYPERV_FEAT_RUNTIME 6
1114 #define HYPERV_FEAT_SYNIC 7
1115 #define HYPERV_FEAT_STIMER 8
1116 #define HYPERV_FEAT_FREQUENCIES 9
1117 #define HYPERV_FEAT_REENLIGHTENMENT 10
1118 #define HYPERV_FEAT_TLBFLUSH 11
1119 #define HYPERV_FEAT_EVMCS 12
1120 #define HYPERV_FEAT_IPI 13
1121 #define HYPERV_FEAT_STIMER_DIRECT 14
1122 #define HYPERV_FEAT_AVIC 15
1123 #define HYPERV_FEAT_SYNDBG 16
1124 #define HYPERV_FEAT_MSR_BITMAP 17
1125 #define HYPERV_FEAT_XMM_INPUT 18
1126 #define HYPERV_FEAT_TLBFLUSH_EXT 19
1127 #define HYPERV_FEAT_TLBFLUSH_DIRECT 20
1129 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1130 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
1133 #define EXCP00_DIVZ 0
1135 #define EXCP02_NMI 2
1136 #define EXCP03_INT3 3
1137 #define EXCP04_INTO 4
1138 #define EXCP05_BOUND 5
1139 #define EXCP06_ILLOP 6
1140 #define EXCP07_PREX 7
1141 #define EXCP08_DBLE 8
1142 #define EXCP09_XERR 9
1143 #define EXCP0A_TSS 10
1144 #define EXCP0B_NOSEG 11
1145 #define EXCP0C_STACK 12
1146 #define EXCP0D_GPF 13
1147 #define EXCP0E_PAGE 14
1148 #define EXCP10_COPR 16
1149 #define EXCP11_ALGN 17
1150 #define EXCP12_MCHK 18
1152 #define EXCP_VMEXIT 0x100 /* only for system emulation */
1153 #define EXCP_SYSCALL 0x101 /* only for user emulation */
1154 #define EXCP_VSYSCALL 0x102 /* only for user emulation */
1156 /* i386-specific interrupt pending bits. */
1157 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
1158 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
1159 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
1160 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
1161 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
1162 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
1163 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
1165 /* Use a clearer name for this. */
1166 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
1168 /* Instead of computing the condition codes after each x86 instruction,
1169 * QEMU just stores one operand (called CC_SRC), the result
1170 * (called CC_DST) and the type of operation (called CC_OP). When the
1171 * condition codes are needed, the condition codes can be calculated
1172 * using this information. Condition codes are not generated if they
1173 * are only needed for conditional branches.
1176 CC_OP_DYNAMIC
, /* must use dynamic code to get cc_op */
1177 CC_OP_EFLAGS
, /* all cc are explicitly computed, CC_SRC = flags */
1179 CC_OP_MULB
, /* modify all flags, C, O = (CC_SRC != 0) */
1184 CC_OP_ADDB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1189 CC_OP_ADCB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1194 CC_OP_SUBB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1199 CC_OP_SBBB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1204 CC_OP_LOGICB
, /* modify all flags, CC_DST = res */
1209 CC_OP_INCB
, /* modify all flags except, CC_DST = res, CC_SRC = C */
1214 CC_OP_DECB
, /* modify all flags except, CC_DST = res, CC_SRC = C */
1219 CC_OP_SHLB
, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
1224 CC_OP_SARB
, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
1229 CC_OP_BMILGB
, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1234 CC_OP_ADCX
, /* CC_DST = C, CC_SRC = rest. */
1235 CC_OP_ADOX
, /* CC_DST = O, CC_SRC = rest. */
1236 CC_OP_ADCOX
, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
1238 CC_OP_CLR
, /* Z set, all other flags clear. */
1239 CC_OP_POPCNT
, /* Z via CC_SRC, all other flags clear. */
1244 typedef struct SegmentCache
{
1251 typedef union MMXReg
{
1252 uint8_t _b_MMXReg
[64 / 8];
1253 uint16_t _w_MMXReg
[64 / 16];
1254 uint32_t _l_MMXReg
[64 / 32];
1255 uint64_t _q_MMXReg
[64 / 64];
1256 float32 _s_MMXReg
[64 / 32];
1257 float64 _d_MMXReg
[64 / 64];
1260 typedef union XMMReg
{
1261 uint64_t _q_XMMReg
[128 / 64];
1264 typedef union YMMReg
{
1265 uint64_t _q_YMMReg
[256 / 64];
1266 XMMReg _x_YMMReg
[256 / 128];
1269 typedef union ZMMReg
{
1270 uint8_t _b_ZMMReg
[512 / 8];
1271 uint16_t _w_ZMMReg
[512 / 16];
1272 uint32_t _l_ZMMReg
[512 / 32];
1273 uint64_t _q_ZMMReg
[512 / 64];
1274 float16 _h_ZMMReg
[512 / 16];
1275 float32 _s_ZMMReg
[512 / 32];
1276 float64 _d_ZMMReg
[512 / 64];
1277 XMMReg _x_ZMMReg
[512 / 128];
1278 YMMReg _y_ZMMReg
[512 / 256];
1281 typedef struct BNDReg
{
1286 typedef struct BNDCSReg
{
1291 #define BNDCFG_ENABLE 1ULL
1292 #define BNDCFG_BNDPRESERVE 2ULL
1293 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
1296 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
1297 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
1298 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
1299 #define ZMM_H(n) _h_ZMMReg[31 - (n)]
1300 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
1301 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1302 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
1303 #define ZMM_X(n) _x_ZMMReg[3 - (n)]
1304 #define ZMM_Y(n) _y_ZMMReg[1 - (n)]
1306 #define XMM_Q(n) _q_XMMReg[1 - (n)]
1308 #define YMM_Q(n) _q_YMMReg[3 - (n)]
1309 #define YMM_X(n) _x_YMMReg[1 - (n)]
1311 #define MMX_B(n) _b_MMXReg[7 - (n)]
1312 #define MMX_W(n) _w_MMXReg[3 - (n)]
1313 #define MMX_L(n) _l_MMXReg[1 - (n)]
1314 #define MMX_S(n) _s_MMXReg[1 - (n)]
1316 #define ZMM_B(n) _b_ZMMReg[n]
1317 #define ZMM_W(n) _w_ZMMReg[n]
1318 #define ZMM_L(n) _l_ZMMReg[n]
1319 #define ZMM_H(n) _h_ZMMReg[n]
1320 #define ZMM_S(n) _s_ZMMReg[n]
1321 #define ZMM_Q(n) _q_ZMMReg[n]
1322 #define ZMM_D(n) _d_ZMMReg[n]
1323 #define ZMM_X(n) _x_ZMMReg[n]
1324 #define ZMM_Y(n) _y_ZMMReg[n]
1326 #define XMM_Q(n) _q_XMMReg[n]
1328 #define YMM_Q(n) _q_YMMReg[n]
1329 #define YMM_X(n) _x_YMMReg[n]
1331 #define MMX_B(n) _b_MMXReg[n]
1332 #define MMX_W(n) _w_MMXReg[n]
1333 #define MMX_L(n) _l_MMXReg[n]
1334 #define MMX_S(n) _s_MMXReg[n]
1336 #define MMX_Q(n) _q_MMXReg[n]
1339 floatx80 d
__attribute__((aligned(16)));
1348 #define CPU_NB_REGS64 16
1349 #define CPU_NB_REGS32 8
1351 #ifdef TARGET_X86_64
1352 #define CPU_NB_REGS CPU_NB_REGS64
1354 #define CPU_NB_REGS CPU_NB_REGS32
1357 #define MAX_FIXED_COUNTERS 3
1358 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1360 #define TARGET_INSN_START_EXTRA_WORDS 1
1362 #define NB_OPMASK_REGS 8
1364 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1365 * that APIC ID hasn't been set yet
1367 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1369 typedef union X86LegacyXSaveArea
{
1379 uint32_t mxcsr_mask
;
1381 uint8_t xmm_regs
[16][16];
1384 } X86LegacyXSaveArea
;
1386 typedef struct X86XSaveHeader
{
1390 uint8_t reserved
[40];
1393 /* Ext. save area 2: AVX State */
1394 typedef struct XSaveAVX
{
1395 uint8_t ymmh
[16][16];
1398 /* Ext. save area 3: BNDREG */
1399 typedef struct XSaveBNDREG
{
1403 /* Ext. save area 4: BNDCSR */
1404 typedef union XSaveBNDCSR
{
1409 /* Ext. save area 5: Opmask */
1410 typedef struct XSaveOpmask
{
1411 uint64_t opmask_regs
[NB_OPMASK_REGS
];
1414 /* Ext. save area 6: ZMM_Hi256 */
1415 typedef struct XSaveZMM_Hi256
{
1416 uint8_t zmm_hi256
[16][32];
1419 /* Ext. save area 7: Hi16_ZMM */
1420 typedef struct XSaveHi16_ZMM
{
1421 uint8_t hi16_zmm
[16][64];
1424 /* Ext. save area 9: PKRU state */
1425 typedef struct XSavePKRU
{
1430 /* Ext. save area 17: AMX XTILECFG state */
1431 typedef struct XSaveXTILECFG
{
1432 uint8_t xtilecfg
[64];
1435 /* Ext. save area 18: AMX XTILEDATA state */
1436 typedef struct XSaveXTILEDATA
{
1437 uint8_t xtiledata
[8][1024];
1446 #define ARCH_LBR_NR_ENTRIES 32
1448 /* Ext. save area 19: Supervisor mode Arch LBR state */
1449 typedef struct XSavesArchLBR
{
1455 LBREntry lbr_records
[ARCH_LBR_NR_ENTRIES
];
1458 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX
) != 0x100);
1459 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG
) != 0x40);
1460 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR
) != 0x40);
1461 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask
) != 0x40);
1462 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256
) != 0x200);
1463 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM
) != 0x400);
1464 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU
) != 0x8);
1465 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG
) != 0x40);
1466 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA
) != 0x2000);
1467 QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR
) != 0x328);
1469 typedef struct ExtSaveArea
{
1470 uint32_t feature
, bits
;
1471 uint32_t offset
, size
;
1475 #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
1477 extern ExtSaveArea x86_ext_save_areas
[XSAVE_STATE_AREA_COUNT
];
1479 typedef enum TPRAccess
{
1484 /* Cache information data structures: */
1492 typedef struct CPUCacheInfo
{
1493 enum CacheType type
;
1497 /* Line size, in bytes */
1501 * Note: representation of fully-associative caches is not implemented
1503 uint8_t associativity
;
1504 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1506 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1510 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1511 * (Is this synonym to @partitions?)
1513 uint8_t lines_per_tag
;
1515 /* Self-initializing cache */
1518 * WBINVD/INVD is not guaranteed to act upon lower level caches of
1519 * non-originating threads sharing this cache.
1520 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1522 bool no_invd_sharing
;
1524 * Cache is inclusive of lower cache levels.
1525 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1529 * A complex function is used to index the cache, potentially using all
1530 * address bits. CPUID[4].EDX[bit 2].
1532 bool complex_indexing
;
1536 typedef struct CPUCaches
{
1537 CPUCacheInfo
*l1d_cache
;
1538 CPUCacheInfo
*l1i_cache
;
1539 CPUCacheInfo
*l2_cache
;
1540 CPUCacheInfo
*l3_cache
;
1543 typedef struct HVFX86LazyFlags
{
1544 target_ulong result
;
1545 target_ulong auxbits
;
1548 typedef struct CPUArchState
{
1549 /* standard registers */
1550 target_ulong regs
[CPU_NB_REGS
];
1552 target_ulong eflags
; /* eflags register. During CPU emulation, CC
1553 flags and DF are set to zero because they are
1556 /* emulator internal eflags handling */
1557 target_ulong cc_dst
;
1558 target_ulong cc_src
;
1559 target_ulong cc_src2
;
1561 int32_t df
; /* D flag : 1 if D = 0, -1 if D = 1 */
1562 uint32_t hflags
; /* TB flags, see HF_xxx constants. These flags
1563 are known at translation time. */
1564 uint32_t hflags2
; /* various other flags, see HF2_xxx constants. */
1567 SegmentCache segs
[6]; /* selector values */
1570 SegmentCache gdt
; /* only base and limit are used */
1571 SegmentCache idt
; /* only base and limit are used */
1573 target_ulong cr
[5]; /* NOTE: cr1 is unused */
1580 BNDCSReg bndcs_regs
;
1581 uint64_t msr_bndcfgs
;
1584 /* Beginning of state preserved by INIT (dummy marker). */
1585 struct {} start_init_save
;
1588 unsigned int fpstt
; /* top of stack index */
1591 uint8_t fptags
[8]; /* 0 = valid, 1 = empty */
1593 /* KVM-only so far */
1600 /* emulator internal variables */
1601 float_status fp_status
;
1604 float_status mmx_status
; /* for 3DNow! float ops */
1605 float_status sse_status
;
1607 ZMMReg xmm_regs
[CPU_NB_REGS
== 8 ? 8 : 32] QEMU_ALIGNED(16);
1608 ZMMReg xmm_t0
QEMU_ALIGNED(16);
1611 uint64_t opmask_regs
[NB_OPMASK_REGS
];
1612 #ifdef TARGET_X86_64
1613 uint8_t xtilecfg
[64];
1614 uint8_t xtiledata
[8192];
1617 /* sysenter registers */
1618 uint32_t sysenter_cs
;
1619 target_ulong sysenter_esp
;
1620 target_ulong sysenter_eip
;
1625 #ifdef TARGET_X86_64
1629 target_ulong kernelgsbase
;
1632 uint64_t tsc_adjust
;
1633 uint64_t tsc_deadline
;
1638 uint64_t mcg_status
;
1639 uint64_t msr_ia32_misc_enable
;
1640 uint64_t msr_ia32_feature_control
;
1641 uint64_t msr_ia32_sgxlepubkeyhash
[4];
1643 uint64_t msr_fixed_ctr_ctrl
;
1644 uint64_t msr_global_ctrl
;
1645 uint64_t msr_global_status
;
1646 uint64_t msr_global_ovf_ctrl
;
1647 uint64_t msr_fixed_counters
[MAX_FIXED_COUNTERS
];
1648 uint64_t msr_gp_counters
[MAX_GP_COUNTERS
];
1649 uint64_t msr_gp_evtsel
[MAX_GP_COUNTERS
];
1653 uint64_t msr_smi_count
;
1660 uint64_t amd_tsc_scale_msr
;
1663 /* End of state preserved by INIT (dummy marker). */
1664 struct {} end_init_save
;
1666 uint64_t system_time_msr
;
1667 uint64_t wall_clock_msr
;
1668 uint64_t steal_time_msr
;
1669 uint64_t async_pf_en_msr
;
1670 uint64_t async_pf_int_msr
;
1671 uint64_t pv_eoi_en_msr
;
1672 uint64_t poll_control_msr
;
1674 /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1675 uint64_t msr_hv_hypercall
;
1676 uint64_t msr_hv_guest_os_id
;
1677 uint64_t msr_hv_tsc
;
1678 uint64_t msr_hv_syndbg_control
;
1679 uint64_t msr_hv_syndbg_status
;
1680 uint64_t msr_hv_syndbg_send_page
;
1681 uint64_t msr_hv_syndbg_recv_page
;
1682 uint64_t msr_hv_syndbg_pending_page
;
1683 uint64_t msr_hv_syndbg_options
;
1685 /* Per-VCPU HV MSRs */
1686 uint64_t msr_hv_vapic
;
1687 uint64_t msr_hv_crash_params
[HV_CRASH_PARAMS
];
1688 uint64_t msr_hv_runtime
;
1689 uint64_t msr_hv_synic_control
;
1690 uint64_t msr_hv_synic_evt_page
;
1691 uint64_t msr_hv_synic_msg_page
;
1692 uint64_t msr_hv_synic_sint
[HV_SINT_COUNT
];
1693 uint64_t msr_hv_stimer_config
[HV_STIMER_COUNT
];
1694 uint64_t msr_hv_stimer_count
[HV_STIMER_COUNT
];
1695 uint64_t msr_hv_reenlightenment_control
;
1696 uint64_t msr_hv_tsc_emulation_control
;
1697 uint64_t msr_hv_tsc_emulation_status
;
1699 uint64_t msr_rtit_ctrl
;
1700 uint64_t msr_rtit_status
;
1701 uint64_t msr_rtit_output_base
;
1702 uint64_t msr_rtit_output_mask
;
1703 uint64_t msr_rtit_cr3_match
;
1704 uint64_t msr_rtit_addrs
[MAX_RTIT_ADDRS
];
1706 /* Per-VCPU XFD MSRs */
1708 uint64_t msr_xfd_err
;
1710 /* Per-VCPU Arch LBR MSRs */
1711 uint64_t msr_lbr_ctl
;
1712 uint64_t msr_lbr_depth
;
1713 LBREntry lbr_records
[ARCH_LBR_NR_ENTRIES
];
1715 /* exception/interrupt handling */
1717 int exception_is_int
;
1718 target_ulong exception_next_eip
;
1719 target_ulong dr
[8]; /* debug registers; note dr4 and dr5 are unused */
1721 struct CPUBreakpoint
*cpu_breakpoint
[4];
1722 struct CPUWatchpoint
*cpu_watchpoint
[4];
1723 }; /* break/watchpoints for dr[0..3] */
1724 int old_exception
; /* exception in flight */
1727 uint64_t tsc_offset
;
1729 uint16_t intercept_cr_read
;
1730 uint16_t intercept_cr_write
;
1731 uint16_t intercept_dr_read
;
1732 uint16_t intercept_dr_write
;
1733 uint32_t intercept_exceptions
;
1734 uint64_t nested_cr3
;
1735 uint32_t nested_pg_mode
;
1739 /* KVM states, automatically cleared on reset */
1740 uint8_t nmi_injected
;
1741 uint8_t nmi_pending
;
1745 /* Fields up to this point are cleared by a CPU reset */
1746 struct {} end_reset_fields
;
1748 /* Fields after this point are preserved across CPU reset. */
1750 /* processor features (e.g. for CPUID insn) */
1751 /* Minimum cpuid leaf 7 value */
1752 uint32_t cpuid_level_func7
;
1753 /* Actual cpuid leaf 7 value */
1754 uint32_t cpuid_min_level_func7
;
1755 /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1756 uint32_t cpuid_min_level
, cpuid_min_xlevel
, cpuid_min_xlevel2
;
1757 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1758 uint32_t cpuid_max_level
, cpuid_max_xlevel
, cpuid_max_xlevel2
;
1759 /* Actual level/xlevel/xlevel2 value: */
1760 uint32_t cpuid_level
, cpuid_xlevel
, cpuid_xlevel2
;
1761 uint32_t cpuid_vendor1
;
1762 uint32_t cpuid_vendor2
;
1763 uint32_t cpuid_vendor3
;
1764 uint32_t cpuid_version
;
1765 FeatureWordArray features
;
1766 /* Features that were explicitly enabled/disabled */
1767 FeatureWordArray user_features
;
1768 uint32_t cpuid_model
[12];
1769 /* Cache information for CPUID. When legacy-cache=on, the cache data
1770 * on each CPUID leaf will be different, because we keep compatibility
1771 * with old QEMU versions.
1773 CPUCaches cache_info_cpuid2
, cache_info_cpuid4
, cache_info_amd
;
1776 uint64_t mtrr_fixed
[11];
1777 uint64_t mtrr_deftype
;
1778 MTRRVar mtrr_var
[MSR_MTRRcap_VCNT
];
1782 int32_t exception_nr
;
1783 int32_t interrupt_injected
;
1784 uint8_t soft_interrupt
;
1785 uint8_t exception_pending
;
1786 uint8_t exception_injected
;
1787 uint8_t has_error_code
;
1788 uint8_t exception_has_payload
;
1789 uint64_t exception_payload
;
1790 uint8_t triple_fault_pending
;
1792 uint32_t sipi_vector
;
1795 int64_t user_tsc_khz
; /* for sanity check only */
1796 uint64_t apic_bus_freq
;
1798 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1800 uint32_t xsave_buf_len
;
1802 #if defined(CONFIG_KVM)
1803 struct kvm_nested_state
*nested_state
;
1804 MemoryRegion
*xen_vcpu_info_mr
;
1805 void *xen_vcpu_info_hva
;
1806 uint64_t xen_vcpu_info_gpa
;
1807 uint64_t xen_vcpu_info_default_gpa
;
1808 uint64_t xen_vcpu_time_info_gpa
;
1809 uint64_t xen_vcpu_runstate_gpa
;
1810 uint8_t xen_vcpu_callback_vector
;
1811 uint16_t xen_virq
[XEN_NR_VIRQS
];
1812 uint64_t xen_singleshot_timer_ns
;
1814 #if defined(CONFIG_HVF)
1815 HVFX86LazyFlags hvf_lflags
;
1821 uint64_t mcg_ext_ctl
;
1822 uint64_t mce_banks
[MCE_BANKS_DEF
*4];
1826 uint16_t fpus_vmstate
;
1827 uint16_t fptag_vmstate
;
1828 uint16_t fpregs_format_vmstate
;
1833 TPRAccess tpr_access_type
;
1842 * @env: #CPUX86State
1843 * @migratable: If set, only migratable flags will be accepted when "enforce"
1844 * mode is used, and only migratable flags will be included in the "host"
1851 CPUState parent_obj
;
1854 CPUNegativeOffsetState neg
;
1856 VMChangeStateEntry
*vmsentry
;
1860 uint32_t hyperv_spinlock_attempts
;
1861 char *hyperv_vendor
;
1862 bool hyperv_synic_kvm_only
;
1863 uint64_t hyperv_features
;
1864 bool hyperv_passthrough
;
1865 OnOffAuto hyperv_no_nonarch_cs
;
1866 uint32_t hyperv_vendor_id
[3];
1867 uint32_t hyperv_interface_id
[4];
1868 uint32_t hyperv_limits
[3];
1869 bool hyperv_enforce_cpuid
;
1870 uint32_t hyperv_ver_id_build
;
1871 uint16_t hyperv_ver_id_major
;
1872 uint16_t hyperv_ver_id_minor
;
1873 uint32_t hyperv_ver_id_sp
;
1874 uint8_t hyperv_ver_id_sb
;
1875 uint32_t hyperv_ver_id_sn
;
1880 * Force features to be enabled even if the host doesn't support them.
1881 * This is dangerous and should be done only for testing CPUID
1884 bool force_features
;
1888 bool migrate_smi_count
;
1889 bool max_features
; /* Enable all supported features automatically */
1892 /* Enables publishing of TSC increment and Local APIC bus frequencies to
1893 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
1894 bool vmware_cpuid_freq
;
1896 /* if true the CPUID code directly forward host cache leaves to the guest */
1897 bool cache_info_passthrough
;
1899 /* if true the CPUID code directly forwards
1900 * host monitor/mwait leaves to the guest */
1908 /* Features that were filtered out because of missing host capabilities */
1909 FeatureWordArray filtered_features
;
1911 /* Enable PMU CPUID bits. This can't be enabled by default yet because
1912 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
1913 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
1914 * capabilities) directly to the guest.
1919 * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR.
1920 * This can't be initialized with a default because it doesn't have
1921 * stable ABI support yet. It is only allowed to pass all LBR_FMT bits
1922 * returned by kvm_arch_get_supported_msr_feature()(which depends on both
1923 * host CPU and kernel capabilities) to the guest.
1927 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
1928 * disabled by default to avoid breaking migration between QEMU with
1929 * different LMCE configurations.
1933 /* Compatibility bits for old machine types.
1934 * If true present virtual l3 cache for VM, the vcpus in the same virtual
1935 * socket share an virtual l3 cache.
1937 bool enable_l3_cache
;
1939 /* Compatibility bits for old machine types.
1940 * If true present the old cache topology information
1944 /* Compatibility bits for old machine types: */
1945 bool enable_cpuid_0xb
;
1947 /* Enable auto level-increase for all CPUID leaves */
1948 bool full_cpuid_auto_level
;
1950 /* Only advertise CPUID leaves defined by the vendor */
1951 bool vendor_cpuid_only
;
1953 /* Enable auto level-increase for Intel Processor Trace leave */
1954 bool intel_pt_auto_level
;
1956 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
1957 bool fill_mtrr_mask
;
1959 /* if true override the phys_bits value with a value read from the host */
1960 bool host_phys_bits
;
1962 /* if set, limit maximum value for phys_bits when host_phys_bits is true */
1963 uint8_t host_phys_bits_limit
;
1965 /* Stop SMI delivery for migration compatibility with old machines */
1966 bool kvm_no_smi_migration
;
1968 /* Forcefully disable KVM PV features not exposed in guest CPUIDs */
1969 bool kvm_pv_enforce_cpuid
;
1971 /* Number of physical address bits supported */
1974 /* in order to simplify APIC support, we leave this pointer to the
1976 struct DeviceState
*apic_state
;
1977 struct MemoryRegion
*cpu_as_root
, *cpu_as_mem
, *smram
;
1978 Notifier machine_done
;
1980 struct kvm_msrs
*kvm_msr_buf
;
1982 int32_t node_id
; /* NUMA node this CPU belongs to */
1994 #ifndef CONFIG_USER_ONLY
1995 extern const VMStateDescription vmstate_x86_cpu
;
1998 int x86_cpu_pending_interrupt(CPUState
*cs
, int interrupt_request
);
2000 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
2001 int cpuid
, DumpState
*s
);
2002 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
2003 int cpuid
, DumpState
*s
);
2004 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
2006 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
2009 void x86_cpu_get_memory_mapping(CPUState
*cpu
, MemoryMappingList
*list
,
2012 void x86_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
);
2014 int x86_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
2015 int x86_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
2017 void x86_cpu_list(void);
2018 int cpu_x86_support_mca_broadcast(CPUX86State
*env
);
2020 #ifndef CONFIG_USER_ONLY
2021 hwaddr
x86_cpu_get_phys_page_attrs_debug(CPUState
*cpu
, vaddr addr
,
2023 int cpu_get_pic_interrupt(CPUX86State
*s
);
2025 /* MSDOS compatibility mode FPU exception support */
2026 void x86_register_ferr_irq(qemu_irq irq
);
2027 void fpu_check_raise_ferr_irq(CPUX86State
*s
);
2028 void cpu_set_ignne(void);
2029 void cpu_clear_ignne(void);
2033 void cpu_sync_bndcs_hflags(CPUX86State
*env
);
2035 /* this function must always be used to load data in the segment
2036 cache: it synchronizes the hflags with the segment cache values */
2037 static inline void cpu_x86_load_seg_cache(CPUX86State
*env
,
2038 X86Seg seg_reg
, unsigned int selector
,
2044 unsigned int new_hflags
;
2046 sc
= &env
->segs
[seg_reg
];
2047 sc
->selector
= selector
;
2052 /* update the hidden flags */
2054 if (seg_reg
== R_CS
) {
2055 #ifdef TARGET_X86_64
2056 if ((env
->hflags
& HF_LMA_MASK
) && (flags
& DESC_L_MASK
)) {
2058 env
->hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
2059 env
->hflags
&= ~(HF_ADDSEG_MASK
);
2063 /* legacy / compatibility case */
2064 new_hflags
= (env
->segs
[R_CS
].flags
& DESC_B_MASK
)
2065 >> (DESC_B_SHIFT
- HF_CS32_SHIFT
);
2066 env
->hflags
= (env
->hflags
& ~(HF_CS32_MASK
| HF_CS64_MASK
)) |
2070 if (seg_reg
== R_SS
) {
2071 int cpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
2072 #if HF_CPL_MASK != 3
2073 #error HF_CPL_MASK is hardcoded
2075 env
->hflags
= (env
->hflags
& ~HF_CPL_MASK
) | cpl
;
2076 /* Possibly switch between BNDCFGS and BNDCFGU */
2077 cpu_sync_bndcs_hflags(env
);
2079 new_hflags
= (env
->segs
[R_SS
].flags
& DESC_B_MASK
)
2080 >> (DESC_B_SHIFT
- HF_SS32_SHIFT
);
2081 if (env
->hflags
& HF_CS64_MASK
) {
2082 /* zero base assumed for DS, ES and SS in long mode */
2083 } else if (!(env
->cr
[0] & CR0_PE_MASK
) ||
2084 (env
->eflags
& VM_MASK
) ||
2085 !(env
->hflags
& HF_CS32_MASK
)) {
2086 /* XXX: try to avoid this test. The problem comes from the
2087 fact that is real mode or vm86 mode we only modify the
2088 'base' and 'selector' fields of the segment cache to go
2089 faster. A solution may be to force addseg to one in
2090 translate-i386.c. */
2091 new_hflags
|= HF_ADDSEG_MASK
;
2093 new_hflags
|= ((env
->segs
[R_DS
].base
|
2094 env
->segs
[R_ES
].base
|
2095 env
->segs
[R_SS
].base
) != 0) <<
2098 env
->hflags
= (env
->hflags
&
2099 ~(HF_SS32_MASK
| HF_ADDSEG_MASK
)) | new_hflags
;
2103 static inline void cpu_x86_load_seg_cache_sipi(X86CPU
*cpu
,
2104 uint8_t sipi_vector
)
2106 CPUState
*cs
= CPU(cpu
);
2107 CPUX86State
*env
= &cpu
->env
;
2110 cpu_x86_load_seg_cache(env
, R_CS
, sipi_vector
<< 8,
2112 env
->segs
[R_CS
].limit
,
2113 env
->segs
[R_CS
].flags
);
2117 int cpu_x86_get_descr_debug(CPUX86State
*env
, unsigned int selector
,
2118 target_ulong
*base
, unsigned int *limit
,
2119 unsigned int *flags
);
2122 /* used for debug or cpu save/restore */
2125 /* the following helpers are only usable in user mode simulation as
2126 they can trigger unexpected exceptions */
2127 void cpu_x86_load_seg(CPUX86State
*s
, X86Seg seg_reg
, int selector
);
2128 void cpu_x86_fsave(CPUX86State
*s
, target_ulong ptr
, int data32
);
2129 void cpu_x86_frstor(CPUX86State
*s
, target_ulong ptr
, int data32
);
2130 void cpu_x86_fxsave(CPUX86State
*s
, target_ulong ptr
);
2131 void cpu_x86_fxrstor(CPUX86State
*s
, target_ulong ptr
);
2132 void cpu_x86_xsave(CPUX86State
*s
, target_ulong ptr
);
2133 void cpu_x86_xrstor(CPUX86State
*s
, target_ulong ptr
);
2136 void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
2137 uint32_t vendor2
, uint32_t vendor3
);
2138 typedef struct PropValue
{
2139 const char *prop
, *value
;
2141 void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
);
2143 void x86_cpu_after_reset(X86CPU
*cpu
);
2145 uint32_t cpu_x86_virtual_addr_width(CPUX86State
*env
);
2147 /* cpu.c other functions (cpuid) */
2148 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
2149 uint32_t *eax
, uint32_t *ebx
,
2150 uint32_t *ecx
, uint32_t *edx
);
2151 void cpu_clear_apic_feature(CPUX86State
*env
);
2152 void host_cpuid(uint32_t function
, uint32_t count
,
2153 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
);
2156 void x86_cpu_set_a20(X86CPU
*cpu
, int a20_state
);
2157 void cpu_sync_avx_hflag(CPUX86State
*env
);
2159 #ifndef CONFIG_USER_ONLY
2160 static inline int x86_asidx_from_attrs(CPUState
*cs
, MemTxAttrs attrs
)
2162 return !!attrs
.secure
;
2165 static inline AddressSpace
*cpu_addressspace(CPUState
*cs
, MemTxAttrs attrs
)
2167 return cpu_get_address_space(cs
, cpu_asidx_from_attrs(cs
, attrs
));
2171 * load efer and update the corresponding hflags. XXX: do consistency
2172 * checks with cpuid bits?
2174 void cpu_load_efer(CPUX86State
*env
, uint64_t val
);
2175 uint8_t x86_ldub_phys(CPUState
*cs
, hwaddr addr
);
2176 uint32_t x86_lduw_phys(CPUState
*cs
, hwaddr addr
);
2177 uint32_t x86_ldl_phys(CPUState
*cs
, hwaddr addr
);
2178 uint64_t x86_ldq_phys(CPUState
*cs
, hwaddr addr
);
2179 void x86_stb_phys(CPUState
*cs
, hwaddr addr
, uint8_t val
);
2180 void x86_stl_phys_notdirty(CPUState
*cs
, hwaddr addr
, uint32_t val
);
2181 void x86_stw_phys(CPUState
*cs
, hwaddr addr
, uint32_t val
);
2182 void x86_stl_phys(CPUState
*cs
, hwaddr addr
, uint32_t val
);
2183 void x86_stq_phys(CPUState
*cs
, hwaddr addr
, uint64_t val
);
2186 /* will be suppressed */
2187 void cpu_x86_update_cr0(CPUX86State
*env
, uint32_t new_cr0
);
2188 void cpu_x86_update_cr3(CPUX86State
*env
, target_ulong new_cr3
);
2189 void cpu_x86_update_cr4(CPUX86State
*env
, uint32_t new_cr4
);
2190 void cpu_x86_update_dr7(CPUX86State
*env
, uint32_t new_dr7
);
2193 uint64_t cpu_get_tsc(CPUX86State
*env
);
2195 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
2196 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
2197 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
2199 #ifdef TARGET_X86_64
2200 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
2202 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
2205 #define cpu_list x86_cpu_list
2207 /* MMU modes definitions */
2208 #define MMU_KSMAP_IDX 0
2209 #define MMU_USER_IDX 1
2210 #define MMU_KNOSMAP_IDX 2
2211 #define MMU_NESTED_IDX 3
2212 #define MMU_PHYS_IDX 4
2214 static inline int cpu_mmu_index(CPUX86State
*env
, bool ifetch
)
2216 return (env
->hflags
& HF_CPL_MASK
) == 3 ? MMU_USER_IDX
:
2217 (!(env
->hflags
& HF_SMAP_MASK
) || (env
->eflags
& AC_MASK
))
2218 ? MMU_KNOSMAP_IDX
: MMU_KSMAP_IDX
;
2221 static inline int cpu_mmu_index_kernel(CPUX86State
*env
)
2223 return !(env
->hflags
& HF_SMAP_MASK
) ? MMU_KNOSMAP_IDX
:
2224 ((env
->hflags
& HF_CPL_MASK
) < 3 && (env
->eflags
& AC_MASK
))
2225 ? MMU_KNOSMAP_IDX
: MMU_KSMAP_IDX
;
2228 #define CC_DST (env->cc_dst)
2229 #define CC_SRC (env->cc_src)
2230 #define CC_SRC2 (env->cc_src2)
2231 #define CC_OP (env->cc_op)
2233 #include "exec/cpu-all.h"
2236 #if !defined(CONFIG_USER_ONLY)
2237 #include "hw/i386/apic.h"
2240 static inline void cpu_get_tb_cpu_state(CPUX86State
*env
, target_ulong
*pc
,
2241 target_ulong
*cs_base
, uint32_t *flags
)
2243 *cs_base
= env
->segs
[R_CS
].base
;
2244 *pc
= *cs_base
+ env
->eip
;
2245 *flags
= env
->hflags
|
2246 (env
->eflags
& (IOPL_MASK
| TF_MASK
| RF_MASK
| VM_MASK
| AC_MASK
));
2249 void do_cpu_init(X86CPU
*cpu
);
2250 void do_cpu_sipi(X86CPU
*cpu
);
2252 #define MCE_INJECT_BROADCAST 1
2253 #define MCE_INJECT_UNCOND_AO 2
2255 void cpu_x86_inject_mce(Monitor
*mon
, X86CPU
*cpu
, int bank
,
2256 uint64_t status
, uint64_t mcg_status
, uint64_t addr
,
2257 uint64_t misc
, int flags
);
2259 uint32_t cpu_cc_compute_all(CPUX86State
*env1
, int op
);
2261 static inline uint32_t cpu_compute_eflags(CPUX86State
*env
)
2263 uint32_t eflags
= env
->eflags
;
2264 if (tcg_enabled()) {
2265 eflags
|= cpu_cc_compute_all(env
, CC_OP
) | (env
->df
& DF_MASK
);
2270 static inline MemTxAttrs
cpu_get_mem_attrs(CPUX86State
*env
)
2272 return ((MemTxAttrs
) { .secure
= (env
->hflags
& HF_SMM_MASK
) != 0 });
2275 static inline int32_t x86_get_a20_mask(CPUX86State
*env
)
2277 if (env
->hflags
& HF_SMM_MASK
) {
2280 return env
->a20_mask
;
2284 static inline bool cpu_has_vmx(CPUX86State
*env
)
2286 return env
->features
[FEAT_1_ECX
] & CPUID_EXT_VMX
;
2289 static inline bool cpu_has_svm(CPUX86State
*env
)
2291 return env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
;
2295 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
2296 * Since it was set, CR4.VMXE must remain set as long as vCPU is in
2297 * VMX operation. This is because CR4.VMXE is one of the bits set
2298 * in MSR_IA32_VMX_CR4_FIXED1.
2300 * There is one exception to above statement when vCPU enters SMM mode.
2301 * When a vCPU enters SMM mode, it temporarily exit VMX operation and
2302 * may also reset CR4.VMXE during execution in SMM mode.
2303 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation
2304 * and CR4.VMXE is restored to it's original value of being set.
2306 * Therefore, when vCPU is not in SMM mode, we can infer whether
2307 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot
2310 static inline bool cpu_vmx_maybe_enabled(CPUX86State
*env
)
2312 return cpu_has_vmx(env
) &&
2313 ((env
->cr
[4] & CR4_VMXE_MASK
) || (env
->hflags
& HF_SMM_MASK
));
2317 int get_pg_mode(CPUX86State
*env
);
2320 void update_fp_status(CPUX86State
*env
);
2321 void update_mxcsr_status(CPUX86State
*env
);
2322 void update_mxcsr_from_sse_status(CPUX86State
*env
);
2324 static inline void cpu_set_mxcsr(CPUX86State
*env
, uint32_t mxcsr
)
2327 if (tcg_enabled()) {
2328 update_mxcsr_status(env
);
2332 static inline void cpu_set_fpuc(CPUX86State
*env
, uint16_t fpuc
)
2335 if (tcg_enabled()) {
2336 update_fp_status(env
);
2341 #ifdef CONFIG_USER_ONLY
2343 cpu_svm_check_intercept_param(CPUX86State
*env1
, uint32_t type
,
2344 uint64_t param
, uintptr_t retaddr
)
2347 cpu_svm_has_intercept(CPUX86State
*env
, uint32_t type
)
2350 void cpu_svm_check_intercept_param(CPUX86State
*env1
, uint32_t type
,
2351 uint64_t param
, uintptr_t retaddr
);
2352 bool cpu_svm_has_intercept(CPUX86State
*env
, uint32_t type
);
2356 void cpu_report_tpr_access(CPUX86State
*env
, TPRAccess access
);
2357 void apic_handle_tpr_access_report(DeviceState
*d
, target_ulong ip
,
2360 /* Special values for X86CPUVersion: */
2362 /* Resolve to latest CPU version */
2363 #define CPU_VERSION_LATEST -1
2366 * Resolve to version defined by current machine type.
2367 * See x86_cpu_set_default_version()
2369 #define CPU_VERSION_AUTO -2
2371 /* Don't resolve to any versioned CPU models, like old QEMU versions */
2372 #define CPU_VERSION_LEGACY 0
2374 typedef int X86CPUVersion
;
2377 * Set default CPU model version for CPU models having
2378 * version == CPU_VERSION_AUTO.
2380 void x86_cpu_set_default_version(X86CPUVersion version
);
2382 #ifndef CONFIG_USER_ONLY
2384 #define APIC_DEFAULT_ADDRESS 0xfee00000
2385 #define APIC_SPACE_SIZE 0x100000
2388 void x86_cpu_dump_local_apic_state(CPUState
*cs
, int flags
);
2393 bool cpu_is_bsp(X86CPU
*cpu
);
2395 void x86_cpu_xrstor_all_areas(X86CPU
*cpu
, const void *buf
, uint32_t buflen
);
2396 void x86_cpu_xsave_all_areas(X86CPU
*cpu
, void *buf
, uint32_t buflen
);
2397 uint32_t xsave_area_size(uint64_t mask
, bool compacted
);
2398 void x86_update_hflags(CPUX86State
* env
);
2400 static inline bool hyperv_feat_enabled(X86CPU
*cpu
, int feat
)
2402 return !!(cpu
->hyperv_features
& BIT(feat
));
2405 static inline uint64_t cr4_reserved_bits(CPUX86State
*env
)
2407 uint64_t reserved_bits
= CR4_RESERVED_MASK
;
2408 if (!env
->features
[FEAT_XSAVE
]) {
2409 reserved_bits
|= CR4_OSXSAVE_MASK
;
2411 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_SMEP
)) {
2412 reserved_bits
|= CR4_SMEP_MASK
;
2414 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_SMAP
)) {
2415 reserved_bits
|= CR4_SMAP_MASK
;
2417 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
)) {
2418 reserved_bits
|= CR4_FSGSBASE_MASK
;
2420 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_PKU
)) {
2421 reserved_bits
|= CR4_PKE_MASK
;
2423 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
)) {
2424 reserved_bits
|= CR4_LA57_MASK
;
2426 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_UMIP
)) {
2427 reserved_bits
|= CR4_UMIP_MASK
;
2429 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_PKS
)) {
2430 reserved_bits
|= CR4_PKS_MASK
;
2432 return reserved_bits
;
2435 static inline bool ctl_has_irq(CPUX86State
*env
)
2440 int_prio
= (env
->int_ctl
& V_INTR_PRIO_MASK
) >> V_INTR_PRIO_SHIFT
;
2441 tpr
= env
->int_ctl
& V_TPR_MASK
;
2443 if (env
->int_ctl
& V_IGN_TPR_MASK
) {
2444 return (env
->int_ctl
& V_IRQ_MASK
);
2447 return (env
->int_ctl
& V_IRQ_MASK
) && (int_prio
>= tpr
);
2450 #if defined(TARGET_X86_64) && \
2451 defined(CONFIG_USER_ONLY) && \
2452 defined(CONFIG_LINUX)
2453 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20)
2456 #endif /* I386_CPU_H */