2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
25 #include "hyperv-proto.h"
28 #define TARGET_LONG_BITS 64
30 #define TARGET_LONG_BITS 32
33 /* The x86 has a strong memory model with some store-after-load re-ordering */
34 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
36 /* Maximum instruction code size */
37 #define TARGET_MAX_INSN_SIZE 16
39 /* support for self modifying code even if the modified instruction is
40 close to the modifying instruction */
41 #define TARGET_HAS_PRECISE_SMC
44 #define I386_ELF_MACHINE EM_X86_64
45 #define ELF_MACHINE_UNAME "x86_64"
47 #define I386_ELF_MACHINE EM_386
48 #define ELF_MACHINE_UNAME "i686"
51 #define CPUArchState struct CPUX86State
53 #include "exec/cpu-defs.h"
56 #include "fpu/softfloat.h"
84 /* segment descriptor fields */
85 #define DESC_G_MASK (1 << 23)
86 #define DESC_B_SHIFT 22
87 #define DESC_B_MASK (1 << DESC_B_SHIFT)
88 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
89 #define DESC_L_MASK (1 << DESC_L_SHIFT)
90 #define DESC_AVL_MASK (1 << 20)
91 #define DESC_P_MASK (1 << 15)
92 #define DESC_DPL_SHIFT 13
93 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
94 #define DESC_S_MASK (1 << 12)
95 #define DESC_TYPE_SHIFT 8
96 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
97 #define DESC_A_MASK (1 << 8)
99 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
100 #define DESC_C_MASK (1 << 10) /* code: conforming */
101 #define DESC_R_MASK (1 << 9) /* code: readable */
103 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
104 #define DESC_W_MASK (1 << 9) /* data: writable */
106 #define DESC_TSS_BUSY_MASK (1 << 9)
117 #define IOPL_SHIFT 12
120 #define TF_MASK 0x00000100
121 #define IF_MASK 0x00000200
122 #define DF_MASK 0x00000400
123 #define IOPL_MASK 0x00003000
124 #define NT_MASK 0x00004000
125 #define RF_MASK 0x00010000
126 #define VM_MASK 0x00020000
127 #define AC_MASK 0x00040000
128 #define VIF_MASK 0x00080000
129 #define VIP_MASK 0x00100000
130 #define ID_MASK 0x00200000
132 /* hidden flags - used internally by qemu to represent additional cpu
133 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
134 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
135 positions to ease oring with eflags. */
137 #define HF_CPL_SHIFT 0
138 /* true if hardware interrupts must be disabled for next instruction */
139 #define HF_INHIBIT_IRQ_SHIFT 3
140 /* 16 or 32 segments */
141 #define HF_CS32_SHIFT 4
142 #define HF_SS32_SHIFT 5
143 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
144 #define HF_ADDSEG_SHIFT 6
145 /* copy of CR0.PE (protected mode) */
146 #define HF_PE_SHIFT 7
147 #define HF_TF_SHIFT 8 /* must be same as eflags */
148 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
149 #define HF_EM_SHIFT 10
150 #define HF_TS_SHIFT 11
151 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
152 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
153 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
154 #define HF_RF_SHIFT 16 /* must be same as eflags */
155 #define HF_VM_SHIFT 17 /* must be same as eflags */
156 #define HF_AC_SHIFT 18 /* must be same as eflags */
157 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
158 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
159 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */
160 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
161 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
162 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
163 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
164 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
166 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
167 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
168 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
169 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
170 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
171 #define HF_PE_MASK (1 << HF_PE_SHIFT)
172 #define HF_TF_MASK (1 << HF_TF_SHIFT)
173 #define HF_MP_MASK (1 << HF_MP_SHIFT)
174 #define HF_EM_MASK (1 << HF_EM_SHIFT)
175 #define HF_TS_MASK (1 << HF_TS_SHIFT)
176 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
177 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
178 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
179 #define HF_RF_MASK (1 << HF_RF_SHIFT)
180 #define HF_VM_MASK (1 << HF_VM_SHIFT)
181 #define HF_AC_MASK (1 << HF_AC_SHIFT)
182 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
183 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
184 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
185 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
186 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
187 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
188 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
189 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
193 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
194 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
195 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
196 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
197 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
198 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
200 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
201 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
202 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
203 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
204 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
205 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
207 #define CR0_PE_SHIFT 0
208 #define CR0_MP_SHIFT 1
210 #define CR0_PE_MASK (1U << 0)
211 #define CR0_MP_MASK (1U << 1)
212 #define CR0_EM_MASK (1U << 2)
213 #define CR0_TS_MASK (1U << 3)
214 #define CR0_ET_MASK (1U << 4)
215 #define CR0_NE_MASK (1U << 5)
216 #define CR0_WP_MASK (1U << 16)
217 #define CR0_AM_MASK (1U << 18)
218 #define CR0_PG_MASK (1U << 31)
220 #define CR4_VME_MASK (1U << 0)
221 #define CR4_PVI_MASK (1U << 1)
222 #define CR4_TSD_MASK (1U << 2)
223 #define CR4_DE_MASK (1U << 3)
224 #define CR4_PSE_MASK (1U << 4)
225 #define CR4_PAE_MASK (1U << 5)
226 #define CR4_MCE_MASK (1U << 6)
227 #define CR4_PGE_MASK (1U << 7)
228 #define CR4_PCE_MASK (1U << 8)
229 #define CR4_OSFXSR_SHIFT 9
230 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
231 #define CR4_OSXMMEXCPT_MASK (1U << 10)
232 #define CR4_LA57_MASK (1U << 12)
233 #define CR4_VMXE_MASK (1U << 13)
234 #define CR4_SMXE_MASK (1U << 14)
235 #define CR4_FSGSBASE_MASK (1U << 16)
236 #define CR4_PCIDE_MASK (1U << 17)
237 #define CR4_OSXSAVE_MASK (1U << 18)
238 #define CR4_SMEP_MASK (1U << 20)
239 #define CR4_SMAP_MASK (1U << 21)
240 #define CR4_PKE_MASK (1U << 22)
242 #define DR6_BD (1 << 13)
243 #define DR6_BS (1 << 14)
244 #define DR6_BT (1 << 15)
245 #define DR6_FIXED_1 0xffff0ff0
247 #define DR7_GD (1 << 13)
248 #define DR7_TYPE_SHIFT 16
249 #define DR7_LEN_SHIFT 18
250 #define DR7_FIXED_1 0x00000400
251 #define DR7_GLOBAL_BP_MASK 0xaa
252 #define DR7_LOCAL_BP_MASK 0x55
254 #define DR7_TYPE_BP_INST 0x0
255 #define DR7_TYPE_DATA_WR 0x1
256 #define DR7_TYPE_IO_RW 0x2
257 #define DR7_TYPE_DATA_RW 0x3
259 #define PG_PRESENT_BIT 0
261 #define PG_USER_BIT 2
264 #define PG_ACCESSED_BIT 5
265 #define PG_DIRTY_BIT 6
267 #define PG_GLOBAL_BIT 8
268 #define PG_PSE_PAT_BIT 12
269 #define PG_PKRU_BIT 59
272 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
273 #define PG_RW_MASK (1 << PG_RW_BIT)
274 #define PG_USER_MASK (1 << PG_USER_BIT)
275 #define PG_PWT_MASK (1 << PG_PWT_BIT)
276 #define PG_PCD_MASK (1 << PG_PCD_BIT)
277 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
278 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
279 #define PG_PSE_MASK (1 << PG_PSE_BIT)
280 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
281 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
282 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
283 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
284 #define PG_HI_USER_MASK 0x7ff0000000000000LL
285 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
286 #define PG_NX_MASK (1ULL << PG_NX_BIT)
288 #define PG_ERROR_W_BIT 1
290 #define PG_ERROR_P_MASK 0x01
291 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
292 #define PG_ERROR_U_MASK 0x04
293 #define PG_ERROR_RSVD_MASK 0x08
294 #define PG_ERROR_I_D_MASK 0x10
295 #define PG_ERROR_PK_MASK 0x20
297 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
298 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
299 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
301 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
302 #define MCE_BANKS_DEF 10
304 #define MCG_CAP_BANKS_MASK 0xff
306 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
307 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
308 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
309 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */
311 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
313 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
314 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
315 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
316 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
317 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
318 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
319 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
320 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
321 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
323 /* MISC register defines */
324 #define MCM_ADDR_SEGOFF 0 /* segment offset */
325 #define MCM_ADDR_LINEAR 1 /* linear address */
326 #define MCM_ADDR_PHYS 2 /* physical address */
327 #define MCM_ADDR_MEM 3 /* memory address */
328 #define MCM_ADDR_GENERIC 7 /* generic */
330 #define MSR_IA32_TSC 0x10
331 #define MSR_IA32_APICBASE 0x1b
332 #define MSR_IA32_APICBASE_BSP (1<<8)
333 #define MSR_IA32_APICBASE_ENABLE (1<<11)
334 #define MSR_IA32_APICBASE_EXTD (1 << 10)
335 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
336 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
337 #define MSR_TSC_ADJUST 0x0000003b
338 #define MSR_IA32_TSCDEADLINE 0x6e0
340 #define FEATURE_CONTROL_LOCKED (1<<0)
341 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
342 #define FEATURE_CONTROL_LMCE (1<<20)
344 #define MSR_P6_PERFCTR0 0xc1
346 #define MSR_IA32_SMBASE 0x9e
347 #define MSR_MTRRcap 0xfe
348 #define MSR_MTRRcap_VCNT 8
349 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
350 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
352 #define MSR_IA32_SYSENTER_CS 0x174
353 #define MSR_IA32_SYSENTER_ESP 0x175
354 #define MSR_IA32_SYSENTER_EIP 0x176
356 #define MSR_MCG_CAP 0x179
357 #define MSR_MCG_STATUS 0x17a
358 #define MSR_MCG_CTL 0x17b
359 #define MSR_MCG_EXT_CTL 0x4d0
361 #define MSR_P6_EVNTSEL0 0x186
363 #define MSR_IA32_PERF_STATUS 0x198
365 #define MSR_IA32_MISC_ENABLE 0x1a0
366 /* Indicates good rep/movs microcode on some processors: */
367 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
369 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
370 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
372 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
374 #define MSR_MTRRfix64K_00000 0x250
375 #define MSR_MTRRfix16K_80000 0x258
376 #define MSR_MTRRfix16K_A0000 0x259
377 #define MSR_MTRRfix4K_C0000 0x268
378 #define MSR_MTRRfix4K_C8000 0x269
379 #define MSR_MTRRfix4K_D0000 0x26a
380 #define MSR_MTRRfix4K_D8000 0x26b
381 #define MSR_MTRRfix4K_E0000 0x26c
382 #define MSR_MTRRfix4K_E8000 0x26d
383 #define MSR_MTRRfix4K_F0000 0x26e
384 #define MSR_MTRRfix4K_F8000 0x26f
386 #define MSR_PAT 0x277
388 #define MSR_MTRRdefType 0x2ff
390 #define MSR_CORE_PERF_FIXED_CTR0 0x309
391 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
392 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
393 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
394 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
395 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
396 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
398 #define MSR_MC0_CTL 0x400
399 #define MSR_MC0_STATUS 0x401
400 #define MSR_MC0_ADDR 0x402
401 #define MSR_MC0_MISC 0x403
403 #define MSR_EFER 0xc0000080
405 #define MSR_EFER_SCE (1 << 0)
406 #define MSR_EFER_LME (1 << 8)
407 #define MSR_EFER_LMA (1 << 10)
408 #define MSR_EFER_NXE (1 << 11)
409 #define MSR_EFER_SVME (1 << 12)
410 #define MSR_EFER_FFXSR (1 << 14)
412 #define MSR_STAR 0xc0000081
413 #define MSR_LSTAR 0xc0000082
414 #define MSR_CSTAR 0xc0000083
415 #define MSR_FMASK 0xc0000084
416 #define MSR_FSBASE 0xc0000100
417 #define MSR_GSBASE 0xc0000101
418 #define MSR_KERNELGSBASE 0xc0000102
419 #define MSR_TSC_AUX 0xc0000103
421 #define MSR_VM_HSAVE_PA 0xc0010117
423 #define MSR_IA32_BNDCFGS 0x00000d90
424 #define MSR_IA32_XSS 0x00000da0
426 #define XSTATE_FP_BIT 0
427 #define XSTATE_SSE_BIT 1
428 #define XSTATE_YMM_BIT 2
429 #define XSTATE_BNDREGS_BIT 3
430 #define XSTATE_BNDCSR_BIT 4
431 #define XSTATE_OPMASK_BIT 5
432 #define XSTATE_ZMM_Hi256_BIT 6
433 #define XSTATE_Hi16_ZMM_BIT 7
434 #define XSTATE_PKRU_BIT 9
436 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
437 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
438 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
439 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
440 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
441 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
442 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
443 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
444 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
446 /* CPUID feature words */
447 typedef enum FeatureWord
{
448 FEAT_1_EDX
, /* CPUID[1].EDX */
449 FEAT_1_ECX
, /* CPUID[1].ECX */
450 FEAT_7_0_EBX
, /* CPUID[EAX=7,ECX=0].EBX */
451 FEAT_7_0_ECX
, /* CPUID[EAX=7,ECX=0].ECX */
452 FEAT_7_0_EDX
, /* CPUID[EAX=7,ECX=0].EDX */
453 FEAT_8000_0001_EDX
, /* CPUID[8000_0001].EDX */
454 FEAT_8000_0001_ECX
, /* CPUID[8000_0001].ECX */
455 FEAT_8000_0007_EDX
, /* CPUID[8000_0007].EDX */
456 FEAT_C000_0001_EDX
, /* CPUID[C000_0001].EDX */
457 FEAT_KVM
, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
458 FEAT_HYPERV_EAX
, /* CPUID[4000_0003].EAX */
459 FEAT_HYPERV_EBX
, /* CPUID[4000_0003].EBX */
460 FEAT_HYPERV_EDX
, /* CPUID[4000_0003].EDX */
461 FEAT_SVM
, /* CPUID[8000_000A].EDX */
462 FEAT_XSAVE
, /* CPUID[EAX=0xd,ECX=1].EAX */
463 FEAT_6_EAX
, /* CPUID[6].EAX */
464 FEAT_XSAVE_COMP_LO
, /* CPUID[EAX=0xd,ECX=0].EAX */
465 FEAT_XSAVE_COMP_HI
, /* CPUID[EAX=0xd,ECX=0].EDX */
469 typedef uint32_t FeatureWordArray
[FEATURE_WORDS
];
471 /* cpuid_features bits */
472 #define CPUID_FP87 (1U << 0)
473 #define CPUID_VME (1U << 1)
474 #define CPUID_DE (1U << 2)
475 #define CPUID_PSE (1U << 3)
476 #define CPUID_TSC (1U << 4)
477 #define CPUID_MSR (1U << 5)
478 #define CPUID_PAE (1U << 6)
479 #define CPUID_MCE (1U << 7)
480 #define CPUID_CX8 (1U << 8)
481 #define CPUID_APIC (1U << 9)
482 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
483 #define CPUID_MTRR (1U << 12)
484 #define CPUID_PGE (1U << 13)
485 #define CPUID_MCA (1U << 14)
486 #define CPUID_CMOV (1U << 15)
487 #define CPUID_PAT (1U << 16)
488 #define CPUID_PSE36 (1U << 17)
489 #define CPUID_PN (1U << 18)
490 #define CPUID_CLFLUSH (1U << 19)
491 #define CPUID_DTS (1U << 21)
492 #define CPUID_ACPI (1U << 22)
493 #define CPUID_MMX (1U << 23)
494 #define CPUID_FXSR (1U << 24)
495 #define CPUID_SSE (1U << 25)
496 #define CPUID_SSE2 (1U << 26)
497 #define CPUID_SS (1U << 27)
498 #define CPUID_HT (1U << 28)
499 #define CPUID_TM (1U << 29)
500 #define CPUID_IA64 (1U << 30)
501 #define CPUID_PBE (1U << 31)
503 #define CPUID_EXT_SSE3 (1U << 0)
504 #define CPUID_EXT_PCLMULQDQ (1U << 1)
505 #define CPUID_EXT_DTES64 (1U << 2)
506 #define CPUID_EXT_MONITOR (1U << 3)
507 #define CPUID_EXT_DSCPL (1U << 4)
508 #define CPUID_EXT_VMX (1U << 5)
509 #define CPUID_EXT_SMX (1U << 6)
510 #define CPUID_EXT_EST (1U << 7)
511 #define CPUID_EXT_TM2 (1U << 8)
512 #define CPUID_EXT_SSSE3 (1U << 9)
513 #define CPUID_EXT_CID (1U << 10)
514 #define CPUID_EXT_FMA (1U << 12)
515 #define CPUID_EXT_CX16 (1U << 13)
516 #define CPUID_EXT_XTPR (1U << 14)
517 #define CPUID_EXT_PDCM (1U << 15)
518 #define CPUID_EXT_PCID (1U << 17)
519 #define CPUID_EXT_DCA (1U << 18)
520 #define CPUID_EXT_SSE41 (1U << 19)
521 #define CPUID_EXT_SSE42 (1U << 20)
522 #define CPUID_EXT_X2APIC (1U << 21)
523 #define CPUID_EXT_MOVBE (1U << 22)
524 #define CPUID_EXT_POPCNT (1U << 23)
525 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
526 #define CPUID_EXT_AES (1U << 25)
527 #define CPUID_EXT_XSAVE (1U << 26)
528 #define CPUID_EXT_OSXSAVE (1U << 27)
529 #define CPUID_EXT_AVX (1U << 28)
530 #define CPUID_EXT_F16C (1U << 29)
531 #define CPUID_EXT_RDRAND (1U << 30)
532 #define CPUID_EXT_HYPERVISOR (1U << 31)
534 #define CPUID_EXT2_FPU (1U << 0)
535 #define CPUID_EXT2_VME (1U << 1)
536 #define CPUID_EXT2_DE (1U << 2)
537 #define CPUID_EXT2_PSE (1U << 3)
538 #define CPUID_EXT2_TSC (1U << 4)
539 #define CPUID_EXT2_MSR (1U << 5)
540 #define CPUID_EXT2_PAE (1U << 6)
541 #define CPUID_EXT2_MCE (1U << 7)
542 #define CPUID_EXT2_CX8 (1U << 8)
543 #define CPUID_EXT2_APIC (1U << 9)
544 #define CPUID_EXT2_SYSCALL (1U << 11)
545 #define CPUID_EXT2_MTRR (1U << 12)
546 #define CPUID_EXT2_PGE (1U << 13)
547 #define CPUID_EXT2_MCA (1U << 14)
548 #define CPUID_EXT2_CMOV (1U << 15)
549 #define CPUID_EXT2_PAT (1U << 16)
550 #define CPUID_EXT2_PSE36 (1U << 17)
551 #define CPUID_EXT2_MP (1U << 19)
552 #define CPUID_EXT2_NX (1U << 20)
553 #define CPUID_EXT2_MMXEXT (1U << 22)
554 #define CPUID_EXT2_MMX (1U << 23)
555 #define CPUID_EXT2_FXSR (1U << 24)
556 #define CPUID_EXT2_FFXSR (1U << 25)
557 #define CPUID_EXT2_PDPE1GB (1U << 26)
558 #define CPUID_EXT2_RDTSCP (1U << 27)
559 #define CPUID_EXT2_LM (1U << 29)
560 #define CPUID_EXT2_3DNOWEXT (1U << 30)
561 #define CPUID_EXT2_3DNOW (1U << 31)
563 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
564 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
565 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
566 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
567 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
568 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
569 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
570 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
571 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
572 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
574 #define CPUID_EXT3_LAHF_LM (1U << 0)
575 #define CPUID_EXT3_CMP_LEG (1U << 1)
576 #define CPUID_EXT3_SVM (1U << 2)
577 #define CPUID_EXT3_EXTAPIC (1U << 3)
578 #define CPUID_EXT3_CR8LEG (1U << 4)
579 #define CPUID_EXT3_ABM (1U << 5)
580 #define CPUID_EXT3_SSE4A (1U << 6)
581 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
582 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
583 #define CPUID_EXT3_OSVW (1U << 9)
584 #define CPUID_EXT3_IBS (1U << 10)
585 #define CPUID_EXT3_XOP (1U << 11)
586 #define CPUID_EXT3_SKINIT (1U << 12)
587 #define CPUID_EXT3_WDT (1U << 13)
588 #define CPUID_EXT3_LWP (1U << 15)
589 #define CPUID_EXT3_FMA4 (1U << 16)
590 #define CPUID_EXT3_TCE (1U << 17)
591 #define CPUID_EXT3_NODEID (1U << 19)
592 #define CPUID_EXT3_TBM (1U << 21)
593 #define CPUID_EXT3_TOPOEXT (1U << 22)
594 #define CPUID_EXT3_PERFCORE (1U << 23)
595 #define CPUID_EXT3_PERFNB (1U << 24)
597 #define CPUID_SVM_NPT (1U << 0)
598 #define CPUID_SVM_LBRV (1U << 1)
599 #define CPUID_SVM_SVMLOCK (1U << 2)
600 #define CPUID_SVM_NRIPSAVE (1U << 3)
601 #define CPUID_SVM_TSCSCALE (1U << 4)
602 #define CPUID_SVM_VMCBCLEAN (1U << 5)
603 #define CPUID_SVM_FLUSHASID (1U << 6)
604 #define CPUID_SVM_DECODEASSIST (1U << 7)
605 #define CPUID_SVM_PAUSEFILTER (1U << 10)
606 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
608 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
609 #define CPUID_7_0_EBX_BMI1 (1U << 3)
610 #define CPUID_7_0_EBX_HLE (1U << 4)
611 #define CPUID_7_0_EBX_AVX2 (1U << 5)
612 #define CPUID_7_0_EBX_SMEP (1U << 7)
613 #define CPUID_7_0_EBX_BMI2 (1U << 8)
614 #define CPUID_7_0_EBX_ERMS (1U << 9)
615 #define CPUID_7_0_EBX_INVPCID (1U << 10)
616 #define CPUID_7_0_EBX_RTM (1U << 11)
617 #define CPUID_7_0_EBX_MPX (1U << 14)
618 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */
619 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */
620 #define CPUID_7_0_EBX_RDSEED (1U << 18)
621 #define CPUID_7_0_EBX_ADX (1U << 19)
622 #define CPUID_7_0_EBX_SMAP (1U << 20)
623 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */
624 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
625 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
626 #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
627 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
628 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
629 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
630 #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */
631 #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */
632 #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */
634 #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */
635 #define CPUID_7_0_ECX_UMIP (1U << 2)
636 #define CPUID_7_0_ECX_PKU (1U << 3)
637 #define CPUID_7_0_ECX_OSPKE (1U << 4)
638 #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */
639 #define CPUID_7_0_ECX_GFNI (1U << 8)
640 #define CPUID_7_0_ECX_VAES (1U << 9)
641 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
642 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
643 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
644 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
645 #define CPUID_7_0_ECX_LA57 (1U << 16)
646 #define CPUID_7_0_ECX_RDPID (1U << 22)
648 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
649 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
651 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
652 #define CPUID_XSAVE_XSAVEC (1U << 1)
653 #define CPUID_XSAVE_XGETBV1 (1U << 2)
654 #define CPUID_XSAVE_XSAVES (1U << 3)
656 #define CPUID_6_EAX_ARAT (1U << 2)
658 /* CPUID[0x80000007].EDX flags: */
659 #define CPUID_APM_INVTSC (1U << 8)
661 #define CPUID_VENDOR_SZ 12
663 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
664 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
665 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
666 #define CPUID_VENDOR_INTEL "GenuineIntel"
668 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
669 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
670 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
671 #define CPUID_VENDOR_AMD "AuthenticAMD"
673 #define CPUID_VENDOR_VIA "CentaurHauls"
675 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
676 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
678 /* CPUID[0xB].ECX level types */
679 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
680 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
681 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
683 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
684 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
687 #define EXCP00_DIVZ 0
690 #define EXCP03_INT3 3
691 #define EXCP04_INTO 4
692 #define EXCP05_BOUND 5
693 #define EXCP06_ILLOP 6
694 #define EXCP07_PREX 7
695 #define EXCP08_DBLE 8
696 #define EXCP09_XERR 9
697 #define EXCP0A_TSS 10
698 #define EXCP0B_NOSEG 11
699 #define EXCP0C_STACK 12
700 #define EXCP0D_GPF 13
701 #define EXCP0E_PAGE 14
702 #define EXCP10_COPR 16
703 #define EXCP11_ALGN 17
704 #define EXCP12_MCHK 18
706 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation
707 for syscall instruction */
708 #define EXCP_VMEXIT 0x100
710 /* i386-specific interrupt pending bits. */
711 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
712 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
713 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
714 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
715 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
716 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
717 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
719 /* Use a clearer name for this. */
720 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
722 /* Instead of computing the condition codes after each x86 instruction,
723 * QEMU just stores one operand (called CC_SRC), the result
724 * (called CC_DST) and the type of operation (called CC_OP). When the
725 * condition codes are needed, the condition codes can be calculated
726 * using this information. Condition codes are not generated if they
727 * are only needed for conditional branches.
730 CC_OP_DYNAMIC
, /* must use dynamic code to get cc_op */
731 CC_OP_EFLAGS
, /* all cc are explicitly computed, CC_SRC = flags */
733 CC_OP_MULB
, /* modify all flags, C, O = (CC_SRC != 0) */
738 CC_OP_ADDB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
743 CC_OP_ADCB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
748 CC_OP_SUBB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
753 CC_OP_SBBB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
758 CC_OP_LOGICB
, /* modify all flags, CC_DST = res */
763 CC_OP_INCB
, /* modify all flags except, CC_DST = res, CC_SRC = C */
768 CC_OP_DECB
, /* modify all flags except, CC_DST = res, CC_SRC = C */
773 CC_OP_SHLB
, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
778 CC_OP_SARB
, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
783 CC_OP_BMILGB
, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
788 CC_OP_ADCX
, /* CC_DST = C, CC_SRC = rest. */
789 CC_OP_ADOX
, /* CC_DST = O, CC_SRC = rest. */
790 CC_OP_ADCOX
, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
792 CC_OP_CLR
, /* Z set, all other flags clear. */
793 CC_OP_POPCNT
, /* Z via CC_SRC, all other flags clear. */
798 typedef struct SegmentCache
{
805 #define MMREG_UNION(n, bits) \
807 uint8_t _b_##n[(bits)/8]; \
808 uint16_t _w_##n[(bits)/16]; \
809 uint32_t _l_##n[(bits)/32]; \
810 uint64_t _q_##n[(bits)/64]; \
811 float32 _s_##n[(bits)/32]; \
812 float64 _d_##n[(bits)/64]; \
815 typedef MMREG_UNION(ZMMReg
, 512) ZMMReg
;
816 typedef MMREG_UNION(MMXReg
, 64) MMXReg
;
818 typedef struct BNDReg
{
823 typedef struct BNDCSReg
{
828 #define BNDCFG_ENABLE 1ULL
829 #define BNDCFG_BNDPRESERVE 2ULL
830 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
832 #ifdef HOST_WORDS_BIGENDIAN
833 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
834 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
835 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
836 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
837 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
838 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
840 #define MMX_B(n) _b_MMXReg[7 - (n)]
841 #define MMX_W(n) _w_MMXReg[3 - (n)]
842 #define MMX_L(n) _l_MMXReg[1 - (n)]
843 #define MMX_S(n) _s_MMXReg[1 - (n)]
845 #define ZMM_B(n) _b_ZMMReg[n]
846 #define ZMM_W(n) _w_ZMMReg[n]
847 #define ZMM_L(n) _l_ZMMReg[n]
848 #define ZMM_S(n) _s_ZMMReg[n]
849 #define ZMM_Q(n) _q_ZMMReg[n]
850 #define ZMM_D(n) _d_ZMMReg[n]
852 #define MMX_B(n) _b_MMXReg[n]
853 #define MMX_W(n) _w_MMXReg[n]
854 #define MMX_L(n) _l_MMXReg[n]
855 #define MMX_S(n) _s_MMXReg[n]
857 #define MMX_Q(n) _q_MMXReg[n]
860 floatx80 d
__attribute__((aligned(16)));
869 #define CPU_NB_REGS64 16
870 #define CPU_NB_REGS32 8
873 #define CPU_NB_REGS CPU_NB_REGS64
875 #define CPU_NB_REGS CPU_NB_REGS32
878 #define MAX_FIXED_COUNTERS 3
879 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
881 #define NB_MMU_MODES 3
882 #define TARGET_INSN_START_EXTRA_WORDS 1
884 #define NB_OPMASK_REGS 8
886 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
887 * that APIC ID hasn't been set yet
889 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
891 typedef union X86LegacyXSaveArea
{
903 uint8_t xmm_regs
[16][16];
906 } X86LegacyXSaveArea
;
908 typedef struct X86XSaveHeader
{
912 uint8_t reserved
[40];
915 /* Ext. save area 2: AVX State */
916 typedef struct XSaveAVX
{
917 uint8_t ymmh
[16][16];
920 /* Ext. save area 3: BNDREG */
921 typedef struct XSaveBNDREG
{
925 /* Ext. save area 4: BNDCSR */
926 typedef union XSaveBNDCSR
{
931 /* Ext. save area 5: Opmask */
932 typedef struct XSaveOpmask
{
933 uint64_t opmask_regs
[NB_OPMASK_REGS
];
936 /* Ext. save area 6: ZMM_Hi256 */
937 typedef struct XSaveZMM_Hi256
{
938 uint8_t zmm_hi256
[16][32];
941 /* Ext. save area 7: Hi16_ZMM */
942 typedef struct XSaveHi16_ZMM
{
943 uint8_t hi16_zmm
[16][64];
946 /* Ext. save area 9: PKRU state */
947 typedef struct XSavePKRU
{
952 typedef struct X86XSaveArea
{
953 X86LegacyXSaveArea legacy
;
954 X86XSaveHeader header
;
956 /* Extended save areas: */
960 uint8_t padding
[960 - 576 - sizeof(XSaveAVX
)];
962 XSaveBNDREG bndreg_state
;
963 XSaveBNDCSR bndcsr_state
;
965 XSaveOpmask opmask_state
;
966 XSaveZMM_Hi256 zmm_hi256_state
;
967 XSaveHi16_ZMM hi16_zmm_state
;
969 XSavePKRU pkru_state
;
972 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea
, avx_state
) != 0x240);
973 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX
) != 0x100);
974 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea
, bndreg_state
) != 0x3c0);
975 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG
) != 0x40);
976 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea
, bndcsr_state
) != 0x400);
977 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR
) != 0x40);
978 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea
, opmask_state
) != 0x440);
979 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask
) != 0x40);
980 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea
, zmm_hi256_state
) != 0x480);
981 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256
) != 0x200);
982 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea
, hi16_zmm_state
) != 0x680);
983 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM
) != 0x400);
984 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea
, pkru_state
) != 0xA80);
985 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU
) != 0x8);
987 typedef enum TPRAccess
{
992 typedef struct CPUX86State
{
993 /* standard registers */
994 target_ulong regs
[CPU_NB_REGS
];
996 target_ulong eflags
; /* eflags register. During CPU emulation, CC
997 flags and DF are set to zero because they are
1000 /* emulator internal eflags handling */
1001 target_ulong cc_dst
;
1002 target_ulong cc_src
;
1003 target_ulong cc_src2
;
1005 int32_t df
; /* D flag : 1 if D = 0, -1 if D = 1 */
1006 uint32_t hflags
; /* TB flags, see HF_xxx constants. These flags
1007 are known at translation time. */
1008 uint32_t hflags2
; /* various other flags, see HF2_xxx constants. */
1011 SegmentCache segs
[6]; /* selector values */
1014 SegmentCache gdt
; /* only base and limit are used */
1015 SegmentCache idt
; /* only base and limit are used */
1017 target_ulong cr
[5]; /* NOTE: cr1 is unused */
1021 BNDCSReg bndcs_regs
;
1022 uint64_t msr_bndcfgs
;
1025 /* Beginning of state preserved by INIT (dummy marker). */
1026 struct {} start_init_save
;
1029 unsigned int fpstt
; /* top of stack index */
1032 uint8_t fptags
[8]; /* 0 = valid, 1 = empty */
1034 /* KVM-only so far */
1039 /* emulator internal variables */
1040 float_status fp_status
;
1043 float_status mmx_status
; /* for 3DNow! float ops */
1044 float_status sse_status
;
1046 ZMMReg xmm_regs
[CPU_NB_REGS
== 8 ? 8 : 32];
1050 uint64_t opmask_regs
[NB_OPMASK_REGS
];
1052 /* sysenter registers */
1053 uint32_t sysenter_cs
;
1054 target_ulong sysenter_esp
;
1055 target_ulong sysenter_eip
;
1060 #ifdef TARGET_X86_64
1064 target_ulong kernelgsbase
;
1068 uint64_t tsc_adjust
;
1069 uint64_t tsc_deadline
;
1074 uint64_t mcg_status
;
1075 uint64_t msr_ia32_misc_enable
;
1076 uint64_t msr_ia32_feature_control
;
1078 uint64_t msr_fixed_ctr_ctrl
;
1079 uint64_t msr_global_ctrl
;
1080 uint64_t msr_global_status
;
1081 uint64_t msr_global_ovf_ctrl
;
1082 uint64_t msr_fixed_counters
[MAX_FIXED_COUNTERS
];
1083 uint64_t msr_gp_counters
[MAX_GP_COUNTERS
];
1084 uint64_t msr_gp_evtsel
[MAX_GP_COUNTERS
];
1091 /* End of state preserved by INIT (dummy marker). */
1092 struct {} end_init_save
;
1094 uint64_t system_time_msr
;
1095 uint64_t wall_clock_msr
;
1096 uint64_t steal_time_msr
;
1097 uint64_t async_pf_en_msr
;
1098 uint64_t pv_eoi_en_msr
;
1100 /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1101 uint64_t msr_hv_hypercall
;
1102 uint64_t msr_hv_guest_os_id
;
1103 uint64_t msr_hv_tsc
;
1105 /* Per-VCPU HV MSRs */
1106 uint64_t msr_hv_vapic
;
1107 uint64_t msr_hv_crash_params
[HV_CRASH_PARAMS
];
1108 uint64_t msr_hv_runtime
;
1109 uint64_t msr_hv_synic_control
;
1110 uint64_t msr_hv_synic_version
;
1111 uint64_t msr_hv_synic_evt_page
;
1112 uint64_t msr_hv_synic_msg_page
;
1113 uint64_t msr_hv_synic_sint
[HV_SINT_COUNT
];
1114 uint64_t msr_hv_stimer_config
[HV_STIMER_COUNT
];
1115 uint64_t msr_hv_stimer_count
[HV_STIMER_COUNT
];
1117 /* exception/interrupt handling */
1119 int exception_is_int
;
1120 target_ulong exception_next_eip
;
1121 target_ulong dr
[8]; /* debug registers; note dr4 and dr5 are unused */
1123 struct CPUBreakpoint
*cpu_breakpoint
[4];
1124 struct CPUWatchpoint
*cpu_watchpoint
[4];
1125 }; /* break/watchpoints for dr[0..3] */
1126 int old_exception
; /* exception in flight */
1129 uint64_t tsc_offset
;
1131 uint16_t intercept_cr_read
;
1132 uint16_t intercept_cr_write
;
1133 uint16_t intercept_dr_read
;
1134 uint16_t intercept_dr_write
;
1135 uint32_t intercept_exceptions
;
1138 /* KVM states, automatically cleared on reset */
1139 uint8_t nmi_injected
;
1140 uint8_t nmi_pending
;
1142 /* Fields up to this point are cleared by a CPU reset */
1143 struct {} end_reset_fields
;
1147 /* Fields after CPU_COMMON are preserved across CPU reset. */
1149 /* processor features (e.g. for CPUID insn) */
1150 /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1151 uint32_t cpuid_min_level
, cpuid_min_xlevel
, cpuid_min_xlevel2
;
1152 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1153 uint32_t cpuid_max_level
, cpuid_max_xlevel
, cpuid_max_xlevel2
;
1154 /* Actual level/xlevel/xlevel2 value: */
1155 uint32_t cpuid_level
, cpuid_xlevel
, cpuid_xlevel2
;
1156 uint32_t cpuid_vendor1
;
1157 uint32_t cpuid_vendor2
;
1158 uint32_t cpuid_vendor3
;
1159 uint32_t cpuid_version
;
1160 FeatureWordArray features
;
1161 /* Features that were explicitly enabled/disabled */
1162 FeatureWordArray user_features
;
1163 uint32_t cpuid_model
[12];
1166 uint64_t mtrr_fixed
[11];
1167 uint64_t mtrr_deftype
;
1168 MTRRVar mtrr_var
[MSR_MTRRcap_VCNT
];
1172 int32_t exception_injected
;
1173 int32_t interrupt_injected
;
1174 uint8_t soft_interrupt
;
1175 uint8_t has_error_code
;
1176 uint32_t sipi_vector
;
1179 int64_t user_tsc_khz
; /* for sanity check only */
1180 void *kvm_xsave_buf
;
1184 uint64_t mcg_ext_ctl
;
1185 uint64_t mce_banks
[MCE_BANKS_DEF
*4];
1189 uint16_t fpus_vmstate
;
1190 uint16_t fptag_vmstate
;
1191 uint16_t fpregs_format_vmstate
;
1195 TPRAccess tpr_access_type
;
1202 * @env: #CPUX86State
1203 * @migratable: If set, only migratable flags will be accepted when "enforce"
1204 * mode is used, and only migratable flags will be included in the "host"
1211 CPUState parent_obj
;
1217 bool hyperv_relaxed_timing
;
1218 int hyperv_spinlock_attempts
;
1219 char *hyperv_vendor_id
;
1223 bool hyperv_vpindex
;
1224 bool hyperv_runtime
;
1232 bool max_features
; /* Enable all supported features automatically */
1235 /* Enables publishing of TSC increment and Local APIC bus frequencies to
1236 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
1237 bool vmware_cpuid_freq
;
1239 /* if true the CPUID code directly forward host cache leaves to the guest */
1240 bool cache_info_passthrough
;
1242 /* Features that were filtered out because of missing host capabilities */
1243 uint32_t filtered_features
[FEATURE_WORDS
];
1245 /* Enable PMU CPUID bits. This can't be enabled by default yet because
1246 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
1247 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
1248 * capabilities) directly to the guest.
1252 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
1253 * disabled by default to avoid breaking migration between QEMU with
1254 * different LMCE configurations.
1258 /* Compatibility bits for old machine types.
1259 * If true present virtual l3 cache for VM, the vcpus in the same virtual
1260 * socket share an virtual l3 cache.
1262 bool enable_l3_cache
;
1264 /* Compatibility bits for old machine types: */
1265 bool enable_cpuid_0xb
;
1267 /* Enable auto level-increase for all CPUID leaves */
1268 bool full_cpuid_auto_level
;
1270 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
1271 bool fill_mtrr_mask
;
1273 /* if true override the phys_bits value with a value read from the host */
1274 bool host_phys_bits
;
1276 /* Stop SMI delivery for migration compatibility with old machines */
1277 bool kvm_no_smi_migration
;
1279 /* Number of physical address bits supported */
1282 /* in order to simplify APIC support, we leave this pointer to the
1284 struct DeviceState
*apic_state
;
1285 struct MemoryRegion
*cpu_as_root
, *cpu_as_mem
, *smram
;
1286 Notifier machine_done
;
1288 struct kvm_msrs
*kvm_msr_buf
;
1290 int32_t node_id
; /* NUMA node this CPU belongs to */
1298 static inline X86CPU
*x86_env_get_cpu(CPUX86State
*env
)
1300 return container_of(env
, X86CPU
, env
);
1303 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
1305 #define ENV_OFFSET offsetof(X86CPU, env)
1307 #ifndef CONFIG_USER_ONLY
1308 extern struct VMStateDescription vmstate_x86_cpu
;
1312 * x86_cpu_do_interrupt:
1313 * @cpu: vCPU the interrupt is to be handled by.
1315 void x86_cpu_do_interrupt(CPUState
*cpu
);
1316 bool x86_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
1318 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
1319 int cpuid
, void *opaque
);
1320 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
1321 int cpuid
, void *opaque
);
1322 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
1324 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
1327 void x86_cpu_get_memory_mapping(CPUState
*cpu
, MemoryMappingList
*list
,
1330 void x86_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
1333 hwaddr
x86_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
1335 int x86_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
1336 int x86_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
1338 void x86_cpu_exec_enter(CPUState
*cpu
);
1339 void x86_cpu_exec_exit(CPUState
*cpu
);
1341 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
1342 int cpu_x86_support_mca_broadcast(CPUX86State
*env
);
1344 int cpu_get_pic_interrupt(CPUX86State
*s
);
1345 /* MSDOS compatibility mode FPU exception support */
1346 void cpu_set_ferr(CPUX86State
*s
);
1348 /* this function must always be used to load data in the segment
1349 cache: it synchronizes the hflags with the segment cache values */
1350 static inline void cpu_x86_load_seg_cache(CPUX86State
*env
,
1351 int seg_reg
, unsigned int selector
,
1357 unsigned int new_hflags
;
1359 sc
= &env
->segs
[seg_reg
];
1360 sc
->selector
= selector
;
1365 /* update the hidden flags */
1367 if (seg_reg
== R_CS
) {
1368 #ifdef TARGET_X86_64
1369 if ((env
->hflags
& HF_LMA_MASK
) && (flags
& DESC_L_MASK
)) {
1371 env
->hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1372 env
->hflags
&= ~(HF_ADDSEG_MASK
);
1376 /* legacy / compatibility case */
1377 new_hflags
= (env
->segs
[R_CS
].flags
& DESC_B_MASK
)
1378 >> (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1379 env
->hflags
= (env
->hflags
& ~(HF_CS32_MASK
| HF_CS64_MASK
)) |
1383 if (seg_reg
== R_SS
) {
1384 int cpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
1385 #if HF_CPL_MASK != 3
1386 #error HF_CPL_MASK is hardcoded
1388 env
->hflags
= (env
->hflags
& ~HF_CPL_MASK
) | cpl
;
1390 new_hflags
= (env
->segs
[R_SS
].flags
& DESC_B_MASK
)
1391 >> (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1392 if (env
->hflags
& HF_CS64_MASK
) {
1393 /* zero base assumed for DS, ES and SS in long mode */
1394 } else if (!(env
->cr
[0] & CR0_PE_MASK
) ||
1395 (env
->eflags
& VM_MASK
) ||
1396 !(env
->hflags
& HF_CS32_MASK
)) {
1397 /* XXX: try to avoid this test. The problem comes from the
1398 fact that is real mode or vm86 mode we only modify the
1399 'base' and 'selector' fields of the segment cache to go
1400 faster. A solution may be to force addseg to one in
1401 translate-i386.c. */
1402 new_hflags
|= HF_ADDSEG_MASK
;
1404 new_hflags
|= ((env
->segs
[R_DS
].base
|
1405 env
->segs
[R_ES
].base
|
1406 env
->segs
[R_SS
].base
) != 0) <<
1409 env
->hflags
= (env
->hflags
&
1410 ~(HF_SS32_MASK
| HF_ADDSEG_MASK
)) | new_hflags
;
1414 static inline void cpu_x86_load_seg_cache_sipi(X86CPU
*cpu
,
1415 uint8_t sipi_vector
)
1417 CPUState
*cs
= CPU(cpu
);
1418 CPUX86State
*env
= &cpu
->env
;
1421 cpu_x86_load_seg_cache(env
, R_CS
, sipi_vector
<< 8,
1423 env
->segs
[R_CS
].limit
,
1424 env
->segs
[R_CS
].flags
);
1428 int cpu_x86_get_descr_debug(CPUX86State
*env
, unsigned int selector
,
1429 target_ulong
*base
, unsigned int *limit
,
1430 unsigned int *flags
);
1433 /* used for debug or cpu save/restore */
1436 /* the following helpers are only usable in user mode simulation as
1437 they can trigger unexpected exceptions */
1438 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
);
1439 void cpu_x86_fsave(CPUX86State
*s
, target_ulong ptr
, int data32
);
1440 void cpu_x86_frstor(CPUX86State
*s
, target_ulong ptr
, int data32
);
1441 void cpu_x86_fxsave(CPUX86State
*s
, target_ulong ptr
);
1442 void cpu_x86_fxrstor(CPUX86State
*s
, target_ulong ptr
);
1444 /* you can call this signal handler from your SIGBUS and SIGSEGV
1445 signal handlers to inform the virtual CPU of exceptions. non zero
1446 is returned if the signal was handled by the virtual CPU. */
1447 int cpu_x86_signal_handler(int host_signum
, void *pinfo
,
1451 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
1452 uint32_t *eax
, uint32_t *ebx
,
1453 uint32_t *ecx
, uint32_t *edx
);
1454 void cpu_clear_apic_feature(CPUX86State
*env
);
1455 void host_cpuid(uint32_t function
, uint32_t count
,
1456 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
);
1457 void host_vendor_fms(char *vendor
, int *family
, int *model
, int *stepping
);
1460 int x86_cpu_handle_mmu_fault(CPUState
*cpu
, vaddr addr
,
1461 int is_write
, int mmu_idx
);
1462 void x86_cpu_set_a20(X86CPU
*cpu
, int a20_state
);
1464 #ifndef CONFIG_USER_ONLY
1465 static inline int x86_asidx_from_attrs(CPUState
*cs
, MemTxAttrs attrs
)
1467 return !!attrs
.secure
;
1470 static inline AddressSpace
*cpu_addressspace(CPUState
*cs
, MemTxAttrs attrs
)
1472 return cpu_get_address_space(cs
, cpu_asidx_from_attrs(cs
, attrs
));
1475 uint8_t x86_ldub_phys(CPUState
*cs
, hwaddr addr
);
1476 uint32_t x86_lduw_phys(CPUState
*cs
, hwaddr addr
);
1477 uint32_t x86_ldl_phys(CPUState
*cs
, hwaddr addr
);
1478 uint64_t x86_ldq_phys(CPUState
*cs
, hwaddr addr
);
1479 void x86_stb_phys(CPUState
*cs
, hwaddr addr
, uint8_t val
);
1480 void x86_stl_phys_notdirty(CPUState
*cs
, hwaddr addr
, uint32_t val
);
1481 void x86_stw_phys(CPUState
*cs
, hwaddr addr
, uint32_t val
);
1482 void x86_stl_phys(CPUState
*cs
, hwaddr addr
, uint32_t val
);
1483 void x86_stq_phys(CPUState
*cs
, hwaddr addr
, uint64_t val
);
1486 void breakpoint_handler(CPUState
*cs
);
1488 /* will be suppressed */
1489 void cpu_x86_update_cr0(CPUX86State
*env
, uint32_t new_cr0
);
1490 void cpu_x86_update_cr3(CPUX86State
*env
, target_ulong new_cr3
);
1491 void cpu_x86_update_cr4(CPUX86State
*env
, uint32_t new_cr4
);
1492 void cpu_x86_update_dr7(CPUX86State
*env
, uint32_t new_dr7
);
1495 uint64_t cpu_get_tsc(CPUX86State
*env
);
1497 #define TARGET_PAGE_BITS 12
1499 #ifdef TARGET_X86_64
1500 #define TARGET_PHYS_ADDR_SPACE_BITS 52
1501 /* ??? This is really 48 bits, sign-extended, but the only thing
1502 accessible to userland with bit 48 set is the VSYSCALL, and that
1503 is handled via other mechanisms. */
1504 #define TARGET_VIRT_ADDR_SPACE_BITS 47
1506 #define TARGET_PHYS_ADDR_SPACE_BITS 36
1507 #define TARGET_VIRT_ADDR_SPACE_BITS 32
1510 /* XXX: This value should match the one returned by CPUID
1512 # if defined(TARGET_X86_64)
1513 # define TCG_PHYS_ADDR_BITS 40
1515 # define TCG_PHYS_ADDR_BITS 36
1518 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
1520 #define cpu_init(cpu_model) cpu_generic_init(TYPE_X86_CPU, cpu_model)
1522 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
1523 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
1525 #ifdef TARGET_X86_64
1526 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
1528 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
1531 #define cpu_signal_handler cpu_x86_signal_handler
1532 #define cpu_list x86_cpu_list
1534 /* MMU modes definitions */
1535 #define MMU_MODE0_SUFFIX _ksmap
1536 #define MMU_MODE1_SUFFIX _user
1537 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */
1538 #define MMU_KSMAP_IDX 0
1539 #define MMU_USER_IDX 1
1540 #define MMU_KNOSMAP_IDX 2
1541 static inline int cpu_mmu_index(CPUX86State
*env
, bool ifetch
)
1543 return (env
->hflags
& HF_CPL_MASK
) == 3 ? MMU_USER_IDX
:
1544 (!(env
->hflags
& HF_SMAP_MASK
) || (env
->eflags
& AC_MASK
))
1545 ? MMU_KNOSMAP_IDX
: MMU_KSMAP_IDX
;
1548 static inline int cpu_mmu_index_kernel(CPUX86State
*env
)
1550 return !(env
->hflags
& HF_SMAP_MASK
) ? MMU_KNOSMAP_IDX
:
1551 ((env
->hflags
& HF_CPL_MASK
) < 3 && (env
->eflags
& AC_MASK
))
1552 ? MMU_KNOSMAP_IDX
: MMU_KSMAP_IDX
;
1555 #define CC_DST (env->cc_dst)
1556 #define CC_SRC (env->cc_src)
1557 #define CC_SRC2 (env->cc_src2)
1558 #define CC_OP (env->cc_op)
1560 /* n must be a constant to be efficient */
1561 static inline target_long
lshift(target_long x
, int n
)
1571 #define FT0 (env->ft0)
1572 #define ST0 (env->fpregs[env->fpstt].d)
1573 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1577 void tcg_x86_init(void);
1579 #include "exec/cpu-all.h"
1582 #if !defined(CONFIG_USER_ONLY)
1583 #include "hw/i386/apic.h"
1586 static inline void cpu_get_tb_cpu_state(CPUX86State
*env
, target_ulong
*pc
,
1587 target_ulong
*cs_base
, uint32_t *flags
)
1589 *cs_base
= env
->segs
[R_CS
].base
;
1590 *pc
= *cs_base
+ env
->eip
;
1591 *flags
= env
->hflags
|
1592 (env
->eflags
& (IOPL_MASK
| TF_MASK
| RF_MASK
| VM_MASK
| AC_MASK
));
1595 void do_cpu_init(X86CPU
*cpu
);
1596 void do_cpu_sipi(X86CPU
*cpu
);
1598 #define MCE_INJECT_BROADCAST 1
1599 #define MCE_INJECT_UNCOND_AO 2
1601 void cpu_x86_inject_mce(Monitor
*mon
, X86CPU
*cpu
, int bank
,
1602 uint64_t status
, uint64_t mcg_status
, uint64_t addr
,
1603 uint64_t misc
, int flags
);
1606 void QEMU_NORETURN
raise_exception(CPUX86State
*env
, int exception_index
);
1607 void QEMU_NORETURN
raise_exception_ra(CPUX86State
*env
, int exception_index
,
1609 void QEMU_NORETURN
raise_exception_err(CPUX86State
*env
, int exception_index
,
1611 void QEMU_NORETURN
raise_exception_err_ra(CPUX86State
*env
, int exception_index
,
1612 int error_code
, uintptr_t retaddr
);
1613 void QEMU_NORETURN
raise_interrupt(CPUX86State
*nenv
, int intno
, int is_int
,
1614 int error_code
, int next_eip_addend
);
1617 extern const uint8_t parity_table
[256];
1618 uint32_t cpu_cc_compute_all(CPUX86State
*env1
, int op
);
1620 static inline uint32_t cpu_compute_eflags(CPUX86State
*env
)
1622 uint32_t eflags
= env
->eflags
;
1623 if (tcg_enabled()) {
1624 eflags
|= cpu_cc_compute_all(env
, CC_OP
) | (env
->df
& DF_MASK
);
1629 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
1630 * after generating a call to a helper that uses this.
1632 static inline void cpu_load_eflags(CPUX86State
*env
, int eflags
,
1635 CC_SRC
= eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
1636 CC_OP
= CC_OP_EFLAGS
;
1637 env
->df
= 1 - (2 * ((eflags
>> 10) & 1));
1638 env
->eflags
= (env
->eflags
& ~update_mask
) |
1639 (eflags
& update_mask
) | 0x2;
1642 /* load efer and update the corresponding hflags. XXX: do consistency
1643 checks with cpuid bits? */
1644 static inline void cpu_load_efer(CPUX86State
*env
, uint64_t val
)
1647 env
->hflags
&= ~(HF_LMA_MASK
| HF_SVME_MASK
);
1648 if (env
->efer
& MSR_EFER_LMA
) {
1649 env
->hflags
|= HF_LMA_MASK
;
1651 if (env
->efer
& MSR_EFER_SVME
) {
1652 env
->hflags
|= HF_SVME_MASK
;
1656 static inline MemTxAttrs
cpu_get_mem_attrs(CPUX86State
*env
)
1658 return ((MemTxAttrs
) { .secure
= (env
->hflags
& HF_SMM_MASK
) != 0 });
1661 static inline int32_t x86_get_a20_mask(CPUX86State
*env
)
1663 if (env
->hflags
& HF_SMM_MASK
) {
1666 return env
->a20_mask
;
1671 void update_fp_status(CPUX86State
*env
);
1672 void update_mxcsr_status(CPUX86State
*env
);
1674 static inline void cpu_set_mxcsr(CPUX86State
*env
, uint32_t mxcsr
)
1677 if (tcg_enabled()) {
1678 update_mxcsr_status(env
);
1682 static inline void cpu_set_fpuc(CPUX86State
*env
, uint16_t fpuc
)
1685 if (tcg_enabled()) {
1686 update_fp_status(env
);
1691 void helper_lock_init(void);
1694 void cpu_svm_check_intercept_param(CPUX86State
*env1
, uint32_t type
,
1695 uint64_t param
, uintptr_t retaddr
);
1696 void cpu_vmexit(CPUX86State
*nenv
, uint32_t exit_code
, uint64_t exit_info_1
,
1698 void do_vmexit(CPUX86State
*env
, uint32_t exit_code
, uint64_t exit_info_1
);
1701 void do_interrupt_x86_hardirq(CPUX86State
*env
, int intno
, int is_hw
);
1704 void do_smm_enter(X86CPU
*cpu
);
1707 void cpu_report_tpr_access(CPUX86State
*env
, TPRAccess access
);
1708 void apic_handle_tpr_access_report(DeviceState
*d
, target_ulong ip
,
1712 /* Change the value of a KVM-specific default
1714 * If value is NULL, no default will be set and the original
1715 * value from the CPU model table will be kept.
1717 * It is valid to call this function only for properties that
1718 * are already present in the kvm_default_props table.
1720 void x86_cpu_change_kvm_default(const char *prop
, const char *value
);
1723 void cpu_sync_bndcs_hflags(CPUX86State
*env
);
1725 /* Return name of 32-bit register, from a R_* constant */
1726 const char *get_register_name_32(unsigned int reg
);
1728 void enable_compat_apic_id_mode(void);
1730 #define APIC_DEFAULT_ADDRESS 0xfee00000
1731 #define APIC_SPACE_SIZE 0x100000
1733 void x86_cpu_dump_local_apic_state(CPUState
*cs
, FILE *f
,
1734 fprintf_function cpu_fprintf
, int flags
);
1737 bool cpu_is_bsp(X86CPU
*cpu
);
1739 void x86_cpu_xrstor_all_areas(X86CPU
*cpu
, const X86XSaveArea
*buf
);
1740 void x86_cpu_xsave_all_areas(X86CPU
*cpu
, X86XSaveArea
*buf
);
1741 #endif /* I386_CPU_H */