1 /* Copyright 2008 IBM Corporation
3 * Copyright 2011 Intel Corporation
4 * Copyright 2016 Veertu, Inc.
5 * Copyright 2017 The Android Open Source Project
7 * QEMU Hypervisor.framework support
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of version 2 of the GNU General Public
11 * License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 * This file contain code under public domain from the hvdos project:
22 * https://github.com/mist64/hvdos
24 * Parts Copyright (c) 2011 NetApp, Inc.
25 * All rights reserved.
27 * Redistribution and use in source and binary forms, with or without
28 * modification, are permitted provided that the following conditions
30 * 1. Redistributions of source code must retain the above copyright
31 * notice, this list of conditions and the following disclaimer.
32 * 2. Redistributions in binary form must reproduce the above copyright
33 * notice, this list of conditions and the following disclaimer in the
34 * documentation and/or other materials provided with the distribution.
36 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
37 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
39 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
42 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
43 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
44 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
45 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
48 #include "qemu/osdep.h"
49 #include "qemu-common.h"
50 #include "qemu/error-report.h"
52 #include "sysemu/hvf.h"
57 #include "x86_descr.h"
59 #include "x86_decode.h"
64 #include <Hypervisor/hv.h>
65 #include <Hypervisor/hv_vmx.h>
67 #include "exec/address-spaces.h"
68 #include "hw/i386/apic_internal.h"
69 #include "hw/boards.h"
70 #include "qemu/main-loop.h"
71 #include "sysemu/accel.h"
72 #include "sysemu/sysemu.h"
73 #include "target/i386/cpu.h"
77 static void assert_hvf_ok(hv_return_t ret
)
79 if (ret
== HV_SUCCESS
) {
85 error_report("Error: HV_ERROR");
88 error_report("Error: HV_BUSY");
91 error_report("Error: HV_BAD_ARGUMENT");
94 error_report("Error: HV_NO_RESOURCES");
97 error_report("Error: HV_NO_DEVICE");
100 error_report("Error: HV_UNSUPPORTED");
103 error_report("Unknown Error");
110 hvf_slot
*hvf_find_overlap_slot(uint64_t start
, uint64_t end
)
114 for (x
= 0; x
< hvf_state
->num_slots
; ++x
) {
115 slot
= &hvf_state
->slots
[x
];
116 if (slot
->size
&& start
< (slot
->start
+ slot
->size
) &&
131 struct mac_slot mac_slots
[32];
132 #define ALIGN(x, y) (((x) + (y) - 1) & ~((y) - 1))
134 static int do_hvf_set_memory(hvf_slot
*slot
)
136 struct mac_slot
*macslot
;
137 hv_memory_flags_t flags
;
140 macslot
= &mac_slots
[slot
->slot_id
];
142 if (macslot
->present
) {
143 if (macslot
->size
!= slot
->size
) {
144 macslot
->present
= 0;
145 ret
= hv_vm_unmap(macslot
->gpa_start
, macslot
->size
);
154 flags
= HV_MEMORY_READ
| HV_MEMORY_WRITE
| HV_MEMORY_EXEC
;
156 macslot
->present
= 1;
157 macslot
->gpa_start
= slot
->start
;
158 macslot
->size
= slot
->size
;
159 ret
= hv_vm_map((hv_uvaddr_t
)slot
->mem
, slot
->start
, slot
->size
, flags
);
164 void hvf_set_phys_mem(MemoryRegionSection
*section
, bool add
)
167 MemoryRegion
*area
= section
->mr
;
169 if (!memory_region_is_ram(area
)) {
173 mem
= hvf_find_overlap_slot(
174 section
->offset_within_address_space
,
175 section
->offset_within_address_space
+ int128_get64(section
->size
));
178 if (mem
->size
== int128_get64(section
->size
) &&
179 mem
->start
== section
->offset_within_address_space
&&
180 mem
->mem
== (memory_region_get_ram_ptr(area
) +
181 section
->offset_within_region
)) {
182 return; /* Same region was attempted to register, go away. */
186 /* Region needs to be reset. set the size to 0 and remap it. */
189 if (do_hvf_set_memory(mem
)) {
190 error_report("Failed to reset overlapping slot");
199 /* Now make a new slot. */
202 for (x
= 0; x
< hvf_state
->num_slots
; ++x
) {
203 mem
= &hvf_state
->slots
[x
];
209 if (x
== hvf_state
->num_slots
) {
210 error_report("No free slots");
214 mem
->size
= int128_get64(section
->size
);
215 mem
->mem
= memory_region_get_ram_ptr(area
) + section
->offset_within_region
;
216 mem
->start
= section
->offset_within_address_space
;
219 if (do_hvf_set_memory(mem
)) {
220 error_report("Error registering new memory slot");
225 void vmx_update_tpr(CPUState
*cpu
)
227 /* TODO: need integrate APIC handling */
228 X86CPU
*x86_cpu
= X86_CPU(cpu
);
229 int tpr
= cpu_get_apic_tpr(x86_cpu
->apic_state
) << 4;
230 int irr
= apic_get_highest_priority_irr(x86_cpu
->apic_state
);
232 wreg(cpu
->hvf_fd
, HV_X86_TPR
, tpr
);
234 wvmcs(cpu
->hvf_fd
, VMCS_TPR_THRESHOLD
, 0);
236 wvmcs(cpu
->hvf_fd
, VMCS_TPR_THRESHOLD
, (irr
> tpr
) ? tpr
>> 4 :
241 void update_apic_tpr(CPUState
*cpu
)
243 X86CPU
*x86_cpu
= X86_CPU(cpu
);
244 int tpr
= rreg(cpu
->hvf_fd
, HV_X86_TPR
) >> 4;
245 cpu_set_apic_tpr(x86_cpu
->apic_state
, tpr
);
248 #define VECTORING_INFO_VECTOR_MASK 0xff
250 static void hvf_handle_interrupt(CPUState
* cpu
, int mask
)
252 cpu
->interrupt_request
|= mask
;
253 if (!qemu_cpu_is_self(cpu
)) {
258 void hvf_handle_io(CPUArchState
*env
, uint16_t port
, void *buffer
,
259 int direction
, int size
, int count
)
262 uint8_t *ptr
= buffer
;
264 for (i
= 0; i
< count
; i
++) {
265 address_space_rw(&address_space_io
, port
, MEMTXATTRS_UNSPECIFIED
,
272 /* TODO: synchronize vcpu state */
273 static void do_hvf_cpu_synchronize_state(CPUState
*cpu
, run_on_cpu_data arg
)
275 CPUState
*cpu_state
= cpu
;
276 if (cpu_state
->vcpu_dirty
== 0) {
277 hvf_get_registers(cpu_state
);
280 cpu_state
->vcpu_dirty
= 1;
283 void hvf_cpu_synchronize_state(CPUState
*cpu_state
)
285 if (cpu_state
->vcpu_dirty
== 0) {
286 run_on_cpu(cpu_state
, do_hvf_cpu_synchronize_state
, RUN_ON_CPU_NULL
);
290 static void do_hvf_cpu_synchronize_post_reset(CPUState
*cpu
, run_on_cpu_data arg
)
292 CPUState
*cpu_state
= cpu
;
293 hvf_put_registers(cpu_state
);
294 cpu_state
->vcpu_dirty
= false;
297 void hvf_cpu_synchronize_post_reset(CPUState
*cpu_state
)
299 run_on_cpu(cpu_state
, do_hvf_cpu_synchronize_post_reset
, RUN_ON_CPU_NULL
);
302 void _hvf_cpu_synchronize_post_init(CPUState
*cpu
, run_on_cpu_data arg
)
304 CPUState
*cpu_state
= cpu
;
305 hvf_put_registers(cpu_state
);
306 cpu_state
->vcpu_dirty
= false;
309 void hvf_cpu_synchronize_post_init(CPUState
*cpu_state
)
311 run_on_cpu(cpu_state
, _hvf_cpu_synchronize_post_init
, RUN_ON_CPU_NULL
);
314 static bool ept_emulation_fault(hvf_slot
*slot
, uint64_t gpa
, uint64_t ept_qual
)
318 /* EPT fault on an instruction fetch doesn't make sense here */
319 if (ept_qual
& EPT_VIOLATION_INST_FETCH
) {
323 /* EPT fault must be a read fault or a write fault */
324 read
= ept_qual
& EPT_VIOLATION_DATA_READ
? 1 : 0;
325 write
= ept_qual
& EPT_VIOLATION_DATA_WRITE
? 1 : 0;
326 if ((read
| write
) == 0) {
331 if (slot
->flags
& HVF_SLOT_LOG
) {
332 memory_region_set_dirty(slot
->region
, gpa
- slot
->start
, 1);
333 hv_vm_protect((hv_gpaddr_t
)slot
->start
, (size_t)slot
->size
,
334 HV_MEMORY_READ
| HV_MEMORY_WRITE
);
339 * The EPT violation must have been caused by accessing a
340 * guest-physical address that is a translation of a guest-linear
343 if ((ept_qual
& EPT_VIOLATION_GLA_VALID
) == 0 ||
344 (ept_qual
& EPT_VIOLATION_XLAT_VALID
) == 0) {
351 static void hvf_set_dirty_tracking(MemoryRegionSection
*section
, bool on
)
355 slot
= hvf_find_overlap_slot(
356 section
->offset_within_address_space
,
357 section
->offset_within_address_space
+ int128_get64(section
->size
));
359 /* protect region against writes; begin tracking it */
361 slot
->flags
|= HVF_SLOT_LOG
;
362 hv_vm_protect((hv_gpaddr_t
)slot
->start
, (size_t)slot
->size
,
364 /* stop tracking region*/
366 slot
->flags
&= ~HVF_SLOT_LOG
;
367 hv_vm_protect((hv_gpaddr_t
)slot
->start
, (size_t)slot
->size
,
368 HV_MEMORY_READ
| HV_MEMORY_WRITE
);
372 static void hvf_log_start(MemoryListener
*listener
,
373 MemoryRegionSection
*section
, int old
, int new)
379 hvf_set_dirty_tracking(section
, 1);
382 static void hvf_log_stop(MemoryListener
*listener
,
383 MemoryRegionSection
*section
, int old
, int new)
389 hvf_set_dirty_tracking(section
, 0);
392 static void hvf_log_sync(MemoryListener
*listener
,
393 MemoryRegionSection
*section
)
396 * sync of dirty pages is handled elsewhere; just make sure we keep
397 * tracking the region.
399 hvf_set_dirty_tracking(section
, 1);
402 static void hvf_region_add(MemoryListener
*listener
,
403 MemoryRegionSection
*section
)
405 hvf_set_phys_mem(section
, true);
408 static void hvf_region_del(MemoryListener
*listener
,
409 MemoryRegionSection
*section
)
411 hvf_set_phys_mem(section
, false);
414 static MemoryListener hvf_memory_listener
= {
416 .region_add
= hvf_region_add
,
417 .region_del
= hvf_region_del
,
418 .log_start
= hvf_log_start
,
419 .log_stop
= hvf_log_stop
,
420 .log_sync
= hvf_log_sync
,
423 void hvf_reset_vcpu(CPUState
*cpu
) {
425 /* TODO: this shouldn't be needed; there is already a call to
426 * cpu_synchronize_all_post_reset in vl.c
428 wvmcs(cpu
->hvf_fd
, VMCS_ENTRY_CTLS
, 0);
429 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_IA32_EFER
, 0);
430 macvm_set_cr0(cpu
->hvf_fd
, 0x60000010);
432 wvmcs(cpu
->hvf_fd
, VMCS_CR4_MASK
, CR4_VMXE_MASK
);
433 wvmcs(cpu
->hvf_fd
, VMCS_CR4_SHADOW
, 0x0);
434 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_CR4
, CR4_VMXE_MASK
);
436 /* set VMCS guest state fields */
437 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_CS_SELECTOR
, 0xf000);
438 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_CS_LIMIT
, 0xffff);
439 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_CS_ACCESS_RIGHTS
, 0x9b);
440 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_CS_BASE
, 0xffff0000);
442 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_DS_SELECTOR
, 0);
443 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_DS_LIMIT
, 0xffff);
444 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_DS_ACCESS_RIGHTS
, 0x93);
445 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_DS_BASE
, 0);
447 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_ES_SELECTOR
, 0);
448 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_ES_LIMIT
, 0xffff);
449 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_ES_ACCESS_RIGHTS
, 0x93);
450 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_ES_BASE
, 0);
452 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_FS_SELECTOR
, 0);
453 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_FS_LIMIT
, 0xffff);
454 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_FS_ACCESS_RIGHTS
, 0x93);
455 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_FS_BASE
, 0);
457 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_GS_SELECTOR
, 0);
458 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_GS_LIMIT
, 0xffff);
459 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_GS_ACCESS_RIGHTS
, 0x93);
460 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_GS_BASE
, 0);
462 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_SS_SELECTOR
, 0);
463 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_SS_LIMIT
, 0xffff);
464 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_SS_ACCESS_RIGHTS
, 0x93);
465 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_SS_BASE
, 0);
467 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_LDTR_SELECTOR
, 0);
468 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_LDTR_LIMIT
, 0);
469 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_LDTR_ACCESS_RIGHTS
, 0x10000);
470 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_LDTR_BASE
, 0);
472 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_TR_SELECTOR
, 0);
473 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_TR_LIMIT
, 0);
474 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_TR_ACCESS_RIGHTS
, 0x83);
475 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_TR_BASE
, 0);
477 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_GDTR_LIMIT
, 0);
478 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_GDTR_BASE
, 0);
480 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_IDTR_LIMIT
, 0);
481 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_IDTR_BASE
, 0);
483 /*wvmcs(cpu->hvf_fd, VMCS_GUEST_CR2, 0x0);*/
484 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_CR3
, 0x0);
486 wreg(cpu
->hvf_fd
, HV_X86_RIP
, 0xfff0);
487 wreg(cpu
->hvf_fd
, HV_X86_RDX
, 0x623);
488 wreg(cpu
->hvf_fd
, HV_X86_RFLAGS
, 0x2);
489 wreg(cpu
->hvf_fd
, HV_X86_RSP
, 0x0);
490 wreg(cpu
->hvf_fd
, HV_X86_RAX
, 0x0);
491 wreg(cpu
->hvf_fd
, HV_X86_RBX
, 0x0);
492 wreg(cpu
->hvf_fd
, HV_X86_RCX
, 0x0);
493 wreg(cpu
->hvf_fd
, HV_X86_RSI
, 0x0);
494 wreg(cpu
->hvf_fd
, HV_X86_RDI
, 0x0);
495 wreg(cpu
->hvf_fd
, HV_X86_RBP
, 0x0);
497 for (int i
= 0; i
< 8; i
++) {
498 wreg(cpu
->hvf_fd
, HV_X86_R8
+ i
, 0x0);
502 hv_vcpu_invalidate_tlb(cpu
->hvf_fd
);
503 hv_vcpu_flush(cpu
->hvf_fd
);
506 void hvf_vcpu_destroy(CPUState
*cpu
)
508 hv_return_t ret
= hv_vcpu_destroy((hv_vcpuid_t
)cpu
->hvf_fd
);
512 static void dummy_signal(int sig
)
516 int hvf_init_vcpu(CPUState
*cpu
)
519 X86CPU
*x86cpu
= X86_CPU(cpu
);
520 CPUX86State
*env
= &x86cpu
->env
;
523 /* init cpu signals */
525 struct sigaction sigact
;
527 memset(&sigact
, 0, sizeof(sigact
));
528 sigact
.sa_handler
= dummy_signal
;
529 sigaction(SIG_IPI
, &sigact
, NULL
);
531 pthread_sigmask(SIG_BLOCK
, NULL
, &set
);
532 sigdelset(&set
, SIG_IPI
);
537 hvf_state
->hvf_caps
= g_new0(struct hvf_vcpu_caps
, 1);
538 env
->hvf_emul
= g_new0(HVFX86EmulatorState
, 1);
540 r
= hv_vcpu_create((hv_vcpuid_t
*)&cpu
->hvf_fd
, HV_VCPU_DEFAULT
);
544 if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED
,
545 &hvf_state
->hvf_caps
->vmx_cap_pinbased
)) {
548 if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED
,
549 &hvf_state
->hvf_caps
->vmx_cap_procbased
)) {
552 if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2
,
553 &hvf_state
->hvf_caps
->vmx_cap_procbased2
)) {
556 if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY
,
557 &hvf_state
->hvf_caps
->vmx_cap_entry
)) {
561 /* set VMCS control fields */
562 wvmcs(cpu
->hvf_fd
, VMCS_PIN_BASED_CTLS
,
563 cap2ctrl(hvf_state
->hvf_caps
->vmx_cap_pinbased
,
564 VMCS_PIN_BASED_CTLS_EXTINT
|
565 VMCS_PIN_BASED_CTLS_NMI
|
566 VMCS_PIN_BASED_CTLS_VNMI
));
567 wvmcs(cpu
->hvf_fd
, VMCS_PRI_PROC_BASED_CTLS
,
568 cap2ctrl(hvf_state
->hvf_caps
->vmx_cap_procbased
,
569 VMCS_PRI_PROC_BASED_CTLS_HLT
|
570 VMCS_PRI_PROC_BASED_CTLS_MWAIT
|
571 VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET
|
572 VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW
) |
573 VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL
);
574 wvmcs(cpu
->hvf_fd
, VMCS_SEC_PROC_BASED_CTLS
,
575 cap2ctrl(hvf_state
->hvf_caps
->vmx_cap_procbased2
,
576 VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES
));
578 wvmcs(cpu
->hvf_fd
, VMCS_ENTRY_CTLS
, cap2ctrl(hvf_state
->hvf_caps
->vmx_cap_entry
,
580 wvmcs(cpu
->hvf_fd
, VMCS_EXCEPTION_BITMAP
, 0); /* Double fault */
582 wvmcs(cpu
->hvf_fd
, VMCS_TPR_THRESHOLD
, 0);
584 x86cpu
= X86_CPU(cpu
);
585 x86cpu
->env
.xsave_buf
= qemu_memalign(4096, 4096);
587 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_STAR
, 1);
588 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_LSTAR
, 1);
589 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_CSTAR
, 1);
590 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_FMASK
, 1);
591 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_FSBASE
, 1);
592 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_GSBASE
, 1);
593 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_KERNELGSBASE
, 1);
594 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_TSC_AUX
, 1);
595 /*hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1);*/
596 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_IA32_SYSENTER_CS
, 1);
597 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_IA32_SYSENTER_EIP
, 1);
598 hv_vcpu_enable_native_msr(cpu
->hvf_fd
, MSR_IA32_SYSENTER_ESP
, 1);
603 static void hvf_store_events(CPUState
*cpu
, uint32_t ins_len
, uint64_t idtvec_info
)
605 X86CPU
*x86_cpu
= X86_CPU(cpu
);
606 CPUX86State
*env
= &x86_cpu
->env
;
608 env
->exception_nr
= -1;
609 env
->exception_pending
= 0;
610 env
->exception_injected
= 0;
611 env
->interrupt_injected
= -1;
612 env
->nmi_injected
= false;
613 if (idtvec_info
& VMCS_IDT_VEC_VALID
) {
614 switch (idtvec_info
& VMCS_IDT_VEC_TYPE
) {
615 case VMCS_IDT_VEC_HWINTR
:
616 case VMCS_IDT_VEC_SWINTR
:
617 env
->interrupt_injected
= idtvec_info
& VMCS_IDT_VEC_VECNUM
;
619 case VMCS_IDT_VEC_NMI
:
620 env
->nmi_injected
= true;
622 case VMCS_IDT_VEC_HWEXCEPTION
:
623 case VMCS_IDT_VEC_SWEXCEPTION
:
624 env
->exception_nr
= idtvec_info
& VMCS_IDT_VEC_VECNUM
;
625 env
->exception_injected
= 1;
627 case VMCS_IDT_VEC_PRIV_SWEXCEPTION
:
631 if ((idtvec_info
& VMCS_IDT_VEC_TYPE
) == VMCS_IDT_VEC_SWEXCEPTION
||
632 (idtvec_info
& VMCS_IDT_VEC_TYPE
) == VMCS_IDT_VEC_SWINTR
) {
633 env
->ins_len
= ins_len
;
635 if (idtvec_info
& VMCS_INTR_DEL_ERRCODE
) {
636 env
->has_error_code
= true;
637 env
->error_code
= rvmcs(cpu
->hvf_fd
, VMCS_IDT_VECTORING_ERROR
);
640 if ((rvmcs(cpu
->hvf_fd
, VMCS_GUEST_INTERRUPTIBILITY
) &
641 VMCS_INTERRUPTIBILITY_NMI_BLOCKING
)) {
642 env
->hflags2
|= HF2_NMI_MASK
;
644 env
->hflags2
&= ~HF2_NMI_MASK
;
646 if (rvmcs(cpu
->hvf_fd
, VMCS_GUEST_INTERRUPTIBILITY
) &
647 (VMCS_INTERRUPTIBILITY_STI_BLOCKING
|
648 VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING
)) {
649 env
->hflags
|= HF_INHIBIT_IRQ_MASK
;
651 env
->hflags
&= ~HF_INHIBIT_IRQ_MASK
;
655 int hvf_vcpu_exec(CPUState
*cpu
)
657 X86CPU
*x86_cpu
= X86_CPU(cpu
);
658 CPUX86State
*env
= &x86_cpu
->env
;
662 if (hvf_process_events(cpu
)) {
667 if (cpu
->vcpu_dirty
) {
668 hvf_put_registers(cpu
);
669 cpu
->vcpu_dirty
= false;
672 if (hvf_inject_interrupts(cpu
)) {
673 return EXCP_INTERRUPT
;
677 qemu_mutex_unlock_iothread();
678 if (!cpu_is_bsp(X86_CPU(cpu
)) && cpu
->halted
) {
679 qemu_mutex_lock_iothread();
683 hv_return_t r
= hv_vcpu_run(cpu
->hvf_fd
);
687 uint64_t exit_reason
= rvmcs(cpu
->hvf_fd
, VMCS_EXIT_REASON
);
688 uint64_t exit_qual
= rvmcs(cpu
->hvf_fd
, VMCS_EXIT_QUALIFICATION
);
689 uint32_t ins_len
= (uint32_t)rvmcs(cpu
->hvf_fd
,
690 VMCS_EXIT_INSTRUCTION_LENGTH
);
692 uint64_t idtvec_info
= rvmcs(cpu
->hvf_fd
, VMCS_IDT_VECTORING_INFO
);
694 hvf_store_events(cpu
, ins_len
, idtvec_info
);
695 rip
= rreg(cpu
->hvf_fd
, HV_X86_RIP
);
696 RFLAGS(env
) = rreg(cpu
->hvf_fd
, HV_X86_RFLAGS
);
697 env
->eflags
= RFLAGS(env
);
699 qemu_mutex_lock_iothread();
701 update_apic_tpr(cpu
);
705 switch (exit_reason
) {
706 case EXIT_REASON_HLT
: {
707 macvm_set_rip(cpu
, rip
+ ins_len
);
708 if (!((cpu
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
709 (EFLAGS(env
) & IF_MASK
))
710 && !(cpu
->interrupt_request
& CPU_INTERRUPT_NMI
) &&
711 !(idtvec_info
& VMCS_IDT_VEC_VALID
)) {
716 ret
= EXCP_INTERRUPT
;
719 case EXIT_REASON_MWAIT
: {
720 ret
= EXCP_INTERRUPT
;
723 /* Need to check if MMIO or unmmaped fault */
724 case EXIT_REASON_EPT_FAULT
:
727 uint64_t gpa
= rvmcs(cpu
->hvf_fd
, VMCS_GUEST_PHYSICAL_ADDRESS
);
729 if (((idtvec_info
& VMCS_IDT_VEC_VALID
) == 0) &&
730 ((exit_qual
& EXIT_QUAL_NMIUDTI
) != 0)) {
731 vmx_set_nmi_blocking(cpu
);
734 slot
= hvf_find_overlap_slot(gpa
, gpa
);
736 if (ept_emulation_fault(slot
, gpa
, exit_qual
)) {
737 struct x86_decode decode
;
740 env
->hvf_emul
->fetch_rip
= rip
;
742 decode_instruction(env
, &decode
);
743 exec_instruction(env
, &decode
);
749 case EXIT_REASON_INOUT
:
751 uint32_t in
= (exit_qual
& 8) != 0;
752 uint32_t size
= (exit_qual
& 7) + 1;
753 uint32_t string
= (exit_qual
& 16) != 0;
754 uint32_t port
= exit_qual
>> 16;
755 /*uint32_t rep = (exit_qual & 0x20) != 0;*/
760 hvf_handle_io(env
, port
, &val
, 0, size
, 1);
763 } else if (size
== 2) {
765 } else if (size
== 4) {
766 RAX(env
) = (uint32_t)val
;
768 RAX(env
) = (uint64_t)val
;
773 } else if (!string
&& !in
) {
774 RAX(env
) = rreg(cpu
->hvf_fd
, HV_X86_RAX
);
775 hvf_handle_io(env
, port
, &RAX(env
), 1, size
, 1);
776 macvm_set_rip(cpu
, rip
+ ins_len
);
779 struct x86_decode decode
;
782 env
->hvf_emul
->fetch_rip
= rip
;
784 decode_instruction(env
, &decode
);
785 assert(ins_len
== decode
.len
);
786 exec_instruction(env
, &decode
);
791 case EXIT_REASON_CPUID
: {
792 uint32_t rax
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RAX
);
793 uint32_t rbx
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RBX
);
794 uint32_t rcx
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RCX
);
795 uint32_t rdx
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RDX
);
797 cpu_x86_cpuid(env
, rax
, rcx
, &rax
, &rbx
, &rcx
, &rdx
);
799 wreg(cpu
->hvf_fd
, HV_X86_RAX
, rax
);
800 wreg(cpu
->hvf_fd
, HV_X86_RBX
, rbx
);
801 wreg(cpu
->hvf_fd
, HV_X86_RCX
, rcx
);
802 wreg(cpu
->hvf_fd
, HV_X86_RDX
, rdx
);
804 macvm_set_rip(cpu
, rip
+ ins_len
);
807 case EXIT_REASON_XSETBV
: {
808 X86CPU
*x86_cpu
= X86_CPU(cpu
);
809 CPUX86State
*env
= &x86_cpu
->env
;
810 uint32_t eax
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RAX
);
811 uint32_t ecx
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RCX
);
812 uint32_t edx
= (uint32_t)rreg(cpu
->hvf_fd
, HV_X86_RDX
);
815 macvm_set_rip(cpu
, rip
+ ins_len
);
818 env
->xcr0
= ((uint64_t)edx
<< 32) | eax
;
819 wreg(cpu
->hvf_fd
, HV_X86_XCR0
, env
->xcr0
| 1);
820 macvm_set_rip(cpu
, rip
+ ins_len
);
823 case EXIT_REASON_INTR_WINDOW
:
824 vmx_clear_int_window_exiting(cpu
);
825 ret
= EXCP_INTERRUPT
;
827 case EXIT_REASON_NMI_WINDOW
:
828 vmx_clear_nmi_window_exiting(cpu
);
829 ret
= EXCP_INTERRUPT
;
831 case EXIT_REASON_EXT_INTR
:
832 /* force exit and allow io handling */
833 ret
= EXCP_INTERRUPT
;
835 case EXIT_REASON_RDMSR
:
836 case EXIT_REASON_WRMSR
:
839 if (exit_reason
== EXIT_REASON_RDMSR
) {
844 RIP(env
) += rvmcs(cpu
->hvf_fd
, VMCS_EXIT_INSTRUCTION_LENGTH
);
848 case EXIT_REASON_CR_ACCESS
: {
854 reg
= (exit_qual
>> 8) & 15;
858 macvm_set_cr0(cpu
->hvf_fd
, RRX(env
, reg
));
862 macvm_set_cr4(cpu
->hvf_fd
, RRX(env
, reg
));
866 X86CPU
*x86_cpu
= X86_CPU(cpu
);
867 if (exit_qual
& 0x10) {
868 RRX(env
, reg
) = cpu_get_apic_tpr(x86_cpu
->apic_state
);
870 int tpr
= RRX(env
, reg
);
871 cpu_set_apic_tpr(x86_cpu
->apic_state
, tpr
);
872 ret
= EXCP_INTERRUPT
;
877 error_report("Unrecognized CR %d", cr
);
884 case EXIT_REASON_APIC_ACCESS
: { /* TODO */
885 struct x86_decode decode
;
888 env
->hvf_emul
->fetch_rip
= rip
;
890 decode_instruction(env
, &decode
);
891 exec_instruction(env
, &decode
);
895 case EXIT_REASON_TPR
: {
899 case EXIT_REASON_TASK_SWITCH
: {
900 uint64_t vinfo
= rvmcs(cpu
->hvf_fd
, VMCS_IDT_VECTORING_INFO
);
901 x68_segment_selector sel
= {.sel
= exit_qual
& 0xffff};
902 vmx_handle_task_switch(cpu
, sel
, (exit_qual
>> 30) & 0x3,
903 vinfo
& VMCS_INTR_VALID
, vinfo
& VECTORING_INFO_VECTOR_MASK
, vinfo
907 case EXIT_REASON_TRIPLE_FAULT
: {
908 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
909 ret
= EXCP_INTERRUPT
;
912 case EXIT_REASON_RDPMC
:
913 wreg(cpu
->hvf_fd
, HV_X86_RAX
, 0);
914 wreg(cpu
->hvf_fd
, HV_X86_RDX
, 0);
915 macvm_set_rip(cpu
, rip
+ ins_len
);
917 case VMX_REASON_VMCALL
:
918 env
->exception_nr
= EXCP0D_GPF
;
919 env
->exception_injected
= 1;
920 env
->has_error_code
= true;
924 error_report("%llx: unhandled exit %llx", rip
, exit_reason
);
933 static int hvf_accel_init(MachineState
*ms
)
939 ret
= hv_vm_create(HV_VM_DEFAULT
);
942 s
= g_new0(HVFState
, 1);
945 for (x
= 0; x
< s
->num_slots
; ++x
) {
946 s
->slots
[x
].size
= 0;
947 s
->slots
[x
].slot_id
= x
;
951 cpu_interrupt_handler
= hvf_handle_interrupt
;
952 memory_listener_register(&hvf_memory_listener
, &address_space_memory
);
956 static void hvf_accel_class_init(ObjectClass
*oc
, void *data
)
958 AccelClass
*ac
= ACCEL_CLASS(oc
);
960 ac
->init_machine
= hvf_accel_init
;
961 ac
->allowed
= &hvf_allowed
;
964 static const TypeInfo hvf_accel_type
= {
965 .name
= TYPE_HVF_ACCEL
,
966 .parent
= TYPE_ACCEL
,
967 .class_init
= hvf_accel_class_init
,
970 static void hvf_type_init(void)
972 type_register_static(&hvf_accel_type
);
975 type_init(hvf_type_init
);