]>
git.proxmox.com Git - mirror_qemu.git/blob - target/i386/hvf/x86_emu.c
2 * Copyright (C) 2016 Veertu Inc,
3 * Copyright (C) 2017 Google Inc,
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU Lesser General Public
7 * License as published by the Free Software Foundation; either
8 * version 2 of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this program; if not, see <http://www.gnu.org/licenses/>.
19 /////////////////////////////////////////////////////////////////////////
21 // Copyright (C) 2001-2012 The Bochs Project
23 // This library is free software; you can redistribute it and/or
24 // modify it under the terms of the GNU Lesser General Public
25 // License as published by the Free Software Foundation; either
26 // version 2 of the License, or (at your option) any later version.
28 // This library is distributed in the hope that it will be useful,
29 // but WITHOUT ANY WARRANTY; without even the implied warranty of
30 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
31 // Lesser General Public License for more details.
33 // You should have received a copy of the GNU Lesser General Public
34 // License along with this library; if not, write to the Free Software
35 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
36 /////////////////////////////////////////////////////////////////////////
38 #include "qemu/osdep.h"
40 #include "qemu-common.h"
41 #include "x86_decode.h"
45 #include "x86_flags.h"
49 void hvf_handle_io(struct CPUState
*cpu
, uint16_t port
, void *data
,
50 int direction
, int size
, uint32_t count
);
52 #define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \
54 fetch_operands(env, decode, 2, true, true, false); \
55 switch (decode->operand_size) { \
58 uint8_t v1 = (uint8_t)decode->op[0].val; \
59 uint8_t v2 = (uint8_t)decode->op[1].val; \
60 uint8_t diff = v1 cmd v2; \
62 write_val_ext(env, decode->op[0].ptr, diff, 1); \
64 FLAGS_FUNC##8(env, v1, v2, diff); \
69 uint16_t v1 = (uint16_t)decode->op[0].val; \
70 uint16_t v2 = (uint16_t)decode->op[1].val; \
71 uint16_t diff = v1 cmd v2; \
73 write_val_ext(env, decode->op[0].ptr, diff, 2); \
75 FLAGS_FUNC##16(env, v1, v2, diff); \
80 uint32_t v1 = (uint32_t)decode->op[0].val; \
81 uint32_t v2 = (uint32_t)decode->op[1].val; \
82 uint32_t diff = v1 cmd v2; \
84 write_val_ext(env, decode->op[0].ptr, diff, 4); \
86 FLAGS_FUNC##32(env, v1, v2, diff); \
90 VM_PANIC("bad size\n"); \
94 target_ulong read_reg(CPUX86State *env, int reg, int size)
98 return env
->hvf_emul
->regs
[reg
].lx
;
100 return env
->hvf_emul
->regs
[reg
].rx
;
102 return env
->hvf_emul
->regs
[reg
].erx
;
104 return env
->hvf_emul
->regs
[reg
].rrx
;
111 void write_reg(CPUX86State
*env
, int reg
, target_ulong val
, int size
)
115 env
->hvf_emul
->regs
[reg
].lx
= val
;
118 env
->hvf_emul
->regs
[reg
].rx
= val
;
121 env
->hvf_emul
->regs
[reg
].rrx
= (uint32_t)val
;
124 env
->hvf_emul
->regs
[reg
].rrx
= val
;
131 target_ulong
read_val_from_reg(target_ulong reg_ptr
, int size
)
137 val
= *(uint8_t *)reg_ptr
;
140 val
= *(uint16_t *)reg_ptr
;
143 val
= *(uint32_t *)reg_ptr
;
146 val
= *(uint64_t *)reg_ptr
;
154 void write_val_to_reg(target_ulong reg_ptr
, target_ulong val
, int size
)
158 *(uint8_t *)reg_ptr
= val
;
161 *(uint16_t *)reg_ptr
= val
;
164 *(uint64_t *)reg_ptr
= (uint32_t)val
;
167 *(uint64_t *)reg_ptr
= val
;
174 static bool is_host_reg(struct CPUX86State
*env
, target_ulong ptr
)
176 return (ptr
- (target_ulong
)&env
->hvf_emul
->regs
[0]) < sizeof(env
->hvf_emul
->regs
);
179 void write_val_ext(struct CPUX86State
*env
, target_ulong ptr
, target_ulong val
, int size
)
181 if (is_host_reg(env
, ptr
)) {
182 write_val_to_reg(ptr
, val
, size
);
185 vmx_write_mem(env_cpu(env
), ptr
, &val
, size
);
188 uint8_t *read_mmio(struct CPUX86State
*env
, target_ulong ptr
, int bytes
)
190 vmx_read_mem(env_cpu(env
), env
->hvf_emul
->mmio_buf
, ptr
, bytes
);
191 return env
->hvf_emul
->mmio_buf
;
195 target_ulong
read_val_ext(struct CPUX86State
*env
, target_ulong ptr
, int size
)
200 if (is_host_reg(env
, ptr
)) {
201 return read_val_from_reg(ptr
, size
);
204 mmio_ptr
= read_mmio(env
, ptr
, size
);
207 val
= *(uint8_t *)mmio_ptr
;
210 val
= *(uint16_t *)mmio_ptr
;
213 val
= *(uint32_t *)mmio_ptr
;
216 val
= *(uint64_t *)mmio_ptr
;
219 VM_PANIC("bad size\n");
225 static void fetch_operands(struct CPUX86State
*env
, struct x86_decode
*decode
,
226 int n
, bool val_op0
, bool val_op1
, bool val_op2
)
229 bool calc_val
[3] = {val_op0
, val_op1
, val_op2
};
231 for (i
= 0; i
< n
; i
++) {
232 switch (decode
->op
[i
].type
) {
233 case X86_VAR_IMMEDIATE
:
236 VM_PANIC_ON(!decode
->op
[i
].ptr
);
238 decode
->op
[i
].val
= read_val_from_reg(decode
->op
[i
].ptr
,
239 decode
->operand_size
);
243 calc_modrm_operand(env
, decode
, &decode
->op
[i
]);
245 decode
->op
[i
].val
= read_val_ext(env
, decode
->op
[i
].ptr
,
246 decode
->operand_size
);
250 decode
->op
[i
].ptr
= decode_linear_addr(env
, decode
,
254 decode
->op
[i
].val
= read_val_ext(env
, decode
->op
[i
].ptr
,
255 decode
->operand_size
);
264 static void exec_mov(struct CPUX86State
*env
, struct x86_decode
*decode
)
266 fetch_operands(env
, decode
, 2, false, true, false);
267 write_val_ext(env
, decode
->op
[0].ptr
, decode
->op
[1].val
,
268 decode
->operand_size
);
270 RIP(env
) += decode
->len
;
273 static void exec_add(struct CPUX86State
*env
, struct x86_decode
*decode
)
275 EXEC_2OP_FLAGS_CMD(env
, decode
, +, SET_FLAGS_OSZAPC_ADD
, true);
276 RIP(env
) += decode
->len
;
279 static void exec_or(struct CPUX86State
*env
, struct x86_decode
*decode
)
281 EXEC_2OP_FLAGS_CMD(env
, decode
, |, SET_FLAGS_OSZAPC_LOGIC
, true);
282 RIP(env
) += decode
->len
;
285 static void exec_adc(struct CPUX86State
*env
, struct x86_decode
*decode
)
287 EXEC_2OP_FLAGS_CMD(env
, decode
, +get_CF(env
)+, SET_FLAGS_OSZAPC_ADD
, true);
288 RIP(env
) += decode
->len
;
291 static void exec_sbb(struct CPUX86State
*env
, struct x86_decode
*decode
)
293 EXEC_2OP_FLAGS_CMD(env
, decode
, -get_CF(env
)-, SET_FLAGS_OSZAPC_SUB
, true);
294 RIP(env
) += decode
->len
;
297 static void exec_and(struct CPUX86State
*env
, struct x86_decode
*decode
)
299 EXEC_2OP_FLAGS_CMD(env
, decode
, &, SET_FLAGS_OSZAPC_LOGIC
, true);
300 RIP(env
) += decode
->len
;
303 static void exec_sub(struct CPUX86State
*env
, struct x86_decode
*decode
)
305 EXEC_2OP_FLAGS_CMD(env
, decode
, -, SET_FLAGS_OSZAPC_SUB
, true);
306 RIP(env
) += decode
->len
;
309 static void exec_xor(struct CPUX86State
*env
, struct x86_decode
*decode
)
311 EXEC_2OP_FLAGS_CMD(env
, decode
, ^, SET_FLAGS_OSZAPC_LOGIC
, true);
312 RIP(env
) += decode
->len
;
315 static void exec_neg(struct CPUX86State
*env
, struct x86_decode
*decode
)
317 /*EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);*/
319 fetch_operands(env
, decode
, 2, true, true, false);
321 val
= 0 - sign(decode
->op
[1].val
, decode
->operand_size
);
322 write_val_ext(env
, decode
->op
[1].ptr
, val
, decode
->operand_size
);
324 if (4 == decode
->operand_size
) {
325 SET_FLAGS_OSZAPC_SUB32(env
, 0, 0 - val
, val
);
326 } else if (2 == decode
->operand_size
) {
327 SET_FLAGS_OSZAPC_SUB16(env
, 0, 0 - val
, val
);
328 } else if (1 == decode
->operand_size
) {
329 SET_FLAGS_OSZAPC_SUB8(env
, 0, 0 - val
, val
);
331 VM_PANIC("bad op size\n");
334 /*lflags_to_rflags(env);*/
335 RIP(env
) += decode
->len
;
338 static void exec_cmp(struct CPUX86State
*env
, struct x86_decode
*decode
)
340 EXEC_2OP_FLAGS_CMD(env
, decode
, -, SET_FLAGS_OSZAPC_SUB
, false);
341 RIP(env
) += decode
->len
;
344 static void exec_inc(struct CPUX86State
*env
, struct x86_decode
*decode
)
346 decode
->op
[1].type
= X86_VAR_IMMEDIATE
;
347 decode
->op
[1].val
= 0;
349 EXEC_2OP_FLAGS_CMD(env
, decode
, +1+, SET_FLAGS_OSZAP_ADD
, true);
351 RIP(env
) += decode
->len
;
354 static void exec_dec(struct CPUX86State
*env
, struct x86_decode
*decode
)
356 decode
->op
[1].type
= X86_VAR_IMMEDIATE
;
357 decode
->op
[1].val
= 0;
359 EXEC_2OP_FLAGS_CMD(env
, decode
, -1-, SET_FLAGS_OSZAP_SUB
, true);
360 RIP(env
) += decode
->len
;
363 static void exec_tst(struct CPUX86State
*env
, struct x86_decode
*decode
)
365 EXEC_2OP_FLAGS_CMD(env
, decode
, &, SET_FLAGS_OSZAPC_LOGIC
, false);
366 RIP(env
) += decode
->len
;
369 static void exec_not(struct CPUX86State
*env
, struct x86_decode
*decode
)
371 fetch_operands(env
, decode
, 1, true, false, false);
373 write_val_ext(env
, decode
->op
[0].ptr
, ~decode
->op
[0].val
,
374 decode
->operand_size
);
375 RIP(env
) += decode
->len
;
378 void exec_movzx(struct CPUX86State
*env
, struct x86_decode
*decode
)
381 int op_size
= decode
->operand_size
;
383 fetch_operands(env
, decode
, 1, false, false, false);
385 if (0xb6 == decode
->opcode
[1]) {
390 decode
->operand_size
= src_op_size
;
391 calc_modrm_operand(env
, decode
, &decode
->op
[1]);
392 decode
->op
[1].val
= read_val_ext(env
, decode
->op
[1].ptr
, src_op_size
);
393 write_val_ext(env
, decode
->op
[0].ptr
, decode
->op
[1].val
, op_size
);
395 RIP(env
) += decode
->len
;
398 static void exec_out(struct CPUX86State
*env
, struct x86_decode
*decode
)
400 switch (decode
->opcode
[0]) {
402 hvf_handle_io(env_cpu(env
), decode
->op
[0].val
, &AL(env
), 1, 1, 1);
405 hvf_handle_io(env_cpu(env
), decode
->op
[0].val
, &RAX(env
), 1,
406 decode
->operand_size
, 1);
409 hvf_handle_io(env_cpu(env
), DX(env
), &AL(env
), 1, 1, 1);
412 hvf_handle_io(env_cpu(env
), DX(env
), &RAX(env
), 1,
413 decode
->operand_size
, 1);
416 VM_PANIC("Bad out opcode\n");
419 RIP(env
) += decode
->len
;
422 static void exec_in(struct CPUX86State
*env
, struct x86_decode
*decode
)
424 target_ulong val
= 0;
425 switch (decode
->opcode
[0]) {
427 hvf_handle_io(env_cpu(env
), decode
->op
[0].val
, &AL(env
), 0, 1, 1);
430 hvf_handle_io(env_cpu(env
), decode
->op
[0].val
, &val
, 0,
431 decode
->operand_size
, 1);
432 if (decode
->operand_size
== 2) {
435 RAX(env
) = (uint32_t)val
;
439 hvf_handle_io(env_cpu(env
), DX(env
), &AL(env
), 0, 1, 1);
442 hvf_handle_io(env_cpu(env
), DX(env
), &val
, 0, decode
->operand_size
, 1);
443 if (decode
->operand_size
== 2) {
446 RAX(env
) = (uint32_t)val
;
451 VM_PANIC("Bad in opcode\n");
455 RIP(env
) += decode
->len
;
458 static inline void string_increment_reg(struct CPUX86State
*env
, int reg
,
459 struct x86_decode
*decode
)
461 target_ulong val
= read_reg(env
, reg
, decode
->addressing_size
);
462 if (env
->hvf_emul
->rflags
.df
) {
463 val
-= decode
->operand_size
;
465 val
+= decode
->operand_size
;
467 write_reg(env
, reg
, val
, decode
->addressing_size
);
470 static inline void string_rep(struct CPUX86State
*env
, struct x86_decode
*decode
,
471 void (*func
)(struct CPUX86State
*env
,
472 struct x86_decode
*ins
), int rep
)
474 target_ulong rcx
= read_reg(env
, R_ECX
, decode
->addressing_size
);
477 write_reg(env
, R_ECX
, rcx
, decode
->addressing_size
);
478 if ((PREFIX_REP
== rep
) && !get_ZF(env
)) {
481 if ((PREFIX_REPN
== rep
) && get_ZF(env
)) {
487 static void exec_ins_single(struct CPUX86State
*env
, struct x86_decode
*decode
)
489 target_ulong addr
= linear_addr_size(env_cpu(env
), RDI(env
),
490 decode
->addressing_size
, R_ES
);
492 hvf_handle_io(env_cpu(env
), DX(env
), env
->hvf_emul
->mmio_buf
, 0,
493 decode
->operand_size
, 1);
494 vmx_write_mem(env_cpu(env
), addr
, env
->hvf_emul
->mmio_buf
,
495 decode
->operand_size
);
497 string_increment_reg(env
, R_EDI
, decode
);
500 static void exec_ins(struct CPUX86State
*env
, struct x86_decode
*decode
)
503 string_rep(env
, decode
, exec_ins_single
, 0);
505 exec_ins_single(env
, decode
);
508 RIP(env
) += decode
->len
;
511 static void exec_outs_single(struct CPUX86State
*env
, struct x86_decode
*decode
)
513 target_ulong addr
= decode_linear_addr(env
, decode
, RSI(env
), R_DS
);
515 vmx_read_mem(env_cpu(env
), env
->hvf_emul
->mmio_buf
, addr
,
516 decode
->operand_size
);
517 hvf_handle_io(env_cpu(env
), DX(env
), env
->hvf_emul
->mmio_buf
, 1,
518 decode
->operand_size
, 1);
520 string_increment_reg(env
, R_ESI
, decode
);
523 static void exec_outs(struct CPUX86State
*env
, struct x86_decode
*decode
)
526 string_rep(env
, decode
, exec_outs_single
, 0);
528 exec_outs_single(env
, decode
);
531 RIP(env
) += decode
->len
;
534 static void exec_movs_single(struct CPUX86State
*env
, struct x86_decode
*decode
)
536 target_ulong src_addr
;
537 target_ulong dst_addr
;
540 src_addr
= decode_linear_addr(env
, decode
, RSI(env
), R_DS
);
541 dst_addr
= linear_addr_size(env_cpu(env
), RDI(env
),
542 decode
->addressing_size
, R_ES
);
544 val
= read_val_ext(env
, src_addr
, decode
->operand_size
);
545 write_val_ext(env
, dst_addr
, val
, decode
->operand_size
);
547 string_increment_reg(env
, R_ESI
, decode
);
548 string_increment_reg(env
, R_EDI
, decode
);
551 static void exec_movs(struct CPUX86State
*env
, struct x86_decode
*decode
)
554 string_rep(env
, decode
, exec_movs_single
, 0);
556 exec_movs_single(env
, decode
);
559 RIP(env
) += decode
->len
;
562 static void exec_cmps_single(struct CPUX86State
*env
, struct x86_decode
*decode
)
564 target_ulong src_addr
;
565 target_ulong dst_addr
;
567 src_addr
= decode_linear_addr(env
, decode
, RSI(env
), R_DS
);
568 dst_addr
= linear_addr_size(env_cpu(env
), RDI(env
),
569 decode
->addressing_size
, R_ES
);
571 decode
->op
[0].type
= X86_VAR_IMMEDIATE
;
572 decode
->op
[0].val
= read_val_ext(env
, src_addr
, decode
->operand_size
);
573 decode
->op
[1].type
= X86_VAR_IMMEDIATE
;
574 decode
->op
[1].val
= read_val_ext(env
, dst_addr
, decode
->operand_size
);
576 EXEC_2OP_FLAGS_CMD(env
, decode
, -, SET_FLAGS_OSZAPC_SUB
, false);
578 string_increment_reg(env
, R_ESI
, decode
);
579 string_increment_reg(env
, R_EDI
, decode
);
582 static void exec_cmps(struct CPUX86State
*env
, struct x86_decode
*decode
)
585 string_rep(env
, decode
, exec_cmps_single
, decode
->rep
);
587 exec_cmps_single(env
, decode
);
589 RIP(env
) += decode
->len
;
593 static void exec_stos_single(struct CPUX86State
*env
, struct x86_decode
*decode
)
598 addr
= linear_addr_size(env_cpu(env
), RDI(env
),
599 decode
->addressing_size
, R_ES
);
600 val
= read_reg(env
, R_EAX
, decode
->operand_size
);
601 vmx_write_mem(env_cpu(env
), addr
, &val
, decode
->operand_size
);
603 string_increment_reg(env
, R_EDI
, decode
);
607 static void exec_stos(struct CPUX86State
*env
, struct x86_decode
*decode
)
610 string_rep(env
, decode
, exec_stos_single
, 0);
612 exec_stos_single(env
, decode
);
615 RIP(env
) += decode
->len
;
618 static void exec_scas_single(struct CPUX86State
*env
, struct x86_decode
*decode
)
622 addr
= linear_addr_size(env_cpu(env
), RDI(env
),
623 decode
->addressing_size
, R_ES
);
624 decode
->op
[1].type
= X86_VAR_IMMEDIATE
;
625 vmx_read_mem(env_cpu(env
), &decode
->op
[1].val
, addr
, decode
->operand_size
);
627 EXEC_2OP_FLAGS_CMD(env
, decode
, -, SET_FLAGS_OSZAPC_SUB
, false);
628 string_increment_reg(env
, R_EDI
, decode
);
631 static void exec_scas(struct CPUX86State
*env
, struct x86_decode
*decode
)
633 decode
->op
[0].type
= X86_VAR_REG
;
634 decode
->op
[0].reg
= R_EAX
;
636 string_rep(env
, decode
, exec_scas_single
, decode
->rep
);
638 exec_scas_single(env
, decode
);
641 RIP(env
) += decode
->len
;
644 static void exec_lods_single(struct CPUX86State
*env
, struct x86_decode
*decode
)
647 target_ulong val
= 0;
649 addr
= decode_linear_addr(env
, decode
, RSI(env
), R_DS
);
650 vmx_read_mem(env_cpu(env
), &val
, addr
, decode
->operand_size
);
651 write_reg(env
, R_EAX
, val
, decode
->operand_size
);
653 string_increment_reg(env
, R_ESI
, decode
);
656 static void exec_lods(struct CPUX86State
*env
, struct x86_decode
*decode
)
659 string_rep(env
, decode
, exec_lods_single
, 0);
661 exec_lods_single(env
, decode
);
664 RIP(env
) += decode
->len
;
667 #define MSR_IA32_UCODE_REV 0x00000017
669 void simulate_rdmsr(struct CPUState
*cpu
)
671 X86CPU
*x86_cpu
= X86_CPU(cpu
);
672 CPUX86State
*env
= &x86_cpu
->env
;
673 uint32_t msr
= ECX(env
);
678 val
= rdtscp() + rvmcs(cpu
->hvf_fd
, VMCS_TSC_OFFSET
);
680 case MSR_IA32_APICBASE
:
681 val
= cpu_get_apic_base(X86_CPU(cpu
)->apic_state
);
683 case MSR_IA32_UCODE_REV
:
684 val
= (0x100000000ULL
<< 32) | 0x100000000ULL
;
687 val
= rvmcs(cpu
->hvf_fd
, VMCS_GUEST_IA32_EFER
);
690 val
= rvmcs(cpu
->hvf_fd
, VMCS_GUEST_FS_BASE
);
693 val
= rvmcs(cpu
->hvf_fd
, VMCS_GUEST_GS_BASE
);
695 case MSR_KERNELGSBASE
:
696 val
= rvmcs(cpu
->hvf_fd
, VMCS_HOST_FS_BASE
);
707 case MSR_IA32_MISC_ENABLE
:
708 val
= env
->msr_ia32_misc_enable
;
710 case MSR_MTRRphysBase(0):
711 case MSR_MTRRphysBase(1):
712 case MSR_MTRRphysBase(2):
713 case MSR_MTRRphysBase(3):
714 case MSR_MTRRphysBase(4):
715 case MSR_MTRRphysBase(5):
716 case MSR_MTRRphysBase(6):
717 case MSR_MTRRphysBase(7):
718 val
= env
->mtrr_var
[(ECX(env
) - MSR_MTRRphysBase(0)) / 2].base
;
720 case MSR_MTRRphysMask(0):
721 case MSR_MTRRphysMask(1):
722 case MSR_MTRRphysMask(2):
723 case MSR_MTRRphysMask(3):
724 case MSR_MTRRphysMask(4):
725 case MSR_MTRRphysMask(5):
726 case MSR_MTRRphysMask(6):
727 case MSR_MTRRphysMask(7):
728 val
= env
->mtrr_var
[(ECX(env
) - MSR_MTRRphysMask(0)) / 2].mask
;
730 case MSR_MTRRfix64K_00000
:
731 val
= env
->mtrr_fixed
[0];
733 case MSR_MTRRfix16K_80000
:
734 case MSR_MTRRfix16K_A0000
:
735 val
= env
->mtrr_fixed
[ECX(env
) - MSR_MTRRfix16K_80000
+ 1];
737 case MSR_MTRRfix4K_C0000
:
738 case MSR_MTRRfix4K_C8000
:
739 case MSR_MTRRfix4K_D0000
:
740 case MSR_MTRRfix4K_D8000
:
741 case MSR_MTRRfix4K_E0000
:
742 case MSR_MTRRfix4K_E8000
:
743 case MSR_MTRRfix4K_F0000
:
744 case MSR_MTRRfix4K_F8000
:
745 val
= env
->mtrr_fixed
[ECX(env
) - MSR_MTRRfix4K_C0000
+ 3];
747 case MSR_MTRRdefType
:
748 val
= env
->mtrr_deftype
;
751 /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */
756 RAX(env
) = (uint32_t)val
;
757 RDX(env
) = (uint32_t)(val
>> 32);
760 static void exec_rdmsr(struct CPUX86State
*env
, struct x86_decode
*decode
)
762 simulate_rdmsr(env_cpu(env
));
763 RIP(env
) += decode
->len
;
766 void simulate_wrmsr(struct CPUState
*cpu
)
768 X86CPU
*x86_cpu
= X86_CPU(cpu
);
769 CPUX86State
*env
= &x86_cpu
->env
;
770 uint32_t msr
= ECX(env
);
771 uint64_t data
= ((uint64_t)EDX(env
) << 32) | EAX(env
);
776 case MSR_IA32_APICBASE
:
777 cpu_set_apic_base(X86_CPU(cpu
)->apic_state
, data
);
780 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_FS_BASE
, data
);
783 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_GS_BASE
, data
);
785 case MSR_KERNELGSBASE
:
786 wvmcs(cpu
->hvf_fd
, VMCS_HOST_FS_BASE
, data
);
798 /*printf("new efer %llx\n", EFER(cpu));*/
799 wvmcs(cpu
->hvf_fd
, VMCS_GUEST_IA32_EFER
, data
);
800 if (data
& MSR_EFER_NXE
) {
801 hv_vcpu_invalidate_tlb(cpu
->hvf_fd
);
804 case MSR_MTRRphysBase(0):
805 case MSR_MTRRphysBase(1):
806 case MSR_MTRRphysBase(2):
807 case MSR_MTRRphysBase(3):
808 case MSR_MTRRphysBase(4):
809 case MSR_MTRRphysBase(5):
810 case MSR_MTRRphysBase(6):
811 case MSR_MTRRphysBase(7):
812 env
->mtrr_var
[(ECX(env
) - MSR_MTRRphysBase(0)) / 2].base
= data
;
814 case MSR_MTRRphysMask(0):
815 case MSR_MTRRphysMask(1):
816 case MSR_MTRRphysMask(2):
817 case MSR_MTRRphysMask(3):
818 case MSR_MTRRphysMask(4):
819 case MSR_MTRRphysMask(5):
820 case MSR_MTRRphysMask(6):
821 case MSR_MTRRphysMask(7):
822 env
->mtrr_var
[(ECX(env
) - MSR_MTRRphysMask(0)) / 2].mask
= data
;
824 case MSR_MTRRfix64K_00000
:
825 env
->mtrr_fixed
[ECX(env
) - MSR_MTRRfix64K_00000
] = data
;
827 case MSR_MTRRfix16K_80000
:
828 case MSR_MTRRfix16K_A0000
:
829 env
->mtrr_fixed
[ECX(env
) - MSR_MTRRfix16K_80000
+ 1] = data
;
831 case MSR_MTRRfix4K_C0000
:
832 case MSR_MTRRfix4K_C8000
:
833 case MSR_MTRRfix4K_D0000
:
834 case MSR_MTRRfix4K_D8000
:
835 case MSR_MTRRfix4K_E0000
:
836 case MSR_MTRRfix4K_E8000
:
837 case MSR_MTRRfix4K_F0000
:
838 case MSR_MTRRfix4K_F8000
:
839 env
->mtrr_fixed
[ECX(env
) - MSR_MTRRfix4K_C0000
+ 3] = data
;
841 case MSR_MTRRdefType
:
842 env
->mtrr_deftype
= data
;
848 /* Related to support known hypervisor interface */
849 /* if (g_hypervisor_iface)
850 g_hypervisor_iface->wrmsr_handler(cpu, msr, data);
852 printf("write msr %llx\n", RCX(cpu));*/
855 static void exec_wrmsr(struct CPUX86State
*env
, struct x86_decode
*decode
)
857 simulate_wrmsr(env_cpu(env
));
858 RIP(env
) += decode
->len
;
863 * 0 - bt, 1 - btc, 2 - bts, 3 - btr
865 static void do_bt(struct CPUX86State
*env
, struct x86_decode
*decode
, int flag
)
867 int32_t displacement
;
870 int mask
= (4 == decode
->operand_size
) ? 0x1f : 0xf;
872 VM_PANIC_ON(decode
->rex
.rex
);
874 fetch_operands(env
, decode
, 2, false, true, false);
875 index
= decode
->op
[1].val
& mask
;
877 if (decode
->op
[0].type
!= X86_VAR_REG
) {
878 if (4 == decode
->operand_size
) {
879 displacement
= ((int32_t) (decode
->op
[1].val
& 0xffffffe0)) / 32;
880 decode
->op
[0].ptr
+= 4 * displacement
;
881 } else if (2 == decode
->operand_size
) {
882 displacement
= ((int16_t) (decode
->op
[1].val
& 0xfff0)) / 16;
883 decode
->op
[0].ptr
+= 2 * displacement
;
885 VM_PANIC("bt 64bit\n");
888 decode
->op
[0].val
= read_val_ext(env
, decode
->op
[0].ptr
,
889 decode
->operand_size
);
890 cf
= (decode
->op
[0].val
>> index
) & 0x01;
897 decode
->op
[0].val
^= (1u << index
);
900 decode
->op
[0].val
|= (1u << index
);
903 decode
->op
[0].val
&= ~(1u << index
);
906 write_val_ext(env
, decode
->op
[0].ptr
, decode
->op
[0].val
,
907 decode
->operand_size
);
911 static void exec_bt(struct CPUX86State
*env
, struct x86_decode
*decode
)
913 do_bt(env
, decode
, 0);
914 RIP(env
) += decode
->len
;
917 static void exec_btc(struct CPUX86State
*env
, struct x86_decode
*decode
)
919 do_bt(env
, decode
, 1);
920 RIP(env
) += decode
->len
;
923 static void exec_btr(struct CPUX86State
*env
, struct x86_decode
*decode
)
925 do_bt(env
, decode
, 3);
926 RIP(env
) += decode
->len
;
929 static void exec_bts(struct CPUX86State
*env
, struct x86_decode
*decode
)
931 do_bt(env
, decode
, 2);
932 RIP(env
) += decode
->len
;
935 void exec_shl(struct CPUX86State
*env
, struct x86_decode
*decode
)
940 fetch_operands(env
, decode
, 2, true, true, false);
942 count
= decode
->op
[1].val
;
943 count
&= 0x1f; /* count is masked to 5 bits*/
948 switch (decode
->operand_size
) {
953 res
= (decode
->op
[0].val
<< count
);
954 cf
= (decode
->op
[0].val
>> (8 - count
)) & 0x1;
955 of
= cf
^ (res
>> 7);
958 write_val_ext(env
, decode
->op
[0].ptr
, res
, 1);
959 SET_FLAGS_OSZAPC_LOGIC8(env
, 0, 0, res
);
960 SET_FLAGS_OxxxxC(env
, of
, cf
);
969 res
= (decode
->op
[0].val
<< count
);
970 cf
= (decode
->op
[0].val
>> (16 - count
)) & 0x1;
971 of
= cf
^ (res
>> 15); /* of = cf ^ result15 */
974 write_val_ext(env
, decode
->op
[0].ptr
, res
, 2);
975 SET_FLAGS_OSZAPC_LOGIC16(env
, 0, 0, res
);
976 SET_FLAGS_OxxxxC(env
, of
, cf
);
981 uint32_t res
= decode
->op
[0].val
<< count
;
983 write_val_ext(env
, decode
->op
[0].ptr
, res
, 4);
984 SET_FLAGS_OSZAPC_LOGIC32(env
, 0, 0, res
);
985 cf
= (decode
->op
[0].val
>> (32 - count
)) & 0x1;
986 of
= cf
^ (res
>> 31); /* of = cf ^ result31 */
987 SET_FLAGS_OxxxxC(env
, of
, cf
);
995 /* lflags_to_rflags(env); */
996 RIP(env
) += decode
->len
;
999 void exec_movsx(CPUX86State
*env
, struct x86_decode
*decode
)
1002 int op_size
= decode
->operand_size
;
1004 fetch_operands(env
, decode
, 2, false, false, false);
1006 if (0xbe == decode
->opcode
[1]) {
1012 decode
->operand_size
= src_op_size
;
1013 calc_modrm_operand(env
, decode
, &decode
->op
[1]);
1014 decode
->op
[1].val
= sign(read_val_ext(env
, decode
->op
[1].ptr
, src_op_size
),
1017 write_val_ext(env
, decode
->op
[0].ptr
, decode
->op
[1].val
, op_size
);
1019 RIP(env
) += decode
->len
;
1022 void exec_ror(struct CPUX86State
*env
, struct x86_decode
*decode
)
1026 fetch_operands(env
, decode
, 2, true, true, false);
1027 count
= decode
->op
[1].val
;
1029 switch (decode
->operand_size
) {
1032 uint32_t bit6
, bit7
;
1035 if ((count
& 0x07) == 0) {
1037 bit6
= ((uint8_t)decode
->op
[0].val
>> 6) & 1;
1038 bit7
= ((uint8_t)decode
->op
[0].val
>> 7) & 1;
1039 SET_FLAGS_OxxxxC(env
, bit6
^ bit7
, bit7
);
1042 count
&= 0x7; /* use only bottom 3 bits */
1043 res
= ((uint8_t)decode
->op
[0].val
>> count
) |
1044 ((uint8_t)decode
->op
[0].val
<< (8 - count
));
1045 write_val_ext(env
, decode
->op
[0].ptr
, res
, 1);
1046 bit6
= (res
>> 6) & 1;
1047 bit7
= (res
>> 7) & 1;
1048 /* set eflags: ROR count affects the following flags: C, O */
1049 SET_FLAGS_OxxxxC(env
, bit6
^ bit7
, bit7
);
1055 uint32_t bit14
, bit15
;
1058 if ((count
& 0x0f) == 0) {
1060 bit14
= ((uint16_t)decode
->op
[0].val
>> 14) & 1;
1061 bit15
= ((uint16_t)decode
->op
[0].val
>> 15) & 1;
1062 /* of = result14 ^ result15 */
1063 SET_FLAGS_OxxxxC(env
, bit14
^ bit15
, bit15
);
1066 count
&= 0x0f; /* use only 4 LSB's */
1067 res
= ((uint16_t)decode
->op
[0].val
>> count
) |
1068 ((uint16_t)decode
->op
[0].val
<< (16 - count
));
1069 write_val_ext(env
, decode
->op
[0].ptr
, res
, 2);
1071 bit14
= (res
>> 14) & 1;
1072 bit15
= (res
>> 15) & 1;
1073 /* of = result14 ^ result15 */
1074 SET_FLAGS_OxxxxC(env
, bit14
^ bit15
, bit15
);
1080 uint32_t bit31
, bit30
;
1085 res
= ((uint32_t)decode
->op
[0].val
>> count
) |
1086 ((uint32_t)decode
->op
[0].val
<< (32 - count
));
1087 write_val_ext(env
, decode
->op
[0].ptr
, res
, 4);
1089 bit31
= (res
>> 31) & 1;
1090 bit30
= (res
>> 30) & 1;
1091 /* of = result30 ^ result31 */
1092 SET_FLAGS_OxxxxC(env
, bit30
^ bit31
, bit31
);
1097 RIP(env
) += decode
->len
;
1100 void exec_rol(struct CPUX86State
*env
, struct x86_decode
*decode
)
1104 fetch_operands(env
, decode
, 2, true, true, false);
1105 count
= decode
->op
[1].val
;
1107 switch (decode
->operand_size
) {
1110 uint32_t bit0
, bit7
;
1113 if ((count
& 0x07) == 0) {
1115 bit0
= ((uint8_t)decode
->op
[0].val
& 1);
1116 bit7
= ((uint8_t)decode
->op
[0].val
>> 7);
1117 SET_FLAGS_OxxxxC(env
, bit0
^ bit7
, bit0
);
1120 count
&= 0x7; /* use only lowest 3 bits */
1121 res
= ((uint8_t)decode
->op
[0].val
<< count
) |
1122 ((uint8_t)decode
->op
[0].val
>> (8 - count
));
1124 write_val_ext(env
, decode
->op
[0].ptr
, res
, 1);
1126 * ROL count affects the following flags: C, O
1130 SET_FLAGS_OxxxxC(env
, bit0
^ bit7
, bit0
);
1136 uint32_t bit0
, bit15
;
1139 if ((count
& 0x0f) == 0) {
1141 bit0
= ((uint16_t)decode
->op
[0].val
& 0x1);
1142 bit15
= ((uint16_t)decode
->op
[0].val
>> 15);
1143 /* of = cf ^ result15 */
1144 SET_FLAGS_OxxxxC(env
, bit0
^ bit15
, bit0
);
1147 count
&= 0x0f; /* only use bottom 4 bits */
1148 res
= ((uint16_t)decode
->op
[0].val
<< count
) |
1149 ((uint16_t)decode
->op
[0].val
>> (16 - count
));
1151 write_val_ext(env
, decode
->op
[0].ptr
, res
, 2);
1153 bit15
= (res
>> 15);
1154 /* of = cf ^ result15 */
1155 SET_FLAGS_OxxxxC(env
, bit0
^ bit15
, bit0
);
1161 uint32_t bit0
, bit31
;
1166 res
= ((uint32_t)decode
->op
[0].val
<< count
) |
1167 ((uint32_t)decode
->op
[0].val
>> (32 - count
));
1169 write_val_ext(env
, decode
->op
[0].ptr
, res
, 4);
1171 bit31
= (res
>> 31);
1172 /* of = cf ^ result31 */
1173 SET_FLAGS_OxxxxC(env
, bit0
^ bit31
, bit0
);
1178 RIP(env
) += decode
->len
;
1182 void exec_rcl(struct CPUX86State
*env
, struct x86_decode
*decode
)
1187 fetch_operands(env
, decode
, 2, true, true, false);
1188 count
= decode
->op
[1].val
& 0x1f;
1190 switch (decode
->operand_size
) {
1193 uint8_t op1_8
= decode
->op
[0].val
;
1201 res
= (op1_8
<< 1) | get_CF(env
);
1203 res
= (op1_8
<< count
) | (get_CF(env
) << (count
- 1)) |
1204 (op1_8
>> (9 - count
));
1207 write_val_ext(env
, decode
->op
[0].ptr
, res
, 1);
1209 cf
= (op1_8
>> (8 - count
)) & 0x01;
1210 of
= cf
^ (res
>> 7); /* of = cf ^ result7 */
1211 SET_FLAGS_OxxxxC(env
, of
, cf
);
1217 uint16_t op1_16
= decode
->op
[0].val
;
1225 res
= (op1_16
<< 1) | get_CF(env
);
1226 } else if (count
== 16) {
1227 res
= (get_CF(env
) << 15) | (op1_16
>> 1);
1228 } else { /* 2..15 */
1229 res
= (op1_16
<< count
) | (get_CF(env
) << (count
- 1)) |
1230 (op1_16
>> (17 - count
));
1233 write_val_ext(env
, decode
->op
[0].ptr
, res
, 2);
1235 cf
= (op1_16
>> (16 - count
)) & 0x1;
1236 of
= cf
^ (res
>> 15); /* of = cf ^ result15 */
1237 SET_FLAGS_OxxxxC(env
, of
, cf
);
1243 uint32_t op1_32
= decode
->op
[0].val
;
1250 res
= (op1_32
<< 1) | get_CF(env
);
1252 res
= (op1_32
<< count
) | (get_CF(env
) << (count
- 1)) |
1253 (op1_32
>> (33 - count
));
1256 write_val_ext(env
, decode
->op
[0].ptr
, res
, 4);
1258 cf
= (op1_32
>> (32 - count
)) & 0x1;
1259 of
= cf
^ (res
>> 31); /* of = cf ^ result31 */
1260 SET_FLAGS_OxxxxC(env
, of
, cf
);
1264 RIP(env
) += decode
->len
;
1267 void exec_rcr(struct CPUX86State
*env
, struct x86_decode
*decode
)
1272 fetch_operands(env
, decode
, 2, true, true, false);
1273 count
= decode
->op
[1].val
& 0x1f;
1275 switch (decode
->operand_size
) {
1278 uint8_t op1_8
= decode
->op
[0].val
;
1285 res
= (op1_8
>> count
) | (get_CF(env
) << (8 - count
)) |
1286 (op1_8
<< (9 - count
));
1288 write_val_ext(env
, decode
->op
[0].ptr
, res
, 1);
1290 cf
= (op1_8
>> (count
- 1)) & 0x1;
1291 of
= (((res
<< 1) ^ res
) >> 7) & 0x1; /* of = result6 ^ result7 */
1292 SET_FLAGS_OxxxxC(env
, of
, cf
);
1297 uint16_t op1_16
= decode
->op
[0].val
;
1304 res
= (op1_16
>> count
) | (get_CF(env
) << (16 - count
)) |
1305 (op1_16
<< (17 - count
));
1307 write_val_ext(env
, decode
->op
[0].ptr
, res
, 2);
1309 cf
= (op1_16
>> (count
- 1)) & 0x1;
1310 of
= ((uint16_t)((res
<< 1) ^ res
) >> 15) & 0x1; /* of = result15 ^
1312 SET_FLAGS_OxxxxC(env
, of
, cf
);
1318 uint32_t op1_32
= decode
->op
[0].val
;
1325 res
= (op1_32
>> 1) | (get_CF(env
) << 31);
1327 res
= (op1_32
>> count
) | (get_CF(env
) << (32 - count
)) |
1328 (op1_32
<< (33 - count
));
1331 write_val_ext(env
, decode
->op
[0].ptr
, res
, 4);
1333 cf
= (op1_32
>> (count
- 1)) & 0x1;
1334 of
= ((res
<< 1) ^ res
) >> 31; /* of = result30 ^ result31 */
1335 SET_FLAGS_OxxxxC(env
, of
, cf
);
1339 RIP(env
) += decode
->len
;
1342 static void exec_xchg(struct CPUX86State
*env
, struct x86_decode
*decode
)
1344 fetch_operands(env
, decode
, 2, true, true, false);
1346 write_val_ext(env
, decode
->op
[0].ptr
, decode
->op
[1].val
,
1347 decode
->operand_size
);
1348 write_val_ext(env
, decode
->op
[1].ptr
, decode
->op
[0].val
,
1349 decode
->operand_size
);
1351 RIP(env
) += decode
->len
;
1354 static void exec_xadd(struct CPUX86State
*env
, struct x86_decode
*decode
)
1356 EXEC_2OP_FLAGS_CMD(env
, decode
, +, SET_FLAGS_OSZAPC_ADD
, true);
1357 write_val_ext(env
, decode
->op
[1].ptr
, decode
->op
[0].val
,
1358 decode
->operand_size
);
1360 RIP(env
) += decode
->len
;
1363 static struct cmd_handler
{
1364 enum x86_decode_cmd cmd
;
1365 void (*handler
)(struct CPUX86State
*env
, struct x86_decode
*ins
);
1367 {X86_DECODE_CMD_INVL
, NULL
,},
1368 {X86_DECODE_CMD_MOV
, exec_mov
},
1369 {X86_DECODE_CMD_ADD
, exec_add
},
1370 {X86_DECODE_CMD_OR
, exec_or
},
1371 {X86_DECODE_CMD_ADC
, exec_adc
},
1372 {X86_DECODE_CMD_SBB
, exec_sbb
},
1373 {X86_DECODE_CMD_AND
, exec_and
},
1374 {X86_DECODE_CMD_SUB
, exec_sub
},
1375 {X86_DECODE_CMD_NEG
, exec_neg
},
1376 {X86_DECODE_CMD_XOR
, exec_xor
},
1377 {X86_DECODE_CMD_CMP
, exec_cmp
},
1378 {X86_DECODE_CMD_INC
, exec_inc
},
1379 {X86_DECODE_CMD_DEC
, exec_dec
},
1380 {X86_DECODE_CMD_TST
, exec_tst
},
1381 {X86_DECODE_CMD_NOT
, exec_not
},
1382 {X86_DECODE_CMD_MOVZX
, exec_movzx
},
1383 {X86_DECODE_CMD_OUT
, exec_out
},
1384 {X86_DECODE_CMD_IN
, exec_in
},
1385 {X86_DECODE_CMD_INS
, exec_ins
},
1386 {X86_DECODE_CMD_OUTS
, exec_outs
},
1387 {X86_DECODE_CMD_RDMSR
, exec_rdmsr
},
1388 {X86_DECODE_CMD_WRMSR
, exec_wrmsr
},
1389 {X86_DECODE_CMD_BT
, exec_bt
},
1390 {X86_DECODE_CMD_BTR
, exec_btr
},
1391 {X86_DECODE_CMD_BTC
, exec_btc
},
1392 {X86_DECODE_CMD_BTS
, exec_bts
},
1393 {X86_DECODE_CMD_SHL
, exec_shl
},
1394 {X86_DECODE_CMD_ROL
, exec_rol
},
1395 {X86_DECODE_CMD_ROR
, exec_ror
},
1396 {X86_DECODE_CMD_RCR
, exec_rcr
},
1397 {X86_DECODE_CMD_RCL
, exec_rcl
},
1398 /*{X86_DECODE_CMD_CPUID, exec_cpuid},*/
1399 {X86_DECODE_CMD_MOVS
, exec_movs
},
1400 {X86_DECODE_CMD_CMPS
, exec_cmps
},
1401 {X86_DECODE_CMD_STOS
, exec_stos
},
1402 {X86_DECODE_CMD_SCAS
, exec_scas
},
1403 {X86_DECODE_CMD_LODS
, exec_lods
},
1404 {X86_DECODE_CMD_MOVSX
, exec_movsx
},
1405 {X86_DECODE_CMD_XCHG
, exec_xchg
},
1406 {X86_DECODE_CMD_XADD
, exec_xadd
},
1409 static struct cmd_handler _cmd_handler
[X86_DECODE_CMD_LAST
];
1411 static void init_cmd_handler()
1414 for (i
= 0; i
< ARRAY_SIZE(handlers
); i
++) {
1415 _cmd_handler
[handlers
[i
].cmd
] = handlers
[i
];
1419 void load_regs(struct CPUState
*cpu
)
1421 X86CPU
*x86_cpu
= X86_CPU(cpu
);
1422 CPUX86State
*env
= &x86_cpu
->env
;
1425 RRX(env
, R_EAX
) = rreg(cpu
->hvf_fd
, HV_X86_RAX
);
1426 RRX(env
, R_EBX
) = rreg(cpu
->hvf_fd
, HV_X86_RBX
);
1427 RRX(env
, R_ECX
) = rreg(cpu
->hvf_fd
, HV_X86_RCX
);
1428 RRX(env
, R_EDX
) = rreg(cpu
->hvf_fd
, HV_X86_RDX
);
1429 RRX(env
, R_ESI
) = rreg(cpu
->hvf_fd
, HV_X86_RSI
);
1430 RRX(env
, R_EDI
) = rreg(cpu
->hvf_fd
, HV_X86_RDI
);
1431 RRX(env
, R_ESP
) = rreg(cpu
->hvf_fd
, HV_X86_RSP
);
1432 RRX(env
, R_EBP
) = rreg(cpu
->hvf_fd
, HV_X86_RBP
);
1433 for (i
= 8; i
< 16; i
++) {
1434 RRX(env
, i
) = rreg(cpu
->hvf_fd
, HV_X86_RAX
+ i
);
1437 RFLAGS(env
) = rreg(cpu
->hvf_fd
, HV_X86_RFLAGS
);
1438 rflags_to_lflags(env
);
1439 RIP(env
) = rreg(cpu
->hvf_fd
, HV_X86_RIP
);
1442 void store_regs(struct CPUState
*cpu
)
1444 X86CPU
*x86_cpu
= X86_CPU(cpu
);
1445 CPUX86State
*env
= &x86_cpu
->env
;
1448 wreg(cpu
->hvf_fd
, HV_X86_RAX
, RAX(env
));
1449 wreg(cpu
->hvf_fd
, HV_X86_RBX
, RBX(env
));
1450 wreg(cpu
->hvf_fd
, HV_X86_RCX
, RCX(env
));
1451 wreg(cpu
->hvf_fd
, HV_X86_RDX
, RDX(env
));
1452 wreg(cpu
->hvf_fd
, HV_X86_RSI
, RSI(env
));
1453 wreg(cpu
->hvf_fd
, HV_X86_RDI
, RDI(env
));
1454 wreg(cpu
->hvf_fd
, HV_X86_RBP
, RBP(env
));
1455 wreg(cpu
->hvf_fd
, HV_X86_RSP
, RSP(env
));
1456 for (i
= 8; i
< 16; i
++) {
1457 wreg(cpu
->hvf_fd
, HV_X86_RAX
+ i
, RRX(env
, i
));
1460 lflags_to_rflags(env
);
1461 wreg(cpu
->hvf_fd
, HV_X86_RFLAGS
, RFLAGS(env
));
1462 macvm_set_rip(cpu
, RIP(env
));
1465 bool exec_instruction(struct CPUX86State
*env
, struct x86_decode
*ins
)
1467 /*if (hvf_vcpu_id(cpu))
1468 printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), RIP(cpu),
1469 decode_cmd_to_string(ins->cmd));*/
1471 if (!_cmd_handler
[ins
->cmd
].handler
) {
1472 printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(env
),
1473 ins
->cmd
, ins
->opcode
[0],
1474 ins
->opcode_len
> 1 ? ins
->opcode
[1] : 0);
1475 RIP(env
) += ins
->len
;
1479 _cmd_handler
[ins
->cmd
].handler(env
, ins
);