target/i386/hvf/x86_task.c

   1 // This software is licensed under the terms of the GNU General Public
   2 // License version 2, as published by the Free Software Foundation, and
   3 // may be copied, distributed, and modified under those terms.
   4 //
   5 // This program is distributed in the hope that it will be useful,
   6 // but WITHOUT ANY WARRANTY; without even the implied warranty of
   7 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8 // GNU General Public License for more details.
   9 #include "qemu/osdep.h"
  10 #include "panic.h"
  11 #include "qemu-common.h"
  12 #include "qemu/error-report.h"
  13
  14 #include "sysemu/hvf.h"
  15 #include "hvf-i386.h"
  16 #include "vmcs.h"
  17 #include "vmx.h"
  18 #include "x86.h"
  19 #include "x86_descr.h"
  20 #include "x86_mmu.h"
  21 #include "x86_decode.h"
  22 #include "x86_emu.h"
  23 #include "x86_task.h"
  24 #include "x86hvf.h"
  25
  26 #include <Hypervisor/hv.h>
  27 #include <Hypervisor/hv_vmx.h>
  28
  29 #include "exec/address-spaces.h"
  30 #include "exec/exec-all.h"
  31 #include "exec/ioport.h"
  32 #include "hw/i386/apic_internal.h"
  33 #include "hw/boards.h"
  34 #include "qemu/main-loop.h"
  35 #include "strings.h"
  36 #include "sysemu/accel.h"
  37 #include "sysemu/sysemu.h"
  38 #include "target/i386/cpu.h"
  39
  40 // TODO: taskswitch handling
  41 static void save_state_to_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
  42 {
  43     X86CPU *x86_cpu = X86_CPU(cpu);
  44     CPUX86State *env = &x86_cpu->env;
  45
  46     /* CR3 and ldt selector are not saved intentionally */
  47     tss->eip = EIP(env);
  48     tss->eflags = EFLAGS(env);
  49     tss->eax = EAX(env);
  50     tss->ecx = ECX(env);
  51     tss->edx = EDX(env);
  52     tss->ebx = EBX(env);
  53     tss->esp = ESP(env);
  54     tss->ebp = EBP(env);
  55     tss->esi = ESI(env);
  56     tss->edi = EDI(env);
  57
  58     tss->es = vmx_read_segment_selector(cpu, R_ES).sel;
  59     tss->cs = vmx_read_segment_selector(cpu, R_CS).sel;
  60     tss->ss = vmx_read_segment_selector(cpu, R_SS).sel;
  61     tss->ds = vmx_read_segment_selector(cpu, R_DS).sel;
  62     tss->fs = vmx_read_segment_selector(cpu, R_FS).sel;
  63     tss->gs = vmx_read_segment_selector(cpu, R_GS).sel;
  64 }
  65
  66 static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
  67 {
  68     X86CPU *x86_cpu = X86_CPU(cpu);
  69     CPUX86State *env = &x86_cpu->env;
  70
  71     wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, tss->cr3);
  72
  73     RIP(env) = tss->eip;
  74     EFLAGS(env) = tss->eflags | 2;
  75
  76     /* General purpose registers */
  77     RAX(env) = tss->eax;
  78     RCX(env) = tss->ecx;
  79     RDX(env) = tss->edx;
  80     RBX(env) = tss->ebx;
  81     RSP(env) = tss->esp;
  82     RBP(env) = tss->ebp;
  83     RSI(env) = tss->esi;
  84     RDI(env) = tss->edi;
  85
  86     vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}}, R_LDTR);
  87     vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}}, R_ES);
  88     vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}}, R_CS);
  89     vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}}, R_SS);
  90     vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, R_DS);
  91     vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, R_FS);
  92     vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, R_GS);
  93 }
  94
  95 static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segment_selector old_tss_sel,
  96                           uint64_t old_tss_base, struct x86_segment_descriptor *new_desc)
  97 {
  98     struct x86_tss_segment32 tss_seg;
  99     uint32_t new_tss_base = x86_segment_base(new_desc);
 100     uint32_t eip_offset = offsetof(struct x86_tss_segment32, eip);
 101     uint32_t ldt_sel_offset = offsetof(struct x86_tss_segment32, ldt);
 102
 103     vmx_read_mem(cpu, &tss_seg, old_tss_base, sizeof(tss_seg));
 104     save_state_to_tss32(cpu, &tss_seg);
 105
 106     vmx_write_mem(cpu, old_tss_base + eip_offset, &tss_seg.eip, ldt_sel_offset - eip_offset);
 107     vmx_read_mem(cpu, &tss_seg, new_tss_base, sizeof(tss_seg));
 108
 109     if (old_tss_sel.sel != 0xffff) {
 110         tss_seg.prev_tss = old_tss_sel.sel;
 111
 112         vmx_write_mem(cpu, new_tss_base, &tss_seg.prev_tss, sizeof(tss_seg.prev_tss));
 113     }
 114     load_state_from_tss32(cpu, &tss_seg);
 115     return 0;
 116 }
 117
 118 void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type)
 119 {
 120     uint64_t rip = rreg(cpu->hvf_fd, HV_X86_RIP);
 121     if (!gate_valid || (gate_type != VMCS_INTR_T_HWEXCEPTION &&
 122                         gate_type != VMCS_INTR_T_HWINTR &&
 123                         gate_type != VMCS_INTR_T_NMI)) {
 124         int ins_len = rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
 125         macvm_set_rip(cpu, rip + ins_len);
 126         return;
 127     }
 128
 129     load_regs(cpu);
 130
 131     struct x86_segment_descriptor curr_tss_desc, next_tss_desc;
 132     int ret;
 133     x68_segment_selector old_tss_sel = vmx_read_segment_selector(cpu, R_TR);
 134     uint64_t old_tss_base = vmx_read_segment_base(cpu, R_TR);
 135     uint32_t desc_limit;
 136     struct x86_call_gate task_gate_desc;
 137     struct vmx_segment vmx_seg;
 138
 139     X86CPU *x86_cpu = X86_CPU(cpu);
 140     CPUX86State *env = &x86_cpu->env;
 141
 142     x86_read_segment_descriptor(cpu, &next_tss_desc, tss_sel);
 143     x86_read_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel);
 144
 145     if (reason == TSR_IDT_GATE && gate_valid) {
 146         int dpl;
 147
 148         ret = x86_read_call_gate(cpu, &task_gate_desc, gate);
 149
 150         dpl = task_gate_desc.dpl;
 151         x68_segment_selector cs = vmx_read_segment_selector(cpu, R_CS);
 152         if (tss_sel.rpl > dpl || cs.rpl > dpl)
 153             ;//DPRINTF("emulate_gp");
 154     }
 155
 156     desc_limit = x86_segment_limit(&next_tss_desc);
 157     if (!next_tss_desc.p || ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || desc_limit < 0x2b)) {
 158         VM_PANIC("emulate_ts");
 159     }
 160
 161     if (reason == TSR_IRET || reason == TSR_JMP) {
 162         curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
 163         x86_write_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel);
 164     }
 165
 166     if (reason == TSR_IRET)
 167         EFLAGS(env) &= ~RFLAGS_NT;
 168
 169     if (reason != TSR_CALL && reason != TSR_IDT_GATE)
 170         old_tss_sel.sel = 0xffff;
 171
 172     if (reason != TSR_IRET) {
 173         next_tss_desc.type |= (1 << 1); /* set busy flag */
 174         x86_write_segment_descriptor(cpu, &next_tss_desc, tss_sel);
 175     }
 176
 177     if (next_tss_desc.type & 8)
 178         ret = task_switch_32(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
 179     else
 180         //ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
 181         VM_PANIC("task_switch_16");
 182
 183     macvm_set_cr0(cpu->hvf_fd, rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS);
 184     x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg);
 185     vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR);
 186
 187     store_regs(cpu);
 188
 189     hv_vcpu_invalidate_tlb(cpu->hvf_fd);
 190     hv_vcpu_flush(cpu->hvf_fd);
 191 }