4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include "standard-headers/asm-x86/kvm_para.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/hw_accel.h"
26 #include "sysemu/kvm_int.h"
27 #include "sysemu/reset.h"
28 #include "sysemu/runstate.h"
31 #include "hyperv-proto.h"
33 #include "exec/gdbstub.h"
34 #include "qemu/host-utils.h"
35 #include "qemu/main-loop.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #include "hw/i386/pc.h"
39 #include "hw/i386/apic.h"
40 #include "hw/i386/apic_internal.h"
41 #include "hw/i386/apic-msidef.h"
42 #include "hw/i386/intel_iommu.h"
43 #include "hw/i386/x86-iommu.h"
44 #include "hw/i386/e820_memory_layout.h"
46 #include "hw/pci/pci.h"
47 #include "hw/pci/msi.h"
48 #include "hw/pci/msix.h"
49 #include "migration/blocker.h"
50 #include "exec/memattrs.h"
56 #define DPRINTF(fmt, ...) \
57 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
59 #define DPRINTF(fmt, ...) \
63 #define MSR_KVM_WALL_CLOCK 0x11
64 #define MSR_KVM_SYSTEM_TIME 0x12
66 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
67 * 255 kvm_msr_entry structs */
68 #define MSR_BUF_SIZE 4096
70 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
71 KVM_CAP_INFO(SET_TSS_ADDR
),
72 KVM_CAP_INFO(EXT_CPUID
),
73 KVM_CAP_INFO(MP_STATE
),
77 static bool has_msr_star
;
78 static bool has_msr_hsave_pa
;
79 static bool has_msr_tsc_aux
;
80 static bool has_msr_tsc_adjust
;
81 static bool has_msr_tsc_deadline
;
82 static bool has_msr_feature_control
;
83 static bool has_msr_misc_enable
;
84 static bool has_msr_smbase
;
85 static bool has_msr_bndcfgs
;
86 static int lm_capable_kernel
;
87 static bool has_msr_hv_hypercall
;
88 static bool has_msr_hv_crash
;
89 static bool has_msr_hv_reset
;
90 static bool has_msr_hv_vpindex
;
91 static bool hv_vpindex_settable
;
92 static bool has_msr_hv_runtime
;
93 static bool has_msr_hv_synic
;
94 static bool has_msr_hv_stimer
;
95 static bool has_msr_hv_frequencies
;
96 static bool has_msr_hv_reenlightenment
;
97 static bool has_msr_xss
;
98 static bool has_msr_umwait
;
99 static bool has_msr_spec_ctrl
;
100 static bool has_msr_tsx_ctrl
;
101 static bool has_msr_virt_ssbd
;
102 static bool has_msr_smi_count
;
103 static bool has_msr_arch_capabs
;
104 static bool has_msr_core_capabs
;
105 static bool has_msr_vmx_vmfunc
;
107 static uint32_t has_architectural_pmu_version
;
108 static uint32_t num_architectural_pmu_gp_counters
;
109 static uint32_t num_architectural_pmu_fixed_counters
;
111 static int has_xsave
;
113 static int has_pit_state2
;
114 static int has_exception_payload
;
116 static bool has_msr_mcg_ext_ctl
;
118 static struct kvm_cpuid2
*cpuid_cache
;
119 static struct kvm_msr_list
*kvm_feature_msrs
;
121 int kvm_has_pit_state2(void)
123 return has_pit_state2
;
126 bool kvm_has_smm(void)
128 return kvm_check_extension(kvm_state
, KVM_CAP_X86_SMM
);
131 bool kvm_has_adjust_clock_stable(void)
133 int ret
= kvm_check_extension(kvm_state
, KVM_CAP_ADJUST_CLOCK
);
135 return (ret
== KVM_CLOCK_TSC_STABLE
);
138 bool kvm_has_exception_payload(void)
140 return has_exception_payload
;
143 bool kvm_allows_irq0_override(void)
145 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
148 static bool kvm_x2apic_api_set_flags(uint64_t flags
)
150 KVMState
*s
= KVM_STATE(current_machine
->accelerator
);
152 return !kvm_vm_enable_cap(s
, KVM_CAP_X2APIC_API
, 0, flags
);
155 #define MEMORIZE(fn, _result) \
157 static bool _memorized; \
166 static bool has_x2apic_api
;
168 bool kvm_has_x2apic_api(void)
170 return has_x2apic_api
;
173 bool kvm_enable_x2apic(void)
176 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS
|
177 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK
),
181 bool kvm_hv_vpindex_settable(void)
183 return hv_vpindex_settable
;
186 static int kvm_get_tsc(CPUState
*cs
)
188 X86CPU
*cpu
= X86_CPU(cs
);
189 CPUX86State
*env
= &cpu
->env
;
191 struct kvm_msrs info
;
192 struct kvm_msr_entry entries
[1];
196 if (env
->tsc_valid
) {
200 memset(&msr_data
, 0, sizeof(msr_data
));
201 msr_data
.info
.nmsrs
= 1;
202 msr_data
.entries
[0].index
= MSR_IA32_TSC
;
203 env
->tsc_valid
= !runstate_is_running();
205 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, &msr_data
);
211 env
->tsc
= msr_data
.entries
[0].data
;
215 static inline void do_kvm_synchronize_tsc(CPUState
*cpu
, run_on_cpu_data arg
)
220 void kvm_synchronize_all_tsc(void)
226 run_on_cpu(cpu
, do_kvm_synchronize_tsc
, RUN_ON_CPU_NULL
);
231 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
233 struct kvm_cpuid2
*cpuid
;
236 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
237 cpuid
= g_malloc0(size
);
239 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
240 if (r
== 0 && cpuid
->nent
>= max
) {
248 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
256 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
259 static struct kvm_cpuid2
*get_supported_cpuid(KVMState
*s
)
261 struct kvm_cpuid2
*cpuid
;
264 if (cpuid_cache
!= NULL
) {
267 while ((cpuid
= try_get_cpuid(s
, max
)) == NULL
) {
274 static const struct kvm_para_features
{
277 } para_features
[] = {
278 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
279 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
280 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
281 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
284 static int get_para_features(KVMState
*s
)
288 for (i
= 0; i
< ARRAY_SIZE(para_features
); i
++) {
289 if (kvm_check_extension(s
, para_features
[i
].cap
)) {
290 features
|= (1 << para_features
[i
].feature
);
297 static bool host_tsx_blacklisted(void)
299 int family
, model
, stepping
;\
300 char vendor
[CPUID_VENDOR_SZ
+ 1];
302 host_vendor_fms(vendor
, &family
, &model
, &stepping
);
304 /* Check if we are running on a Haswell host known to have broken TSX */
305 return !strcmp(vendor
, CPUID_VENDOR_INTEL
) &&
307 ((model
== 63 && stepping
< 4) ||
308 model
== 60 || model
== 69 || model
== 70);
311 /* Returns the value for a specific register on the cpuid entry
313 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2
*entry
, int reg
)
333 /* Find matching entry for function/index on kvm_cpuid2 struct
335 static struct kvm_cpuid_entry2
*cpuid_find_entry(struct kvm_cpuid2
*cpuid
,
340 for (i
= 0; i
< cpuid
->nent
; ++i
) {
341 if (cpuid
->entries
[i
].function
== function
&&
342 cpuid
->entries
[i
].index
== index
) {
343 return &cpuid
->entries
[i
];
350 uint32_t kvm_arch_get_supported_cpuid(KVMState
*s
, uint32_t function
,
351 uint32_t index
, int reg
)
353 struct kvm_cpuid2
*cpuid
;
355 uint32_t cpuid_1_edx
;
358 cpuid
= get_supported_cpuid(s
);
360 struct kvm_cpuid_entry2
*entry
= cpuid_find_entry(cpuid
, function
, index
);
363 ret
= cpuid_entry_get_reg(entry
, reg
);
366 /* Fixups for the data returned by KVM, below */
368 if (function
== 1 && reg
== R_EDX
) {
369 /* KVM before 2.6.30 misreports the following features */
370 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
371 } else if (function
== 1 && reg
== R_ECX
) {
372 /* We can set the hypervisor flag, even if KVM does not return it on
373 * GET_SUPPORTED_CPUID
375 ret
|= CPUID_EXT_HYPERVISOR
;
376 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
377 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
378 * and the irqchip is in the kernel.
380 if (kvm_irqchip_in_kernel() &&
381 kvm_check_extension(s
, KVM_CAP_TSC_DEADLINE_TIMER
)) {
382 ret
|= CPUID_EXT_TSC_DEADLINE_TIMER
;
385 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
386 * without the in-kernel irqchip
388 if (!kvm_irqchip_in_kernel()) {
389 ret
&= ~CPUID_EXT_X2APIC
;
393 int disable_exits
= kvm_check_extension(s
,
394 KVM_CAP_X86_DISABLE_EXITS
);
396 if (disable_exits
& KVM_X86_DISABLE_EXITS_MWAIT
) {
397 ret
|= CPUID_EXT_MONITOR
;
400 } else if (function
== 6 && reg
== R_EAX
) {
401 ret
|= CPUID_6_EAX_ARAT
; /* safe to allow because of emulated APIC */
402 } else if (function
== 7 && index
== 0 && reg
== R_EBX
) {
403 if (host_tsx_blacklisted()) {
404 ret
&= ~(CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_HLE
);
406 } else if (function
== 7 && index
== 0 && reg
== R_ECX
) {
408 ret
|= CPUID_7_0_ECX_WAITPKG
;
410 ret
&= ~CPUID_7_0_ECX_WAITPKG
;
412 } else if (function
== 7 && index
== 0 && reg
== R_EDX
) {
414 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
415 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
416 * returned by KVM_GET_MSR_INDEX_LIST.
418 if (!has_msr_arch_capabs
) {
419 ret
&= ~CPUID_7_0_EDX_ARCH_CAPABILITIES
;
421 } else if (function
== 0x80000001 && reg
== R_ECX
) {
423 * It's safe to enable TOPOEXT even if it's not returned by
424 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
425 * us to keep CPU models including TOPOEXT runnable on older kernels.
427 ret
|= CPUID_EXT3_TOPOEXT
;
428 } else if (function
== 0x80000001 && reg
== R_EDX
) {
429 /* On Intel, kvm returns cpuid according to the Intel spec,
430 * so add missing bits according to the AMD spec:
432 cpuid_1_edx
= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
433 ret
|= cpuid_1_edx
& CPUID_EXT2_AMD_ALIASES
;
434 } else if (function
== KVM_CPUID_FEATURES
&& reg
== R_EAX
) {
435 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
436 * be enabled without the in-kernel irqchip
438 if (!kvm_irqchip_in_kernel()) {
439 ret
&= ~(1U << KVM_FEATURE_PV_UNHALT
);
441 } else if (function
== KVM_CPUID_FEATURES
&& reg
== R_EDX
) {
442 ret
|= 1U << KVM_HINTS_REALTIME
;
446 /* fallback for older kernels */
447 if ((function
== KVM_CPUID_FEATURES
) && !found
) {
448 ret
= get_para_features(s
);
454 uint64_t kvm_arch_get_supported_msr_feature(KVMState
*s
, uint32_t index
)
457 struct kvm_msrs info
;
458 struct kvm_msr_entry entries
[1];
461 uint32_t ret
, can_be_one
, must_be_one
;
463 if (kvm_feature_msrs
== NULL
) { /* Host doesn't support feature MSRs */
467 /* Check if requested MSR is supported feature MSR */
469 for (i
= 0; i
< kvm_feature_msrs
->nmsrs
; i
++)
470 if (kvm_feature_msrs
->indices
[i
] == index
) {
473 if (i
== kvm_feature_msrs
->nmsrs
) {
474 return 0; /* if the feature MSR is not supported, simply return 0 */
477 msr_data
.info
.nmsrs
= 1;
478 msr_data
.entries
[0].index
= index
;
480 ret
= kvm_ioctl(s
, KVM_GET_MSRS
, &msr_data
);
482 error_report("KVM get MSR (index=0x%x) feature failed, %s",
483 index
, strerror(-ret
));
487 value
= msr_data
.entries
[0].data
;
489 case MSR_IA32_VMX_PROCBASED_CTLS2
:
490 /* KVM forgot to add these bits for some time, do this ourselves. */
491 if (kvm_arch_get_supported_cpuid(s
, 0xD, 1, R_ECX
) & CPUID_XSAVE_XSAVES
) {
492 value
|= (uint64_t)VMX_SECONDARY_EXEC_XSAVES
<< 32;
494 if (kvm_arch_get_supported_cpuid(s
, 1, 0, R_ECX
) & CPUID_EXT_RDRAND
) {
495 value
|= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING
<< 32;
497 if (kvm_arch_get_supported_cpuid(s
, 7, 0, R_EBX
) & CPUID_7_0_EBX_INVPCID
) {
498 value
|= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID
<< 32;
500 if (kvm_arch_get_supported_cpuid(s
, 7, 0, R_EBX
) & CPUID_7_0_EBX_RDSEED
) {
501 value
|= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING
<< 32;
503 if (kvm_arch_get_supported_cpuid(s
, 0x80000001, 0, R_EDX
) & CPUID_EXT2_RDTSCP
) {
504 value
|= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP
<< 32;
507 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
508 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
509 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
510 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
512 * Return true for bits that can be one, but do not have to be one.
513 * The SDM tells us which bits could have a "must be one" setting,
514 * so we can do the opposite transformation in make_vmx_msr_value.
516 must_be_one
= (uint32_t)value
;
517 can_be_one
= (uint32_t)(value
>> 32);
518 return can_be_one
& ~must_be_one
;
526 typedef struct HWPoisonPage
{
528 QLIST_ENTRY(HWPoisonPage
) list
;
531 static QLIST_HEAD(, HWPoisonPage
) hwpoison_page_list
=
532 QLIST_HEAD_INITIALIZER(hwpoison_page_list
);
534 static void kvm_unpoison_all(void *param
)
536 HWPoisonPage
*page
, *next_page
;
538 QLIST_FOREACH_SAFE(page
, &hwpoison_page_list
, list
, next_page
) {
539 QLIST_REMOVE(page
, list
);
540 qemu_ram_remap(page
->ram_addr
, TARGET_PAGE_SIZE
);
545 static void kvm_hwpoison_page_add(ram_addr_t ram_addr
)
549 QLIST_FOREACH(page
, &hwpoison_page_list
, list
) {
550 if (page
->ram_addr
== ram_addr
) {
554 page
= g_new(HWPoisonPage
, 1);
555 page
->ram_addr
= ram_addr
;
556 QLIST_INSERT_HEAD(&hwpoison_page_list
, page
, list
);
559 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
564 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
567 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
572 static void kvm_mce_inject(X86CPU
*cpu
, hwaddr paddr
, int code
)
574 CPUState
*cs
= CPU(cpu
);
575 CPUX86State
*env
= &cpu
->env
;
576 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
577 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
578 uint64_t mcg_status
= MCG_STATUS_MCIP
;
581 if (code
== BUS_MCEERR_AR
) {
582 status
|= MCI_STATUS_AR
| 0x134;
583 mcg_status
|= MCG_STATUS_EIPV
;
586 mcg_status
|= MCG_STATUS_RIPV
;
589 flags
= cpu_x86_support_mca_broadcast(env
) ? MCE_INJECT_BROADCAST
: 0;
590 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
591 * guest kernel back into env->mcg_ext_ctl.
593 cpu_synchronize_state(cs
);
594 if (env
->mcg_ext_ctl
& MCG_EXT_CTL_LMCE_EN
) {
595 mcg_status
|= MCG_STATUS_LMCE
;
599 cpu_x86_inject_mce(NULL
, cpu
, 9, status
, mcg_status
, paddr
,
600 (MCM_ADDR_PHYS
<< 6) | 0xc, flags
);
603 static void hardware_memory_error(void *host_addr
)
605 error_report("QEMU got Hardware memory error at addr %p", host_addr
);
609 void kvm_arch_on_sigbus_vcpu(CPUState
*c
, int code
, void *addr
)
611 X86CPU
*cpu
= X86_CPU(c
);
612 CPUX86State
*env
= &cpu
->env
;
616 /* If we get an action required MCE, it has been injected by KVM
617 * while the VM was running. An action optional MCE instead should
618 * be coming from the main thread, which qemu_init_sigbus identifies
619 * as the "early kill" thread.
621 assert(code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
);
623 if ((env
->mcg_cap
& MCG_SER_P
) && addr
) {
624 ram_addr
= qemu_ram_addr_from_host(addr
);
625 if (ram_addr
!= RAM_ADDR_INVALID
&&
626 kvm_physical_memory_addr_from_host(c
->kvm_state
, addr
, &paddr
)) {
627 kvm_hwpoison_page_add(ram_addr
);
628 kvm_mce_inject(cpu
, paddr
, code
);
631 * Use different logging severity based on error type.
632 * If there is additional MCE reporting on the hypervisor, QEMU VA
633 * could be another source to identify the PA and MCE details.
635 if (code
== BUS_MCEERR_AR
) {
636 error_report("Guest MCE Memory Error at QEMU addr %p and "
637 "GUEST addr 0x%" HWADDR_PRIx
" of type %s injected",
638 addr
, paddr
, "BUS_MCEERR_AR");
640 warn_report("Guest MCE Memory Error at QEMU addr %p and "
641 "GUEST addr 0x%" HWADDR_PRIx
" of type %s injected",
642 addr
, paddr
, "BUS_MCEERR_AO");
648 if (code
== BUS_MCEERR_AO
) {
649 warn_report("Hardware memory error at addr %p of type %s "
650 "for memory used by QEMU itself instead of guest system!",
651 addr
, "BUS_MCEERR_AO");
655 if (code
== BUS_MCEERR_AR
) {
656 hardware_memory_error(addr
);
659 /* Hope we are lucky for AO MCE */
662 static void kvm_reset_exception(CPUX86State
*env
)
664 env
->exception_nr
= -1;
665 env
->exception_pending
= 0;
666 env
->exception_injected
= 0;
667 env
->exception_has_payload
= false;
668 env
->exception_payload
= 0;
671 static void kvm_queue_exception(CPUX86State
*env
,
672 int32_t exception_nr
,
673 uint8_t exception_has_payload
,
674 uint64_t exception_payload
)
676 assert(env
->exception_nr
== -1);
677 assert(!env
->exception_pending
);
678 assert(!env
->exception_injected
);
679 assert(!env
->exception_has_payload
);
681 env
->exception_nr
= exception_nr
;
683 if (has_exception_payload
) {
684 env
->exception_pending
= 1;
686 env
->exception_has_payload
= exception_has_payload
;
687 env
->exception_payload
= exception_payload
;
689 env
->exception_injected
= 1;
691 if (exception_nr
== EXCP01_DB
) {
692 assert(exception_has_payload
);
693 env
->dr
[6] = exception_payload
;
694 } else if (exception_nr
== EXCP0E_PAGE
) {
695 assert(exception_has_payload
);
696 env
->cr
[2] = exception_payload
;
698 assert(!exception_has_payload
);
703 static int kvm_inject_mce_oldstyle(X86CPU
*cpu
)
705 CPUX86State
*env
= &cpu
->env
;
707 if (!kvm_has_vcpu_events() && env
->exception_nr
== EXCP12_MCHK
) {
708 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
709 struct kvm_x86_mce mce
;
711 kvm_reset_exception(env
);
714 * There must be at least one bank in use if an MCE is pending.
715 * Find it and use its values for the event injection.
717 for (bank
= 0; bank
< bank_num
; bank
++) {
718 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
722 assert(bank
< bank_num
);
725 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
726 mce
.mcg_status
= env
->mcg_status
;
727 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
728 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
730 return kvm_vcpu_ioctl(CPU(cpu
), KVM_X86_SET_MCE
, &mce
);
735 static void cpu_update_state(void *opaque
, int running
, RunState state
)
737 CPUX86State
*env
= opaque
;
740 env
->tsc_valid
= false;
744 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
746 X86CPU
*cpu
= X86_CPU(cs
);
750 #ifndef KVM_CPUID_SIGNATURE_NEXT
751 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
754 static bool hyperv_enabled(X86CPU
*cpu
)
756 CPUState
*cs
= CPU(cpu
);
757 return kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV
) > 0 &&
758 ((cpu
->hyperv_spinlock_attempts
!= HYPERV_SPINLOCK_NEVER_RETRY
) ||
759 cpu
->hyperv_features
|| cpu
->hyperv_passthrough
);
762 static int kvm_arch_set_tsc_khz(CPUState
*cs
)
764 X86CPU
*cpu
= X86_CPU(cs
);
765 CPUX86State
*env
= &cpu
->env
;
772 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_TSC_CONTROL
) ?
773 kvm_vcpu_ioctl(cs
, KVM_SET_TSC_KHZ
, env
->tsc_khz
) :
776 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
777 * TSC frequency doesn't match the one we want.
779 int cur_freq
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
780 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
782 if (cur_freq
<= 0 || cur_freq
!= env
->tsc_khz
) {
783 warn_report("TSC frequency mismatch between "
784 "VM (%" PRId64
" kHz) and host (%d kHz), "
785 "and TSC scaling unavailable",
786 env
->tsc_khz
, cur_freq
);
794 static bool tsc_is_stable_and_known(CPUX86State
*env
)
799 return (env
->features
[FEAT_8000_0007_EDX
] & CPUID_APM_INVTSC
)
800 || env
->user_tsc_khz
;
809 uint64_t dependencies
;
810 } kvm_hyperv_properties
[] = {
811 [HYPERV_FEAT_RELAXED
] = {
812 .desc
= "relaxed timing (hv-relaxed)",
814 {.fw
= FEAT_HYPERV_EAX
,
815 .bits
= HV_HYPERCALL_AVAILABLE
},
816 {.fw
= FEAT_HV_RECOMM_EAX
,
817 .bits
= HV_RELAXED_TIMING_RECOMMENDED
}
820 [HYPERV_FEAT_VAPIC
] = {
821 .desc
= "virtual APIC (hv-vapic)",
823 {.fw
= FEAT_HYPERV_EAX
,
824 .bits
= HV_HYPERCALL_AVAILABLE
| HV_APIC_ACCESS_AVAILABLE
},
825 {.fw
= FEAT_HV_RECOMM_EAX
,
826 .bits
= HV_APIC_ACCESS_RECOMMENDED
}
829 [HYPERV_FEAT_TIME
] = {
830 .desc
= "clocksources (hv-time)",
832 {.fw
= FEAT_HYPERV_EAX
,
833 .bits
= HV_HYPERCALL_AVAILABLE
| HV_TIME_REF_COUNT_AVAILABLE
|
834 HV_REFERENCE_TSC_AVAILABLE
}
837 [HYPERV_FEAT_CRASH
] = {
838 .desc
= "crash MSRs (hv-crash)",
840 {.fw
= FEAT_HYPERV_EDX
,
841 .bits
= HV_GUEST_CRASH_MSR_AVAILABLE
}
844 [HYPERV_FEAT_RESET
] = {
845 .desc
= "reset MSR (hv-reset)",
847 {.fw
= FEAT_HYPERV_EAX
,
848 .bits
= HV_RESET_AVAILABLE
}
851 [HYPERV_FEAT_VPINDEX
] = {
852 .desc
= "VP_INDEX MSR (hv-vpindex)",
854 {.fw
= FEAT_HYPERV_EAX
,
855 .bits
= HV_VP_INDEX_AVAILABLE
}
858 [HYPERV_FEAT_RUNTIME
] = {
859 .desc
= "VP_RUNTIME MSR (hv-runtime)",
861 {.fw
= FEAT_HYPERV_EAX
,
862 .bits
= HV_VP_RUNTIME_AVAILABLE
}
865 [HYPERV_FEAT_SYNIC
] = {
866 .desc
= "synthetic interrupt controller (hv-synic)",
868 {.fw
= FEAT_HYPERV_EAX
,
869 .bits
= HV_SYNIC_AVAILABLE
}
872 [HYPERV_FEAT_STIMER
] = {
873 .desc
= "synthetic timers (hv-stimer)",
875 {.fw
= FEAT_HYPERV_EAX
,
876 .bits
= HV_SYNTIMERS_AVAILABLE
}
878 .dependencies
= BIT(HYPERV_FEAT_SYNIC
) | BIT(HYPERV_FEAT_TIME
)
880 [HYPERV_FEAT_FREQUENCIES
] = {
881 .desc
= "frequency MSRs (hv-frequencies)",
883 {.fw
= FEAT_HYPERV_EAX
,
884 .bits
= HV_ACCESS_FREQUENCY_MSRS
},
885 {.fw
= FEAT_HYPERV_EDX
,
886 .bits
= HV_FREQUENCY_MSRS_AVAILABLE
}
889 [HYPERV_FEAT_REENLIGHTENMENT
] = {
890 .desc
= "reenlightenment MSRs (hv-reenlightenment)",
892 {.fw
= FEAT_HYPERV_EAX
,
893 .bits
= HV_ACCESS_REENLIGHTENMENTS_CONTROL
}
896 [HYPERV_FEAT_TLBFLUSH
] = {
897 .desc
= "paravirtualized TLB flush (hv-tlbflush)",
899 {.fw
= FEAT_HV_RECOMM_EAX
,
900 .bits
= HV_REMOTE_TLB_FLUSH_RECOMMENDED
|
901 HV_EX_PROCESSOR_MASKS_RECOMMENDED
}
903 .dependencies
= BIT(HYPERV_FEAT_VPINDEX
)
905 [HYPERV_FEAT_EVMCS
] = {
906 .desc
= "enlightened VMCS (hv-evmcs)",
908 {.fw
= FEAT_HV_RECOMM_EAX
,
909 .bits
= HV_ENLIGHTENED_VMCS_RECOMMENDED
}
911 .dependencies
= BIT(HYPERV_FEAT_VAPIC
)
913 [HYPERV_FEAT_IPI
] = {
914 .desc
= "paravirtualized IPI (hv-ipi)",
916 {.fw
= FEAT_HV_RECOMM_EAX
,
917 .bits
= HV_CLUSTER_IPI_RECOMMENDED
|
918 HV_EX_PROCESSOR_MASKS_RECOMMENDED
}
920 .dependencies
= BIT(HYPERV_FEAT_VPINDEX
)
922 [HYPERV_FEAT_STIMER_DIRECT
] = {
923 .desc
= "direct mode synthetic timers (hv-stimer-direct)",
925 {.fw
= FEAT_HYPERV_EDX
,
926 .bits
= HV_STIMER_DIRECT_MODE_AVAILABLE
}
928 .dependencies
= BIT(HYPERV_FEAT_STIMER
)
932 static struct kvm_cpuid2
*try_get_hv_cpuid(CPUState
*cs
, int max
)
934 struct kvm_cpuid2
*cpuid
;
937 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
938 cpuid
= g_malloc0(size
);
941 r
= kvm_vcpu_ioctl(cs
, KVM_GET_SUPPORTED_HV_CPUID
, cpuid
);
942 if (r
== 0 && cpuid
->nent
>= max
) {
950 fprintf(stderr
, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
959 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
962 static struct kvm_cpuid2
*get_supported_hv_cpuid(CPUState
*cs
)
964 struct kvm_cpuid2
*cpuid
;
965 int max
= 7; /* 0x40000000..0x40000005, 0x4000000A */
968 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
969 * -E2BIG, however, it doesn't report back the right size. Keep increasing
970 * it and re-trying until we succeed.
972 while ((cpuid
= try_get_hv_cpuid(cs
, max
)) == NULL
) {
979 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
980 * leaves from KVM_CAP_HYPERV* and present MSRs data.
982 static struct kvm_cpuid2
*get_supported_hv_cpuid_legacy(CPUState
*cs
)
984 X86CPU
*cpu
= X86_CPU(cs
);
985 struct kvm_cpuid2
*cpuid
;
986 struct kvm_cpuid_entry2
*entry_feat
, *entry_recomm
;
988 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
989 cpuid
= g_malloc0(sizeof(*cpuid
) + 2 * sizeof(*cpuid
->entries
));
992 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
993 entry_feat
= &cpuid
->entries
[0];
994 entry_feat
->function
= HV_CPUID_FEATURES
;
996 entry_recomm
= &cpuid
->entries
[1];
997 entry_recomm
->function
= HV_CPUID_ENLIGHTMENT_INFO
;
998 entry_recomm
->ebx
= cpu
->hyperv_spinlock_attempts
;
1000 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV
) > 0) {
1001 entry_feat
->eax
|= HV_HYPERCALL_AVAILABLE
;
1002 entry_feat
->eax
|= HV_APIC_ACCESS_AVAILABLE
;
1003 entry_feat
->edx
|= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE
;
1004 entry_recomm
->eax
|= HV_RELAXED_TIMING_RECOMMENDED
;
1005 entry_recomm
->eax
|= HV_APIC_ACCESS_RECOMMENDED
;
1008 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV_TIME
) > 0) {
1009 entry_feat
->eax
|= HV_TIME_REF_COUNT_AVAILABLE
;
1010 entry_feat
->eax
|= HV_REFERENCE_TSC_AVAILABLE
;
1013 if (has_msr_hv_frequencies
) {
1014 entry_feat
->eax
|= HV_ACCESS_FREQUENCY_MSRS
;
1015 entry_feat
->edx
|= HV_FREQUENCY_MSRS_AVAILABLE
;
1018 if (has_msr_hv_crash
) {
1019 entry_feat
->edx
|= HV_GUEST_CRASH_MSR_AVAILABLE
;
1022 if (has_msr_hv_reenlightenment
) {
1023 entry_feat
->eax
|= HV_ACCESS_REENLIGHTENMENTS_CONTROL
;
1026 if (has_msr_hv_reset
) {
1027 entry_feat
->eax
|= HV_RESET_AVAILABLE
;
1030 if (has_msr_hv_vpindex
) {
1031 entry_feat
->eax
|= HV_VP_INDEX_AVAILABLE
;
1034 if (has_msr_hv_runtime
) {
1035 entry_feat
->eax
|= HV_VP_RUNTIME_AVAILABLE
;
1038 if (has_msr_hv_synic
) {
1039 unsigned int cap
= cpu
->hyperv_synic_kvm_only
?
1040 KVM_CAP_HYPERV_SYNIC
: KVM_CAP_HYPERV_SYNIC2
;
1042 if (kvm_check_extension(cs
->kvm_state
, cap
) > 0) {
1043 entry_feat
->eax
|= HV_SYNIC_AVAILABLE
;
1047 if (has_msr_hv_stimer
) {
1048 entry_feat
->eax
|= HV_SYNTIMERS_AVAILABLE
;
1051 if (kvm_check_extension(cs
->kvm_state
,
1052 KVM_CAP_HYPERV_TLBFLUSH
) > 0) {
1053 entry_recomm
->eax
|= HV_REMOTE_TLB_FLUSH_RECOMMENDED
;
1054 entry_recomm
->eax
|= HV_EX_PROCESSOR_MASKS_RECOMMENDED
;
1057 if (kvm_check_extension(cs
->kvm_state
,
1058 KVM_CAP_HYPERV_ENLIGHTENED_VMCS
) > 0) {
1059 entry_recomm
->eax
|= HV_ENLIGHTENED_VMCS_RECOMMENDED
;
1062 if (kvm_check_extension(cs
->kvm_state
,
1063 KVM_CAP_HYPERV_SEND_IPI
) > 0) {
1064 entry_recomm
->eax
|= HV_CLUSTER_IPI_RECOMMENDED
;
1065 entry_recomm
->eax
|= HV_EX_PROCESSOR_MASKS_RECOMMENDED
;
1071 static int hv_cpuid_get_fw(struct kvm_cpuid2
*cpuid
, int fw
, uint32_t *r
)
1073 struct kvm_cpuid_entry2
*entry
;
1078 case FEAT_HYPERV_EAX
:
1080 func
= HV_CPUID_FEATURES
;
1082 case FEAT_HYPERV_EDX
:
1084 func
= HV_CPUID_FEATURES
;
1086 case FEAT_HV_RECOMM_EAX
:
1088 func
= HV_CPUID_ENLIGHTMENT_INFO
;
1094 entry
= cpuid_find_entry(cpuid
, func
, 0);
1113 static int hv_cpuid_check_and_set(CPUState
*cs
, struct kvm_cpuid2
*cpuid
,
1116 X86CPU
*cpu
= X86_CPU(cs
);
1117 CPUX86State
*env
= &cpu
->env
;
1118 uint32_t r
, fw
, bits
;
1122 if (!hyperv_feat_enabled(cpu
, feature
) && !cpu
->hyperv_passthrough
) {
1126 deps
= kvm_hyperv_properties
[feature
].dependencies
;
1128 dep_feat
= ctz64(deps
);
1129 if (!(hyperv_feat_enabled(cpu
, dep_feat
))) {
1131 "Hyper-V %s requires Hyper-V %s\n",
1132 kvm_hyperv_properties
[feature
].desc
,
1133 kvm_hyperv_properties
[dep_feat
].desc
);
1136 deps
&= ~(1ull << dep_feat
);
1139 for (i
= 0; i
< ARRAY_SIZE(kvm_hyperv_properties
[feature
].flags
); i
++) {
1140 fw
= kvm_hyperv_properties
[feature
].flags
[i
].fw
;
1141 bits
= kvm_hyperv_properties
[feature
].flags
[i
].bits
;
1147 if (hv_cpuid_get_fw(cpuid
, fw
, &r
) || (r
& bits
) != bits
) {
1148 if (hyperv_feat_enabled(cpu
, feature
)) {
1150 "Hyper-V %s is not supported by kernel\n",
1151 kvm_hyperv_properties
[feature
].desc
);
1158 env
->features
[fw
] |= bits
;
1161 if (cpu
->hyperv_passthrough
) {
1162 cpu
->hyperv_features
|= BIT(feature
);
1169 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1170 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1171 * extentions are enabled.
1173 static int hyperv_handle_properties(CPUState
*cs
,
1174 struct kvm_cpuid_entry2
*cpuid_ent
)
1176 X86CPU
*cpu
= X86_CPU(cs
);
1177 CPUX86State
*env
= &cpu
->env
;
1178 struct kvm_cpuid2
*cpuid
;
1179 struct kvm_cpuid_entry2
*c
;
1180 uint32_t signature
[3];
1181 uint32_t cpuid_i
= 0;
1184 if (!hyperv_enabled(cpu
))
1187 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_EVMCS
) ||
1188 cpu
->hyperv_passthrough
) {
1189 uint16_t evmcs_version
;
1191 r
= kvm_vcpu_enable_cap(cs
, KVM_CAP_HYPERV_ENLIGHTENED_VMCS
, 0,
1192 (uintptr_t)&evmcs_version
);
1194 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_EVMCS
) && r
) {
1195 fprintf(stderr
, "Hyper-V %s is not supported by kernel\n",
1196 kvm_hyperv_properties
[HYPERV_FEAT_EVMCS
].desc
);
1201 env
->features
[FEAT_HV_RECOMM_EAX
] |=
1202 HV_ENLIGHTENED_VMCS_RECOMMENDED
;
1203 env
->features
[FEAT_HV_NESTED_EAX
] = evmcs_version
;
1207 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV_CPUID
) > 0) {
1208 cpuid
= get_supported_hv_cpuid(cs
);
1210 cpuid
= get_supported_hv_cpuid_legacy(cs
);
1213 if (cpu
->hyperv_passthrough
) {
1214 memcpy(cpuid_ent
, &cpuid
->entries
[0],
1215 cpuid
->nent
* sizeof(cpuid
->entries
[0]));
1217 c
= cpuid_find_entry(cpuid
, HV_CPUID_FEATURES
, 0);
1219 env
->features
[FEAT_HYPERV_EAX
] = c
->eax
;
1220 env
->features
[FEAT_HYPERV_EBX
] = c
->ebx
;
1221 env
->features
[FEAT_HYPERV_EDX
] = c
->eax
;
1223 c
= cpuid_find_entry(cpuid
, HV_CPUID_ENLIGHTMENT_INFO
, 0);
1225 env
->features
[FEAT_HV_RECOMM_EAX
] = c
->eax
;
1227 /* hv-spinlocks may have been overriden */
1228 if (cpu
->hyperv_spinlock_attempts
!= HYPERV_SPINLOCK_NEVER_RETRY
) {
1229 c
->ebx
= cpu
->hyperv_spinlock_attempts
;
1232 c
= cpuid_find_entry(cpuid
, HV_CPUID_NESTED_FEATURES
, 0);
1234 env
->features
[FEAT_HV_NESTED_EAX
] = c
->eax
;
1238 if (cpu
->hyperv_no_nonarch_cs
== ON_OFF_AUTO_ON
) {
1239 env
->features
[FEAT_HV_RECOMM_EAX
] |= HV_NO_NONARCH_CORESHARING
;
1240 } else if (cpu
->hyperv_no_nonarch_cs
== ON_OFF_AUTO_AUTO
) {
1241 c
= cpuid_find_entry(cpuid
, HV_CPUID_ENLIGHTMENT_INFO
, 0);
1243 env
->features
[FEAT_HV_RECOMM_EAX
] |=
1244 c
->eax
& HV_NO_NONARCH_CORESHARING
;
1249 r
= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_RELAXED
);
1250 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_VAPIC
);
1251 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_TIME
);
1252 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_CRASH
);
1253 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_RESET
);
1254 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_VPINDEX
);
1255 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_RUNTIME
);
1256 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_SYNIC
);
1257 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_STIMER
);
1258 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_FREQUENCIES
);
1259 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_REENLIGHTENMENT
);
1260 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_TLBFLUSH
);
1261 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_EVMCS
);
1262 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_IPI
);
1263 r
|= hv_cpuid_check_and_set(cs
, cpuid
, HYPERV_FEAT_STIMER_DIRECT
);
1265 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1266 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
) &&
1267 !cpu
->hyperv_synic_kvm_only
&&
1268 !hyperv_feat_enabled(cpu
, HYPERV_FEAT_VPINDEX
)) {
1269 fprintf(stderr
, "Hyper-V %s requires Hyper-V %s\n",
1270 kvm_hyperv_properties
[HYPERV_FEAT_SYNIC
].desc
,
1271 kvm_hyperv_properties
[HYPERV_FEAT_VPINDEX
].desc
);
1275 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1276 env
->features
[FEAT_HYPERV_EDX
] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE
;
1283 if (cpu
->hyperv_passthrough
) {
1284 /* We already copied all feature words from KVM as is */
1289 c
= &cpuid_ent
[cpuid_i
++];
1290 c
->function
= HV_CPUID_VENDOR_AND_MAX_FUNCTIONS
;
1291 if (!cpu
->hyperv_vendor_id
) {
1292 memcpy(signature
, "Microsoft Hv", 12);
1294 size_t len
= strlen(cpu
->hyperv_vendor_id
);
1297 error_report("hv-vendor-id truncated to 12 characters");
1300 memset(signature
, 0, 12);
1301 memcpy(signature
, cpu
->hyperv_vendor_id
, len
);
1303 c
->eax
= hyperv_feat_enabled(cpu
, HYPERV_FEAT_EVMCS
) ?
1304 HV_CPUID_NESTED_FEATURES
: HV_CPUID_IMPLEMENT_LIMITS
;
1305 c
->ebx
= signature
[0];
1306 c
->ecx
= signature
[1];
1307 c
->edx
= signature
[2];
1309 c
= &cpuid_ent
[cpuid_i
++];
1310 c
->function
= HV_CPUID_INTERFACE
;
1311 memcpy(signature
, "Hv#1\0\0\0\0\0\0\0\0", 12);
1312 c
->eax
= signature
[0];
1317 c
= &cpuid_ent
[cpuid_i
++];
1318 c
->function
= HV_CPUID_VERSION
;
1319 c
->eax
= 0x00001bbc;
1320 c
->ebx
= 0x00060001;
1322 c
= &cpuid_ent
[cpuid_i
++];
1323 c
->function
= HV_CPUID_FEATURES
;
1324 c
->eax
= env
->features
[FEAT_HYPERV_EAX
];
1325 c
->ebx
= env
->features
[FEAT_HYPERV_EBX
];
1326 c
->edx
= env
->features
[FEAT_HYPERV_EDX
];
1328 c
= &cpuid_ent
[cpuid_i
++];
1329 c
->function
= HV_CPUID_ENLIGHTMENT_INFO
;
1330 c
->eax
= env
->features
[FEAT_HV_RECOMM_EAX
];
1331 c
->ebx
= cpu
->hyperv_spinlock_attempts
;
1333 c
= &cpuid_ent
[cpuid_i
++];
1334 c
->function
= HV_CPUID_IMPLEMENT_LIMITS
;
1335 c
->eax
= cpu
->hv_max_vps
;
1338 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_EVMCS
)) {
1341 /* Create zeroed 0x40000006..0x40000009 leaves */
1342 for (function
= HV_CPUID_IMPLEMENT_LIMITS
+ 1;
1343 function
< HV_CPUID_NESTED_FEATURES
; function
++) {
1344 c
= &cpuid_ent
[cpuid_i
++];
1345 c
->function
= function
;
1348 c
= &cpuid_ent
[cpuid_i
++];
1349 c
->function
= HV_CPUID_NESTED_FEATURES
;
1350 c
->eax
= env
->features
[FEAT_HV_NESTED_EAX
];
1360 static Error
*hv_passthrough_mig_blocker
;
1361 static Error
*hv_no_nonarch_cs_mig_blocker
;
1363 static int hyperv_init_vcpu(X86CPU
*cpu
)
1365 CPUState
*cs
= CPU(cpu
);
1366 Error
*local_err
= NULL
;
1369 if (cpu
->hyperv_passthrough
&& hv_passthrough_mig_blocker
== NULL
) {
1370 error_setg(&hv_passthrough_mig_blocker
,
1371 "'hv-passthrough' CPU flag prevents migration, use explicit"
1372 " set of hv-* flags instead");
1373 ret
= migrate_add_blocker(hv_passthrough_mig_blocker
, &local_err
);
1375 error_report_err(local_err
);
1376 error_free(hv_passthrough_mig_blocker
);
1381 if (cpu
->hyperv_no_nonarch_cs
== ON_OFF_AUTO_AUTO
&&
1382 hv_no_nonarch_cs_mig_blocker
== NULL
) {
1383 error_setg(&hv_no_nonarch_cs_mig_blocker
,
1384 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1385 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1386 " make sure SMT is disabled and/or that vCPUs are properly"
1388 ret
= migrate_add_blocker(hv_no_nonarch_cs_mig_blocker
, &local_err
);
1390 error_report_err(local_err
);
1391 error_free(hv_no_nonarch_cs_mig_blocker
);
1396 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VPINDEX
) && !hv_vpindex_settable
) {
1398 * the kernel doesn't support setting vp_index; assert that its value
1402 struct kvm_msrs info
;
1403 struct kvm_msr_entry entries
[1];
1406 .entries
[0].index
= HV_X64_MSR_VP_INDEX
,
1409 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_MSRS
, &msr_data
);
1415 if (msr_data
.entries
[0].data
!= hyperv_vp_index(CPU(cpu
))) {
1416 error_report("kernel's vp_index != QEMU's vp_index");
1421 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
)) {
1422 uint32_t synic_cap
= cpu
->hyperv_synic_kvm_only
?
1423 KVM_CAP_HYPERV_SYNIC
: KVM_CAP_HYPERV_SYNIC2
;
1424 ret
= kvm_vcpu_enable_cap(cs
, synic_cap
, 0);
1426 error_report("failed to turn on HyperV SynIC in KVM: %s",
1431 if (!cpu
->hyperv_synic_kvm_only
) {
1432 ret
= hyperv_x86_synic_add(cpu
);
1434 error_report("failed to create HyperV SynIC: %s",
1444 static Error
*invtsc_mig_blocker
;
1446 #define KVM_MAX_CPUID_ENTRIES 100
1448 int kvm_arch_init_vcpu(CPUState
*cs
)
1451 struct kvm_cpuid2 cpuid
;
1452 struct kvm_cpuid_entry2 entries
[KVM_MAX_CPUID_ENTRIES
];
1455 * The kernel defines these structs with padding fields so there
1456 * should be no extra padding in our cpuid_data struct.
1458 QEMU_BUILD_BUG_ON(sizeof(cpuid_data
) !=
1459 sizeof(struct kvm_cpuid2
) +
1460 sizeof(struct kvm_cpuid_entry2
) * KVM_MAX_CPUID_ENTRIES
);
1462 X86CPU
*cpu
= X86_CPU(cs
);
1463 CPUX86State
*env
= &cpu
->env
;
1464 uint32_t limit
, i
, j
, cpuid_i
;
1466 struct kvm_cpuid_entry2
*c
;
1467 uint32_t signature
[3];
1468 int kvm_base
= KVM_CPUID_SIGNATURE
;
1469 int max_nested_state_len
;
1471 Error
*local_err
= NULL
;
1473 memset(&cpuid_data
, 0, sizeof(cpuid_data
));
1477 r
= kvm_arch_set_tsc_khz(cs
);
1482 /* vcpu's TSC frequency is either specified by user, or following
1483 * the value used by KVM if the former is not present. In the
1484 * latter case, we query it from KVM and record in env->tsc_khz,
1485 * so that vcpu's TSC frequency can be migrated later via this field.
1487 if (!env
->tsc_khz
) {
1488 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
1489 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
1496 /* Paravirtualization CPUIDs */
1497 r
= hyperv_handle_properties(cs
, cpuid_data
.entries
);
1502 kvm_base
= KVM_CPUID_SIGNATURE_NEXT
;
1503 has_msr_hv_hypercall
= true;
1506 if (cpu
->expose_kvm
) {
1507 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
1508 c
= &cpuid_data
.entries
[cpuid_i
++];
1509 c
->function
= KVM_CPUID_SIGNATURE
| kvm_base
;
1510 c
->eax
= KVM_CPUID_FEATURES
| kvm_base
;
1511 c
->ebx
= signature
[0];
1512 c
->ecx
= signature
[1];
1513 c
->edx
= signature
[2];
1515 c
= &cpuid_data
.entries
[cpuid_i
++];
1516 c
->function
= KVM_CPUID_FEATURES
| kvm_base
;
1517 c
->eax
= env
->features
[FEAT_KVM
];
1518 c
->edx
= env
->features
[FEAT_KVM_HINTS
];
1521 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
1523 for (i
= 0; i
<= limit
; i
++) {
1524 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1525 fprintf(stderr
, "unsupported level value: 0x%x\n", limit
);
1528 c
= &cpuid_data
.entries
[cpuid_i
++];
1532 /* Keep reading function 2 till all the input is received */
1536 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
1537 KVM_CPUID_FLAG_STATE_READ_NEXT
;
1538 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1539 times
= c
->eax
& 0xff;
1541 for (j
= 1; j
< times
; ++j
) {
1542 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1543 fprintf(stderr
, "cpuid_data is full, no space for "
1544 "cpuid(eax:2):eax & 0xf = 0x%x\n", times
);
1547 c
= &cpuid_data
.entries
[cpuid_i
++];
1549 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
1550 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1555 if (env
->nr_dies
< 2) {
1561 for (j
= 0; ; j
++) {
1562 if (i
== 0xd && j
== 64) {
1566 if (i
== 0x1f && j
== 64) {
1571 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1573 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1575 if (i
== 4 && c
->eax
== 0) {
1578 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
1581 if (i
== 0x1f && !(c
->ecx
& 0xff00)) {
1584 if (i
== 0xd && c
->eax
== 0) {
1587 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1588 fprintf(stderr
, "cpuid_data is full, no space for "
1589 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
1592 c
= &cpuid_data
.entries
[cpuid_i
++];
1601 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1602 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1605 for (j
= 1; j
<= times
; ++j
) {
1606 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1607 fprintf(stderr
, "cpuid_data is full, no space for "
1608 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
1611 c
= &cpuid_data
.entries
[cpuid_i
++];
1614 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1615 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1622 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1623 if (!c
->eax
&& !c
->ebx
&& !c
->ecx
&& !c
->edx
) {
1625 * KVM already returns all zeroes if a CPUID entry is missing,
1626 * so we can omit it and avoid hitting KVM's 80-entry limit.
1634 if (limit
>= 0x0a) {
1637 cpu_x86_cpuid(env
, 0x0a, 0, &eax
, &unused
, &unused
, &edx
);
1639 has_architectural_pmu_version
= eax
& 0xff;
1640 if (has_architectural_pmu_version
> 0) {
1641 num_architectural_pmu_gp_counters
= (eax
& 0xff00) >> 8;
1643 /* Shouldn't be more than 32, since that's the number of bits
1644 * available in EBX to tell us _which_ counters are available.
1647 if (num_architectural_pmu_gp_counters
> MAX_GP_COUNTERS
) {
1648 num_architectural_pmu_gp_counters
= MAX_GP_COUNTERS
;
1651 if (has_architectural_pmu_version
> 1) {
1652 num_architectural_pmu_fixed_counters
= edx
& 0x1f;
1654 if (num_architectural_pmu_fixed_counters
> MAX_FIXED_COUNTERS
) {
1655 num_architectural_pmu_fixed_counters
= MAX_FIXED_COUNTERS
;
1661 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
1663 for (i
= 0x80000000; i
<= limit
; i
++) {
1664 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1665 fprintf(stderr
, "unsupported xlevel value: 0x%x\n", limit
);
1668 c
= &cpuid_data
.entries
[cpuid_i
++];
1672 /* Query for all AMD cache information leaves */
1673 for (j
= 0; ; j
++) {
1675 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1677 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1682 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1683 fprintf(stderr
, "cpuid_data is full, no space for "
1684 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
1687 c
= &cpuid_data
.entries
[cpuid_i
++];
1693 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1694 if (!c
->eax
&& !c
->ebx
&& !c
->ecx
&& !c
->edx
) {
1696 * KVM already returns all zeroes if a CPUID entry is missing,
1697 * so we can omit it and avoid hitting KVM's 80-entry limit.
1705 /* Call Centaur's CPUID instructions they are supported. */
1706 if (env
->cpuid_xlevel2
> 0) {
1707 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
1709 for (i
= 0xC0000000; i
<= limit
; i
++) {
1710 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
1711 fprintf(stderr
, "unsupported xlevel2 value: 0x%x\n", limit
);
1714 c
= &cpuid_data
.entries
[cpuid_i
++];
1718 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
1722 cpuid_data
.cpuid
.nent
= cpuid_i
;
1724 if (((env
->cpuid_version
>> 8)&0xF) >= 6
1725 && (env
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
1726 (CPUID_MCE
| CPUID_MCA
)
1727 && kvm_check_extension(cs
->kvm_state
, KVM_CAP_MCE
) > 0) {
1728 uint64_t mcg_cap
, unsupported_caps
;
1732 ret
= kvm_get_mce_cap_supported(cs
->kvm_state
, &mcg_cap
, &banks
);
1734 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
1738 if (banks
< (env
->mcg_cap
& MCG_CAP_BANKS_MASK
)) {
1739 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1740 (int)(env
->mcg_cap
& MCG_CAP_BANKS_MASK
), banks
);
1744 unsupported_caps
= env
->mcg_cap
& ~(mcg_cap
| MCG_CAP_BANKS_MASK
);
1745 if (unsupported_caps
) {
1746 if (unsupported_caps
& MCG_LMCE_P
) {
1747 error_report("kvm: LMCE not supported");
1750 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64
,
1754 env
->mcg_cap
&= mcg_cap
| MCG_CAP_BANKS_MASK
;
1755 ret
= kvm_vcpu_ioctl(cs
, KVM_X86_SETUP_MCE
, &env
->mcg_cap
);
1757 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
1762 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
1764 c
= cpuid_find_entry(&cpuid_data
.cpuid
, 1, 0);
1766 has_msr_feature_control
= !!(c
->ecx
& CPUID_EXT_VMX
) ||
1767 !!(c
->ecx
& CPUID_EXT_SMX
);
1770 if (env
->mcg_cap
& MCG_LMCE_P
) {
1771 has_msr_mcg_ext_ctl
= has_msr_feature_control
= true;
1774 if (!env
->user_tsc_khz
) {
1775 if ((env
->features
[FEAT_8000_0007_EDX
] & CPUID_APM_INVTSC
) &&
1776 invtsc_mig_blocker
== NULL
) {
1777 error_setg(&invtsc_mig_blocker
,
1778 "State blocked by non-migratable CPU device"
1780 r
= migrate_add_blocker(invtsc_mig_blocker
, &local_err
);
1782 error_report_err(local_err
);
1783 error_free(invtsc_mig_blocker
);
1789 if (cpu
->vmware_cpuid_freq
1790 /* Guests depend on 0x40000000 to detect this feature, so only expose
1791 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1793 && kvm_base
== KVM_CPUID_SIGNATURE
1794 /* TSC clock must be stable and known for this feature. */
1795 && tsc_is_stable_and_known(env
)) {
1797 c
= &cpuid_data
.entries
[cpuid_i
++];
1798 c
->function
= KVM_CPUID_SIGNATURE
| 0x10;
1799 c
->eax
= env
->tsc_khz
;
1800 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1801 * APIC_BUS_CYCLE_NS */
1803 c
->ecx
= c
->edx
= 0;
1805 c
= cpuid_find_entry(&cpuid_data
.cpuid
, kvm_base
, 0);
1806 c
->eax
= MAX(c
->eax
, KVM_CPUID_SIGNATURE
| 0x10);
1809 cpuid_data
.cpuid
.nent
= cpuid_i
;
1811 cpuid_data
.cpuid
.padding
= 0;
1812 r
= kvm_vcpu_ioctl(cs
, KVM_SET_CPUID2
, &cpuid_data
);
1818 env
->xsave_buf
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
1819 memset(env
->xsave_buf
, 0, sizeof(struct kvm_xsave
));
1822 max_nested_state_len
= kvm_max_nested_state_length();
1823 if (max_nested_state_len
> 0) {
1824 assert(max_nested_state_len
>= offsetof(struct kvm_nested_state
, data
));
1826 if (cpu_has_vmx(env
)) {
1827 struct kvm_vmx_nested_state_hdr
*vmx_hdr
;
1829 env
->nested_state
= g_malloc0(max_nested_state_len
);
1830 env
->nested_state
->size
= max_nested_state_len
;
1831 env
->nested_state
->format
= KVM_STATE_NESTED_FORMAT_VMX
;
1833 vmx_hdr
= &env
->nested_state
->hdr
.vmx
;
1834 vmx_hdr
->vmxon_pa
= -1ull;
1835 vmx_hdr
->vmcs12_pa
= -1ull;
1839 cpu
->kvm_msr_buf
= g_malloc0(MSR_BUF_SIZE
);
1841 if (!(env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_RDTSCP
)) {
1842 has_msr_tsc_aux
= false;
1845 r
= hyperv_init_vcpu(cpu
);
1853 migrate_del_blocker(invtsc_mig_blocker
);
1858 int kvm_arch_destroy_vcpu(CPUState
*cs
)
1860 X86CPU
*cpu
= X86_CPU(cs
);
1861 CPUX86State
*env
= &cpu
->env
;
1863 if (cpu
->kvm_msr_buf
) {
1864 g_free(cpu
->kvm_msr_buf
);
1865 cpu
->kvm_msr_buf
= NULL
;
1868 if (env
->nested_state
) {
1869 g_free(env
->nested_state
);
1870 env
->nested_state
= NULL
;
1876 void kvm_arch_reset_vcpu(X86CPU
*cpu
)
1878 CPUX86State
*env
= &cpu
->env
;
1881 if (kvm_irqchip_in_kernel()) {
1882 env
->mp_state
= cpu_is_bsp(cpu
) ? KVM_MP_STATE_RUNNABLE
:
1883 KVM_MP_STATE_UNINITIALIZED
;
1885 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
1888 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
)) {
1890 for (i
= 0; i
< ARRAY_SIZE(env
->msr_hv_synic_sint
); i
++) {
1891 env
->msr_hv_synic_sint
[i
] = HV_SINT_MASKED
;
1894 hyperv_x86_synic_reset(cpu
);
1896 /* enabled by default */
1897 env
->poll_control_msr
= 1;
1900 void kvm_arch_do_init_vcpu(X86CPU
*cpu
)
1902 CPUX86State
*env
= &cpu
->env
;
1904 /* APs get directly into wait-for-SIPI state. */
1905 if (env
->mp_state
== KVM_MP_STATE_UNINITIALIZED
) {
1906 env
->mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
1910 static int kvm_get_supported_feature_msrs(KVMState
*s
)
1914 if (kvm_feature_msrs
!= NULL
) {
1918 if (!kvm_check_extension(s
, KVM_CAP_GET_MSR_FEATURES
)) {
1922 struct kvm_msr_list msr_list
;
1925 ret
= kvm_ioctl(s
, KVM_GET_MSR_FEATURE_INDEX_LIST
, &msr_list
);
1926 if (ret
< 0 && ret
!= -E2BIG
) {
1927 error_report("Fetch KVM feature MSR list failed: %s",
1932 assert(msr_list
.nmsrs
> 0);
1933 kvm_feature_msrs
= (struct kvm_msr_list
*) \
1934 g_malloc0(sizeof(msr_list
) +
1935 msr_list
.nmsrs
* sizeof(msr_list
.indices
[0]));
1937 kvm_feature_msrs
->nmsrs
= msr_list
.nmsrs
;
1938 ret
= kvm_ioctl(s
, KVM_GET_MSR_FEATURE_INDEX_LIST
, kvm_feature_msrs
);
1941 error_report("Fetch KVM feature MSR list failed: %s",
1943 g_free(kvm_feature_msrs
);
1944 kvm_feature_msrs
= NULL
;
1951 static int kvm_get_supported_msrs(KVMState
*s
)
1954 struct kvm_msr_list msr_list
, *kvm_msr_list
;
1957 * Obtain MSR list from KVM. These are the MSRs that we must
1961 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
1962 if (ret
< 0 && ret
!= -E2BIG
) {
1966 * Old kernel modules had a bug and could write beyond the provided
1967 * memory. Allocate at least a safe amount of 1K.
1969 kvm_msr_list
= g_malloc0(MAX(1024, sizeof(msr_list
) +
1971 sizeof(msr_list
.indices
[0])));
1973 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
1974 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
1978 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
1979 switch (kvm_msr_list
->indices
[i
]) {
1981 has_msr_star
= true;
1983 case MSR_VM_HSAVE_PA
:
1984 has_msr_hsave_pa
= true;
1987 has_msr_tsc_aux
= true;
1989 case MSR_TSC_ADJUST
:
1990 has_msr_tsc_adjust
= true;
1992 case MSR_IA32_TSCDEADLINE
:
1993 has_msr_tsc_deadline
= true;
1995 case MSR_IA32_SMBASE
:
1996 has_msr_smbase
= true;
1999 has_msr_smi_count
= true;
2001 case MSR_IA32_MISC_ENABLE
:
2002 has_msr_misc_enable
= true;
2004 case MSR_IA32_BNDCFGS
:
2005 has_msr_bndcfgs
= true;
2010 case MSR_IA32_UMWAIT_CONTROL
:
2011 has_msr_umwait
= true;
2013 case HV_X64_MSR_CRASH_CTL
:
2014 has_msr_hv_crash
= true;
2016 case HV_X64_MSR_RESET
:
2017 has_msr_hv_reset
= true;
2019 case HV_X64_MSR_VP_INDEX
:
2020 has_msr_hv_vpindex
= true;
2022 case HV_X64_MSR_VP_RUNTIME
:
2023 has_msr_hv_runtime
= true;
2025 case HV_X64_MSR_SCONTROL
:
2026 has_msr_hv_synic
= true;
2028 case HV_X64_MSR_STIMER0_CONFIG
:
2029 has_msr_hv_stimer
= true;
2031 case HV_X64_MSR_TSC_FREQUENCY
:
2032 has_msr_hv_frequencies
= true;
2034 case HV_X64_MSR_REENLIGHTENMENT_CONTROL
:
2035 has_msr_hv_reenlightenment
= true;
2037 case MSR_IA32_SPEC_CTRL
:
2038 has_msr_spec_ctrl
= true;
2040 case MSR_IA32_TSX_CTRL
:
2041 has_msr_tsx_ctrl
= true;
2044 has_msr_virt_ssbd
= true;
2046 case MSR_IA32_ARCH_CAPABILITIES
:
2047 has_msr_arch_capabs
= true;
2049 case MSR_IA32_CORE_CAPABILITY
:
2050 has_msr_core_capabs
= true;
2052 case MSR_IA32_VMX_VMFUNC
:
2053 has_msr_vmx_vmfunc
= true;
2059 g_free(kvm_msr_list
);
2064 static Notifier smram_machine_done
;
2065 static KVMMemoryListener smram_listener
;
2066 static AddressSpace smram_address_space
;
2067 static MemoryRegion smram_as_root
;
2068 static MemoryRegion smram_as_mem
;
2070 static void register_smram_listener(Notifier
*n
, void *unused
)
2072 MemoryRegion
*smram
=
2073 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
2075 /* Outer container... */
2076 memory_region_init(&smram_as_root
, OBJECT(kvm_state
), "mem-container-smram", ~0ull);
2077 memory_region_set_enabled(&smram_as_root
, true);
2079 /* ... with two regions inside: normal system memory with low
2082 memory_region_init_alias(&smram_as_mem
, OBJECT(kvm_state
), "mem-smram",
2083 get_system_memory(), 0, ~0ull);
2084 memory_region_add_subregion_overlap(&smram_as_root
, 0, &smram_as_mem
, 0);
2085 memory_region_set_enabled(&smram_as_mem
, true);
2088 /* ... SMRAM with higher priority */
2089 memory_region_add_subregion_overlap(&smram_as_root
, 0, smram
, 10);
2090 memory_region_set_enabled(smram
, true);
2093 address_space_init(&smram_address_space
, &smram_as_root
, "KVM-SMRAM");
2094 kvm_memory_listener_register(kvm_state
, &smram_listener
,
2095 &smram_address_space
, 1);
2098 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
2100 uint64_t identity_base
= 0xfffbc000;
2101 uint64_t shadow_mem
;
2103 struct utsname utsname
;
2105 has_xsave
= kvm_check_extension(s
, KVM_CAP_XSAVE
);
2106 has_xcrs
= kvm_check_extension(s
, KVM_CAP_XCRS
);
2107 has_pit_state2
= kvm_check_extension(s
, KVM_CAP_PIT_STATE2
);
2109 hv_vpindex_settable
= kvm_check_extension(s
, KVM_CAP_HYPERV_VP_INDEX
);
2111 has_exception_payload
= kvm_check_extension(s
, KVM_CAP_EXCEPTION_PAYLOAD
);
2112 if (has_exception_payload
) {
2113 ret
= kvm_vm_enable_cap(s
, KVM_CAP_EXCEPTION_PAYLOAD
, 0, true);
2115 error_report("kvm: Failed to enable exception payload cap: %s",
2121 ret
= kvm_get_supported_msrs(s
);
2126 kvm_get_supported_feature_msrs(s
);
2129 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
2132 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2133 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2134 * Since these must be part of guest physical memory, we need to allocate
2135 * them, both by setting their start addresses in the kernel and by
2136 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2138 * Older KVM versions may not support setting the identity map base. In
2139 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2142 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
2143 /* Allows up to 16M BIOSes. */
2144 identity_base
= 0xfeffc000;
2146 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
2152 /* Set TSS base one page after EPT identity map. */
2153 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
2158 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2159 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
2161 fprintf(stderr
, "e820_add_entry() table is full\n");
2164 qemu_register_reset(kvm_unpoison_all
, NULL
);
2166 shadow_mem
= machine_kvm_shadow_mem(ms
);
2167 if (shadow_mem
!= -1) {
2169 ret
= kvm_vm_ioctl(s
, KVM_SET_NR_MMU_PAGES
, shadow_mem
);
2175 if (kvm_check_extension(s
, KVM_CAP_X86_SMM
) &&
2176 object_dynamic_cast(OBJECT(ms
), TYPE_PC_MACHINE
) &&
2177 pc_machine_is_smm_enabled(PC_MACHINE(ms
))) {
2178 smram_machine_done
.notify
= register_smram_listener
;
2179 qemu_add_machine_init_done_notifier(&smram_machine_done
);
2182 if (enable_cpu_pm
) {
2183 int disable_exits
= kvm_check_extension(s
, KVM_CAP_X86_DISABLE_EXITS
);
2186 /* Work around for kernel header with a typo. TODO: fix header and drop. */
2187 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2188 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2190 if (disable_exits
) {
2191 disable_exits
&= (KVM_X86_DISABLE_EXITS_MWAIT
|
2192 KVM_X86_DISABLE_EXITS_HLT
|
2193 KVM_X86_DISABLE_EXITS_PAUSE
|
2194 KVM_X86_DISABLE_EXITS_CSTATE
);
2197 ret
= kvm_vm_enable_cap(s
, KVM_CAP_X86_DISABLE_EXITS
, 0,
2200 error_report("kvm: guest stopping CPU not supported: %s",
2208 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
2210 lhs
->selector
= rhs
->selector
;
2211 lhs
->base
= rhs
->base
;
2212 lhs
->limit
= rhs
->limit
;
2224 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
2226 unsigned flags
= rhs
->flags
;
2227 lhs
->selector
= rhs
->selector
;
2228 lhs
->base
= rhs
->base
;
2229 lhs
->limit
= rhs
->limit
;
2230 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
2231 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
2232 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
2233 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
2234 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
2235 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
2236 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
2237 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
2238 lhs
->unusable
= !lhs
->present
;
2242 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
2244 lhs
->selector
= rhs
->selector
;
2245 lhs
->base
= rhs
->base
;
2246 lhs
->limit
= rhs
->limit
;
2247 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
2248 ((rhs
->present
&& !rhs
->unusable
) * DESC_P_MASK
) |
2249 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
2250 (rhs
->db
<< DESC_B_SHIFT
) |
2251 (rhs
->s
* DESC_S_MASK
) |
2252 (rhs
->l
<< DESC_L_SHIFT
) |
2253 (rhs
->g
* DESC_G_MASK
) |
2254 (rhs
->avl
* DESC_AVL_MASK
);
2257 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
2260 *kvm_reg
= *qemu_reg
;
2262 *qemu_reg
= *kvm_reg
;
2266 static int kvm_getput_regs(X86CPU
*cpu
, int set
)
2268 CPUX86State
*env
= &cpu
->env
;
2269 struct kvm_regs regs
;
2273 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_REGS
, ®s
);
2279 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
2280 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
2281 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
2282 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
2283 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
2284 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
2285 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
2286 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
2287 #ifdef TARGET_X86_64
2288 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
2289 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
2290 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
2291 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
2292 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
2293 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
2294 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
2295 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
2298 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
2299 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
2302 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_REGS
, ®s
);
2308 static int kvm_put_fpu(X86CPU
*cpu
)
2310 CPUX86State
*env
= &cpu
->env
;
2314 memset(&fpu
, 0, sizeof fpu
);
2315 fpu
.fsw
= env
->fpus
& ~(7 << 11);
2316 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
2317 fpu
.fcw
= env
->fpuc
;
2318 fpu
.last_opcode
= env
->fpop
;
2319 fpu
.last_ip
= env
->fpip
;
2320 fpu
.last_dp
= env
->fpdp
;
2321 for (i
= 0; i
< 8; ++i
) {
2322 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
2324 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
2325 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
2326 stq_p(&fpu
.xmm
[i
][0], env
->xmm_regs
[i
].ZMM_Q(0));
2327 stq_p(&fpu
.xmm
[i
][8], env
->xmm_regs
[i
].ZMM_Q(1));
2329 fpu
.mxcsr
= env
->mxcsr
;
2331 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_FPU
, &fpu
);
2334 #define XSAVE_FCW_FSW 0
2335 #define XSAVE_FTW_FOP 1
2336 #define XSAVE_CWD_RIP 2
2337 #define XSAVE_CWD_RDP 4
2338 #define XSAVE_MXCSR 6
2339 #define XSAVE_ST_SPACE 8
2340 #define XSAVE_XMM_SPACE 40
2341 #define XSAVE_XSTATE_BV 128
2342 #define XSAVE_YMMH_SPACE 144
2343 #define XSAVE_BNDREGS 240
2344 #define XSAVE_BNDCSR 256
2345 #define XSAVE_OPMASK 272
2346 #define XSAVE_ZMM_Hi256 288
2347 #define XSAVE_Hi16_ZMM 416
2348 #define XSAVE_PKRU 672
2350 #define XSAVE_BYTE_OFFSET(word_offset) \
2351 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
2353 #define ASSERT_OFFSET(word_offset, field) \
2354 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2355 offsetof(X86XSaveArea, field))
2357 ASSERT_OFFSET(XSAVE_FCW_FSW
, legacy
.fcw
);
2358 ASSERT_OFFSET(XSAVE_FTW_FOP
, legacy
.ftw
);
2359 ASSERT_OFFSET(XSAVE_CWD_RIP
, legacy
.fpip
);
2360 ASSERT_OFFSET(XSAVE_CWD_RDP
, legacy
.fpdp
);
2361 ASSERT_OFFSET(XSAVE_MXCSR
, legacy
.mxcsr
);
2362 ASSERT_OFFSET(XSAVE_ST_SPACE
, legacy
.fpregs
);
2363 ASSERT_OFFSET(XSAVE_XMM_SPACE
, legacy
.xmm_regs
);
2364 ASSERT_OFFSET(XSAVE_XSTATE_BV
, header
.xstate_bv
);
2365 ASSERT_OFFSET(XSAVE_YMMH_SPACE
, avx_state
);
2366 ASSERT_OFFSET(XSAVE_BNDREGS
, bndreg_state
);
2367 ASSERT_OFFSET(XSAVE_BNDCSR
, bndcsr_state
);
2368 ASSERT_OFFSET(XSAVE_OPMASK
, opmask_state
);
2369 ASSERT_OFFSET(XSAVE_ZMM_Hi256
, zmm_hi256_state
);
2370 ASSERT_OFFSET(XSAVE_Hi16_ZMM
, hi16_zmm_state
);
2371 ASSERT_OFFSET(XSAVE_PKRU
, pkru_state
);
2373 static int kvm_put_xsave(X86CPU
*cpu
)
2375 CPUX86State
*env
= &cpu
->env
;
2376 X86XSaveArea
*xsave
= env
->xsave_buf
;
2379 return kvm_put_fpu(cpu
);
2381 x86_cpu_xsave_all_areas(cpu
, xsave
);
2383 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XSAVE
, xsave
);
2386 static int kvm_put_xcrs(X86CPU
*cpu
)
2388 CPUX86State
*env
= &cpu
->env
;
2389 struct kvm_xcrs xcrs
= {};
2397 xcrs
.xcrs
[0].xcr
= 0;
2398 xcrs
.xcrs
[0].value
= env
->xcr0
;
2399 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XCRS
, &xcrs
);
2402 static int kvm_put_sregs(X86CPU
*cpu
)
2404 CPUX86State
*env
= &cpu
->env
;
2405 struct kvm_sregs sregs
;
2407 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
2408 if (env
->interrupt_injected
>= 0) {
2409 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
2410 (uint64_t)1 << (env
->interrupt_injected
% 64);
2413 if ((env
->eflags
& VM_MASK
)) {
2414 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
2415 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
2416 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
2417 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
2418 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
2419 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
2421 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
2422 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
2423 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
2424 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
2425 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
2426 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
2429 set_seg(&sregs
.tr
, &env
->tr
);
2430 set_seg(&sregs
.ldt
, &env
->ldt
);
2432 sregs
.idt
.limit
= env
->idt
.limit
;
2433 sregs
.idt
.base
= env
->idt
.base
;
2434 memset(sregs
.idt
.padding
, 0, sizeof sregs
.idt
.padding
);
2435 sregs
.gdt
.limit
= env
->gdt
.limit
;
2436 sregs
.gdt
.base
= env
->gdt
.base
;
2437 memset(sregs
.gdt
.padding
, 0, sizeof sregs
.gdt
.padding
);
2439 sregs
.cr0
= env
->cr
[0];
2440 sregs
.cr2
= env
->cr
[2];
2441 sregs
.cr3
= env
->cr
[3];
2442 sregs
.cr4
= env
->cr
[4];
2444 sregs
.cr8
= cpu_get_apic_tpr(cpu
->apic_state
);
2445 sregs
.apic_base
= cpu_get_apic_base(cpu
->apic_state
);
2447 sregs
.efer
= env
->efer
;
2449 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
2452 static void kvm_msr_buf_reset(X86CPU
*cpu
)
2454 memset(cpu
->kvm_msr_buf
, 0, MSR_BUF_SIZE
);
2457 static void kvm_msr_entry_add(X86CPU
*cpu
, uint32_t index
, uint64_t value
)
2459 struct kvm_msrs
*msrs
= cpu
->kvm_msr_buf
;
2460 void *limit
= ((void *)msrs
) + MSR_BUF_SIZE
;
2461 struct kvm_msr_entry
*entry
= &msrs
->entries
[msrs
->nmsrs
];
2463 assert((void *)(entry
+ 1) <= limit
);
2465 entry
->index
= index
;
2466 entry
->reserved
= 0;
2467 entry
->data
= value
;
2471 static int kvm_put_one_msr(X86CPU
*cpu
, int index
, uint64_t value
)
2473 kvm_msr_buf_reset(cpu
);
2474 kvm_msr_entry_add(cpu
, index
, value
);
2476 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
2479 void kvm_put_apicbase(X86CPU
*cpu
, uint64_t value
)
2483 ret
= kvm_put_one_msr(cpu
, MSR_IA32_APICBASE
, value
);
2487 static int kvm_put_tscdeadline_msr(X86CPU
*cpu
)
2489 CPUX86State
*env
= &cpu
->env
;
2492 if (!has_msr_tsc_deadline
) {
2496 ret
= kvm_put_one_msr(cpu
, MSR_IA32_TSCDEADLINE
, env
->tsc_deadline
);
2506 * Provide a separate write service for the feature control MSR in order to
2507 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2508 * before writing any other state because forcibly leaving nested mode
2509 * invalidates the VCPU state.
2511 static int kvm_put_msr_feature_control(X86CPU
*cpu
)
2515 if (!has_msr_feature_control
) {
2519 ret
= kvm_put_one_msr(cpu
, MSR_IA32_FEATURE_CONTROL
,
2520 cpu
->env
.msr_ia32_feature_control
);
2529 static uint64_t make_vmx_msr_value(uint32_t index
, uint32_t features
)
2531 uint32_t default1
, can_be_one
, can_be_zero
;
2532 uint32_t must_be_one
;
2535 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2536 default1
= 0x00000016;
2538 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2539 default1
= 0x0401e172;
2541 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2542 default1
= 0x000011ff;
2544 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2545 default1
= 0x00036dff;
2547 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2554 /* If a feature bit is set, the control can be either set or clear.
2555 * Otherwise the value is limited to either 0 or 1 by default1.
2557 can_be_one
= features
| default1
;
2558 can_be_zero
= features
| ~default1
;
2559 must_be_one
= ~can_be_zero
;
2562 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2563 * Bit 32:63 -> 1 if the control bit can be one.
2565 return must_be_one
| (((uint64_t)can_be_one
) << 32);
2568 #define VMCS12_MAX_FIELD_INDEX (0x17)
2570 static void kvm_msr_entry_add_vmx(X86CPU
*cpu
, FeatureWordArray f
)
2572 uint64_t kvm_vmx_basic
=
2573 kvm_arch_get_supported_msr_feature(kvm_state
,
2574 MSR_IA32_VMX_BASIC
);
2576 if (!kvm_vmx_basic
) {
2577 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
2578 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
2583 uint64_t kvm_vmx_misc
=
2584 kvm_arch_get_supported_msr_feature(kvm_state
,
2586 uint64_t kvm_vmx_ept_vpid
=
2587 kvm_arch_get_supported_msr_feature(kvm_state
,
2588 MSR_IA32_VMX_EPT_VPID_CAP
);
2591 * If the guest is 64-bit, a value of 1 is allowed for the host address
2592 * space size vmexit control.
2594 uint64_t fixed_vmx_exit
= f
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
2595 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE
<< 32 : 0;
2598 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2599 * not change them for backwards compatibility.
2601 uint64_t fixed_vmx_basic
= kvm_vmx_basic
&
2602 (MSR_VMX_BASIC_VMCS_REVISION_MASK
|
2603 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK
|
2604 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK
);
2607 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2608 * change in the future but are always zero for now, clear them to be
2609 * future proof. Bits 32-63 in theory could change, though KVM does
2610 * not support dual-monitor treatment and probably never will; mask
2613 uint64_t fixed_vmx_misc
= kvm_vmx_misc
&
2614 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK
|
2615 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK
);
2618 * EPT memory types should not change either, so we do not bother
2619 * adding features for them.
2621 uint64_t fixed_vmx_ept_mask
=
2622 (f
[FEAT_VMX_SECONDARY_CTLS
] & VMX_SECONDARY_EXEC_ENABLE_EPT
?
2623 MSR_VMX_EPT_UC
| MSR_VMX_EPT_WB
: 0);
2624 uint64_t fixed_vmx_ept_vpid
= kvm_vmx_ept_vpid
& fixed_vmx_ept_mask
;
2626 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_TRUE_PROCBASED_CTLS
,
2627 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS
,
2628 f
[FEAT_VMX_PROCBASED_CTLS
]));
2629 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_TRUE_PINBASED_CTLS
,
2630 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS
,
2631 f
[FEAT_VMX_PINBASED_CTLS
]));
2632 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_TRUE_EXIT_CTLS
,
2633 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS
,
2634 f
[FEAT_VMX_EXIT_CTLS
]) | fixed_vmx_exit
);
2635 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_TRUE_ENTRY_CTLS
,
2636 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS
,
2637 f
[FEAT_VMX_ENTRY_CTLS
]));
2638 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_PROCBASED_CTLS2
,
2639 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2
,
2640 f
[FEAT_VMX_SECONDARY_CTLS
]));
2641 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_EPT_VPID_CAP
,
2642 f
[FEAT_VMX_EPT_VPID_CAPS
] | fixed_vmx_ept_vpid
);
2643 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_BASIC
,
2644 f
[FEAT_VMX_BASIC
] | fixed_vmx_basic
);
2645 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_MISC
,
2646 f
[FEAT_VMX_MISC
] | fixed_vmx_misc
);
2647 if (has_msr_vmx_vmfunc
) {
2648 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_VMFUNC
, f
[FEAT_VMX_VMFUNC
]);
2652 * Just to be safe, write these with constant values. The CRn_FIXED1
2653 * MSRs are generated by KVM based on the vCPU's CPUID.
2655 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_CR0_FIXED0
,
2656 CR0_PE_MASK
| CR0_PG_MASK
| CR0_NE_MASK
);
2657 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_CR4_FIXED0
,
2659 kvm_msr_entry_add(cpu
, MSR_IA32_VMX_VMCS_ENUM
,
2660 VMCS12_MAX_FIELD_INDEX
<< 1);
2663 static int kvm_put_msrs(X86CPU
*cpu
, int level
)
2665 CPUX86State
*env
= &cpu
->env
;
2669 kvm_msr_buf_reset(cpu
);
2671 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
2672 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
2673 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
2674 kvm_msr_entry_add(cpu
, MSR_PAT
, env
->pat
);
2676 kvm_msr_entry_add(cpu
, MSR_STAR
, env
->star
);
2678 if (has_msr_hsave_pa
) {
2679 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, env
->vm_hsave
);
2681 if (has_msr_tsc_aux
) {
2682 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, env
->tsc_aux
);
2684 if (has_msr_tsc_adjust
) {
2685 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, env
->tsc_adjust
);
2687 if (has_msr_misc_enable
) {
2688 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
,
2689 env
->msr_ia32_misc_enable
);
2691 if (has_msr_smbase
) {
2692 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, env
->smbase
);
2694 if (has_msr_smi_count
) {
2695 kvm_msr_entry_add(cpu
, MSR_SMI_COUNT
, env
->msr_smi_count
);
2697 if (has_msr_bndcfgs
) {
2698 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, env
->msr_bndcfgs
);
2701 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, env
->xss
);
2703 if (has_msr_umwait
) {
2704 kvm_msr_entry_add(cpu
, MSR_IA32_UMWAIT_CONTROL
, env
->umwait
);
2706 if (has_msr_spec_ctrl
) {
2707 kvm_msr_entry_add(cpu
, MSR_IA32_SPEC_CTRL
, env
->spec_ctrl
);
2709 if (has_msr_tsx_ctrl
) {
2710 kvm_msr_entry_add(cpu
, MSR_IA32_TSX_CTRL
, env
->tsx_ctrl
);
2712 if (has_msr_virt_ssbd
) {
2713 kvm_msr_entry_add(cpu
, MSR_VIRT_SSBD
, env
->virt_ssbd
);
2716 #ifdef TARGET_X86_64
2717 if (lm_capable_kernel
) {
2718 kvm_msr_entry_add(cpu
, MSR_CSTAR
, env
->cstar
);
2719 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, env
->kernelgsbase
);
2720 kvm_msr_entry_add(cpu
, MSR_FMASK
, env
->fmask
);
2721 kvm_msr_entry_add(cpu
, MSR_LSTAR
, env
->lstar
);
2725 /* If host supports feature MSR, write down. */
2726 if (has_msr_arch_capabs
) {
2727 kvm_msr_entry_add(cpu
, MSR_IA32_ARCH_CAPABILITIES
,
2728 env
->features
[FEAT_ARCH_CAPABILITIES
]);
2731 if (has_msr_core_capabs
) {
2732 kvm_msr_entry_add(cpu
, MSR_IA32_CORE_CAPABILITY
,
2733 env
->features
[FEAT_CORE_CAPABILITY
]);
2737 * The following MSRs have side effects on the guest or are too heavy
2738 * for normal writeback. Limit them to reset or full state updates.
2740 if (level
>= KVM_PUT_RESET_STATE
) {
2741 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, env
->tsc
);
2742 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, env
->system_time_msr
);
2743 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
2744 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_ASYNC_PF
)) {
2745 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, env
->async_pf_en_msr
);
2747 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_PV_EOI
)) {
2748 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, env
->pv_eoi_en_msr
);
2750 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_STEAL_TIME
)) {
2751 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, env
->steal_time_msr
);
2754 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_POLL_CONTROL
)) {
2755 kvm_msr_entry_add(cpu
, MSR_KVM_POLL_CONTROL
, env
->poll_control_msr
);
2758 if (has_architectural_pmu_version
> 0) {
2759 if (has_architectural_pmu_version
> 1) {
2760 /* Stop the counter. */
2761 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
2762 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
2765 /* Set the counter values. */
2766 for (i
= 0; i
< num_architectural_pmu_fixed_counters
; i
++) {
2767 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
,
2768 env
->msr_fixed_counters
[i
]);
2770 for (i
= 0; i
< num_architectural_pmu_gp_counters
; i
++) {
2771 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
,
2772 env
->msr_gp_counters
[i
]);
2773 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
,
2774 env
->msr_gp_evtsel
[i
]);
2776 if (has_architectural_pmu_version
> 1) {
2777 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
,
2778 env
->msr_global_status
);
2779 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
,
2780 env
->msr_global_ovf_ctrl
);
2782 /* Now start the PMU. */
2783 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
,
2784 env
->msr_fixed_ctr_ctrl
);
2785 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
,
2786 env
->msr_global_ctrl
);
2790 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2791 * only sync them to KVM on the first cpu
2793 if (current_cpu
== first_cpu
) {
2794 if (has_msr_hv_hypercall
) {
2795 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
,
2796 env
->msr_hv_guest_os_id
);
2797 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
,
2798 env
->msr_hv_hypercall
);
2800 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_TIME
)) {
2801 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
,
2804 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_REENLIGHTENMENT
)) {
2805 kvm_msr_entry_add(cpu
, HV_X64_MSR_REENLIGHTENMENT_CONTROL
,
2806 env
->msr_hv_reenlightenment_control
);
2807 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_CONTROL
,
2808 env
->msr_hv_tsc_emulation_control
);
2809 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_STATUS
,
2810 env
->msr_hv_tsc_emulation_status
);
2813 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VAPIC
)) {
2814 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
,
2817 if (has_msr_hv_crash
) {
2820 for (j
= 0; j
< HV_CRASH_PARAMS
; j
++)
2821 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
,
2822 env
->msr_hv_crash_params
[j
]);
2824 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_CTL
, HV_CRASH_CTL_NOTIFY
);
2826 if (has_msr_hv_runtime
) {
2827 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, env
->msr_hv_runtime
);
2829 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VPINDEX
)
2830 && hv_vpindex_settable
) {
2831 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_INDEX
,
2832 hyperv_vp_index(CPU(cpu
)));
2834 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
)) {
2837 kvm_msr_entry_add(cpu
, HV_X64_MSR_SVERSION
, HV_SYNIC_VERSION
);
2839 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
,
2840 env
->msr_hv_synic_control
);
2841 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
,
2842 env
->msr_hv_synic_evt_page
);
2843 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
,
2844 env
->msr_hv_synic_msg_page
);
2846 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_synic_sint
); j
++) {
2847 kvm_msr_entry_add(cpu
, HV_X64_MSR_SINT0
+ j
,
2848 env
->msr_hv_synic_sint
[j
]);
2851 if (has_msr_hv_stimer
) {
2854 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_config
); j
++) {
2855 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_CONFIG
+ j
* 2,
2856 env
->msr_hv_stimer_config
[j
]);
2859 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_count
); j
++) {
2860 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_COUNT
+ j
* 2,
2861 env
->msr_hv_stimer_count
[j
]);
2864 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
2865 uint64_t phys_mask
= MAKE_64BIT_MASK(0, cpu
->phys_bits
);
2867 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, env
->mtrr_deftype
);
2868 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, env
->mtrr_fixed
[0]);
2869 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, env
->mtrr_fixed
[1]);
2870 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, env
->mtrr_fixed
[2]);
2871 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, env
->mtrr_fixed
[3]);
2872 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, env
->mtrr_fixed
[4]);
2873 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, env
->mtrr_fixed
[5]);
2874 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, env
->mtrr_fixed
[6]);
2875 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, env
->mtrr_fixed
[7]);
2876 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, env
->mtrr_fixed
[8]);
2877 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, env
->mtrr_fixed
[9]);
2878 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, env
->mtrr_fixed
[10]);
2879 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
2880 /* The CPU GPs if we write to a bit above the physical limit of
2881 * the host CPU (and KVM emulates that)
2883 uint64_t mask
= env
->mtrr_var
[i
].mask
;
2886 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
),
2887 env
->mtrr_var
[i
].base
);
2888 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), mask
);
2891 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) {
2892 int addr_num
= kvm_arch_get_supported_cpuid(kvm_state
,
2893 0x14, 1, R_EAX
) & 0x7;
2895 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CTL
,
2896 env
->msr_rtit_ctrl
);
2897 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_STATUS
,
2898 env
->msr_rtit_status
);
2899 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_BASE
,
2900 env
->msr_rtit_output_base
);
2901 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_MASK
,
2902 env
->msr_rtit_output_mask
);
2903 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CR3_MATCH
,
2904 env
->msr_rtit_cr3_match
);
2905 for (i
= 0; i
< addr_num
; i
++) {
2906 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_ADDR0_A
+ i
,
2907 env
->msr_rtit_addrs
[i
]);
2911 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2912 * kvm_put_msr_feature_control. */
2915 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
2916 * all kernels with MSR features should have them.
2918 if (kvm_feature_msrs
&& cpu_has_vmx(env
)) {
2919 kvm_msr_entry_add_vmx(cpu
, env
->features
);
2926 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, env
->mcg_status
);
2927 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, env
->mcg_ctl
);
2928 if (has_msr_mcg_ext_ctl
) {
2929 kvm_msr_entry_add(cpu
, MSR_MCG_EXT_CTL
, env
->mcg_ext_ctl
);
2931 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
2932 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
2936 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
2941 if (ret
< cpu
->kvm_msr_buf
->nmsrs
) {
2942 struct kvm_msr_entry
*e
= &cpu
->kvm_msr_buf
->entries
[ret
];
2943 error_report("error: failed to set MSR 0x%" PRIx32
" to 0x%" PRIx64
,
2944 (uint32_t)e
->index
, (uint64_t)e
->data
);
2947 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
2952 static int kvm_get_fpu(X86CPU
*cpu
)
2954 CPUX86State
*env
= &cpu
->env
;
2958 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_FPU
, &fpu
);
2963 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
2964 env
->fpus
= fpu
.fsw
;
2965 env
->fpuc
= fpu
.fcw
;
2966 env
->fpop
= fpu
.last_opcode
;
2967 env
->fpip
= fpu
.last_ip
;
2968 env
->fpdp
= fpu
.last_dp
;
2969 for (i
= 0; i
< 8; ++i
) {
2970 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
2972 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
2973 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
2974 env
->xmm_regs
[i
].ZMM_Q(0) = ldq_p(&fpu
.xmm
[i
][0]);
2975 env
->xmm_regs
[i
].ZMM_Q(1) = ldq_p(&fpu
.xmm
[i
][8]);
2977 env
->mxcsr
= fpu
.mxcsr
;
2982 static int kvm_get_xsave(X86CPU
*cpu
)
2984 CPUX86State
*env
= &cpu
->env
;
2985 X86XSaveArea
*xsave
= env
->xsave_buf
;
2989 return kvm_get_fpu(cpu
);
2992 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XSAVE
, xsave
);
2996 x86_cpu_xrstor_all_areas(cpu
, xsave
);
3001 static int kvm_get_xcrs(X86CPU
*cpu
)
3003 CPUX86State
*env
= &cpu
->env
;
3005 struct kvm_xcrs xcrs
;
3011 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XCRS
, &xcrs
);
3016 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
3017 /* Only support xcr0 now */
3018 if (xcrs
.xcrs
[i
].xcr
== 0) {
3019 env
->xcr0
= xcrs
.xcrs
[i
].value
;
3026 static int kvm_get_sregs(X86CPU
*cpu
)
3028 CPUX86State
*env
= &cpu
->env
;
3029 struct kvm_sregs sregs
;
3032 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
3037 /* There can only be one pending IRQ set in the bitmap at a time, so try
3038 to find it and save its number instead (-1 for none). */
3039 env
->interrupt_injected
= -1;
3040 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
3041 if (sregs
.interrupt_bitmap
[i
]) {
3042 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
3043 env
->interrupt_injected
= i
* 64 + bit
;
3048 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
3049 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
3050 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
3051 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
3052 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
3053 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
3055 get_seg(&env
->tr
, &sregs
.tr
);
3056 get_seg(&env
->ldt
, &sregs
.ldt
);
3058 env
->idt
.limit
= sregs
.idt
.limit
;
3059 env
->idt
.base
= sregs
.idt
.base
;
3060 env
->gdt
.limit
= sregs
.gdt
.limit
;
3061 env
->gdt
.base
= sregs
.gdt
.base
;
3063 env
->cr
[0] = sregs
.cr0
;
3064 env
->cr
[2] = sregs
.cr2
;
3065 env
->cr
[3] = sregs
.cr3
;
3066 env
->cr
[4] = sregs
.cr4
;
3068 env
->efer
= sregs
.efer
;
3070 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
3071 x86_update_hflags(env
);
3076 static int kvm_get_msrs(X86CPU
*cpu
)
3078 CPUX86State
*env
= &cpu
->env
;
3079 struct kvm_msr_entry
*msrs
= cpu
->kvm_msr_buf
->entries
;
3081 uint64_t mtrr_top_bits
;
3083 kvm_msr_buf_reset(cpu
);
3085 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, 0);
3086 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, 0);
3087 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, 0);
3088 kvm_msr_entry_add(cpu
, MSR_PAT
, 0);
3090 kvm_msr_entry_add(cpu
, MSR_STAR
, 0);
3092 if (has_msr_hsave_pa
) {
3093 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, 0);
3095 if (has_msr_tsc_aux
) {
3096 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, 0);
3098 if (has_msr_tsc_adjust
) {
3099 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, 0);
3101 if (has_msr_tsc_deadline
) {
3102 kvm_msr_entry_add(cpu
, MSR_IA32_TSCDEADLINE
, 0);
3104 if (has_msr_misc_enable
) {
3105 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
, 0);
3107 if (has_msr_smbase
) {
3108 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, 0);
3110 if (has_msr_smi_count
) {
3111 kvm_msr_entry_add(cpu
, MSR_SMI_COUNT
, 0);
3113 if (has_msr_feature_control
) {
3114 kvm_msr_entry_add(cpu
, MSR_IA32_FEATURE_CONTROL
, 0);
3116 if (has_msr_bndcfgs
) {
3117 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, 0);
3120 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, 0);
3122 if (has_msr_umwait
) {
3123 kvm_msr_entry_add(cpu
, MSR_IA32_UMWAIT_CONTROL
, 0);
3125 if (has_msr_spec_ctrl
) {
3126 kvm_msr_entry_add(cpu
, MSR_IA32_SPEC_CTRL
, 0);
3128 if (has_msr_tsx_ctrl
) {
3129 kvm_msr_entry_add(cpu
, MSR_IA32_TSX_CTRL
, 0);
3131 if (has_msr_virt_ssbd
) {
3132 kvm_msr_entry_add(cpu
, MSR_VIRT_SSBD
, 0);
3134 if (!env
->tsc_valid
) {
3135 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, 0);
3136 env
->tsc_valid
= !runstate_is_running();
3139 #ifdef TARGET_X86_64
3140 if (lm_capable_kernel
) {
3141 kvm_msr_entry_add(cpu
, MSR_CSTAR
, 0);
3142 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, 0);
3143 kvm_msr_entry_add(cpu
, MSR_FMASK
, 0);
3144 kvm_msr_entry_add(cpu
, MSR_LSTAR
, 0);
3147 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, 0);
3148 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, 0);
3149 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_ASYNC_PF
)) {
3150 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, 0);
3152 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_PV_EOI
)) {
3153 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, 0);
3155 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_STEAL_TIME
)) {
3156 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, 0);
3158 if (env
->features
[FEAT_KVM
] & (1 << KVM_FEATURE_POLL_CONTROL
)) {
3159 kvm_msr_entry_add(cpu
, MSR_KVM_POLL_CONTROL
, 1);
3161 if (has_architectural_pmu_version
> 0) {
3162 if (has_architectural_pmu_version
> 1) {
3163 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
3164 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
3165 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
, 0);
3166 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
, 0);
3168 for (i
= 0; i
< num_architectural_pmu_fixed_counters
; i
++) {
3169 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
, 0);
3171 for (i
= 0; i
< num_architectural_pmu_gp_counters
; i
++) {
3172 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
, 0);
3173 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
, 0);
3178 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, 0);
3179 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, 0);
3180 if (has_msr_mcg_ext_ctl
) {
3181 kvm_msr_entry_add(cpu
, MSR_MCG_EXT_CTL
, 0);
3183 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
3184 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, 0);
3188 if (has_msr_hv_hypercall
) {
3189 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
, 0);
3190 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
, 0);
3192 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VAPIC
)) {
3193 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
, 0);
3195 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_TIME
)) {
3196 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
, 0);
3198 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_REENLIGHTENMENT
)) {
3199 kvm_msr_entry_add(cpu
, HV_X64_MSR_REENLIGHTENMENT_CONTROL
, 0);
3200 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_CONTROL
, 0);
3201 kvm_msr_entry_add(cpu
, HV_X64_MSR_TSC_EMULATION_STATUS
, 0);
3203 if (has_msr_hv_crash
) {
3206 for (j
= 0; j
< HV_CRASH_PARAMS
; j
++) {
3207 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
, 0);
3210 if (has_msr_hv_runtime
) {
3211 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, 0);
3213 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_SYNIC
)) {
3216 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
, 0);
3217 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
, 0);
3218 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
, 0);
3219 for (msr
= HV_X64_MSR_SINT0
; msr
<= HV_X64_MSR_SINT15
; msr
++) {
3220 kvm_msr_entry_add(cpu
, msr
, 0);
3223 if (has_msr_hv_stimer
) {
3226 for (msr
= HV_X64_MSR_STIMER0_CONFIG
; msr
<= HV_X64_MSR_STIMER3_COUNT
;
3228 kvm_msr_entry_add(cpu
, msr
, 0);
3231 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
3232 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, 0);
3233 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, 0);
3234 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, 0);
3235 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, 0);
3236 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, 0);
3237 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, 0);
3238 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, 0);
3239 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, 0);
3240 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, 0);
3241 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, 0);
3242 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, 0);
3243 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, 0);
3244 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
3245 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
), 0);
3246 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), 0);
3250 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) {
3252 kvm_arch_get_supported_cpuid(kvm_state
, 0x14, 1, R_EAX
) & 0x7;
3254 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CTL
, 0);
3255 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_STATUS
, 0);
3256 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_BASE
, 0);
3257 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_OUTPUT_MASK
, 0);
3258 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_CR3_MATCH
, 0);
3259 for (i
= 0; i
< addr_num
; i
++) {
3260 kvm_msr_entry_add(cpu
, MSR_IA32_RTIT_ADDR0_A
+ i
, 0);
3264 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, cpu
->kvm_msr_buf
);
3269 if (ret
< cpu
->kvm_msr_buf
->nmsrs
) {
3270 struct kvm_msr_entry
*e
= &cpu
->kvm_msr_buf
->entries
[ret
];
3271 error_report("error: failed to get MSR 0x%" PRIx32
,
3272 (uint32_t)e
->index
);
3275 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
3277 * MTRR masks: Each mask consists of 5 parts
3278 * a 10..0: must be zero
3280 * c n-1.12: actual mask bits
3281 * d 51..n: reserved must be zero
3282 * e 63.52: reserved must be zero
3284 * 'n' is the number of physical bits supported by the CPU and is
3285 * apparently always <= 52. We know our 'n' but don't know what
3286 * the destinations 'n' is; it might be smaller, in which case
3287 * it masks (c) on loading. It might be larger, in which case
3288 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3289 * we're migrating to.
3292 if (cpu
->fill_mtrr_mask
) {
3293 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS
> 52);
3294 assert(cpu
->phys_bits
<= TARGET_PHYS_ADDR_SPACE_BITS
);
3295 mtrr_top_bits
= MAKE_64BIT_MASK(cpu
->phys_bits
, 52 - cpu
->phys_bits
);
3300 for (i
= 0; i
< ret
; i
++) {
3301 uint32_t index
= msrs
[i
].index
;
3303 case MSR_IA32_SYSENTER_CS
:
3304 env
->sysenter_cs
= msrs
[i
].data
;
3306 case MSR_IA32_SYSENTER_ESP
:
3307 env
->sysenter_esp
= msrs
[i
].data
;
3309 case MSR_IA32_SYSENTER_EIP
:
3310 env
->sysenter_eip
= msrs
[i
].data
;
3313 env
->pat
= msrs
[i
].data
;
3316 env
->star
= msrs
[i
].data
;
3318 #ifdef TARGET_X86_64
3320 env
->cstar
= msrs
[i
].data
;
3322 case MSR_KERNELGSBASE
:
3323 env
->kernelgsbase
= msrs
[i
].data
;
3326 env
->fmask
= msrs
[i
].data
;
3329 env
->lstar
= msrs
[i
].data
;
3333 env
->tsc
= msrs
[i
].data
;
3336 env
->tsc_aux
= msrs
[i
].data
;
3338 case MSR_TSC_ADJUST
:
3339 env
->tsc_adjust
= msrs
[i
].data
;
3341 case MSR_IA32_TSCDEADLINE
:
3342 env
->tsc_deadline
= msrs
[i
].data
;
3344 case MSR_VM_HSAVE_PA
:
3345 env
->vm_hsave
= msrs
[i
].data
;
3347 case MSR_KVM_SYSTEM_TIME
:
3348 env
->system_time_msr
= msrs
[i
].data
;
3350 case MSR_KVM_WALL_CLOCK
:
3351 env
->wall_clock_msr
= msrs
[i
].data
;
3353 case MSR_MCG_STATUS
:
3354 env
->mcg_status
= msrs
[i
].data
;
3357 env
->mcg_ctl
= msrs
[i
].data
;
3359 case MSR_MCG_EXT_CTL
:
3360 env
->mcg_ext_ctl
= msrs
[i
].data
;
3362 case MSR_IA32_MISC_ENABLE
:
3363 env
->msr_ia32_misc_enable
= msrs
[i
].data
;
3365 case MSR_IA32_SMBASE
:
3366 env
->smbase
= msrs
[i
].data
;
3369 env
->msr_smi_count
= msrs
[i
].data
;
3371 case MSR_IA32_FEATURE_CONTROL
:
3372 env
->msr_ia32_feature_control
= msrs
[i
].data
;
3374 case MSR_IA32_BNDCFGS
:
3375 env
->msr_bndcfgs
= msrs
[i
].data
;
3378 env
->xss
= msrs
[i
].data
;
3380 case MSR_IA32_UMWAIT_CONTROL
:
3381 env
->umwait
= msrs
[i
].data
;
3384 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
3385 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
3386 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
3389 case MSR_KVM_ASYNC_PF_EN
:
3390 env
->async_pf_en_msr
= msrs
[i
].data
;
3392 case MSR_KVM_PV_EOI_EN
:
3393 env
->pv_eoi_en_msr
= msrs
[i
].data
;
3395 case MSR_KVM_STEAL_TIME
:
3396 env
->steal_time_msr
= msrs
[i
].data
;
3398 case MSR_KVM_POLL_CONTROL
: {
3399 env
->poll_control_msr
= msrs
[i
].data
;
3402 case MSR_CORE_PERF_FIXED_CTR_CTRL
:
3403 env
->msr_fixed_ctr_ctrl
= msrs
[i
].data
;
3405 case MSR_CORE_PERF_GLOBAL_CTRL
:
3406 env
->msr_global_ctrl
= msrs
[i
].data
;
3408 case MSR_CORE_PERF_GLOBAL_STATUS
:
3409 env
->msr_global_status
= msrs
[i
].data
;
3411 case MSR_CORE_PERF_GLOBAL_OVF_CTRL
:
3412 env
->msr_global_ovf_ctrl
= msrs
[i
].data
;
3414 case MSR_CORE_PERF_FIXED_CTR0
... MSR_CORE_PERF_FIXED_CTR0
+ MAX_FIXED_COUNTERS
- 1:
3415 env
->msr_fixed_counters
[index
- MSR_CORE_PERF_FIXED_CTR0
] = msrs
[i
].data
;
3417 case MSR_P6_PERFCTR0
... MSR_P6_PERFCTR0
+ MAX_GP_COUNTERS
- 1:
3418 env
->msr_gp_counters
[index
- MSR_P6_PERFCTR0
] = msrs
[i
].data
;
3420 case MSR_P6_EVNTSEL0
... MSR_P6_EVNTSEL0
+ MAX_GP_COUNTERS
- 1:
3421 env
->msr_gp_evtsel
[index
- MSR_P6_EVNTSEL0
] = msrs
[i
].data
;
3423 case HV_X64_MSR_HYPERCALL
:
3424 env
->msr_hv_hypercall
= msrs
[i
].data
;
3426 case HV_X64_MSR_GUEST_OS_ID
:
3427 env
->msr_hv_guest_os_id
= msrs
[i
].data
;
3429 case HV_X64_MSR_APIC_ASSIST_PAGE
:
3430 env
->msr_hv_vapic
= msrs
[i
].data
;
3432 case HV_X64_MSR_REFERENCE_TSC
:
3433 env
->msr_hv_tsc
= msrs
[i
].data
;
3435 case HV_X64_MSR_CRASH_P0
... HV_X64_MSR_CRASH_P4
:
3436 env
->msr_hv_crash_params
[index
- HV_X64_MSR_CRASH_P0
] = msrs
[i
].data
;
3438 case HV_X64_MSR_VP_RUNTIME
:
3439 env
->msr_hv_runtime
= msrs
[i
].data
;
3441 case HV_X64_MSR_SCONTROL
:
3442 env
->msr_hv_synic_control
= msrs
[i
].data
;
3444 case HV_X64_MSR_SIEFP
:
3445 env
->msr_hv_synic_evt_page
= msrs
[i
].data
;
3447 case HV_X64_MSR_SIMP
:
3448 env
->msr_hv_synic_msg_page
= msrs
[i
].data
;
3450 case HV_X64_MSR_SINT0
... HV_X64_MSR_SINT15
:
3451 env
->msr_hv_synic_sint
[index
- HV_X64_MSR_SINT0
] = msrs
[i
].data
;
3453 case HV_X64_MSR_STIMER0_CONFIG
:
3454 case HV_X64_MSR_STIMER1_CONFIG
:
3455 case HV_X64_MSR_STIMER2_CONFIG
:
3456 case HV_X64_MSR_STIMER3_CONFIG
:
3457 env
->msr_hv_stimer_config
[(index
- HV_X64_MSR_STIMER0_CONFIG
)/2] =
3460 case HV_X64_MSR_STIMER0_COUNT
:
3461 case HV_X64_MSR_STIMER1_COUNT
:
3462 case HV_X64_MSR_STIMER2_COUNT
:
3463 case HV_X64_MSR_STIMER3_COUNT
:
3464 env
->msr_hv_stimer_count
[(index
- HV_X64_MSR_STIMER0_COUNT
)/2] =
3467 case HV_X64_MSR_REENLIGHTENMENT_CONTROL
:
3468 env
->msr_hv_reenlightenment_control
= msrs
[i
].data
;
3470 case HV_X64_MSR_TSC_EMULATION_CONTROL
:
3471 env
->msr_hv_tsc_emulation_control
= msrs
[i
].data
;
3473 case HV_X64_MSR_TSC_EMULATION_STATUS
:
3474 env
->msr_hv_tsc_emulation_status
= msrs
[i
].data
;
3476 case MSR_MTRRdefType
:
3477 env
->mtrr_deftype
= msrs
[i
].data
;
3479 case MSR_MTRRfix64K_00000
:
3480 env
->mtrr_fixed
[0] = msrs
[i
].data
;
3482 case MSR_MTRRfix16K_80000
:
3483 env
->mtrr_fixed
[1] = msrs
[i
].data
;
3485 case MSR_MTRRfix16K_A0000
:
3486 env
->mtrr_fixed
[2] = msrs
[i
].data
;
3488 case MSR_MTRRfix4K_C0000
:
3489 env
->mtrr_fixed
[3] = msrs
[i
].data
;
3491 case MSR_MTRRfix4K_C8000
:
3492 env
->mtrr_fixed
[4] = msrs
[i
].data
;
3494 case MSR_MTRRfix4K_D0000
:
3495 env
->mtrr_fixed
[5] = msrs
[i
].data
;
3497 case MSR_MTRRfix4K_D8000
:
3498 env
->mtrr_fixed
[6] = msrs
[i
].data
;
3500 case MSR_MTRRfix4K_E0000
:
3501 env
->mtrr_fixed
[7] = msrs
[i
].data
;
3503 case MSR_MTRRfix4K_E8000
:
3504 env
->mtrr_fixed
[8] = msrs
[i
].data
;
3506 case MSR_MTRRfix4K_F0000
:
3507 env
->mtrr_fixed
[9] = msrs
[i
].data
;
3509 case MSR_MTRRfix4K_F8000
:
3510 env
->mtrr_fixed
[10] = msrs
[i
].data
;
3512 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT
- 1):
3514 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].mask
= msrs
[i
].data
|
3517 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].base
= msrs
[i
].data
;
3520 case MSR_IA32_SPEC_CTRL
:
3521 env
->spec_ctrl
= msrs
[i
].data
;
3523 case MSR_IA32_TSX_CTRL
:
3524 env
->tsx_ctrl
= msrs
[i
].data
;
3527 env
->virt_ssbd
= msrs
[i
].data
;
3529 case MSR_IA32_RTIT_CTL
:
3530 env
->msr_rtit_ctrl
= msrs
[i
].data
;
3532 case MSR_IA32_RTIT_STATUS
:
3533 env
->msr_rtit_status
= msrs
[i
].data
;
3535 case MSR_IA32_RTIT_OUTPUT_BASE
:
3536 env
->msr_rtit_output_base
= msrs
[i
].data
;
3538 case MSR_IA32_RTIT_OUTPUT_MASK
:
3539 env
->msr_rtit_output_mask
= msrs
[i
].data
;
3541 case MSR_IA32_RTIT_CR3_MATCH
:
3542 env
->msr_rtit_cr3_match
= msrs
[i
].data
;
3544 case MSR_IA32_RTIT_ADDR0_A
... MSR_IA32_RTIT_ADDR3_B
:
3545 env
->msr_rtit_addrs
[index
- MSR_IA32_RTIT_ADDR0_A
] = msrs
[i
].data
;
3553 static int kvm_put_mp_state(X86CPU
*cpu
)
3555 struct kvm_mp_state mp_state
= { .mp_state
= cpu
->env
.mp_state
};
3557 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MP_STATE
, &mp_state
);
3560 static int kvm_get_mp_state(X86CPU
*cpu
)
3562 CPUState
*cs
= CPU(cpu
);
3563 CPUX86State
*env
= &cpu
->env
;
3564 struct kvm_mp_state mp_state
;
3567 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_MP_STATE
, &mp_state
);
3571 env
->mp_state
= mp_state
.mp_state
;
3572 if (kvm_irqchip_in_kernel()) {
3573 cs
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
3578 static int kvm_get_apic(X86CPU
*cpu
)
3580 DeviceState
*apic
= cpu
->apic_state
;
3581 struct kvm_lapic_state kapic
;
3584 if (apic
&& kvm_irqchip_in_kernel()) {
3585 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_LAPIC
, &kapic
);
3590 kvm_get_apic_state(apic
, &kapic
);
3595 static int kvm_put_vcpu_events(X86CPU
*cpu
, int level
)
3597 CPUState
*cs
= CPU(cpu
);
3598 CPUX86State
*env
= &cpu
->env
;
3599 struct kvm_vcpu_events events
= {};
3601 if (!kvm_has_vcpu_events()) {
3607 if (has_exception_payload
) {
3608 events
.flags
|= KVM_VCPUEVENT_VALID_PAYLOAD
;
3609 events
.exception
.pending
= env
->exception_pending
;
3610 events
.exception_has_payload
= env
->exception_has_payload
;
3611 events
.exception_payload
= env
->exception_payload
;
3613 events
.exception
.nr
= env
->exception_nr
;
3614 events
.exception
.injected
= env
->exception_injected
;
3615 events
.exception
.has_error_code
= env
->has_error_code
;
3616 events
.exception
.error_code
= env
->error_code
;
3618 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
3619 events
.interrupt
.nr
= env
->interrupt_injected
;
3620 events
.interrupt
.soft
= env
->soft_interrupt
;
3622 events
.nmi
.injected
= env
->nmi_injected
;
3623 events
.nmi
.pending
= env
->nmi_pending
;
3624 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
3626 events
.sipi_vector
= env
->sipi_vector
;
3628 if (has_msr_smbase
) {
3629 events
.smi
.smm
= !!(env
->hflags
& HF_SMM_MASK
);
3630 events
.smi
.smm_inside_nmi
= !!(env
->hflags2
& HF2_SMM_INSIDE_NMI_MASK
);
3631 if (kvm_irqchip_in_kernel()) {
3632 /* As soon as these are moved to the kernel, remove them
3633 * from cs->interrupt_request.
3635 events
.smi
.pending
= cs
->interrupt_request
& CPU_INTERRUPT_SMI
;
3636 events
.smi
.latched_init
= cs
->interrupt_request
& CPU_INTERRUPT_INIT
;
3637 cs
->interrupt_request
&= ~(CPU_INTERRUPT_INIT
| CPU_INTERRUPT_SMI
);
3639 /* Keep these in cs->interrupt_request. */
3640 events
.smi
.pending
= 0;
3641 events
.smi
.latched_init
= 0;
3643 /* Stop SMI delivery on old machine types to avoid a reboot
3644 * on an inward migration of an old VM.
3646 if (!cpu
->kvm_no_smi_migration
) {
3647 events
.flags
|= KVM_VCPUEVENT_VALID_SMM
;
3651 if (level
>= KVM_PUT_RESET_STATE
) {
3652 events
.flags
|= KVM_VCPUEVENT_VALID_NMI_PENDING
;
3653 if (env
->mp_state
== KVM_MP_STATE_SIPI_RECEIVED
) {
3654 events
.flags
|= KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
3658 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_VCPU_EVENTS
, &events
);
3661 static int kvm_get_vcpu_events(X86CPU
*cpu
)
3663 CPUX86State
*env
= &cpu
->env
;
3664 struct kvm_vcpu_events events
;
3667 if (!kvm_has_vcpu_events()) {
3671 memset(&events
, 0, sizeof(events
));
3672 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_VCPU_EVENTS
, &events
);
3677 if (events
.flags
& KVM_VCPUEVENT_VALID_PAYLOAD
) {
3678 env
->exception_pending
= events
.exception
.pending
;
3679 env
->exception_has_payload
= events
.exception_has_payload
;
3680 env
->exception_payload
= events
.exception_payload
;
3682 env
->exception_pending
= 0;
3683 env
->exception_has_payload
= false;
3685 env
->exception_injected
= events
.exception
.injected
;
3687 (env
->exception_pending
|| env
->exception_injected
) ?
3688 events
.exception
.nr
: -1;
3689 env
->has_error_code
= events
.exception
.has_error_code
;
3690 env
->error_code
= events
.exception
.error_code
;
3692 env
->interrupt_injected
=
3693 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
3694 env
->soft_interrupt
= events
.interrupt
.soft
;
3696 env
->nmi_injected
= events
.nmi
.injected
;
3697 env
->nmi_pending
= events
.nmi
.pending
;
3698 if (events
.nmi
.masked
) {
3699 env
->hflags2
|= HF2_NMI_MASK
;
3701 env
->hflags2
&= ~HF2_NMI_MASK
;
3704 if (events
.flags
& KVM_VCPUEVENT_VALID_SMM
) {
3705 if (events
.smi
.smm
) {
3706 env
->hflags
|= HF_SMM_MASK
;
3708 env
->hflags
&= ~HF_SMM_MASK
;
3710 if (events
.smi
.pending
) {
3711 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
3713 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
3715 if (events
.smi
.smm_inside_nmi
) {
3716 env
->hflags2
|= HF2_SMM_INSIDE_NMI_MASK
;
3718 env
->hflags2
&= ~HF2_SMM_INSIDE_NMI_MASK
;
3720 if (events
.smi
.latched_init
) {
3721 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
3723 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
3727 env
->sipi_vector
= events
.sipi_vector
;
3732 static int kvm_guest_debug_workarounds(X86CPU
*cpu
)
3734 CPUState
*cs
= CPU(cpu
);
3735 CPUX86State
*env
= &cpu
->env
;
3737 unsigned long reinject_trap
= 0;
3739 if (!kvm_has_vcpu_events()) {
3740 if (env
->exception_nr
== EXCP01_DB
) {
3741 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
3742 } else if (env
->exception_injected
== EXCP03_INT3
) {
3743 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
3745 kvm_reset_exception(env
);
3749 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3750 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3751 * by updating the debug state once again if single-stepping is on.
3752 * Another reason to call kvm_update_guest_debug here is a pending debug
3753 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3754 * reinject them via SET_GUEST_DEBUG.
3756 if (reinject_trap
||
3757 (!kvm_has_robust_singlestep() && cs
->singlestep_enabled
)) {
3758 ret
= kvm_update_guest_debug(cs
, reinject_trap
);
3763 static int kvm_put_debugregs(X86CPU
*cpu
)
3765 CPUX86State
*env
= &cpu
->env
;
3766 struct kvm_debugregs dbgregs
;
3769 if (!kvm_has_debugregs()) {
3773 memset(&dbgregs
, 0, sizeof(dbgregs
));
3774 for (i
= 0; i
< 4; i
++) {
3775 dbgregs
.db
[i
] = env
->dr
[i
];
3777 dbgregs
.dr6
= env
->dr
[6];
3778 dbgregs
.dr7
= env
->dr
[7];
3781 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_DEBUGREGS
, &dbgregs
);
3784 static int kvm_get_debugregs(X86CPU
*cpu
)
3786 CPUX86State
*env
= &cpu
->env
;
3787 struct kvm_debugregs dbgregs
;
3790 if (!kvm_has_debugregs()) {
3794 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_DEBUGREGS
, &dbgregs
);
3798 for (i
= 0; i
< 4; i
++) {
3799 env
->dr
[i
] = dbgregs
.db
[i
];
3801 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
3802 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
3807 static int kvm_put_nested_state(X86CPU
*cpu
)
3809 CPUX86State
*env
= &cpu
->env
;
3810 int max_nested_state_len
= kvm_max_nested_state_length();
3812 if (!env
->nested_state
) {
3816 assert(env
->nested_state
->size
<= max_nested_state_len
);
3817 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_NESTED_STATE
, env
->nested_state
);
3820 static int kvm_get_nested_state(X86CPU
*cpu
)
3822 CPUX86State
*env
= &cpu
->env
;
3823 int max_nested_state_len
= kvm_max_nested_state_length();
3826 if (!env
->nested_state
) {
3831 * It is possible that migration restored a smaller size into
3832 * nested_state->hdr.size than what our kernel support.
3833 * We preserve migration origin nested_state->hdr.size for
3834 * call to KVM_SET_NESTED_STATE but wish that our next call
3835 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3837 env
->nested_state
->size
= max_nested_state_len
;
3839 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_NESTED_STATE
, env
->nested_state
);
3844 if (env
->nested_state
->flags
& KVM_STATE_NESTED_GUEST_MODE
) {
3845 env
->hflags
|= HF_GUEST_MASK
;
3847 env
->hflags
&= ~HF_GUEST_MASK
;
3853 int kvm_arch_put_registers(CPUState
*cpu
, int level
)
3855 X86CPU
*x86_cpu
= X86_CPU(cpu
);
3858 assert(cpu_is_stopped(cpu
) || qemu_cpu_is_self(cpu
));
3860 if (level
>= KVM_PUT_RESET_STATE
) {
3861 ret
= kvm_put_nested_state(x86_cpu
);
3866 ret
= kvm_put_msr_feature_control(x86_cpu
);
3872 if (level
== KVM_PUT_FULL_STATE
) {
3873 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3874 * because TSC frequency mismatch shouldn't abort migration,
3875 * unless the user explicitly asked for a more strict TSC
3876 * setting (e.g. using an explicit "tsc-freq" option).
3878 kvm_arch_set_tsc_khz(cpu
);
3881 ret
= kvm_getput_regs(x86_cpu
, 1);
3885 ret
= kvm_put_xsave(x86_cpu
);
3889 ret
= kvm_put_xcrs(x86_cpu
);
3893 ret
= kvm_put_sregs(x86_cpu
);
3897 /* must be before kvm_put_msrs */
3898 ret
= kvm_inject_mce_oldstyle(x86_cpu
);
3902 ret
= kvm_put_msrs(x86_cpu
, level
);
3906 ret
= kvm_put_vcpu_events(x86_cpu
, level
);
3910 if (level
>= KVM_PUT_RESET_STATE
) {
3911 ret
= kvm_put_mp_state(x86_cpu
);
3917 ret
= kvm_put_tscdeadline_msr(x86_cpu
);
3921 ret
= kvm_put_debugregs(x86_cpu
);
3926 ret
= kvm_guest_debug_workarounds(x86_cpu
);
3933 int kvm_arch_get_registers(CPUState
*cs
)
3935 X86CPU
*cpu
= X86_CPU(cs
);
3938 assert(cpu_is_stopped(cs
) || qemu_cpu_is_self(cs
));
3940 ret
= kvm_get_vcpu_events(cpu
);
3945 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3946 * KVM_GET_REGS and KVM_GET_SREGS.
3948 ret
= kvm_get_mp_state(cpu
);
3952 ret
= kvm_getput_regs(cpu
, 0);
3956 ret
= kvm_get_xsave(cpu
);
3960 ret
= kvm_get_xcrs(cpu
);
3964 ret
= kvm_get_sregs(cpu
);
3968 ret
= kvm_get_msrs(cpu
);
3972 ret
= kvm_get_apic(cpu
);
3976 ret
= kvm_get_debugregs(cpu
);
3980 ret
= kvm_get_nested_state(cpu
);
3986 cpu_sync_bndcs_hflags(&cpu
->env
);
3990 void kvm_arch_pre_run(CPUState
*cpu
, struct kvm_run
*run
)
3992 X86CPU
*x86_cpu
= X86_CPU(cpu
);
3993 CPUX86State
*env
= &x86_cpu
->env
;
3997 if (cpu
->interrupt_request
& (CPU_INTERRUPT_NMI
| CPU_INTERRUPT_SMI
)) {
3998 if (cpu
->interrupt_request
& CPU_INTERRUPT_NMI
) {
3999 qemu_mutex_lock_iothread();
4000 cpu
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
4001 qemu_mutex_unlock_iothread();
4002 DPRINTF("injected NMI\n");
4003 ret
= kvm_vcpu_ioctl(cpu
, KVM_NMI
);
4005 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
4009 if (cpu
->interrupt_request
& CPU_INTERRUPT_SMI
) {
4010 qemu_mutex_lock_iothread();
4011 cpu
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
4012 qemu_mutex_unlock_iothread();
4013 DPRINTF("injected SMI\n");
4014 ret
= kvm_vcpu_ioctl(cpu
, KVM_SMI
);
4016 fprintf(stderr
, "KVM: injection failed, SMI lost (%s)\n",
4022 if (!kvm_pic_in_kernel()) {
4023 qemu_mutex_lock_iothread();
4026 /* Force the VCPU out of its inner loop to process any INIT requests
4027 * or (for userspace APIC, but it is cheap to combine the checks here)
4028 * pending TPR access reports.
4030 if (cpu
->interrupt_request
& (CPU_INTERRUPT_INIT
| CPU_INTERRUPT_TPR
)) {
4031 if ((cpu
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
4032 !(env
->hflags
& HF_SMM_MASK
)) {
4033 cpu
->exit_request
= 1;
4035 if (cpu
->interrupt_request
& CPU_INTERRUPT_TPR
) {
4036 cpu
->exit_request
= 1;
4040 if (!kvm_pic_in_kernel()) {
4041 /* Try to inject an interrupt if the guest can accept it */
4042 if (run
->ready_for_interrupt_injection
&&
4043 (cpu
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
4044 (env
->eflags
& IF_MASK
)) {
4047 cpu
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
4048 irq
= cpu_get_pic_interrupt(env
);
4050 struct kvm_interrupt intr
;
4053 DPRINTF("injected interrupt %d\n", irq
);
4054 ret
= kvm_vcpu_ioctl(cpu
, KVM_INTERRUPT
, &intr
);
4057 "KVM: injection failed, interrupt lost (%s)\n",
4063 /* If we have an interrupt but the guest is not ready to receive an
4064 * interrupt, request an interrupt window exit. This will
4065 * cause a return to userspace as soon as the guest is ready to
4066 * receive interrupts. */
4067 if ((cpu
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
4068 run
->request_interrupt_window
= 1;
4070 run
->request_interrupt_window
= 0;
4073 DPRINTF("setting tpr\n");
4074 run
->cr8
= cpu_get_apic_tpr(x86_cpu
->apic_state
);
4076 qemu_mutex_unlock_iothread();
4080 MemTxAttrs
kvm_arch_post_run(CPUState
*cpu
, struct kvm_run
*run
)
4082 X86CPU
*x86_cpu
= X86_CPU(cpu
);
4083 CPUX86State
*env
= &x86_cpu
->env
;
4085 if (run
->flags
& KVM_RUN_X86_SMM
) {
4086 env
->hflags
|= HF_SMM_MASK
;
4088 env
->hflags
&= ~HF_SMM_MASK
;
4091 env
->eflags
|= IF_MASK
;
4093 env
->eflags
&= ~IF_MASK
;
4096 /* We need to protect the apic state against concurrent accesses from
4097 * different threads in case the userspace irqchip is used. */
4098 if (!kvm_irqchip_in_kernel()) {
4099 qemu_mutex_lock_iothread();
4101 cpu_set_apic_tpr(x86_cpu
->apic_state
, run
->cr8
);
4102 cpu_set_apic_base(x86_cpu
->apic_state
, run
->apic_base
);
4103 if (!kvm_irqchip_in_kernel()) {
4104 qemu_mutex_unlock_iothread();
4106 return cpu_get_mem_attrs(env
);
4109 int kvm_arch_process_async_events(CPUState
*cs
)
4111 X86CPU
*cpu
= X86_CPU(cs
);
4112 CPUX86State
*env
= &cpu
->env
;
4114 if (cs
->interrupt_request
& CPU_INTERRUPT_MCE
) {
4115 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4116 assert(env
->mcg_cap
);
4118 cs
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
4120 kvm_cpu_synchronize_state(cs
);
4122 if (env
->exception_nr
== EXCP08_DBLE
) {
4123 /* this means triple fault */
4124 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
4125 cs
->exit_request
= 1;
4128 kvm_queue_exception(env
, EXCP12_MCHK
, 0, 0);
4129 env
->has_error_code
= 0;
4132 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
4133 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
4137 if ((cs
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
4138 !(env
->hflags
& HF_SMM_MASK
)) {
4139 kvm_cpu_synchronize_state(cs
);
4143 if (kvm_irqchip_in_kernel()) {
4147 if (cs
->interrupt_request
& CPU_INTERRUPT_POLL
) {
4148 cs
->interrupt_request
&= ~CPU_INTERRUPT_POLL
;
4149 apic_poll_irq(cpu
->apic_state
);
4151 if (((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
4152 (env
->eflags
& IF_MASK
)) ||
4153 (cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
4156 if (cs
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
4157 kvm_cpu_synchronize_state(cs
);
4160 if (cs
->interrupt_request
& CPU_INTERRUPT_TPR
) {
4161 cs
->interrupt_request
&= ~CPU_INTERRUPT_TPR
;
4162 kvm_cpu_synchronize_state(cs
);
4163 apic_handle_tpr_access_report(cpu
->apic_state
, env
->eip
,
4164 env
->tpr_access_type
);
4170 static int kvm_handle_halt(X86CPU
*cpu
)
4172 CPUState
*cs
= CPU(cpu
);
4173 CPUX86State
*env
= &cpu
->env
;
4175 if (!((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
4176 (env
->eflags
& IF_MASK
)) &&
4177 !(cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
4185 static int kvm_handle_tpr_access(X86CPU
*cpu
)
4187 CPUState
*cs
= CPU(cpu
);
4188 struct kvm_run
*run
= cs
->kvm_run
;
4190 apic_handle_tpr_access_report(cpu
->apic_state
, run
->tpr_access
.rip
,
4191 run
->tpr_access
.is_write
? TPR_ACCESS_WRITE
4196 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
4198 static const uint8_t int3
= 0xcc;
4200 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
4201 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
4207 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
4211 if (cpu_memory_rw_debug(cs
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
4212 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
4224 static int nb_hw_breakpoint
;
4226 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
4230 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
4231 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
4232 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
4239 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
4240 target_ulong len
, int type
)
4243 case GDB_BREAKPOINT_HW
:
4246 case GDB_WATCHPOINT_WRITE
:
4247 case GDB_WATCHPOINT_ACCESS
:
4254 if (addr
& (len
- 1)) {
4266 if (nb_hw_breakpoint
== 4) {
4269 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
4272 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
4273 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
4274 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
4280 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
4281 target_ulong len
, int type
)
4285 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
4290 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
4295 void kvm_arch_remove_all_hw_breakpoints(void)
4297 nb_hw_breakpoint
= 0;
4300 static CPUWatchpoint hw_watchpoint
;
4302 static int kvm_handle_debug(X86CPU
*cpu
,
4303 struct kvm_debug_exit_arch
*arch_info
)
4305 CPUState
*cs
= CPU(cpu
);
4306 CPUX86State
*env
= &cpu
->env
;
4310 if (arch_info
->exception
== EXCP01_DB
) {
4311 if (arch_info
->dr6
& DR6_BS
) {
4312 if (cs
->singlestep_enabled
) {
4316 for (n
= 0; n
< 4; n
++) {
4317 if (arch_info
->dr6
& (1 << n
)) {
4318 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
4324 cs
->watchpoint_hit
= &hw_watchpoint
;
4325 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
4326 hw_watchpoint
.flags
= BP_MEM_WRITE
;
4330 cs
->watchpoint_hit
= &hw_watchpoint
;
4331 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
4332 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
4338 } else if (kvm_find_sw_breakpoint(cs
, arch_info
->pc
)) {
4342 cpu_synchronize_state(cs
);
4343 assert(env
->exception_nr
== -1);
4346 kvm_queue_exception(env
, arch_info
->exception
,
4347 arch_info
->exception
== EXCP01_DB
,
4349 env
->has_error_code
= 0;
4355 void kvm_arch_update_guest_debug(CPUState
*cpu
, struct kvm_guest_debug
*dbg
)
4357 const uint8_t type_code
[] = {
4358 [GDB_BREAKPOINT_HW
] = 0x0,
4359 [GDB_WATCHPOINT_WRITE
] = 0x1,
4360 [GDB_WATCHPOINT_ACCESS
] = 0x3
4362 const uint8_t len_code
[] = {
4363 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4367 if (kvm_sw_breakpoints_active(cpu
)) {
4368 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
4370 if (nb_hw_breakpoint
> 0) {
4371 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
4372 dbg
->arch
.debugreg
[7] = 0x0600;
4373 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
4374 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
4375 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
4376 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
4377 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
4382 static bool host_supports_vmx(void)
4384 uint32_t ecx
, unused
;
4386 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
4387 return ecx
& CPUID_EXT_VMX
;
4390 #define VMX_INVALID_GUEST_STATE 0x80000021
4392 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
4394 X86CPU
*cpu
= X86_CPU(cs
);
4398 switch (run
->exit_reason
) {
4400 DPRINTF("handle_hlt\n");
4401 qemu_mutex_lock_iothread();
4402 ret
= kvm_handle_halt(cpu
);
4403 qemu_mutex_unlock_iothread();
4405 case KVM_EXIT_SET_TPR
:
4408 case KVM_EXIT_TPR_ACCESS
:
4409 qemu_mutex_lock_iothread();
4410 ret
= kvm_handle_tpr_access(cpu
);
4411 qemu_mutex_unlock_iothread();
4413 case KVM_EXIT_FAIL_ENTRY
:
4414 code
= run
->fail_entry
.hardware_entry_failure_reason
;
4415 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
4417 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
4419 "\nIf you're running a guest on an Intel machine without "
4420 "unrestricted mode\n"
4421 "support, the failure can be most likely due to the guest "
4422 "entering an invalid\n"
4423 "state for Intel VT. For example, the guest maybe running "
4424 "in big real mode\n"
4425 "which is not supported on less recent Intel processors."
4430 case KVM_EXIT_EXCEPTION
:
4431 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
4432 run
->ex
.exception
, run
->ex
.error_code
);
4435 case KVM_EXIT_DEBUG
:
4436 DPRINTF("kvm_exit_debug\n");
4437 qemu_mutex_lock_iothread();
4438 ret
= kvm_handle_debug(cpu
, &run
->debug
.arch
);
4439 qemu_mutex_unlock_iothread();
4441 case KVM_EXIT_HYPERV
:
4442 ret
= kvm_hv_handle_exit(cpu
, &run
->hyperv
);
4444 case KVM_EXIT_IOAPIC_EOI
:
4445 ioapic_eoi_broadcast(run
->eoi
.vector
);
4449 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
4457 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
4459 X86CPU
*cpu
= X86_CPU(cs
);
4460 CPUX86State
*env
= &cpu
->env
;
4462 kvm_cpu_synchronize_state(cs
);
4463 return !(env
->cr
[0] & CR0_PE_MASK
) ||
4464 ((env
->segs
[R_CS
].selector
& 3) != 3);
4467 void kvm_arch_init_irq_routing(KVMState
*s
)
4469 if (!kvm_check_extension(s
, KVM_CAP_IRQ_ROUTING
)) {
4470 /* If kernel can't do irq routing, interrupt source
4471 * override 0->2 cannot be set up as required by HPET.
4472 * So we have to disable it.
4476 /* We know at this point that we're using the in-kernel
4477 * irqchip, so we can use irqfds, and on x86 we know
4478 * we can use msi via irqfd and GSI routing.
4480 kvm_msi_via_irqfd_allowed
= true;
4481 kvm_gsi_routing_allowed
= true;
4483 if (kvm_irqchip_is_split()) {
4486 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4487 MSI routes for signaling interrupts to the local apics. */
4488 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
4489 if (kvm_irqchip_add_msi_route(s
, 0, NULL
) < 0) {
4490 error_report("Could not enable split IRQ mode.");
4497 int kvm_arch_irqchip_create(MachineState
*ms
, KVMState
*s
)
4500 if (machine_kernel_irqchip_split(ms
)) {
4501 ret
= kvm_vm_enable_cap(s
, KVM_CAP_SPLIT_IRQCHIP
, 0, 24);
4503 error_report("Could not enable split irqchip mode: %s",
4507 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4508 kvm_split_irqchip
= true;
4516 /* Classic KVM device assignment interface. Will remain x86 only. */
4517 int kvm_device_pci_assign(KVMState
*s
, PCIHostDeviceAddress
*dev_addr
,
4518 uint32_t flags
, uint32_t *dev_id
)
4520 struct kvm_assigned_pci_dev dev_data
= {
4521 .segnr
= dev_addr
->domain
,
4522 .busnr
= dev_addr
->bus
,
4523 .devfn
= PCI_DEVFN(dev_addr
->slot
, dev_addr
->function
),
4528 dev_data
.assigned_dev_id
=
4529 (dev_addr
->domain
<< 16) | (dev_addr
->bus
<< 8) | dev_data
.devfn
;
4531 ret
= kvm_vm_ioctl(s
, KVM_ASSIGN_PCI_DEVICE
, &dev_data
);
4536 *dev_id
= dev_data
.assigned_dev_id
;
4541 int kvm_device_pci_deassign(KVMState
*s
, uint32_t dev_id
)
4543 struct kvm_assigned_pci_dev dev_data
= {
4544 .assigned_dev_id
= dev_id
,
4547 return kvm_vm_ioctl(s
, KVM_DEASSIGN_PCI_DEVICE
, &dev_data
);
4550 static int kvm_assign_irq_internal(KVMState
*s
, uint32_t dev_id
,
4551 uint32_t irq_type
, uint32_t guest_irq
)
4553 struct kvm_assigned_irq assigned_irq
= {
4554 .assigned_dev_id
= dev_id
,
4555 .guest_irq
= guest_irq
,
4559 if (kvm_check_extension(s
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
4560 return kvm_vm_ioctl(s
, KVM_ASSIGN_DEV_IRQ
, &assigned_irq
);
4562 return kvm_vm_ioctl(s
, KVM_ASSIGN_IRQ
, &assigned_irq
);
4566 int kvm_device_intx_assign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
,
4569 uint32_t irq_type
= KVM_DEV_IRQ_GUEST_INTX
|
4570 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
);
4572 return kvm_assign_irq_internal(s
, dev_id
, irq_type
, guest_irq
);
4575 int kvm_device_intx_set_mask(KVMState
*s
, uint32_t dev_id
, bool masked
)
4577 struct kvm_assigned_pci_dev dev_data
= {
4578 .assigned_dev_id
= dev_id
,
4579 .flags
= masked
? KVM_DEV_ASSIGN_MASK_INTX
: 0,
4582 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_INTX_MASK
, &dev_data
);
4585 static int kvm_deassign_irq_internal(KVMState
*s
, uint32_t dev_id
,
4588 struct kvm_assigned_irq assigned_irq
= {
4589 .assigned_dev_id
= dev_id
,
4593 return kvm_vm_ioctl(s
, KVM_DEASSIGN_DEV_IRQ
, &assigned_irq
);
4596 int kvm_device_intx_deassign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
)
4598 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_INTX
|
4599 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
));
4602 int kvm_device_msi_assign(KVMState
*s
, uint32_t dev_id
, int virq
)
4604 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSI
|
4605 KVM_DEV_IRQ_GUEST_MSI
, virq
);
4608 int kvm_device_msi_deassign(KVMState
*s
, uint32_t dev_id
)
4610 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSI
|
4611 KVM_DEV_IRQ_HOST_MSI
);
4614 bool kvm_device_msix_supported(KVMState
*s
)
4616 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4617 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4618 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, NULL
) == -EFAULT
;
4621 int kvm_device_msix_init_vectors(KVMState
*s
, uint32_t dev_id
,
4622 uint32_t nr_vectors
)
4624 struct kvm_assigned_msix_nr msix_nr
= {
4625 .assigned_dev_id
= dev_id
,
4626 .entry_nr
= nr_vectors
,
4629 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, &msix_nr
);
4632 int kvm_device_msix_set_vector(KVMState
*s
, uint32_t dev_id
, uint32_t vector
,
4635 struct kvm_assigned_msix_entry msix_entry
= {
4636 .assigned_dev_id
= dev_id
,
4641 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_ENTRY
, &msix_entry
);
4644 int kvm_device_msix_assign(KVMState
*s
, uint32_t dev_id
)
4646 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSIX
|
4647 KVM_DEV_IRQ_GUEST_MSIX
, 0);
4650 int kvm_device_msix_deassign(KVMState
*s
, uint32_t dev_id
)
4652 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSIX
|
4653 KVM_DEV_IRQ_HOST_MSIX
);
4656 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
4657 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
4659 X86IOMMUState
*iommu
= x86_iommu_get_default();
4663 MSIMessage src
, dst
;
4664 X86IOMMUClass
*class = X86_IOMMU_GET_CLASS(iommu
);
4666 if (!class->int_remap
) {
4670 src
.address
= route
->u
.msi
.address_hi
;
4671 src
.address
<<= VTD_MSI_ADDR_HI_SHIFT
;
4672 src
.address
|= route
->u
.msi
.address_lo
;
4673 src
.data
= route
->u
.msi
.data
;
4675 ret
= class->int_remap(iommu
, &src
, &dst
, dev
? \
4676 pci_requester_id(dev
) : \
4677 X86_IOMMU_SID_INVALID
);
4679 trace_kvm_x86_fixup_msi_error(route
->gsi
);
4683 route
->u
.msi
.address_hi
= dst
.address
>> VTD_MSI_ADDR_HI_SHIFT
;
4684 route
->u
.msi
.address_lo
= dst
.address
& VTD_MSI_ADDR_LO_MASK
;
4685 route
->u
.msi
.data
= dst
.data
;
4691 typedef struct MSIRouteEntry MSIRouteEntry
;
4693 struct MSIRouteEntry
{
4694 PCIDevice
*dev
; /* Device pointer */
4695 int vector
; /* MSI/MSIX vector index */
4696 int virq
; /* Virtual IRQ index */
4697 QLIST_ENTRY(MSIRouteEntry
) list
;
4700 /* List of used GSI routes */
4701 static QLIST_HEAD(, MSIRouteEntry
) msi_route_list
= \
4702 QLIST_HEAD_INITIALIZER(msi_route_list
);
4704 static void kvm_update_msi_routes_all(void *private, bool global
,
4705 uint32_t index
, uint32_t mask
)
4707 int cnt
= 0, vector
;
4708 MSIRouteEntry
*entry
;
4712 /* TODO: explicit route update */
4713 QLIST_FOREACH(entry
, &msi_route_list
, list
) {
4715 vector
= entry
->vector
;
4717 if (msix_enabled(dev
) && !msix_is_masked(dev
, vector
)) {
4718 msg
= msix_get_message(dev
, vector
);
4719 } else if (msi_enabled(dev
) && !msi_is_masked(dev
, vector
)) {
4720 msg
= msi_get_message(dev
, vector
);
4723 * Either MSI/MSIX is disabled for the device, or the
4724 * specific message was masked out. Skip this one.
4728 kvm_irqchip_update_msi_route(kvm_state
, entry
->virq
, msg
, dev
);
4730 kvm_irqchip_commit_routes(kvm_state
);
4731 trace_kvm_x86_update_msi_routes(cnt
);
4734 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
4735 int vector
, PCIDevice
*dev
)
4737 static bool notify_list_inited
= false;
4738 MSIRouteEntry
*entry
;
4741 /* These are (possibly) IOAPIC routes only used for split
4742 * kernel irqchip mode, while what we are housekeeping are
4743 * PCI devices only. */
4747 entry
= g_new0(MSIRouteEntry
, 1);
4749 entry
->vector
= vector
;
4750 entry
->virq
= route
->gsi
;
4751 QLIST_INSERT_HEAD(&msi_route_list
, entry
, list
);
4753 trace_kvm_x86_add_msi_route(route
->gsi
);
4755 if (!notify_list_inited
) {
4756 /* For the first time we do add route, add ourselves into
4757 * IOMMU's IEC notify list if needed. */
4758 X86IOMMUState
*iommu
= x86_iommu_get_default();
4760 x86_iommu_iec_register_notifier(iommu
,
4761 kvm_update_msi_routes_all
,
4764 notify_list_inited
= true;
4769 int kvm_arch_release_virq_post(int virq
)
4771 MSIRouteEntry
*entry
, *next
;
4772 QLIST_FOREACH_SAFE(entry
, &msi_route_list
, list
, next
) {
4773 if (entry
->virq
== virq
) {
4774 trace_kvm_x86_remove_msi_route(virq
);
4775 QLIST_REMOVE(entry
, list
);
4783 int kvm_arch_msi_data_to_gsi(uint32_t data
)