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hyperv: add header with protocol definitions
[mirror_qemu.git] / target / i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30 #include "hyperv-proto.h"
31
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/config-file.h"
35 #include "qemu/error-report.h"
36 #include "hw/i386/pc.h"
37 #include "hw/i386/apic.h"
38 #include "hw/i386/apic_internal.h"
39 #include "hw/i386/apic-msidef.h"
40 #include "hw/i386/intel_iommu.h"
41 #include "hw/i386/x86-iommu.h"
42
43 #include "exec/ioport.h"
44 #include "hw/pci/pci.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "migration/blocker.h"
48 #include "exec/memattrs.h"
49 #include "trace.h"
50
51 //#define DEBUG_KVM
52
53 #ifdef DEBUG_KVM
54 #define DPRINTF(fmt, ...) \
55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56 #else
57 #define DPRINTF(fmt, ...) \
58 do { } while (0)
59 #endif
60
61 #define MSR_KVM_WALL_CLOCK 0x11
62 #define MSR_KVM_SYSTEM_TIME 0x12
63
64 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66 #define MSR_BUF_SIZE 4096
67
68 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73 };
74
75 static bool has_msr_star;
76 static bool has_msr_hsave_pa;
77 static bool has_msr_tsc_aux;
78 static bool has_msr_tsc_adjust;
79 static bool has_msr_tsc_deadline;
80 static bool has_msr_feature_control;
81 static bool has_msr_misc_enable;
82 static bool has_msr_smbase;
83 static bool has_msr_bndcfgs;
84 static int lm_capable_kernel;
85 static bool has_msr_hv_hypercall;
86 static bool has_msr_hv_crash;
87 static bool has_msr_hv_reset;
88 static bool has_msr_hv_vpindex;
89 static bool has_msr_hv_runtime;
90 static bool has_msr_hv_synic;
91 static bool has_msr_hv_stimer;
92 static bool has_msr_hv_frequencies;
93 static bool has_msr_xss;
94
95 static bool has_msr_architectural_pmu;
96 static uint32_t num_architectural_pmu_counters;
97
98 static int has_xsave;
99 static int has_xcrs;
100 static int has_pit_state2;
101
102 static bool has_msr_mcg_ext_ctl;
103
104 static struct kvm_cpuid2 *cpuid_cache;
105
106 int kvm_has_pit_state2(void)
107 {
108 return has_pit_state2;
109 }
110
111 bool kvm_has_smm(void)
112 {
113 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
114 }
115
116 bool kvm_has_adjust_clock_stable(void)
117 {
118 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
119
120 return (ret == KVM_CLOCK_TSC_STABLE);
121 }
122
123 bool kvm_allows_irq0_override(void)
124 {
125 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
126 }
127
128 static bool kvm_x2apic_api_set_flags(uint64_t flags)
129 {
130 KVMState *s = KVM_STATE(current_machine->accelerator);
131
132 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
133 }
134
135 #define MEMORIZE(fn, _result) \
136 ({ \
137 static bool _memorized; \
138 \
139 if (_memorized) { \
140 return _result; \
141 } \
142 _memorized = true; \
143 _result = fn; \
144 })
145
146 static bool has_x2apic_api;
147
148 bool kvm_has_x2apic_api(void)
149 {
150 return has_x2apic_api;
151 }
152
153 bool kvm_enable_x2apic(void)
154 {
155 return MEMORIZE(
156 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
157 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
158 has_x2apic_api);
159 }
160
161 static int kvm_get_tsc(CPUState *cs)
162 {
163 X86CPU *cpu = X86_CPU(cs);
164 CPUX86State *env = &cpu->env;
165 struct {
166 struct kvm_msrs info;
167 struct kvm_msr_entry entries[1];
168 } msr_data;
169 int ret;
170
171 if (env->tsc_valid) {
172 return 0;
173 }
174
175 msr_data.info.nmsrs = 1;
176 msr_data.entries[0].index = MSR_IA32_TSC;
177 env->tsc_valid = !runstate_is_running();
178
179 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
180 if (ret < 0) {
181 return ret;
182 }
183
184 assert(ret == 1);
185 env->tsc = msr_data.entries[0].data;
186 return 0;
187 }
188
189 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
190 {
191 kvm_get_tsc(cpu);
192 }
193
194 void kvm_synchronize_all_tsc(void)
195 {
196 CPUState *cpu;
197
198 if (kvm_enabled()) {
199 CPU_FOREACH(cpu) {
200 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
201 }
202 }
203 }
204
205 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
206 {
207 struct kvm_cpuid2 *cpuid;
208 int r, size;
209
210 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
211 cpuid = g_malloc0(size);
212 cpuid->nent = max;
213 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
214 if (r == 0 && cpuid->nent >= max) {
215 r = -E2BIG;
216 }
217 if (r < 0) {
218 if (r == -E2BIG) {
219 g_free(cpuid);
220 return NULL;
221 } else {
222 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
223 strerror(-r));
224 exit(1);
225 }
226 }
227 return cpuid;
228 }
229
230 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
231 * for all entries.
232 */
233 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
234 {
235 struct kvm_cpuid2 *cpuid;
236 int max = 1;
237
238 if (cpuid_cache != NULL) {
239 return cpuid_cache;
240 }
241 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
242 max *= 2;
243 }
244 cpuid_cache = cpuid;
245 return cpuid;
246 }
247
248 static const struct kvm_para_features {
249 int cap;
250 int feature;
251 } para_features[] = {
252 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
253 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
254 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
255 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
256 };
257
258 static int get_para_features(KVMState *s)
259 {
260 int i, features = 0;
261
262 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
263 if (kvm_check_extension(s, para_features[i].cap)) {
264 features |= (1 << para_features[i].feature);
265 }
266 }
267
268 return features;
269 }
270
271 static bool host_tsx_blacklisted(void)
272 {
273 int family, model, stepping;\
274 char vendor[CPUID_VENDOR_SZ + 1];
275
276 host_vendor_fms(vendor, &family, &model, &stepping);
277
278 /* Check if we are running on a Haswell host known to have broken TSX */
279 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
280 (family == 6) &&
281 ((model == 63 && stepping < 4) ||
282 model == 60 || model == 69 || model == 70);
283 }
284
285 /* Returns the value for a specific register on the cpuid entry
286 */
287 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
288 {
289 uint32_t ret = 0;
290 switch (reg) {
291 case R_EAX:
292 ret = entry->eax;
293 break;
294 case R_EBX:
295 ret = entry->ebx;
296 break;
297 case R_ECX:
298 ret = entry->ecx;
299 break;
300 case R_EDX:
301 ret = entry->edx;
302 break;
303 }
304 return ret;
305 }
306
307 /* Find matching entry for function/index on kvm_cpuid2 struct
308 */
309 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
310 uint32_t function,
311 uint32_t index)
312 {
313 int i;
314 for (i = 0; i < cpuid->nent; ++i) {
315 if (cpuid->entries[i].function == function &&
316 cpuid->entries[i].index == index) {
317 return &cpuid->entries[i];
318 }
319 }
320 /* not found: */
321 return NULL;
322 }
323
324 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
325 uint32_t index, int reg)
326 {
327 struct kvm_cpuid2 *cpuid;
328 uint32_t ret = 0;
329 uint32_t cpuid_1_edx;
330 bool found = false;
331
332 cpuid = get_supported_cpuid(s);
333
334 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
335 if (entry) {
336 found = true;
337 ret = cpuid_entry_get_reg(entry, reg);
338 }
339
340 /* Fixups for the data returned by KVM, below */
341
342 if (function == 1 && reg == R_EDX) {
343 /* KVM before 2.6.30 misreports the following features */
344 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
345 } else if (function == 1 && reg == R_ECX) {
346 /* We can set the hypervisor flag, even if KVM does not return it on
347 * GET_SUPPORTED_CPUID
348 */
349 ret |= CPUID_EXT_HYPERVISOR;
350 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
351 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
352 * and the irqchip is in the kernel.
353 */
354 if (kvm_irqchip_in_kernel() &&
355 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
356 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
357 }
358
359 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
360 * without the in-kernel irqchip
361 */
362 if (!kvm_irqchip_in_kernel()) {
363 ret &= ~CPUID_EXT_X2APIC;
364 }
365 } else if (function == 6 && reg == R_EAX) {
366 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
367 } else if (function == 7 && index == 0 && reg == R_EBX) {
368 if (host_tsx_blacklisted()) {
369 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
370 }
371 } else if (function == 0x80000001 && reg == R_EDX) {
372 /* On Intel, kvm returns cpuid according to the Intel spec,
373 * so add missing bits according to the AMD spec:
374 */
375 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
376 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
377 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
378 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
379 * be enabled without the in-kernel irqchip
380 */
381 if (!kvm_irqchip_in_kernel()) {
382 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
383 }
384 }
385
386 /* fallback for older kernels */
387 if ((function == KVM_CPUID_FEATURES) && !found) {
388 ret = get_para_features(s);
389 }
390
391 return ret;
392 }
393
394 typedef struct HWPoisonPage {
395 ram_addr_t ram_addr;
396 QLIST_ENTRY(HWPoisonPage) list;
397 } HWPoisonPage;
398
399 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
400 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
401
402 static void kvm_unpoison_all(void *param)
403 {
404 HWPoisonPage *page, *next_page;
405
406 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
407 QLIST_REMOVE(page, list);
408 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
409 g_free(page);
410 }
411 }
412
413 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
414 {
415 HWPoisonPage *page;
416
417 QLIST_FOREACH(page, &hwpoison_page_list, list) {
418 if (page->ram_addr == ram_addr) {
419 return;
420 }
421 }
422 page = g_new(HWPoisonPage, 1);
423 page->ram_addr = ram_addr;
424 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
425 }
426
427 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
428 int *max_banks)
429 {
430 int r;
431
432 r = kvm_check_extension(s, KVM_CAP_MCE);
433 if (r > 0) {
434 *max_banks = r;
435 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
436 }
437 return -ENOSYS;
438 }
439
440 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
441 {
442 CPUState *cs = CPU(cpu);
443 CPUX86State *env = &cpu->env;
444 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
445 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
446 uint64_t mcg_status = MCG_STATUS_MCIP;
447 int flags = 0;
448
449 if (code == BUS_MCEERR_AR) {
450 status |= MCI_STATUS_AR | 0x134;
451 mcg_status |= MCG_STATUS_EIPV;
452 } else {
453 status |= 0xc0;
454 mcg_status |= MCG_STATUS_RIPV;
455 }
456
457 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
458 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
459 * guest kernel back into env->mcg_ext_ctl.
460 */
461 cpu_synchronize_state(cs);
462 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
463 mcg_status |= MCG_STATUS_LMCE;
464 flags = 0;
465 }
466
467 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
468 (MCM_ADDR_PHYS << 6) | 0xc, flags);
469 }
470
471 static void hardware_memory_error(void)
472 {
473 fprintf(stderr, "Hardware memory error!\n");
474 exit(1);
475 }
476
477 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
478 {
479 X86CPU *cpu = X86_CPU(c);
480 CPUX86State *env = &cpu->env;
481 ram_addr_t ram_addr;
482 hwaddr paddr;
483
484 /* If we get an action required MCE, it has been injected by KVM
485 * while the VM was running. An action optional MCE instead should
486 * be coming from the main thread, which qemu_init_sigbus identifies
487 * as the "early kill" thread.
488 */
489 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
490
491 if ((env->mcg_cap & MCG_SER_P) && addr) {
492 ram_addr = qemu_ram_addr_from_host(addr);
493 if (ram_addr != RAM_ADDR_INVALID &&
494 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
495 kvm_hwpoison_page_add(ram_addr);
496 kvm_mce_inject(cpu, paddr, code);
497 return;
498 }
499
500 fprintf(stderr, "Hardware memory error for memory used by "
501 "QEMU itself instead of guest system!\n");
502 }
503
504 if (code == BUS_MCEERR_AR) {
505 hardware_memory_error();
506 }
507
508 /* Hope we are lucky for AO MCE */
509 }
510
511 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
512 {
513 CPUX86State *env = &cpu->env;
514
515 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
516 unsigned int bank, bank_num = env->mcg_cap & 0xff;
517 struct kvm_x86_mce mce;
518
519 env->exception_injected = -1;
520
521 /*
522 * There must be at least one bank in use if an MCE is pending.
523 * Find it and use its values for the event injection.
524 */
525 for (bank = 0; bank < bank_num; bank++) {
526 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
527 break;
528 }
529 }
530 assert(bank < bank_num);
531
532 mce.bank = bank;
533 mce.status = env->mce_banks[bank * 4 + 1];
534 mce.mcg_status = env->mcg_status;
535 mce.addr = env->mce_banks[bank * 4 + 2];
536 mce.misc = env->mce_banks[bank * 4 + 3];
537
538 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
539 }
540 return 0;
541 }
542
543 static void cpu_update_state(void *opaque, int running, RunState state)
544 {
545 CPUX86State *env = opaque;
546
547 if (running) {
548 env->tsc_valid = false;
549 }
550 }
551
552 unsigned long kvm_arch_vcpu_id(CPUState *cs)
553 {
554 X86CPU *cpu = X86_CPU(cs);
555 return cpu->apic_id;
556 }
557
558 #ifndef KVM_CPUID_SIGNATURE_NEXT
559 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
560 #endif
561
562 static bool hyperv_hypercall_available(X86CPU *cpu)
563 {
564 return cpu->hyperv_vapic ||
565 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
566 }
567
568 static bool hyperv_enabled(X86CPU *cpu)
569 {
570 CPUState *cs = CPU(cpu);
571 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
572 (hyperv_hypercall_available(cpu) ||
573 cpu->hyperv_time ||
574 cpu->hyperv_relaxed_timing ||
575 cpu->hyperv_crash ||
576 cpu->hyperv_reset ||
577 cpu->hyperv_vpindex ||
578 cpu->hyperv_runtime ||
579 cpu->hyperv_synic ||
580 cpu->hyperv_stimer);
581 }
582
583 static int kvm_arch_set_tsc_khz(CPUState *cs)
584 {
585 X86CPU *cpu = X86_CPU(cs);
586 CPUX86State *env = &cpu->env;
587 int r;
588
589 if (!env->tsc_khz) {
590 return 0;
591 }
592
593 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
594 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
595 -ENOTSUP;
596 if (r < 0) {
597 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
598 * TSC frequency doesn't match the one we want.
599 */
600 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
601 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
602 -ENOTSUP;
603 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
604 warn_report("TSC frequency mismatch between "
605 "VM (%" PRId64 " kHz) and host (%d kHz), "
606 "and TSC scaling unavailable",
607 env->tsc_khz, cur_freq);
608 return r;
609 }
610 }
611
612 return 0;
613 }
614
615 static bool tsc_is_stable_and_known(CPUX86State *env)
616 {
617 if (!env->tsc_khz) {
618 return false;
619 }
620 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
621 || env->user_tsc_khz;
622 }
623
624 static int hyperv_handle_properties(CPUState *cs)
625 {
626 X86CPU *cpu = X86_CPU(cs);
627 CPUX86State *env = &cpu->env;
628
629 if (cpu->hyperv_time &&
630 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
631 cpu->hyperv_time = false;
632 }
633
634 if (cpu->hyperv_relaxed_timing) {
635 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
636 }
637 if (cpu->hyperv_vapic) {
638 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
639 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
640 }
641 if (cpu->hyperv_time) {
642 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
643 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
644 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
645
646 if (has_msr_hv_frequencies && tsc_is_stable_and_known(env)) {
647 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
648 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
649 }
650 }
651 if (cpu->hyperv_crash && has_msr_hv_crash) {
652 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
653 }
654 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
655 if (cpu->hyperv_reset && has_msr_hv_reset) {
656 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
657 }
658 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
659 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
660 }
661 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
662 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
663 }
664 if (cpu->hyperv_synic) {
665 int sint;
666
667 if (!has_msr_hv_synic ||
668 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
669 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
670 return -ENOSYS;
671 }
672
673 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
674 env->msr_hv_synic_version = HV_SYNIC_VERSION;
675 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
676 env->msr_hv_synic_sint[sint] = HV_SINT_MASKED;
677 }
678 }
679 if (cpu->hyperv_stimer) {
680 if (!has_msr_hv_stimer) {
681 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
682 return -ENOSYS;
683 }
684 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
685 }
686 return 0;
687 }
688
689 static Error *invtsc_mig_blocker;
690
691 #define KVM_MAX_CPUID_ENTRIES 100
692
693 int kvm_arch_init_vcpu(CPUState *cs)
694 {
695 struct {
696 struct kvm_cpuid2 cpuid;
697 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
698 } QEMU_PACKED cpuid_data;
699 X86CPU *cpu = X86_CPU(cs);
700 CPUX86State *env = &cpu->env;
701 uint32_t limit, i, j, cpuid_i;
702 uint32_t unused;
703 struct kvm_cpuid_entry2 *c;
704 uint32_t signature[3];
705 int kvm_base = KVM_CPUID_SIGNATURE;
706 int r;
707 Error *local_err = NULL;
708
709 memset(&cpuid_data, 0, sizeof(cpuid_data));
710
711 cpuid_i = 0;
712
713 r = kvm_arch_set_tsc_khz(cs);
714 if (r < 0) {
715 goto fail;
716 }
717
718 /* vcpu's TSC frequency is either specified by user, or following
719 * the value used by KVM if the former is not present. In the
720 * latter case, we query it from KVM and record in env->tsc_khz,
721 * so that vcpu's TSC frequency can be migrated later via this field.
722 */
723 if (!env->tsc_khz) {
724 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
725 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
726 -ENOTSUP;
727 if (r > 0) {
728 env->tsc_khz = r;
729 }
730 }
731
732 /* Paravirtualization CPUIDs */
733 if (hyperv_enabled(cpu)) {
734 c = &cpuid_data.entries[cpuid_i++];
735 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
736 if (!cpu->hyperv_vendor_id) {
737 memcpy(signature, "Microsoft Hv", 12);
738 } else {
739 size_t len = strlen(cpu->hyperv_vendor_id);
740
741 if (len > 12) {
742 error_report("hv-vendor-id truncated to 12 characters");
743 len = 12;
744 }
745 memset(signature, 0, 12);
746 memcpy(signature, cpu->hyperv_vendor_id, len);
747 }
748 c->eax = HV_CPUID_MIN;
749 c->ebx = signature[0];
750 c->ecx = signature[1];
751 c->edx = signature[2];
752
753 c = &cpuid_data.entries[cpuid_i++];
754 c->function = HV_CPUID_INTERFACE;
755 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
756 c->eax = signature[0];
757 c->ebx = 0;
758 c->ecx = 0;
759 c->edx = 0;
760
761 c = &cpuid_data.entries[cpuid_i++];
762 c->function = HV_CPUID_VERSION;
763 c->eax = 0x00001bbc;
764 c->ebx = 0x00060001;
765
766 c = &cpuid_data.entries[cpuid_i++];
767 c->function = HV_CPUID_FEATURES;
768 r = hyperv_handle_properties(cs);
769 if (r) {
770 return r;
771 }
772 c->eax = env->features[FEAT_HYPERV_EAX];
773 c->ebx = env->features[FEAT_HYPERV_EBX];
774 c->edx = env->features[FEAT_HYPERV_EDX];
775
776 c = &cpuid_data.entries[cpuid_i++];
777 c->function = HV_CPUID_ENLIGHTMENT_INFO;
778 if (cpu->hyperv_relaxed_timing) {
779 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
780 }
781 if (cpu->hyperv_vapic) {
782 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
783 }
784 c->ebx = cpu->hyperv_spinlock_attempts;
785
786 c = &cpuid_data.entries[cpuid_i++];
787 c->function = HV_CPUID_IMPLEMENT_LIMITS;
788
789 c->eax = cpu->hv_max_vps;
790 c->ebx = 0x40;
791
792 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
793 has_msr_hv_hypercall = true;
794 }
795
796 if (cpu->expose_kvm) {
797 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
798 c = &cpuid_data.entries[cpuid_i++];
799 c->function = KVM_CPUID_SIGNATURE | kvm_base;
800 c->eax = KVM_CPUID_FEATURES | kvm_base;
801 c->ebx = signature[0];
802 c->ecx = signature[1];
803 c->edx = signature[2];
804
805 c = &cpuid_data.entries[cpuid_i++];
806 c->function = KVM_CPUID_FEATURES | kvm_base;
807 c->eax = env->features[FEAT_KVM];
808 }
809
810 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
811
812 for (i = 0; i <= limit; i++) {
813 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
814 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
815 abort();
816 }
817 c = &cpuid_data.entries[cpuid_i++];
818
819 switch (i) {
820 case 2: {
821 /* Keep reading function 2 till all the input is received */
822 int times;
823
824 c->function = i;
825 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
826 KVM_CPUID_FLAG_STATE_READ_NEXT;
827 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
828 times = c->eax & 0xff;
829
830 for (j = 1; j < times; ++j) {
831 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
832 fprintf(stderr, "cpuid_data is full, no space for "
833 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
834 abort();
835 }
836 c = &cpuid_data.entries[cpuid_i++];
837 c->function = i;
838 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
839 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
840 }
841 break;
842 }
843 case 4:
844 case 0xb:
845 case 0xd:
846 for (j = 0; ; j++) {
847 if (i == 0xd && j == 64) {
848 break;
849 }
850 c->function = i;
851 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
852 c->index = j;
853 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
854
855 if (i == 4 && c->eax == 0) {
856 break;
857 }
858 if (i == 0xb && !(c->ecx & 0xff00)) {
859 break;
860 }
861 if (i == 0xd && c->eax == 0) {
862 continue;
863 }
864 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
865 fprintf(stderr, "cpuid_data is full, no space for "
866 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
867 abort();
868 }
869 c = &cpuid_data.entries[cpuid_i++];
870 }
871 break;
872 default:
873 c->function = i;
874 c->flags = 0;
875 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
876 break;
877 }
878 }
879
880 if (limit >= 0x0a) {
881 uint32_t ver;
882
883 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
884 if ((ver & 0xff) > 0) {
885 has_msr_architectural_pmu = true;
886 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
887
888 /* Shouldn't be more than 32, since that's the number of bits
889 * available in EBX to tell us _which_ counters are available.
890 * Play it safe.
891 */
892 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
893 num_architectural_pmu_counters = MAX_GP_COUNTERS;
894 }
895 }
896 }
897
898 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
899
900 for (i = 0x80000000; i <= limit; i++) {
901 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
902 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
903 abort();
904 }
905 c = &cpuid_data.entries[cpuid_i++];
906
907 c->function = i;
908 c->flags = 0;
909 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
910 }
911
912 /* Call Centaur's CPUID instructions they are supported. */
913 if (env->cpuid_xlevel2 > 0) {
914 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
915
916 for (i = 0xC0000000; i <= limit; i++) {
917 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
918 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
919 abort();
920 }
921 c = &cpuid_data.entries[cpuid_i++];
922
923 c->function = i;
924 c->flags = 0;
925 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
926 }
927 }
928
929 cpuid_data.cpuid.nent = cpuid_i;
930
931 if (((env->cpuid_version >> 8)&0xF) >= 6
932 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
933 (CPUID_MCE | CPUID_MCA)
934 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
935 uint64_t mcg_cap, unsupported_caps;
936 int banks;
937 int ret;
938
939 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
940 if (ret < 0) {
941 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
942 return ret;
943 }
944
945 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
946 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
947 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
948 return -ENOTSUP;
949 }
950
951 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
952 if (unsupported_caps) {
953 if (unsupported_caps & MCG_LMCE_P) {
954 error_report("kvm: LMCE not supported");
955 return -ENOTSUP;
956 }
957 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
958 unsupported_caps);
959 }
960
961 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
962 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
963 if (ret < 0) {
964 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
965 return ret;
966 }
967 }
968
969 qemu_add_vm_change_state_handler(cpu_update_state, env);
970
971 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
972 if (c) {
973 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
974 !!(c->ecx & CPUID_EXT_SMX);
975 }
976
977 if (env->mcg_cap & MCG_LMCE_P) {
978 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
979 }
980
981 if (!env->user_tsc_khz) {
982 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
983 invtsc_mig_blocker == NULL) {
984 /* for migration */
985 error_setg(&invtsc_mig_blocker,
986 "State blocked by non-migratable CPU device"
987 " (invtsc flag)");
988 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
989 if (local_err) {
990 error_report_err(local_err);
991 error_free(invtsc_mig_blocker);
992 goto fail;
993 }
994 /* for savevm */
995 vmstate_x86_cpu.unmigratable = 1;
996 }
997 }
998
999 if (cpu->vmware_cpuid_freq
1000 /* Guests depend on 0x40000000 to detect this feature, so only expose
1001 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1002 && cpu->expose_kvm
1003 && kvm_base == KVM_CPUID_SIGNATURE
1004 /* TSC clock must be stable and known for this feature. */
1005 && tsc_is_stable_and_known(env)) {
1006
1007 c = &cpuid_data.entries[cpuid_i++];
1008 c->function = KVM_CPUID_SIGNATURE | 0x10;
1009 c->eax = env->tsc_khz;
1010 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1011 * APIC_BUS_CYCLE_NS */
1012 c->ebx = 1000000;
1013 c->ecx = c->edx = 0;
1014
1015 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1016 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1017 }
1018
1019 cpuid_data.cpuid.nent = cpuid_i;
1020
1021 cpuid_data.cpuid.padding = 0;
1022 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1023 if (r) {
1024 goto fail;
1025 }
1026
1027 if (has_xsave) {
1028 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1029 }
1030 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1031
1032 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1033 has_msr_tsc_aux = false;
1034 }
1035
1036 return 0;
1037
1038 fail:
1039 migrate_del_blocker(invtsc_mig_blocker);
1040 return r;
1041 }
1042
1043 void kvm_arch_reset_vcpu(X86CPU *cpu)
1044 {
1045 CPUX86State *env = &cpu->env;
1046
1047 env->exception_injected = -1;
1048 env->interrupt_injected = -1;
1049 env->xcr0 = 1;
1050 if (kvm_irqchip_in_kernel()) {
1051 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1052 KVM_MP_STATE_UNINITIALIZED;
1053 } else {
1054 env->mp_state = KVM_MP_STATE_RUNNABLE;
1055 }
1056 }
1057
1058 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1059 {
1060 CPUX86State *env = &cpu->env;
1061
1062 /* APs get directly into wait-for-SIPI state. */
1063 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1064 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1065 }
1066 }
1067
1068 static int kvm_get_supported_msrs(KVMState *s)
1069 {
1070 static int kvm_supported_msrs;
1071 int ret = 0;
1072
1073 /* first time */
1074 if (kvm_supported_msrs == 0) {
1075 struct kvm_msr_list msr_list, *kvm_msr_list;
1076
1077 kvm_supported_msrs = -1;
1078
1079 /* Obtain MSR list from KVM. These are the MSRs that we must
1080 * save/restore */
1081 msr_list.nmsrs = 0;
1082 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1083 if (ret < 0 && ret != -E2BIG) {
1084 return ret;
1085 }
1086 /* Old kernel modules had a bug and could write beyond the provided
1087 memory. Allocate at least a safe amount of 1K. */
1088 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1089 msr_list.nmsrs *
1090 sizeof(msr_list.indices[0])));
1091
1092 kvm_msr_list->nmsrs = msr_list.nmsrs;
1093 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1094 if (ret >= 0) {
1095 int i;
1096
1097 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1098 switch (kvm_msr_list->indices[i]) {
1099 case MSR_STAR:
1100 has_msr_star = true;
1101 break;
1102 case MSR_VM_HSAVE_PA:
1103 has_msr_hsave_pa = true;
1104 break;
1105 case MSR_TSC_AUX:
1106 has_msr_tsc_aux = true;
1107 break;
1108 case MSR_TSC_ADJUST:
1109 has_msr_tsc_adjust = true;
1110 break;
1111 case MSR_IA32_TSCDEADLINE:
1112 has_msr_tsc_deadline = true;
1113 break;
1114 case MSR_IA32_SMBASE:
1115 has_msr_smbase = true;
1116 break;
1117 case MSR_IA32_MISC_ENABLE:
1118 has_msr_misc_enable = true;
1119 break;
1120 case MSR_IA32_BNDCFGS:
1121 has_msr_bndcfgs = true;
1122 break;
1123 case MSR_IA32_XSS:
1124 has_msr_xss = true;
1125 break;;
1126 case HV_X64_MSR_CRASH_CTL:
1127 has_msr_hv_crash = true;
1128 break;
1129 case HV_X64_MSR_RESET:
1130 has_msr_hv_reset = true;
1131 break;
1132 case HV_X64_MSR_VP_INDEX:
1133 has_msr_hv_vpindex = true;
1134 break;
1135 case HV_X64_MSR_VP_RUNTIME:
1136 has_msr_hv_runtime = true;
1137 break;
1138 case HV_X64_MSR_SCONTROL:
1139 has_msr_hv_synic = true;
1140 break;
1141 case HV_X64_MSR_STIMER0_CONFIG:
1142 has_msr_hv_stimer = true;
1143 break;
1144 case HV_X64_MSR_TSC_FREQUENCY:
1145 has_msr_hv_frequencies = true;
1146 break;
1147 }
1148 }
1149 }
1150
1151 g_free(kvm_msr_list);
1152 }
1153
1154 return ret;
1155 }
1156
1157 static Notifier smram_machine_done;
1158 static KVMMemoryListener smram_listener;
1159 static AddressSpace smram_address_space;
1160 static MemoryRegion smram_as_root;
1161 static MemoryRegion smram_as_mem;
1162
1163 static void register_smram_listener(Notifier *n, void *unused)
1164 {
1165 MemoryRegion *smram =
1166 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1167
1168 /* Outer container... */
1169 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1170 memory_region_set_enabled(&smram_as_root, true);
1171
1172 /* ... with two regions inside: normal system memory with low
1173 * priority, and...
1174 */
1175 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1176 get_system_memory(), 0, ~0ull);
1177 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1178 memory_region_set_enabled(&smram_as_mem, true);
1179
1180 if (smram) {
1181 /* ... SMRAM with higher priority */
1182 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1183 memory_region_set_enabled(smram, true);
1184 }
1185
1186 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1187 kvm_memory_listener_register(kvm_state, &smram_listener,
1188 &smram_address_space, 1);
1189 }
1190
1191 int kvm_arch_init(MachineState *ms, KVMState *s)
1192 {
1193 uint64_t identity_base = 0xfffbc000;
1194 uint64_t shadow_mem;
1195 int ret;
1196 struct utsname utsname;
1197
1198 #ifdef KVM_CAP_XSAVE
1199 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1200 #endif
1201
1202 #ifdef KVM_CAP_XCRS
1203 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1204 #endif
1205
1206 #ifdef KVM_CAP_PIT_STATE2
1207 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1208 #endif
1209
1210 ret = kvm_get_supported_msrs(s);
1211 if (ret < 0) {
1212 return ret;
1213 }
1214
1215 uname(&utsname);
1216 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1217
1218 /*
1219 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1220 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1221 * Since these must be part of guest physical memory, we need to allocate
1222 * them, both by setting their start addresses in the kernel and by
1223 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1224 *
1225 * Older KVM versions may not support setting the identity map base. In
1226 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1227 * size.
1228 */
1229 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1230 /* Allows up to 16M BIOSes. */
1231 identity_base = 0xfeffc000;
1232
1233 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1234 if (ret < 0) {
1235 return ret;
1236 }
1237 }
1238
1239 /* Set TSS base one page after EPT identity map. */
1240 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1241 if (ret < 0) {
1242 return ret;
1243 }
1244
1245 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1246 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1247 if (ret < 0) {
1248 fprintf(stderr, "e820_add_entry() table is full\n");
1249 return ret;
1250 }
1251 qemu_register_reset(kvm_unpoison_all, NULL);
1252
1253 shadow_mem = machine_kvm_shadow_mem(ms);
1254 if (shadow_mem != -1) {
1255 shadow_mem /= 4096;
1256 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1257 if (ret < 0) {
1258 return ret;
1259 }
1260 }
1261
1262 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1263 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1264 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1265 smram_machine_done.notify = register_smram_listener;
1266 qemu_add_machine_init_done_notifier(&smram_machine_done);
1267 }
1268 return 0;
1269 }
1270
1271 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1272 {
1273 lhs->selector = rhs->selector;
1274 lhs->base = rhs->base;
1275 lhs->limit = rhs->limit;
1276 lhs->type = 3;
1277 lhs->present = 1;
1278 lhs->dpl = 3;
1279 lhs->db = 0;
1280 lhs->s = 1;
1281 lhs->l = 0;
1282 lhs->g = 0;
1283 lhs->avl = 0;
1284 lhs->unusable = 0;
1285 }
1286
1287 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1288 {
1289 unsigned flags = rhs->flags;
1290 lhs->selector = rhs->selector;
1291 lhs->base = rhs->base;
1292 lhs->limit = rhs->limit;
1293 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1294 lhs->present = (flags & DESC_P_MASK) != 0;
1295 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1296 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1297 lhs->s = (flags & DESC_S_MASK) != 0;
1298 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1299 lhs->g = (flags & DESC_G_MASK) != 0;
1300 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1301 lhs->unusable = !lhs->present;
1302 lhs->padding = 0;
1303 }
1304
1305 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1306 {
1307 lhs->selector = rhs->selector;
1308 lhs->base = rhs->base;
1309 lhs->limit = rhs->limit;
1310 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1311 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1312 (rhs->dpl << DESC_DPL_SHIFT) |
1313 (rhs->db << DESC_B_SHIFT) |
1314 (rhs->s * DESC_S_MASK) |
1315 (rhs->l << DESC_L_SHIFT) |
1316 (rhs->g * DESC_G_MASK) |
1317 (rhs->avl * DESC_AVL_MASK);
1318 }
1319
1320 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1321 {
1322 if (set) {
1323 *kvm_reg = *qemu_reg;
1324 } else {
1325 *qemu_reg = *kvm_reg;
1326 }
1327 }
1328
1329 static int kvm_getput_regs(X86CPU *cpu, int set)
1330 {
1331 CPUX86State *env = &cpu->env;
1332 struct kvm_regs regs;
1333 int ret = 0;
1334
1335 if (!set) {
1336 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1337 if (ret < 0) {
1338 return ret;
1339 }
1340 }
1341
1342 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1343 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1344 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1345 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1346 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1347 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1348 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1349 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1350 #ifdef TARGET_X86_64
1351 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1352 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1353 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1354 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1355 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1356 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1357 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1358 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1359 #endif
1360
1361 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1362 kvm_getput_reg(&regs.rip, &env->eip, set);
1363
1364 if (set) {
1365 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1366 }
1367
1368 return ret;
1369 }
1370
1371 static int kvm_put_fpu(X86CPU *cpu)
1372 {
1373 CPUX86State *env = &cpu->env;
1374 struct kvm_fpu fpu;
1375 int i;
1376
1377 memset(&fpu, 0, sizeof fpu);
1378 fpu.fsw = env->fpus & ~(7 << 11);
1379 fpu.fsw |= (env->fpstt & 7) << 11;
1380 fpu.fcw = env->fpuc;
1381 fpu.last_opcode = env->fpop;
1382 fpu.last_ip = env->fpip;
1383 fpu.last_dp = env->fpdp;
1384 for (i = 0; i < 8; ++i) {
1385 fpu.ftwx |= (!env->fptags[i]) << i;
1386 }
1387 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1388 for (i = 0; i < CPU_NB_REGS; i++) {
1389 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1390 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1391 }
1392 fpu.mxcsr = env->mxcsr;
1393
1394 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1395 }
1396
1397 #define XSAVE_FCW_FSW 0
1398 #define XSAVE_FTW_FOP 1
1399 #define XSAVE_CWD_RIP 2
1400 #define XSAVE_CWD_RDP 4
1401 #define XSAVE_MXCSR 6
1402 #define XSAVE_ST_SPACE 8
1403 #define XSAVE_XMM_SPACE 40
1404 #define XSAVE_XSTATE_BV 128
1405 #define XSAVE_YMMH_SPACE 144
1406 #define XSAVE_BNDREGS 240
1407 #define XSAVE_BNDCSR 256
1408 #define XSAVE_OPMASK 272
1409 #define XSAVE_ZMM_Hi256 288
1410 #define XSAVE_Hi16_ZMM 416
1411 #define XSAVE_PKRU 672
1412
1413 #define XSAVE_BYTE_OFFSET(word_offset) \
1414 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1415
1416 #define ASSERT_OFFSET(word_offset, field) \
1417 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1418 offsetof(X86XSaveArea, field))
1419
1420 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1421 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1422 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1423 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1424 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1425 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1426 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1427 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1428 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1429 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1430 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1431 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1432 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1433 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1434 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1435
1436 static int kvm_put_xsave(X86CPU *cpu)
1437 {
1438 CPUX86State *env = &cpu->env;
1439 X86XSaveArea *xsave = env->kvm_xsave_buf;
1440
1441 if (!has_xsave) {
1442 return kvm_put_fpu(cpu);
1443 }
1444 x86_cpu_xsave_all_areas(cpu, xsave);
1445
1446 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1447 }
1448
1449 static int kvm_put_xcrs(X86CPU *cpu)
1450 {
1451 CPUX86State *env = &cpu->env;
1452 struct kvm_xcrs xcrs = {};
1453
1454 if (!has_xcrs) {
1455 return 0;
1456 }
1457
1458 xcrs.nr_xcrs = 1;
1459 xcrs.flags = 0;
1460 xcrs.xcrs[0].xcr = 0;
1461 xcrs.xcrs[0].value = env->xcr0;
1462 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1463 }
1464
1465 static int kvm_put_sregs(X86CPU *cpu)
1466 {
1467 CPUX86State *env = &cpu->env;
1468 struct kvm_sregs sregs;
1469
1470 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1471 if (env->interrupt_injected >= 0) {
1472 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1473 (uint64_t)1 << (env->interrupt_injected % 64);
1474 }
1475
1476 if ((env->eflags & VM_MASK)) {
1477 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1478 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1479 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1480 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1481 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1482 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1483 } else {
1484 set_seg(&sregs.cs, &env->segs[R_CS]);
1485 set_seg(&sregs.ds, &env->segs[R_DS]);
1486 set_seg(&sregs.es, &env->segs[R_ES]);
1487 set_seg(&sregs.fs, &env->segs[R_FS]);
1488 set_seg(&sregs.gs, &env->segs[R_GS]);
1489 set_seg(&sregs.ss, &env->segs[R_SS]);
1490 }
1491
1492 set_seg(&sregs.tr, &env->tr);
1493 set_seg(&sregs.ldt, &env->ldt);
1494
1495 sregs.idt.limit = env->idt.limit;
1496 sregs.idt.base = env->idt.base;
1497 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1498 sregs.gdt.limit = env->gdt.limit;
1499 sregs.gdt.base = env->gdt.base;
1500 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1501
1502 sregs.cr0 = env->cr[0];
1503 sregs.cr2 = env->cr[2];
1504 sregs.cr3 = env->cr[3];
1505 sregs.cr4 = env->cr[4];
1506
1507 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1508 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1509
1510 sregs.efer = env->efer;
1511
1512 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1513 }
1514
1515 static void kvm_msr_buf_reset(X86CPU *cpu)
1516 {
1517 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1518 }
1519
1520 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1521 {
1522 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1523 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1524 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1525
1526 assert((void *)(entry + 1) <= limit);
1527
1528 entry->index = index;
1529 entry->reserved = 0;
1530 entry->data = value;
1531 msrs->nmsrs++;
1532 }
1533
1534 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1535 {
1536 kvm_msr_buf_reset(cpu);
1537 kvm_msr_entry_add(cpu, index, value);
1538
1539 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1540 }
1541
1542 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1543 {
1544 int ret;
1545
1546 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1547 assert(ret == 1);
1548 }
1549
1550 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1551 {
1552 CPUX86State *env = &cpu->env;
1553 int ret;
1554
1555 if (!has_msr_tsc_deadline) {
1556 return 0;
1557 }
1558
1559 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1560 if (ret < 0) {
1561 return ret;
1562 }
1563
1564 assert(ret == 1);
1565 return 0;
1566 }
1567
1568 /*
1569 * Provide a separate write service for the feature control MSR in order to
1570 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1571 * before writing any other state because forcibly leaving nested mode
1572 * invalidates the VCPU state.
1573 */
1574 static int kvm_put_msr_feature_control(X86CPU *cpu)
1575 {
1576 int ret;
1577
1578 if (!has_msr_feature_control) {
1579 return 0;
1580 }
1581
1582 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1583 cpu->env.msr_ia32_feature_control);
1584 if (ret < 0) {
1585 return ret;
1586 }
1587
1588 assert(ret == 1);
1589 return 0;
1590 }
1591
1592 static int kvm_put_msrs(X86CPU *cpu, int level)
1593 {
1594 CPUX86State *env = &cpu->env;
1595 int i;
1596 int ret;
1597
1598 kvm_msr_buf_reset(cpu);
1599
1600 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1601 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1602 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1603 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1604 if (has_msr_star) {
1605 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1606 }
1607 if (has_msr_hsave_pa) {
1608 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1609 }
1610 if (has_msr_tsc_aux) {
1611 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1612 }
1613 if (has_msr_tsc_adjust) {
1614 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1615 }
1616 if (has_msr_misc_enable) {
1617 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1618 env->msr_ia32_misc_enable);
1619 }
1620 if (has_msr_smbase) {
1621 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1622 }
1623 if (has_msr_bndcfgs) {
1624 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1625 }
1626 if (has_msr_xss) {
1627 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1628 }
1629 #ifdef TARGET_X86_64
1630 if (lm_capable_kernel) {
1631 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1632 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1633 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1634 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1635 }
1636 #endif
1637 /*
1638 * The following MSRs have side effects on the guest or are too heavy
1639 * for normal writeback. Limit them to reset or full state updates.
1640 */
1641 if (level >= KVM_PUT_RESET_STATE) {
1642 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1643 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1644 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1645 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1646 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1647 }
1648 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1649 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1650 }
1651 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1652 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1653 }
1654 if (has_msr_architectural_pmu) {
1655 /* Stop the counter. */
1656 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1657 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1658
1659 /* Set the counter values. */
1660 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1661 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1662 env->msr_fixed_counters[i]);
1663 }
1664 for (i = 0; i < num_architectural_pmu_counters; i++) {
1665 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1666 env->msr_gp_counters[i]);
1667 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1668 env->msr_gp_evtsel[i]);
1669 }
1670 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1671 env->msr_global_status);
1672 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1673 env->msr_global_ovf_ctrl);
1674
1675 /* Now start the PMU. */
1676 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1677 env->msr_fixed_ctr_ctrl);
1678 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1679 env->msr_global_ctrl);
1680 }
1681 if (has_msr_hv_hypercall) {
1682 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1683 env->msr_hv_guest_os_id);
1684 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1685 env->msr_hv_hypercall);
1686 }
1687 if (cpu->hyperv_vapic) {
1688 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1689 env->msr_hv_vapic);
1690 }
1691 if (cpu->hyperv_time) {
1692 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1693 }
1694 if (has_msr_hv_crash) {
1695 int j;
1696
1697 for (j = 0; j < HV_CRASH_PARAMS; j++)
1698 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1699 env->msr_hv_crash_params[j]);
1700
1701 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
1702 }
1703 if (has_msr_hv_runtime) {
1704 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1705 }
1706 if (cpu->hyperv_synic) {
1707 int j;
1708
1709 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1710 env->msr_hv_synic_control);
1711 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1712 env->msr_hv_synic_version);
1713 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1714 env->msr_hv_synic_evt_page);
1715 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1716 env->msr_hv_synic_msg_page);
1717
1718 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1719 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1720 env->msr_hv_synic_sint[j]);
1721 }
1722 }
1723 if (has_msr_hv_stimer) {
1724 int j;
1725
1726 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1727 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1728 env->msr_hv_stimer_config[j]);
1729 }
1730
1731 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1732 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1733 env->msr_hv_stimer_count[j]);
1734 }
1735 }
1736 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1737 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1738
1739 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1740 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1741 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1742 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1743 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1744 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1745 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1746 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1747 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1748 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1749 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1750 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1751 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1752 /* The CPU GPs if we write to a bit above the physical limit of
1753 * the host CPU (and KVM emulates that)
1754 */
1755 uint64_t mask = env->mtrr_var[i].mask;
1756 mask &= phys_mask;
1757
1758 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1759 env->mtrr_var[i].base);
1760 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1761 }
1762 }
1763
1764 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1765 * kvm_put_msr_feature_control. */
1766 }
1767 if (env->mcg_cap) {
1768 int i;
1769
1770 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1771 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1772 if (has_msr_mcg_ext_ctl) {
1773 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1774 }
1775 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1776 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1777 }
1778 }
1779
1780 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1781 if (ret < 0) {
1782 return ret;
1783 }
1784
1785 if (ret < cpu->kvm_msr_buf->nmsrs) {
1786 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1787 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1788 (uint32_t)e->index, (uint64_t)e->data);
1789 }
1790
1791 assert(ret == cpu->kvm_msr_buf->nmsrs);
1792 return 0;
1793 }
1794
1795
1796 static int kvm_get_fpu(X86CPU *cpu)
1797 {
1798 CPUX86State *env = &cpu->env;
1799 struct kvm_fpu fpu;
1800 int i, ret;
1801
1802 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1803 if (ret < 0) {
1804 return ret;
1805 }
1806
1807 env->fpstt = (fpu.fsw >> 11) & 7;
1808 env->fpus = fpu.fsw;
1809 env->fpuc = fpu.fcw;
1810 env->fpop = fpu.last_opcode;
1811 env->fpip = fpu.last_ip;
1812 env->fpdp = fpu.last_dp;
1813 for (i = 0; i < 8; ++i) {
1814 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1815 }
1816 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1817 for (i = 0; i < CPU_NB_REGS; i++) {
1818 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1819 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1820 }
1821 env->mxcsr = fpu.mxcsr;
1822
1823 return 0;
1824 }
1825
1826 static int kvm_get_xsave(X86CPU *cpu)
1827 {
1828 CPUX86State *env = &cpu->env;
1829 X86XSaveArea *xsave = env->kvm_xsave_buf;
1830 int ret;
1831
1832 if (!has_xsave) {
1833 return kvm_get_fpu(cpu);
1834 }
1835
1836 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1837 if (ret < 0) {
1838 return ret;
1839 }
1840 x86_cpu_xrstor_all_areas(cpu, xsave);
1841
1842 return 0;
1843 }
1844
1845 static int kvm_get_xcrs(X86CPU *cpu)
1846 {
1847 CPUX86State *env = &cpu->env;
1848 int i, ret;
1849 struct kvm_xcrs xcrs;
1850
1851 if (!has_xcrs) {
1852 return 0;
1853 }
1854
1855 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1856 if (ret < 0) {
1857 return ret;
1858 }
1859
1860 for (i = 0; i < xcrs.nr_xcrs; i++) {
1861 /* Only support xcr0 now */
1862 if (xcrs.xcrs[i].xcr == 0) {
1863 env->xcr0 = xcrs.xcrs[i].value;
1864 break;
1865 }
1866 }
1867 return 0;
1868 }
1869
1870 static int kvm_get_sregs(X86CPU *cpu)
1871 {
1872 CPUX86State *env = &cpu->env;
1873 struct kvm_sregs sregs;
1874 uint32_t hflags;
1875 int bit, i, ret;
1876
1877 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1878 if (ret < 0) {
1879 return ret;
1880 }
1881
1882 /* There can only be one pending IRQ set in the bitmap at a time, so try
1883 to find it and save its number instead (-1 for none). */
1884 env->interrupt_injected = -1;
1885 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1886 if (sregs.interrupt_bitmap[i]) {
1887 bit = ctz64(sregs.interrupt_bitmap[i]);
1888 env->interrupt_injected = i * 64 + bit;
1889 break;
1890 }
1891 }
1892
1893 get_seg(&env->segs[R_CS], &sregs.cs);
1894 get_seg(&env->segs[R_DS], &sregs.ds);
1895 get_seg(&env->segs[R_ES], &sregs.es);
1896 get_seg(&env->segs[R_FS], &sregs.fs);
1897 get_seg(&env->segs[R_GS], &sregs.gs);
1898 get_seg(&env->segs[R_SS], &sregs.ss);
1899
1900 get_seg(&env->tr, &sregs.tr);
1901 get_seg(&env->ldt, &sregs.ldt);
1902
1903 env->idt.limit = sregs.idt.limit;
1904 env->idt.base = sregs.idt.base;
1905 env->gdt.limit = sregs.gdt.limit;
1906 env->gdt.base = sregs.gdt.base;
1907
1908 env->cr[0] = sregs.cr0;
1909 env->cr[2] = sregs.cr2;
1910 env->cr[3] = sregs.cr3;
1911 env->cr[4] = sregs.cr4;
1912
1913 env->efer = sregs.efer;
1914
1915 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1916
1917 #define HFLAG_COPY_MASK \
1918 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1919 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1920 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1921 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1922
1923 hflags = env->hflags & HFLAG_COPY_MASK;
1924 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1925 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1926 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1927 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1928 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1929
1930 if (env->cr[4] & CR4_OSFXSR_MASK) {
1931 hflags |= HF_OSFXSR_MASK;
1932 }
1933
1934 if (env->efer & MSR_EFER_LMA) {
1935 hflags |= HF_LMA_MASK;
1936 }
1937
1938 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1939 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1940 } else {
1941 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1942 (DESC_B_SHIFT - HF_CS32_SHIFT);
1943 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1944 (DESC_B_SHIFT - HF_SS32_SHIFT);
1945 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1946 !(hflags & HF_CS32_MASK)) {
1947 hflags |= HF_ADDSEG_MASK;
1948 } else {
1949 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1950 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1951 }
1952 }
1953 env->hflags = hflags;
1954
1955 return 0;
1956 }
1957
1958 static int kvm_get_msrs(X86CPU *cpu)
1959 {
1960 CPUX86State *env = &cpu->env;
1961 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1962 int ret, i;
1963 uint64_t mtrr_top_bits;
1964
1965 kvm_msr_buf_reset(cpu);
1966
1967 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1968 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1969 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1970 kvm_msr_entry_add(cpu, MSR_PAT, 0);
1971 if (has_msr_star) {
1972 kvm_msr_entry_add(cpu, MSR_STAR, 0);
1973 }
1974 if (has_msr_hsave_pa) {
1975 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
1976 }
1977 if (has_msr_tsc_aux) {
1978 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
1979 }
1980 if (has_msr_tsc_adjust) {
1981 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
1982 }
1983 if (has_msr_tsc_deadline) {
1984 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
1985 }
1986 if (has_msr_misc_enable) {
1987 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
1988 }
1989 if (has_msr_smbase) {
1990 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
1991 }
1992 if (has_msr_feature_control) {
1993 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
1994 }
1995 if (has_msr_bndcfgs) {
1996 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
1997 }
1998 if (has_msr_xss) {
1999 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2000 }
2001
2002
2003 if (!env->tsc_valid) {
2004 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2005 env->tsc_valid = !runstate_is_running();
2006 }
2007
2008 #ifdef TARGET_X86_64
2009 if (lm_capable_kernel) {
2010 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2011 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2012 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2013 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2014 }
2015 #endif
2016 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2017 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2018 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2019 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2020 }
2021 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2022 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2023 }
2024 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2025 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2026 }
2027 if (has_msr_architectural_pmu) {
2028 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2029 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2030 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2031 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2032 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2033 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2034 }
2035 for (i = 0; i < num_architectural_pmu_counters; i++) {
2036 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2037 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2038 }
2039 }
2040
2041 if (env->mcg_cap) {
2042 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2043 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2044 if (has_msr_mcg_ext_ctl) {
2045 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2046 }
2047 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2048 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2049 }
2050 }
2051
2052 if (has_msr_hv_hypercall) {
2053 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2054 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2055 }
2056 if (cpu->hyperv_vapic) {
2057 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2058 }
2059 if (cpu->hyperv_time) {
2060 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2061 }
2062 if (has_msr_hv_crash) {
2063 int j;
2064
2065 for (j = 0; j < HV_CRASH_PARAMS; j++) {
2066 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2067 }
2068 }
2069 if (has_msr_hv_runtime) {
2070 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2071 }
2072 if (cpu->hyperv_synic) {
2073 uint32_t msr;
2074
2075 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2076 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2077 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2078 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2079 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2080 kvm_msr_entry_add(cpu, msr, 0);
2081 }
2082 }
2083 if (has_msr_hv_stimer) {
2084 uint32_t msr;
2085
2086 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2087 msr++) {
2088 kvm_msr_entry_add(cpu, msr, 0);
2089 }
2090 }
2091 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2092 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2093 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2094 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2095 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2096 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2097 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2098 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2099 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2100 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2101 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2102 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2103 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2104 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2105 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2106 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2107 }
2108 }
2109
2110 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2111 if (ret < 0) {
2112 return ret;
2113 }
2114
2115 if (ret < cpu->kvm_msr_buf->nmsrs) {
2116 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2117 error_report("error: failed to get MSR 0x%" PRIx32,
2118 (uint32_t)e->index);
2119 }
2120
2121 assert(ret == cpu->kvm_msr_buf->nmsrs);
2122 /*
2123 * MTRR masks: Each mask consists of 5 parts
2124 * a 10..0: must be zero
2125 * b 11 : valid bit
2126 * c n-1.12: actual mask bits
2127 * d 51..n: reserved must be zero
2128 * e 63.52: reserved must be zero
2129 *
2130 * 'n' is the number of physical bits supported by the CPU and is
2131 * apparently always <= 52. We know our 'n' but don't know what
2132 * the destinations 'n' is; it might be smaller, in which case
2133 * it masks (c) on loading. It might be larger, in which case
2134 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2135 * we're migrating to.
2136 */
2137
2138 if (cpu->fill_mtrr_mask) {
2139 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2140 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2141 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2142 } else {
2143 mtrr_top_bits = 0;
2144 }
2145
2146 for (i = 0; i < ret; i++) {
2147 uint32_t index = msrs[i].index;
2148 switch (index) {
2149 case MSR_IA32_SYSENTER_CS:
2150 env->sysenter_cs = msrs[i].data;
2151 break;
2152 case MSR_IA32_SYSENTER_ESP:
2153 env->sysenter_esp = msrs[i].data;
2154 break;
2155 case MSR_IA32_SYSENTER_EIP:
2156 env->sysenter_eip = msrs[i].data;
2157 break;
2158 case MSR_PAT:
2159 env->pat = msrs[i].data;
2160 break;
2161 case MSR_STAR:
2162 env->star = msrs[i].data;
2163 break;
2164 #ifdef TARGET_X86_64
2165 case MSR_CSTAR:
2166 env->cstar = msrs[i].data;
2167 break;
2168 case MSR_KERNELGSBASE:
2169 env->kernelgsbase = msrs[i].data;
2170 break;
2171 case MSR_FMASK:
2172 env->fmask = msrs[i].data;
2173 break;
2174 case MSR_LSTAR:
2175 env->lstar = msrs[i].data;
2176 break;
2177 #endif
2178 case MSR_IA32_TSC:
2179 env->tsc = msrs[i].data;
2180 break;
2181 case MSR_TSC_AUX:
2182 env->tsc_aux = msrs[i].data;
2183 break;
2184 case MSR_TSC_ADJUST:
2185 env->tsc_adjust = msrs[i].data;
2186 break;
2187 case MSR_IA32_TSCDEADLINE:
2188 env->tsc_deadline = msrs[i].data;
2189 break;
2190 case MSR_VM_HSAVE_PA:
2191 env->vm_hsave = msrs[i].data;
2192 break;
2193 case MSR_KVM_SYSTEM_TIME:
2194 env->system_time_msr = msrs[i].data;
2195 break;
2196 case MSR_KVM_WALL_CLOCK:
2197 env->wall_clock_msr = msrs[i].data;
2198 break;
2199 case MSR_MCG_STATUS:
2200 env->mcg_status = msrs[i].data;
2201 break;
2202 case MSR_MCG_CTL:
2203 env->mcg_ctl = msrs[i].data;
2204 break;
2205 case MSR_MCG_EXT_CTL:
2206 env->mcg_ext_ctl = msrs[i].data;
2207 break;
2208 case MSR_IA32_MISC_ENABLE:
2209 env->msr_ia32_misc_enable = msrs[i].data;
2210 break;
2211 case MSR_IA32_SMBASE:
2212 env->smbase = msrs[i].data;
2213 break;
2214 case MSR_IA32_FEATURE_CONTROL:
2215 env->msr_ia32_feature_control = msrs[i].data;
2216 break;
2217 case MSR_IA32_BNDCFGS:
2218 env->msr_bndcfgs = msrs[i].data;
2219 break;
2220 case MSR_IA32_XSS:
2221 env->xss = msrs[i].data;
2222 break;
2223 default:
2224 if (msrs[i].index >= MSR_MC0_CTL &&
2225 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2226 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2227 }
2228 break;
2229 case MSR_KVM_ASYNC_PF_EN:
2230 env->async_pf_en_msr = msrs[i].data;
2231 break;
2232 case MSR_KVM_PV_EOI_EN:
2233 env->pv_eoi_en_msr = msrs[i].data;
2234 break;
2235 case MSR_KVM_STEAL_TIME:
2236 env->steal_time_msr = msrs[i].data;
2237 break;
2238 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2239 env->msr_fixed_ctr_ctrl = msrs[i].data;
2240 break;
2241 case MSR_CORE_PERF_GLOBAL_CTRL:
2242 env->msr_global_ctrl = msrs[i].data;
2243 break;
2244 case MSR_CORE_PERF_GLOBAL_STATUS:
2245 env->msr_global_status = msrs[i].data;
2246 break;
2247 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2248 env->msr_global_ovf_ctrl = msrs[i].data;
2249 break;
2250 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2251 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2252 break;
2253 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2254 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2255 break;
2256 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2257 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2258 break;
2259 case HV_X64_MSR_HYPERCALL:
2260 env->msr_hv_hypercall = msrs[i].data;
2261 break;
2262 case HV_X64_MSR_GUEST_OS_ID:
2263 env->msr_hv_guest_os_id = msrs[i].data;
2264 break;
2265 case HV_X64_MSR_APIC_ASSIST_PAGE:
2266 env->msr_hv_vapic = msrs[i].data;
2267 break;
2268 case HV_X64_MSR_REFERENCE_TSC:
2269 env->msr_hv_tsc = msrs[i].data;
2270 break;
2271 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2272 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2273 break;
2274 case HV_X64_MSR_VP_RUNTIME:
2275 env->msr_hv_runtime = msrs[i].data;
2276 break;
2277 case HV_X64_MSR_SCONTROL:
2278 env->msr_hv_synic_control = msrs[i].data;
2279 break;
2280 case HV_X64_MSR_SVERSION:
2281 env->msr_hv_synic_version = msrs[i].data;
2282 break;
2283 case HV_X64_MSR_SIEFP:
2284 env->msr_hv_synic_evt_page = msrs[i].data;
2285 break;
2286 case HV_X64_MSR_SIMP:
2287 env->msr_hv_synic_msg_page = msrs[i].data;
2288 break;
2289 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2290 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2291 break;
2292 case HV_X64_MSR_STIMER0_CONFIG:
2293 case HV_X64_MSR_STIMER1_CONFIG:
2294 case HV_X64_MSR_STIMER2_CONFIG:
2295 case HV_X64_MSR_STIMER3_CONFIG:
2296 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2297 msrs[i].data;
2298 break;
2299 case HV_X64_MSR_STIMER0_COUNT:
2300 case HV_X64_MSR_STIMER1_COUNT:
2301 case HV_X64_MSR_STIMER2_COUNT:
2302 case HV_X64_MSR_STIMER3_COUNT:
2303 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2304 msrs[i].data;
2305 break;
2306 case MSR_MTRRdefType:
2307 env->mtrr_deftype = msrs[i].data;
2308 break;
2309 case MSR_MTRRfix64K_00000:
2310 env->mtrr_fixed[0] = msrs[i].data;
2311 break;
2312 case MSR_MTRRfix16K_80000:
2313 env->mtrr_fixed[1] = msrs[i].data;
2314 break;
2315 case MSR_MTRRfix16K_A0000:
2316 env->mtrr_fixed[2] = msrs[i].data;
2317 break;
2318 case MSR_MTRRfix4K_C0000:
2319 env->mtrr_fixed[3] = msrs[i].data;
2320 break;
2321 case MSR_MTRRfix4K_C8000:
2322 env->mtrr_fixed[4] = msrs[i].data;
2323 break;
2324 case MSR_MTRRfix4K_D0000:
2325 env->mtrr_fixed[5] = msrs[i].data;
2326 break;
2327 case MSR_MTRRfix4K_D8000:
2328 env->mtrr_fixed[6] = msrs[i].data;
2329 break;
2330 case MSR_MTRRfix4K_E0000:
2331 env->mtrr_fixed[7] = msrs[i].data;
2332 break;
2333 case MSR_MTRRfix4K_E8000:
2334 env->mtrr_fixed[8] = msrs[i].data;
2335 break;
2336 case MSR_MTRRfix4K_F0000:
2337 env->mtrr_fixed[9] = msrs[i].data;
2338 break;
2339 case MSR_MTRRfix4K_F8000:
2340 env->mtrr_fixed[10] = msrs[i].data;
2341 break;
2342 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2343 if (index & 1) {
2344 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2345 mtrr_top_bits;
2346 } else {
2347 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2348 }
2349 break;
2350 }
2351 }
2352
2353 return 0;
2354 }
2355
2356 static int kvm_put_mp_state(X86CPU *cpu)
2357 {
2358 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2359
2360 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2361 }
2362
2363 static int kvm_get_mp_state(X86CPU *cpu)
2364 {
2365 CPUState *cs = CPU(cpu);
2366 CPUX86State *env = &cpu->env;
2367 struct kvm_mp_state mp_state;
2368 int ret;
2369
2370 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2371 if (ret < 0) {
2372 return ret;
2373 }
2374 env->mp_state = mp_state.mp_state;
2375 if (kvm_irqchip_in_kernel()) {
2376 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2377 }
2378 return 0;
2379 }
2380
2381 static int kvm_get_apic(X86CPU *cpu)
2382 {
2383 DeviceState *apic = cpu->apic_state;
2384 struct kvm_lapic_state kapic;
2385 int ret;
2386
2387 if (apic && kvm_irqchip_in_kernel()) {
2388 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2389 if (ret < 0) {
2390 return ret;
2391 }
2392
2393 kvm_get_apic_state(apic, &kapic);
2394 }
2395 return 0;
2396 }
2397
2398 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2399 {
2400 CPUState *cs = CPU(cpu);
2401 CPUX86State *env = &cpu->env;
2402 struct kvm_vcpu_events events = {};
2403
2404 if (!kvm_has_vcpu_events()) {
2405 return 0;
2406 }
2407
2408 events.exception.injected = (env->exception_injected >= 0);
2409 events.exception.nr = env->exception_injected;
2410 events.exception.has_error_code = env->has_error_code;
2411 events.exception.error_code = env->error_code;
2412 events.exception.pad = 0;
2413
2414 events.interrupt.injected = (env->interrupt_injected >= 0);
2415 events.interrupt.nr = env->interrupt_injected;
2416 events.interrupt.soft = env->soft_interrupt;
2417
2418 events.nmi.injected = env->nmi_injected;
2419 events.nmi.pending = env->nmi_pending;
2420 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2421 events.nmi.pad = 0;
2422
2423 events.sipi_vector = env->sipi_vector;
2424 events.flags = 0;
2425
2426 if (has_msr_smbase) {
2427 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2428 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2429 if (kvm_irqchip_in_kernel()) {
2430 /* As soon as these are moved to the kernel, remove them
2431 * from cs->interrupt_request.
2432 */
2433 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2434 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2435 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2436 } else {
2437 /* Keep these in cs->interrupt_request. */
2438 events.smi.pending = 0;
2439 events.smi.latched_init = 0;
2440 }
2441 /* Stop SMI delivery on old machine types to avoid a reboot
2442 * on an inward migration of an old VM.
2443 */
2444 if (!cpu->kvm_no_smi_migration) {
2445 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2446 }
2447 }
2448
2449 if (level >= KVM_PUT_RESET_STATE) {
2450 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2451 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2452 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2453 }
2454 }
2455
2456 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2457 }
2458
2459 static int kvm_get_vcpu_events(X86CPU *cpu)
2460 {
2461 CPUX86State *env = &cpu->env;
2462 struct kvm_vcpu_events events;
2463 int ret;
2464
2465 if (!kvm_has_vcpu_events()) {
2466 return 0;
2467 }
2468
2469 memset(&events, 0, sizeof(events));
2470 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2471 if (ret < 0) {
2472 return ret;
2473 }
2474 env->exception_injected =
2475 events.exception.injected ? events.exception.nr : -1;
2476 env->has_error_code = events.exception.has_error_code;
2477 env->error_code = events.exception.error_code;
2478
2479 env->interrupt_injected =
2480 events.interrupt.injected ? events.interrupt.nr : -1;
2481 env->soft_interrupt = events.interrupt.soft;
2482
2483 env->nmi_injected = events.nmi.injected;
2484 env->nmi_pending = events.nmi.pending;
2485 if (events.nmi.masked) {
2486 env->hflags2 |= HF2_NMI_MASK;
2487 } else {
2488 env->hflags2 &= ~HF2_NMI_MASK;
2489 }
2490
2491 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2492 if (events.smi.smm) {
2493 env->hflags |= HF_SMM_MASK;
2494 } else {
2495 env->hflags &= ~HF_SMM_MASK;
2496 }
2497 if (events.smi.pending) {
2498 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2499 } else {
2500 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2501 }
2502 if (events.smi.smm_inside_nmi) {
2503 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2504 } else {
2505 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2506 }
2507 if (events.smi.latched_init) {
2508 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2509 } else {
2510 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2511 }
2512 }
2513
2514 env->sipi_vector = events.sipi_vector;
2515
2516 return 0;
2517 }
2518
2519 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2520 {
2521 CPUState *cs = CPU(cpu);
2522 CPUX86State *env = &cpu->env;
2523 int ret = 0;
2524 unsigned long reinject_trap = 0;
2525
2526 if (!kvm_has_vcpu_events()) {
2527 if (env->exception_injected == 1) {
2528 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2529 } else if (env->exception_injected == 3) {
2530 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2531 }
2532 env->exception_injected = -1;
2533 }
2534
2535 /*
2536 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2537 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2538 * by updating the debug state once again if single-stepping is on.
2539 * Another reason to call kvm_update_guest_debug here is a pending debug
2540 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2541 * reinject them via SET_GUEST_DEBUG.
2542 */
2543 if (reinject_trap ||
2544 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2545 ret = kvm_update_guest_debug(cs, reinject_trap);
2546 }
2547 return ret;
2548 }
2549
2550 static int kvm_put_debugregs(X86CPU *cpu)
2551 {
2552 CPUX86State *env = &cpu->env;
2553 struct kvm_debugregs dbgregs;
2554 int i;
2555
2556 if (!kvm_has_debugregs()) {
2557 return 0;
2558 }
2559
2560 for (i = 0; i < 4; i++) {
2561 dbgregs.db[i] = env->dr[i];
2562 }
2563 dbgregs.dr6 = env->dr[6];
2564 dbgregs.dr7 = env->dr[7];
2565 dbgregs.flags = 0;
2566
2567 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2568 }
2569
2570 static int kvm_get_debugregs(X86CPU *cpu)
2571 {
2572 CPUX86State *env = &cpu->env;
2573 struct kvm_debugregs dbgregs;
2574 int i, ret;
2575
2576 if (!kvm_has_debugregs()) {
2577 return 0;
2578 }
2579
2580 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2581 if (ret < 0) {
2582 return ret;
2583 }
2584 for (i = 0; i < 4; i++) {
2585 env->dr[i] = dbgregs.db[i];
2586 }
2587 env->dr[4] = env->dr[6] = dbgregs.dr6;
2588 env->dr[5] = env->dr[7] = dbgregs.dr7;
2589
2590 return 0;
2591 }
2592
2593 int kvm_arch_put_registers(CPUState *cpu, int level)
2594 {
2595 X86CPU *x86_cpu = X86_CPU(cpu);
2596 int ret;
2597
2598 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2599
2600 if (level >= KVM_PUT_RESET_STATE) {
2601 ret = kvm_put_msr_feature_control(x86_cpu);
2602 if (ret < 0) {
2603 return ret;
2604 }
2605 }
2606
2607 if (level == KVM_PUT_FULL_STATE) {
2608 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2609 * because TSC frequency mismatch shouldn't abort migration,
2610 * unless the user explicitly asked for a more strict TSC
2611 * setting (e.g. using an explicit "tsc-freq" option).
2612 */
2613 kvm_arch_set_tsc_khz(cpu);
2614 }
2615
2616 ret = kvm_getput_regs(x86_cpu, 1);
2617 if (ret < 0) {
2618 return ret;
2619 }
2620 ret = kvm_put_xsave(x86_cpu);
2621 if (ret < 0) {
2622 return ret;
2623 }
2624 ret = kvm_put_xcrs(x86_cpu);
2625 if (ret < 0) {
2626 return ret;
2627 }
2628 ret = kvm_put_sregs(x86_cpu);
2629 if (ret < 0) {
2630 return ret;
2631 }
2632 /* must be before kvm_put_msrs */
2633 ret = kvm_inject_mce_oldstyle(x86_cpu);
2634 if (ret < 0) {
2635 return ret;
2636 }
2637 ret = kvm_put_msrs(x86_cpu, level);
2638 if (ret < 0) {
2639 return ret;
2640 }
2641 ret = kvm_put_vcpu_events(x86_cpu, level);
2642 if (ret < 0) {
2643 return ret;
2644 }
2645 if (level >= KVM_PUT_RESET_STATE) {
2646 ret = kvm_put_mp_state(x86_cpu);
2647 if (ret < 0) {
2648 return ret;
2649 }
2650 }
2651
2652 ret = kvm_put_tscdeadline_msr(x86_cpu);
2653 if (ret < 0) {
2654 return ret;
2655 }
2656 ret = kvm_put_debugregs(x86_cpu);
2657 if (ret < 0) {
2658 return ret;
2659 }
2660 /* must be last */
2661 ret = kvm_guest_debug_workarounds(x86_cpu);
2662 if (ret < 0) {
2663 return ret;
2664 }
2665 return 0;
2666 }
2667
2668 int kvm_arch_get_registers(CPUState *cs)
2669 {
2670 X86CPU *cpu = X86_CPU(cs);
2671 int ret;
2672
2673 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2674
2675 ret = kvm_get_vcpu_events(cpu);
2676 if (ret < 0) {
2677 goto out;
2678 }
2679 /*
2680 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2681 * KVM_GET_REGS and KVM_GET_SREGS.
2682 */
2683 ret = kvm_get_mp_state(cpu);
2684 if (ret < 0) {
2685 goto out;
2686 }
2687 ret = kvm_getput_regs(cpu, 0);
2688 if (ret < 0) {
2689 goto out;
2690 }
2691 ret = kvm_get_xsave(cpu);
2692 if (ret < 0) {
2693 goto out;
2694 }
2695 ret = kvm_get_xcrs(cpu);
2696 if (ret < 0) {
2697 goto out;
2698 }
2699 ret = kvm_get_sregs(cpu);
2700 if (ret < 0) {
2701 goto out;
2702 }
2703 ret = kvm_get_msrs(cpu);
2704 if (ret < 0) {
2705 goto out;
2706 }
2707 ret = kvm_get_apic(cpu);
2708 if (ret < 0) {
2709 goto out;
2710 }
2711 ret = kvm_get_debugregs(cpu);
2712 if (ret < 0) {
2713 goto out;
2714 }
2715 ret = 0;
2716 out:
2717 cpu_sync_bndcs_hflags(&cpu->env);
2718 return ret;
2719 }
2720
2721 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2722 {
2723 X86CPU *x86_cpu = X86_CPU(cpu);
2724 CPUX86State *env = &x86_cpu->env;
2725 int ret;
2726
2727 /* Inject NMI */
2728 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2729 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2730 qemu_mutex_lock_iothread();
2731 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2732 qemu_mutex_unlock_iothread();
2733 DPRINTF("injected NMI\n");
2734 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2735 if (ret < 0) {
2736 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2737 strerror(-ret));
2738 }
2739 }
2740 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2741 qemu_mutex_lock_iothread();
2742 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2743 qemu_mutex_unlock_iothread();
2744 DPRINTF("injected SMI\n");
2745 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2746 if (ret < 0) {
2747 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2748 strerror(-ret));
2749 }
2750 }
2751 }
2752
2753 if (!kvm_pic_in_kernel()) {
2754 qemu_mutex_lock_iothread();
2755 }
2756
2757 /* Force the VCPU out of its inner loop to process any INIT requests
2758 * or (for userspace APIC, but it is cheap to combine the checks here)
2759 * pending TPR access reports.
2760 */
2761 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2762 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2763 !(env->hflags & HF_SMM_MASK)) {
2764 cpu->exit_request = 1;
2765 }
2766 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2767 cpu->exit_request = 1;
2768 }
2769 }
2770
2771 if (!kvm_pic_in_kernel()) {
2772 /* Try to inject an interrupt if the guest can accept it */
2773 if (run->ready_for_interrupt_injection &&
2774 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2775 (env->eflags & IF_MASK)) {
2776 int irq;
2777
2778 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2779 irq = cpu_get_pic_interrupt(env);
2780 if (irq >= 0) {
2781 struct kvm_interrupt intr;
2782
2783 intr.irq = irq;
2784 DPRINTF("injected interrupt %d\n", irq);
2785 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2786 if (ret < 0) {
2787 fprintf(stderr,
2788 "KVM: injection failed, interrupt lost (%s)\n",
2789 strerror(-ret));
2790 }
2791 }
2792 }
2793
2794 /* If we have an interrupt but the guest is not ready to receive an
2795 * interrupt, request an interrupt window exit. This will
2796 * cause a return to userspace as soon as the guest is ready to
2797 * receive interrupts. */
2798 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2799 run->request_interrupt_window = 1;
2800 } else {
2801 run->request_interrupt_window = 0;
2802 }
2803
2804 DPRINTF("setting tpr\n");
2805 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2806
2807 qemu_mutex_unlock_iothread();
2808 }
2809 }
2810
2811 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2812 {
2813 X86CPU *x86_cpu = X86_CPU(cpu);
2814 CPUX86State *env = &x86_cpu->env;
2815
2816 if (run->flags & KVM_RUN_X86_SMM) {
2817 env->hflags |= HF_SMM_MASK;
2818 } else {
2819 env->hflags &= ~HF_SMM_MASK;
2820 }
2821 if (run->if_flag) {
2822 env->eflags |= IF_MASK;
2823 } else {
2824 env->eflags &= ~IF_MASK;
2825 }
2826
2827 /* We need to protect the apic state against concurrent accesses from
2828 * different threads in case the userspace irqchip is used. */
2829 if (!kvm_irqchip_in_kernel()) {
2830 qemu_mutex_lock_iothread();
2831 }
2832 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2833 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2834 if (!kvm_irqchip_in_kernel()) {
2835 qemu_mutex_unlock_iothread();
2836 }
2837 return cpu_get_mem_attrs(env);
2838 }
2839
2840 int kvm_arch_process_async_events(CPUState *cs)
2841 {
2842 X86CPU *cpu = X86_CPU(cs);
2843 CPUX86State *env = &cpu->env;
2844
2845 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2846 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2847 assert(env->mcg_cap);
2848
2849 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2850
2851 kvm_cpu_synchronize_state(cs);
2852
2853 if (env->exception_injected == EXCP08_DBLE) {
2854 /* this means triple fault */
2855 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
2856 cs->exit_request = 1;
2857 return 0;
2858 }
2859 env->exception_injected = EXCP12_MCHK;
2860 env->has_error_code = 0;
2861
2862 cs->halted = 0;
2863 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2864 env->mp_state = KVM_MP_STATE_RUNNABLE;
2865 }
2866 }
2867
2868 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2869 !(env->hflags & HF_SMM_MASK)) {
2870 kvm_cpu_synchronize_state(cs);
2871 do_cpu_init(cpu);
2872 }
2873
2874 if (kvm_irqchip_in_kernel()) {
2875 return 0;
2876 }
2877
2878 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2879 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2880 apic_poll_irq(cpu->apic_state);
2881 }
2882 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2883 (env->eflags & IF_MASK)) ||
2884 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2885 cs->halted = 0;
2886 }
2887 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2888 kvm_cpu_synchronize_state(cs);
2889 do_cpu_sipi(cpu);
2890 }
2891 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2892 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2893 kvm_cpu_synchronize_state(cs);
2894 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2895 env->tpr_access_type);
2896 }
2897
2898 return cs->halted;
2899 }
2900
2901 static int kvm_handle_halt(X86CPU *cpu)
2902 {
2903 CPUState *cs = CPU(cpu);
2904 CPUX86State *env = &cpu->env;
2905
2906 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2907 (env->eflags & IF_MASK)) &&
2908 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2909 cs->halted = 1;
2910 return EXCP_HLT;
2911 }
2912
2913 return 0;
2914 }
2915
2916 static int kvm_handle_tpr_access(X86CPU *cpu)
2917 {
2918 CPUState *cs = CPU(cpu);
2919 struct kvm_run *run = cs->kvm_run;
2920
2921 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2922 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2923 : TPR_ACCESS_READ);
2924 return 1;
2925 }
2926
2927 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2928 {
2929 static const uint8_t int3 = 0xcc;
2930
2931 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2932 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2933 return -EINVAL;
2934 }
2935 return 0;
2936 }
2937
2938 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2939 {
2940 uint8_t int3;
2941
2942 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2943 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2944 return -EINVAL;
2945 }
2946 return 0;
2947 }
2948
2949 static struct {
2950 target_ulong addr;
2951 int len;
2952 int type;
2953 } hw_breakpoint[4];
2954
2955 static int nb_hw_breakpoint;
2956
2957 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2958 {
2959 int n;
2960
2961 for (n = 0; n < nb_hw_breakpoint; n++) {
2962 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2963 (hw_breakpoint[n].len == len || len == -1)) {
2964 return n;
2965 }
2966 }
2967 return -1;
2968 }
2969
2970 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2971 target_ulong len, int type)
2972 {
2973 switch (type) {
2974 case GDB_BREAKPOINT_HW:
2975 len = 1;
2976 break;
2977 case GDB_WATCHPOINT_WRITE:
2978 case GDB_WATCHPOINT_ACCESS:
2979 switch (len) {
2980 case 1:
2981 break;
2982 case 2:
2983 case 4:
2984 case 8:
2985 if (addr & (len - 1)) {
2986 return -EINVAL;
2987 }
2988 break;
2989 default:
2990 return -EINVAL;
2991 }
2992 break;
2993 default:
2994 return -ENOSYS;
2995 }
2996
2997 if (nb_hw_breakpoint == 4) {
2998 return -ENOBUFS;
2999 }
3000 if (find_hw_breakpoint(addr, len, type) >= 0) {
3001 return -EEXIST;
3002 }
3003 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3004 hw_breakpoint[nb_hw_breakpoint].len = len;
3005 hw_breakpoint[nb_hw_breakpoint].type = type;
3006 nb_hw_breakpoint++;
3007
3008 return 0;
3009 }
3010
3011 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3012 target_ulong len, int type)
3013 {
3014 int n;
3015
3016 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3017 if (n < 0) {
3018 return -ENOENT;
3019 }
3020 nb_hw_breakpoint--;
3021 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3022
3023 return 0;
3024 }
3025
3026 void kvm_arch_remove_all_hw_breakpoints(void)
3027 {
3028 nb_hw_breakpoint = 0;
3029 }
3030
3031 static CPUWatchpoint hw_watchpoint;
3032
3033 static int kvm_handle_debug(X86CPU *cpu,
3034 struct kvm_debug_exit_arch *arch_info)
3035 {
3036 CPUState *cs = CPU(cpu);
3037 CPUX86State *env = &cpu->env;
3038 int ret = 0;
3039 int n;
3040
3041 if (arch_info->exception == 1) {
3042 if (arch_info->dr6 & (1 << 14)) {
3043 if (cs->singlestep_enabled) {
3044 ret = EXCP_DEBUG;
3045 }
3046 } else {
3047 for (n = 0; n < 4; n++) {
3048 if (arch_info->dr6 & (1 << n)) {
3049 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3050 case 0x0:
3051 ret = EXCP_DEBUG;
3052 break;
3053 case 0x1:
3054 ret = EXCP_DEBUG;
3055 cs->watchpoint_hit = &hw_watchpoint;
3056 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3057 hw_watchpoint.flags = BP_MEM_WRITE;
3058 break;
3059 case 0x3:
3060 ret = EXCP_DEBUG;
3061 cs->watchpoint_hit = &hw_watchpoint;
3062 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3063 hw_watchpoint.flags = BP_MEM_ACCESS;
3064 break;
3065 }
3066 }
3067 }
3068 }
3069 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3070 ret = EXCP_DEBUG;
3071 }
3072 if (ret == 0) {
3073 cpu_synchronize_state(cs);
3074 assert(env->exception_injected == -1);
3075
3076 /* pass to guest */
3077 env->exception_injected = arch_info->exception;
3078 env->has_error_code = 0;
3079 }
3080
3081 return ret;
3082 }
3083
3084 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3085 {
3086 const uint8_t type_code[] = {
3087 [GDB_BREAKPOINT_HW] = 0x0,
3088 [GDB_WATCHPOINT_WRITE] = 0x1,
3089 [GDB_WATCHPOINT_ACCESS] = 0x3
3090 };
3091 const uint8_t len_code[] = {
3092 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3093 };
3094 int n;
3095
3096 if (kvm_sw_breakpoints_active(cpu)) {
3097 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3098 }
3099 if (nb_hw_breakpoint > 0) {
3100 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3101 dbg->arch.debugreg[7] = 0x0600;
3102 for (n = 0; n < nb_hw_breakpoint; n++) {
3103 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3104 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3105 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3106 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3107 }
3108 }
3109 }
3110
3111 static bool host_supports_vmx(void)
3112 {
3113 uint32_t ecx, unused;
3114
3115 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3116 return ecx & CPUID_EXT_VMX;
3117 }
3118
3119 #define VMX_INVALID_GUEST_STATE 0x80000021
3120
3121 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3122 {
3123 X86CPU *cpu = X86_CPU(cs);
3124 uint64_t code;
3125 int ret;
3126
3127 switch (run->exit_reason) {
3128 case KVM_EXIT_HLT:
3129 DPRINTF("handle_hlt\n");
3130 qemu_mutex_lock_iothread();
3131 ret = kvm_handle_halt(cpu);
3132 qemu_mutex_unlock_iothread();
3133 break;
3134 case KVM_EXIT_SET_TPR:
3135 ret = 0;
3136 break;
3137 case KVM_EXIT_TPR_ACCESS:
3138 qemu_mutex_lock_iothread();
3139 ret = kvm_handle_tpr_access(cpu);
3140 qemu_mutex_unlock_iothread();
3141 break;
3142 case KVM_EXIT_FAIL_ENTRY:
3143 code = run->fail_entry.hardware_entry_failure_reason;
3144 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3145 code);
3146 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3147 fprintf(stderr,
3148 "\nIf you're running a guest on an Intel machine without "
3149 "unrestricted mode\n"
3150 "support, the failure can be most likely due to the guest "
3151 "entering an invalid\n"
3152 "state for Intel VT. For example, the guest maybe running "
3153 "in big real mode\n"
3154 "which is not supported on less recent Intel processors."
3155 "\n\n");
3156 }
3157 ret = -1;
3158 break;
3159 case KVM_EXIT_EXCEPTION:
3160 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3161 run->ex.exception, run->ex.error_code);
3162 ret = -1;
3163 break;
3164 case KVM_EXIT_DEBUG:
3165 DPRINTF("kvm_exit_debug\n");
3166 qemu_mutex_lock_iothread();
3167 ret = kvm_handle_debug(cpu, &run->debug.arch);
3168 qemu_mutex_unlock_iothread();
3169 break;
3170 case KVM_EXIT_HYPERV:
3171 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3172 break;
3173 case KVM_EXIT_IOAPIC_EOI:
3174 ioapic_eoi_broadcast(run->eoi.vector);
3175 ret = 0;
3176 break;
3177 default:
3178 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3179 ret = -1;
3180 break;
3181 }
3182
3183 return ret;
3184 }
3185
3186 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3187 {
3188 X86CPU *cpu = X86_CPU(cs);
3189 CPUX86State *env = &cpu->env;
3190
3191 kvm_cpu_synchronize_state(cs);
3192 return !(env->cr[0] & CR0_PE_MASK) ||
3193 ((env->segs[R_CS].selector & 3) != 3);
3194 }
3195
3196 void kvm_arch_init_irq_routing(KVMState *s)
3197 {
3198 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3199 /* If kernel can't do irq routing, interrupt source
3200 * override 0->2 cannot be set up as required by HPET.
3201 * So we have to disable it.
3202 */
3203 no_hpet = 1;
3204 }
3205 /* We know at this point that we're using the in-kernel
3206 * irqchip, so we can use irqfds, and on x86 we know
3207 * we can use msi via irqfd and GSI routing.
3208 */
3209 kvm_msi_via_irqfd_allowed = true;
3210 kvm_gsi_routing_allowed = true;
3211
3212 if (kvm_irqchip_is_split()) {
3213 int i;
3214
3215 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3216 MSI routes for signaling interrupts to the local apics. */
3217 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3218 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3219 error_report("Could not enable split IRQ mode.");
3220 exit(1);
3221 }
3222 }
3223 }
3224 }
3225
3226 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3227 {
3228 int ret;
3229 if (machine_kernel_irqchip_split(ms)) {
3230 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3231 if (ret) {
3232 error_report("Could not enable split irqchip mode: %s",
3233 strerror(-ret));
3234 exit(1);
3235 } else {
3236 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3237 kvm_split_irqchip = true;
3238 return 1;
3239 }
3240 } else {
3241 return 0;
3242 }
3243 }
3244
3245 /* Classic KVM device assignment interface. Will remain x86 only. */
3246 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3247 uint32_t flags, uint32_t *dev_id)
3248 {
3249 struct kvm_assigned_pci_dev dev_data = {
3250 .segnr = dev_addr->domain,
3251 .busnr = dev_addr->bus,
3252 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3253 .flags = flags,
3254 };
3255 int ret;
3256
3257 dev_data.assigned_dev_id =
3258 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3259
3260 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3261 if (ret < 0) {
3262 return ret;
3263 }
3264
3265 *dev_id = dev_data.assigned_dev_id;
3266
3267 return 0;
3268 }
3269
3270 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3271 {
3272 struct kvm_assigned_pci_dev dev_data = {
3273 .assigned_dev_id = dev_id,
3274 };
3275
3276 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3277 }
3278
3279 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3280 uint32_t irq_type, uint32_t guest_irq)
3281 {
3282 struct kvm_assigned_irq assigned_irq = {
3283 .assigned_dev_id = dev_id,
3284 .guest_irq = guest_irq,
3285 .flags = irq_type,
3286 };
3287
3288 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3289 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3290 } else {
3291 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3292 }
3293 }
3294
3295 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3296 uint32_t guest_irq)
3297 {
3298 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3299 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3300
3301 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3302 }
3303
3304 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3305 {
3306 struct kvm_assigned_pci_dev dev_data = {
3307 .assigned_dev_id = dev_id,
3308 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3309 };
3310
3311 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3312 }
3313
3314 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3315 uint32_t type)
3316 {
3317 struct kvm_assigned_irq assigned_irq = {
3318 .assigned_dev_id = dev_id,
3319 .flags = type,
3320 };
3321
3322 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3323 }
3324
3325 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3326 {
3327 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3328 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3329 }
3330
3331 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3332 {
3333 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3334 KVM_DEV_IRQ_GUEST_MSI, virq);
3335 }
3336
3337 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3338 {
3339 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3340 KVM_DEV_IRQ_HOST_MSI);
3341 }
3342
3343 bool kvm_device_msix_supported(KVMState *s)
3344 {
3345 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3346 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3347 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3348 }
3349
3350 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3351 uint32_t nr_vectors)
3352 {
3353 struct kvm_assigned_msix_nr msix_nr = {
3354 .assigned_dev_id = dev_id,
3355 .entry_nr = nr_vectors,
3356 };
3357
3358 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3359 }
3360
3361 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3362 int virq)
3363 {
3364 struct kvm_assigned_msix_entry msix_entry = {
3365 .assigned_dev_id = dev_id,
3366 .gsi = virq,
3367 .entry = vector,
3368 };
3369
3370 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3371 }
3372
3373 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3374 {
3375 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3376 KVM_DEV_IRQ_GUEST_MSIX, 0);
3377 }
3378
3379 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3380 {
3381 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3382 KVM_DEV_IRQ_HOST_MSIX);
3383 }
3384
3385 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3386 uint64_t address, uint32_t data, PCIDevice *dev)
3387 {
3388 X86IOMMUState *iommu = x86_iommu_get_default();
3389
3390 if (iommu) {
3391 int ret;
3392 MSIMessage src, dst;
3393 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3394
3395 src.address = route->u.msi.address_hi;
3396 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3397 src.address |= route->u.msi.address_lo;
3398 src.data = route->u.msi.data;
3399
3400 ret = class->int_remap(iommu, &src, &dst, dev ? \
3401 pci_requester_id(dev) : \
3402 X86_IOMMU_SID_INVALID);
3403 if (ret) {
3404 trace_kvm_x86_fixup_msi_error(route->gsi);
3405 return 1;
3406 }
3407
3408 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3409 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3410 route->u.msi.data = dst.data;
3411 }
3412
3413 return 0;
3414 }
3415
3416 typedef struct MSIRouteEntry MSIRouteEntry;
3417
3418 struct MSIRouteEntry {
3419 PCIDevice *dev; /* Device pointer */
3420 int vector; /* MSI/MSIX vector index */
3421 int virq; /* Virtual IRQ index */
3422 QLIST_ENTRY(MSIRouteEntry) list;
3423 };
3424
3425 /* List of used GSI routes */
3426 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3427 QLIST_HEAD_INITIALIZER(msi_route_list);
3428
3429 static void kvm_update_msi_routes_all(void *private, bool global,
3430 uint32_t index, uint32_t mask)
3431 {
3432 int cnt = 0;
3433 MSIRouteEntry *entry;
3434 MSIMessage msg;
3435 PCIDevice *dev;
3436
3437 /* TODO: explicit route update */
3438 QLIST_FOREACH(entry, &msi_route_list, list) {
3439 cnt++;
3440 dev = entry->dev;
3441 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3442 continue;
3443 }
3444 msg = pci_get_msi_message(dev, entry->vector);
3445 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3446 }
3447 kvm_irqchip_commit_routes(kvm_state);
3448 trace_kvm_x86_update_msi_routes(cnt);
3449 }
3450
3451 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3452 int vector, PCIDevice *dev)
3453 {
3454 static bool notify_list_inited = false;
3455 MSIRouteEntry *entry;
3456
3457 if (!dev) {
3458 /* These are (possibly) IOAPIC routes only used for split
3459 * kernel irqchip mode, while what we are housekeeping are
3460 * PCI devices only. */
3461 return 0;
3462 }
3463
3464 entry = g_new0(MSIRouteEntry, 1);
3465 entry->dev = dev;
3466 entry->vector = vector;
3467 entry->virq = route->gsi;
3468 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3469
3470 trace_kvm_x86_add_msi_route(route->gsi);
3471
3472 if (!notify_list_inited) {
3473 /* For the first time we do add route, add ourselves into
3474 * IOMMU's IEC notify list if needed. */
3475 X86IOMMUState *iommu = x86_iommu_get_default();
3476 if (iommu) {
3477 x86_iommu_iec_register_notifier(iommu,
3478 kvm_update_msi_routes_all,
3479 NULL);
3480 }
3481 notify_list_inited = true;
3482 }
3483 return 0;
3484 }
3485
3486 int kvm_arch_release_virq_post(int virq)
3487 {
3488 MSIRouteEntry *entry, *next;
3489 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3490 if (entry->virq == virq) {
3491 trace_kvm_x86_remove_msi_route(virq);
3492 QLIST_REMOVE(entry, list);
3493 break;
3494 }
3495 }
3496 return 0;
3497 }
3498
3499 int kvm_arch_msi_data_to_gsi(uint32_t data)
3500 {
3501 abort();
3502 }
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