target/i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "qapi/error.h"
  17 #include <sys/ioctl.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include "standard-headers/asm-x86/kvm_para.h"
  22
  23 #include "qemu-common.h"
  24 #include "cpu.h"
  25 #include "sysemu/sysemu.h"
  26 #include "sysemu/hw_accel.h"
  27 #include "sysemu/kvm_int.h"
  28 #include "kvm_i386.h"
  29 #include "hyperv.h"
  30 #include "hyperv-proto.h"
  31
  32 #include "exec/gdbstub.h"
  33 #include "qemu/host-utils.h"
  34 #include "qemu/config-file.h"
  35 #include "qemu/error-report.h"
  36 #include "hw/i386/pc.h"
  37 #include "hw/i386/apic.h"
  38 #include "hw/i386/apic_internal.h"
  39 #include "hw/i386/apic-msidef.h"
  40 #include "hw/i386/intel_iommu.h"
  41 #include "hw/i386/x86-iommu.h"
  42
  43 #include "hw/pci/pci.h"
  44 #include "hw/pci/msi.h"
  45 #include "hw/pci/msix.h"
  46 #include "migration/blocker.h"
  47 #include "exec/memattrs.h"
  48 #include "trace.h"
  49
  50 //#define DEBUG_KVM
  51
  52 #ifdef DEBUG_KVM
  53 #define DPRINTF(fmt, ...) \
  54     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  55 #else
  56 #define DPRINTF(fmt, ...) \
  57     do { } while (0)
  58 #endif
  59
  60 #define MSR_KVM_WALL_CLOCK  0x11
  61 #define MSR_KVM_SYSTEM_TIME 0x12
  62
  63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
  64  * 255 kvm_msr_entry structs */
  65 #define MSR_BUF_SIZE 4096
  66
  67 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  68     KVM_CAP_INFO(SET_TSS_ADDR),
  69     KVM_CAP_INFO(EXT_CPUID),
  70     KVM_CAP_INFO(MP_STATE),
  71     KVM_CAP_LAST_INFO
  72 };
  73
  74 static bool has_msr_star;
  75 static bool has_msr_hsave_pa;
  76 static bool has_msr_tsc_aux;
  77 static bool has_msr_tsc_adjust;
  78 static bool has_msr_tsc_deadline;
  79 static bool has_msr_feature_control;
  80 static bool has_msr_misc_enable;
  81 static bool has_msr_smbase;
  82 static bool has_msr_bndcfgs;
  83 static int lm_capable_kernel;
  84 static bool has_msr_hv_hypercall;
  85 static bool has_msr_hv_crash;
  86 static bool has_msr_hv_reset;
  87 static bool has_msr_hv_vpindex;
  88 static bool hv_vpindex_settable;
  89 static bool has_msr_hv_runtime;
  90 static bool has_msr_hv_synic;
  91 static bool has_msr_hv_stimer;
  92 static bool has_msr_hv_frequencies;
  93 static bool has_msr_hv_reenlightenment;
  94 static bool has_msr_xss;
  95 static bool has_msr_spec_ctrl;
  96 static bool has_msr_virt_ssbd;
  97 static bool has_msr_smi_count;
  98 static bool has_msr_arch_capabs;
  99
 100 static uint32_t has_architectural_pmu_version;
 101 static uint32_t num_architectural_pmu_gp_counters;
 102 static uint32_t num_architectural_pmu_fixed_counters;
 103
 104 static int has_xsave;
 105 static int has_xcrs;
 106 static int has_pit_state2;
 107
 108 static bool has_msr_mcg_ext_ctl;
 109
 110 static struct kvm_cpuid2 *cpuid_cache;
 111 static struct kvm_msr_list *kvm_feature_msrs;
 112
 113 int kvm_has_pit_state2(void)
 114 {
 115     return has_pit_state2;
 116 }
 117
 118 bool kvm_has_smm(void)
 119 {
 120     return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
 121 }
 122
 123 bool kvm_has_adjust_clock_stable(void)
 124 {
 125     int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
 126
 127     return (ret == KVM_CLOCK_TSC_STABLE);
 128 }
 129
 130 bool kvm_allows_irq0_override(void)
 131 {
 132     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
 133 }
 134
 135 static bool kvm_x2apic_api_set_flags(uint64_t flags)
 136 {
 137     KVMState *s = KVM_STATE(current_machine->accelerator);
 138
 139     return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
 140 }
 141
 142 #define MEMORIZE(fn, _result) \
 143     ({ \
 144         static bool _memorized; \
 145         \
 146         if (_memorized) { \
 147             return _result; \
 148         } \
 149         _memorized = true; \
 150         _result = fn; \
 151     })
 152
 153 static bool has_x2apic_api;
 154
 155 bool kvm_has_x2apic_api(void)
 156 {
 157     return has_x2apic_api;
 158 }
 159
 160 bool kvm_enable_x2apic(void)
 161 {
 162     return MEMORIZE(
 163              kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
 164                                       KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
 165              has_x2apic_api);
 166 }
 167
 168 bool kvm_hv_vpindex_settable(void)
 169 {
 170     return hv_vpindex_settable;
 171 }
 172
 173 static int kvm_get_tsc(CPUState *cs)
 174 {
 175     X86CPU *cpu = X86_CPU(cs);
 176     CPUX86State *env = &cpu->env;
 177     struct {
 178         struct kvm_msrs info;
 179         struct kvm_msr_entry entries[1];
 180     } msr_data;
 181     int ret;
 182
 183     if (env->tsc_valid) {
 184         return 0;
 185     }
 186
 187     msr_data.info.nmsrs = 1;
 188     msr_data.entries[0].index = MSR_IA32_TSC;
 189     env->tsc_valid = !runstate_is_running();
 190
 191     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
 192     if (ret < 0) {
 193         return ret;
 194     }
 195
 196     assert(ret == 1);
 197     env->tsc = msr_data.entries[0].data;
 198     return 0;
 199 }
 200
 201 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
 202 {
 203     kvm_get_tsc(cpu);
 204 }
 205
 206 void kvm_synchronize_all_tsc(void)
 207 {
 208     CPUState *cpu;
 209
 210     if (kvm_enabled()) {
 211         CPU_FOREACH(cpu) {
 212             run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
 213         }
 214     }
 215 }
 216
 217 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
 218 {
 219     struct kvm_cpuid2 *cpuid;
 220     int r, size;
 221
 222     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
 223     cpuid = g_malloc0(size);
 224     cpuid->nent = max;
 225     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
 226     if (r == 0 && cpuid->nent >= max) {
 227         r = -E2BIG;
 228     }
 229     if (r < 0) {
 230         if (r == -E2BIG) {
 231             g_free(cpuid);
 232             return NULL;
 233         } else {
 234             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
 235                     strerror(-r));
 236             exit(1);
 237         }
 238     }
 239     return cpuid;
 240 }
 241
 242 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 243  * for all entries.
 244  */
 245 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 246 {
 247     struct kvm_cpuid2 *cpuid;
 248     int max = 1;
 249
 250     if (cpuid_cache != NULL) {
 251         return cpuid_cache;
 252     }
 253     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 254         max *= 2;
 255     }
 256     cpuid_cache = cpuid;
 257     return cpuid;
 258 }
 259
 260 static const struct kvm_para_features {
 261     int cap;
 262     int feature;
 263 } para_features[] = {
 264     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 265     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 266     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 267     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 268 };
 269
 270 static int get_para_features(KVMState *s)
 271 {
 272     int i, features = 0;
 273
 274     for (i = 0; i < ARRAY_SIZE(para_features); i++) {
 275         if (kvm_check_extension(s, para_features[i].cap)) {
 276             features |= (1 << para_features[i].feature);
 277         }
 278     }
 279
 280     return features;
 281 }
 282
 283 static bool host_tsx_blacklisted(void)
 284 {
 285     int family, model, stepping;\
 286     char vendor[CPUID_VENDOR_SZ + 1];
 287
 288     host_vendor_fms(vendor, &family, &model, &stepping);
 289
 290     /* Check if we are running on a Haswell host known to have broken TSX */
 291     return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
 292            (family == 6) &&
 293            ((model == 63 && stepping < 4) ||
 294             model == 60 || model == 69 || model == 70);
 295 }
 296
 297 /* Returns the value for a specific register on the cpuid entry
 298  */
 299 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 300 {
 301     uint32_t ret = 0;
 302     switch (reg) {
 303     case R_EAX:
 304         ret = entry->eax;
 305         break;
 306     case R_EBX:
 307         ret = entry->ebx;
 308         break;
 309     case R_ECX:
 310         ret = entry->ecx;
 311         break;
 312     case R_EDX:
 313         ret = entry->edx;
 314         break;
 315     }
 316     return ret;
 317 }
 318
 319 /* Find matching entry for function/index on kvm_cpuid2 struct
 320  */
 321 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 322                                                  uint32_t function,
 323                                                  uint32_t index)
 324 {
 325     int i;
 326     for (i = 0; i < cpuid->nent; ++i) {
 327         if (cpuid->entries[i].function == function &&
 328             cpuid->entries[i].index == index) {
 329             return &cpuid->entries[i];
 330         }
 331     }
 332     /* not found: */
 333     return NULL;
 334 }
 335
 336 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 337                                       uint32_t index, int reg)
 338 {
 339     struct kvm_cpuid2 *cpuid;
 340     uint32_t ret = 0;
 341     uint32_t cpuid_1_edx;
 342     bool found = false;
 343
 344     cpuid = get_supported_cpuid(s);
 345
 346     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 347     if (entry) {
 348         found = true;
 349         ret = cpuid_entry_get_reg(entry, reg);
 350     }
 351
 352     /* Fixups for the data returned by KVM, below */
 353
 354     if (function == 1 && reg == R_EDX) {
 355         /* KVM before 2.6.30 misreports the following features */
 356         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 357     } else if (function == 1 && reg == R_ECX) {
 358         /* We can set the hypervisor flag, even if KVM does not return it on
 359          * GET_SUPPORTED_CPUID
 360          */
 361         ret |= CPUID_EXT_HYPERVISOR;
 362         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 363          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 364          * and the irqchip is in the kernel.
 365          */
 366         if (kvm_irqchip_in_kernel() &&
 367                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 368             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 369         }
 370
 371         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 372          * without the in-kernel irqchip
 373          */
 374         if (!kvm_irqchip_in_kernel()) {
 375             ret &= ~CPUID_EXT_X2APIC;
 376         }
 377
 378         if (enable_cpu_pm) {
 379             int disable_exits = kvm_check_extension(s,
 380                                                     KVM_CAP_X86_DISABLE_EXITS);
 381
 382             if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
 383                 ret |= CPUID_EXT_MONITOR;
 384             }
 385         }
 386     } else if (function == 6 && reg == R_EAX) {
 387         ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
 388     } else if (function == 7 && index == 0 && reg == R_EBX) {
 389         if (host_tsx_blacklisted()) {
 390             ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
 391         }
 392     } else if (function == 0x80000001 && reg == R_ECX) {
 393         /*
 394          * It's safe to enable TOPOEXT even if it's not returned by
 395          * GET_SUPPORTED_CPUID.  Unconditionally enabling TOPOEXT here allows
 396          * us to keep CPU models including TOPOEXT runnable on older kernels.
 397          */
 398         ret |= CPUID_EXT3_TOPOEXT;
 399     } else if (function == 0x80000001 && reg == R_EDX) {
 400         /* On Intel, kvm returns cpuid according to the Intel spec,
 401          * so add missing bits according to the AMD spec:
 402          */
 403         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 404         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 405     } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
 406         /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
 407          * be enabled without the in-kernel irqchip
 408          */
 409         if (!kvm_irqchip_in_kernel()) {
 410             ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
 411         }
 412     } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
 413         ret |= 1U << KVM_HINTS_REALTIME;
 414         found = 1;
 415     }
 416
 417     /* fallback for older kernels */
 418     if ((function == KVM_CPUID_FEATURES) && !found) {
 419         ret = get_para_features(s);
 420     }
 421
 422     return ret;
 423 }
 424
 425 uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
 426 {
 427     struct {
 428         struct kvm_msrs info;
 429         struct kvm_msr_entry entries[1];
 430     } msr_data;
 431     uint32_t ret;
 432
 433     if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
 434         return 0;
 435     }
 436
 437     /* Check if requested MSR is supported feature MSR */
 438     int i;
 439     for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
 440         if (kvm_feature_msrs->indices[i] == index) {
 441             break;
 442         }
 443     if (i == kvm_feature_msrs->nmsrs) {
 444         return 0; /* if the feature MSR is not supported, simply return 0 */
 445     }
 446
 447     msr_data.info.nmsrs = 1;
 448     msr_data.entries[0].index = index;
 449
 450     ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
 451     if (ret != 1) {
 452         error_report("KVM get MSR (index=0x%x) feature failed, %s",
 453             index, strerror(-ret));
 454         exit(1);
 455     }
 456
 457     return msr_data.entries[0].data;
 458 }
 459
 460
 461 typedef struct HWPoisonPage {
 462     ram_addr_t ram_addr;
 463     QLIST_ENTRY(HWPoisonPage) list;
 464 } HWPoisonPage;
 465
 466 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 467     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 468
 469 static void kvm_unpoison_all(void *param)
 470 {
 471     HWPoisonPage *page, *next_page;
 472
 473     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 474         QLIST_REMOVE(page, list);
 475         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 476         g_free(page);
 477     }
 478 }
 479
 480 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 481 {
 482     HWPoisonPage *page;
 483
 484     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 485         if (page->ram_addr == ram_addr) {
 486             return;
 487         }
 488     }
 489     page = g_new(HWPoisonPage, 1);
 490     page->ram_addr = ram_addr;
 491     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 492 }
 493
 494 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 495                                      int *max_banks)
 496 {
 497     int r;
 498
 499     r = kvm_check_extension(s, KVM_CAP_MCE);
 500     if (r > 0) {
 501         *max_banks = r;
 502         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 503     }
 504     return -ENOSYS;
 505 }
 506
 507 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
 508 {
 509     CPUState *cs = CPU(cpu);
 510     CPUX86State *env = &cpu->env;
 511     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 512                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 513     uint64_t mcg_status = MCG_STATUS_MCIP;
 514     int flags = 0;
 515
 516     if (code == BUS_MCEERR_AR) {
 517         status |= MCI_STATUS_AR | 0x134;
 518         mcg_status |= MCG_STATUS_EIPV;
 519     } else {
 520         status |= 0xc0;
 521         mcg_status |= MCG_STATUS_RIPV;
 522     }
 523
 524     flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
 525     /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
 526      * guest kernel back into env->mcg_ext_ctl.
 527      */
 528     cpu_synchronize_state(cs);
 529     if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
 530         mcg_status |= MCG_STATUS_LMCE;
 531         flags = 0;
 532     }
 533
 534     cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
 535                        (MCM_ADDR_PHYS << 6) | 0xc, flags);
 536 }
 537
 538 static void hardware_memory_error(void)
 539 {
 540     fprintf(stderr, "Hardware memory error!\n");
 541     exit(1);
 542 }
 543
 544 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
 545 {
 546     X86CPU *cpu = X86_CPU(c);
 547     CPUX86State *env = &cpu->env;
 548     ram_addr_t ram_addr;
 549     hwaddr paddr;
 550
 551     /* If we get an action required MCE, it has been injected by KVM
 552      * while the VM was running.  An action optional MCE instead should
 553      * be coming from the main thread, which qemu_init_sigbus identifies
 554      * as the "early kill" thread.
 555      */
 556     assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
 557
 558     if ((env->mcg_cap & MCG_SER_P) && addr) {
 559         ram_addr = qemu_ram_addr_from_host(addr);
 560         if (ram_addr != RAM_ADDR_INVALID &&
 561             kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
 562             kvm_hwpoison_page_add(ram_addr);
 563             kvm_mce_inject(cpu, paddr, code);
 564             return;
 565         }
 566
 567         fprintf(stderr, "Hardware memory error for memory used by "
 568                 "QEMU itself instead of guest system!\n");
 569     }
 570
 571     if (code == BUS_MCEERR_AR) {
 572         hardware_memory_error();
 573     }
 574
 575     /* Hope we are lucky for AO MCE */
 576 }
 577
 578 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
 579 {
 580     CPUX86State *env = &cpu->env;
 581
 582     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 583         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 584         struct kvm_x86_mce mce;
 585
 586         env->exception_injected = -1;
 587
 588         /*
 589          * There must be at least one bank in use if an MCE is pending.
 590          * Find it and use its values for the event injection.
 591          */
 592         for (bank = 0; bank < bank_num; bank++) {
 593             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 594                 break;
 595             }
 596         }
 597         assert(bank < bank_num);
 598
 599         mce.bank = bank;
 600         mce.status = env->mce_banks[bank * 4 + 1];
 601         mce.mcg_status = env->mcg_status;
 602         mce.addr = env->mce_banks[bank * 4 + 2];
 603         mce.misc = env->mce_banks[bank * 4 + 3];
 604
 605         return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
 606     }
 607     return 0;
 608 }
 609
 610 static void cpu_update_state(void *opaque, int running, RunState state)
 611 {
 612     CPUX86State *env = opaque;
 613
 614     if (running) {
 615         env->tsc_valid = false;
 616     }
 617 }
 618
 619 unsigned long kvm_arch_vcpu_id(CPUState *cs)
 620 {
 621     X86CPU *cpu = X86_CPU(cs);
 622     return cpu->apic_id;
 623 }
 624
 625 #ifndef KVM_CPUID_SIGNATURE_NEXT
 626 #define KVM_CPUID_SIGNATURE_NEXT                0x40000100
 627 #endif
 628
 629 static bool hyperv_hypercall_available(X86CPU *cpu)
 630 {
 631     return cpu->hyperv_vapic ||
 632            (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
 633 }
 634
 635 static bool hyperv_enabled(X86CPU *cpu)
 636 {
 637     CPUState *cs = CPU(cpu);
 638     return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
 639            (hyperv_hypercall_available(cpu) ||
 640             cpu->hyperv_time  ||
 641             cpu->hyperv_relaxed_timing ||
 642             cpu->hyperv_crash ||
 643             cpu->hyperv_reset ||
 644             cpu->hyperv_vpindex ||
 645             cpu->hyperv_runtime ||
 646             cpu->hyperv_synic ||
 647             cpu->hyperv_stimer ||
 648             cpu->hyperv_reenlightenment ||
 649             cpu->hyperv_tlbflush ||
 650             cpu->hyperv_ipi);
 651 }
 652
 653 static int kvm_arch_set_tsc_khz(CPUState *cs)
 654 {
 655     X86CPU *cpu = X86_CPU(cs);
 656     CPUX86State *env = &cpu->env;
 657     int r;
 658
 659     if (!env->tsc_khz) {
 660         return 0;
 661     }
 662
 663     r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
 664         kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
 665         -ENOTSUP;
 666     if (r < 0) {
 667         /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
 668          * TSC frequency doesn't match the one we want.
 669          */
 670         int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
 671                        kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
 672                        -ENOTSUP;
 673         if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
 674             warn_report("TSC frequency mismatch between "
 675                         "VM (%" PRId64 " kHz) and host (%d kHz), "
 676                         "and TSC scaling unavailable",
 677                         env->tsc_khz, cur_freq);
 678             return r;
 679         }
 680     }
 681
 682     return 0;
 683 }
 684
 685 static bool tsc_is_stable_and_known(CPUX86State *env)
 686 {
 687     if (!env->tsc_khz) {
 688         return false;
 689     }
 690     return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
 691         || env->user_tsc_khz;
 692 }
 693
 694 static int hyperv_handle_properties(CPUState *cs)
 695 {
 696     X86CPU *cpu = X86_CPU(cs);
 697     CPUX86State *env = &cpu->env;
 698
 699     if (cpu->hyperv_relaxed_timing) {
 700         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 701     }
 702     if (cpu->hyperv_vapic) {
 703         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 704         env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
 705     }
 706     if (cpu->hyperv_time) {
 707         if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
 708             fprintf(stderr, "Hyper-V clocksources "
 709                     "(requested by 'hv-time' cpu flag) "
 710                     "are not supported by kernel\n");
 711             return -ENOSYS;
 712         }
 713         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 714         env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
 715         env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
 716     }
 717     if (cpu->hyperv_frequencies) {
 718         if (!has_msr_hv_frequencies) {
 719             fprintf(stderr, "Hyper-V frequency MSRs "
 720                     "(requested by 'hv-frequencies' cpu flag) "
 721                     "are not supported by kernel\n");
 722             return -ENOSYS;
 723         }
 724         env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
 725         env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
 726     }
 727     if (cpu->hyperv_crash) {
 728         if (!has_msr_hv_crash) {
 729             fprintf(stderr, "Hyper-V crash MSRs "
 730                     "(requested by 'hv-crash' cpu flag) "
 731                     "are not supported by kernel\n");
 732             return -ENOSYS;
 733         }
 734         env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
 735     }
 736     if (cpu->hyperv_reenlightenment) {
 737         if (!has_msr_hv_reenlightenment) {
 738             fprintf(stderr,
 739                     "Hyper-V Reenlightenment MSRs "
 740                     "(requested by 'hv-reenlightenment' cpu flag) "
 741                     "are not supported by kernel\n");
 742             return -ENOSYS;
 743         }
 744         env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
 745     }
 746     env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
 747     if (cpu->hyperv_reset) {
 748         if (!has_msr_hv_reset) {
 749             fprintf(stderr, "Hyper-V reset MSR "
 750                     "(requested by 'hv-reset' cpu flag) "
 751                     "is not supported by kernel\n");
 752             return -ENOSYS;
 753         }
 754         env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
 755     }
 756     if (cpu->hyperv_vpindex) {
 757         if (!has_msr_hv_vpindex) {
 758             fprintf(stderr, "Hyper-V VP_INDEX MSR "
 759                     "(requested by 'hv-vpindex' cpu flag) "
 760                     "is not supported by kernel\n");
 761             return -ENOSYS;
 762         }
 763         env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
 764     }
 765     if (cpu->hyperv_runtime) {
 766         if (!has_msr_hv_runtime) {
 767             fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
 768                     "(requested by 'hv-runtime' cpu flag) "
 769                     "is not supported by kernel\n");
 770             return -ENOSYS;
 771         }
 772         env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
 773     }
 774     if (cpu->hyperv_synic) {
 775         unsigned int cap = KVM_CAP_HYPERV_SYNIC;
 776         if (!cpu->hyperv_synic_kvm_only) {
 777             if (!cpu->hyperv_vpindex) {
 778                 fprintf(stderr, "Hyper-V SynIC "
 779                         "(requested by 'hv-synic' cpu flag) "
 780                         "requires Hyper-V VP_INDEX ('hv-vpindex')\n");
 781             return -ENOSYS;
 782             }
 783             cap = KVM_CAP_HYPERV_SYNIC2;
 784         }
 785
 786         if (!has_msr_hv_synic || !kvm_check_extension(cs->kvm_state, cap)) {
 787             fprintf(stderr, "Hyper-V SynIC (requested by 'hv-synic' cpu flag) "
 788                     "is not supported by kernel\n");
 789             return -ENOSYS;
 790         }
 791
 792         env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
 793     }
 794     if (cpu->hyperv_stimer) {
 795         if (!has_msr_hv_stimer) {
 796             fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
 797             return -ENOSYS;
 798         }
 799         env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
 800     }
 801     if (cpu->hyperv_relaxed_timing) {
 802         env->features[FEAT_HV_RECOMM_EAX] |= HV_RELAXED_TIMING_RECOMMENDED;
 803     }
 804     if (cpu->hyperv_vapic) {
 805         env->features[FEAT_HV_RECOMM_EAX] |= HV_APIC_ACCESS_RECOMMENDED;
 806     }
 807     if (cpu->hyperv_tlbflush) {
 808         if (kvm_check_extension(cs->kvm_state,
 809                                 KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
 810             fprintf(stderr, "Hyper-V TLB flush support "
 811                     "(requested by 'hv-tlbflush' cpu flag) "
 812                     " is not supported by kernel\n");
 813             return -ENOSYS;
 814         }
 815         env->features[FEAT_HV_RECOMM_EAX] |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
 816         env->features[FEAT_HV_RECOMM_EAX] |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
 817     }
 818     if (cpu->hyperv_ipi) {
 819         if (kvm_check_extension(cs->kvm_state,
 820                                 KVM_CAP_HYPERV_SEND_IPI) <= 0) {
 821             fprintf(stderr, "Hyper-V IPI send support "
 822                     "(requested by 'hv-ipi' cpu flag) "
 823                     " is not supported by kernel\n");
 824             return -ENOSYS;
 825         }
 826         env->features[FEAT_HV_RECOMM_EAX] |= HV_CLUSTER_IPI_RECOMMENDED;
 827         env->features[FEAT_HV_RECOMM_EAX] |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
 828     }
 829     if (cpu->hyperv_evmcs) {
 830         uint16_t evmcs_version;
 831
 832         if (kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
 833                                 (uintptr_t)&evmcs_version)) {
 834             fprintf(stderr, "Hyper-V Enlightened VMCS "
 835                     "(requested by 'hv-evmcs' cpu flag) "
 836                     "is not supported by kernel\n");
 837             return -ENOSYS;
 838         }
 839         env->features[FEAT_HV_RECOMM_EAX] |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
 840         env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
 841     }
 842
 843     return 0;
 844 }
 845
 846 static int hyperv_init_vcpu(X86CPU *cpu)
 847 {
 848     CPUState *cs = CPU(cpu);
 849     int ret;
 850
 851     if (cpu->hyperv_vpindex && !hv_vpindex_settable) {
 852         /*
 853          * the kernel doesn't support setting vp_index; assert that its value
 854          * is in sync
 855          */
 856         struct {
 857             struct kvm_msrs info;
 858             struct kvm_msr_entry entries[1];
 859         } msr_data = {
 860             .info.nmsrs = 1,
 861             .entries[0].index = HV_X64_MSR_VP_INDEX,
 862         };
 863
 864         ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
 865         if (ret < 0) {
 866             return ret;
 867         }
 868         assert(ret == 1);
 869
 870         if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
 871             error_report("kernel's vp_index != QEMU's vp_index");
 872             return -ENXIO;
 873         }
 874     }
 875
 876     if (cpu->hyperv_synic) {
 877         uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
 878             KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
 879         ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
 880         if (ret < 0) {
 881             error_report("failed to turn on HyperV SynIC in KVM: %s",
 882                          strerror(-ret));
 883             return ret;
 884         }
 885
 886         if (!cpu->hyperv_synic_kvm_only) {
 887             ret = hyperv_x86_synic_add(cpu);
 888             if (ret < 0) {
 889                 error_report("failed to create HyperV SynIC: %s",
 890                              strerror(-ret));
 891                 return ret;
 892             }
 893         }
 894     }
 895
 896     return 0;
 897 }
 898
 899 static Error *invtsc_mig_blocker;
 900 static Error *vmx_mig_blocker;
 901
 902 #define KVM_MAX_CPUID_ENTRIES  100
 903
 904 int kvm_arch_init_vcpu(CPUState *cs)
 905 {
 906     struct {
 907         struct kvm_cpuid2 cpuid;
 908         struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
 909     } cpuid_data;
 910     /*
 911      * The kernel defines these structs with padding fields so there
 912      * should be no extra padding in our cpuid_data struct.
 913      */
 914     QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
 915                       sizeof(struct kvm_cpuid2) +
 916                       sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
 917
 918     X86CPU *cpu = X86_CPU(cs);
 919     CPUX86State *env = &cpu->env;
 920     uint32_t limit, i, j, cpuid_i;
 921     uint32_t unused;
 922     struct kvm_cpuid_entry2 *c;
 923     uint32_t signature[3];
 924     int kvm_base = KVM_CPUID_SIGNATURE;
 925     int r;
 926     Error *local_err = NULL;
 927
 928     memset(&cpuid_data, 0, sizeof(cpuid_data));
 929
 930     cpuid_i = 0;
 931
 932     r = kvm_arch_set_tsc_khz(cs);
 933     if (r < 0) {
 934         goto fail;
 935     }
 936
 937     /* vcpu's TSC frequency is either specified by user, or following
 938      * the value used by KVM if the former is not present. In the
 939      * latter case, we query it from KVM and record in env->tsc_khz,
 940      * so that vcpu's TSC frequency can be migrated later via this field.
 941      */
 942     if (!env->tsc_khz) {
 943         r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
 944             kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
 945             -ENOTSUP;
 946         if (r > 0) {
 947             env->tsc_khz = r;
 948         }
 949     }
 950
 951     /* Paravirtualization CPUIDs */
 952     if (hyperv_enabled(cpu)) {
 953         c = &cpuid_data.entries[cpuid_i++];
 954         c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
 955         if (!cpu->hyperv_vendor_id) {
 956             memcpy(signature, "Microsoft Hv", 12);
 957         } else {
 958             size_t len = strlen(cpu->hyperv_vendor_id);
 959
 960             if (len > 12) {
 961                 error_report("hv-vendor-id truncated to 12 characters");
 962                 len = 12;
 963             }
 964             memset(signature, 0, 12);
 965             memcpy(signature, cpu->hyperv_vendor_id, len);
 966         }
 967         c->eax = cpu->hyperv_evmcs ?
 968             HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
 969         c->ebx = signature[0];
 970         c->ecx = signature[1];
 971         c->edx = signature[2];
 972
 973         c = &cpuid_data.entries[cpuid_i++];
 974         c->function = HV_CPUID_INTERFACE;
 975         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 976         c->eax = signature[0];
 977         c->ebx = 0;
 978         c->ecx = 0;
 979         c->edx = 0;
 980
 981         c = &cpuid_data.entries[cpuid_i++];
 982         c->function = HV_CPUID_VERSION;
 983         c->eax = 0x00001bbc;
 984         c->ebx = 0x00060001;
 985
 986         c = &cpuid_data.entries[cpuid_i++];
 987         c->function = HV_CPUID_FEATURES;
 988         r = hyperv_handle_properties(cs);
 989         if (r) {
 990             return r;
 991         }
 992         c->eax = env->features[FEAT_HYPERV_EAX];
 993         c->ebx = env->features[FEAT_HYPERV_EBX];
 994         c->edx = env->features[FEAT_HYPERV_EDX];
 995
 996         c = &cpuid_data.entries[cpuid_i++];
 997         c->function = HV_CPUID_ENLIGHTMENT_INFO;
 998
 999         c->eax = env->features[FEAT_HV_RECOMM_EAX];
1000         c->ebx = cpu->hyperv_spinlock_attempts;
1001
1002         c = &cpuid_data.entries[cpuid_i++];
1003         c->function = HV_CPUID_IMPLEMENT_LIMITS;
1004
1005         c->eax = cpu->hv_max_vps;
1006         c->ebx = 0x40;
1007
1008         kvm_base = KVM_CPUID_SIGNATURE_NEXT;
1009         has_msr_hv_hypercall = true;
1010
1011         if (cpu->hyperv_evmcs) {
1012             __u32 function;
1013
1014             /* Create zeroed 0x40000006..0x40000009 leaves */
1015             for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1016                  function < HV_CPUID_NESTED_FEATURES; function++) {
1017                 c = &cpuid_data.entries[cpuid_i++];
1018                 c->function = function;
1019             }
1020
1021             c = &cpuid_data.entries[cpuid_i++];
1022             c->function = HV_CPUID_NESTED_FEATURES;
1023             c->eax = env->features[FEAT_HV_NESTED_EAX];
1024         }
1025     }
1026
1027     if (cpu->expose_kvm) {
1028         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1029         c = &cpuid_data.entries[cpuid_i++];
1030         c->function = KVM_CPUID_SIGNATURE | kvm_base;
1031         c->eax = KVM_CPUID_FEATURES | kvm_base;
1032         c->ebx = signature[0];
1033         c->ecx = signature[1];
1034         c->edx = signature[2];
1035
1036         c = &cpuid_data.entries[cpuid_i++];
1037         c->function = KVM_CPUID_FEATURES | kvm_base;
1038         c->eax = env->features[FEAT_KVM];
1039         c->edx = env->features[FEAT_KVM_HINTS];
1040     }
1041
1042     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1043
1044     for (i = 0; i <= limit; i++) {
1045         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1046             fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1047             abort();
1048         }
1049         c = &cpuid_data.entries[cpuid_i++];
1050
1051         switch (i) {
1052         case 2: {
1053             /* Keep reading function 2 till all the input is received */
1054             int times;
1055
1056             c->function = i;
1057             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1058                        KVM_CPUID_FLAG_STATE_READ_NEXT;
1059             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1060             times = c->eax & 0xff;
1061
1062             for (j = 1; j < times; ++j) {
1063                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1064                     fprintf(stderr, "cpuid_data is full, no space for "
1065                             "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1066                     abort();
1067                 }
1068                 c = &cpuid_data.entries[cpuid_i++];
1069                 c->function = i;
1070                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1071                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1072             }
1073             break;
1074         }
1075         case 4:
1076         case 0xb:
1077         case 0xd:
1078             for (j = 0; ; j++) {
1079                 if (i == 0xd && j == 64) {
1080                     break;
1081                 }
1082                 c->function = i;
1083                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1084                 c->index = j;
1085                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1086
1087                 if (i == 4 && c->eax == 0) {
1088                     break;
1089                 }
1090                 if (i == 0xb && !(c->ecx & 0xff00)) {
1091                     break;
1092                 }
1093                 if (i == 0xd && c->eax == 0) {
1094                     continue;
1095                 }
1096                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1097                     fprintf(stderr, "cpuid_data is full, no space for "
1098                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1099                     abort();
1100                 }
1101                 c = &cpuid_data.entries[cpuid_i++];
1102             }
1103             break;
1104         case 0x14: {
1105             uint32_t times;
1106
1107             c->function = i;
1108             c->index = 0;
1109             c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1110             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1111             times = c->eax;
1112
1113             for (j = 1; j <= times; ++j) {
1114                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1115                     fprintf(stderr, "cpuid_data is full, no space for "
1116                                 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1117                     abort();
1118                 }
1119                 c = &cpuid_data.entries[cpuid_i++];
1120                 c->function = i;
1121                 c->index = j;
1122                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1123                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1124             }
1125             break;
1126         }
1127         default:
1128             c->function = i;
1129             c->flags = 0;
1130             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1131             break;
1132         }
1133     }
1134
1135     if (limit >= 0x0a) {
1136         uint32_t eax, edx;
1137
1138         cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1139
1140         has_architectural_pmu_version = eax & 0xff;
1141         if (has_architectural_pmu_version > 0) {
1142             num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1143
1144             /* Shouldn't be more than 32, since that's the number of bits
1145              * available in EBX to tell us _which_ counters are available.
1146              * Play it safe.
1147              */
1148             if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1149                 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1150             }
1151
1152             if (has_architectural_pmu_version > 1) {
1153                 num_architectural_pmu_fixed_counters = edx & 0x1f;
1154
1155                 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1156                     num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1157                 }
1158             }
1159         }
1160     }
1161
1162     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1163
1164     for (i = 0x80000000; i <= limit; i++) {
1165         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1166             fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1167             abort();
1168         }
1169         c = &cpuid_data.entries[cpuid_i++];
1170
1171         switch (i) {
1172         case 0x8000001d:
1173             /* Query for all AMD cache information leaves */
1174             for (j = 0; ; j++) {
1175                 c->function = i;
1176                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1177                 c->index = j;
1178                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1179
1180                 if (c->eax == 0) {
1181                     break;
1182                 }
1183                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1184                     fprintf(stderr, "cpuid_data is full, no space for "
1185                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1186                     abort();
1187                 }
1188                 c = &cpuid_data.entries[cpuid_i++];
1189             }
1190             break;
1191         default:
1192             c->function = i;
1193             c->flags = 0;
1194             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1195             break;
1196         }
1197     }
1198
1199     /* Call Centaur's CPUID instructions they are supported. */
1200     if (env->cpuid_xlevel2 > 0) {
1201         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1202
1203         for (i = 0xC0000000; i <= limit; i++) {
1204             if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1205                 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1206                 abort();
1207             }
1208             c = &cpuid_data.entries[cpuid_i++];
1209
1210             c->function = i;
1211             c->flags = 0;
1212             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1213         }
1214     }
1215
1216     cpuid_data.cpuid.nent = cpuid_i;
1217
1218     if (((env->cpuid_version >> 8)&0xF) >= 6
1219         && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1220            (CPUID_MCE | CPUID_MCA)
1221         && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1222         uint64_t mcg_cap, unsupported_caps;
1223         int banks;
1224         int ret;
1225
1226         ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1227         if (ret < 0) {
1228             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1229             return ret;
1230         }
1231
1232         if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1233             error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1234                          (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1235             return -ENOTSUP;
1236         }
1237
1238         unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1239         if (unsupported_caps) {
1240             if (unsupported_caps & MCG_LMCE_P) {
1241                 error_report("kvm: LMCE not supported");
1242                 return -ENOTSUP;
1243             }
1244             warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1245                         unsupported_caps);
1246         }
1247
1248         env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1249         ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1250         if (ret < 0) {
1251             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1252             return ret;
1253         }
1254     }
1255
1256     qemu_add_vm_change_state_handler(cpu_update_state, env);
1257
1258     c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1259     if (c) {
1260         has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1261                                   !!(c->ecx & CPUID_EXT_SMX);
1262     }
1263
1264     if ((env->features[FEAT_1_ECX] & CPUID_EXT_VMX) && !vmx_mig_blocker) {
1265         error_setg(&vmx_mig_blocker,
1266                    "Nested VMX virtualization does not support live migration yet");
1267         r = migrate_add_blocker(vmx_mig_blocker, &local_err);
1268         if (local_err) {
1269             error_report_err(local_err);
1270             error_free(vmx_mig_blocker);
1271             return r;
1272         }
1273     }
1274
1275     if (env->mcg_cap & MCG_LMCE_P) {
1276         has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1277     }
1278
1279     if (!env->user_tsc_khz) {
1280         if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1281             invtsc_mig_blocker == NULL) {
1282             error_setg(&invtsc_mig_blocker,
1283                        "State blocked by non-migratable CPU device"
1284                        " (invtsc flag)");
1285             r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1286             if (local_err) {
1287                 error_report_err(local_err);
1288                 error_free(invtsc_mig_blocker);
1289                 return r;
1290             }
1291         }
1292     }
1293
1294     if (cpu->vmware_cpuid_freq
1295         /* Guests depend on 0x40000000 to detect this feature, so only expose
1296          * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1297         && cpu->expose_kvm
1298         && kvm_base == KVM_CPUID_SIGNATURE
1299         /* TSC clock must be stable and known for this feature. */
1300         && tsc_is_stable_and_known(env)) {
1301
1302         c = &cpuid_data.entries[cpuid_i++];
1303         c->function = KVM_CPUID_SIGNATURE | 0x10;
1304         c->eax = env->tsc_khz;
1305         /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1306          * APIC_BUS_CYCLE_NS */
1307         c->ebx = 1000000;
1308         c->ecx = c->edx = 0;
1309
1310         c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1311         c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1312     }
1313
1314     cpuid_data.cpuid.nent = cpuid_i;
1315
1316     cpuid_data.cpuid.padding = 0;
1317     r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1318     if (r) {
1319         goto fail;
1320     }
1321
1322     if (has_xsave) {
1323         env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1324     }
1325     cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1326
1327     if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1328         has_msr_tsc_aux = false;
1329     }
1330
1331     r = hyperv_init_vcpu(cpu);
1332     if (r) {
1333         goto fail;
1334     }
1335
1336     return 0;
1337
1338  fail:
1339     migrate_del_blocker(invtsc_mig_blocker);
1340     return r;
1341 }
1342
1343 void kvm_arch_reset_vcpu(X86CPU *cpu)
1344 {
1345     CPUX86State *env = &cpu->env;
1346
1347     env->xcr0 = 1;
1348     if (kvm_irqchip_in_kernel()) {
1349         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1350                                           KVM_MP_STATE_UNINITIALIZED;
1351     } else {
1352         env->mp_state = KVM_MP_STATE_RUNNABLE;
1353     }
1354
1355     if (cpu->hyperv_synic) {
1356         int i;
1357         for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1358             env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1359         }
1360
1361         hyperv_x86_synic_reset(cpu);
1362     }
1363 }
1364
1365 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1366 {
1367     CPUX86State *env = &cpu->env;
1368
1369     /* APs get directly into wait-for-SIPI state.  */
1370     if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1371         env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1372     }
1373 }
1374
1375 static int kvm_get_supported_feature_msrs(KVMState *s)
1376 {
1377     int ret = 0;
1378
1379     if (kvm_feature_msrs != NULL) {
1380         return 0;
1381     }
1382
1383     if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1384         return 0;
1385     }
1386
1387     struct kvm_msr_list msr_list;
1388
1389     msr_list.nmsrs = 0;
1390     ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1391     if (ret < 0 && ret != -E2BIG) {
1392         error_report("Fetch KVM feature MSR list failed: %s",
1393             strerror(-ret));
1394         return ret;
1395     }
1396
1397     assert(msr_list.nmsrs > 0);
1398     kvm_feature_msrs = (struct kvm_msr_list *) \
1399         g_malloc0(sizeof(msr_list) +
1400                  msr_list.nmsrs * sizeof(msr_list.indices[0]));
1401
1402     kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1403     ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1404
1405     if (ret < 0) {
1406         error_report("Fetch KVM feature MSR list failed: %s",
1407             strerror(-ret));
1408         g_free(kvm_feature_msrs);
1409         kvm_feature_msrs = NULL;
1410         return ret;
1411     }
1412
1413     return 0;
1414 }
1415
1416 static int kvm_get_supported_msrs(KVMState *s)
1417 {
1418     static int kvm_supported_msrs;
1419     int ret = 0;
1420
1421     /* first time */
1422     if (kvm_supported_msrs == 0) {
1423         struct kvm_msr_list msr_list, *kvm_msr_list;
1424
1425         kvm_supported_msrs = -1;
1426
1427         /* Obtain MSR list from KVM.  These are the MSRs that we must
1428          * save/restore */
1429         msr_list.nmsrs = 0;
1430         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1431         if (ret < 0 && ret != -E2BIG) {
1432             return ret;
1433         }
1434         /* Old kernel modules had a bug and could write beyond the provided
1435            memory. Allocate at least a safe amount of 1K. */
1436         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1437                                               msr_list.nmsrs *
1438                                               sizeof(msr_list.indices[0])));
1439
1440         kvm_msr_list->nmsrs = msr_list.nmsrs;
1441         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1442         if (ret >= 0) {
1443             int i;
1444
1445             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1446                 switch (kvm_msr_list->indices[i]) {
1447                 case MSR_STAR:
1448                     has_msr_star = true;
1449                     break;
1450                 case MSR_VM_HSAVE_PA:
1451                     has_msr_hsave_pa = true;
1452                     break;
1453                 case MSR_TSC_AUX:
1454                     has_msr_tsc_aux = true;
1455                     break;
1456                 case MSR_TSC_ADJUST:
1457                     has_msr_tsc_adjust = true;
1458                     break;
1459                 case MSR_IA32_TSCDEADLINE:
1460                     has_msr_tsc_deadline = true;
1461                     break;
1462                 case MSR_IA32_SMBASE:
1463                     has_msr_smbase = true;
1464                     break;
1465                 case MSR_SMI_COUNT:
1466                     has_msr_smi_count = true;
1467                     break;
1468                 case MSR_IA32_MISC_ENABLE:
1469                     has_msr_misc_enable = true;
1470                     break;
1471                 case MSR_IA32_BNDCFGS:
1472                     has_msr_bndcfgs = true;
1473                     break;
1474                 case MSR_IA32_XSS:
1475                     has_msr_xss = true;
1476                     break;
1477                 case HV_X64_MSR_CRASH_CTL:
1478                     has_msr_hv_crash = true;
1479                     break;
1480                 case HV_X64_MSR_RESET:
1481                     has_msr_hv_reset = true;
1482                     break;
1483                 case HV_X64_MSR_VP_INDEX:
1484                     has_msr_hv_vpindex = true;
1485                     break;
1486                 case HV_X64_MSR_VP_RUNTIME:
1487                     has_msr_hv_runtime = true;
1488                     break;
1489                 case HV_X64_MSR_SCONTROL:
1490                     has_msr_hv_synic = true;
1491                     break;
1492                 case HV_X64_MSR_STIMER0_CONFIG:
1493                     has_msr_hv_stimer = true;
1494                     break;
1495                 case HV_X64_MSR_TSC_FREQUENCY:
1496                     has_msr_hv_frequencies = true;
1497                     break;
1498                 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1499                     has_msr_hv_reenlightenment = true;
1500                     break;
1501                 case MSR_IA32_SPEC_CTRL:
1502                     has_msr_spec_ctrl = true;
1503                     break;
1504                 case MSR_VIRT_SSBD:
1505                     has_msr_virt_ssbd = true;
1506                     break;
1507                 case MSR_IA32_ARCH_CAPABILITIES:
1508                     has_msr_arch_capabs = true;
1509                     break;
1510                 }
1511             }
1512         }
1513
1514         g_free(kvm_msr_list);
1515     }
1516
1517     return ret;
1518 }
1519
1520 static Notifier smram_machine_done;
1521 static KVMMemoryListener smram_listener;
1522 static AddressSpace smram_address_space;
1523 static MemoryRegion smram_as_root;
1524 static MemoryRegion smram_as_mem;
1525
1526 static void register_smram_listener(Notifier *n, void *unused)
1527 {
1528     MemoryRegion *smram =
1529         (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1530
1531     /* Outer container... */
1532     memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1533     memory_region_set_enabled(&smram_as_root, true);
1534
1535     /* ... with two regions inside: normal system memory with low
1536      * priority, and...
1537      */
1538     memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1539                              get_system_memory(), 0, ~0ull);
1540     memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1541     memory_region_set_enabled(&smram_as_mem, true);
1542
1543     if (smram) {
1544         /* ... SMRAM with higher priority */
1545         memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1546         memory_region_set_enabled(smram, true);
1547     }
1548
1549     address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1550     kvm_memory_listener_register(kvm_state, &smram_listener,
1551                                  &smram_address_space, 1);
1552 }
1553
1554 int kvm_arch_init(MachineState *ms, KVMState *s)
1555 {
1556     uint64_t identity_base = 0xfffbc000;
1557     uint64_t shadow_mem;
1558     int ret;
1559     struct utsname utsname;
1560
1561     has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1562     has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1563     has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1564
1565     hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1566
1567     ret = kvm_get_supported_msrs(s);
1568     if (ret < 0) {
1569         return ret;
1570     }
1571
1572     kvm_get_supported_feature_msrs(s);
1573
1574     uname(&utsname);
1575     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1576
1577     /*
1578      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1579      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
1580      * Since these must be part of guest physical memory, we need to allocate
1581      * them, both by setting their start addresses in the kernel and by
1582      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1583      *
1584      * Older KVM versions may not support setting the identity map base. In
1585      * that case we need to stick with the default, i.e. a 256K maximum BIOS
1586      * size.
1587      */
1588     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1589         /* Allows up to 16M BIOSes. */
1590         identity_base = 0xfeffc000;
1591
1592         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1593         if (ret < 0) {
1594             return ret;
1595         }
1596     }
1597
1598     /* Set TSS base one page after EPT identity map. */
1599     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1600     if (ret < 0) {
1601         return ret;
1602     }
1603
1604     /* Tell fw_cfg to notify the BIOS to reserve the range. */
1605     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1606     if (ret < 0) {
1607         fprintf(stderr, "e820_add_entry() table is full\n");
1608         return ret;
1609     }
1610     qemu_register_reset(kvm_unpoison_all, NULL);
1611
1612     shadow_mem = machine_kvm_shadow_mem(ms);
1613     if (shadow_mem != -1) {
1614         shadow_mem /= 4096;
1615         ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1616         if (ret < 0) {
1617             return ret;
1618         }
1619     }
1620
1621     if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1622         object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1623         pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1624         smram_machine_done.notify = register_smram_listener;
1625         qemu_add_machine_init_done_notifier(&smram_machine_done);
1626     }
1627
1628     if (enable_cpu_pm) {
1629         int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1630         int ret;
1631
1632 /* Work around for kernel header with a typo. TODO: fix header and drop. */
1633 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1634 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1635 #endif
1636         if (disable_exits) {
1637             disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1638                               KVM_X86_DISABLE_EXITS_HLT |
1639                               KVM_X86_DISABLE_EXITS_PAUSE);
1640         }
1641
1642         ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1643                                 disable_exits);
1644         if (ret < 0) {
1645             error_report("kvm: guest stopping CPU not supported: %s",
1646                          strerror(-ret));
1647         }
1648     }
1649
1650     return 0;
1651 }
1652
1653 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1654 {
1655     lhs->selector = rhs->selector;
1656     lhs->base = rhs->base;
1657     lhs->limit = rhs->limit;
1658     lhs->type = 3;
1659     lhs->present = 1;
1660     lhs->dpl = 3;
1661     lhs->db = 0;
1662     lhs->s = 1;
1663     lhs->l = 0;
1664     lhs->g = 0;
1665     lhs->avl = 0;
1666     lhs->unusable = 0;
1667 }
1668
1669 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1670 {
1671     unsigned flags = rhs->flags;
1672     lhs->selector = rhs->selector;
1673     lhs->base = rhs->base;
1674     lhs->limit = rhs->limit;
1675     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1676     lhs->present = (flags & DESC_P_MASK) != 0;
1677     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1678     lhs->db = (flags >> DESC_B_SHIFT) & 1;
1679     lhs->s = (flags & DESC_S_MASK) != 0;
1680     lhs->l = (flags >> DESC_L_SHIFT) & 1;
1681     lhs->g = (flags & DESC_G_MASK) != 0;
1682     lhs->avl = (flags & DESC_AVL_MASK) != 0;
1683     lhs->unusable = !lhs->present;
1684     lhs->padding = 0;
1685 }
1686
1687 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1688 {
1689     lhs->selector = rhs->selector;
1690     lhs->base = rhs->base;
1691     lhs->limit = rhs->limit;
1692     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1693                  ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1694                  (rhs->dpl << DESC_DPL_SHIFT) |
1695                  (rhs->db << DESC_B_SHIFT) |
1696                  (rhs->s * DESC_S_MASK) |
1697                  (rhs->l << DESC_L_SHIFT) |
1698                  (rhs->g * DESC_G_MASK) |
1699                  (rhs->avl * DESC_AVL_MASK);
1700 }
1701
1702 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1703 {
1704     if (set) {
1705         *kvm_reg = *qemu_reg;
1706     } else {
1707         *qemu_reg = *kvm_reg;
1708     }
1709 }
1710
1711 static int kvm_getput_regs(X86CPU *cpu, int set)
1712 {
1713     CPUX86State *env = &cpu->env;
1714     struct kvm_regs regs;
1715     int ret = 0;
1716
1717     if (!set) {
1718         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1719         if (ret < 0) {
1720             return ret;
1721         }
1722     }
1723
1724     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1725     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1726     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1727     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1728     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1729     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1730     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1731     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1732 #ifdef TARGET_X86_64
1733     kvm_getput_reg(&regs.r8, &env->regs[8], set);
1734     kvm_getput_reg(&regs.r9, &env->regs[9], set);
1735     kvm_getput_reg(&regs.r10, &env->regs[10], set);
1736     kvm_getput_reg(&regs.r11, &env->regs[11], set);
1737     kvm_getput_reg(&regs.r12, &env->regs[12], set);
1738     kvm_getput_reg(&regs.r13, &env->regs[13], set);
1739     kvm_getput_reg(&regs.r14, &env->regs[14], set);
1740     kvm_getput_reg(&regs.r15, &env->regs[15], set);
1741 #endif
1742
1743     kvm_getput_reg(&regs.rflags, &env->eflags, set);
1744     kvm_getput_reg(&regs.rip, &env->eip, set);
1745
1746     if (set) {
1747         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1748     }
1749
1750     return ret;
1751 }
1752
1753 static int kvm_put_fpu(X86CPU *cpu)
1754 {
1755     CPUX86State *env = &cpu->env;
1756     struct kvm_fpu fpu;
1757     int i;
1758
1759     memset(&fpu, 0, sizeof fpu);
1760     fpu.fsw = env->fpus & ~(7 << 11);
1761     fpu.fsw |= (env->fpstt & 7) << 11;
1762     fpu.fcw = env->fpuc;
1763     fpu.last_opcode = env->fpop;
1764     fpu.last_ip = env->fpip;
1765     fpu.last_dp = env->fpdp;
1766     for (i = 0; i < 8; ++i) {
1767         fpu.ftwx |= (!env->fptags[i]) << i;
1768     }
1769     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1770     for (i = 0; i < CPU_NB_REGS; i++) {
1771         stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1772         stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1773     }
1774     fpu.mxcsr = env->mxcsr;
1775
1776     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1777 }
1778
1779 #define XSAVE_FCW_FSW     0
1780 #define XSAVE_FTW_FOP     1
1781 #define XSAVE_CWD_RIP     2
1782 #define XSAVE_CWD_RDP     4
1783 #define XSAVE_MXCSR       6
1784 #define XSAVE_ST_SPACE    8
1785 #define XSAVE_XMM_SPACE   40
1786 #define XSAVE_XSTATE_BV   128
1787 #define XSAVE_YMMH_SPACE  144
1788 #define XSAVE_BNDREGS     240
1789 #define XSAVE_BNDCSR      256
1790 #define XSAVE_OPMASK      272
1791 #define XSAVE_ZMM_Hi256   288
1792 #define XSAVE_Hi16_ZMM    416
1793 #define XSAVE_PKRU        672
1794
1795 #define XSAVE_BYTE_OFFSET(word_offset) \
1796     ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
1797
1798 #define ASSERT_OFFSET(word_offset, field) \
1799     QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1800                       offsetof(X86XSaveArea, field))
1801
1802 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1803 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1804 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1805 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1806 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1807 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1808 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1809 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1810 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1811 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1812 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1813 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1814 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1815 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1816 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1817
1818 static int kvm_put_xsave(X86CPU *cpu)
1819 {
1820     CPUX86State *env = &cpu->env;
1821     X86XSaveArea *xsave = env->xsave_buf;
1822
1823     if (!has_xsave) {
1824         return kvm_put_fpu(cpu);
1825     }
1826     x86_cpu_xsave_all_areas(cpu, xsave);
1827
1828     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1829 }
1830
1831 static int kvm_put_xcrs(X86CPU *cpu)
1832 {
1833     CPUX86State *env = &cpu->env;
1834     struct kvm_xcrs xcrs = {};
1835
1836     if (!has_xcrs) {
1837         return 0;
1838     }
1839
1840     xcrs.nr_xcrs = 1;
1841     xcrs.flags = 0;
1842     xcrs.xcrs[0].xcr = 0;
1843     xcrs.xcrs[0].value = env->xcr0;
1844     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1845 }
1846
1847 static int kvm_put_sregs(X86CPU *cpu)
1848 {
1849     CPUX86State *env = &cpu->env;
1850     struct kvm_sregs sregs;
1851
1852     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1853     if (env->interrupt_injected >= 0) {
1854         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1855                 (uint64_t)1 << (env->interrupt_injected % 64);
1856     }
1857
1858     if ((env->eflags & VM_MASK)) {
1859         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1860         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1861         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1862         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1863         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1864         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1865     } else {
1866         set_seg(&sregs.cs, &env->segs[R_CS]);
1867         set_seg(&sregs.ds, &env->segs[R_DS]);
1868         set_seg(&sregs.es, &env->segs[R_ES]);
1869         set_seg(&sregs.fs, &env->segs[R_FS]);
1870         set_seg(&sregs.gs, &env->segs[R_GS]);
1871         set_seg(&sregs.ss, &env->segs[R_SS]);
1872     }
1873
1874     set_seg(&sregs.tr, &env->tr);
1875     set_seg(&sregs.ldt, &env->ldt);
1876
1877     sregs.idt.limit = env->idt.limit;
1878     sregs.idt.base = env->idt.base;
1879     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1880     sregs.gdt.limit = env->gdt.limit;
1881     sregs.gdt.base = env->gdt.base;
1882     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1883
1884     sregs.cr0 = env->cr[0];
1885     sregs.cr2 = env->cr[2];
1886     sregs.cr3 = env->cr[3];
1887     sregs.cr4 = env->cr[4];
1888
1889     sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1890     sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1891
1892     sregs.efer = env->efer;
1893
1894     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1895 }
1896
1897 static void kvm_msr_buf_reset(X86CPU *cpu)
1898 {
1899     memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1900 }
1901
1902 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1903 {
1904     struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1905     void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1906     struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1907
1908     assert((void *)(entry + 1) <= limit);
1909
1910     entry->index = index;
1911     entry->reserved = 0;
1912     entry->data = value;
1913     msrs->nmsrs++;
1914 }
1915
1916 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1917 {
1918     kvm_msr_buf_reset(cpu);
1919     kvm_msr_entry_add(cpu, index, value);
1920
1921     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1922 }
1923
1924 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1925 {
1926     int ret;
1927
1928     ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1929     assert(ret == 1);
1930 }
1931
1932 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1933 {
1934     CPUX86State *env = &cpu->env;
1935     int ret;
1936
1937     if (!has_msr_tsc_deadline) {
1938         return 0;
1939     }
1940
1941     ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1942     if (ret < 0) {
1943         return ret;
1944     }
1945
1946     assert(ret == 1);
1947     return 0;
1948 }
1949
1950 /*
1951  * Provide a separate write service for the feature control MSR in order to
1952  * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1953  * before writing any other state because forcibly leaving nested mode
1954  * invalidates the VCPU state.
1955  */
1956 static int kvm_put_msr_feature_control(X86CPU *cpu)
1957 {
1958     int ret;
1959
1960     if (!has_msr_feature_control) {
1961         return 0;
1962     }
1963
1964     ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1965                           cpu->env.msr_ia32_feature_control);
1966     if (ret < 0) {
1967         return ret;
1968     }
1969
1970     assert(ret == 1);
1971     return 0;
1972 }
1973
1974 static int kvm_put_msrs(X86CPU *cpu, int level)
1975 {
1976     CPUX86State *env = &cpu->env;
1977     int i;
1978     int ret;
1979
1980     kvm_msr_buf_reset(cpu);
1981
1982     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1983     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1984     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1985     kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1986     if (has_msr_star) {
1987         kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1988     }
1989     if (has_msr_hsave_pa) {
1990         kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1991     }
1992     if (has_msr_tsc_aux) {
1993         kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1994     }
1995     if (has_msr_tsc_adjust) {
1996         kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1997     }
1998     if (has_msr_misc_enable) {
1999         kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
2000                           env->msr_ia32_misc_enable);
2001     }
2002     if (has_msr_smbase) {
2003         kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
2004     }
2005     if (has_msr_smi_count) {
2006         kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2007     }
2008     if (has_msr_bndcfgs) {
2009         kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
2010     }
2011     if (has_msr_xss) {
2012         kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
2013     }
2014     if (has_msr_spec_ctrl) {
2015         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2016     }
2017     if (has_msr_virt_ssbd) {
2018         kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2019     }
2020
2021 #ifdef TARGET_X86_64
2022     if (lm_capable_kernel) {
2023         kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2024         kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2025         kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2026         kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
2027     }
2028 #endif
2029
2030     /* If host supports feature MSR, write down. */
2031     if (has_msr_arch_capabs) {
2032         kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2033                           env->features[FEAT_ARCH_CAPABILITIES]);
2034     }
2035
2036     /*
2037      * The following MSRs have side effects on the guest or are too heavy
2038      * for normal writeback. Limit them to reset or full state updates.
2039      */
2040     if (level >= KVM_PUT_RESET_STATE) {
2041         kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2042         kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2043         kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
2044         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2045             kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
2046         }
2047         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2048             kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2049         }
2050         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2051             kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2052         }
2053         if (has_architectural_pmu_version > 0) {
2054             if (has_architectural_pmu_version > 1) {
2055                 /* Stop the counter.  */
2056                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2057                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2058             }
2059
2060             /* Set the counter values.  */
2061             for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2062                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2063                                   env->msr_fixed_counters[i]);
2064             }
2065             for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2066                 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2067                                   env->msr_gp_counters[i]);
2068                 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2069                                   env->msr_gp_evtsel[i]);
2070             }
2071             if (has_architectural_pmu_version > 1) {
2072                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2073                                   env->msr_global_status);
2074                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2075                                   env->msr_global_ovf_ctrl);
2076
2077                 /* Now start the PMU.  */
2078                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2079                                   env->msr_fixed_ctr_ctrl);
2080                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2081                                   env->msr_global_ctrl);
2082             }
2083         }
2084         /*
2085          * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2086          * only sync them to KVM on the first cpu
2087          */
2088         if (current_cpu == first_cpu) {
2089             if (has_msr_hv_hypercall) {
2090                 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2091                                   env->msr_hv_guest_os_id);
2092                 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2093                                   env->msr_hv_hypercall);
2094             }
2095             if (cpu->hyperv_time) {
2096                 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2097                                   env->msr_hv_tsc);
2098             }
2099             if (cpu->hyperv_reenlightenment) {
2100                 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2101                                   env->msr_hv_reenlightenment_control);
2102                 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2103                                   env->msr_hv_tsc_emulation_control);
2104                 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2105                                   env->msr_hv_tsc_emulation_status);
2106             }
2107         }
2108         if (cpu->hyperv_vapic) {
2109             kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2110                               env->msr_hv_vapic);
2111         }
2112         if (has_msr_hv_crash) {
2113             int j;
2114
2115             for (j = 0; j < HV_CRASH_PARAMS; j++)
2116                 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2117                                   env->msr_hv_crash_params[j]);
2118
2119             kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2120         }
2121         if (has_msr_hv_runtime) {
2122             kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2123         }
2124         if (cpu->hyperv_vpindex && hv_vpindex_settable) {
2125             kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2126                               hyperv_vp_index(CPU(cpu)));
2127         }
2128         if (cpu->hyperv_synic) {
2129             int j;
2130
2131             kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2132
2133             kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2134                               env->msr_hv_synic_control);
2135             kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
2136                               env->msr_hv_synic_evt_page);
2137             kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
2138                               env->msr_hv_synic_msg_page);
2139
2140             for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
2141                 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
2142                                   env->msr_hv_synic_sint[j]);
2143             }
2144         }
2145         if (has_msr_hv_stimer) {
2146             int j;
2147
2148             for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
2149                 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
2150                                 env->msr_hv_stimer_config[j]);
2151             }
2152
2153             for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2154                 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2155                                 env->msr_hv_stimer_count[j]);
2156             }
2157         }
2158         if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2159             uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2160
2161             kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2162             kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2163             kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2164             kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2165             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2166             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2167             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2168             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2169             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2170             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2171             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2172             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2173             for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2174                 /* The CPU GPs if we write to a bit above the physical limit of
2175                  * the host CPU (and KVM emulates that)
2176                  */
2177                 uint64_t mask = env->mtrr_var[i].mask;
2178                 mask &= phys_mask;
2179
2180                 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2181                                   env->mtrr_var[i].base);
2182                 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2183             }
2184         }
2185         if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2186             int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2187                                                     0x14, 1, R_EAX) & 0x7;
2188
2189             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2190                             env->msr_rtit_ctrl);
2191             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2192                             env->msr_rtit_status);
2193             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2194                             env->msr_rtit_output_base);
2195             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2196                             env->msr_rtit_output_mask);
2197             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2198                             env->msr_rtit_cr3_match);
2199             for (i = 0; i < addr_num; i++) {
2200                 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2201                             env->msr_rtit_addrs[i]);
2202             }
2203         }
2204
2205         /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2206          *       kvm_put_msr_feature_control. */
2207     }
2208     if (env->mcg_cap) {
2209         int i;
2210
2211         kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2212         kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2213         if (has_msr_mcg_ext_ctl) {
2214             kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2215         }
2216         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2217             kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2218         }
2219     }
2220
2221     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2222     if (ret < 0) {
2223         return ret;
2224     }
2225
2226     if (ret < cpu->kvm_msr_buf->nmsrs) {
2227         struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2228         error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2229                      (uint32_t)e->index, (uint64_t)e->data);
2230     }
2231
2232     assert(ret == cpu->kvm_msr_buf->nmsrs);
2233     return 0;
2234 }
2235
2236
2237 static int kvm_get_fpu(X86CPU *cpu)
2238 {
2239     CPUX86State *env = &cpu->env;
2240     struct kvm_fpu fpu;
2241     int i, ret;
2242
2243     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
2244     if (ret < 0) {
2245         return ret;
2246     }
2247
2248     env->fpstt = (fpu.fsw >> 11) & 7;
2249     env->fpus = fpu.fsw;
2250     env->fpuc = fpu.fcw;
2251     env->fpop = fpu.last_opcode;
2252     env->fpip = fpu.last_ip;
2253     env->fpdp = fpu.last_dp;
2254     for (i = 0; i < 8; ++i) {
2255         env->fptags[i] = !((fpu.ftwx >> i) & 1);
2256     }
2257     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
2258     for (i = 0; i < CPU_NB_REGS; i++) {
2259         env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2260         env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
2261     }
2262     env->mxcsr = fpu.mxcsr;
2263
2264     return 0;
2265 }
2266
2267 static int kvm_get_xsave(X86CPU *cpu)
2268 {
2269     CPUX86State *env = &cpu->env;
2270     X86XSaveArea *xsave = env->xsave_buf;
2271     int ret;
2272
2273     if (!has_xsave) {
2274         return kvm_get_fpu(cpu);
2275     }
2276
2277     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
2278     if (ret < 0) {
2279         return ret;
2280     }
2281     x86_cpu_xrstor_all_areas(cpu, xsave);
2282
2283     return 0;
2284 }
2285
2286 static int kvm_get_xcrs(X86CPU *cpu)
2287 {
2288     CPUX86State *env = &cpu->env;
2289     int i, ret;
2290     struct kvm_xcrs xcrs;
2291
2292     if (!has_xcrs) {
2293         return 0;
2294     }
2295
2296     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
2297     if (ret < 0) {
2298         return ret;
2299     }
2300
2301     for (i = 0; i < xcrs.nr_xcrs; i++) {
2302         /* Only support xcr0 now */
2303         if (xcrs.xcrs[i].xcr == 0) {
2304             env->xcr0 = xcrs.xcrs[i].value;
2305             break;
2306         }
2307     }
2308     return 0;
2309 }
2310
2311 static int kvm_get_sregs(X86CPU *cpu)
2312 {
2313     CPUX86State *env = &cpu->env;
2314     struct kvm_sregs sregs;
2315     int bit, i, ret;
2316
2317     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
2318     if (ret < 0) {
2319         return ret;
2320     }
2321
2322     /* There can only be one pending IRQ set in the bitmap at a time, so try
2323        to find it and save its number instead (-1 for none). */
2324     env->interrupt_injected = -1;
2325     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2326         if (sregs.interrupt_bitmap[i]) {
2327             bit = ctz64(sregs.interrupt_bitmap[i]);
2328             env->interrupt_injected = i * 64 + bit;
2329             break;
2330         }
2331     }
2332
2333     get_seg(&env->segs[R_CS], &sregs.cs);
2334     get_seg(&env->segs[R_DS], &sregs.ds);
2335     get_seg(&env->segs[R_ES], &sregs.es);
2336     get_seg(&env->segs[R_FS], &sregs.fs);
2337     get_seg(&env->segs[R_GS], &sregs.gs);
2338     get_seg(&env->segs[R_SS], &sregs.ss);
2339
2340     get_seg(&env->tr, &sregs.tr);
2341     get_seg(&env->ldt, &sregs.ldt);
2342
2343     env->idt.limit = sregs.idt.limit;
2344     env->idt.base = sregs.idt.base;
2345     env->gdt.limit = sregs.gdt.limit;
2346     env->gdt.base = sregs.gdt.base;
2347
2348     env->cr[0] = sregs.cr0;
2349     env->cr[2] = sregs.cr2;
2350     env->cr[3] = sregs.cr3;
2351     env->cr[4] = sregs.cr4;
2352
2353     env->efer = sregs.efer;
2354
2355     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2356     x86_update_hflags(env);
2357
2358     return 0;
2359 }
2360
2361 static int kvm_get_msrs(X86CPU *cpu)
2362 {
2363     CPUX86State *env = &cpu->env;
2364     struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2365     int ret, i;
2366     uint64_t mtrr_top_bits;
2367
2368     kvm_msr_buf_reset(cpu);
2369
2370     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2371     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2372     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2373     kvm_msr_entry_add(cpu, MSR_PAT, 0);
2374     if (has_msr_star) {
2375         kvm_msr_entry_add(cpu, MSR_STAR, 0);
2376     }
2377     if (has_msr_hsave_pa) {
2378         kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2379     }
2380     if (has_msr_tsc_aux) {
2381         kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2382     }
2383     if (has_msr_tsc_adjust) {
2384         kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2385     }
2386     if (has_msr_tsc_deadline) {
2387         kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2388     }
2389     if (has_msr_misc_enable) {
2390         kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2391     }
2392     if (has_msr_smbase) {
2393         kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2394     }
2395     if (has_msr_smi_count) {
2396         kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2397     }
2398     if (has_msr_feature_control) {
2399         kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2400     }
2401     if (has_msr_bndcfgs) {
2402         kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2403     }
2404     if (has_msr_xss) {
2405         kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2406     }
2407     if (has_msr_spec_ctrl) {
2408         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2409     }
2410     if (has_msr_virt_ssbd) {
2411         kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2412     }
2413     if (!env->tsc_valid) {
2414         kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2415         env->tsc_valid = !runstate_is_running();
2416     }
2417
2418 #ifdef TARGET_X86_64
2419     if (lm_capable_kernel) {
2420         kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2421         kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2422         kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2423         kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2424     }
2425 #endif
2426     kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2427     kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2428     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2429         kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2430     }
2431     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2432         kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2433     }
2434     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2435         kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2436     }
2437     if (has_architectural_pmu_version > 0) {
2438         if (has_architectural_pmu_version > 1) {
2439             kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2440             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2441             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2442             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2443         }
2444         for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2445             kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2446         }
2447         for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2448             kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2449             kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2450         }
2451     }
2452
2453     if (env->mcg_cap) {
2454         kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2455         kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2456         if (has_msr_mcg_ext_ctl) {
2457             kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2458         }
2459         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2460             kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2461         }
2462     }
2463
2464     if (has_msr_hv_hypercall) {
2465         kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2466         kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2467     }
2468     if (cpu->hyperv_vapic) {
2469         kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2470     }
2471     if (cpu->hyperv_time) {
2472         kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2473     }
2474     if (cpu->hyperv_reenlightenment) {
2475         kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2476         kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2477         kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2478     }
2479     if (has_msr_hv_crash) {
2480         int j;
2481
2482         for (j = 0; j < HV_CRASH_PARAMS; j++) {
2483             kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2484         }
2485     }
2486     if (has_msr_hv_runtime) {
2487         kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2488     }
2489     if (cpu->hyperv_synic) {
2490         uint32_t msr;
2491
2492         kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2493         kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2494         kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2495         for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2496             kvm_msr_entry_add(cpu, msr, 0);
2497         }
2498     }
2499     if (has_msr_hv_stimer) {
2500         uint32_t msr;
2501
2502         for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2503              msr++) {
2504             kvm_msr_entry_add(cpu, msr, 0);
2505         }
2506     }
2507     if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2508         kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2509         kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2510         kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2511         kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2512         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2513         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2514         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2515         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2516         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2517         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2518         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2519         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2520         for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2521             kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2522             kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2523         }
2524     }
2525
2526     if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2527         int addr_num =
2528             kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2529
2530         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2531         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2532         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2533         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2534         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2535         for (i = 0; i < addr_num; i++) {
2536             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2537         }
2538     }
2539
2540     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2541     if (ret < 0) {
2542         return ret;
2543     }
2544
2545     if (ret < cpu->kvm_msr_buf->nmsrs) {
2546         struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2547         error_report("error: failed to get MSR 0x%" PRIx32,
2548                      (uint32_t)e->index);
2549     }
2550
2551     assert(ret == cpu->kvm_msr_buf->nmsrs);
2552     /*
2553      * MTRR masks: Each mask consists of 5 parts
2554      * a  10..0: must be zero
2555      * b  11   : valid bit
2556      * c n-1.12: actual mask bits
2557      * d  51..n: reserved must be zero
2558      * e  63.52: reserved must be zero
2559      *
2560      * 'n' is the number of physical bits supported by the CPU and is
2561      * apparently always <= 52.   We know our 'n' but don't know what
2562      * the destinations 'n' is; it might be smaller, in which case
2563      * it masks (c) on loading. It might be larger, in which case
2564      * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2565      * we're migrating to.
2566      */
2567
2568     if (cpu->fill_mtrr_mask) {
2569         QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2570         assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2571         mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2572     } else {
2573         mtrr_top_bits = 0;
2574     }
2575
2576     for (i = 0; i < ret; i++) {
2577         uint32_t index = msrs[i].index;
2578         switch (index) {
2579         case MSR_IA32_SYSENTER_CS:
2580             env->sysenter_cs = msrs[i].data;
2581             break;
2582         case MSR_IA32_SYSENTER_ESP:
2583             env->sysenter_esp = msrs[i].data;
2584             break;
2585         case MSR_IA32_SYSENTER_EIP:
2586             env->sysenter_eip = msrs[i].data;
2587             break;
2588         case MSR_PAT:
2589             env->pat = msrs[i].data;
2590             break;
2591         case MSR_STAR:
2592             env->star = msrs[i].data;
2593             break;
2594 #ifdef TARGET_X86_64
2595         case MSR_CSTAR:
2596             env->cstar = msrs[i].data;
2597             break;
2598         case MSR_KERNELGSBASE:
2599             env->kernelgsbase = msrs[i].data;
2600             break;
2601         case MSR_FMASK:
2602             env->fmask = msrs[i].data;
2603             break;
2604         case MSR_LSTAR:
2605             env->lstar = msrs[i].data;
2606             break;
2607 #endif
2608         case MSR_IA32_TSC:
2609             env->tsc = msrs[i].data;
2610             break;
2611         case MSR_TSC_AUX:
2612             env->tsc_aux = msrs[i].data;
2613             break;
2614         case MSR_TSC_ADJUST:
2615             env->tsc_adjust = msrs[i].data;
2616             break;
2617         case MSR_IA32_TSCDEADLINE:
2618             env->tsc_deadline = msrs[i].data;
2619             break;
2620         case MSR_VM_HSAVE_PA:
2621             env->vm_hsave = msrs[i].data;
2622             break;
2623         case MSR_KVM_SYSTEM_TIME:
2624             env->system_time_msr = msrs[i].data;
2625             break;
2626         case MSR_KVM_WALL_CLOCK:
2627             env->wall_clock_msr = msrs[i].data;
2628             break;
2629         case MSR_MCG_STATUS:
2630             env->mcg_status = msrs[i].data;
2631             break;
2632         case MSR_MCG_CTL:
2633             env->mcg_ctl = msrs[i].data;
2634             break;
2635         case MSR_MCG_EXT_CTL:
2636             env->mcg_ext_ctl = msrs[i].data;
2637             break;
2638         case MSR_IA32_MISC_ENABLE:
2639             env->msr_ia32_misc_enable = msrs[i].data;
2640             break;
2641         case MSR_IA32_SMBASE:
2642             env->smbase = msrs[i].data;
2643             break;
2644         case MSR_SMI_COUNT:
2645             env->msr_smi_count = msrs[i].data;
2646             break;
2647         case MSR_IA32_FEATURE_CONTROL:
2648             env->msr_ia32_feature_control = msrs[i].data;
2649             break;
2650         case MSR_IA32_BNDCFGS:
2651             env->msr_bndcfgs = msrs[i].data;
2652             break;
2653         case MSR_IA32_XSS:
2654             env->xss = msrs[i].data;
2655             break;
2656         default:
2657             if (msrs[i].index >= MSR_MC0_CTL &&
2658                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2659                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2660             }
2661             break;
2662         case MSR_KVM_ASYNC_PF_EN:
2663             env->async_pf_en_msr = msrs[i].data;
2664             break;
2665         case MSR_KVM_PV_EOI_EN:
2666             env->pv_eoi_en_msr = msrs[i].data;
2667             break;
2668         case MSR_KVM_STEAL_TIME:
2669             env->steal_time_msr = msrs[i].data;
2670             break;
2671         case MSR_CORE_PERF_FIXED_CTR_CTRL:
2672             env->msr_fixed_ctr_ctrl = msrs[i].data;
2673             break;
2674         case MSR_CORE_PERF_GLOBAL_CTRL:
2675             env->msr_global_ctrl = msrs[i].data;
2676             break;
2677         case MSR_CORE_PERF_GLOBAL_STATUS:
2678             env->msr_global_status = msrs[i].data;
2679             break;
2680         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2681             env->msr_global_ovf_ctrl = msrs[i].data;
2682             break;
2683         case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2684             env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2685             break;
2686         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2687             env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2688             break;
2689         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2690             env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2691             break;
2692         case HV_X64_MSR_HYPERCALL:
2693             env->msr_hv_hypercall = msrs[i].data;
2694             break;
2695         case HV_X64_MSR_GUEST_OS_ID:
2696             env->msr_hv_guest_os_id = msrs[i].data;
2697             break;
2698         case HV_X64_MSR_APIC_ASSIST_PAGE:
2699             env->msr_hv_vapic = msrs[i].data;
2700             break;
2701         case HV_X64_MSR_REFERENCE_TSC:
2702             env->msr_hv_tsc = msrs[i].data;
2703             break;
2704         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2705             env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2706             break;
2707         case HV_X64_MSR_VP_RUNTIME:
2708             env->msr_hv_runtime = msrs[i].data;
2709             break;
2710         case HV_X64_MSR_SCONTROL:
2711             env->msr_hv_synic_control = msrs[i].data;
2712             break;
2713         case HV_X64_MSR_SIEFP:
2714             env->msr_hv_synic_evt_page = msrs[i].data;
2715             break;
2716         case HV_X64_MSR_SIMP:
2717             env->msr_hv_synic_msg_page = msrs[i].data;
2718             break;
2719         case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2720             env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2721             break;
2722         case HV_X64_MSR_STIMER0_CONFIG:
2723         case HV_X64_MSR_STIMER1_CONFIG:
2724         case HV_X64_MSR_STIMER2_CONFIG:
2725         case HV_X64_MSR_STIMER3_CONFIG:
2726             env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2727                                 msrs[i].data;
2728             break;
2729         case HV_X64_MSR_STIMER0_COUNT:
2730         case HV_X64_MSR_STIMER1_COUNT:
2731         case HV_X64_MSR_STIMER2_COUNT:
2732         case HV_X64_MSR_STIMER3_COUNT:
2733             env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2734                                 msrs[i].data;
2735             break;
2736         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2737             env->msr_hv_reenlightenment_control = msrs[i].data;
2738             break;
2739         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2740             env->msr_hv_tsc_emulation_control = msrs[i].data;
2741             break;
2742         case HV_X64_MSR_TSC_EMULATION_STATUS:
2743             env->msr_hv_tsc_emulation_status = msrs[i].data;
2744             break;
2745         case MSR_MTRRdefType:
2746             env->mtrr_deftype = msrs[i].data;
2747             break;
2748         case MSR_MTRRfix64K_00000:
2749             env->mtrr_fixed[0] = msrs[i].data;
2750             break;
2751         case MSR_MTRRfix16K_80000:
2752             env->mtrr_fixed[1] = msrs[i].data;
2753             break;
2754         case MSR_MTRRfix16K_A0000:
2755             env->mtrr_fixed[2] = msrs[i].data;
2756             break;
2757         case MSR_MTRRfix4K_C0000:
2758             env->mtrr_fixed[3] = msrs[i].data;
2759             break;
2760         case MSR_MTRRfix4K_C8000:
2761             env->mtrr_fixed[4] = msrs[i].data;
2762             break;
2763         case MSR_MTRRfix4K_D0000:
2764             env->mtrr_fixed[5] = msrs[i].data;
2765             break;
2766         case MSR_MTRRfix4K_D8000:
2767             env->mtrr_fixed[6] = msrs[i].data;
2768             break;
2769         case MSR_MTRRfix4K_E0000:
2770             env->mtrr_fixed[7] = msrs[i].data;
2771             break;
2772         case MSR_MTRRfix4K_E8000:
2773             env->mtrr_fixed[8] = msrs[i].data;
2774             break;
2775         case MSR_MTRRfix4K_F0000:
2776             env->mtrr_fixed[9] = msrs[i].data;
2777             break;
2778         case MSR_MTRRfix4K_F8000:
2779             env->mtrr_fixed[10] = msrs[i].data;
2780             break;
2781         case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2782             if (index & 1) {
2783                 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2784                                                                mtrr_top_bits;
2785             } else {
2786                 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2787             }
2788             break;
2789         case MSR_IA32_SPEC_CTRL:
2790             env->spec_ctrl = msrs[i].data;
2791             break;
2792         case MSR_VIRT_SSBD:
2793             env->virt_ssbd = msrs[i].data;
2794             break;
2795         case MSR_IA32_RTIT_CTL:
2796             env->msr_rtit_ctrl = msrs[i].data;
2797             break;
2798         case MSR_IA32_RTIT_STATUS:
2799             env->msr_rtit_status = msrs[i].data;
2800             break;
2801         case MSR_IA32_RTIT_OUTPUT_BASE:
2802             env->msr_rtit_output_base = msrs[i].data;
2803             break;
2804         case MSR_IA32_RTIT_OUTPUT_MASK:
2805             env->msr_rtit_output_mask = msrs[i].data;
2806             break;
2807         case MSR_IA32_RTIT_CR3_MATCH:
2808             env->msr_rtit_cr3_match = msrs[i].data;
2809             break;
2810         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2811             env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2812             break;
2813         }
2814     }
2815
2816     return 0;
2817 }
2818
2819 static int kvm_put_mp_state(X86CPU *cpu)
2820 {
2821     struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2822
2823     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2824 }
2825
2826 static int kvm_get_mp_state(X86CPU *cpu)
2827 {
2828     CPUState *cs = CPU(cpu);
2829     CPUX86State *env = &cpu->env;
2830     struct kvm_mp_state mp_state;
2831     int ret;
2832
2833     ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2834     if (ret < 0) {
2835         return ret;
2836     }
2837     env->mp_state = mp_state.mp_state;
2838     if (kvm_irqchip_in_kernel()) {
2839         cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2840     }
2841     return 0;
2842 }
2843
2844 static int kvm_get_apic(X86CPU *cpu)
2845 {
2846     DeviceState *apic = cpu->apic_state;
2847     struct kvm_lapic_state kapic;
2848     int ret;
2849
2850     if (apic && kvm_irqchip_in_kernel()) {
2851         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2852         if (ret < 0) {
2853             return ret;
2854         }
2855
2856         kvm_get_apic_state(apic, &kapic);
2857     }
2858     return 0;
2859 }
2860
2861 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2862 {
2863     CPUState *cs = CPU(cpu);
2864     CPUX86State *env = &cpu->env;
2865     struct kvm_vcpu_events events = {};
2866
2867     if (!kvm_has_vcpu_events()) {
2868         return 0;
2869     }
2870
2871     events.exception.injected = (env->exception_injected >= 0);
2872     events.exception.nr = env->exception_injected;
2873     events.exception.has_error_code = env->has_error_code;
2874     events.exception.error_code = env->error_code;
2875
2876     events.interrupt.injected = (env->interrupt_injected >= 0);
2877     events.interrupt.nr = env->interrupt_injected;
2878     events.interrupt.soft = env->soft_interrupt;
2879
2880     events.nmi.injected = env->nmi_injected;
2881     events.nmi.pending = env->nmi_pending;
2882     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2883
2884     events.sipi_vector = env->sipi_vector;
2885     events.flags = 0;
2886
2887     if (has_msr_smbase) {
2888         events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2889         events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2890         if (kvm_irqchip_in_kernel()) {
2891             /* As soon as these are moved to the kernel, remove them
2892              * from cs->interrupt_request.
2893              */
2894             events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2895             events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2896             cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2897         } else {
2898             /* Keep these in cs->interrupt_request.  */
2899             events.smi.pending = 0;
2900             events.smi.latched_init = 0;
2901         }
2902         /* Stop SMI delivery on old machine types to avoid a reboot
2903          * on an inward migration of an old VM.
2904          */
2905         if (!cpu->kvm_no_smi_migration) {
2906             events.flags |= KVM_VCPUEVENT_VALID_SMM;
2907         }
2908     }
2909
2910     if (level >= KVM_PUT_RESET_STATE) {
2911         events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2912         if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2913             events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2914         }
2915     }
2916
2917     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2918 }
2919
2920 static int kvm_get_vcpu_events(X86CPU *cpu)
2921 {
2922     CPUX86State *env = &cpu->env;
2923     struct kvm_vcpu_events events;
2924     int ret;
2925
2926     if (!kvm_has_vcpu_events()) {
2927         return 0;
2928     }
2929
2930     memset(&events, 0, sizeof(events));
2931     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2932     if (ret < 0) {
2933        return ret;
2934     }
2935     env->exception_injected =
2936        events.exception.injected ? events.exception.nr : -1;
2937     env->has_error_code = events.exception.has_error_code;
2938     env->error_code = events.exception.error_code;
2939
2940     env->interrupt_injected =
2941         events.interrupt.injected ? events.interrupt.nr : -1;
2942     env->soft_interrupt = events.interrupt.soft;
2943
2944     env->nmi_injected = events.nmi.injected;
2945     env->nmi_pending = events.nmi.pending;
2946     if (events.nmi.masked) {
2947         env->hflags2 |= HF2_NMI_MASK;
2948     } else {
2949         env->hflags2 &= ~HF2_NMI_MASK;
2950     }
2951
2952     if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2953         if (events.smi.smm) {
2954             env->hflags |= HF_SMM_MASK;
2955         } else {
2956             env->hflags &= ~HF_SMM_MASK;
2957         }
2958         if (events.smi.pending) {
2959             cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2960         } else {
2961             cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2962         }
2963         if (events.smi.smm_inside_nmi) {
2964             env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2965         } else {
2966             env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2967         }
2968         if (events.smi.latched_init) {
2969             cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2970         } else {
2971             cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2972         }
2973     }
2974
2975     env->sipi_vector = events.sipi_vector;
2976
2977     return 0;
2978 }
2979
2980 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2981 {
2982     CPUState *cs = CPU(cpu);
2983     CPUX86State *env = &cpu->env;
2984     int ret = 0;
2985     unsigned long reinject_trap = 0;
2986
2987     if (!kvm_has_vcpu_events()) {
2988         if (env->exception_injected == 1) {
2989             reinject_trap = KVM_GUESTDBG_INJECT_DB;
2990         } else if (env->exception_injected == 3) {
2991             reinject_trap = KVM_GUESTDBG_INJECT_BP;
2992         }
2993         env->exception_injected = -1;
2994     }
2995
2996     /*
2997      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2998      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2999      * by updating the debug state once again if single-stepping is on.
3000      * Another reason to call kvm_update_guest_debug here is a pending debug
3001      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3002      * reinject them via SET_GUEST_DEBUG.
3003      */
3004     if (reinject_trap ||
3005         (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
3006         ret = kvm_update_guest_debug(cs, reinject_trap);
3007     }
3008     return ret;
3009 }
3010
3011 static int kvm_put_debugregs(X86CPU *cpu)
3012 {
3013     CPUX86State *env = &cpu->env;
3014     struct kvm_debugregs dbgregs;
3015     int i;
3016
3017     if (!kvm_has_debugregs()) {
3018         return 0;
3019     }
3020
3021     for (i = 0; i < 4; i++) {
3022         dbgregs.db[i] = env->dr[i];
3023     }
3024     dbgregs.dr6 = env->dr[6];
3025     dbgregs.dr7 = env->dr[7];
3026     dbgregs.flags = 0;
3027
3028     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
3029 }
3030
3031 static int kvm_get_debugregs(X86CPU *cpu)
3032 {
3033     CPUX86State *env = &cpu->env;
3034     struct kvm_debugregs dbgregs;
3035     int i, ret;
3036
3037     if (!kvm_has_debugregs()) {
3038         return 0;
3039     }
3040
3041     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
3042     if (ret < 0) {
3043         return ret;
3044     }
3045     for (i = 0; i < 4; i++) {
3046         env->dr[i] = dbgregs.db[i];
3047     }
3048     env->dr[4] = env->dr[6] = dbgregs.dr6;
3049     env->dr[5] = env->dr[7] = dbgregs.dr7;
3050
3051     return 0;
3052 }
3053
3054 int kvm_arch_put_registers(CPUState *cpu, int level)
3055 {
3056     X86CPU *x86_cpu = X86_CPU(cpu);
3057     int ret;
3058
3059     assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
3060
3061     if (level >= KVM_PUT_RESET_STATE) {
3062         ret = kvm_put_msr_feature_control(x86_cpu);
3063         if (ret < 0) {
3064             return ret;
3065         }
3066     }
3067
3068     if (level == KVM_PUT_FULL_STATE) {
3069         /* We don't check for kvm_arch_set_tsc_khz() errors here,
3070          * because TSC frequency mismatch shouldn't abort migration,
3071          * unless the user explicitly asked for a more strict TSC
3072          * setting (e.g. using an explicit "tsc-freq" option).
3073          */
3074         kvm_arch_set_tsc_khz(cpu);
3075     }
3076
3077     ret = kvm_getput_regs(x86_cpu, 1);
3078     if (ret < 0) {
3079         return ret;
3080     }
3081     ret = kvm_put_xsave(x86_cpu);
3082     if (ret < 0) {
3083         return ret;
3084     }
3085     ret = kvm_put_xcrs(x86_cpu);
3086     if (ret < 0) {
3087         return ret;
3088     }
3089     ret = kvm_put_sregs(x86_cpu);
3090     if (ret < 0) {
3091         return ret;
3092     }
3093     /* must be before kvm_put_msrs */
3094     ret = kvm_inject_mce_oldstyle(x86_cpu);
3095     if (ret < 0) {
3096         return ret;
3097     }
3098     ret = kvm_put_msrs(x86_cpu, level);
3099     if (ret < 0) {
3100         return ret;
3101     }
3102     ret = kvm_put_vcpu_events(x86_cpu, level);
3103     if (ret < 0) {
3104         return ret;
3105     }
3106     if (level >= KVM_PUT_RESET_STATE) {
3107         ret = kvm_put_mp_state(x86_cpu);
3108         if (ret < 0) {
3109             return ret;
3110         }
3111     }
3112
3113     ret = kvm_put_tscdeadline_msr(x86_cpu);
3114     if (ret < 0) {
3115         return ret;
3116     }
3117     ret = kvm_put_debugregs(x86_cpu);
3118     if (ret < 0) {
3119         return ret;
3120     }
3121     /* must be last */
3122     ret = kvm_guest_debug_workarounds(x86_cpu);
3123     if (ret < 0) {
3124         return ret;
3125     }
3126     return 0;
3127 }
3128
3129 int kvm_arch_get_registers(CPUState *cs)
3130 {
3131     X86CPU *cpu = X86_CPU(cs);
3132     int ret;
3133
3134     assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
3135
3136     ret = kvm_get_vcpu_events(cpu);
3137     if (ret < 0) {
3138         goto out;
3139     }
3140     /*
3141      * KVM_GET_MPSTATE can modify CS and RIP, call it before
3142      * KVM_GET_REGS and KVM_GET_SREGS.
3143      */
3144     ret = kvm_get_mp_state(cpu);
3145     if (ret < 0) {
3146         goto out;
3147     }
3148     ret = kvm_getput_regs(cpu, 0);
3149     if (ret < 0) {
3150         goto out;
3151     }
3152     ret = kvm_get_xsave(cpu);
3153     if (ret < 0) {
3154         goto out;
3155     }
3156     ret = kvm_get_xcrs(cpu);
3157     if (ret < 0) {
3158         goto out;
3159     }
3160     ret = kvm_get_sregs(cpu);
3161     if (ret < 0) {
3162         goto out;
3163     }
3164     ret = kvm_get_msrs(cpu);
3165     if (ret < 0) {
3166         goto out;
3167     }
3168     ret = kvm_get_apic(cpu);
3169     if (ret < 0) {
3170         goto out;
3171     }
3172     ret = kvm_get_debugregs(cpu);
3173     if (ret < 0) {
3174         goto out;
3175     }
3176     ret = 0;
3177  out:
3178     cpu_sync_bndcs_hflags(&cpu->env);
3179     return ret;
3180 }
3181
3182 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
3183 {
3184     X86CPU *x86_cpu = X86_CPU(cpu);
3185     CPUX86State *env = &x86_cpu->env;
3186     int ret;
3187
3188     /* Inject NMI */
3189     if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3190         if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3191             qemu_mutex_lock_iothread();
3192             cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3193             qemu_mutex_unlock_iothread();
3194             DPRINTF("injected NMI\n");
3195             ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3196             if (ret < 0) {
3197                 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3198                         strerror(-ret));
3199             }
3200         }
3201         if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3202             qemu_mutex_lock_iothread();
3203             cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3204             qemu_mutex_unlock_iothread();
3205             DPRINTF("injected SMI\n");
3206             ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3207             if (ret < 0) {
3208                 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3209                         strerror(-ret));
3210             }
3211         }
3212     }
3213
3214     if (!kvm_pic_in_kernel()) {
3215         qemu_mutex_lock_iothread();
3216     }
3217
3218     /* Force the VCPU out of its inner loop to process any INIT requests
3219      * or (for userspace APIC, but it is cheap to combine the checks here)
3220      * pending TPR access reports.
3221      */
3222     if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
3223         if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3224             !(env->hflags & HF_SMM_MASK)) {
3225             cpu->exit_request = 1;
3226         }
3227         if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3228             cpu->exit_request = 1;
3229         }
3230     }
3231
3232     if (!kvm_pic_in_kernel()) {
3233         /* Try to inject an interrupt if the guest can accept it */
3234         if (run->ready_for_interrupt_injection &&
3235             (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
3236             (env->eflags & IF_MASK)) {
3237             int irq;
3238
3239             cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
3240             irq = cpu_get_pic_interrupt(env);
3241             if (irq >= 0) {
3242                 struct kvm_interrupt intr;
3243
3244                 intr.irq = irq;
3245                 DPRINTF("injected interrupt %d\n", irq);
3246                 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
3247                 if (ret < 0) {
3248                     fprintf(stderr,
3249                             "KVM: injection failed, interrupt lost (%s)\n",
3250                             strerror(-ret));
3251                 }
3252             }
3253         }
3254
3255         /* If we have an interrupt but the guest is not ready to receive an
3256          * interrupt, request an interrupt window exit.  This will
3257          * cause a return to userspace as soon as the guest is ready to
3258          * receive interrupts. */
3259         if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
3260             run->request_interrupt_window = 1;
3261         } else {
3262             run->request_interrupt_window = 0;
3263         }
3264
3265         DPRINTF("setting tpr\n");
3266         run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
3267
3268         qemu_mutex_unlock_iothread();
3269     }
3270 }
3271
3272 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
3273 {
3274     X86CPU *x86_cpu = X86_CPU(cpu);
3275     CPUX86State *env = &x86_cpu->env;
3276
3277     if (run->flags & KVM_RUN_X86_SMM) {
3278         env->hflags |= HF_SMM_MASK;
3279     } else {
3280         env->hflags &= ~HF_SMM_MASK;
3281     }
3282     if (run->if_flag) {
3283         env->eflags |= IF_MASK;
3284     } else {
3285         env->eflags &= ~IF_MASK;
3286     }
3287
3288     /* We need to protect the apic state against concurrent accesses from
3289      * different threads in case the userspace irqchip is used. */
3290     if (!kvm_irqchip_in_kernel()) {
3291         qemu_mutex_lock_iothread();
3292     }
3293     cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3294     cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
3295     if (!kvm_irqchip_in_kernel()) {
3296         qemu_mutex_unlock_iothread();
3297     }
3298     return cpu_get_mem_attrs(env);
3299 }
3300
3301 int kvm_arch_process_async_events(CPUState *cs)
3302 {
3303     X86CPU *cpu = X86_CPU(cs);
3304     CPUX86State *env = &cpu->env;
3305
3306     if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
3307         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3308         assert(env->mcg_cap);
3309
3310         cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
3311
3312         kvm_cpu_synchronize_state(cs);
3313
3314         if (env->exception_injected == EXCP08_DBLE) {
3315             /* this means triple fault */
3316             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
3317             cs->exit_request = 1;
3318             return 0;
3319         }
3320         env->exception_injected = EXCP12_MCHK;
3321         env->has_error_code = 0;
3322
3323         cs->halted = 0;
3324         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3325             env->mp_state = KVM_MP_STATE_RUNNABLE;
3326         }
3327     }
3328
3329     if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3330         !(env->hflags & HF_SMM_MASK)) {
3331         kvm_cpu_synchronize_state(cs);
3332         do_cpu_init(cpu);
3333     }
3334
3335     if (kvm_irqchip_in_kernel()) {
3336         return 0;
3337     }
3338
3339     if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3340         cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
3341         apic_poll_irq(cpu->apic_state);
3342     }
3343     if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3344          (env->eflags & IF_MASK)) ||
3345         (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3346         cs->halted = 0;
3347     }
3348     if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
3349         kvm_cpu_synchronize_state(cs);
3350         do_cpu_sipi(cpu);
3351     }
3352     if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3353         cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
3354         kvm_cpu_synchronize_state(cs);
3355         apic_handle_tpr_access_report(cpu->apic_state, env->eip,
3356                                       env->tpr_access_type);
3357     }
3358
3359     return cs->halted;
3360 }
3361
3362 static int kvm_handle_halt(X86CPU *cpu)
3363 {
3364     CPUState *cs = CPU(cpu);
3365     CPUX86State *env = &cpu->env;
3366
3367     if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3368           (env->eflags & IF_MASK)) &&
3369         !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3370         cs->halted = 1;
3371         return EXCP_HLT;
3372     }
3373
3374     return 0;
3375 }
3376
3377 static int kvm_handle_tpr_access(X86CPU *cpu)
3378 {
3379     CPUState *cs = CPU(cpu);
3380     struct kvm_run *run = cs->kvm_run;
3381
3382     apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3383                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
3384                                                            : TPR_ACCESS_READ);
3385     return 1;
3386 }
3387
3388 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3389 {
3390     static const uint8_t int3 = 0xcc;
3391
3392     if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3393         cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3394         return -EINVAL;
3395     }
3396     return 0;
3397 }
3398
3399 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3400 {
3401     uint8_t int3;
3402
3403     if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3404         cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3405         return -EINVAL;
3406     }
3407     return 0;
3408 }
3409
3410 static struct {
3411     target_ulong addr;
3412     int len;
3413     int type;
3414 } hw_breakpoint[4];
3415
3416 static int nb_hw_breakpoint;
3417
3418 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3419 {
3420     int n;
3421
3422     for (n = 0; n < nb_hw_breakpoint; n++) {
3423         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3424             (hw_breakpoint[n].len == len || len == -1)) {
3425             return n;
3426         }
3427     }
3428     return -1;
3429 }
3430
3431 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3432                                   target_ulong len, int type)
3433 {
3434     switch (type) {
3435     case GDB_BREAKPOINT_HW:
3436         len = 1;
3437         break;
3438     case GDB_WATCHPOINT_WRITE:
3439     case GDB_WATCHPOINT_ACCESS:
3440         switch (len) {
3441         case 1:
3442             break;
3443         case 2:
3444         case 4:
3445         case 8:
3446             if (addr & (len - 1)) {
3447                 return -EINVAL;
3448             }
3449             break;
3450         default:
3451             return -EINVAL;
3452         }
3453         break;
3454     default:
3455         return -ENOSYS;
3456     }
3457
3458     if (nb_hw_breakpoint == 4) {
3459         return -ENOBUFS;
3460     }
3461     if (find_hw_breakpoint(addr, len, type) >= 0) {
3462         return -EEXIST;
3463     }
3464     hw_breakpoint[nb_hw_breakpoint].addr = addr;
3465     hw_breakpoint[nb_hw_breakpoint].len = len;
3466     hw_breakpoint[nb_hw_breakpoint].type = type;
3467     nb_hw_breakpoint++;
3468
3469     return 0;
3470 }
3471
3472 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3473                                   target_ulong len, int type)
3474 {
3475     int n;
3476
3477     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3478     if (n < 0) {
3479         return -ENOENT;
3480     }
3481     nb_hw_breakpoint--;
3482     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3483
3484     return 0;
3485 }
3486
3487 void kvm_arch_remove_all_hw_breakpoints(void)
3488 {
3489     nb_hw_breakpoint = 0;
3490 }
3491
3492 static CPUWatchpoint hw_watchpoint;
3493
3494 static int kvm_handle_debug(X86CPU *cpu,
3495                             struct kvm_debug_exit_arch *arch_info)
3496 {
3497     CPUState *cs = CPU(cpu);
3498     CPUX86State *env = &cpu->env;
3499     int ret = 0;
3500     int n;
3501
3502     if (arch_info->exception == 1) {
3503         if (arch_info->dr6 & (1 << 14)) {
3504             if (cs->singlestep_enabled) {
3505                 ret = EXCP_DEBUG;
3506             }
3507         } else {
3508             for (n = 0; n < 4; n++) {
3509                 if (arch_info->dr6 & (1 << n)) {
3510                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3511                     case 0x0:
3512                         ret = EXCP_DEBUG;
3513                         break;
3514                     case 0x1:
3515                         ret = EXCP_DEBUG;
3516                         cs->watchpoint_hit = &hw_watchpoint;
3517                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3518                         hw_watchpoint.flags = BP_MEM_WRITE;
3519                         break;
3520                     case 0x3:
3521                         ret = EXCP_DEBUG;
3522                         cs->watchpoint_hit = &hw_watchpoint;
3523                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3524                         hw_watchpoint.flags = BP_MEM_ACCESS;
3525                         break;
3526                     }
3527                 }
3528             }
3529         }
3530     } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3531         ret = EXCP_DEBUG;
3532     }
3533     if (ret == 0) {
3534         cpu_synchronize_state(cs);
3535         assert(env->exception_injected == -1);
3536
3537         /* pass to guest */
3538         env->exception_injected = arch_info->exception;
3539         env->has_error_code = 0;
3540     }
3541
3542     return ret;
3543 }
3544
3545 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3546 {
3547     const uint8_t type_code[] = {
3548         [GDB_BREAKPOINT_HW] = 0x0,
3549         [GDB_WATCHPOINT_WRITE] = 0x1,
3550         [GDB_WATCHPOINT_ACCESS] = 0x3
3551     };
3552     const uint8_t len_code[] = {
3553         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3554     };
3555     int n;
3556
3557     if (kvm_sw_breakpoints_active(cpu)) {
3558         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3559     }
3560     if (nb_hw_breakpoint > 0) {
3561         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3562         dbg->arch.debugreg[7] = 0x0600;
3563         for (n = 0; n < nb_hw_breakpoint; n++) {
3564             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3565             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3566                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3567                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3568         }
3569     }
3570 }
3571
3572 static bool host_supports_vmx(void)
3573 {
3574     uint32_t ecx, unused;
3575
3576     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3577     return ecx & CPUID_EXT_VMX;
3578 }
3579
3580 #define VMX_INVALID_GUEST_STATE 0x80000021
3581
3582 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3583 {
3584     X86CPU *cpu = X86_CPU(cs);
3585     uint64_t code;
3586     int ret;
3587
3588     switch (run->exit_reason) {
3589     case KVM_EXIT_HLT:
3590         DPRINTF("handle_hlt\n");
3591         qemu_mutex_lock_iothread();
3592         ret = kvm_handle_halt(cpu);
3593         qemu_mutex_unlock_iothread();
3594         break;
3595     case KVM_EXIT_SET_TPR:
3596         ret = 0;
3597         break;
3598     case KVM_EXIT_TPR_ACCESS:
3599         qemu_mutex_lock_iothread();
3600         ret = kvm_handle_tpr_access(cpu);
3601         qemu_mutex_unlock_iothread();
3602         break;
3603     case KVM_EXIT_FAIL_ENTRY:
3604         code = run->fail_entry.hardware_entry_failure_reason;
3605         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3606                 code);
3607         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3608             fprintf(stderr,
3609                     "\nIf you're running a guest on an Intel machine without "
3610                         "unrestricted mode\n"
3611                     "support, the failure can be most likely due to the guest "
3612                         "entering an invalid\n"
3613                     "state for Intel VT. For example, the guest maybe running "
3614                         "in big real mode\n"
3615                     "which is not supported on less recent Intel processors."
3616                         "\n\n");
3617         }
3618         ret = -1;
3619         break;
3620     case KVM_EXIT_EXCEPTION:
3621         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3622                 run->ex.exception, run->ex.error_code);
3623         ret = -1;
3624         break;
3625     case KVM_EXIT_DEBUG:
3626         DPRINTF("kvm_exit_debug\n");
3627         qemu_mutex_lock_iothread();
3628         ret = kvm_handle_debug(cpu, &run->debug.arch);
3629         qemu_mutex_unlock_iothread();
3630         break;
3631     case KVM_EXIT_HYPERV:
3632         ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3633         break;
3634     case KVM_EXIT_IOAPIC_EOI:
3635         ioapic_eoi_broadcast(run->eoi.vector);
3636         ret = 0;
3637         break;
3638     default:
3639         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3640         ret = -1;
3641         break;
3642     }
3643
3644     return ret;
3645 }
3646
3647 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3648 {
3649     X86CPU *cpu = X86_CPU(cs);
3650     CPUX86State *env = &cpu->env;
3651
3652     kvm_cpu_synchronize_state(cs);
3653     return !(env->cr[0] & CR0_PE_MASK) ||
3654            ((env->segs[R_CS].selector  & 3) != 3);
3655 }
3656
3657 void kvm_arch_init_irq_routing(KVMState *s)
3658 {
3659     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3660         /* If kernel can't do irq routing, interrupt source
3661          * override 0->2 cannot be set up as required by HPET.
3662          * So we have to disable it.
3663          */
3664         no_hpet = 1;
3665     }
3666     /* We know at this point that we're using the in-kernel
3667      * irqchip, so we can use irqfds, and on x86 we know
3668      * we can use msi via irqfd and GSI routing.
3669      */
3670     kvm_msi_via_irqfd_allowed = true;
3671     kvm_gsi_routing_allowed = true;
3672
3673     if (kvm_irqchip_is_split()) {
3674         int i;
3675
3676         /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3677            MSI routes for signaling interrupts to the local apics. */
3678         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3679             if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3680                 error_report("Could not enable split IRQ mode.");
3681                 exit(1);
3682             }
3683         }
3684     }
3685 }
3686
3687 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3688 {
3689     int ret;
3690     if (machine_kernel_irqchip_split(ms)) {
3691         ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3692         if (ret) {
3693             error_report("Could not enable split irqchip mode: %s",
3694                          strerror(-ret));
3695             exit(1);
3696         } else {
3697             DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3698             kvm_split_irqchip = true;
3699             return 1;
3700         }
3701     } else {
3702         return 0;
3703     }
3704 }
3705
3706 /* Classic KVM device assignment interface. Will remain x86 only. */
3707 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3708                           uint32_t flags, uint32_t *dev_id)
3709 {
3710     struct kvm_assigned_pci_dev dev_data = {
3711         .segnr = dev_addr->domain,
3712         .busnr = dev_addr->bus,
3713         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3714         .flags = flags,
3715     };
3716     int ret;
3717
3718     dev_data.assigned_dev_id =
3719         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3720
3721     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3722     if (ret < 0) {
3723         return ret;
3724     }
3725
3726     *dev_id = dev_data.assigned_dev_id;
3727
3728     return 0;
3729 }
3730
3731 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3732 {
3733     struct kvm_assigned_pci_dev dev_data = {
3734         .assigned_dev_id = dev_id,
3735     };
3736
3737     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3738 }
3739
3740 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3741                                    uint32_t irq_type, uint32_t guest_irq)
3742 {
3743     struct kvm_assigned_irq assigned_irq = {
3744         .assigned_dev_id = dev_id,
3745         .guest_irq = guest_irq,
3746         .flags = irq_type,
3747     };
3748
3749     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3750         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3751     } else {
3752         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3753     }
3754 }
3755
3756 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3757                            uint32_t guest_irq)
3758 {
3759     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3760         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3761
3762     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3763 }
3764
3765 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3766 {
3767     struct kvm_assigned_pci_dev dev_data = {
3768         .assigned_dev_id = dev_id,
3769         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3770     };
3771
3772     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3773 }
3774
3775 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3776                                      uint32_t type)
3777 {
3778     struct kvm_assigned_irq assigned_irq = {
3779         .assigned_dev_id = dev_id,
3780         .flags = type,
3781     };
3782
3783     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3784 }
3785
3786 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3787 {
3788     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3789         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3790 }
3791
3792 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3793 {
3794     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3795                                               KVM_DEV_IRQ_GUEST_MSI, virq);
3796 }
3797
3798 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3799 {
3800     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3801                                                 KVM_DEV_IRQ_HOST_MSI);
3802 }
3803
3804 bool kvm_device_msix_supported(KVMState *s)
3805 {
3806     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3807      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3808     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3809 }
3810
3811 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3812                                  uint32_t nr_vectors)
3813 {
3814     struct kvm_assigned_msix_nr msix_nr = {
3815         .assigned_dev_id = dev_id,
3816         .entry_nr = nr_vectors,
3817     };
3818
3819     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3820 }
3821
3822 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3823                                int virq)
3824 {
3825     struct kvm_assigned_msix_entry msix_entry = {
3826         .assigned_dev_id = dev_id,
3827         .gsi = virq,
3828         .entry = vector,
3829     };
3830
3831     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3832 }
3833
3834 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3835 {
3836     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3837                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
3838 }
3839
3840 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3841 {
3842     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3843                                                 KVM_DEV_IRQ_HOST_MSIX);
3844 }
3845
3846 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3847                              uint64_t address, uint32_t data, PCIDevice *dev)
3848 {
3849     X86IOMMUState *iommu = x86_iommu_get_default();
3850
3851     if (iommu) {
3852         int ret;
3853         MSIMessage src, dst;
3854         X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3855
3856         if (!class->int_remap) {
3857             return 0;
3858         }
3859
3860         src.address = route->u.msi.address_hi;
3861         src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3862         src.address |= route->u.msi.address_lo;
3863         src.data = route->u.msi.data;
3864
3865         ret = class->int_remap(iommu, &src, &dst, dev ? \
3866                                pci_requester_id(dev) : \
3867                                X86_IOMMU_SID_INVALID);
3868         if (ret) {
3869             trace_kvm_x86_fixup_msi_error(route->gsi);
3870             return 1;
3871         }
3872
3873         route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3874         route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3875         route->u.msi.data = dst.data;
3876     }
3877
3878     return 0;
3879 }
3880
3881 typedef struct MSIRouteEntry MSIRouteEntry;
3882
3883 struct MSIRouteEntry {
3884     PCIDevice *dev;             /* Device pointer */
3885     int vector;                 /* MSI/MSIX vector index */
3886     int virq;                   /* Virtual IRQ index */
3887     QLIST_ENTRY(MSIRouteEntry) list;
3888 };
3889
3890 /* List of used GSI routes */
3891 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3892     QLIST_HEAD_INITIALIZER(msi_route_list);
3893
3894 static void kvm_update_msi_routes_all(void *private, bool global,
3895                                       uint32_t index, uint32_t mask)
3896 {
3897     int cnt = 0, vector;
3898     MSIRouteEntry *entry;
3899     MSIMessage msg;
3900     PCIDevice *dev;
3901
3902     /* TODO: explicit route update */
3903     QLIST_FOREACH(entry, &msi_route_list, list) {
3904         cnt++;
3905         vector = entry->vector;
3906         dev = entry->dev;
3907         if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
3908             msg = msix_get_message(dev, vector);
3909         } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
3910             msg = msi_get_message(dev, vector);
3911         } else {
3912             /*
3913              * Either MSI/MSIX is disabled for the device, or the
3914              * specific message was masked out.  Skip this one.
3915              */
3916             continue;
3917         }
3918         kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3919     }
3920     kvm_irqchip_commit_routes(kvm_state);
3921     trace_kvm_x86_update_msi_routes(cnt);
3922 }
3923
3924 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3925                                 int vector, PCIDevice *dev)
3926 {
3927     static bool notify_list_inited = false;
3928     MSIRouteEntry *entry;
3929
3930     if (!dev) {
3931         /* These are (possibly) IOAPIC routes only used for split
3932          * kernel irqchip mode, while what we are housekeeping are
3933          * PCI devices only. */
3934         return 0;
3935     }
3936
3937     entry = g_new0(MSIRouteEntry, 1);
3938     entry->dev = dev;
3939     entry->vector = vector;
3940     entry->virq = route->gsi;
3941     QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3942
3943     trace_kvm_x86_add_msi_route(route->gsi);
3944
3945     if (!notify_list_inited) {
3946         /* For the first time we do add route, add ourselves into
3947          * IOMMU's IEC notify list if needed. */
3948         X86IOMMUState *iommu = x86_iommu_get_default();
3949         if (iommu) {
3950             x86_iommu_iec_register_notifier(iommu,
3951                                             kvm_update_msi_routes_all,
3952                                             NULL);
3953         }
3954         notify_list_inited = true;
3955     }
3956     return 0;
3957 }
3958
3959 int kvm_arch_release_virq_post(int virq)
3960 {
3961     MSIRouteEntry *entry, *next;
3962     QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3963         if (entry->virq == virq) {
3964             trace_kvm_x86_remove_msi_route(virq);
3965             QLIST_REMOVE(entry, list);
3966             g_free(entry);
3967             break;
3968         }
3969     }
3970     return 0;
3971 }
3972
3973 int kvm_arch_msi_data_to_gsi(uint32_t data)
3974 {
3975     abort();
3976 }