target/i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "qapi/error.h"
  17 #include <sys/ioctl.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include "standard-headers/asm-x86/kvm_para.h"
  22
  23 #include "qemu-common.h"
  24 #include "cpu.h"
  25 #include "sysemu/sysemu.h"
  26 #include "sysemu/hw_accel.h"
  27 #include "sysemu/kvm_int.h"
  28 #include "kvm_i386.h"
  29 #include "hyperv.h"
  30 #include "hyperv-proto.h"
  31
  32 #include "exec/gdbstub.h"
  33 #include "qemu/host-utils.h"
  34 #include "qemu/config-file.h"
  35 #include "qemu/error-report.h"
  36 #include "hw/i386/pc.h"
  37 #include "hw/i386/apic.h"
  38 #include "hw/i386/apic_internal.h"
  39 #include "hw/i386/apic-msidef.h"
  40 #include "hw/i386/intel_iommu.h"
  41 #include "hw/i386/x86-iommu.h"
  42
  43 #include "hw/pci/pci.h"
  44 #include "hw/pci/msi.h"
  45 #include "hw/pci/msix.h"
  46 #include "migration/blocker.h"
  47 #include "exec/memattrs.h"
  48 #include "trace.h"
  49
  50 //#define DEBUG_KVM
  51
  52 #ifdef DEBUG_KVM
  53 #define DPRINTF(fmt, ...) \
  54     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  55 #else
  56 #define DPRINTF(fmt, ...) \
  57     do { } while (0)
  58 #endif
  59
  60 #define MSR_KVM_WALL_CLOCK  0x11
  61 #define MSR_KVM_SYSTEM_TIME 0x12
  62
  63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
  64  * 255 kvm_msr_entry structs */
  65 #define MSR_BUF_SIZE 4096
  66
  67 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  68     KVM_CAP_INFO(SET_TSS_ADDR),
  69     KVM_CAP_INFO(EXT_CPUID),
  70     KVM_CAP_INFO(MP_STATE),
  71     KVM_CAP_LAST_INFO
  72 };
  73
  74 static bool has_msr_star;
  75 static bool has_msr_hsave_pa;
  76 static bool has_msr_tsc_aux;
  77 static bool has_msr_tsc_adjust;
  78 static bool has_msr_tsc_deadline;
  79 static bool has_msr_feature_control;
  80 static bool has_msr_misc_enable;
  81 static bool has_msr_smbase;
  82 static bool has_msr_bndcfgs;
  83 static int lm_capable_kernel;
  84 static bool has_msr_hv_hypercall;
  85 static bool has_msr_hv_crash;
  86 static bool has_msr_hv_reset;
  87 static bool has_msr_hv_vpindex;
  88 static bool hv_vpindex_settable;
  89 static bool has_msr_hv_runtime;
  90 static bool has_msr_hv_synic;
  91 static bool has_msr_hv_stimer;
  92 static bool has_msr_hv_frequencies;
  93 static bool has_msr_hv_reenlightenment;
  94 static bool has_msr_xss;
  95 static bool has_msr_spec_ctrl;
  96 static bool has_msr_virt_ssbd;
  97 static bool has_msr_smi_count;
  98
  99 static uint32_t has_architectural_pmu_version;
 100 static uint32_t num_architectural_pmu_gp_counters;
 101 static uint32_t num_architectural_pmu_fixed_counters;
 102
 103 static int has_xsave;
 104 static int has_xcrs;
 105 static int has_pit_state2;
 106
 107 static bool has_msr_mcg_ext_ctl;
 108
 109 static struct kvm_cpuid2 *cpuid_cache;
 110
 111 int kvm_has_pit_state2(void)
 112 {
 113     return has_pit_state2;
 114 }
 115
 116 bool kvm_has_smm(void)
 117 {
 118     return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
 119 }
 120
 121 bool kvm_has_adjust_clock_stable(void)
 122 {
 123     int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
 124
 125     return (ret == KVM_CLOCK_TSC_STABLE);
 126 }
 127
 128 bool kvm_allows_irq0_override(void)
 129 {
 130     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
 131 }
 132
 133 static bool kvm_x2apic_api_set_flags(uint64_t flags)
 134 {
 135     KVMState *s = KVM_STATE(current_machine->accelerator);
 136
 137     return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
 138 }
 139
 140 #define MEMORIZE(fn, _result) \
 141     ({ \
 142         static bool _memorized; \
 143         \
 144         if (_memorized) { \
 145             return _result; \
 146         } \
 147         _memorized = true; \
 148         _result = fn; \
 149     })
 150
 151 static bool has_x2apic_api;
 152
 153 bool kvm_has_x2apic_api(void)
 154 {
 155     return has_x2apic_api;
 156 }
 157
 158 bool kvm_enable_x2apic(void)
 159 {
 160     return MEMORIZE(
 161              kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
 162                                       KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
 163              has_x2apic_api);
 164 }
 165
 166 bool kvm_hv_vpindex_settable(void)
 167 {
 168     return hv_vpindex_settable;
 169 }
 170
 171 static int kvm_get_tsc(CPUState *cs)
 172 {
 173     X86CPU *cpu = X86_CPU(cs);
 174     CPUX86State *env = &cpu->env;
 175     struct {
 176         struct kvm_msrs info;
 177         struct kvm_msr_entry entries[1];
 178     } msr_data;
 179     int ret;
 180
 181     if (env->tsc_valid) {
 182         return 0;
 183     }
 184
 185     msr_data.info.nmsrs = 1;
 186     msr_data.entries[0].index = MSR_IA32_TSC;
 187     env->tsc_valid = !runstate_is_running();
 188
 189     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
 190     if (ret < 0) {
 191         return ret;
 192     }
 193
 194     assert(ret == 1);
 195     env->tsc = msr_data.entries[0].data;
 196     return 0;
 197 }
 198
 199 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
 200 {
 201     kvm_get_tsc(cpu);
 202 }
 203
 204 void kvm_synchronize_all_tsc(void)
 205 {
 206     CPUState *cpu;
 207
 208     if (kvm_enabled()) {
 209         CPU_FOREACH(cpu) {
 210             run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
 211         }
 212     }
 213 }
 214
 215 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
 216 {
 217     struct kvm_cpuid2 *cpuid;
 218     int r, size;
 219
 220     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
 221     cpuid = g_malloc0(size);
 222     cpuid->nent = max;
 223     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
 224     if (r == 0 && cpuid->nent >= max) {
 225         r = -E2BIG;
 226     }
 227     if (r < 0) {
 228         if (r == -E2BIG) {
 229             g_free(cpuid);
 230             return NULL;
 231         } else {
 232             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
 233                     strerror(-r));
 234             exit(1);
 235         }
 236     }
 237     return cpuid;
 238 }
 239
 240 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 241  * for all entries.
 242  */
 243 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 244 {
 245     struct kvm_cpuid2 *cpuid;
 246     int max = 1;
 247
 248     if (cpuid_cache != NULL) {
 249         return cpuid_cache;
 250     }
 251     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 252         max *= 2;
 253     }
 254     cpuid_cache = cpuid;
 255     return cpuid;
 256 }
 257
 258 static const struct kvm_para_features {
 259     int cap;
 260     int feature;
 261 } para_features[] = {
 262     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 263     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 264     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 265     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 266 };
 267
 268 static int get_para_features(KVMState *s)
 269 {
 270     int i, features = 0;
 271
 272     for (i = 0; i < ARRAY_SIZE(para_features); i++) {
 273         if (kvm_check_extension(s, para_features[i].cap)) {
 274             features |= (1 << para_features[i].feature);
 275         }
 276     }
 277
 278     return features;
 279 }
 280
 281 static bool host_tsx_blacklisted(void)
 282 {
 283     int family, model, stepping;\
 284     char vendor[CPUID_VENDOR_SZ + 1];
 285
 286     host_vendor_fms(vendor, &family, &model, &stepping);
 287
 288     /* Check if we are running on a Haswell host known to have broken TSX */
 289     return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
 290            (family == 6) &&
 291            ((model == 63 && stepping < 4) ||
 292             model == 60 || model == 69 || model == 70);
 293 }
 294
 295 /* Returns the value for a specific register on the cpuid entry
 296  */
 297 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 298 {
 299     uint32_t ret = 0;
 300     switch (reg) {
 301     case R_EAX:
 302         ret = entry->eax;
 303         break;
 304     case R_EBX:
 305         ret = entry->ebx;
 306         break;
 307     case R_ECX:
 308         ret = entry->ecx;
 309         break;
 310     case R_EDX:
 311         ret = entry->edx;
 312         break;
 313     }
 314     return ret;
 315 }
 316
 317 /* Find matching entry for function/index on kvm_cpuid2 struct
 318  */
 319 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 320                                                  uint32_t function,
 321                                                  uint32_t index)
 322 {
 323     int i;
 324     for (i = 0; i < cpuid->nent; ++i) {
 325         if (cpuid->entries[i].function == function &&
 326             cpuid->entries[i].index == index) {
 327             return &cpuid->entries[i];
 328         }
 329     }
 330     /* not found: */
 331     return NULL;
 332 }
 333
 334 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 335                                       uint32_t index, int reg)
 336 {
 337     struct kvm_cpuid2 *cpuid;
 338     uint32_t ret = 0;
 339     uint32_t cpuid_1_edx;
 340     bool found = false;
 341
 342     cpuid = get_supported_cpuid(s);
 343
 344     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 345     if (entry) {
 346         found = true;
 347         ret = cpuid_entry_get_reg(entry, reg);
 348     }
 349
 350     /* Fixups for the data returned by KVM, below */
 351
 352     if (function == 1 && reg == R_EDX) {
 353         /* KVM before 2.6.30 misreports the following features */
 354         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 355     } else if (function == 1 && reg == R_ECX) {
 356         /* We can set the hypervisor flag, even if KVM does not return it on
 357          * GET_SUPPORTED_CPUID
 358          */
 359         ret |= CPUID_EXT_HYPERVISOR;
 360         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 361          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 362          * and the irqchip is in the kernel.
 363          */
 364         if (kvm_irqchip_in_kernel() &&
 365                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 366             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 367         }
 368
 369         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 370          * without the in-kernel irqchip
 371          */
 372         if (!kvm_irqchip_in_kernel()) {
 373             ret &= ~CPUID_EXT_X2APIC;
 374         }
 375
 376         if (enable_cpu_pm) {
 377             int disable_exits = kvm_check_extension(s,
 378                                                     KVM_CAP_X86_DISABLE_EXITS);
 379
 380             if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
 381                 ret |= CPUID_EXT_MONITOR;
 382             }
 383         }
 384     } else if (function == 6 && reg == R_EAX) {
 385         ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
 386     } else if (function == 7 && index == 0 && reg == R_EBX) {
 387         if (host_tsx_blacklisted()) {
 388             ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
 389         }
 390     } else if (function == 0x80000001 && reg == R_ECX) {
 391         /*
 392          * It's safe to enable TOPOEXT even if it's not returned by
 393          * GET_SUPPORTED_CPUID.  Unconditionally enabling TOPOEXT here allows
 394          * us to keep CPU models including TOPOEXT runnable on older kernels.
 395          */
 396         ret |= CPUID_EXT3_TOPOEXT;
 397     } else if (function == 0x80000001 && reg == R_EDX) {
 398         /* On Intel, kvm returns cpuid according to the Intel spec,
 399          * so add missing bits according to the AMD spec:
 400          */
 401         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 402         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 403     } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
 404         /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
 405          * be enabled without the in-kernel irqchip
 406          */
 407         if (!kvm_irqchip_in_kernel()) {
 408             ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
 409         }
 410     } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
 411         ret |= 1U << KVM_HINTS_REALTIME;
 412         found = 1;
 413     }
 414
 415     /* fallback for older kernels */
 416     if ((function == KVM_CPUID_FEATURES) && !found) {
 417         ret = get_para_features(s);
 418     }
 419
 420     return ret;
 421 }
 422
 423 typedef struct HWPoisonPage {
 424     ram_addr_t ram_addr;
 425     QLIST_ENTRY(HWPoisonPage) list;
 426 } HWPoisonPage;
 427
 428 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 429     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 430
 431 static void kvm_unpoison_all(void *param)
 432 {
 433     HWPoisonPage *page, *next_page;
 434
 435     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 436         QLIST_REMOVE(page, list);
 437         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 438         g_free(page);
 439     }
 440 }
 441
 442 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 443 {
 444     HWPoisonPage *page;
 445
 446     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 447         if (page->ram_addr == ram_addr) {
 448             return;
 449         }
 450     }
 451     page = g_new(HWPoisonPage, 1);
 452     page->ram_addr = ram_addr;
 453     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 454 }
 455
 456 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 457                                      int *max_banks)
 458 {
 459     int r;
 460
 461     r = kvm_check_extension(s, KVM_CAP_MCE);
 462     if (r > 0) {
 463         *max_banks = r;
 464         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 465     }
 466     return -ENOSYS;
 467 }
 468
 469 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
 470 {
 471     CPUState *cs = CPU(cpu);
 472     CPUX86State *env = &cpu->env;
 473     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 474                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 475     uint64_t mcg_status = MCG_STATUS_MCIP;
 476     int flags = 0;
 477
 478     if (code == BUS_MCEERR_AR) {
 479         status |= MCI_STATUS_AR | 0x134;
 480         mcg_status |= MCG_STATUS_EIPV;
 481     } else {
 482         status |= 0xc0;
 483         mcg_status |= MCG_STATUS_RIPV;
 484     }
 485
 486     flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
 487     /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
 488      * guest kernel back into env->mcg_ext_ctl.
 489      */
 490     cpu_synchronize_state(cs);
 491     if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
 492         mcg_status |= MCG_STATUS_LMCE;
 493         flags = 0;
 494     }
 495
 496     cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
 497                        (MCM_ADDR_PHYS << 6) | 0xc, flags);
 498 }
 499
 500 static void hardware_memory_error(void)
 501 {
 502     fprintf(stderr, "Hardware memory error!\n");
 503     exit(1);
 504 }
 505
 506 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
 507 {
 508     X86CPU *cpu = X86_CPU(c);
 509     CPUX86State *env = &cpu->env;
 510     ram_addr_t ram_addr;
 511     hwaddr paddr;
 512
 513     /* If we get an action required MCE, it has been injected by KVM
 514      * while the VM was running.  An action optional MCE instead should
 515      * be coming from the main thread, which qemu_init_sigbus identifies
 516      * as the "early kill" thread.
 517      */
 518     assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
 519
 520     if ((env->mcg_cap & MCG_SER_P) && addr) {
 521         ram_addr = qemu_ram_addr_from_host(addr);
 522         if (ram_addr != RAM_ADDR_INVALID &&
 523             kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
 524             kvm_hwpoison_page_add(ram_addr);
 525             kvm_mce_inject(cpu, paddr, code);
 526             return;
 527         }
 528
 529         fprintf(stderr, "Hardware memory error for memory used by "
 530                 "QEMU itself instead of guest system!\n");
 531     }
 532
 533     if (code == BUS_MCEERR_AR) {
 534         hardware_memory_error();
 535     }
 536
 537     /* Hope we are lucky for AO MCE */
 538 }
 539
 540 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
 541 {
 542     CPUX86State *env = &cpu->env;
 543
 544     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 545         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 546         struct kvm_x86_mce mce;
 547
 548         env->exception_injected = -1;
 549
 550         /*
 551          * There must be at least one bank in use if an MCE is pending.
 552          * Find it and use its values for the event injection.
 553          */
 554         for (bank = 0; bank < bank_num; bank++) {
 555             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 556                 break;
 557             }
 558         }
 559         assert(bank < bank_num);
 560
 561         mce.bank = bank;
 562         mce.status = env->mce_banks[bank * 4 + 1];
 563         mce.mcg_status = env->mcg_status;
 564         mce.addr = env->mce_banks[bank * 4 + 2];
 565         mce.misc = env->mce_banks[bank * 4 + 3];
 566
 567         return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
 568     }
 569     return 0;
 570 }
 571
 572 static void cpu_update_state(void *opaque, int running, RunState state)
 573 {
 574     CPUX86State *env = opaque;
 575
 576     if (running) {
 577         env->tsc_valid = false;
 578     }
 579 }
 580
 581 unsigned long kvm_arch_vcpu_id(CPUState *cs)
 582 {
 583     X86CPU *cpu = X86_CPU(cs);
 584     return cpu->apic_id;
 585 }
 586
 587 #ifndef KVM_CPUID_SIGNATURE_NEXT
 588 #define KVM_CPUID_SIGNATURE_NEXT                0x40000100
 589 #endif
 590
 591 static bool hyperv_hypercall_available(X86CPU *cpu)
 592 {
 593     return cpu->hyperv_vapic ||
 594            (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
 595 }
 596
 597 static bool hyperv_enabled(X86CPU *cpu)
 598 {
 599     CPUState *cs = CPU(cpu);
 600     return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
 601            (hyperv_hypercall_available(cpu) ||
 602             cpu->hyperv_time  ||
 603             cpu->hyperv_relaxed_timing ||
 604             cpu->hyperv_crash ||
 605             cpu->hyperv_reset ||
 606             cpu->hyperv_vpindex ||
 607             cpu->hyperv_runtime ||
 608             cpu->hyperv_synic ||
 609             cpu->hyperv_stimer ||
 610             cpu->hyperv_reenlightenment ||
 611             cpu->hyperv_tlbflush);
 612 }
 613
 614 static int kvm_arch_set_tsc_khz(CPUState *cs)
 615 {
 616     X86CPU *cpu = X86_CPU(cs);
 617     CPUX86State *env = &cpu->env;
 618     int r;
 619
 620     if (!env->tsc_khz) {
 621         return 0;
 622     }
 623
 624     r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
 625         kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
 626         -ENOTSUP;
 627     if (r < 0) {
 628         /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
 629          * TSC frequency doesn't match the one we want.
 630          */
 631         int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
 632                        kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
 633                        -ENOTSUP;
 634         if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
 635             warn_report("TSC frequency mismatch between "
 636                         "VM (%" PRId64 " kHz) and host (%d kHz), "
 637                         "and TSC scaling unavailable",
 638                         env->tsc_khz, cur_freq);
 639             return r;
 640         }
 641     }
 642
 643     return 0;
 644 }
 645
 646 static bool tsc_is_stable_and_known(CPUX86State *env)
 647 {
 648     if (!env->tsc_khz) {
 649         return false;
 650     }
 651     return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
 652         || env->user_tsc_khz;
 653 }
 654
 655 static int hyperv_handle_properties(CPUState *cs)
 656 {
 657     X86CPU *cpu = X86_CPU(cs);
 658     CPUX86State *env = &cpu->env;
 659
 660     if (cpu->hyperv_relaxed_timing) {
 661         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 662     }
 663     if (cpu->hyperv_vapic) {
 664         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 665         env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
 666     }
 667     if (cpu->hyperv_time) {
 668         if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
 669             fprintf(stderr, "Hyper-V clocksources "
 670                     "(requested by 'hv-time' cpu flag) "
 671                     "are not supported by kernel\n");
 672             return -ENOSYS;
 673         }
 674         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 675         env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
 676         env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
 677     }
 678     if (cpu->hyperv_frequencies) {
 679         if (!has_msr_hv_frequencies) {
 680             fprintf(stderr, "Hyper-V frequency MSRs "
 681                     "(requested by 'hv-frequencies' cpu flag) "
 682                     "are not supported by kernel\n");
 683             return -ENOSYS;
 684         }
 685         env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
 686         env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
 687     }
 688     if (cpu->hyperv_crash) {
 689         if (!has_msr_hv_crash) {
 690             fprintf(stderr, "Hyper-V crash MSRs "
 691                     "(requested by 'hv-crash' cpu flag) "
 692                     "are not supported by kernel\n");
 693             return -ENOSYS;
 694         }
 695         env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
 696     }
 697     if (cpu->hyperv_reenlightenment) {
 698         if (!has_msr_hv_reenlightenment) {
 699             fprintf(stderr,
 700                     "Hyper-V Reenlightenment MSRs "
 701                     "(requested by 'hv-reenlightenment' cpu flag) "
 702                     "are not supported by kernel\n");
 703             return -ENOSYS;
 704         }
 705         env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
 706     }
 707     env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
 708     if (cpu->hyperv_reset) {
 709         if (!has_msr_hv_reset) {
 710             fprintf(stderr, "Hyper-V reset MSR "
 711                     "(requested by 'hv-reset' cpu flag) "
 712                     "is not supported by kernel\n");
 713             return -ENOSYS;
 714         }
 715         env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
 716     }
 717     if (cpu->hyperv_vpindex) {
 718         if (!has_msr_hv_vpindex) {
 719             fprintf(stderr, "Hyper-V VP_INDEX MSR "
 720                     "(requested by 'hv-vpindex' cpu flag) "
 721                     "is not supported by kernel\n");
 722             return -ENOSYS;
 723         }
 724         env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
 725     }
 726     if (cpu->hyperv_runtime) {
 727         if (!has_msr_hv_runtime) {
 728             fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
 729                     "(requested by 'hv-runtime' cpu flag) "
 730                     "is not supported by kernel\n");
 731             return -ENOSYS;
 732         }
 733         env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
 734     }
 735     if (cpu->hyperv_synic) {
 736         if (!has_msr_hv_synic ||
 737             kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
 738             fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
 739             return -ENOSYS;
 740         }
 741
 742         env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
 743     }
 744     if (cpu->hyperv_stimer) {
 745         if (!has_msr_hv_stimer) {
 746             fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
 747             return -ENOSYS;
 748         }
 749         env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
 750     }
 751     return 0;
 752 }
 753
 754 static int hyperv_init_vcpu(X86CPU *cpu)
 755 {
 756     if (cpu->hyperv_vpindex && !hv_vpindex_settable) {
 757         /*
 758          * the kernel doesn't support setting vp_index; assert that its value
 759          * is in sync
 760          */
 761         int ret;
 762         struct {
 763             struct kvm_msrs info;
 764             struct kvm_msr_entry entries[1];
 765         } msr_data = {
 766             .info.nmsrs = 1,
 767             .entries[0].index = HV_X64_MSR_VP_INDEX,
 768         };
 769
 770         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
 771         if (ret < 0) {
 772             return ret;
 773         }
 774         assert(ret == 1);
 775
 776         if (msr_data.entries[0].data != hyperv_vp_index(cpu)) {
 777             error_report("kernel's vp_index != QEMU's vp_index");
 778             return -ENXIO;
 779         }
 780     }
 781
 782     return 0;
 783 }
 784
 785 static Error *invtsc_mig_blocker;
 786
 787 #define KVM_MAX_CPUID_ENTRIES  100
 788
 789 int kvm_arch_init_vcpu(CPUState *cs)
 790 {
 791     struct {
 792         struct kvm_cpuid2 cpuid;
 793         struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
 794     } QEMU_PACKED cpuid_data;
 795     X86CPU *cpu = X86_CPU(cs);
 796     CPUX86State *env = &cpu->env;
 797     uint32_t limit, i, j, cpuid_i;
 798     uint32_t unused;
 799     struct kvm_cpuid_entry2 *c;
 800     uint32_t signature[3];
 801     int kvm_base = KVM_CPUID_SIGNATURE;
 802     int r;
 803     Error *local_err = NULL;
 804
 805     memset(&cpuid_data, 0, sizeof(cpuid_data));
 806
 807     cpuid_i = 0;
 808
 809     r = kvm_arch_set_tsc_khz(cs);
 810     if (r < 0) {
 811         goto fail;
 812     }
 813
 814     /* vcpu's TSC frequency is either specified by user, or following
 815      * the value used by KVM if the former is not present. In the
 816      * latter case, we query it from KVM and record in env->tsc_khz,
 817      * so that vcpu's TSC frequency can be migrated later via this field.
 818      */
 819     if (!env->tsc_khz) {
 820         r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
 821             kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
 822             -ENOTSUP;
 823         if (r > 0) {
 824             env->tsc_khz = r;
 825         }
 826     }
 827
 828     /* Paravirtualization CPUIDs */
 829     if (hyperv_enabled(cpu)) {
 830         c = &cpuid_data.entries[cpuid_i++];
 831         c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
 832         if (!cpu->hyperv_vendor_id) {
 833             memcpy(signature, "Microsoft Hv", 12);
 834         } else {
 835             size_t len = strlen(cpu->hyperv_vendor_id);
 836
 837             if (len > 12) {
 838                 error_report("hv-vendor-id truncated to 12 characters");
 839                 len = 12;
 840             }
 841             memset(signature, 0, 12);
 842             memcpy(signature, cpu->hyperv_vendor_id, len);
 843         }
 844         c->eax = HV_CPUID_MIN;
 845         c->ebx = signature[0];
 846         c->ecx = signature[1];
 847         c->edx = signature[2];
 848
 849         c = &cpuid_data.entries[cpuid_i++];
 850         c->function = HV_CPUID_INTERFACE;
 851         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 852         c->eax = signature[0];
 853         c->ebx = 0;
 854         c->ecx = 0;
 855         c->edx = 0;
 856
 857         c = &cpuid_data.entries[cpuid_i++];
 858         c->function = HV_CPUID_VERSION;
 859         c->eax = 0x00001bbc;
 860         c->ebx = 0x00060001;
 861
 862         c = &cpuid_data.entries[cpuid_i++];
 863         c->function = HV_CPUID_FEATURES;
 864         r = hyperv_handle_properties(cs);
 865         if (r) {
 866             return r;
 867         }
 868         c->eax = env->features[FEAT_HYPERV_EAX];
 869         c->ebx = env->features[FEAT_HYPERV_EBX];
 870         c->edx = env->features[FEAT_HYPERV_EDX];
 871
 872         c = &cpuid_data.entries[cpuid_i++];
 873         c->function = HV_CPUID_ENLIGHTMENT_INFO;
 874         if (cpu->hyperv_relaxed_timing) {
 875             c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
 876         }
 877         if (cpu->hyperv_vapic) {
 878             c->eax |= HV_APIC_ACCESS_RECOMMENDED;
 879         }
 880         if (cpu->hyperv_tlbflush) {
 881             if (kvm_check_extension(cs->kvm_state,
 882                                     KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
 883                 fprintf(stderr, "Hyper-V TLB flush support "
 884                         "(requested by 'hv-tlbflush' cpu flag) "
 885                         " is not supported by kernel\n");
 886                 return -ENOSYS;
 887             }
 888             c->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
 889             c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
 890         }
 891
 892         c->ebx = cpu->hyperv_spinlock_attempts;
 893
 894         c = &cpuid_data.entries[cpuid_i++];
 895         c->function = HV_CPUID_IMPLEMENT_LIMITS;
 896
 897         c->eax = cpu->hv_max_vps;
 898         c->ebx = 0x40;
 899
 900         kvm_base = KVM_CPUID_SIGNATURE_NEXT;
 901         has_msr_hv_hypercall = true;
 902     }
 903
 904     if (cpu->expose_kvm) {
 905         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 906         c = &cpuid_data.entries[cpuid_i++];
 907         c->function = KVM_CPUID_SIGNATURE | kvm_base;
 908         c->eax = KVM_CPUID_FEATURES | kvm_base;
 909         c->ebx = signature[0];
 910         c->ecx = signature[1];
 911         c->edx = signature[2];
 912
 913         c = &cpuid_data.entries[cpuid_i++];
 914         c->function = KVM_CPUID_FEATURES | kvm_base;
 915         c->eax = env->features[FEAT_KVM];
 916         c->edx = env->features[FEAT_KVM_HINTS];
 917     }
 918
 919     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 920
 921     for (i = 0; i <= limit; i++) {
 922         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 923             fprintf(stderr, "unsupported level value: 0x%x\n", limit);
 924             abort();
 925         }
 926         c = &cpuid_data.entries[cpuid_i++];
 927
 928         switch (i) {
 929         case 2: {
 930             /* Keep reading function 2 till all the input is received */
 931             int times;
 932
 933             c->function = i;
 934             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 935                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 936             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 937             times = c->eax & 0xff;
 938
 939             for (j = 1; j < times; ++j) {
 940                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 941                     fprintf(stderr, "cpuid_data is full, no space for "
 942                             "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
 943                     abort();
 944                 }
 945                 c = &cpuid_data.entries[cpuid_i++];
 946                 c->function = i;
 947                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 948                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 949             }
 950             break;
 951         }
 952         case 4:
 953         case 0xb:
 954         case 0xd:
 955             for (j = 0; ; j++) {
 956                 if (i == 0xd && j == 64) {
 957                     break;
 958                 }
 959                 c->function = i;
 960                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 961                 c->index = j;
 962                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 963
 964                 if (i == 4 && c->eax == 0) {
 965                     break;
 966                 }
 967                 if (i == 0xb && !(c->ecx & 0xff00)) {
 968                     break;
 969                 }
 970                 if (i == 0xd && c->eax == 0) {
 971                     continue;
 972                 }
 973                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 974                     fprintf(stderr, "cpuid_data is full, no space for "
 975                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
 976                     abort();
 977                 }
 978                 c = &cpuid_data.entries[cpuid_i++];
 979             }
 980             break;
 981         case 0x14: {
 982             uint32_t times;
 983
 984             c->function = i;
 985             c->index = 0;
 986             c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 987             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 988             times = c->eax;
 989
 990             for (j = 1; j <= times; ++j) {
 991                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 992                     fprintf(stderr, "cpuid_data is full, no space for "
 993                                 "cpuid(eax:0x14,ecx:0x%x)\n", j);
 994                     abort();
 995                 }
 996                 c = &cpuid_data.entries[cpuid_i++];
 997                 c->function = i;
 998                 c->index = j;
 999                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1000                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1001             }
1002             break;
1003         }
1004         default:
1005             c->function = i;
1006             c->flags = 0;
1007             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1008             break;
1009         }
1010     }
1011
1012     if (limit >= 0x0a) {
1013         uint32_t eax, edx;
1014
1015         cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1016
1017         has_architectural_pmu_version = eax & 0xff;
1018         if (has_architectural_pmu_version > 0) {
1019             num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1020
1021             /* Shouldn't be more than 32, since that's the number of bits
1022              * available in EBX to tell us _which_ counters are available.
1023              * Play it safe.
1024              */
1025             if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1026                 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1027             }
1028
1029             if (has_architectural_pmu_version > 1) {
1030                 num_architectural_pmu_fixed_counters = edx & 0x1f;
1031
1032                 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1033                     num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1034                 }
1035             }
1036         }
1037     }
1038
1039     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1040
1041     for (i = 0x80000000; i <= limit; i++) {
1042         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1043             fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1044             abort();
1045         }
1046         c = &cpuid_data.entries[cpuid_i++];
1047
1048         switch (i) {
1049         case 0x8000001d:
1050             /* Query for all AMD cache information leaves */
1051             for (j = 0; ; j++) {
1052                 c->function = i;
1053                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1054                 c->index = j;
1055                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1056
1057                 if (c->eax == 0) {
1058                     break;
1059                 }
1060                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1061                     fprintf(stderr, "cpuid_data is full, no space for "
1062                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1063                     abort();
1064                 }
1065                 c = &cpuid_data.entries[cpuid_i++];
1066             }
1067             break;
1068         default:
1069             c->function = i;
1070             c->flags = 0;
1071             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1072             break;
1073         }
1074     }
1075
1076     /* Call Centaur's CPUID instructions they are supported. */
1077     if (env->cpuid_xlevel2 > 0) {
1078         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1079
1080         for (i = 0xC0000000; i <= limit; i++) {
1081             if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1082                 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1083                 abort();
1084             }
1085             c = &cpuid_data.entries[cpuid_i++];
1086
1087             c->function = i;
1088             c->flags = 0;
1089             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1090         }
1091     }
1092
1093     cpuid_data.cpuid.nent = cpuid_i;
1094
1095     if (((env->cpuid_version >> 8)&0xF) >= 6
1096         && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1097            (CPUID_MCE | CPUID_MCA)
1098         && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1099         uint64_t mcg_cap, unsupported_caps;
1100         int banks;
1101         int ret;
1102
1103         ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1104         if (ret < 0) {
1105             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1106             return ret;
1107         }
1108
1109         if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1110             error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1111                          (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1112             return -ENOTSUP;
1113         }
1114
1115         unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1116         if (unsupported_caps) {
1117             if (unsupported_caps & MCG_LMCE_P) {
1118                 error_report("kvm: LMCE not supported");
1119                 return -ENOTSUP;
1120             }
1121             warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1122                         unsupported_caps);
1123         }
1124
1125         env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1126         ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1127         if (ret < 0) {
1128             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1129             return ret;
1130         }
1131     }
1132
1133     qemu_add_vm_change_state_handler(cpu_update_state, env);
1134
1135     c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1136     if (c) {
1137         has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1138                                   !!(c->ecx & CPUID_EXT_SMX);
1139     }
1140
1141     if (env->mcg_cap & MCG_LMCE_P) {
1142         has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1143     }
1144
1145     if (!env->user_tsc_khz) {
1146         if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1147             invtsc_mig_blocker == NULL) {
1148             /* for migration */
1149             error_setg(&invtsc_mig_blocker,
1150                        "State blocked by non-migratable CPU device"
1151                        " (invtsc flag)");
1152             r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1153             if (local_err) {
1154                 error_report_err(local_err);
1155                 error_free(invtsc_mig_blocker);
1156                 goto fail;
1157             }
1158             /* for savevm */
1159             vmstate_x86_cpu.unmigratable = 1;
1160         }
1161     }
1162
1163     if (cpu->vmware_cpuid_freq
1164         /* Guests depend on 0x40000000 to detect this feature, so only expose
1165          * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1166         && cpu->expose_kvm
1167         && kvm_base == KVM_CPUID_SIGNATURE
1168         /* TSC clock must be stable and known for this feature. */
1169         && tsc_is_stable_and_known(env)) {
1170
1171         c = &cpuid_data.entries[cpuid_i++];
1172         c->function = KVM_CPUID_SIGNATURE | 0x10;
1173         c->eax = env->tsc_khz;
1174         /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1175          * APIC_BUS_CYCLE_NS */
1176         c->ebx = 1000000;
1177         c->ecx = c->edx = 0;
1178
1179         c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1180         c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1181     }
1182
1183     cpuid_data.cpuid.nent = cpuid_i;
1184
1185     cpuid_data.cpuid.padding = 0;
1186     r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1187     if (r) {
1188         goto fail;
1189     }
1190
1191     if (has_xsave) {
1192         env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1193     }
1194     cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1195
1196     if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1197         has_msr_tsc_aux = false;
1198     }
1199
1200     r = hyperv_init_vcpu(cpu);
1201     if (r) {
1202         goto fail;
1203     }
1204
1205     return 0;
1206
1207  fail:
1208     migrate_del_blocker(invtsc_mig_blocker);
1209     return r;
1210 }
1211
1212 void kvm_arch_reset_vcpu(X86CPU *cpu)
1213 {
1214     CPUX86State *env = &cpu->env;
1215
1216     env->xcr0 = 1;
1217     if (kvm_irqchip_in_kernel()) {
1218         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1219                                           KVM_MP_STATE_UNINITIALIZED;
1220     } else {
1221         env->mp_state = KVM_MP_STATE_RUNNABLE;
1222     }
1223
1224     if (cpu->hyperv_synic) {
1225         int i;
1226         for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1227             env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1228         }
1229     }
1230 }
1231
1232 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1233 {
1234     CPUX86State *env = &cpu->env;
1235
1236     /* APs get directly into wait-for-SIPI state.  */
1237     if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1238         env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1239     }
1240 }
1241
1242 static int kvm_get_supported_msrs(KVMState *s)
1243 {
1244     static int kvm_supported_msrs;
1245     int ret = 0;
1246
1247     /* first time */
1248     if (kvm_supported_msrs == 0) {
1249         struct kvm_msr_list msr_list, *kvm_msr_list;
1250
1251         kvm_supported_msrs = -1;
1252
1253         /* Obtain MSR list from KVM.  These are the MSRs that we must
1254          * save/restore */
1255         msr_list.nmsrs = 0;
1256         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1257         if (ret < 0 && ret != -E2BIG) {
1258             return ret;
1259         }
1260         /* Old kernel modules had a bug and could write beyond the provided
1261            memory. Allocate at least a safe amount of 1K. */
1262         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1263                                               msr_list.nmsrs *
1264                                               sizeof(msr_list.indices[0])));
1265
1266         kvm_msr_list->nmsrs = msr_list.nmsrs;
1267         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1268         if (ret >= 0) {
1269             int i;
1270
1271             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1272                 switch (kvm_msr_list->indices[i]) {
1273                 case MSR_STAR:
1274                     has_msr_star = true;
1275                     break;
1276                 case MSR_VM_HSAVE_PA:
1277                     has_msr_hsave_pa = true;
1278                     break;
1279                 case MSR_TSC_AUX:
1280                     has_msr_tsc_aux = true;
1281                     break;
1282                 case MSR_TSC_ADJUST:
1283                     has_msr_tsc_adjust = true;
1284                     break;
1285                 case MSR_IA32_TSCDEADLINE:
1286                     has_msr_tsc_deadline = true;
1287                     break;
1288                 case MSR_IA32_SMBASE:
1289                     has_msr_smbase = true;
1290                     break;
1291                 case MSR_SMI_COUNT:
1292                     has_msr_smi_count = true;
1293                     break;
1294                 case MSR_IA32_MISC_ENABLE:
1295                     has_msr_misc_enable = true;
1296                     break;
1297                 case MSR_IA32_BNDCFGS:
1298                     has_msr_bndcfgs = true;
1299                     break;
1300                 case MSR_IA32_XSS:
1301                     has_msr_xss = true;
1302                     break;
1303                 case HV_X64_MSR_CRASH_CTL:
1304                     has_msr_hv_crash = true;
1305                     break;
1306                 case HV_X64_MSR_RESET:
1307                     has_msr_hv_reset = true;
1308                     break;
1309                 case HV_X64_MSR_VP_INDEX:
1310                     has_msr_hv_vpindex = true;
1311                     break;
1312                 case HV_X64_MSR_VP_RUNTIME:
1313                     has_msr_hv_runtime = true;
1314                     break;
1315                 case HV_X64_MSR_SCONTROL:
1316                     has_msr_hv_synic = true;
1317                     break;
1318                 case HV_X64_MSR_STIMER0_CONFIG:
1319                     has_msr_hv_stimer = true;
1320                     break;
1321                 case HV_X64_MSR_TSC_FREQUENCY:
1322                     has_msr_hv_frequencies = true;
1323                     break;
1324                 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1325                     has_msr_hv_reenlightenment = true;
1326                     break;
1327                 case MSR_IA32_SPEC_CTRL:
1328                     has_msr_spec_ctrl = true;
1329                     break;
1330                 case MSR_VIRT_SSBD:
1331                     has_msr_virt_ssbd = true;
1332                     break;
1333                 }
1334             }
1335         }
1336
1337         g_free(kvm_msr_list);
1338     }
1339
1340     return ret;
1341 }
1342
1343 static Notifier smram_machine_done;
1344 static KVMMemoryListener smram_listener;
1345 static AddressSpace smram_address_space;
1346 static MemoryRegion smram_as_root;
1347 static MemoryRegion smram_as_mem;
1348
1349 static void register_smram_listener(Notifier *n, void *unused)
1350 {
1351     MemoryRegion *smram =
1352         (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1353
1354     /* Outer container... */
1355     memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1356     memory_region_set_enabled(&smram_as_root, true);
1357
1358     /* ... with two regions inside: normal system memory with low
1359      * priority, and...
1360      */
1361     memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1362                              get_system_memory(), 0, ~0ull);
1363     memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1364     memory_region_set_enabled(&smram_as_mem, true);
1365
1366     if (smram) {
1367         /* ... SMRAM with higher priority */
1368         memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1369         memory_region_set_enabled(smram, true);
1370     }
1371
1372     address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1373     kvm_memory_listener_register(kvm_state, &smram_listener,
1374                                  &smram_address_space, 1);
1375 }
1376
1377 int kvm_arch_init(MachineState *ms, KVMState *s)
1378 {
1379     uint64_t identity_base = 0xfffbc000;
1380     uint64_t shadow_mem;
1381     int ret;
1382     struct utsname utsname;
1383
1384     has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1385     has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1386     has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1387
1388     hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1389
1390     ret = kvm_get_supported_msrs(s);
1391     if (ret < 0) {
1392         return ret;
1393     }
1394
1395     uname(&utsname);
1396     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1397
1398     /*
1399      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1400      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
1401      * Since these must be part of guest physical memory, we need to allocate
1402      * them, both by setting their start addresses in the kernel and by
1403      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1404      *
1405      * Older KVM versions may not support setting the identity map base. In
1406      * that case we need to stick with the default, i.e. a 256K maximum BIOS
1407      * size.
1408      */
1409     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1410         /* Allows up to 16M BIOSes. */
1411         identity_base = 0xfeffc000;
1412
1413         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1414         if (ret < 0) {
1415             return ret;
1416         }
1417     }
1418
1419     /* Set TSS base one page after EPT identity map. */
1420     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1421     if (ret < 0) {
1422         return ret;
1423     }
1424
1425     /* Tell fw_cfg to notify the BIOS to reserve the range. */
1426     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1427     if (ret < 0) {
1428         fprintf(stderr, "e820_add_entry() table is full\n");
1429         return ret;
1430     }
1431     qemu_register_reset(kvm_unpoison_all, NULL);
1432
1433     shadow_mem = machine_kvm_shadow_mem(ms);
1434     if (shadow_mem != -1) {
1435         shadow_mem /= 4096;
1436         ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1437         if (ret < 0) {
1438             return ret;
1439         }
1440     }
1441
1442     if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1443         object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1444         pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1445         smram_machine_done.notify = register_smram_listener;
1446         qemu_add_machine_init_done_notifier(&smram_machine_done);
1447     }
1448
1449     if (enable_cpu_pm) {
1450         int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1451         int ret;
1452
1453 /* Work around for kernel header with a typo. TODO: fix header and drop. */
1454 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1455 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1456 #endif
1457         if (disable_exits) {
1458             disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1459                               KVM_X86_DISABLE_EXITS_HLT |
1460                               KVM_X86_DISABLE_EXITS_PAUSE);
1461         }
1462
1463         ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1464                                 disable_exits);
1465         if (ret < 0) {
1466             error_report("kvm: guest stopping CPU not supported: %s",
1467                          strerror(-ret));
1468         }
1469     }
1470
1471     return 0;
1472 }
1473
1474 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1475 {
1476     lhs->selector = rhs->selector;
1477     lhs->base = rhs->base;
1478     lhs->limit = rhs->limit;
1479     lhs->type = 3;
1480     lhs->present = 1;
1481     lhs->dpl = 3;
1482     lhs->db = 0;
1483     lhs->s = 1;
1484     lhs->l = 0;
1485     lhs->g = 0;
1486     lhs->avl = 0;
1487     lhs->unusable = 0;
1488 }
1489
1490 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1491 {
1492     unsigned flags = rhs->flags;
1493     lhs->selector = rhs->selector;
1494     lhs->base = rhs->base;
1495     lhs->limit = rhs->limit;
1496     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1497     lhs->present = (flags & DESC_P_MASK) != 0;
1498     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1499     lhs->db = (flags >> DESC_B_SHIFT) & 1;
1500     lhs->s = (flags & DESC_S_MASK) != 0;
1501     lhs->l = (flags >> DESC_L_SHIFT) & 1;
1502     lhs->g = (flags & DESC_G_MASK) != 0;
1503     lhs->avl = (flags & DESC_AVL_MASK) != 0;
1504     lhs->unusable = !lhs->present;
1505     lhs->padding = 0;
1506 }
1507
1508 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1509 {
1510     lhs->selector = rhs->selector;
1511     lhs->base = rhs->base;
1512     lhs->limit = rhs->limit;
1513     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1514                  ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1515                  (rhs->dpl << DESC_DPL_SHIFT) |
1516                  (rhs->db << DESC_B_SHIFT) |
1517                  (rhs->s * DESC_S_MASK) |
1518                  (rhs->l << DESC_L_SHIFT) |
1519                  (rhs->g * DESC_G_MASK) |
1520                  (rhs->avl * DESC_AVL_MASK);
1521 }
1522
1523 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1524 {
1525     if (set) {
1526         *kvm_reg = *qemu_reg;
1527     } else {
1528         *qemu_reg = *kvm_reg;
1529     }
1530 }
1531
1532 static int kvm_getput_regs(X86CPU *cpu, int set)
1533 {
1534     CPUX86State *env = &cpu->env;
1535     struct kvm_regs regs;
1536     int ret = 0;
1537
1538     if (!set) {
1539         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1540         if (ret < 0) {
1541             return ret;
1542         }
1543     }
1544
1545     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1546     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1547     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1548     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1549     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1550     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1551     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1552     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1553 #ifdef TARGET_X86_64
1554     kvm_getput_reg(&regs.r8, &env->regs[8], set);
1555     kvm_getput_reg(&regs.r9, &env->regs[9], set);
1556     kvm_getput_reg(&regs.r10, &env->regs[10], set);
1557     kvm_getput_reg(&regs.r11, &env->regs[11], set);
1558     kvm_getput_reg(&regs.r12, &env->regs[12], set);
1559     kvm_getput_reg(&regs.r13, &env->regs[13], set);
1560     kvm_getput_reg(&regs.r14, &env->regs[14], set);
1561     kvm_getput_reg(&regs.r15, &env->regs[15], set);
1562 #endif
1563
1564     kvm_getput_reg(&regs.rflags, &env->eflags, set);
1565     kvm_getput_reg(&regs.rip, &env->eip, set);
1566
1567     if (set) {
1568         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1569     }
1570
1571     return ret;
1572 }
1573
1574 static int kvm_put_fpu(X86CPU *cpu)
1575 {
1576     CPUX86State *env = &cpu->env;
1577     struct kvm_fpu fpu;
1578     int i;
1579
1580     memset(&fpu, 0, sizeof fpu);
1581     fpu.fsw = env->fpus & ~(7 << 11);
1582     fpu.fsw |= (env->fpstt & 7) << 11;
1583     fpu.fcw = env->fpuc;
1584     fpu.last_opcode = env->fpop;
1585     fpu.last_ip = env->fpip;
1586     fpu.last_dp = env->fpdp;
1587     for (i = 0; i < 8; ++i) {
1588         fpu.ftwx |= (!env->fptags[i]) << i;
1589     }
1590     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1591     for (i = 0; i < CPU_NB_REGS; i++) {
1592         stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1593         stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1594     }
1595     fpu.mxcsr = env->mxcsr;
1596
1597     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1598 }
1599
1600 #define XSAVE_FCW_FSW     0
1601 #define XSAVE_FTW_FOP     1
1602 #define XSAVE_CWD_RIP     2
1603 #define XSAVE_CWD_RDP     4
1604 #define XSAVE_MXCSR       6
1605 #define XSAVE_ST_SPACE    8
1606 #define XSAVE_XMM_SPACE   40
1607 #define XSAVE_XSTATE_BV   128
1608 #define XSAVE_YMMH_SPACE  144
1609 #define XSAVE_BNDREGS     240
1610 #define XSAVE_BNDCSR      256
1611 #define XSAVE_OPMASK      272
1612 #define XSAVE_ZMM_Hi256   288
1613 #define XSAVE_Hi16_ZMM    416
1614 #define XSAVE_PKRU        672
1615
1616 #define XSAVE_BYTE_OFFSET(word_offset) \
1617     ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
1618
1619 #define ASSERT_OFFSET(word_offset, field) \
1620     QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1621                       offsetof(X86XSaveArea, field))
1622
1623 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1624 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1625 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1626 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1627 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1628 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1629 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1630 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1631 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1632 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1633 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1634 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1635 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1636 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1637 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1638
1639 static int kvm_put_xsave(X86CPU *cpu)
1640 {
1641     CPUX86State *env = &cpu->env;
1642     X86XSaveArea *xsave = env->xsave_buf;
1643
1644     if (!has_xsave) {
1645         return kvm_put_fpu(cpu);
1646     }
1647     x86_cpu_xsave_all_areas(cpu, xsave);
1648
1649     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1650 }
1651
1652 static int kvm_put_xcrs(X86CPU *cpu)
1653 {
1654     CPUX86State *env = &cpu->env;
1655     struct kvm_xcrs xcrs = {};
1656
1657     if (!has_xcrs) {
1658         return 0;
1659     }
1660
1661     xcrs.nr_xcrs = 1;
1662     xcrs.flags = 0;
1663     xcrs.xcrs[0].xcr = 0;
1664     xcrs.xcrs[0].value = env->xcr0;
1665     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1666 }
1667
1668 static int kvm_put_sregs(X86CPU *cpu)
1669 {
1670     CPUX86State *env = &cpu->env;
1671     struct kvm_sregs sregs;
1672
1673     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1674     if (env->interrupt_injected >= 0) {
1675         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1676                 (uint64_t)1 << (env->interrupt_injected % 64);
1677     }
1678
1679     if ((env->eflags & VM_MASK)) {
1680         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1681         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1682         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1683         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1684         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1685         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1686     } else {
1687         set_seg(&sregs.cs, &env->segs[R_CS]);
1688         set_seg(&sregs.ds, &env->segs[R_DS]);
1689         set_seg(&sregs.es, &env->segs[R_ES]);
1690         set_seg(&sregs.fs, &env->segs[R_FS]);
1691         set_seg(&sregs.gs, &env->segs[R_GS]);
1692         set_seg(&sregs.ss, &env->segs[R_SS]);
1693     }
1694
1695     set_seg(&sregs.tr, &env->tr);
1696     set_seg(&sregs.ldt, &env->ldt);
1697
1698     sregs.idt.limit = env->idt.limit;
1699     sregs.idt.base = env->idt.base;
1700     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1701     sregs.gdt.limit = env->gdt.limit;
1702     sregs.gdt.base = env->gdt.base;
1703     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1704
1705     sregs.cr0 = env->cr[0];
1706     sregs.cr2 = env->cr[2];
1707     sregs.cr3 = env->cr[3];
1708     sregs.cr4 = env->cr[4];
1709
1710     sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1711     sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1712
1713     sregs.efer = env->efer;
1714
1715     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1716 }
1717
1718 static void kvm_msr_buf_reset(X86CPU *cpu)
1719 {
1720     memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1721 }
1722
1723 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1724 {
1725     struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1726     void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1727     struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1728
1729     assert((void *)(entry + 1) <= limit);
1730
1731     entry->index = index;
1732     entry->reserved = 0;
1733     entry->data = value;
1734     msrs->nmsrs++;
1735 }
1736
1737 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1738 {
1739     kvm_msr_buf_reset(cpu);
1740     kvm_msr_entry_add(cpu, index, value);
1741
1742     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1743 }
1744
1745 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1746 {
1747     int ret;
1748
1749     ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1750     assert(ret == 1);
1751 }
1752
1753 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1754 {
1755     CPUX86State *env = &cpu->env;
1756     int ret;
1757
1758     if (!has_msr_tsc_deadline) {
1759         return 0;
1760     }
1761
1762     ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1763     if (ret < 0) {
1764         return ret;
1765     }
1766
1767     assert(ret == 1);
1768     return 0;
1769 }
1770
1771 /*
1772  * Provide a separate write service for the feature control MSR in order to
1773  * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1774  * before writing any other state because forcibly leaving nested mode
1775  * invalidates the VCPU state.
1776  */
1777 static int kvm_put_msr_feature_control(X86CPU *cpu)
1778 {
1779     int ret;
1780
1781     if (!has_msr_feature_control) {
1782         return 0;
1783     }
1784
1785     ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1786                           cpu->env.msr_ia32_feature_control);
1787     if (ret < 0) {
1788         return ret;
1789     }
1790
1791     assert(ret == 1);
1792     return 0;
1793 }
1794
1795 static int kvm_put_msrs(X86CPU *cpu, int level)
1796 {
1797     CPUX86State *env = &cpu->env;
1798     int i;
1799     int ret;
1800
1801     kvm_msr_buf_reset(cpu);
1802
1803     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1804     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1805     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1806     kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1807     if (has_msr_star) {
1808         kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1809     }
1810     if (has_msr_hsave_pa) {
1811         kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1812     }
1813     if (has_msr_tsc_aux) {
1814         kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1815     }
1816     if (has_msr_tsc_adjust) {
1817         kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1818     }
1819     if (has_msr_misc_enable) {
1820         kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1821                           env->msr_ia32_misc_enable);
1822     }
1823     if (has_msr_smbase) {
1824         kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1825     }
1826     if (has_msr_smi_count) {
1827         kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1828     }
1829     if (has_msr_bndcfgs) {
1830         kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1831     }
1832     if (has_msr_xss) {
1833         kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1834     }
1835     if (has_msr_spec_ctrl) {
1836         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1837     }
1838     if (has_msr_virt_ssbd) {
1839         kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
1840     }
1841
1842 #ifdef TARGET_X86_64
1843     if (lm_capable_kernel) {
1844         kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1845         kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1846         kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1847         kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1848     }
1849 #endif
1850
1851     /*
1852      * The following MSRs have side effects on the guest or are too heavy
1853      * for normal writeback. Limit them to reset or full state updates.
1854      */
1855     if (level >= KVM_PUT_RESET_STATE) {
1856         kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1857         kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1858         kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1859         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1860             kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1861         }
1862         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1863             kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1864         }
1865         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1866             kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1867         }
1868         if (has_architectural_pmu_version > 0) {
1869             if (has_architectural_pmu_version > 1) {
1870                 /* Stop the counter.  */
1871                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1872                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1873             }
1874
1875             /* Set the counter values.  */
1876             for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
1877                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1878                                   env->msr_fixed_counters[i]);
1879             }
1880             for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
1881                 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1882                                   env->msr_gp_counters[i]);
1883                 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1884                                   env->msr_gp_evtsel[i]);
1885             }
1886             if (has_architectural_pmu_version > 1) {
1887                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1888                                   env->msr_global_status);
1889                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1890                                   env->msr_global_ovf_ctrl);
1891
1892                 /* Now start the PMU.  */
1893                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1894                                   env->msr_fixed_ctr_ctrl);
1895                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1896                                   env->msr_global_ctrl);
1897             }
1898         }
1899         /*
1900          * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1901          * only sync them to KVM on the first cpu
1902          */
1903         if (current_cpu == first_cpu) {
1904             if (has_msr_hv_hypercall) {
1905                 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1906                                   env->msr_hv_guest_os_id);
1907                 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1908                                   env->msr_hv_hypercall);
1909             }
1910             if (cpu->hyperv_time) {
1911                 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1912                                   env->msr_hv_tsc);
1913             }
1914             if (cpu->hyperv_reenlightenment) {
1915                 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
1916                                   env->msr_hv_reenlightenment_control);
1917                 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
1918                                   env->msr_hv_tsc_emulation_control);
1919                 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
1920                                   env->msr_hv_tsc_emulation_status);
1921             }
1922         }
1923         if (cpu->hyperv_vapic) {
1924             kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1925                               env->msr_hv_vapic);
1926         }
1927         if (has_msr_hv_crash) {
1928             int j;
1929
1930             for (j = 0; j < HV_CRASH_PARAMS; j++)
1931                 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1932                                   env->msr_hv_crash_params[j]);
1933
1934             kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
1935         }
1936         if (has_msr_hv_runtime) {
1937             kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1938         }
1939         if (cpu->hyperv_vpindex && hv_vpindex_settable) {
1940             kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX, hyperv_vp_index(cpu));
1941         }
1942         if (cpu->hyperv_synic) {
1943             int j;
1944
1945             kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1946
1947             kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1948                               env->msr_hv_synic_control);
1949             kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1950                               env->msr_hv_synic_evt_page);
1951             kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1952                               env->msr_hv_synic_msg_page);
1953
1954             for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1955                 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1956                                   env->msr_hv_synic_sint[j]);
1957             }
1958         }
1959         if (has_msr_hv_stimer) {
1960             int j;
1961
1962             for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1963                 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1964                                 env->msr_hv_stimer_config[j]);
1965             }
1966
1967             for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1968                 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1969                                 env->msr_hv_stimer_count[j]);
1970             }
1971         }
1972         if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1973             uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1974
1975             kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1976             kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1977             kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1978             kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1979             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1980             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1981             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1982             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1983             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1984             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1985             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1986             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1987             for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1988                 /* The CPU GPs if we write to a bit above the physical limit of
1989                  * the host CPU (and KVM emulates that)
1990                  */
1991                 uint64_t mask = env->mtrr_var[i].mask;
1992                 mask &= phys_mask;
1993
1994                 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1995                                   env->mtrr_var[i].base);
1996                 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1997             }
1998         }
1999         if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2000             int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2001                                                     0x14, 1, R_EAX) & 0x7;
2002
2003             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2004                             env->msr_rtit_ctrl);
2005             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2006                             env->msr_rtit_status);
2007             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2008                             env->msr_rtit_output_base);
2009             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2010                             env->msr_rtit_output_mask);
2011             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2012                             env->msr_rtit_cr3_match);
2013             for (i = 0; i < addr_num; i++) {
2014                 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2015                             env->msr_rtit_addrs[i]);
2016             }
2017         }
2018
2019         /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2020          *       kvm_put_msr_feature_control. */
2021     }
2022     if (env->mcg_cap) {
2023         int i;
2024
2025         kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2026         kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2027         if (has_msr_mcg_ext_ctl) {
2028             kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2029         }
2030         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2031             kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2032         }
2033     }
2034
2035     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2036     if (ret < 0) {
2037         return ret;
2038     }
2039
2040     if (ret < cpu->kvm_msr_buf->nmsrs) {
2041         struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2042         error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2043                      (uint32_t)e->index, (uint64_t)e->data);
2044     }
2045
2046     assert(ret == cpu->kvm_msr_buf->nmsrs);
2047     return 0;
2048 }
2049
2050
2051 static int kvm_get_fpu(X86CPU *cpu)
2052 {
2053     CPUX86State *env = &cpu->env;
2054     struct kvm_fpu fpu;
2055     int i, ret;
2056
2057     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
2058     if (ret < 0) {
2059         return ret;
2060     }
2061
2062     env->fpstt = (fpu.fsw >> 11) & 7;
2063     env->fpus = fpu.fsw;
2064     env->fpuc = fpu.fcw;
2065     env->fpop = fpu.last_opcode;
2066     env->fpip = fpu.last_ip;
2067     env->fpdp = fpu.last_dp;
2068     for (i = 0; i < 8; ++i) {
2069         env->fptags[i] = !((fpu.ftwx >> i) & 1);
2070     }
2071     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
2072     for (i = 0; i < CPU_NB_REGS; i++) {
2073         env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2074         env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
2075     }
2076     env->mxcsr = fpu.mxcsr;
2077
2078     return 0;
2079 }
2080
2081 static int kvm_get_xsave(X86CPU *cpu)
2082 {
2083     CPUX86State *env = &cpu->env;
2084     X86XSaveArea *xsave = env->xsave_buf;
2085     int ret;
2086
2087     if (!has_xsave) {
2088         return kvm_get_fpu(cpu);
2089     }
2090
2091     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
2092     if (ret < 0) {
2093         return ret;
2094     }
2095     x86_cpu_xrstor_all_areas(cpu, xsave);
2096
2097     return 0;
2098 }
2099
2100 static int kvm_get_xcrs(X86CPU *cpu)
2101 {
2102     CPUX86State *env = &cpu->env;
2103     int i, ret;
2104     struct kvm_xcrs xcrs;
2105
2106     if (!has_xcrs) {
2107         return 0;
2108     }
2109
2110     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
2111     if (ret < 0) {
2112         return ret;
2113     }
2114
2115     for (i = 0; i < xcrs.nr_xcrs; i++) {
2116         /* Only support xcr0 now */
2117         if (xcrs.xcrs[i].xcr == 0) {
2118             env->xcr0 = xcrs.xcrs[i].value;
2119             break;
2120         }
2121     }
2122     return 0;
2123 }
2124
2125 static int kvm_get_sregs(X86CPU *cpu)
2126 {
2127     CPUX86State *env = &cpu->env;
2128     struct kvm_sregs sregs;
2129     int bit, i, ret;
2130
2131     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
2132     if (ret < 0) {
2133         return ret;
2134     }
2135
2136     /* There can only be one pending IRQ set in the bitmap at a time, so try
2137        to find it and save its number instead (-1 for none). */
2138     env->interrupt_injected = -1;
2139     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2140         if (sregs.interrupt_bitmap[i]) {
2141             bit = ctz64(sregs.interrupt_bitmap[i]);
2142             env->interrupt_injected = i * 64 + bit;
2143             break;
2144         }
2145     }
2146
2147     get_seg(&env->segs[R_CS], &sregs.cs);
2148     get_seg(&env->segs[R_DS], &sregs.ds);
2149     get_seg(&env->segs[R_ES], &sregs.es);
2150     get_seg(&env->segs[R_FS], &sregs.fs);
2151     get_seg(&env->segs[R_GS], &sregs.gs);
2152     get_seg(&env->segs[R_SS], &sregs.ss);
2153
2154     get_seg(&env->tr, &sregs.tr);
2155     get_seg(&env->ldt, &sregs.ldt);
2156
2157     env->idt.limit = sregs.idt.limit;
2158     env->idt.base = sregs.idt.base;
2159     env->gdt.limit = sregs.gdt.limit;
2160     env->gdt.base = sregs.gdt.base;
2161
2162     env->cr[0] = sregs.cr0;
2163     env->cr[2] = sregs.cr2;
2164     env->cr[3] = sregs.cr3;
2165     env->cr[4] = sregs.cr4;
2166
2167     env->efer = sregs.efer;
2168
2169     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2170     x86_update_hflags(env);
2171
2172     return 0;
2173 }
2174
2175 static int kvm_get_msrs(X86CPU *cpu)
2176 {
2177     CPUX86State *env = &cpu->env;
2178     struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2179     int ret, i;
2180     uint64_t mtrr_top_bits;
2181
2182     kvm_msr_buf_reset(cpu);
2183
2184     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2185     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2186     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2187     kvm_msr_entry_add(cpu, MSR_PAT, 0);
2188     if (has_msr_star) {
2189         kvm_msr_entry_add(cpu, MSR_STAR, 0);
2190     }
2191     if (has_msr_hsave_pa) {
2192         kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2193     }
2194     if (has_msr_tsc_aux) {
2195         kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2196     }
2197     if (has_msr_tsc_adjust) {
2198         kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2199     }
2200     if (has_msr_tsc_deadline) {
2201         kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2202     }
2203     if (has_msr_misc_enable) {
2204         kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2205     }
2206     if (has_msr_smbase) {
2207         kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2208     }
2209     if (has_msr_smi_count) {
2210         kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2211     }
2212     if (has_msr_feature_control) {
2213         kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2214     }
2215     if (has_msr_bndcfgs) {
2216         kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2217     }
2218     if (has_msr_xss) {
2219         kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2220     }
2221     if (has_msr_spec_ctrl) {
2222         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2223     }
2224     if (has_msr_virt_ssbd) {
2225         kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2226     }
2227     if (!env->tsc_valid) {
2228         kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2229         env->tsc_valid = !runstate_is_running();
2230     }
2231
2232 #ifdef TARGET_X86_64
2233     if (lm_capable_kernel) {
2234         kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2235         kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2236         kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2237         kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2238     }
2239 #endif
2240     kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2241     kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2242     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2243         kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2244     }
2245     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2246         kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2247     }
2248     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2249         kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2250     }
2251     if (has_architectural_pmu_version > 0) {
2252         if (has_architectural_pmu_version > 1) {
2253             kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2254             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2255             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2256             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2257         }
2258         for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2259             kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2260         }
2261         for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2262             kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2263             kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2264         }
2265     }
2266
2267     if (env->mcg_cap) {
2268         kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2269         kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2270         if (has_msr_mcg_ext_ctl) {
2271             kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2272         }
2273         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2274             kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2275         }
2276     }
2277
2278     if (has_msr_hv_hypercall) {
2279         kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2280         kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2281     }
2282     if (cpu->hyperv_vapic) {
2283         kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2284     }
2285     if (cpu->hyperv_time) {
2286         kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2287     }
2288     if (cpu->hyperv_reenlightenment) {
2289         kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2290         kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2291         kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2292     }
2293     if (has_msr_hv_crash) {
2294         int j;
2295
2296         for (j = 0; j < HV_CRASH_PARAMS; j++) {
2297             kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2298         }
2299     }
2300     if (has_msr_hv_runtime) {
2301         kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2302     }
2303     if (cpu->hyperv_synic) {
2304         uint32_t msr;
2305
2306         kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2307         kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2308         kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2309         for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2310             kvm_msr_entry_add(cpu, msr, 0);
2311         }
2312     }
2313     if (has_msr_hv_stimer) {
2314         uint32_t msr;
2315
2316         for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2317              msr++) {
2318             kvm_msr_entry_add(cpu, msr, 0);
2319         }
2320     }
2321     if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2322         kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2323         kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2324         kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2325         kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2326         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2327         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2328         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2329         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2330         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2331         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2332         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2333         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2334         for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2335             kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2336             kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2337         }
2338     }
2339
2340     if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2341         int addr_num =
2342             kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2343
2344         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2345         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2346         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2347         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2348         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2349         for (i = 0; i < addr_num; i++) {
2350             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2351         }
2352     }
2353
2354     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2355     if (ret < 0) {
2356         return ret;
2357     }
2358
2359     if (ret < cpu->kvm_msr_buf->nmsrs) {
2360         struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2361         error_report("error: failed to get MSR 0x%" PRIx32,
2362                      (uint32_t)e->index);
2363     }
2364
2365     assert(ret == cpu->kvm_msr_buf->nmsrs);
2366     /*
2367      * MTRR masks: Each mask consists of 5 parts
2368      * a  10..0: must be zero
2369      * b  11   : valid bit
2370      * c n-1.12: actual mask bits
2371      * d  51..n: reserved must be zero
2372      * e  63.52: reserved must be zero
2373      *
2374      * 'n' is the number of physical bits supported by the CPU and is
2375      * apparently always <= 52.   We know our 'n' but don't know what
2376      * the destinations 'n' is; it might be smaller, in which case
2377      * it masks (c) on loading. It might be larger, in which case
2378      * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2379      * we're migrating to.
2380      */
2381
2382     if (cpu->fill_mtrr_mask) {
2383         QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2384         assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2385         mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2386     } else {
2387         mtrr_top_bits = 0;
2388     }
2389
2390     for (i = 0; i < ret; i++) {
2391         uint32_t index = msrs[i].index;
2392         switch (index) {
2393         case MSR_IA32_SYSENTER_CS:
2394             env->sysenter_cs = msrs[i].data;
2395             break;
2396         case MSR_IA32_SYSENTER_ESP:
2397             env->sysenter_esp = msrs[i].data;
2398             break;
2399         case MSR_IA32_SYSENTER_EIP:
2400             env->sysenter_eip = msrs[i].data;
2401             break;
2402         case MSR_PAT:
2403             env->pat = msrs[i].data;
2404             break;
2405         case MSR_STAR:
2406             env->star = msrs[i].data;
2407             break;
2408 #ifdef TARGET_X86_64
2409         case MSR_CSTAR:
2410             env->cstar = msrs[i].data;
2411             break;
2412         case MSR_KERNELGSBASE:
2413             env->kernelgsbase = msrs[i].data;
2414             break;
2415         case MSR_FMASK:
2416             env->fmask = msrs[i].data;
2417             break;
2418         case MSR_LSTAR:
2419             env->lstar = msrs[i].data;
2420             break;
2421 #endif
2422         case MSR_IA32_TSC:
2423             env->tsc = msrs[i].data;
2424             break;
2425         case MSR_TSC_AUX:
2426             env->tsc_aux = msrs[i].data;
2427             break;
2428         case MSR_TSC_ADJUST:
2429             env->tsc_adjust = msrs[i].data;
2430             break;
2431         case MSR_IA32_TSCDEADLINE:
2432             env->tsc_deadline = msrs[i].data;
2433             break;
2434         case MSR_VM_HSAVE_PA:
2435             env->vm_hsave = msrs[i].data;
2436             break;
2437         case MSR_KVM_SYSTEM_TIME:
2438             env->system_time_msr = msrs[i].data;
2439             break;
2440         case MSR_KVM_WALL_CLOCK:
2441             env->wall_clock_msr = msrs[i].data;
2442             break;
2443         case MSR_MCG_STATUS:
2444             env->mcg_status = msrs[i].data;
2445             break;
2446         case MSR_MCG_CTL:
2447             env->mcg_ctl = msrs[i].data;
2448             break;
2449         case MSR_MCG_EXT_CTL:
2450             env->mcg_ext_ctl = msrs[i].data;
2451             break;
2452         case MSR_IA32_MISC_ENABLE:
2453             env->msr_ia32_misc_enable = msrs[i].data;
2454             break;
2455         case MSR_IA32_SMBASE:
2456             env->smbase = msrs[i].data;
2457             break;
2458         case MSR_SMI_COUNT:
2459             env->msr_smi_count = msrs[i].data;
2460             break;
2461         case MSR_IA32_FEATURE_CONTROL:
2462             env->msr_ia32_feature_control = msrs[i].data;
2463             break;
2464         case MSR_IA32_BNDCFGS:
2465             env->msr_bndcfgs = msrs[i].data;
2466             break;
2467         case MSR_IA32_XSS:
2468             env->xss = msrs[i].data;
2469             break;
2470         default:
2471             if (msrs[i].index >= MSR_MC0_CTL &&
2472                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2473                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2474             }
2475             break;
2476         case MSR_KVM_ASYNC_PF_EN:
2477             env->async_pf_en_msr = msrs[i].data;
2478             break;
2479         case MSR_KVM_PV_EOI_EN:
2480             env->pv_eoi_en_msr = msrs[i].data;
2481             break;
2482         case MSR_KVM_STEAL_TIME:
2483             env->steal_time_msr = msrs[i].data;
2484             break;
2485         case MSR_CORE_PERF_FIXED_CTR_CTRL:
2486             env->msr_fixed_ctr_ctrl = msrs[i].data;
2487             break;
2488         case MSR_CORE_PERF_GLOBAL_CTRL:
2489             env->msr_global_ctrl = msrs[i].data;
2490             break;
2491         case MSR_CORE_PERF_GLOBAL_STATUS:
2492             env->msr_global_status = msrs[i].data;
2493             break;
2494         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2495             env->msr_global_ovf_ctrl = msrs[i].data;
2496             break;
2497         case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2498             env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2499             break;
2500         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2501             env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2502             break;
2503         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2504             env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2505             break;
2506         case HV_X64_MSR_HYPERCALL:
2507             env->msr_hv_hypercall = msrs[i].data;
2508             break;
2509         case HV_X64_MSR_GUEST_OS_ID:
2510             env->msr_hv_guest_os_id = msrs[i].data;
2511             break;
2512         case HV_X64_MSR_APIC_ASSIST_PAGE:
2513             env->msr_hv_vapic = msrs[i].data;
2514             break;
2515         case HV_X64_MSR_REFERENCE_TSC:
2516             env->msr_hv_tsc = msrs[i].data;
2517             break;
2518         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2519             env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2520             break;
2521         case HV_X64_MSR_VP_RUNTIME:
2522             env->msr_hv_runtime = msrs[i].data;
2523             break;
2524         case HV_X64_MSR_SCONTROL:
2525             env->msr_hv_synic_control = msrs[i].data;
2526             break;
2527         case HV_X64_MSR_SIEFP:
2528             env->msr_hv_synic_evt_page = msrs[i].data;
2529             break;
2530         case HV_X64_MSR_SIMP:
2531             env->msr_hv_synic_msg_page = msrs[i].data;
2532             break;
2533         case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2534             env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2535             break;
2536         case HV_X64_MSR_STIMER0_CONFIG:
2537         case HV_X64_MSR_STIMER1_CONFIG:
2538         case HV_X64_MSR_STIMER2_CONFIG:
2539         case HV_X64_MSR_STIMER3_CONFIG:
2540             env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2541                                 msrs[i].data;
2542             break;
2543         case HV_X64_MSR_STIMER0_COUNT:
2544         case HV_X64_MSR_STIMER1_COUNT:
2545         case HV_X64_MSR_STIMER2_COUNT:
2546         case HV_X64_MSR_STIMER3_COUNT:
2547             env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2548                                 msrs[i].data;
2549             break;
2550         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2551             env->msr_hv_reenlightenment_control = msrs[i].data;
2552             break;
2553         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2554             env->msr_hv_tsc_emulation_control = msrs[i].data;
2555             break;
2556         case HV_X64_MSR_TSC_EMULATION_STATUS:
2557             env->msr_hv_tsc_emulation_status = msrs[i].data;
2558             break;
2559         case MSR_MTRRdefType:
2560             env->mtrr_deftype = msrs[i].data;
2561             break;
2562         case MSR_MTRRfix64K_00000:
2563             env->mtrr_fixed[0] = msrs[i].data;
2564             break;
2565         case MSR_MTRRfix16K_80000:
2566             env->mtrr_fixed[1] = msrs[i].data;
2567             break;
2568         case MSR_MTRRfix16K_A0000:
2569             env->mtrr_fixed[2] = msrs[i].data;
2570             break;
2571         case MSR_MTRRfix4K_C0000:
2572             env->mtrr_fixed[3] = msrs[i].data;
2573             break;
2574         case MSR_MTRRfix4K_C8000:
2575             env->mtrr_fixed[4] = msrs[i].data;
2576             break;
2577         case MSR_MTRRfix4K_D0000:
2578             env->mtrr_fixed[5] = msrs[i].data;
2579             break;
2580         case MSR_MTRRfix4K_D8000:
2581             env->mtrr_fixed[6] = msrs[i].data;
2582             break;
2583         case MSR_MTRRfix4K_E0000:
2584             env->mtrr_fixed[7] = msrs[i].data;
2585             break;
2586         case MSR_MTRRfix4K_E8000:
2587             env->mtrr_fixed[8] = msrs[i].data;
2588             break;
2589         case MSR_MTRRfix4K_F0000:
2590             env->mtrr_fixed[9] = msrs[i].data;
2591             break;
2592         case MSR_MTRRfix4K_F8000:
2593             env->mtrr_fixed[10] = msrs[i].data;
2594             break;
2595         case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2596             if (index & 1) {
2597                 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2598                                                                mtrr_top_bits;
2599             } else {
2600                 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2601             }
2602             break;
2603         case MSR_IA32_SPEC_CTRL:
2604             env->spec_ctrl = msrs[i].data;
2605             break;
2606         case MSR_VIRT_SSBD:
2607             env->virt_ssbd = msrs[i].data;
2608             break;
2609         case MSR_IA32_RTIT_CTL:
2610             env->msr_rtit_ctrl = msrs[i].data;
2611             break;
2612         case MSR_IA32_RTIT_STATUS:
2613             env->msr_rtit_status = msrs[i].data;
2614             break;
2615         case MSR_IA32_RTIT_OUTPUT_BASE:
2616             env->msr_rtit_output_base = msrs[i].data;
2617             break;
2618         case MSR_IA32_RTIT_OUTPUT_MASK:
2619             env->msr_rtit_output_mask = msrs[i].data;
2620             break;
2621         case MSR_IA32_RTIT_CR3_MATCH:
2622             env->msr_rtit_cr3_match = msrs[i].data;
2623             break;
2624         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2625             env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2626             break;
2627         }
2628     }
2629
2630     return 0;
2631 }
2632
2633 static int kvm_put_mp_state(X86CPU *cpu)
2634 {
2635     struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2636
2637     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2638 }
2639
2640 static int kvm_get_mp_state(X86CPU *cpu)
2641 {
2642     CPUState *cs = CPU(cpu);
2643     CPUX86State *env = &cpu->env;
2644     struct kvm_mp_state mp_state;
2645     int ret;
2646
2647     ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2648     if (ret < 0) {
2649         return ret;
2650     }
2651     env->mp_state = mp_state.mp_state;
2652     if (kvm_irqchip_in_kernel()) {
2653         cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2654     }
2655     return 0;
2656 }
2657
2658 static int kvm_get_apic(X86CPU *cpu)
2659 {
2660     DeviceState *apic = cpu->apic_state;
2661     struct kvm_lapic_state kapic;
2662     int ret;
2663
2664     if (apic && kvm_irqchip_in_kernel()) {
2665         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2666         if (ret < 0) {
2667             return ret;
2668         }
2669
2670         kvm_get_apic_state(apic, &kapic);
2671     }
2672     return 0;
2673 }
2674
2675 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2676 {
2677     CPUState *cs = CPU(cpu);
2678     CPUX86State *env = &cpu->env;
2679     struct kvm_vcpu_events events = {};
2680
2681     if (!kvm_has_vcpu_events()) {
2682         return 0;
2683     }
2684
2685     events.exception.injected = (env->exception_injected >= 0);
2686     events.exception.nr = env->exception_injected;
2687     events.exception.has_error_code = env->has_error_code;
2688     events.exception.error_code = env->error_code;
2689     events.exception.pad = 0;
2690
2691     events.interrupt.injected = (env->interrupt_injected >= 0);
2692     events.interrupt.nr = env->interrupt_injected;
2693     events.interrupt.soft = env->soft_interrupt;
2694
2695     events.nmi.injected = env->nmi_injected;
2696     events.nmi.pending = env->nmi_pending;
2697     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2698     events.nmi.pad = 0;
2699
2700     events.sipi_vector = env->sipi_vector;
2701     events.flags = 0;
2702
2703     if (has_msr_smbase) {
2704         events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2705         events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2706         if (kvm_irqchip_in_kernel()) {
2707             /* As soon as these are moved to the kernel, remove them
2708              * from cs->interrupt_request.
2709              */
2710             events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2711             events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2712             cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2713         } else {
2714             /* Keep these in cs->interrupt_request.  */
2715             events.smi.pending = 0;
2716             events.smi.latched_init = 0;
2717         }
2718         /* Stop SMI delivery on old machine types to avoid a reboot
2719          * on an inward migration of an old VM.
2720          */
2721         if (!cpu->kvm_no_smi_migration) {
2722             events.flags |= KVM_VCPUEVENT_VALID_SMM;
2723         }
2724     }
2725
2726     if (level >= KVM_PUT_RESET_STATE) {
2727         events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2728         if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2729             events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2730         }
2731     }
2732
2733     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2734 }
2735
2736 static int kvm_get_vcpu_events(X86CPU *cpu)
2737 {
2738     CPUX86State *env = &cpu->env;
2739     struct kvm_vcpu_events events;
2740     int ret;
2741
2742     if (!kvm_has_vcpu_events()) {
2743         return 0;
2744     }
2745
2746     memset(&events, 0, sizeof(events));
2747     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2748     if (ret < 0) {
2749        return ret;
2750     }
2751     env->exception_injected =
2752        events.exception.injected ? events.exception.nr : -1;
2753     env->has_error_code = events.exception.has_error_code;
2754     env->error_code = events.exception.error_code;
2755
2756     env->interrupt_injected =
2757         events.interrupt.injected ? events.interrupt.nr : -1;
2758     env->soft_interrupt = events.interrupt.soft;
2759
2760     env->nmi_injected = events.nmi.injected;
2761     env->nmi_pending = events.nmi.pending;
2762     if (events.nmi.masked) {
2763         env->hflags2 |= HF2_NMI_MASK;
2764     } else {
2765         env->hflags2 &= ~HF2_NMI_MASK;
2766     }
2767
2768     if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2769         if (events.smi.smm) {
2770             env->hflags |= HF_SMM_MASK;
2771         } else {
2772             env->hflags &= ~HF_SMM_MASK;
2773         }
2774         if (events.smi.pending) {
2775             cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2776         } else {
2777             cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2778         }
2779         if (events.smi.smm_inside_nmi) {
2780             env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2781         } else {
2782             env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2783         }
2784         if (events.smi.latched_init) {
2785             cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2786         } else {
2787             cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2788         }
2789     }
2790
2791     env->sipi_vector = events.sipi_vector;
2792
2793     return 0;
2794 }
2795
2796 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2797 {
2798     CPUState *cs = CPU(cpu);
2799     CPUX86State *env = &cpu->env;
2800     int ret = 0;
2801     unsigned long reinject_trap = 0;
2802
2803     if (!kvm_has_vcpu_events()) {
2804         if (env->exception_injected == 1) {
2805             reinject_trap = KVM_GUESTDBG_INJECT_DB;
2806         } else if (env->exception_injected == 3) {
2807             reinject_trap = KVM_GUESTDBG_INJECT_BP;
2808         }
2809         env->exception_injected = -1;
2810     }
2811
2812     /*
2813      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2814      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2815      * by updating the debug state once again if single-stepping is on.
2816      * Another reason to call kvm_update_guest_debug here is a pending debug
2817      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2818      * reinject them via SET_GUEST_DEBUG.
2819      */
2820     if (reinject_trap ||
2821         (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2822         ret = kvm_update_guest_debug(cs, reinject_trap);
2823     }
2824     return ret;
2825 }
2826
2827 static int kvm_put_debugregs(X86CPU *cpu)
2828 {
2829     CPUX86State *env = &cpu->env;
2830     struct kvm_debugregs dbgregs;
2831     int i;
2832
2833     if (!kvm_has_debugregs()) {
2834         return 0;
2835     }
2836
2837     for (i = 0; i < 4; i++) {
2838         dbgregs.db[i] = env->dr[i];
2839     }
2840     dbgregs.dr6 = env->dr[6];
2841     dbgregs.dr7 = env->dr[7];
2842     dbgregs.flags = 0;
2843
2844     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2845 }
2846
2847 static int kvm_get_debugregs(X86CPU *cpu)
2848 {
2849     CPUX86State *env = &cpu->env;
2850     struct kvm_debugregs dbgregs;
2851     int i, ret;
2852
2853     if (!kvm_has_debugregs()) {
2854         return 0;
2855     }
2856
2857     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2858     if (ret < 0) {
2859         return ret;
2860     }
2861     for (i = 0; i < 4; i++) {
2862         env->dr[i] = dbgregs.db[i];
2863     }
2864     env->dr[4] = env->dr[6] = dbgregs.dr6;
2865     env->dr[5] = env->dr[7] = dbgregs.dr7;
2866
2867     return 0;
2868 }
2869
2870 int kvm_arch_put_registers(CPUState *cpu, int level)
2871 {
2872     X86CPU *x86_cpu = X86_CPU(cpu);
2873     int ret;
2874
2875     assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2876
2877     if (level >= KVM_PUT_RESET_STATE) {
2878         ret = kvm_put_msr_feature_control(x86_cpu);
2879         if (ret < 0) {
2880             return ret;
2881         }
2882     }
2883
2884     if (level == KVM_PUT_FULL_STATE) {
2885         /* We don't check for kvm_arch_set_tsc_khz() errors here,
2886          * because TSC frequency mismatch shouldn't abort migration,
2887          * unless the user explicitly asked for a more strict TSC
2888          * setting (e.g. using an explicit "tsc-freq" option).
2889          */
2890         kvm_arch_set_tsc_khz(cpu);
2891     }
2892
2893     ret = kvm_getput_regs(x86_cpu, 1);
2894     if (ret < 0) {
2895         return ret;
2896     }
2897     ret = kvm_put_xsave(x86_cpu);
2898     if (ret < 0) {
2899         return ret;
2900     }
2901     ret = kvm_put_xcrs(x86_cpu);
2902     if (ret < 0) {
2903         return ret;
2904     }
2905     ret = kvm_put_sregs(x86_cpu);
2906     if (ret < 0) {
2907         return ret;
2908     }
2909     /* must be before kvm_put_msrs */
2910     ret = kvm_inject_mce_oldstyle(x86_cpu);
2911     if (ret < 0) {
2912         return ret;
2913     }
2914     ret = kvm_put_msrs(x86_cpu, level);
2915     if (ret < 0) {
2916         return ret;
2917     }
2918     ret = kvm_put_vcpu_events(x86_cpu, level);
2919     if (ret < 0) {
2920         return ret;
2921     }
2922     if (level >= KVM_PUT_RESET_STATE) {
2923         ret = kvm_put_mp_state(x86_cpu);
2924         if (ret < 0) {
2925             return ret;
2926         }
2927     }
2928
2929     ret = kvm_put_tscdeadline_msr(x86_cpu);
2930     if (ret < 0) {
2931         return ret;
2932     }
2933     ret = kvm_put_debugregs(x86_cpu);
2934     if (ret < 0) {
2935         return ret;
2936     }
2937     /* must be last */
2938     ret = kvm_guest_debug_workarounds(x86_cpu);
2939     if (ret < 0) {
2940         return ret;
2941     }
2942     return 0;
2943 }
2944
2945 int kvm_arch_get_registers(CPUState *cs)
2946 {
2947     X86CPU *cpu = X86_CPU(cs);
2948     int ret;
2949
2950     assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2951
2952     ret = kvm_get_vcpu_events(cpu);
2953     if (ret < 0) {
2954         goto out;
2955     }
2956     /*
2957      * KVM_GET_MPSTATE can modify CS and RIP, call it before
2958      * KVM_GET_REGS and KVM_GET_SREGS.
2959      */
2960     ret = kvm_get_mp_state(cpu);
2961     if (ret < 0) {
2962         goto out;
2963     }
2964     ret = kvm_getput_regs(cpu, 0);
2965     if (ret < 0) {
2966         goto out;
2967     }
2968     ret = kvm_get_xsave(cpu);
2969     if (ret < 0) {
2970         goto out;
2971     }
2972     ret = kvm_get_xcrs(cpu);
2973     if (ret < 0) {
2974         goto out;
2975     }
2976     ret = kvm_get_sregs(cpu);
2977     if (ret < 0) {
2978         goto out;
2979     }
2980     ret = kvm_get_msrs(cpu);
2981     if (ret < 0) {
2982         goto out;
2983     }
2984     ret = kvm_get_apic(cpu);
2985     if (ret < 0) {
2986         goto out;
2987     }
2988     ret = kvm_get_debugregs(cpu);
2989     if (ret < 0) {
2990         goto out;
2991     }
2992     ret = 0;
2993  out:
2994     cpu_sync_bndcs_hflags(&cpu->env);
2995     return ret;
2996 }
2997
2998 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2999 {
3000     X86CPU *x86_cpu = X86_CPU(cpu);
3001     CPUX86State *env = &x86_cpu->env;
3002     int ret;
3003
3004     /* Inject NMI */
3005     if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3006         if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3007             qemu_mutex_lock_iothread();
3008             cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3009             qemu_mutex_unlock_iothread();
3010             DPRINTF("injected NMI\n");
3011             ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3012             if (ret < 0) {
3013                 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3014                         strerror(-ret));
3015             }
3016         }
3017         if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3018             qemu_mutex_lock_iothread();
3019             cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3020             qemu_mutex_unlock_iothread();
3021             DPRINTF("injected SMI\n");
3022             ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3023             if (ret < 0) {
3024                 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3025                         strerror(-ret));
3026             }
3027         }
3028     }
3029
3030     if (!kvm_pic_in_kernel()) {
3031         qemu_mutex_lock_iothread();
3032     }
3033
3034     /* Force the VCPU out of its inner loop to process any INIT requests
3035      * or (for userspace APIC, but it is cheap to combine the checks here)
3036      * pending TPR access reports.
3037      */
3038     if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
3039         if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3040             !(env->hflags & HF_SMM_MASK)) {
3041             cpu->exit_request = 1;
3042         }
3043         if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3044             cpu->exit_request = 1;
3045         }
3046     }
3047
3048     if (!kvm_pic_in_kernel()) {
3049         /* Try to inject an interrupt if the guest can accept it */
3050         if (run->ready_for_interrupt_injection &&
3051             (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
3052             (env->eflags & IF_MASK)) {
3053             int irq;
3054
3055             cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
3056             irq = cpu_get_pic_interrupt(env);
3057             if (irq >= 0) {
3058                 struct kvm_interrupt intr;
3059
3060                 intr.irq = irq;
3061                 DPRINTF("injected interrupt %d\n", irq);
3062                 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
3063                 if (ret < 0) {
3064                     fprintf(stderr,
3065                             "KVM: injection failed, interrupt lost (%s)\n",
3066                             strerror(-ret));
3067                 }
3068             }
3069         }
3070
3071         /* If we have an interrupt but the guest is not ready to receive an
3072          * interrupt, request an interrupt window exit.  This will
3073          * cause a return to userspace as soon as the guest is ready to
3074          * receive interrupts. */
3075         if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
3076             run->request_interrupt_window = 1;
3077         } else {
3078             run->request_interrupt_window = 0;
3079         }
3080
3081         DPRINTF("setting tpr\n");
3082         run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
3083
3084         qemu_mutex_unlock_iothread();
3085     }
3086 }
3087
3088 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
3089 {
3090     X86CPU *x86_cpu = X86_CPU(cpu);
3091     CPUX86State *env = &x86_cpu->env;
3092
3093     if (run->flags & KVM_RUN_X86_SMM) {
3094         env->hflags |= HF_SMM_MASK;
3095     } else {
3096         env->hflags &= ~HF_SMM_MASK;
3097     }
3098     if (run->if_flag) {
3099         env->eflags |= IF_MASK;
3100     } else {
3101         env->eflags &= ~IF_MASK;
3102     }
3103
3104     /* We need to protect the apic state against concurrent accesses from
3105      * different threads in case the userspace irqchip is used. */
3106     if (!kvm_irqchip_in_kernel()) {
3107         qemu_mutex_lock_iothread();
3108     }
3109     cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3110     cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
3111     if (!kvm_irqchip_in_kernel()) {
3112         qemu_mutex_unlock_iothread();
3113     }
3114     return cpu_get_mem_attrs(env);
3115 }
3116
3117 int kvm_arch_process_async_events(CPUState *cs)
3118 {
3119     X86CPU *cpu = X86_CPU(cs);
3120     CPUX86State *env = &cpu->env;
3121
3122     if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
3123         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3124         assert(env->mcg_cap);
3125
3126         cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
3127
3128         kvm_cpu_synchronize_state(cs);
3129
3130         if (env->exception_injected == EXCP08_DBLE) {
3131             /* this means triple fault */
3132             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
3133             cs->exit_request = 1;
3134             return 0;
3135         }
3136         env->exception_injected = EXCP12_MCHK;
3137         env->has_error_code = 0;
3138
3139         cs->halted = 0;
3140         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3141             env->mp_state = KVM_MP_STATE_RUNNABLE;
3142         }
3143     }
3144
3145     if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3146         !(env->hflags & HF_SMM_MASK)) {
3147         kvm_cpu_synchronize_state(cs);
3148         do_cpu_init(cpu);
3149     }
3150
3151     if (kvm_irqchip_in_kernel()) {
3152         return 0;
3153     }
3154
3155     if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3156         cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
3157         apic_poll_irq(cpu->apic_state);
3158     }
3159     if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3160          (env->eflags & IF_MASK)) ||
3161         (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3162         cs->halted = 0;
3163     }
3164     if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
3165         kvm_cpu_synchronize_state(cs);
3166         do_cpu_sipi(cpu);
3167     }
3168     if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3169         cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
3170         kvm_cpu_synchronize_state(cs);
3171         apic_handle_tpr_access_report(cpu->apic_state, env->eip,
3172                                       env->tpr_access_type);
3173     }
3174
3175     return cs->halted;
3176 }
3177
3178 static int kvm_handle_halt(X86CPU *cpu)
3179 {
3180     CPUState *cs = CPU(cpu);
3181     CPUX86State *env = &cpu->env;
3182
3183     if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3184           (env->eflags & IF_MASK)) &&
3185         !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3186         cs->halted = 1;
3187         return EXCP_HLT;
3188     }
3189
3190     return 0;
3191 }
3192
3193 static int kvm_handle_tpr_access(X86CPU *cpu)
3194 {
3195     CPUState *cs = CPU(cpu);
3196     struct kvm_run *run = cs->kvm_run;
3197
3198     apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3199                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
3200                                                            : TPR_ACCESS_READ);
3201     return 1;
3202 }
3203
3204 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3205 {
3206     static const uint8_t int3 = 0xcc;
3207
3208     if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3209         cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3210         return -EINVAL;
3211     }
3212     return 0;
3213 }
3214
3215 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3216 {
3217     uint8_t int3;
3218
3219     if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3220         cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3221         return -EINVAL;
3222     }
3223     return 0;
3224 }
3225
3226 static struct {
3227     target_ulong addr;
3228     int len;
3229     int type;
3230 } hw_breakpoint[4];
3231
3232 static int nb_hw_breakpoint;
3233
3234 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3235 {
3236     int n;
3237
3238     for (n = 0; n < nb_hw_breakpoint; n++) {
3239         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3240             (hw_breakpoint[n].len == len || len == -1)) {
3241             return n;
3242         }
3243     }
3244     return -1;
3245 }
3246
3247 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3248                                   target_ulong len, int type)
3249 {
3250     switch (type) {
3251     case GDB_BREAKPOINT_HW:
3252         len = 1;
3253         break;
3254     case GDB_WATCHPOINT_WRITE:
3255     case GDB_WATCHPOINT_ACCESS:
3256         switch (len) {
3257         case 1:
3258             break;
3259         case 2:
3260         case 4:
3261         case 8:
3262             if (addr & (len - 1)) {
3263                 return -EINVAL;
3264             }
3265             break;
3266         default:
3267             return -EINVAL;
3268         }
3269         break;
3270     default:
3271         return -ENOSYS;
3272     }
3273
3274     if (nb_hw_breakpoint == 4) {
3275         return -ENOBUFS;
3276     }
3277     if (find_hw_breakpoint(addr, len, type) >= 0) {
3278         return -EEXIST;
3279     }
3280     hw_breakpoint[nb_hw_breakpoint].addr = addr;
3281     hw_breakpoint[nb_hw_breakpoint].len = len;
3282     hw_breakpoint[nb_hw_breakpoint].type = type;
3283     nb_hw_breakpoint++;
3284
3285     return 0;
3286 }
3287
3288 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3289                                   target_ulong len, int type)
3290 {
3291     int n;
3292
3293     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3294     if (n < 0) {
3295         return -ENOENT;
3296     }
3297     nb_hw_breakpoint--;
3298     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3299
3300     return 0;
3301 }
3302
3303 void kvm_arch_remove_all_hw_breakpoints(void)
3304 {
3305     nb_hw_breakpoint = 0;
3306 }
3307
3308 static CPUWatchpoint hw_watchpoint;
3309
3310 static int kvm_handle_debug(X86CPU *cpu,
3311                             struct kvm_debug_exit_arch *arch_info)
3312 {
3313     CPUState *cs = CPU(cpu);
3314     CPUX86State *env = &cpu->env;
3315     int ret = 0;
3316     int n;
3317
3318     if (arch_info->exception == 1) {
3319         if (arch_info->dr6 & (1 << 14)) {
3320             if (cs->singlestep_enabled) {
3321                 ret = EXCP_DEBUG;
3322             }
3323         } else {
3324             for (n = 0; n < 4; n++) {
3325                 if (arch_info->dr6 & (1 << n)) {
3326                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3327                     case 0x0:
3328                         ret = EXCP_DEBUG;
3329                         break;
3330                     case 0x1:
3331                         ret = EXCP_DEBUG;
3332                         cs->watchpoint_hit = &hw_watchpoint;
3333                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3334                         hw_watchpoint.flags = BP_MEM_WRITE;
3335                         break;
3336                     case 0x3:
3337                         ret = EXCP_DEBUG;
3338                         cs->watchpoint_hit = &hw_watchpoint;
3339                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3340                         hw_watchpoint.flags = BP_MEM_ACCESS;
3341                         break;
3342                     }
3343                 }
3344             }
3345         }
3346     } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3347         ret = EXCP_DEBUG;
3348     }
3349     if (ret == 0) {
3350         cpu_synchronize_state(cs);
3351         assert(env->exception_injected == -1);
3352
3353         /* pass to guest */
3354         env->exception_injected = arch_info->exception;
3355         env->has_error_code = 0;
3356     }
3357
3358     return ret;
3359 }
3360
3361 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3362 {
3363     const uint8_t type_code[] = {
3364         [GDB_BREAKPOINT_HW] = 0x0,
3365         [GDB_WATCHPOINT_WRITE] = 0x1,
3366         [GDB_WATCHPOINT_ACCESS] = 0x3
3367     };
3368     const uint8_t len_code[] = {
3369         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3370     };
3371     int n;
3372
3373     if (kvm_sw_breakpoints_active(cpu)) {
3374         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3375     }
3376     if (nb_hw_breakpoint > 0) {
3377         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3378         dbg->arch.debugreg[7] = 0x0600;
3379         for (n = 0; n < nb_hw_breakpoint; n++) {
3380             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3381             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3382                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3383                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3384         }
3385     }
3386 }
3387
3388 static bool host_supports_vmx(void)
3389 {
3390     uint32_t ecx, unused;
3391
3392     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3393     return ecx & CPUID_EXT_VMX;
3394 }
3395
3396 #define VMX_INVALID_GUEST_STATE 0x80000021
3397
3398 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3399 {
3400     X86CPU *cpu = X86_CPU(cs);
3401     uint64_t code;
3402     int ret;
3403
3404     switch (run->exit_reason) {
3405     case KVM_EXIT_HLT:
3406         DPRINTF("handle_hlt\n");
3407         qemu_mutex_lock_iothread();
3408         ret = kvm_handle_halt(cpu);
3409         qemu_mutex_unlock_iothread();
3410         break;
3411     case KVM_EXIT_SET_TPR:
3412         ret = 0;
3413         break;
3414     case KVM_EXIT_TPR_ACCESS:
3415         qemu_mutex_lock_iothread();
3416         ret = kvm_handle_tpr_access(cpu);
3417         qemu_mutex_unlock_iothread();
3418         break;
3419     case KVM_EXIT_FAIL_ENTRY:
3420         code = run->fail_entry.hardware_entry_failure_reason;
3421         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3422                 code);
3423         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3424             fprintf(stderr,
3425                     "\nIf you're running a guest on an Intel machine without "
3426                         "unrestricted mode\n"
3427                     "support, the failure can be most likely due to the guest "
3428                         "entering an invalid\n"
3429                     "state for Intel VT. For example, the guest maybe running "
3430                         "in big real mode\n"
3431                     "which is not supported on less recent Intel processors."
3432                         "\n\n");
3433         }
3434         ret = -1;
3435         break;
3436     case KVM_EXIT_EXCEPTION:
3437         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3438                 run->ex.exception, run->ex.error_code);
3439         ret = -1;
3440         break;
3441     case KVM_EXIT_DEBUG:
3442         DPRINTF("kvm_exit_debug\n");
3443         qemu_mutex_lock_iothread();
3444         ret = kvm_handle_debug(cpu, &run->debug.arch);
3445         qemu_mutex_unlock_iothread();
3446         break;
3447     case KVM_EXIT_HYPERV:
3448         ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3449         break;
3450     case KVM_EXIT_IOAPIC_EOI:
3451         ioapic_eoi_broadcast(run->eoi.vector);
3452         ret = 0;
3453         break;
3454     default:
3455         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3456         ret = -1;
3457         break;
3458     }
3459
3460     return ret;
3461 }
3462
3463 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3464 {
3465     X86CPU *cpu = X86_CPU(cs);
3466     CPUX86State *env = &cpu->env;
3467
3468     kvm_cpu_synchronize_state(cs);
3469     return !(env->cr[0] & CR0_PE_MASK) ||
3470            ((env->segs[R_CS].selector  & 3) != 3);
3471 }
3472
3473 void kvm_arch_init_irq_routing(KVMState *s)
3474 {
3475     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3476         /* If kernel can't do irq routing, interrupt source
3477          * override 0->2 cannot be set up as required by HPET.
3478          * So we have to disable it.
3479          */
3480         no_hpet = 1;
3481     }
3482     /* We know at this point that we're using the in-kernel
3483      * irqchip, so we can use irqfds, and on x86 we know
3484      * we can use msi via irqfd and GSI routing.
3485      */
3486     kvm_msi_via_irqfd_allowed = true;
3487     kvm_gsi_routing_allowed = true;
3488
3489     if (kvm_irqchip_is_split()) {
3490         int i;
3491
3492         /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3493            MSI routes for signaling interrupts to the local apics. */
3494         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3495             if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3496                 error_report("Could not enable split IRQ mode.");
3497                 exit(1);
3498             }
3499         }
3500     }
3501 }
3502
3503 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3504 {
3505     int ret;
3506     if (machine_kernel_irqchip_split(ms)) {
3507         ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3508         if (ret) {
3509             error_report("Could not enable split irqchip mode: %s",
3510                          strerror(-ret));
3511             exit(1);
3512         } else {
3513             DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3514             kvm_split_irqchip = true;
3515             return 1;
3516         }
3517     } else {
3518         return 0;
3519     }
3520 }
3521
3522 /* Classic KVM device assignment interface. Will remain x86 only. */
3523 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3524                           uint32_t flags, uint32_t *dev_id)
3525 {
3526     struct kvm_assigned_pci_dev dev_data = {
3527         .segnr = dev_addr->domain,
3528         .busnr = dev_addr->bus,
3529         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3530         .flags = flags,
3531     };
3532     int ret;
3533
3534     dev_data.assigned_dev_id =
3535         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3536
3537     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3538     if (ret < 0) {
3539         return ret;
3540     }
3541
3542     *dev_id = dev_data.assigned_dev_id;
3543
3544     return 0;
3545 }
3546
3547 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3548 {
3549     struct kvm_assigned_pci_dev dev_data = {
3550         .assigned_dev_id = dev_id,
3551     };
3552
3553     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3554 }
3555
3556 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3557                                    uint32_t irq_type, uint32_t guest_irq)
3558 {
3559     struct kvm_assigned_irq assigned_irq = {
3560         .assigned_dev_id = dev_id,
3561         .guest_irq = guest_irq,
3562         .flags = irq_type,
3563     };
3564
3565     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3566         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3567     } else {
3568         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3569     }
3570 }
3571
3572 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3573                            uint32_t guest_irq)
3574 {
3575     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3576         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3577
3578     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3579 }
3580
3581 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3582 {
3583     struct kvm_assigned_pci_dev dev_data = {
3584         .assigned_dev_id = dev_id,
3585         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3586     };
3587
3588     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3589 }
3590
3591 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3592                                      uint32_t type)
3593 {
3594     struct kvm_assigned_irq assigned_irq = {
3595         .assigned_dev_id = dev_id,
3596         .flags = type,
3597     };
3598
3599     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3600 }
3601
3602 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3603 {
3604     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3605         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3606 }
3607
3608 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3609 {
3610     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3611                                               KVM_DEV_IRQ_GUEST_MSI, virq);
3612 }
3613
3614 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3615 {
3616     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3617                                                 KVM_DEV_IRQ_HOST_MSI);
3618 }
3619
3620 bool kvm_device_msix_supported(KVMState *s)
3621 {
3622     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3623      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3624     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3625 }
3626
3627 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3628                                  uint32_t nr_vectors)
3629 {
3630     struct kvm_assigned_msix_nr msix_nr = {
3631         .assigned_dev_id = dev_id,
3632         .entry_nr = nr_vectors,
3633     };
3634
3635     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3636 }
3637
3638 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3639                                int virq)
3640 {
3641     struct kvm_assigned_msix_entry msix_entry = {
3642         .assigned_dev_id = dev_id,
3643         .gsi = virq,
3644         .entry = vector,
3645     };
3646
3647     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3648 }
3649
3650 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3651 {
3652     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3653                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
3654 }
3655
3656 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3657 {
3658     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3659                                                 KVM_DEV_IRQ_HOST_MSIX);
3660 }
3661
3662 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3663                              uint64_t address, uint32_t data, PCIDevice *dev)
3664 {
3665     X86IOMMUState *iommu = x86_iommu_get_default();
3666
3667     if (iommu) {
3668         int ret;
3669         MSIMessage src, dst;
3670         X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3671
3672         if (!class->int_remap) {
3673             return 0;
3674         }
3675
3676         src.address = route->u.msi.address_hi;
3677         src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3678         src.address |= route->u.msi.address_lo;
3679         src.data = route->u.msi.data;
3680
3681         ret = class->int_remap(iommu, &src, &dst, dev ? \
3682                                pci_requester_id(dev) : \
3683                                X86_IOMMU_SID_INVALID);
3684         if (ret) {
3685             trace_kvm_x86_fixup_msi_error(route->gsi);
3686             return 1;
3687         }
3688
3689         route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3690         route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3691         route->u.msi.data = dst.data;
3692     }
3693
3694     return 0;
3695 }
3696
3697 typedef struct MSIRouteEntry MSIRouteEntry;
3698
3699 struct MSIRouteEntry {
3700     PCIDevice *dev;             /* Device pointer */
3701     int vector;                 /* MSI/MSIX vector index */
3702     int virq;                   /* Virtual IRQ index */
3703     QLIST_ENTRY(MSIRouteEntry) list;
3704 };
3705
3706 /* List of used GSI routes */
3707 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3708     QLIST_HEAD_INITIALIZER(msi_route_list);
3709
3710 static void kvm_update_msi_routes_all(void *private, bool global,
3711                                       uint32_t index, uint32_t mask)
3712 {
3713     int cnt = 0;
3714     MSIRouteEntry *entry;
3715     MSIMessage msg;
3716     PCIDevice *dev;
3717
3718     /* TODO: explicit route update */
3719     QLIST_FOREACH(entry, &msi_route_list, list) {
3720         cnt++;
3721         dev = entry->dev;
3722         if (!msix_enabled(dev) && !msi_enabled(dev)) {
3723             continue;
3724         }
3725         msg = pci_get_msi_message(dev, entry->vector);
3726         kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3727     }
3728     kvm_irqchip_commit_routes(kvm_state);
3729     trace_kvm_x86_update_msi_routes(cnt);
3730 }
3731
3732 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3733                                 int vector, PCIDevice *dev)
3734 {
3735     static bool notify_list_inited = false;
3736     MSIRouteEntry *entry;
3737
3738     if (!dev) {
3739         /* These are (possibly) IOAPIC routes only used for split
3740          * kernel irqchip mode, while what we are housekeeping are
3741          * PCI devices only. */
3742         return 0;
3743     }
3744
3745     entry = g_new0(MSIRouteEntry, 1);
3746     entry->dev = dev;
3747     entry->vector = vector;
3748     entry->virq = route->gsi;
3749     QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3750
3751     trace_kvm_x86_add_msi_route(route->gsi);
3752
3753     if (!notify_list_inited) {
3754         /* For the first time we do add route, add ourselves into
3755          * IOMMU's IEC notify list if needed. */
3756         X86IOMMUState *iommu = x86_iommu_get_default();
3757         if (iommu) {
3758             x86_iommu_iec_register_notifier(iommu,
3759                                             kvm_update_msi_routes_all,
3760                                             NULL);
3761         }
3762         notify_list_inited = true;
3763     }
3764     return 0;
3765 }
3766
3767 int kvm_arch_release_virq_post(int virq)
3768 {
3769     MSIRouteEntry *entry, *next;
3770     QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3771         if (entry->virq == virq) {
3772             trace_kvm_x86_remove_msi_route(virq);
3773             QLIST_REMOVE(entry, list);
3774             g_free(entry);
3775             break;
3776         }
3777     }
3778     return 0;
3779 }
3780
3781 int kvm_arch_msi_data_to_gsi(uint32_t data)
3782 {
3783     abort();
3784 }