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[mirror_qemu.git] / target / i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include "standard-headers/asm-x86/kvm_para.h"
22
23 #include "cpu.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/hw_accel.h"
26 #include "sysemu/kvm_int.h"
27 #include "kvm_i386.h"
28 #include "hyperv.h"
29 #include "hyperv-proto.h"
30
31 #include "exec/gdbstub.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/config-file.h"
34 #include "qemu/error-report.h"
35 #include "hw/i386/pc.h"
36 #include "hw/i386/apic.h"
37 #include "hw/i386/apic_internal.h"
38 #include "hw/i386/apic-msidef.h"
39 #include "hw/i386/intel_iommu.h"
40 #include "hw/i386/x86-iommu.h"
41
42 #include "hw/pci/pci.h"
43 #include "hw/pci/msi.h"
44 #include "hw/pci/msix.h"
45 #include "migration/blocker.h"
46 #include "exec/memattrs.h"
47 #include "trace.h"
48
49 //#define DEBUG_KVM
50
51 #ifdef DEBUG_KVM
52 #define DPRINTF(fmt, ...) \
53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54 #else
55 #define DPRINTF(fmt, ...) \
56 do { } while (0)
57 #endif
58
59 #define MSR_KVM_WALL_CLOCK 0x11
60 #define MSR_KVM_SYSTEM_TIME 0x12
61
62 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64 #define MSR_BUF_SIZE 4096
65
66 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
67 KVM_CAP_INFO(SET_TSS_ADDR),
68 KVM_CAP_INFO(EXT_CPUID),
69 KVM_CAP_INFO(MP_STATE),
70 KVM_CAP_LAST_INFO
71 };
72
73 static bool has_msr_star;
74 static bool has_msr_hsave_pa;
75 static bool has_msr_tsc_aux;
76 static bool has_msr_tsc_adjust;
77 static bool has_msr_tsc_deadline;
78 static bool has_msr_feature_control;
79 static bool has_msr_misc_enable;
80 static bool has_msr_smbase;
81 static bool has_msr_bndcfgs;
82 static int lm_capable_kernel;
83 static bool has_msr_hv_hypercall;
84 static bool has_msr_hv_crash;
85 static bool has_msr_hv_reset;
86 static bool has_msr_hv_vpindex;
87 static bool hv_vpindex_settable;
88 static bool has_msr_hv_runtime;
89 static bool has_msr_hv_synic;
90 static bool has_msr_hv_stimer;
91 static bool has_msr_hv_frequencies;
92 static bool has_msr_hv_reenlightenment;
93 static bool has_msr_xss;
94 static bool has_msr_spec_ctrl;
95 static bool has_msr_virt_ssbd;
96 static bool has_msr_smi_count;
97 static bool has_msr_arch_capabs;
98 static bool has_msr_core_capabs;
99
100 static uint32_t has_architectural_pmu_version;
101 static uint32_t num_architectural_pmu_gp_counters;
102 static uint32_t num_architectural_pmu_fixed_counters;
103
104 static int has_xsave;
105 static int has_xcrs;
106 static int has_pit_state2;
107 static int has_exception_payload;
108
109 static bool has_msr_mcg_ext_ctl;
110
111 static struct kvm_cpuid2 *cpuid_cache;
112 static struct kvm_msr_list *kvm_feature_msrs;
113
114 int kvm_has_pit_state2(void)
115 {
116 return has_pit_state2;
117 }
118
119 bool kvm_has_smm(void)
120 {
121 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
122 }
123
124 bool kvm_has_adjust_clock_stable(void)
125 {
126 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
127
128 return (ret == KVM_CLOCK_TSC_STABLE);
129 }
130
131 bool kvm_allows_irq0_override(void)
132 {
133 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
134 }
135
136 static bool kvm_x2apic_api_set_flags(uint64_t flags)
137 {
138 KVMState *s = KVM_STATE(current_machine->accelerator);
139
140 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
141 }
142
143 #define MEMORIZE(fn, _result) \
144 ({ \
145 static bool _memorized; \
146 \
147 if (_memorized) { \
148 return _result; \
149 } \
150 _memorized = true; \
151 _result = fn; \
152 })
153
154 static bool has_x2apic_api;
155
156 bool kvm_has_x2apic_api(void)
157 {
158 return has_x2apic_api;
159 }
160
161 bool kvm_enable_x2apic(void)
162 {
163 return MEMORIZE(
164 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
165 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
166 has_x2apic_api);
167 }
168
169 bool kvm_hv_vpindex_settable(void)
170 {
171 return hv_vpindex_settable;
172 }
173
174 static int kvm_get_tsc(CPUState *cs)
175 {
176 X86CPU *cpu = X86_CPU(cs);
177 CPUX86State *env = &cpu->env;
178 struct {
179 struct kvm_msrs info;
180 struct kvm_msr_entry entries[1];
181 } msr_data;
182 int ret;
183
184 if (env->tsc_valid) {
185 return 0;
186 }
187
188 msr_data.info.nmsrs = 1;
189 msr_data.entries[0].index = MSR_IA32_TSC;
190 env->tsc_valid = !runstate_is_running();
191
192 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
193 if (ret < 0) {
194 return ret;
195 }
196
197 assert(ret == 1);
198 env->tsc = msr_data.entries[0].data;
199 return 0;
200 }
201
202 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
203 {
204 kvm_get_tsc(cpu);
205 }
206
207 void kvm_synchronize_all_tsc(void)
208 {
209 CPUState *cpu;
210
211 if (kvm_enabled()) {
212 CPU_FOREACH(cpu) {
213 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
214 }
215 }
216 }
217
218 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
219 {
220 struct kvm_cpuid2 *cpuid;
221 int r, size;
222
223 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
224 cpuid = g_malloc0(size);
225 cpuid->nent = max;
226 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
227 if (r == 0 && cpuid->nent >= max) {
228 r = -E2BIG;
229 }
230 if (r < 0) {
231 if (r == -E2BIG) {
232 g_free(cpuid);
233 return NULL;
234 } else {
235 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
236 strerror(-r));
237 exit(1);
238 }
239 }
240 return cpuid;
241 }
242
243 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
244 * for all entries.
245 */
246 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
247 {
248 struct kvm_cpuid2 *cpuid;
249 int max = 1;
250
251 if (cpuid_cache != NULL) {
252 return cpuid_cache;
253 }
254 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
255 max *= 2;
256 }
257 cpuid_cache = cpuid;
258 return cpuid;
259 }
260
261 static const struct kvm_para_features {
262 int cap;
263 int feature;
264 } para_features[] = {
265 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
266 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
267 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
268 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
269 };
270
271 static int get_para_features(KVMState *s)
272 {
273 int i, features = 0;
274
275 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
276 if (kvm_check_extension(s, para_features[i].cap)) {
277 features |= (1 << para_features[i].feature);
278 }
279 }
280
281 return features;
282 }
283
284 static bool host_tsx_blacklisted(void)
285 {
286 int family, model, stepping;\
287 char vendor[CPUID_VENDOR_SZ + 1];
288
289 host_vendor_fms(vendor, &family, &model, &stepping);
290
291 /* Check if we are running on a Haswell host known to have broken TSX */
292 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
293 (family == 6) &&
294 ((model == 63 && stepping < 4) ||
295 model == 60 || model == 69 || model == 70);
296 }
297
298 /* Returns the value for a specific register on the cpuid entry
299 */
300 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
301 {
302 uint32_t ret = 0;
303 switch (reg) {
304 case R_EAX:
305 ret = entry->eax;
306 break;
307 case R_EBX:
308 ret = entry->ebx;
309 break;
310 case R_ECX:
311 ret = entry->ecx;
312 break;
313 case R_EDX:
314 ret = entry->edx;
315 break;
316 }
317 return ret;
318 }
319
320 /* Find matching entry for function/index on kvm_cpuid2 struct
321 */
322 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
323 uint32_t function,
324 uint32_t index)
325 {
326 int i;
327 for (i = 0; i < cpuid->nent; ++i) {
328 if (cpuid->entries[i].function == function &&
329 cpuid->entries[i].index == index) {
330 return &cpuid->entries[i];
331 }
332 }
333 /* not found: */
334 return NULL;
335 }
336
337 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
338 uint32_t index, int reg)
339 {
340 struct kvm_cpuid2 *cpuid;
341 uint32_t ret = 0;
342 uint32_t cpuid_1_edx;
343 bool found = false;
344
345 cpuid = get_supported_cpuid(s);
346
347 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
348 if (entry) {
349 found = true;
350 ret = cpuid_entry_get_reg(entry, reg);
351 }
352
353 /* Fixups for the data returned by KVM, below */
354
355 if (function == 1 && reg == R_EDX) {
356 /* KVM before 2.6.30 misreports the following features */
357 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
358 } else if (function == 1 && reg == R_ECX) {
359 /* We can set the hypervisor flag, even if KVM does not return it on
360 * GET_SUPPORTED_CPUID
361 */
362 ret |= CPUID_EXT_HYPERVISOR;
363 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
364 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
365 * and the irqchip is in the kernel.
366 */
367 if (kvm_irqchip_in_kernel() &&
368 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
369 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
370 }
371
372 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
373 * without the in-kernel irqchip
374 */
375 if (!kvm_irqchip_in_kernel()) {
376 ret &= ~CPUID_EXT_X2APIC;
377 }
378
379 if (enable_cpu_pm) {
380 int disable_exits = kvm_check_extension(s,
381 KVM_CAP_X86_DISABLE_EXITS);
382
383 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
384 ret |= CPUID_EXT_MONITOR;
385 }
386 }
387 } else if (function == 6 && reg == R_EAX) {
388 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
389 } else if (function == 7 && index == 0 && reg == R_EBX) {
390 if (host_tsx_blacklisted()) {
391 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
392 }
393 } else if (function == 7 && index == 0 && reg == R_EDX) {
394 /*
395 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
396 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
397 * returned by KVM_GET_MSR_INDEX_LIST.
398 */
399 if (!has_msr_arch_capabs) {
400 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
401 }
402 } else if (function == 0x80000001 && reg == R_ECX) {
403 /*
404 * It's safe to enable TOPOEXT even if it's not returned by
405 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
406 * us to keep CPU models including TOPOEXT runnable on older kernels.
407 */
408 ret |= CPUID_EXT3_TOPOEXT;
409 } else if (function == 0x80000001 && reg == R_EDX) {
410 /* On Intel, kvm returns cpuid according to the Intel spec,
411 * so add missing bits according to the AMD spec:
412 */
413 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
414 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
415 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
416 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
417 * be enabled without the in-kernel irqchip
418 */
419 if (!kvm_irqchip_in_kernel()) {
420 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
421 }
422 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
423 ret |= 1U << KVM_HINTS_REALTIME;
424 found = 1;
425 }
426
427 /* fallback for older kernels */
428 if ((function == KVM_CPUID_FEATURES) && !found) {
429 ret = get_para_features(s);
430 }
431
432 return ret;
433 }
434
435 uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
436 {
437 struct {
438 struct kvm_msrs info;
439 struct kvm_msr_entry entries[1];
440 } msr_data;
441 uint32_t ret;
442
443 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
444 return 0;
445 }
446
447 /* Check if requested MSR is supported feature MSR */
448 int i;
449 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
450 if (kvm_feature_msrs->indices[i] == index) {
451 break;
452 }
453 if (i == kvm_feature_msrs->nmsrs) {
454 return 0; /* if the feature MSR is not supported, simply return 0 */
455 }
456
457 msr_data.info.nmsrs = 1;
458 msr_data.entries[0].index = index;
459
460 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
461 if (ret != 1) {
462 error_report("KVM get MSR (index=0x%x) feature failed, %s",
463 index, strerror(-ret));
464 exit(1);
465 }
466
467 return msr_data.entries[0].data;
468 }
469
470
471 typedef struct HWPoisonPage {
472 ram_addr_t ram_addr;
473 QLIST_ENTRY(HWPoisonPage) list;
474 } HWPoisonPage;
475
476 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
477 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
478
479 static void kvm_unpoison_all(void *param)
480 {
481 HWPoisonPage *page, *next_page;
482
483 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
484 QLIST_REMOVE(page, list);
485 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
486 g_free(page);
487 }
488 }
489
490 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
491 {
492 HWPoisonPage *page;
493
494 QLIST_FOREACH(page, &hwpoison_page_list, list) {
495 if (page->ram_addr == ram_addr) {
496 return;
497 }
498 }
499 page = g_new(HWPoisonPage, 1);
500 page->ram_addr = ram_addr;
501 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
502 }
503
504 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
505 int *max_banks)
506 {
507 int r;
508
509 r = kvm_check_extension(s, KVM_CAP_MCE);
510 if (r > 0) {
511 *max_banks = r;
512 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
513 }
514 return -ENOSYS;
515 }
516
517 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
518 {
519 CPUState *cs = CPU(cpu);
520 CPUX86State *env = &cpu->env;
521 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
522 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
523 uint64_t mcg_status = MCG_STATUS_MCIP;
524 int flags = 0;
525
526 if (code == BUS_MCEERR_AR) {
527 status |= MCI_STATUS_AR | 0x134;
528 mcg_status |= MCG_STATUS_EIPV;
529 } else {
530 status |= 0xc0;
531 mcg_status |= MCG_STATUS_RIPV;
532 }
533
534 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
535 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
536 * guest kernel back into env->mcg_ext_ctl.
537 */
538 cpu_synchronize_state(cs);
539 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
540 mcg_status |= MCG_STATUS_LMCE;
541 flags = 0;
542 }
543
544 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
545 (MCM_ADDR_PHYS << 6) | 0xc, flags);
546 }
547
548 static void hardware_memory_error(void)
549 {
550 fprintf(stderr, "Hardware memory error!\n");
551 exit(1);
552 }
553
554 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
555 {
556 X86CPU *cpu = X86_CPU(c);
557 CPUX86State *env = &cpu->env;
558 ram_addr_t ram_addr;
559 hwaddr paddr;
560
561 /* If we get an action required MCE, it has been injected by KVM
562 * while the VM was running. An action optional MCE instead should
563 * be coming from the main thread, which qemu_init_sigbus identifies
564 * as the "early kill" thread.
565 */
566 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
567
568 if ((env->mcg_cap & MCG_SER_P) && addr) {
569 ram_addr = qemu_ram_addr_from_host(addr);
570 if (ram_addr != RAM_ADDR_INVALID &&
571 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
572 kvm_hwpoison_page_add(ram_addr);
573 kvm_mce_inject(cpu, paddr, code);
574 return;
575 }
576
577 fprintf(stderr, "Hardware memory error for memory used by "
578 "QEMU itself instead of guest system!\n");
579 }
580
581 if (code == BUS_MCEERR_AR) {
582 hardware_memory_error();
583 }
584
585 /* Hope we are lucky for AO MCE */
586 }
587
588 static void kvm_reset_exception(CPUX86State *env)
589 {
590 env->exception_nr = -1;
591 env->exception_pending = 0;
592 env->exception_injected = 0;
593 env->exception_has_payload = false;
594 env->exception_payload = 0;
595 }
596
597 static void kvm_queue_exception(CPUX86State *env,
598 int32_t exception_nr,
599 uint8_t exception_has_payload,
600 uint64_t exception_payload)
601 {
602 assert(env->exception_nr == -1);
603 assert(!env->exception_pending);
604 assert(!env->exception_injected);
605 assert(!env->exception_has_payload);
606
607 env->exception_nr = exception_nr;
608
609 if (has_exception_payload) {
610 env->exception_pending = 1;
611
612 env->exception_has_payload = exception_has_payload;
613 env->exception_payload = exception_payload;
614 } else {
615 env->exception_injected = 1;
616
617 if (exception_nr == EXCP01_DB) {
618 assert(exception_has_payload);
619 env->dr[6] = exception_payload;
620 } else if (exception_nr == EXCP0E_PAGE) {
621 assert(exception_has_payload);
622 env->cr[2] = exception_payload;
623 } else {
624 assert(!exception_has_payload);
625 }
626 }
627 }
628
629 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
630 {
631 CPUX86State *env = &cpu->env;
632
633 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
634 unsigned int bank, bank_num = env->mcg_cap & 0xff;
635 struct kvm_x86_mce mce;
636
637 kvm_reset_exception(env);
638
639 /*
640 * There must be at least one bank in use if an MCE is pending.
641 * Find it and use its values for the event injection.
642 */
643 for (bank = 0; bank < bank_num; bank++) {
644 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
645 break;
646 }
647 }
648 assert(bank < bank_num);
649
650 mce.bank = bank;
651 mce.status = env->mce_banks[bank * 4 + 1];
652 mce.mcg_status = env->mcg_status;
653 mce.addr = env->mce_banks[bank * 4 + 2];
654 mce.misc = env->mce_banks[bank * 4 + 3];
655
656 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
657 }
658 return 0;
659 }
660
661 static void cpu_update_state(void *opaque, int running, RunState state)
662 {
663 CPUX86State *env = opaque;
664
665 if (running) {
666 env->tsc_valid = false;
667 }
668 }
669
670 unsigned long kvm_arch_vcpu_id(CPUState *cs)
671 {
672 X86CPU *cpu = X86_CPU(cs);
673 return cpu->apic_id;
674 }
675
676 #ifndef KVM_CPUID_SIGNATURE_NEXT
677 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
678 #endif
679
680 static bool hyperv_enabled(X86CPU *cpu)
681 {
682 CPUState *cs = CPU(cpu);
683 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
684 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
685 cpu->hyperv_features || cpu->hyperv_passthrough);
686 }
687
688 static int kvm_arch_set_tsc_khz(CPUState *cs)
689 {
690 X86CPU *cpu = X86_CPU(cs);
691 CPUX86State *env = &cpu->env;
692 int r;
693
694 if (!env->tsc_khz) {
695 return 0;
696 }
697
698 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
699 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
700 -ENOTSUP;
701 if (r < 0) {
702 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
703 * TSC frequency doesn't match the one we want.
704 */
705 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
706 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
707 -ENOTSUP;
708 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
709 warn_report("TSC frequency mismatch between "
710 "VM (%" PRId64 " kHz) and host (%d kHz), "
711 "and TSC scaling unavailable",
712 env->tsc_khz, cur_freq);
713 return r;
714 }
715 }
716
717 return 0;
718 }
719
720 static bool tsc_is_stable_and_known(CPUX86State *env)
721 {
722 if (!env->tsc_khz) {
723 return false;
724 }
725 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
726 || env->user_tsc_khz;
727 }
728
729 static struct {
730 const char *desc;
731 struct {
732 uint32_t fw;
733 uint32_t bits;
734 } flags[2];
735 uint64_t dependencies;
736 } kvm_hyperv_properties[] = {
737 [HYPERV_FEAT_RELAXED] = {
738 .desc = "relaxed timing (hv-relaxed)",
739 .flags = {
740 {.fw = FEAT_HYPERV_EAX,
741 .bits = HV_HYPERCALL_AVAILABLE},
742 {.fw = FEAT_HV_RECOMM_EAX,
743 .bits = HV_RELAXED_TIMING_RECOMMENDED}
744 }
745 },
746 [HYPERV_FEAT_VAPIC] = {
747 .desc = "virtual APIC (hv-vapic)",
748 .flags = {
749 {.fw = FEAT_HYPERV_EAX,
750 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
751 {.fw = FEAT_HV_RECOMM_EAX,
752 .bits = HV_APIC_ACCESS_RECOMMENDED}
753 }
754 },
755 [HYPERV_FEAT_TIME] = {
756 .desc = "clocksources (hv-time)",
757 .flags = {
758 {.fw = FEAT_HYPERV_EAX,
759 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
760 HV_REFERENCE_TSC_AVAILABLE}
761 }
762 },
763 [HYPERV_FEAT_CRASH] = {
764 .desc = "crash MSRs (hv-crash)",
765 .flags = {
766 {.fw = FEAT_HYPERV_EDX,
767 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
768 }
769 },
770 [HYPERV_FEAT_RESET] = {
771 .desc = "reset MSR (hv-reset)",
772 .flags = {
773 {.fw = FEAT_HYPERV_EAX,
774 .bits = HV_RESET_AVAILABLE}
775 }
776 },
777 [HYPERV_FEAT_VPINDEX] = {
778 .desc = "VP_INDEX MSR (hv-vpindex)",
779 .flags = {
780 {.fw = FEAT_HYPERV_EAX,
781 .bits = HV_VP_INDEX_AVAILABLE}
782 }
783 },
784 [HYPERV_FEAT_RUNTIME] = {
785 .desc = "VP_RUNTIME MSR (hv-runtime)",
786 .flags = {
787 {.fw = FEAT_HYPERV_EAX,
788 .bits = HV_VP_RUNTIME_AVAILABLE}
789 }
790 },
791 [HYPERV_FEAT_SYNIC] = {
792 .desc = "synthetic interrupt controller (hv-synic)",
793 .flags = {
794 {.fw = FEAT_HYPERV_EAX,
795 .bits = HV_SYNIC_AVAILABLE}
796 }
797 },
798 [HYPERV_FEAT_STIMER] = {
799 .desc = "synthetic timers (hv-stimer)",
800 .flags = {
801 {.fw = FEAT_HYPERV_EAX,
802 .bits = HV_SYNTIMERS_AVAILABLE}
803 },
804 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
805 },
806 [HYPERV_FEAT_FREQUENCIES] = {
807 .desc = "frequency MSRs (hv-frequencies)",
808 .flags = {
809 {.fw = FEAT_HYPERV_EAX,
810 .bits = HV_ACCESS_FREQUENCY_MSRS},
811 {.fw = FEAT_HYPERV_EDX,
812 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
813 }
814 },
815 [HYPERV_FEAT_REENLIGHTENMENT] = {
816 .desc = "reenlightenment MSRs (hv-reenlightenment)",
817 .flags = {
818 {.fw = FEAT_HYPERV_EAX,
819 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
820 }
821 },
822 [HYPERV_FEAT_TLBFLUSH] = {
823 .desc = "paravirtualized TLB flush (hv-tlbflush)",
824 .flags = {
825 {.fw = FEAT_HV_RECOMM_EAX,
826 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
827 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
828 },
829 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
830 },
831 [HYPERV_FEAT_EVMCS] = {
832 .desc = "enlightened VMCS (hv-evmcs)",
833 .flags = {
834 {.fw = FEAT_HV_RECOMM_EAX,
835 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
836 },
837 .dependencies = BIT(HYPERV_FEAT_VAPIC)
838 },
839 [HYPERV_FEAT_IPI] = {
840 .desc = "paravirtualized IPI (hv-ipi)",
841 .flags = {
842 {.fw = FEAT_HV_RECOMM_EAX,
843 .bits = HV_CLUSTER_IPI_RECOMMENDED |
844 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
845 },
846 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
847 },
848 [HYPERV_FEAT_STIMER_DIRECT] = {
849 .desc = "direct mode synthetic timers (hv-stimer-direct)",
850 .flags = {
851 {.fw = FEAT_HYPERV_EDX,
852 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
853 },
854 .dependencies = BIT(HYPERV_FEAT_STIMER)
855 },
856 };
857
858 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
859 {
860 struct kvm_cpuid2 *cpuid;
861 int r, size;
862
863 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
864 cpuid = g_malloc0(size);
865 cpuid->nent = max;
866
867 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
868 if (r == 0 && cpuid->nent >= max) {
869 r = -E2BIG;
870 }
871 if (r < 0) {
872 if (r == -E2BIG) {
873 g_free(cpuid);
874 return NULL;
875 } else {
876 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
877 strerror(-r));
878 exit(1);
879 }
880 }
881 return cpuid;
882 }
883
884 /*
885 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
886 * for all entries.
887 */
888 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
889 {
890 struct kvm_cpuid2 *cpuid;
891 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
892
893 /*
894 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
895 * -E2BIG, however, it doesn't report back the right size. Keep increasing
896 * it and re-trying until we succeed.
897 */
898 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
899 max++;
900 }
901 return cpuid;
902 }
903
904 /*
905 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
906 * leaves from KVM_CAP_HYPERV* and present MSRs data.
907 */
908 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
909 {
910 X86CPU *cpu = X86_CPU(cs);
911 struct kvm_cpuid2 *cpuid;
912 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
913
914 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
915 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
916 cpuid->nent = 2;
917
918 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
919 entry_feat = &cpuid->entries[0];
920 entry_feat->function = HV_CPUID_FEATURES;
921
922 entry_recomm = &cpuid->entries[1];
923 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
924 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
925
926 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
927 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
928 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
929 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
930 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
931 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
932 }
933
934 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
935 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
936 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
937 }
938
939 if (has_msr_hv_frequencies) {
940 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
941 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
942 }
943
944 if (has_msr_hv_crash) {
945 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
946 }
947
948 if (has_msr_hv_reenlightenment) {
949 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
950 }
951
952 if (has_msr_hv_reset) {
953 entry_feat->eax |= HV_RESET_AVAILABLE;
954 }
955
956 if (has_msr_hv_vpindex) {
957 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
958 }
959
960 if (has_msr_hv_runtime) {
961 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
962 }
963
964 if (has_msr_hv_synic) {
965 unsigned int cap = cpu->hyperv_synic_kvm_only ?
966 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
967
968 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
969 entry_feat->eax |= HV_SYNIC_AVAILABLE;
970 }
971 }
972
973 if (has_msr_hv_stimer) {
974 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
975 }
976
977 if (kvm_check_extension(cs->kvm_state,
978 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
979 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
980 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
981 }
982
983 if (kvm_check_extension(cs->kvm_state,
984 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
985 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
986 }
987
988 if (kvm_check_extension(cs->kvm_state,
989 KVM_CAP_HYPERV_SEND_IPI) > 0) {
990 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
991 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
992 }
993
994 return cpuid;
995 }
996
997 static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
998 {
999 struct kvm_cpuid_entry2 *entry;
1000 uint32_t func;
1001 int reg;
1002
1003 switch (fw) {
1004 case FEAT_HYPERV_EAX:
1005 reg = R_EAX;
1006 func = HV_CPUID_FEATURES;
1007 break;
1008 case FEAT_HYPERV_EDX:
1009 reg = R_EDX;
1010 func = HV_CPUID_FEATURES;
1011 break;
1012 case FEAT_HV_RECOMM_EAX:
1013 reg = R_EAX;
1014 func = HV_CPUID_ENLIGHTMENT_INFO;
1015 break;
1016 default:
1017 return -EINVAL;
1018 }
1019
1020 entry = cpuid_find_entry(cpuid, func, 0);
1021 if (!entry) {
1022 return -ENOENT;
1023 }
1024
1025 switch (reg) {
1026 case R_EAX:
1027 *r = entry->eax;
1028 break;
1029 case R_EDX:
1030 *r = entry->edx;
1031 break;
1032 default:
1033 return -EINVAL;
1034 }
1035
1036 return 0;
1037 }
1038
1039 static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
1040 int feature)
1041 {
1042 X86CPU *cpu = X86_CPU(cs);
1043 CPUX86State *env = &cpu->env;
1044 uint32_t r, fw, bits;
1045 uint64_t deps;
1046 int i, dep_feat;
1047
1048 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
1049 return 0;
1050 }
1051
1052 deps = kvm_hyperv_properties[feature].dependencies;
1053 while (deps) {
1054 dep_feat = ctz64(deps);
1055 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1056 fprintf(stderr,
1057 "Hyper-V %s requires Hyper-V %s\n",
1058 kvm_hyperv_properties[feature].desc,
1059 kvm_hyperv_properties[dep_feat].desc);
1060 return 1;
1061 }
1062 deps &= ~(1ull << dep_feat);
1063 }
1064
1065 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1066 fw = kvm_hyperv_properties[feature].flags[i].fw;
1067 bits = kvm_hyperv_properties[feature].flags[i].bits;
1068
1069 if (!fw) {
1070 continue;
1071 }
1072
1073 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
1074 if (hyperv_feat_enabled(cpu, feature)) {
1075 fprintf(stderr,
1076 "Hyper-V %s is not supported by kernel\n",
1077 kvm_hyperv_properties[feature].desc);
1078 return 1;
1079 } else {
1080 return 0;
1081 }
1082 }
1083
1084 env->features[fw] |= bits;
1085 }
1086
1087 if (cpu->hyperv_passthrough) {
1088 cpu->hyperv_features |= BIT(feature);
1089 }
1090
1091 return 0;
1092 }
1093
1094 /*
1095 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1096 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1097 * extentions are enabled.
1098 */
1099 static int hyperv_handle_properties(CPUState *cs,
1100 struct kvm_cpuid_entry2 *cpuid_ent)
1101 {
1102 X86CPU *cpu = X86_CPU(cs);
1103 CPUX86State *env = &cpu->env;
1104 struct kvm_cpuid2 *cpuid;
1105 struct kvm_cpuid_entry2 *c;
1106 uint32_t signature[3];
1107 uint32_t cpuid_i = 0;
1108 int r;
1109
1110 if (!hyperv_enabled(cpu))
1111 return 0;
1112
1113 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1114 cpu->hyperv_passthrough) {
1115 uint16_t evmcs_version;
1116
1117 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1118 (uintptr_t)&evmcs_version);
1119
1120 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
1121 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1122 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1123 return -ENOSYS;
1124 }
1125
1126 if (!r) {
1127 env->features[FEAT_HV_RECOMM_EAX] |=
1128 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1129 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1130 }
1131 }
1132
1133 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1134 cpuid = get_supported_hv_cpuid(cs);
1135 } else {
1136 cpuid = get_supported_hv_cpuid_legacy(cs);
1137 }
1138
1139 if (cpu->hyperv_passthrough) {
1140 memcpy(cpuid_ent, &cpuid->entries[0],
1141 cpuid->nent * sizeof(cpuid->entries[0]));
1142
1143 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1144 if (c) {
1145 env->features[FEAT_HYPERV_EAX] = c->eax;
1146 env->features[FEAT_HYPERV_EBX] = c->ebx;
1147 env->features[FEAT_HYPERV_EDX] = c->eax;
1148 }
1149 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1150 if (c) {
1151 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1152
1153 /* hv-spinlocks may have been overriden */
1154 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1155 c->ebx = cpu->hyperv_spinlock_attempts;
1156 }
1157 }
1158 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1159 if (c) {
1160 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1161 }
1162 }
1163
1164 /* Features */
1165 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
1166 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1167 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1168 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1169 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1170 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1171 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1172 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1173 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1174 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1175 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1176 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1177 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1178 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
1179 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT);
1180
1181 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1182 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1183 !cpu->hyperv_synic_kvm_only &&
1184 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1185 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
1186 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1187 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1188 r |= 1;
1189 }
1190
1191 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1192 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1193
1194 if (r) {
1195 r = -ENOSYS;
1196 goto free;
1197 }
1198
1199 if (cpu->hyperv_passthrough) {
1200 /* We already copied all feature words from KVM as is */
1201 r = cpuid->nent;
1202 goto free;
1203 }
1204
1205 c = &cpuid_ent[cpuid_i++];
1206 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1207 if (!cpu->hyperv_vendor_id) {
1208 memcpy(signature, "Microsoft Hv", 12);
1209 } else {
1210 size_t len = strlen(cpu->hyperv_vendor_id);
1211
1212 if (len > 12) {
1213 error_report("hv-vendor-id truncated to 12 characters");
1214 len = 12;
1215 }
1216 memset(signature, 0, 12);
1217 memcpy(signature, cpu->hyperv_vendor_id, len);
1218 }
1219 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1220 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1221 c->ebx = signature[0];
1222 c->ecx = signature[1];
1223 c->edx = signature[2];
1224
1225 c = &cpuid_ent[cpuid_i++];
1226 c->function = HV_CPUID_INTERFACE;
1227 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1228 c->eax = signature[0];
1229 c->ebx = 0;
1230 c->ecx = 0;
1231 c->edx = 0;
1232
1233 c = &cpuid_ent[cpuid_i++];
1234 c->function = HV_CPUID_VERSION;
1235 c->eax = 0x00001bbc;
1236 c->ebx = 0x00060001;
1237
1238 c = &cpuid_ent[cpuid_i++];
1239 c->function = HV_CPUID_FEATURES;
1240 c->eax = env->features[FEAT_HYPERV_EAX];
1241 c->ebx = env->features[FEAT_HYPERV_EBX];
1242 c->edx = env->features[FEAT_HYPERV_EDX];
1243
1244 c = &cpuid_ent[cpuid_i++];
1245 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1246 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1247 c->ebx = cpu->hyperv_spinlock_attempts;
1248
1249 c = &cpuid_ent[cpuid_i++];
1250 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1251 c->eax = cpu->hv_max_vps;
1252 c->ebx = 0x40;
1253
1254 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1255 __u32 function;
1256
1257 /* Create zeroed 0x40000006..0x40000009 leaves */
1258 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1259 function < HV_CPUID_NESTED_FEATURES; function++) {
1260 c = &cpuid_ent[cpuid_i++];
1261 c->function = function;
1262 }
1263
1264 c = &cpuid_ent[cpuid_i++];
1265 c->function = HV_CPUID_NESTED_FEATURES;
1266 c->eax = env->features[FEAT_HV_NESTED_EAX];
1267 }
1268 r = cpuid_i;
1269
1270 free:
1271 g_free(cpuid);
1272
1273 return r;
1274 }
1275
1276 static Error *hv_passthrough_mig_blocker;
1277
1278 static int hyperv_init_vcpu(X86CPU *cpu)
1279 {
1280 CPUState *cs = CPU(cpu);
1281 Error *local_err = NULL;
1282 int ret;
1283
1284 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1285 error_setg(&hv_passthrough_mig_blocker,
1286 "'hv-passthrough' CPU flag prevents migration, use explicit"
1287 " set of hv-* flags instead");
1288 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1289 if (local_err) {
1290 error_report_err(local_err);
1291 error_free(hv_passthrough_mig_blocker);
1292 return ret;
1293 }
1294 }
1295
1296 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1297 /*
1298 * the kernel doesn't support setting vp_index; assert that its value
1299 * is in sync
1300 */
1301 struct {
1302 struct kvm_msrs info;
1303 struct kvm_msr_entry entries[1];
1304 } msr_data = {
1305 .info.nmsrs = 1,
1306 .entries[0].index = HV_X64_MSR_VP_INDEX,
1307 };
1308
1309 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
1310 if (ret < 0) {
1311 return ret;
1312 }
1313 assert(ret == 1);
1314
1315 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
1316 error_report("kernel's vp_index != QEMU's vp_index");
1317 return -ENXIO;
1318 }
1319 }
1320
1321 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1322 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1323 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1324 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1325 if (ret < 0) {
1326 error_report("failed to turn on HyperV SynIC in KVM: %s",
1327 strerror(-ret));
1328 return ret;
1329 }
1330
1331 if (!cpu->hyperv_synic_kvm_only) {
1332 ret = hyperv_x86_synic_add(cpu);
1333 if (ret < 0) {
1334 error_report("failed to create HyperV SynIC: %s",
1335 strerror(-ret));
1336 return ret;
1337 }
1338 }
1339 }
1340
1341 return 0;
1342 }
1343
1344 static Error *invtsc_mig_blocker;
1345 static Error *nested_virt_mig_blocker;
1346
1347 #define KVM_MAX_CPUID_ENTRIES 100
1348
1349 int kvm_arch_init_vcpu(CPUState *cs)
1350 {
1351 struct {
1352 struct kvm_cpuid2 cpuid;
1353 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
1354 } cpuid_data;
1355 /*
1356 * The kernel defines these structs with padding fields so there
1357 * should be no extra padding in our cpuid_data struct.
1358 */
1359 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1360 sizeof(struct kvm_cpuid2) +
1361 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1362
1363 X86CPU *cpu = X86_CPU(cs);
1364 CPUX86State *env = &cpu->env;
1365 uint32_t limit, i, j, cpuid_i;
1366 uint32_t unused;
1367 struct kvm_cpuid_entry2 *c;
1368 uint32_t signature[3];
1369 int kvm_base = KVM_CPUID_SIGNATURE;
1370 int max_nested_state_len;
1371 int r;
1372 Error *local_err = NULL;
1373
1374 memset(&cpuid_data, 0, sizeof(cpuid_data));
1375
1376 cpuid_i = 0;
1377
1378 r = kvm_arch_set_tsc_khz(cs);
1379 if (r < 0) {
1380 return r;
1381 }
1382
1383 /* vcpu's TSC frequency is either specified by user, or following
1384 * the value used by KVM if the former is not present. In the
1385 * latter case, we query it from KVM and record in env->tsc_khz,
1386 * so that vcpu's TSC frequency can be migrated later via this field.
1387 */
1388 if (!env->tsc_khz) {
1389 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1390 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1391 -ENOTSUP;
1392 if (r > 0) {
1393 env->tsc_khz = r;
1394 }
1395 }
1396
1397 /* Paravirtualization CPUIDs */
1398 r = hyperv_handle_properties(cs, cpuid_data.entries);
1399 if (r < 0) {
1400 return r;
1401 } else if (r > 0) {
1402 cpuid_i = r;
1403 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
1404 has_msr_hv_hypercall = true;
1405 }
1406
1407 if (cpu->expose_kvm) {
1408 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1409 c = &cpuid_data.entries[cpuid_i++];
1410 c->function = KVM_CPUID_SIGNATURE | kvm_base;
1411 c->eax = KVM_CPUID_FEATURES | kvm_base;
1412 c->ebx = signature[0];
1413 c->ecx = signature[1];
1414 c->edx = signature[2];
1415
1416 c = &cpuid_data.entries[cpuid_i++];
1417 c->function = KVM_CPUID_FEATURES | kvm_base;
1418 c->eax = env->features[FEAT_KVM];
1419 c->edx = env->features[FEAT_KVM_HINTS];
1420 }
1421
1422 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1423
1424 for (i = 0; i <= limit; i++) {
1425 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1426 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1427 abort();
1428 }
1429 c = &cpuid_data.entries[cpuid_i++];
1430
1431 switch (i) {
1432 case 2: {
1433 /* Keep reading function 2 till all the input is received */
1434 int times;
1435
1436 c->function = i;
1437 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1438 KVM_CPUID_FLAG_STATE_READ_NEXT;
1439 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1440 times = c->eax & 0xff;
1441
1442 for (j = 1; j < times; ++j) {
1443 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1444 fprintf(stderr, "cpuid_data is full, no space for "
1445 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1446 abort();
1447 }
1448 c = &cpuid_data.entries[cpuid_i++];
1449 c->function = i;
1450 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1451 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1452 }
1453 break;
1454 }
1455 case 0x1f:
1456 if (env->nr_dies < 2) {
1457 break;
1458 }
1459 case 4:
1460 case 0xb:
1461 case 0xd:
1462 for (j = 0; ; j++) {
1463 if (i == 0xd && j == 64) {
1464 break;
1465 }
1466
1467 if (i == 0x1f && j == 64) {
1468 break;
1469 }
1470
1471 c->function = i;
1472 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1473 c->index = j;
1474 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1475
1476 if (i == 4 && c->eax == 0) {
1477 break;
1478 }
1479 if (i == 0xb && !(c->ecx & 0xff00)) {
1480 break;
1481 }
1482 if (i == 0x1f && !(c->ecx & 0xff00)) {
1483 break;
1484 }
1485 if (i == 0xd && c->eax == 0) {
1486 continue;
1487 }
1488 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1489 fprintf(stderr, "cpuid_data is full, no space for "
1490 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1491 abort();
1492 }
1493 c = &cpuid_data.entries[cpuid_i++];
1494 }
1495 break;
1496 case 0x14: {
1497 uint32_t times;
1498
1499 c->function = i;
1500 c->index = 0;
1501 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1502 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1503 times = c->eax;
1504
1505 for (j = 1; j <= times; ++j) {
1506 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1507 fprintf(stderr, "cpuid_data is full, no space for "
1508 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1509 abort();
1510 }
1511 c = &cpuid_data.entries[cpuid_i++];
1512 c->function = i;
1513 c->index = j;
1514 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1515 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1516 }
1517 break;
1518 }
1519 default:
1520 c->function = i;
1521 c->flags = 0;
1522 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1523 break;
1524 }
1525 }
1526
1527 if (limit >= 0x0a) {
1528 uint32_t eax, edx;
1529
1530 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1531
1532 has_architectural_pmu_version = eax & 0xff;
1533 if (has_architectural_pmu_version > 0) {
1534 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1535
1536 /* Shouldn't be more than 32, since that's the number of bits
1537 * available in EBX to tell us _which_ counters are available.
1538 * Play it safe.
1539 */
1540 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1541 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1542 }
1543
1544 if (has_architectural_pmu_version > 1) {
1545 num_architectural_pmu_fixed_counters = edx & 0x1f;
1546
1547 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1548 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1549 }
1550 }
1551 }
1552 }
1553
1554 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1555
1556 for (i = 0x80000000; i <= limit; i++) {
1557 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1558 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1559 abort();
1560 }
1561 c = &cpuid_data.entries[cpuid_i++];
1562
1563 switch (i) {
1564 case 0x8000001d:
1565 /* Query for all AMD cache information leaves */
1566 for (j = 0; ; j++) {
1567 c->function = i;
1568 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1569 c->index = j;
1570 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1571
1572 if (c->eax == 0) {
1573 break;
1574 }
1575 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1576 fprintf(stderr, "cpuid_data is full, no space for "
1577 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1578 abort();
1579 }
1580 c = &cpuid_data.entries[cpuid_i++];
1581 }
1582 break;
1583 default:
1584 c->function = i;
1585 c->flags = 0;
1586 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1587 break;
1588 }
1589 }
1590
1591 /* Call Centaur's CPUID instructions they are supported. */
1592 if (env->cpuid_xlevel2 > 0) {
1593 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1594
1595 for (i = 0xC0000000; i <= limit; i++) {
1596 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1597 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1598 abort();
1599 }
1600 c = &cpuid_data.entries[cpuid_i++];
1601
1602 c->function = i;
1603 c->flags = 0;
1604 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1605 }
1606 }
1607
1608 cpuid_data.cpuid.nent = cpuid_i;
1609
1610 if (((env->cpuid_version >> 8)&0xF) >= 6
1611 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1612 (CPUID_MCE | CPUID_MCA)
1613 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1614 uint64_t mcg_cap, unsupported_caps;
1615 int banks;
1616 int ret;
1617
1618 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1619 if (ret < 0) {
1620 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1621 return ret;
1622 }
1623
1624 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1625 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1626 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1627 return -ENOTSUP;
1628 }
1629
1630 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1631 if (unsupported_caps) {
1632 if (unsupported_caps & MCG_LMCE_P) {
1633 error_report("kvm: LMCE not supported");
1634 return -ENOTSUP;
1635 }
1636 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1637 unsupported_caps);
1638 }
1639
1640 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1641 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1642 if (ret < 0) {
1643 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1644 return ret;
1645 }
1646 }
1647
1648 qemu_add_vm_change_state_handler(cpu_update_state, env);
1649
1650 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1651 if (c) {
1652 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1653 !!(c->ecx & CPUID_EXT_SMX);
1654 }
1655
1656 if (cpu_has_vmx(env) && !nested_virt_mig_blocker &&
1657 ((kvm_max_nested_state_length() <= 0) || !has_exception_payload)) {
1658 error_setg(&nested_virt_mig_blocker,
1659 "Kernel do not provide required capabilities for "
1660 "nested virtualization migration. "
1661 "(CAP_NESTED_STATE=%d, CAP_EXCEPTION_PAYLOAD=%d)",
1662 kvm_max_nested_state_length() > 0,
1663 has_exception_payload);
1664 r = migrate_add_blocker(nested_virt_mig_blocker, &local_err);
1665 if (local_err) {
1666 error_report_err(local_err);
1667 error_free(nested_virt_mig_blocker);
1668 return r;
1669 }
1670 }
1671
1672 if (env->mcg_cap & MCG_LMCE_P) {
1673 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1674 }
1675
1676 if (!env->user_tsc_khz) {
1677 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1678 invtsc_mig_blocker == NULL) {
1679 error_setg(&invtsc_mig_blocker,
1680 "State blocked by non-migratable CPU device"
1681 " (invtsc flag)");
1682 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1683 if (local_err) {
1684 error_report_err(local_err);
1685 error_free(invtsc_mig_blocker);
1686 goto fail2;
1687 }
1688 }
1689 }
1690
1691 if (cpu->vmware_cpuid_freq
1692 /* Guests depend on 0x40000000 to detect this feature, so only expose
1693 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1694 && cpu->expose_kvm
1695 && kvm_base == KVM_CPUID_SIGNATURE
1696 /* TSC clock must be stable and known for this feature. */
1697 && tsc_is_stable_and_known(env)) {
1698
1699 c = &cpuid_data.entries[cpuid_i++];
1700 c->function = KVM_CPUID_SIGNATURE | 0x10;
1701 c->eax = env->tsc_khz;
1702 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1703 * APIC_BUS_CYCLE_NS */
1704 c->ebx = 1000000;
1705 c->ecx = c->edx = 0;
1706
1707 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1708 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1709 }
1710
1711 cpuid_data.cpuid.nent = cpuid_i;
1712
1713 cpuid_data.cpuid.padding = 0;
1714 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1715 if (r) {
1716 goto fail;
1717 }
1718
1719 if (has_xsave) {
1720 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1721 }
1722
1723 max_nested_state_len = kvm_max_nested_state_length();
1724 if (max_nested_state_len > 0) {
1725 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
1726 env->nested_state = g_malloc0(max_nested_state_len);
1727
1728 env->nested_state->size = max_nested_state_len;
1729
1730 if (IS_INTEL_CPU(env)) {
1731 struct kvm_vmx_nested_state_hdr *vmx_hdr =
1732 &env->nested_state->hdr.vmx;
1733
1734 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1735 vmx_hdr->vmxon_pa = -1ull;
1736 vmx_hdr->vmcs12_pa = -1ull;
1737 }
1738 }
1739
1740 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1741
1742 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1743 has_msr_tsc_aux = false;
1744 }
1745
1746 r = hyperv_init_vcpu(cpu);
1747 if (r) {
1748 goto fail;
1749 }
1750
1751 return 0;
1752
1753 fail:
1754 migrate_del_blocker(invtsc_mig_blocker);
1755 fail2:
1756 migrate_del_blocker(nested_virt_mig_blocker);
1757
1758 return r;
1759 }
1760
1761 int kvm_arch_destroy_vcpu(CPUState *cs)
1762 {
1763 X86CPU *cpu = X86_CPU(cs);
1764 CPUX86State *env = &cpu->env;
1765
1766 if (cpu->kvm_msr_buf) {
1767 g_free(cpu->kvm_msr_buf);
1768 cpu->kvm_msr_buf = NULL;
1769 }
1770
1771 if (env->nested_state) {
1772 g_free(env->nested_state);
1773 env->nested_state = NULL;
1774 }
1775
1776 return 0;
1777 }
1778
1779 void kvm_arch_reset_vcpu(X86CPU *cpu)
1780 {
1781 CPUX86State *env = &cpu->env;
1782
1783 env->xcr0 = 1;
1784 if (kvm_irqchip_in_kernel()) {
1785 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1786 KVM_MP_STATE_UNINITIALIZED;
1787 } else {
1788 env->mp_state = KVM_MP_STATE_RUNNABLE;
1789 }
1790
1791 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1792 int i;
1793 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1794 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1795 }
1796
1797 hyperv_x86_synic_reset(cpu);
1798 }
1799 }
1800
1801 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1802 {
1803 CPUX86State *env = &cpu->env;
1804
1805 /* APs get directly into wait-for-SIPI state. */
1806 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1807 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1808 }
1809 }
1810
1811 static int kvm_get_supported_feature_msrs(KVMState *s)
1812 {
1813 int ret = 0;
1814
1815 if (kvm_feature_msrs != NULL) {
1816 return 0;
1817 }
1818
1819 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1820 return 0;
1821 }
1822
1823 struct kvm_msr_list msr_list;
1824
1825 msr_list.nmsrs = 0;
1826 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1827 if (ret < 0 && ret != -E2BIG) {
1828 error_report("Fetch KVM feature MSR list failed: %s",
1829 strerror(-ret));
1830 return ret;
1831 }
1832
1833 assert(msr_list.nmsrs > 0);
1834 kvm_feature_msrs = (struct kvm_msr_list *) \
1835 g_malloc0(sizeof(msr_list) +
1836 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1837
1838 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1839 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1840
1841 if (ret < 0) {
1842 error_report("Fetch KVM feature MSR list failed: %s",
1843 strerror(-ret));
1844 g_free(kvm_feature_msrs);
1845 kvm_feature_msrs = NULL;
1846 return ret;
1847 }
1848
1849 return 0;
1850 }
1851
1852 static int kvm_get_supported_msrs(KVMState *s)
1853 {
1854 static int kvm_supported_msrs;
1855 int ret = 0;
1856
1857 /* first time */
1858 if (kvm_supported_msrs == 0) {
1859 struct kvm_msr_list msr_list, *kvm_msr_list;
1860
1861 kvm_supported_msrs = -1;
1862
1863 /* Obtain MSR list from KVM. These are the MSRs that we must
1864 * save/restore */
1865 msr_list.nmsrs = 0;
1866 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1867 if (ret < 0 && ret != -E2BIG) {
1868 return ret;
1869 }
1870 /* Old kernel modules had a bug and could write beyond the provided
1871 memory. Allocate at least a safe amount of 1K. */
1872 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1873 msr_list.nmsrs *
1874 sizeof(msr_list.indices[0])));
1875
1876 kvm_msr_list->nmsrs = msr_list.nmsrs;
1877 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1878 if (ret >= 0) {
1879 int i;
1880
1881 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1882 switch (kvm_msr_list->indices[i]) {
1883 case MSR_STAR:
1884 has_msr_star = true;
1885 break;
1886 case MSR_VM_HSAVE_PA:
1887 has_msr_hsave_pa = true;
1888 break;
1889 case MSR_TSC_AUX:
1890 has_msr_tsc_aux = true;
1891 break;
1892 case MSR_TSC_ADJUST:
1893 has_msr_tsc_adjust = true;
1894 break;
1895 case MSR_IA32_TSCDEADLINE:
1896 has_msr_tsc_deadline = true;
1897 break;
1898 case MSR_IA32_SMBASE:
1899 has_msr_smbase = true;
1900 break;
1901 case MSR_SMI_COUNT:
1902 has_msr_smi_count = true;
1903 break;
1904 case MSR_IA32_MISC_ENABLE:
1905 has_msr_misc_enable = true;
1906 break;
1907 case MSR_IA32_BNDCFGS:
1908 has_msr_bndcfgs = true;
1909 break;
1910 case MSR_IA32_XSS:
1911 has_msr_xss = true;
1912 break;
1913 case HV_X64_MSR_CRASH_CTL:
1914 has_msr_hv_crash = true;
1915 break;
1916 case HV_X64_MSR_RESET:
1917 has_msr_hv_reset = true;
1918 break;
1919 case HV_X64_MSR_VP_INDEX:
1920 has_msr_hv_vpindex = true;
1921 break;
1922 case HV_X64_MSR_VP_RUNTIME:
1923 has_msr_hv_runtime = true;
1924 break;
1925 case HV_X64_MSR_SCONTROL:
1926 has_msr_hv_synic = true;
1927 break;
1928 case HV_X64_MSR_STIMER0_CONFIG:
1929 has_msr_hv_stimer = true;
1930 break;
1931 case HV_X64_MSR_TSC_FREQUENCY:
1932 has_msr_hv_frequencies = true;
1933 break;
1934 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1935 has_msr_hv_reenlightenment = true;
1936 break;
1937 case MSR_IA32_SPEC_CTRL:
1938 has_msr_spec_ctrl = true;
1939 break;
1940 case MSR_VIRT_SSBD:
1941 has_msr_virt_ssbd = true;
1942 break;
1943 case MSR_IA32_ARCH_CAPABILITIES:
1944 has_msr_arch_capabs = true;
1945 break;
1946 case MSR_IA32_CORE_CAPABILITY:
1947 has_msr_core_capabs = true;
1948 break;
1949 }
1950 }
1951 }
1952
1953 g_free(kvm_msr_list);
1954 }
1955
1956 return ret;
1957 }
1958
1959 static Notifier smram_machine_done;
1960 static KVMMemoryListener smram_listener;
1961 static AddressSpace smram_address_space;
1962 static MemoryRegion smram_as_root;
1963 static MemoryRegion smram_as_mem;
1964
1965 static void register_smram_listener(Notifier *n, void *unused)
1966 {
1967 MemoryRegion *smram =
1968 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1969
1970 /* Outer container... */
1971 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1972 memory_region_set_enabled(&smram_as_root, true);
1973
1974 /* ... with two regions inside: normal system memory with low
1975 * priority, and...
1976 */
1977 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1978 get_system_memory(), 0, ~0ull);
1979 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1980 memory_region_set_enabled(&smram_as_mem, true);
1981
1982 if (smram) {
1983 /* ... SMRAM with higher priority */
1984 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1985 memory_region_set_enabled(smram, true);
1986 }
1987
1988 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1989 kvm_memory_listener_register(kvm_state, &smram_listener,
1990 &smram_address_space, 1);
1991 }
1992
1993 int kvm_arch_init(MachineState *ms, KVMState *s)
1994 {
1995 uint64_t identity_base = 0xfffbc000;
1996 uint64_t shadow_mem;
1997 int ret;
1998 struct utsname utsname;
1999
2000 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
2001 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
2002 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
2003
2004 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2005
2006 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2007 if (has_exception_payload) {
2008 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2009 if (ret < 0) {
2010 error_report("kvm: Failed to enable exception payload cap: %s",
2011 strerror(-ret));
2012 return ret;
2013 }
2014 }
2015
2016 ret = kvm_get_supported_msrs(s);
2017 if (ret < 0) {
2018 return ret;
2019 }
2020
2021 kvm_get_supported_feature_msrs(s);
2022
2023 uname(&utsname);
2024 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2025
2026 /*
2027 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2028 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2029 * Since these must be part of guest physical memory, we need to allocate
2030 * them, both by setting their start addresses in the kernel and by
2031 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2032 *
2033 * Older KVM versions may not support setting the identity map base. In
2034 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2035 * size.
2036 */
2037 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2038 /* Allows up to 16M BIOSes. */
2039 identity_base = 0xfeffc000;
2040
2041 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2042 if (ret < 0) {
2043 return ret;
2044 }
2045 }
2046
2047 /* Set TSS base one page after EPT identity map. */
2048 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
2049 if (ret < 0) {
2050 return ret;
2051 }
2052
2053 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2054 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
2055 if (ret < 0) {
2056 fprintf(stderr, "e820_add_entry() table is full\n");
2057 return ret;
2058 }
2059 qemu_register_reset(kvm_unpoison_all, NULL);
2060
2061 shadow_mem = machine_kvm_shadow_mem(ms);
2062 if (shadow_mem != -1) {
2063 shadow_mem /= 4096;
2064 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2065 if (ret < 0) {
2066 return ret;
2067 }
2068 }
2069
2070 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
2071 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
2072 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
2073 smram_machine_done.notify = register_smram_listener;
2074 qemu_add_machine_init_done_notifier(&smram_machine_done);
2075 }
2076
2077 if (enable_cpu_pm) {
2078 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2079 int ret;
2080
2081 /* Work around for kernel header with a typo. TODO: fix header and drop. */
2082 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2083 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2084 #endif
2085 if (disable_exits) {
2086 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2087 KVM_X86_DISABLE_EXITS_HLT |
2088 KVM_X86_DISABLE_EXITS_PAUSE);
2089 }
2090
2091 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2092 disable_exits);
2093 if (ret < 0) {
2094 error_report("kvm: guest stopping CPU not supported: %s",
2095 strerror(-ret));
2096 }
2097 }
2098
2099 return 0;
2100 }
2101
2102 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2103 {
2104 lhs->selector = rhs->selector;
2105 lhs->base = rhs->base;
2106 lhs->limit = rhs->limit;
2107 lhs->type = 3;
2108 lhs->present = 1;
2109 lhs->dpl = 3;
2110 lhs->db = 0;
2111 lhs->s = 1;
2112 lhs->l = 0;
2113 lhs->g = 0;
2114 lhs->avl = 0;
2115 lhs->unusable = 0;
2116 }
2117
2118 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2119 {
2120 unsigned flags = rhs->flags;
2121 lhs->selector = rhs->selector;
2122 lhs->base = rhs->base;
2123 lhs->limit = rhs->limit;
2124 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2125 lhs->present = (flags & DESC_P_MASK) != 0;
2126 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
2127 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2128 lhs->s = (flags & DESC_S_MASK) != 0;
2129 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2130 lhs->g = (flags & DESC_G_MASK) != 0;
2131 lhs->avl = (flags & DESC_AVL_MASK) != 0;
2132 lhs->unusable = !lhs->present;
2133 lhs->padding = 0;
2134 }
2135
2136 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2137 {
2138 lhs->selector = rhs->selector;
2139 lhs->base = rhs->base;
2140 lhs->limit = rhs->limit;
2141 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2142 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2143 (rhs->dpl << DESC_DPL_SHIFT) |
2144 (rhs->db << DESC_B_SHIFT) |
2145 (rhs->s * DESC_S_MASK) |
2146 (rhs->l << DESC_L_SHIFT) |
2147 (rhs->g * DESC_G_MASK) |
2148 (rhs->avl * DESC_AVL_MASK);
2149 }
2150
2151 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2152 {
2153 if (set) {
2154 *kvm_reg = *qemu_reg;
2155 } else {
2156 *qemu_reg = *kvm_reg;
2157 }
2158 }
2159
2160 static int kvm_getput_regs(X86CPU *cpu, int set)
2161 {
2162 CPUX86State *env = &cpu->env;
2163 struct kvm_regs regs;
2164 int ret = 0;
2165
2166 if (!set) {
2167 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
2168 if (ret < 0) {
2169 return ret;
2170 }
2171 }
2172
2173 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2174 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2175 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2176 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2177 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2178 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2179 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2180 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2181 #ifdef TARGET_X86_64
2182 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2183 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2184 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2185 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2186 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2187 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2188 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2189 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2190 #endif
2191
2192 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2193 kvm_getput_reg(&regs.rip, &env->eip, set);
2194
2195 if (set) {
2196 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
2197 }
2198
2199 return ret;
2200 }
2201
2202 static int kvm_put_fpu(X86CPU *cpu)
2203 {
2204 CPUX86State *env = &cpu->env;
2205 struct kvm_fpu fpu;
2206 int i;
2207
2208 memset(&fpu, 0, sizeof fpu);
2209 fpu.fsw = env->fpus & ~(7 << 11);
2210 fpu.fsw |= (env->fpstt & 7) << 11;
2211 fpu.fcw = env->fpuc;
2212 fpu.last_opcode = env->fpop;
2213 fpu.last_ip = env->fpip;
2214 fpu.last_dp = env->fpdp;
2215 for (i = 0; i < 8; ++i) {
2216 fpu.ftwx |= (!env->fptags[i]) << i;
2217 }
2218 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
2219 for (i = 0; i < CPU_NB_REGS; i++) {
2220 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2221 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
2222 }
2223 fpu.mxcsr = env->mxcsr;
2224
2225 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
2226 }
2227
2228 #define XSAVE_FCW_FSW 0
2229 #define XSAVE_FTW_FOP 1
2230 #define XSAVE_CWD_RIP 2
2231 #define XSAVE_CWD_RDP 4
2232 #define XSAVE_MXCSR 6
2233 #define XSAVE_ST_SPACE 8
2234 #define XSAVE_XMM_SPACE 40
2235 #define XSAVE_XSTATE_BV 128
2236 #define XSAVE_YMMH_SPACE 144
2237 #define XSAVE_BNDREGS 240
2238 #define XSAVE_BNDCSR 256
2239 #define XSAVE_OPMASK 272
2240 #define XSAVE_ZMM_Hi256 288
2241 #define XSAVE_Hi16_ZMM 416
2242 #define XSAVE_PKRU 672
2243
2244 #define XSAVE_BYTE_OFFSET(word_offset) \
2245 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
2246
2247 #define ASSERT_OFFSET(word_offset, field) \
2248 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2249 offsetof(X86XSaveArea, field))
2250
2251 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2252 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2253 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2254 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2255 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2256 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2257 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2258 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2259 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2260 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2261 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2262 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2263 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2264 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2265 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2266
2267 static int kvm_put_xsave(X86CPU *cpu)
2268 {
2269 CPUX86State *env = &cpu->env;
2270 X86XSaveArea *xsave = env->xsave_buf;
2271
2272 if (!has_xsave) {
2273 return kvm_put_fpu(cpu);
2274 }
2275 x86_cpu_xsave_all_areas(cpu, xsave);
2276
2277 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
2278 }
2279
2280 static int kvm_put_xcrs(X86CPU *cpu)
2281 {
2282 CPUX86State *env = &cpu->env;
2283 struct kvm_xcrs xcrs = {};
2284
2285 if (!has_xcrs) {
2286 return 0;
2287 }
2288
2289 xcrs.nr_xcrs = 1;
2290 xcrs.flags = 0;
2291 xcrs.xcrs[0].xcr = 0;
2292 xcrs.xcrs[0].value = env->xcr0;
2293 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
2294 }
2295
2296 static int kvm_put_sregs(X86CPU *cpu)
2297 {
2298 CPUX86State *env = &cpu->env;
2299 struct kvm_sregs sregs;
2300
2301 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2302 if (env->interrupt_injected >= 0) {
2303 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2304 (uint64_t)1 << (env->interrupt_injected % 64);
2305 }
2306
2307 if ((env->eflags & VM_MASK)) {
2308 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2309 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2310 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2311 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2312 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2313 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
2314 } else {
2315 set_seg(&sregs.cs, &env->segs[R_CS]);
2316 set_seg(&sregs.ds, &env->segs[R_DS]);
2317 set_seg(&sregs.es, &env->segs[R_ES]);
2318 set_seg(&sregs.fs, &env->segs[R_FS]);
2319 set_seg(&sregs.gs, &env->segs[R_GS]);
2320 set_seg(&sregs.ss, &env->segs[R_SS]);
2321 }
2322
2323 set_seg(&sregs.tr, &env->tr);
2324 set_seg(&sregs.ldt, &env->ldt);
2325
2326 sregs.idt.limit = env->idt.limit;
2327 sregs.idt.base = env->idt.base;
2328 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
2329 sregs.gdt.limit = env->gdt.limit;
2330 sregs.gdt.base = env->gdt.base;
2331 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
2332
2333 sregs.cr0 = env->cr[0];
2334 sregs.cr2 = env->cr[2];
2335 sregs.cr3 = env->cr[3];
2336 sregs.cr4 = env->cr[4];
2337
2338 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2339 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
2340
2341 sregs.efer = env->efer;
2342
2343 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
2344 }
2345
2346 static void kvm_msr_buf_reset(X86CPU *cpu)
2347 {
2348 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2349 }
2350
2351 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2352 {
2353 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2354 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2355 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2356
2357 assert((void *)(entry + 1) <= limit);
2358
2359 entry->index = index;
2360 entry->reserved = 0;
2361 entry->data = value;
2362 msrs->nmsrs++;
2363 }
2364
2365 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2366 {
2367 kvm_msr_buf_reset(cpu);
2368 kvm_msr_entry_add(cpu, index, value);
2369
2370 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2371 }
2372
2373 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2374 {
2375 int ret;
2376
2377 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2378 assert(ret == 1);
2379 }
2380
2381 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2382 {
2383 CPUX86State *env = &cpu->env;
2384 int ret;
2385
2386 if (!has_msr_tsc_deadline) {
2387 return 0;
2388 }
2389
2390 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
2391 if (ret < 0) {
2392 return ret;
2393 }
2394
2395 assert(ret == 1);
2396 return 0;
2397 }
2398
2399 /*
2400 * Provide a separate write service for the feature control MSR in order to
2401 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2402 * before writing any other state because forcibly leaving nested mode
2403 * invalidates the VCPU state.
2404 */
2405 static int kvm_put_msr_feature_control(X86CPU *cpu)
2406 {
2407 int ret;
2408
2409 if (!has_msr_feature_control) {
2410 return 0;
2411 }
2412
2413 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2414 cpu->env.msr_ia32_feature_control);
2415 if (ret < 0) {
2416 return ret;
2417 }
2418
2419 assert(ret == 1);
2420 return 0;
2421 }
2422
2423 static int kvm_put_msrs(X86CPU *cpu, int level)
2424 {
2425 CPUX86State *env = &cpu->env;
2426 int i;
2427 int ret;
2428
2429 kvm_msr_buf_reset(cpu);
2430
2431 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2432 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2433 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2434 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
2435 if (has_msr_star) {
2436 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
2437 }
2438 if (has_msr_hsave_pa) {
2439 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
2440 }
2441 if (has_msr_tsc_aux) {
2442 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
2443 }
2444 if (has_msr_tsc_adjust) {
2445 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
2446 }
2447 if (has_msr_misc_enable) {
2448 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
2449 env->msr_ia32_misc_enable);
2450 }
2451 if (has_msr_smbase) {
2452 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
2453 }
2454 if (has_msr_smi_count) {
2455 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2456 }
2457 if (has_msr_bndcfgs) {
2458 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
2459 }
2460 if (has_msr_xss) {
2461 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
2462 }
2463 if (has_msr_spec_ctrl) {
2464 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2465 }
2466 if (has_msr_virt_ssbd) {
2467 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2468 }
2469
2470 #ifdef TARGET_X86_64
2471 if (lm_capable_kernel) {
2472 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2473 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2474 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2475 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
2476 }
2477 #endif
2478
2479 /* If host supports feature MSR, write down. */
2480 if (has_msr_arch_capabs) {
2481 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2482 env->features[FEAT_ARCH_CAPABILITIES]);
2483 }
2484
2485 if (has_msr_core_capabs) {
2486 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2487 env->features[FEAT_CORE_CAPABILITY]);
2488 }
2489
2490 /*
2491 * The following MSRs have side effects on the guest or are too heavy
2492 * for normal writeback. Limit them to reset or full state updates.
2493 */
2494 if (level >= KVM_PUT_RESET_STATE) {
2495 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2496 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2497 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
2498 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2499 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
2500 }
2501 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2502 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2503 }
2504 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2505 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2506 }
2507 if (has_architectural_pmu_version > 0) {
2508 if (has_architectural_pmu_version > 1) {
2509 /* Stop the counter. */
2510 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2511 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2512 }
2513
2514 /* Set the counter values. */
2515 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2516 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2517 env->msr_fixed_counters[i]);
2518 }
2519 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2520 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2521 env->msr_gp_counters[i]);
2522 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2523 env->msr_gp_evtsel[i]);
2524 }
2525 if (has_architectural_pmu_version > 1) {
2526 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2527 env->msr_global_status);
2528 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2529 env->msr_global_ovf_ctrl);
2530
2531 /* Now start the PMU. */
2532 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2533 env->msr_fixed_ctr_ctrl);
2534 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2535 env->msr_global_ctrl);
2536 }
2537 }
2538 /*
2539 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2540 * only sync them to KVM on the first cpu
2541 */
2542 if (current_cpu == first_cpu) {
2543 if (has_msr_hv_hypercall) {
2544 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2545 env->msr_hv_guest_os_id);
2546 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2547 env->msr_hv_hypercall);
2548 }
2549 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
2550 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2551 env->msr_hv_tsc);
2552 }
2553 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
2554 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2555 env->msr_hv_reenlightenment_control);
2556 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2557 env->msr_hv_tsc_emulation_control);
2558 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2559 env->msr_hv_tsc_emulation_status);
2560 }
2561 }
2562 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
2563 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2564 env->msr_hv_vapic);
2565 }
2566 if (has_msr_hv_crash) {
2567 int j;
2568
2569 for (j = 0; j < HV_CRASH_PARAMS; j++)
2570 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2571 env->msr_hv_crash_params[j]);
2572
2573 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2574 }
2575 if (has_msr_hv_runtime) {
2576 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2577 }
2578 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2579 && hv_vpindex_settable) {
2580 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2581 hyperv_vp_index(CPU(cpu)));
2582 }
2583 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2584 int j;
2585
2586 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2587
2588 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2589 env->msr_hv_synic_control);
2590 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
2591 env->msr_hv_synic_evt_page);
2592 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
2593 env->msr_hv_synic_msg_page);
2594
2595 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
2596 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
2597 env->msr_hv_synic_sint[j]);
2598 }
2599 }
2600 if (has_msr_hv_stimer) {
2601 int j;
2602
2603 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
2604 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
2605 env->msr_hv_stimer_config[j]);
2606 }
2607
2608 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2609 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2610 env->msr_hv_stimer_count[j]);
2611 }
2612 }
2613 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2614 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2615
2616 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2617 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2618 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2619 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2620 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2621 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2622 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2623 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2624 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2625 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2626 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2627 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2628 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2629 /* The CPU GPs if we write to a bit above the physical limit of
2630 * the host CPU (and KVM emulates that)
2631 */
2632 uint64_t mask = env->mtrr_var[i].mask;
2633 mask &= phys_mask;
2634
2635 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2636 env->mtrr_var[i].base);
2637 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2638 }
2639 }
2640 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2641 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2642 0x14, 1, R_EAX) & 0x7;
2643
2644 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2645 env->msr_rtit_ctrl);
2646 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2647 env->msr_rtit_status);
2648 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2649 env->msr_rtit_output_base);
2650 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2651 env->msr_rtit_output_mask);
2652 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2653 env->msr_rtit_cr3_match);
2654 for (i = 0; i < addr_num; i++) {
2655 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2656 env->msr_rtit_addrs[i]);
2657 }
2658 }
2659
2660 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2661 * kvm_put_msr_feature_control. */
2662 }
2663 if (env->mcg_cap) {
2664 int i;
2665
2666 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2667 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2668 if (has_msr_mcg_ext_ctl) {
2669 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2670 }
2671 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2672 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2673 }
2674 }
2675
2676 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2677 if (ret < 0) {
2678 return ret;
2679 }
2680
2681 if (ret < cpu->kvm_msr_buf->nmsrs) {
2682 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2683 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2684 (uint32_t)e->index, (uint64_t)e->data);
2685 }
2686
2687 assert(ret == cpu->kvm_msr_buf->nmsrs);
2688 return 0;
2689 }
2690
2691
2692 static int kvm_get_fpu(X86CPU *cpu)
2693 {
2694 CPUX86State *env = &cpu->env;
2695 struct kvm_fpu fpu;
2696 int i, ret;
2697
2698 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
2699 if (ret < 0) {
2700 return ret;
2701 }
2702
2703 env->fpstt = (fpu.fsw >> 11) & 7;
2704 env->fpus = fpu.fsw;
2705 env->fpuc = fpu.fcw;
2706 env->fpop = fpu.last_opcode;
2707 env->fpip = fpu.last_ip;
2708 env->fpdp = fpu.last_dp;
2709 for (i = 0; i < 8; ++i) {
2710 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2711 }
2712 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
2713 for (i = 0; i < CPU_NB_REGS; i++) {
2714 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2715 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
2716 }
2717 env->mxcsr = fpu.mxcsr;
2718
2719 return 0;
2720 }
2721
2722 static int kvm_get_xsave(X86CPU *cpu)
2723 {
2724 CPUX86State *env = &cpu->env;
2725 X86XSaveArea *xsave = env->xsave_buf;
2726 int ret;
2727
2728 if (!has_xsave) {
2729 return kvm_get_fpu(cpu);
2730 }
2731
2732 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
2733 if (ret < 0) {
2734 return ret;
2735 }
2736 x86_cpu_xrstor_all_areas(cpu, xsave);
2737
2738 return 0;
2739 }
2740
2741 static int kvm_get_xcrs(X86CPU *cpu)
2742 {
2743 CPUX86State *env = &cpu->env;
2744 int i, ret;
2745 struct kvm_xcrs xcrs;
2746
2747 if (!has_xcrs) {
2748 return 0;
2749 }
2750
2751 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
2752 if (ret < 0) {
2753 return ret;
2754 }
2755
2756 for (i = 0; i < xcrs.nr_xcrs; i++) {
2757 /* Only support xcr0 now */
2758 if (xcrs.xcrs[i].xcr == 0) {
2759 env->xcr0 = xcrs.xcrs[i].value;
2760 break;
2761 }
2762 }
2763 return 0;
2764 }
2765
2766 static int kvm_get_sregs(X86CPU *cpu)
2767 {
2768 CPUX86State *env = &cpu->env;
2769 struct kvm_sregs sregs;
2770 int bit, i, ret;
2771
2772 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
2773 if (ret < 0) {
2774 return ret;
2775 }
2776
2777 /* There can only be one pending IRQ set in the bitmap at a time, so try
2778 to find it and save its number instead (-1 for none). */
2779 env->interrupt_injected = -1;
2780 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2781 if (sregs.interrupt_bitmap[i]) {
2782 bit = ctz64(sregs.interrupt_bitmap[i]);
2783 env->interrupt_injected = i * 64 + bit;
2784 break;
2785 }
2786 }
2787
2788 get_seg(&env->segs[R_CS], &sregs.cs);
2789 get_seg(&env->segs[R_DS], &sregs.ds);
2790 get_seg(&env->segs[R_ES], &sregs.es);
2791 get_seg(&env->segs[R_FS], &sregs.fs);
2792 get_seg(&env->segs[R_GS], &sregs.gs);
2793 get_seg(&env->segs[R_SS], &sregs.ss);
2794
2795 get_seg(&env->tr, &sregs.tr);
2796 get_seg(&env->ldt, &sregs.ldt);
2797
2798 env->idt.limit = sregs.idt.limit;
2799 env->idt.base = sregs.idt.base;
2800 env->gdt.limit = sregs.gdt.limit;
2801 env->gdt.base = sregs.gdt.base;
2802
2803 env->cr[0] = sregs.cr0;
2804 env->cr[2] = sregs.cr2;
2805 env->cr[3] = sregs.cr3;
2806 env->cr[4] = sregs.cr4;
2807
2808 env->efer = sregs.efer;
2809
2810 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2811 x86_update_hflags(env);
2812
2813 return 0;
2814 }
2815
2816 static int kvm_get_msrs(X86CPU *cpu)
2817 {
2818 CPUX86State *env = &cpu->env;
2819 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2820 int ret, i;
2821 uint64_t mtrr_top_bits;
2822
2823 kvm_msr_buf_reset(cpu);
2824
2825 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2826 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2827 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2828 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2829 if (has_msr_star) {
2830 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2831 }
2832 if (has_msr_hsave_pa) {
2833 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2834 }
2835 if (has_msr_tsc_aux) {
2836 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2837 }
2838 if (has_msr_tsc_adjust) {
2839 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2840 }
2841 if (has_msr_tsc_deadline) {
2842 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2843 }
2844 if (has_msr_misc_enable) {
2845 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2846 }
2847 if (has_msr_smbase) {
2848 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2849 }
2850 if (has_msr_smi_count) {
2851 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2852 }
2853 if (has_msr_feature_control) {
2854 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2855 }
2856 if (has_msr_bndcfgs) {
2857 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2858 }
2859 if (has_msr_xss) {
2860 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2861 }
2862 if (has_msr_spec_ctrl) {
2863 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2864 }
2865 if (has_msr_virt_ssbd) {
2866 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2867 }
2868 if (!env->tsc_valid) {
2869 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2870 env->tsc_valid = !runstate_is_running();
2871 }
2872
2873 #ifdef TARGET_X86_64
2874 if (lm_capable_kernel) {
2875 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2876 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2877 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2878 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2879 }
2880 #endif
2881 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2882 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2883 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2884 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2885 }
2886 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2887 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2888 }
2889 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2890 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2891 }
2892 if (has_architectural_pmu_version > 0) {
2893 if (has_architectural_pmu_version > 1) {
2894 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2895 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2896 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2897 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2898 }
2899 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2900 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2901 }
2902 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2903 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2904 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2905 }
2906 }
2907
2908 if (env->mcg_cap) {
2909 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2910 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2911 if (has_msr_mcg_ext_ctl) {
2912 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2913 }
2914 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2915 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2916 }
2917 }
2918
2919 if (has_msr_hv_hypercall) {
2920 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2921 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2922 }
2923 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
2924 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2925 }
2926 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
2927 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2928 }
2929 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
2930 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2931 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2932 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2933 }
2934 if (has_msr_hv_crash) {
2935 int j;
2936
2937 for (j = 0; j < HV_CRASH_PARAMS; j++) {
2938 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2939 }
2940 }
2941 if (has_msr_hv_runtime) {
2942 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2943 }
2944 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2945 uint32_t msr;
2946
2947 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2948 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2949 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2950 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2951 kvm_msr_entry_add(cpu, msr, 0);
2952 }
2953 }
2954 if (has_msr_hv_stimer) {
2955 uint32_t msr;
2956
2957 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2958 msr++) {
2959 kvm_msr_entry_add(cpu, msr, 0);
2960 }
2961 }
2962 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2963 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2964 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2965 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2966 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2967 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2968 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2969 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2970 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2971 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2972 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2973 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2974 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2975 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2976 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2977 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2978 }
2979 }
2980
2981 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2982 int addr_num =
2983 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2984
2985 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2986 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2987 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2988 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2989 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2990 for (i = 0; i < addr_num; i++) {
2991 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2992 }
2993 }
2994
2995 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2996 if (ret < 0) {
2997 return ret;
2998 }
2999
3000 if (ret < cpu->kvm_msr_buf->nmsrs) {
3001 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3002 error_report("error: failed to get MSR 0x%" PRIx32,
3003 (uint32_t)e->index);
3004 }
3005
3006 assert(ret == cpu->kvm_msr_buf->nmsrs);
3007 /*
3008 * MTRR masks: Each mask consists of 5 parts
3009 * a 10..0: must be zero
3010 * b 11 : valid bit
3011 * c n-1.12: actual mask bits
3012 * d 51..n: reserved must be zero
3013 * e 63.52: reserved must be zero
3014 *
3015 * 'n' is the number of physical bits supported by the CPU and is
3016 * apparently always <= 52. We know our 'n' but don't know what
3017 * the destinations 'n' is; it might be smaller, in which case
3018 * it masks (c) on loading. It might be larger, in which case
3019 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3020 * we're migrating to.
3021 */
3022
3023 if (cpu->fill_mtrr_mask) {
3024 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3025 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3026 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3027 } else {
3028 mtrr_top_bits = 0;
3029 }
3030
3031 for (i = 0; i < ret; i++) {
3032 uint32_t index = msrs[i].index;
3033 switch (index) {
3034 case MSR_IA32_SYSENTER_CS:
3035 env->sysenter_cs = msrs[i].data;
3036 break;
3037 case MSR_IA32_SYSENTER_ESP:
3038 env->sysenter_esp = msrs[i].data;
3039 break;
3040 case MSR_IA32_SYSENTER_EIP:
3041 env->sysenter_eip = msrs[i].data;
3042 break;
3043 case MSR_PAT:
3044 env->pat = msrs[i].data;
3045 break;
3046 case MSR_STAR:
3047 env->star = msrs[i].data;
3048 break;
3049 #ifdef TARGET_X86_64
3050 case MSR_CSTAR:
3051 env->cstar = msrs[i].data;
3052 break;
3053 case MSR_KERNELGSBASE:
3054 env->kernelgsbase = msrs[i].data;
3055 break;
3056 case MSR_FMASK:
3057 env->fmask = msrs[i].data;
3058 break;
3059 case MSR_LSTAR:
3060 env->lstar = msrs[i].data;
3061 break;
3062 #endif
3063 case MSR_IA32_TSC:
3064 env->tsc = msrs[i].data;
3065 break;
3066 case MSR_TSC_AUX:
3067 env->tsc_aux = msrs[i].data;
3068 break;
3069 case MSR_TSC_ADJUST:
3070 env->tsc_adjust = msrs[i].data;
3071 break;
3072 case MSR_IA32_TSCDEADLINE:
3073 env->tsc_deadline = msrs[i].data;
3074 break;
3075 case MSR_VM_HSAVE_PA:
3076 env->vm_hsave = msrs[i].data;
3077 break;
3078 case MSR_KVM_SYSTEM_TIME:
3079 env->system_time_msr = msrs[i].data;
3080 break;
3081 case MSR_KVM_WALL_CLOCK:
3082 env->wall_clock_msr = msrs[i].data;
3083 break;
3084 case MSR_MCG_STATUS:
3085 env->mcg_status = msrs[i].data;
3086 break;
3087 case MSR_MCG_CTL:
3088 env->mcg_ctl = msrs[i].data;
3089 break;
3090 case MSR_MCG_EXT_CTL:
3091 env->mcg_ext_ctl = msrs[i].data;
3092 break;
3093 case MSR_IA32_MISC_ENABLE:
3094 env->msr_ia32_misc_enable = msrs[i].data;
3095 break;
3096 case MSR_IA32_SMBASE:
3097 env->smbase = msrs[i].data;
3098 break;
3099 case MSR_SMI_COUNT:
3100 env->msr_smi_count = msrs[i].data;
3101 break;
3102 case MSR_IA32_FEATURE_CONTROL:
3103 env->msr_ia32_feature_control = msrs[i].data;
3104 break;
3105 case MSR_IA32_BNDCFGS:
3106 env->msr_bndcfgs = msrs[i].data;
3107 break;
3108 case MSR_IA32_XSS:
3109 env->xss = msrs[i].data;
3110 break;
3111 default:
3112 if (msrs[i].index >= MSR_MC0_CTL &&
3113 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3114 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
3115 }
3116 break;
3117 case MSR_KVM_ASYNC_PF_EN:
3118 env->async_pf_en_msr = msrs[i].data;
3119 break;
3120 case MSR_KVM_PV_EOI_EN:
3121 env->pv_eoi_en_msr = msrs[i].data;
3122 break;
3123 case MSR_KVM_STEAL_TIME:
3124 env->steal_time_msr = msrs[i].data;
3125 break;
3126 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3127 env->msr_fixed_ctr_ctrl = msrs[i].data;
3128 break;
3129 case MSR_CORE_PERF_GLOBAL_CTRL:
3130 env->msr_global_ctrl = msrs[i].data;
3131 break;
3132 case MSR_CORE_PERF_GLOBAL_STATUS:
3133 env->msr_global_status = msrs[i].data;
3134 break;
3135 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3136 env->msr_global_ovf_ctrl = msrs[i].data;
3137 break;
3138 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3139 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3140 break;
3141 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3142 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3143 break;
3144 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3145 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3146 break;
3147 case HV_X64_MSR_HYPERCALL:
3148 env->msr_hv_hypercall = msrs[i].data;
3149 break;
3150 case HV_X64_MSR_GUEST_OS_ID:
3151 env->msr_hv_guest_os_id = msrs[i].data;
3152 break;
3153 case HV_X64_MSR_APIC_ASSIST_PAGE:
3154 env->msr_hv_vapic = msrs[i].data;
3155 break;
3156 case HV_X64_MSR_REFERENCE_TSC:
3157 env->msr_hv_tsc = msrs[i].data;
3158 break;
3159 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3160 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3161 break;
3162 case HV_X64_MSR_VP_RUNTIME:
3163 env->msr_hv_runtime = msrs[i].data;
3164 break;
3165 case HV_X64_MSR_SCONTROL:
3166 env->msr_hv_synic_control = msrs[i].data;
3167 break;
3168 case HV_X64_MSR_SIEFP:
3169 env->msr_hv_synic_evt_page = msrs[i].data;
3170 break;
3171 case HV_X64_MSR_SIMP:
3172 env->msr_hv_synic_msg_page = msrs[i].data;
3173 break;
3174 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3175 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
3176 break;
3177 case HV_X64_MSR_STIMER0_CONFIG:
3178 case HV_X64_MSR_STIMER1_CONFIG:
3179 case HV_X64_MSR_STIMER2_CONFIG:
3180 case HV_X64_MSR_STIMER3_CONFIG:
3181 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3182 msrs[i].data;
3183 break;
3184 case HV_X64_MSR_STIMER0_COUNT:
3185 case HV_X64_MSR_STIMER1_COUNT:
3186 case HV_X64_MSR_STIMER2_COUNT:
3187 case HV_X64_MSR_STIMER3_COUNT:
3188 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3189 msrs[i].data;
3190 break;
3191 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3192 env->msr_hv_reenlightenment_control = msrs[i].data;
3193 break;
3194 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3195 env->msr_hv_tsc_emulation_control = msrs[i].data;
3196 break;
3197 case HV_X64_MSR_TSC_EMULATION_STATUS:
3198 env->msr_hv_tsc_emulation_status = msrs[i].data;
3199 break;
3200 case MSR_MTRRdefType:
3201 env->mtrr_deftype = msrs[i].data;
3202 break;
3203 case MSR_MTRRfix64K_00000:
3204 env->mtrr_fixed[0] = msrs[i].data;
3205 break;
3206 case MSR_MTRRfix16K_80000:
3207 env->mtrr_fixed[1] = msrs[i].data;
3208 break;
3209 case MSR_MTRRfix16K_A0000:
3210 env->mtrr_fixed[2] = msrs[i].data;
3211 break;
3212 case MSR_MTRRfix4K_C0000:
3213 env->mtrr_fixed[3] = msrs[i].data;
3214 break;
3215 case MSR_MTRRfix4K_C8000:
3216 env->mtrr_fixed[4] = msrs[i].data;
3217 break;
3218 case MSR_MTRRfix4K_D0000:
3219 env->mtrr_fixed[5] = msrs[i].data;
3220 break;
3221 case MSR_MTRRfix4K_D8000:
3222 env->mtrr_fixed[6] = msrs[i].data;
3223 break;
3224 case MSR_MTRRfix4K_E0000:
3225 env->mtrr_fixed[7] = msrs[i].data;
3226 break;
3227 case MSR_MTRRfix4K_E8000:
3228 env->mtrr_fixed[8] = msrs[i].data;
3229 break;
3230 case MSR_MTRRfix4K_F0000:
3231 env->mtrr_fixed[9] = msrs[i].data;
3232 break;
3233 case MSR_MTRRfix4K_F8000:
3234 env->mtrr_fixed[10] = msrs[i].data;
3235 break;
3236 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3237 if (index & 1) {
3238 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3239 mtrr_top_bits;
3240 } else {
3241 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3242 }
3243 break;
3244 case MSR_IA32_SPEC_CTRL:
3245 env->spec_ctrl = msrs[i].data;
3246 break;
3247 case MSR_VIRT_SSBD:
3248 env->virt_ssbd = msrs[i].data;
3249 break;
3250 case MSR_IA32_RTIT_CTL:
3251 env->msr_rtit_ctrl = msrs[i].data;
3252 break;
3253 case MSR_IA32_RTIT_STATUS:
3254 env->msr_rtit_status = msrs[i].data;
3255 break;
3256 case MSR_IA32_RTIT_OUTPUT_BASE:
3257 env->msr_rtit_output_base = msrs[i].data;
3258 break;
3259 case MSR_IA32_RTIT_OUTPUT_MASK:
3260 env->msr_rtit_output_mask = msrs[i].data;
3261 break;
3262 case MSR_IA32_RTIT_CR3_MATCH:
3263 env->msr_rtit_cr3_match = msrs[i].data;
3264 break;
3265 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3266 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3267 break;
3268 }
3269 }
3270
3271 return 0;
3272 }
3273
3274 static int kvm_put_mp_state(X86CPU *cpu)
3275 {
3276 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
3277
3278 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
3279 }
3280
3281 static int kvm_get_mp_state(X86CPU *cpu)
3282 {
3283 CPUState *cs = CPU(cpu);
3284 CPUX86State *env = &cpu->env;
3285 struct kvm_mp_state mp_state;
3286 int ret;
3287
3288 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
3289 if (ret < 0) {
3290 return ret;
3291 }
3292 env->mp_state = mp_state.mp_state;
3293 if (kvm_irqchip_in_kernel()) {
3294 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
3295 }
3296 return 0;
3297 }
3298
3299 static int kvm_get_apic(X86CPU *cpu)
3300 {
3301 DeviceState *apic = cpu->apic_state;
3302 struct kvm_lapic_state kapic;
3303 int ret;
3304
3305 if (apic && kvm_irqchip_in_kernel()) {
3306 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
3307 if (ret < 0) {
3308 return ret;
3309 }
3310
3311 kvm_get_apic_state(apic, &kapic);
3312 }
3313 return 0;
3314 }
3315
3316 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
3317 {
3318 CPUState *cs = CPU(cpu);
3319 CPUX86State *env = &cpu->env;
3320 struct kvm_vcpu_events events = {};
3321
3322 if (!kvm_has_vcpu_events()) {
3323 return 0;
3324 }
3325
3326 events.flags = 0;
3327
3328 if (has_exception_payload) {
3329 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3330 events.exception.pending = env->exception_pending;
3331 events.exception_has_payload = env->exception_has_payload;
3332 events.exception_payload = env->exception_payload;
3333 }
3334 events.exception.nr = env->exception_nr;
3335 events.exception.injected = env->exception_injected;
3336 events.exception.has_error_code = env->has_error_code;
3337 events.exception.error_code = env->error_code;
3338
3339 events.interrupt.injected = (env->interrupt_injected >= 0);
3340 events.interrupt.nr = env->interrupt_injected;
3341 events.interrupt.soft = env->soft_interrupt;
3342
3343 events.nmi.injected = env->nmi_injected;
3344 events.nmi.pending = env->nmi_pending;
3345 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3346
3347 events.sipi_vector = env->sipi_vector;
3348
3349 if (has_msr_smbase) {
3350 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3351 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3352 if (kvm_irqchip_in_kernel()) {
3353 /* As soon as these are moved to the kernel, remove them
3354 * from cs->interrupt_request.
3355 */
3356 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3357 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3358 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3359 } else {
3360 /* Keep these in cs->interrupt_request. */
3361 events.smi.pending = 0;
3362 events.smi.latched_init = 0;
3363 }
3364 /* Stop SMI delivery on old machine types to avoid a reboot
3365 * on an inward migration of an old VM.
3366 */
3367 if (!cpu->kvm_no_smi_migration) {
3368 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3369 }
3370 }
3371
3372 if (level >= KVM_PUT_RESET_STATE) {
3373 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3374 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3375 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3376 }
3377 }
3378
3379 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
3380 }
3381
3382 static int kvm_get_vcpu_events(X86CPU *cpu)
3383 {
3384 CPUX86State *env = &cpu->env;
3385 struct kvm_vcpu_events events;
3386 int ret;
3387
3388 if (!kvm_has_vcpu_events()) {
3389 return 0;
3390 }
3391
3392 memset(&events, 0, sizeof(events));
3393 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
3394 if (ret < 0) {
3395 return ret;
3396 }
3397
3398 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3399 env->exception_pending = events.exception.pending;
3400 env->exception_has_payload = events.exception_has_payload;
3401 env->exception_payload = events.exception_payload;
3402 } else {
3403 env->exception_pending = 0;
3404 env->exception_has_payload = false;
3405 }
3406 env->exception_injected = events.exception.injected;
3407 env->exception_nr =
3408 (env->exception_pending || env->exception_injected) ?
3409 events.exception.nr : -1;
3410 env->has_error_code = events.exception.has_error_code;
3411 env->error_code = events.exception.error_code;
3412
3413 env->interrupt_injected =
3414 events.interrupt.injected ? events.interrupt.nr : -1;
3415 env->soft_interrupt = events.interrupt.soft;
3416
3417 env->nmi_injected = events.nmi.injected;
3418 env->nmi_pending = events.nmi.pending;
3419 if (events.nmi.masked) {
3420 env->hflags2 |= HF2_NMI_MASK;
3421 } else {
3422 env->hflags2 &= ~HF2_NMI_MASK;
3423 }
3424
3425 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3426 if (events.smi.smm) {
3427 env->hflags |= HF_SMM_MASK;
3428 } else {
3429 env->hflags &= ~HF_SMM_MASK;
3430 }
3431 if (events.smi.pending) {
3432 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3433 } else {
3434 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3435 }
3436 if (events.smi.smm_inside_nmi) {
3437 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3438 } else {
3439 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3440 }
3441 if (events.smi.latched_init) {
3442 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3443 } else {
3444 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3445 }
3446 }
3447
3448 env->sipi_vector = events.sipi_vector;
3449
3450 return 0;
3451 }
3452
3453 static int kvm_guest_debug_workarounds(X86CPU *cpu)
3454 {
3455 CPUState *cs = CPU(cpu);
3456 CPUX86State *env = &cpu->env;
3457 int ret = 0;
3458 unsigned long reinject_trap = 0;
3459
3460 if (!kvm_has_vcpu_events()) {
3461 if (env->exception_nr == EXCP01_DB) {
3462 reinject_trap = KVM_GUESTDBG_INJECT_DB;
3463 } else if (env->exception_injected == EXCP03_INT3) {
3464 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3465 }
3466 kvm_reset_exception(env);
3467 }
3468
3469 /*
3470 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3471 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3472 * by updating the debug state once again if single-stepping is on.
3473 * Another reason to call kvm_update_guest_debug here is a pending debug
3474 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3475 * reinject them via SET_GUEST_DEBUG.
3476 */
3477 if (reinject_trap ||
3478 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
3479 ret = kvm_update_guest_debug(cs, reinject_trap);
3480 }
3481 return ret;
3482 }
3483
3484 static int kvm_put_debugregs(X86CPU *cpu)
3485 {
3486 CPUX86State *env = &cpu->env;
3487 struct kvm_debugregs dbgregs;
3488 int i;
3489
3490 if (!kvm_has_debugregs()) {
3491 return 0;
3492 }
3493
3494 for (i = 0; i < 4; i++) {
3495 dbgregs.db[i] = env->dr[i];
3496 }
3497 dbgregs.dr6 = env->dr[6];
3498 dbgregs.dr7 = env->dr[7];
3499 dbgregs.flags = 0;
3500
3501 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
3502 }
3503
3504 static int kvm_get_debugregs(X86CPU *cpu)
3505 {
3506 CPUX86State *env = &cpu->env;
3507 struct kvm_debugregs dbgregs;
3508 int i, ret;
3509
3510 if (!kvm_has_debugregs()) {
3511 return 0;
3512 }
3513
3514 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
3515 if (ret < 0) {
3516 return ret;
3517 }
3518 for (i = 0; i < 4; i++) {
3519 env->dr[i] = dbgregs.db[i];
3520 }
3521 env->dr[4] = env->dr[6] = dbgregs.dr6;
3522 env->dr[5] = env->dr[7] = dbgregs.dr7;
3523
3524 return 0;
3525 }
3526
3527 static int kvm_put_nested_state(X86CPU *cpu)
3528 {
3529 CPUX86State *env = &cpu->env;
3530 int max_nested_state_len = kvm_max_nested_state_length();
3531
3532 if (max_nested_state_len <= 0) {
3533 return 0;
3534 }
3535
3536 assert(env->nested_state->size <= max_nested_state_len);
3537 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3538 }
3539
3540 static int kvm_get_nested_state(X86CPU *cpu)
3541 {
3542 CPUX86State *env = &cpu->env;
3543 int max_nested_state_len = kvm_max_nested_state_length();
3544 int ret;
3545
3546 if (max_nested_state_len <= 0) {
3547 return 0;
3548 }
3549
3550 /*
3551 * It is possible that migration restored a smaller size into
3552 * nested_state->hdr.size than what our kernel support.
3553 * We preserve migration origin nested_state->hdr.size for
3554 * call to KVM_SET_NESTED_STATE but wish that our next call
3555 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3556 */
3557 env->nested_state->size = max_nested_state_len;
3558
3559 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
3560 if (ret < 0) {
3561 return ret;
3562 }
3563
3564 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
3565 env->hflags |= HF_GUEST_MASK;
3566 } else {
3567 env->hflags &= ~HF_GUEST_MASK;
3568 }
3569
3570 return ret;
3571 }
3572
3573 int kvm_arch_put_registers(CPUState *cpu, int level)
3574 {
3575 X86CPU *x86_cpu = X86_CPU(cpu);
3576 int ret;
3577
3578 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
3579
3580 ret = kvm_put_nested_state(x86_cpu);
3581 if (ret < 0) {
3582 return ret;
3583 }
3584
3585 if (level >= KVM_PUT_RESET_STATE) {
3586 ret = kvm_put_msr_feature_control(x86_cpu);
3587 if (ret < 0) {
3588 return ret;
3589 }
3590 }
3591
3592 if (level == KVM_PUT_FULL_STATE) {
3593 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3594 * because TSC frequency mismatch shouldn't abort migration,
3595 * unless the user explicitly asked for a more strict TSC
3596 * setting (e.g. using an explicit "tsc-freq" option).
3597 */
3598 kvm_arch_set_tsc_khz(cpu);
3599 }
3600
3601 ret = kvm_getput_regs(x86_cpu, 1);
3602 if (ret < 0) {
3603 return ret;
3604 }
3605 ret = kvm_put_xsave(x86_cpu);
3606 if (ret < 0) {
3607 return ret;
3608 }
3609 ret = kvm_put_xcrs(x86_cpu);
3610 if (ret < 0) {
3611 return ret;
3612 }
3613 ret = kvm_put_sregs(x86_cpu);
3614 if (ret < 0) {
3615 return ret;
3616 }
3617 /* must be before kvm_put_msrs */
3618 ret = kvm_inject_mce_oldstyle(x86_cpu);
3619 if (ret < 0) {
3620 return ret;
3621 }
3622 ret = kvm_put_msrs(x86_cpu, level);
3623 if (ret < 0) {
3624 return ret;
3625 }
3626 ret = kvm_put_vcpu_events(x86_cpu, level);
3627 if (ret < 0) {
3628 return ret;
3629 }
3630 if (level >= KVM_PUT_RESET_STATE) {
3631 ret = kvm_put_mp_state(x86_cpu);
3632 if (ret < 0) {
3633 return ret;
3634 }
3635 }
3636
3637 ret = kvm_put_tscdeadline_msr(x86_cpu);
3638 if (ret < 0) {
3639 return ret;
3640 }
3641 ret = kvm_put_debugregs(x86_cpu);
3642 if (ret < 0) {
3643 return ret;
3644 }
3645 /* must be last */
3646 ret = kvm_guest_debug_workarounds(x86_cpu);
3647 if (ret < 0) {
3648 return ret;
3649 }
3650 return 0;
3651 }
3652
3653 int kvm_arch_get_registers(CPUState *cs)
3654 {
3655 X86CPU *cpu = X86_CPU(cs);
3656 int ret;
3657
3658 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
3659
3660 ret = kvm_get_vcpu_events(cpu);
3661 if (ret < 0) {
3662 goto out;
3663 }
3664 /*
3665 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3666 * KVM_GET_REGS and KVM_GET_SREGS.
3667 */
3668 ret = kvm_get_mp_state(cpu);
3669 if (ret < 0) {
3670 goto out;
3671 }
3672 ret = kvm_getput_regs(cpu, 0);
3673 if (ret < 0) {
3674 goto out;
3675 }
3676 ret = kvm_get_xsave(cpu);
3677 if (ret < 0) {
3678 goto out;
3679 }
3680 ret = kvm_get_xcrs(cpu);
3681 if (ret < 0) {
3682 goto out;
3683 }
3684 ret = kvm_get_sregs(cpu);
3685 if (ret < 0) {
3686 goto out;
3687 }
3688 ret = kvm_get_msrs(cpu);
3689 if (ret < 0) {
3690 goto out;
3691 }
3692 ret = kvm_get_apic(cpu);
3693 if (ret < 0) {
3694 goto out;
3695 }
3696 ret = kvm_get_debugregs(cpu);
3697 if (ret < 0) {
3698 goto out;
3699 }
3700 ret = kvm_get_nested_state(cpu);
3701 if (ret < 0) {
3702 goto out;
3703 }
3704 ret = 0;
3705 out:
3706 cpu_sync_bndcs_hflags(&cpu->env);
3707 return ret;
3708 }
3709
3710 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
3711 {
3712 X86CPU *x86_cpu = X86_CPU(cpu);
3713 CPUX86State *env = &x86_cpu->env;
3714 int ret;
3715
3716 /* Inject NMI */
3717 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3718 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3719 qemu_mutex_lock_iothread();
3720 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3721 qemu_mutex_unlock_iothread();
3722 DPRINTF("injected NMI\n");
3723 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3724 if (ret < 0) {
3725 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3726 strerror(-ret));
3727 }
3728 }
3729 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3730 qemu_mutex_lock_iothread();
3731 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3732 qemu_mutex_unlock_iothread();
3733 DPRINTF("injected SMI\n");
3734 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3735 if (ret < 0) {
3736 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3737 strerror(-ret));
3738 }
3739 }
3740 }
3741
3742 if (!kvm_pic_in_kernel()) {
3743 qemu_mutex_lock_iothread();
3744 }
3745
3746 /* Force the VCPU out of its inner loop to process any INIT requests
3747 * or (for userspace APIC, but it is cheap to combine the checks here)
3748 * pending TPR access reports.
3749 */
3750 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
3751 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3752 !(env->hflags & HF_SMM_MASK)) {
3753 cpu->exit_request = 1;
3754 }
3755 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3756 cpu->exit_request = 1;
3757 }
3758 }
3759
3760 if (!kvm_pic_in_kernel()) {
3761 /* Try to inject an interrupt if the guest can accept it */
3762 if (run->ready_for_interrupt_injection &&
3763 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
3764 (env->eflags & IF_MASK)) {
3765 int irq;
3766
3767 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
3768 irq = cpu_get_pic_interrupt(env);
3769 if (irq >= 0) {
3770 struct kvm_interrupt intr;
3771
3772 intr.irq = irq;
3773 DPRINTF("injected interrupt %d\n", irq);
3774 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
3775 if (ret < 0) {
3776 fprintf(stderr,
3777 "KVM: injection failed, interrupt lost (%s)\n",
3778 strerror(-ret));
3779 }
3780 }
3781 }
3782
3783 /* If we have an interrupt but the guest is not ready to receive an
3784 * interrupt, request an interrupt window exit. This will
3785 * cause a return to userspace as soon as the guest is ready to
3786 * receive interrupts. */
3787 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
3788 run->request_interrupt_window = 1;
3789 } else {
3790 run->request_interrupt_window = 0;
3791 }
3792
3793 DPRINTF("setting tpr\n");
3794 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
3795
3796 qemu_mutex_unlock_iothread();
3797 }
3798 }
3799
3800 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
3801 {
3802 X86CPU *x86_cpu = X86_CPU(cpu);
3803 CPUX86State *env = &x86_cpu->env;
3804
3805 if (run->flags & KVM_RUN_X86_SMM) {
3806 env->hflags |= HF_SMM_MASK;
3807 } else {
3808 env->hflags &= ~HF_SMM_MASK;
3809 }
3810 if (run->if_flag) {
3811 env->eflags |= IF_MASK;
3812 } else {
3813 env->eflags &= ~IF_MASK;
3814 }
3815
3816 /* We need to protect the apic state against concurrent accesses from
3817 * different threads in case the userspace irqchip is used. */
3818 if (!kvm_irqchip_in_kernel()) {
3819 qemu_mutex_lock_iothread();
3820 }
3821 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3822 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
3823 if (!kvm_irqchip_in_kernel()) {
3824 qemu_mutex_unlock_iothread();
3825 }
3826 return cpu_get_mem_attrs(env);
3827 }
3828
3829 int kvm_arch_process_async_events(CPUState *cs)
3830 {
3831 X86CPU *cpu = X86_CPU(cs);
3832 CPUX86State *env = &cpu->env;
3833
3834 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
3835 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3836 assert(env->mcg_cap);
3837
3838 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
3839
3840 kvm_cpu_synchronize_state(cs);
3841
3842 if (env->exception_nr == EXCP08_DBLE) {
3843 /* this means triple fault */
3844 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
3845 cs->exit_request = 1;
3846 return 0;
3847 }
3848 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
3849 env->has_error_code = 0;
3850
3851 cs->halted = 0;
3852 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3853 env->mp_state = KVM_MP_STATE_RUNNABLE;
3854 }
3855 }
3856
3857 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3858 !(env->hflags & HF_SMM_MASK)) {
3859 kvm_cpu_synchronize_state(cs);
3860 do_cpu_init(cpu);
3861 }
3862
3863 if (kvm_irqchip_in_kernel()) {
3864 return 0;
3865 }
3866
3867 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3868 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
3869 apic_poll_irq(cpu->apic_state);
3870 }
3871 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3872 (env->eflags & IF_MASK)) ||
3873 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3874 cs->halted = 0;
3875 }
3876 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
3877 kvm_cpu_synchronize_state(cs);
3878 do_cpu_sipi(cpu);
3879 }
3880 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3881 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
3882 kvm_cpu_synchronize_state(cs);
3883 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
3884 env->tpr_access_type);
3885 }
3886
3887 return cs->halted;
3888 }
3889
3890 static int kvm_handle_halt(X86CPU *cpu)
3891 {
3892 CPUState *cs = CPU(cpu);
3893 CPUX86State *env = &cpu->env;
3894
3895 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3896 (env->eflags & IF_MASK)) &&
3897 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3898 cs->halted = 1;
3899 return EXCP_HLT;
3900 }
3901
3902 return 0;
3903 }
3904
3905 static int kvm_handle_tpr_access(X86CPU *cpu)
3906 {
3907 CPUState *cs = CPU(cpu);
3908 struct kvm_run *run = cs->kvm_run;
3909
3910 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3911 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3912 : TPR_ACCESS_READ);
3913 return 1;
3914 }
3915
3916 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3917 {
3918 static const uint8_t int3 = 0xcc;
3919
3920 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3921 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3922 return -EINVAL;
3923 }
3924 return 0;
3925 }
3926
3927 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3928 {
3929 uint8_t int3;
3930
3931 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3932 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3933 return -EINVAL;
3934 }
3935 return 0;
3936 }
3937
3938 static struct {
3939 target_ulong addr;
3940 int len;
3941 int type;
3942 } hw_breakpoint[4];
3943
3944 static int nb_hw_breakpoint;
3945
3946 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3947 {
3948 int n;
3949
3950 for (n = 0; n < nb_hw_breakpoint; n++) {
3951 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3952 (hw_breakpoint[n].len == len || len == -1)) {
3953 return n;
3954 }
3955 }
3956 return -1;
3957 }
3958
3959 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3960 target_ulong len, int type)
3961 {
3962 switch (type) {
3963 case GDB_BREAKPOINT_HW:
3964 len = 1;
3965 break;
3966 case GDB_WATCHPOINT_WRITE:
3967 case GDB_WATCHPOINT_ACCESS:
3968 switch (len) {
3969 case 1:
3970 break;
3971 case 2:
3972 case 4:
3973 case 8:
3974 if (addr & (len - 1)) {
3975 return -EINVAL;
3976 }
3977 break;
3978 default:
3979 return -EINVAL;
3980 }
3981 break;
3982 default:
3983 return -ENOSYS;
3984 }
3985
3986 if (nb_hw_breakpoint == 4) {
3987 return -ENOBUFS;
3988 }
3989 if (find_hw_breakpoint(addr, len, type) >= 0) {
3990 return -EEXIST;
3991 }
3992 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3993 hw_breakpoint[nb_hw_breakpoint].len = len;
3994 hw_breakpoint[nb_hw_breakpoint].type = type;
3995 nb_hw_breakpoint++;
3996
3997 return 0;
3998 }
3999
4000 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4001 target_ulong len, int type)
4002 {
4003 int n;
4004
4005 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
4006 if (n < 0) {
4007 return -ENOENT;
4008 }
4009 nb_hw_breakpoint--;
4010 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4011
4012 return 0;
4013 }
4014
4015 void kvm_arch_remove_all_hw_breakpoints(void)
4016 {
4017 nb_hw_breakpoint = 0;
4018 }
4019
4020 static CPUWatchpoint hw_watchpoint;
4021
4022 static int kvm_handle_debug(X86CPU *cpu,
4023 struct kvm_debug_exit_arch *arch_info)
4024 {
4025 CPUState *cs = CPU(cpu);
4026 CPUX86State *env = &cpu->env;
4027 int ret = 0;
4028 int n;
4029
4030 if (arch_info->exception == EXCP01_DB) {
4031 if (arch_info->dr6 & DR6_BS) {
4032 if (cs->singlestep_enabled) {
4033 ret = EXCP_DEBUG;
4034 }
4035 } else {
4036 for (n = 0; n < 4; n++) {
4037 if (arch_info->dr6 & (1 << n)) {
4038 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4039 case 0x0:
4040 ret = EXCP_DEBUG;
4041 break;
4042 case 0x1:
4043 ret = EXCP_DEBUG;
4044 cs->watchpoint_hit = &hw_watchpoint;
4045 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4046 hw_watchpoint.flags = BP_MEM_WRITE;
4047 break;
4048 case 0x3:
4049 ret = EXCP_DEBUG;
4050 cs->watchpoint_hit = &hw_watchpoint;
4051 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4052 hw_watchpoint.flags = BP_MEM_ACCESS;
4053 break;
4054 }
4055 }
4056 }
4057 }
4058 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
4059 ret = EXCP_DEBUG;
4060 }
4061 if (ret == 0) {
4062 cpu_synchronize_state(cs);
4063 assert(env->exception_nr == -1);
4064
4065 /* pass to guest */
4066 kvm_queue_exception(env, arch_info->exception,
4067 arch_info->exception == EXCP01_DB,
4068 arch_info->dr6);
4069 env->has_error_code = 0;
4070 }
4071
4072 return ret;
4073 }
4074
4075 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
4076 {
4077 const uint8_t type_code[] = {
4078 [GDB_BREAKPOINT_HW] = 0x0,
4079 [GDB_WATCHPOINT_WRITE] = 0x1,
4080 [GDB_WATCHPOINT_ACCESS] = 0x3
4081 };
4082 const uint8_t len_code[] = {
4083 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4084 };
4085 int n;
4086
4087 if (kvm_sw_breakpoints_active(cpu)) {
4088 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
4089 }
4090 if (nb_hw_breakpoint > 0) {
4091 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4092 dbg->arch.debugreg[7] = 0x0600;
4093 for (n = 0; n < nb_hw_breakpoint; n++) {
4094 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4095 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4096 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
4097 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
4098 }
4099 }
4100 }
4101
4102 static bool host_supports_vmx(void)
4103 {
4104 uint32_t ecx, unused;
4105
4106 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4107 return ecx & CPUID_EXT_VMX;
4108 }
4109
4110 #define VMX_INVALID_GUEST_STATE 0x80000021
4111
4112 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
4113 {
4114 X86CPU *cpu = X86_CPU(cs);
4115 uint64_t code;
4116 int ret;
4117
4118 switch (run->exit_reason) {
4119 case KVM_EXIT_HLT:
4120 DPRINTF("handle_hlt\n");
4121 qemu_mutex_lock_iothread();
4122 ret = kvm_handle_halt(cpu);
4123 qemu_mutex_unlock_iothread();
4124 break;
4125 case KVM_EXIT_SET_TPR:
4126 ret = 0;
4127 break;
4128 case KVM_EXIT_TPR_ACCESS:
4129 qemu_mutex_lock_iothread();
4130 ret = kvm_handle_tpr_access(cpu);
4131 qemu_mutex_unlock_iothread();
4132 break;
4133 case KVM_EXIT_FAIL_ENTRY:
4134 code = run->fail_entry.hardware_entry_failure_reason;
4135 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4136 code);
4137 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4138 fprintf(stderr,
4139 "\nIf you're running a guest on an Intel machine without "
4140 "unrestricted mode\n"
4141 "support, the failure can be most likely due to the guest "
4142 "entering an invalid\n"
4143 "state for Intel VT. For example, the guest maybe running "
4144 "in big real mode\n"
4145 "which is not supported on less recent Intel processors."
4146 "\n\n");
4147 }
4148 ret = -1;
4149 break;
4150 case KVM_EXIT_EXCEPTION:
4151 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4152 run->ex.exception, run->ex.error_code);
4153 ret = -1;
4154 break;
4155 case KVM_EXIT_DEBUG:
4156 DPRINTF("kvm_exit_debug\n");
4157 qemu_mutex_lock_iothread();
4158 ret = kvm_handle_debug(cpu, &run->debug.arch);
4159 qemu_mutex_unlock_iothread();
4160 break;
4161 case KVM_EXIT_HYPERV:
4162 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4163 break;
4164 case KVM_EXIT_IOAPIC_EOI:
4165 ioapic_eoi_broadcast(run->eoi.vector);
4166 ret = 0;
4167 break;
4168 default:
4169 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4170 ret = -1;
4171 break;
4172 }
4173
4174 return ret;
4175 }
4176
4177 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4178 {
4179 X86CPU *cpu = X86_CPU(cs);
4180 CPUX86State *env = &cpu->env;
4181
4182 kvm_cpu_synchronize_state(cs);
4183 return !(env->cr[0] & CR0_PE_MASK) ||
4184 ((env->segs[R_CS].selector & 3) != 3);
4185 }
4186
4187 void kvm_arch_init_irq_routing(KVMState *s)
4188 {
4189 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
4190 /* If kernel can't do irq routing, interrupt source
4191 * override 0->2 cannot be set up as required by HPET.
4192 * So we have to disable it.
4193 */
4194 no_hpet = 1;
4195 }
4196 /* We know at this point that we're using the in-kernel
4197 * irqchip, so we can use irqfds, and on x86 we know
4198 * we can use msi via irqfd and GSI routing.
4199 */
4200 kvm_msi_via_irqfd_allowed = true;
4201 kvm_gsi_routing_allowed = true;
4202
4203 if (kvm_irqchip_is_split()) {
4204 int i;
4205
4206 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4207 MSI routes for signaling interrupts to the local apics. */
4208 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
4209 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
4210 error_report("Could not enable split IRQ mode.");
4211 exit(1);
4212 }
4213 }
4214 }
4215 }
4216
4217 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
4218 {
4219 int ret;
4220 if (machine_kernel_irqchip_split(ms)) {
4221 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4222 if (ret) {
4223 error_report("Could not enable split irqchip mode: %s",
4224 strerror(-ret));
4225 exit(1);
4226 } else {
4227 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4228 kvm_split_irqchip = true;
4229 return 1;
4230 }
4231 } else {
4232 return 0;
4233 }
4234 }
4235
4236 /* Classic KVM device assignment interface. Will remain x86 only. */
4237 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
4238 uint32_t flags, uint32_t *dev_id)
4239 {
4240 struct kvm_assigned_pci_dev dev_data = {
4241 .segnr = dev_addr->domain,
4242 .busnr = dev_addr->bus,
4243 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
4244 .flags = flags,
4245 };
4246 int ret;
4247
4248 dev_data.assigned_dev_id =
4249 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
4250
4251 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
4252 if (ret < 0) {
4253 return ret;
4254 }
4255
4256 *dev_id = dev_data.assigned_dev_id;
4257
4258 return 0;
4259 }
4260
4261 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
4262 {
4263 struct kvm_assigned_pci_dev dev_data = {
4264 .assigned_dev_id = dev_id,
4265 };
4266
4267 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
4268 }
4269
4270 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
4271 uint32_t irq_type, uint32_t guest_irq)
4272 {
4273 struct kvm_assigned_irq assigned_irq = {
4274 .assigned_dev_id = dev_id,
4275 .guest_irq = guest_irq,
4276 .flags = irq_type,
4277 };
4278
4279 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
4280 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
4281 } else {
4282 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
4283 }
4284 }
4285
4286 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
4287 uint32_t guest_irq)
4288 {
4289 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
4290 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
4291
4292 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
4293 }
4294
4295 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
4296 {
4297 struct kvm_assigned_pci_dev dev_data = {
4298 .assigned_dev_id = dev_id,
4299 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
4300 };
4301
4302 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
4303 }
4304
4305 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
4306 uint32_t type)
4307 {
4308 struct kvm_assigned_irq assigned_irq = {
4309 .assigned_dev_id = dev_id,
4310 .flags = type,
4311 };
4312
4313 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
4314 }
4315
4316 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
4317 {
4318 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
4319 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
4320 }
4321
4322 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
4323 {
4324 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
4325 KVM_DEV_IRQ_GUEST_MSI, virq);
4326 }
4327
4328 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
4329 {
4330 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
4331 KVM_DEV_IRQ_HOST_MSI);
4332 }
4333
4334 bool kvm_device_msix_supported(KVMState *s)
4335 {
4336 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4337 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4338 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
4339 }
4340
4341 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
4342 uint32_t nr_vectors)
4343 {
4344 struct kvm_assigned_msix_nr msix_nr = {
4345 .assigned_dev_id = dev_id,
4346 .entry_nr = nr_vectors,
4347 };
4348
4349 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
4350 }
4351
4352 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
4353 int virq)
4354 {
4355 struct kvm_assigned_msix_entry msix_entry = {
4356 .assigned_dev_id = dev_id,
4357 .gsi = virq,
4358 .entry = vector,
4359 };
4360
4361 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
4362 }
4363
4364 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
4365 {
4366 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
4367 KVM_DEV_IRQ_GUEST_MSIX, 0);
4368 }
4369
4370 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
4371 {
4372 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
4373 KVM_DEV_IRQ_HOST_MSIX);
4374 }
4375
4376 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
4377 uint64_t address, uint32_t data, PCIDevice *dev)
4378 {
4379 X86IOMMUState *iommu = x86_iommu_get_default();
4380
4381 if (iommu) {
4382 int ret;
4383 MSIMessage src, dst;
4384 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4385
4386 if (!class->int_remap) {
4387 return 0;
4388 }
4389
4390 src.address = route->u.msi.address_hi;
4391 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4392 src.address |= route->u.msi.address_lo;
4393 src.data = route->u.msi.data;
4394
4395 ret = class->int_remap(iommu, &src, &dst, dev ? \
4396 pci_requester_id(dev) : \
4397 X86_IOMMU_SID_INVALID);
4398 if (ret) {
4399 trace_kvm_x86_fixup_msi_error(route->gsi);
4400 return 1;
4401 }
4402
4403 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4404 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4405 route->u.msi.data = dst.data;
4406 }
4407
4408 return 0;
4409 }
4410
4411 typedef struct MSIRouteEntry MSIRouteEntry;
4412
4413 struct MSIRouteEntry {
4414 PCIDevice *dev; /* Device pointer */
4415 int vector; /* MSI/MSIX vector index */
4416 int virq; /* Virtual IRQ index */
4417 QLIST_ENTRY(MSIRouteEntry) list;
4418 };
4419
4420 /* List of used GSI routes */
4421 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4422 QLIST_HEAD_INITIALIZER(msi_route_list);
4423
4424 static void kvm_update_msi_routes_all(void *private, bool global,
4425 uint32_t index, uint32_t mask)
4426 {
4427 int cnt = 0, vector;
4428 MSIRouteEntry *entry;
4429 MSIMessage msg;
4430 PCIDevice *dev;
4431
4432 /* TODO: explicit route update */
4433 QLIST_FOREACH(entry, &msi_route_list, list) {
4434 cnt++;
4435 vector = entry->vector;
4436 dev = entry->dev;
4437 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4438 msg = msix_get_message(dev, vector);
4439 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4440 msg = msi_get_message(dev, vector);
4441 } else {
4442 /*
4443 * Either MSI/MSIX is disabled for the device, or the
4444 * specific message was masked out. Skip this one.
4445 */
4446 continue;
4447 }
4448 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
4449 }
4450 kvm_irqchip_commit_routes(kvm_state);
4451 trace_kvm_x86_update_msi_routes(cnt);
4452 }
4453
4454 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4455 int vector, PCIDevice *dev)
4456 {
4457 static bool notify_list_inited = false;
4458 MSIRouteEntry *entry;
4459
4460 if (!dev) {
4461 /* These are (possibly) IOAPIC routes only used for split
4462 * kernel irqchip mode, while what we are housekeeping are
4463 * PCI devices only. */
4464 return 0;
4465 }
4466
4467 entry = g_new0(MSIRouteEntry, 1);
4468 entry->dev = dev;
4469 entry->vector = vector;
4470 entry->virq = route->gsi;
4471 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4472
4473 trace_kvm_x86_add_msi_route(route->gsi);
4474
4475 if (!notify_list_inited) {
4476 /* For the first time we do add route, add ourselves into
4477 * IOMMU's IEC notify list if needed. */
4478 X86IOMMUState *iommu = x86_iommu_get_default();
4479 if (iommu) {
4480 x86_iommu_iec_register_notifier(iommu,
4481 kvm_update_msi_routes_all,
4482 NULL);
4483 }
4484 notify_list_inited = true;
4485 }
4486 return 0;
4487 }
4488
4489 int kvm_arch_release_virq_post(int virq)
4490 {
4491 MSIRouteEntry *entry, *next;
4492 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4493 if (entry->virq == virq) {
4494 trace_kvm_x86_remove_msi_route(virq);
4495 QLIST_REMOVE(entry, list);
4496 g_free(entry);
4497 break;
4498 }
4499 }
4500 return 0;
4501 }
4502
4503 int kvm_arch_msi_data_to_gsi(uint32_t data)
4504 {
4505 abort();
4506 }
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