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Merge remote-tracking branch 'remotes/sstabellini/tags/xen-20170202' into staging
[mirror_qemu.git] / target / i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30
31 #include "exec/gdbstub.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/config-file.h"
34 #include "qemu/error-report.h"
35 #include "hw/i386/pc.h"
36 #include "hw/i386/apic.h"
37 #include "hw/i386/apic_internal.h"
38 #include "hw/i386/apic-msidef.h"
39 #include "hw/i386/intel_iommu.h"
40 #include "hw/i386/x86-iommu.h"
41
42 #include "exec/ioport.h"
43 #include "standard-headers/asm-x86/hyperv.h"
44 #include "hw/pci/pci.h"
45 #include "hw/pci/msi.h"
46 #include "migration/migration.h"
47 #include "exec/memattrs.h"
48 #include "trace.h"
49
50 //#define DEBUG_KVM
51
52 #ifdef DEBUG_KVM
53 #define DPRINTF(fmt, ...) \
54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55 #else
56 #define DPRINTF(fmt, ...) \
57 do { } while (0)
58 #endif
59
60 #define MSR_KVM_WALL_CLOCK 0x11
61 #define MSR_KVM_SYSTEM_TIME 0x12
62
63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65 #define MSR_BUF_SIZE 4096
66
67 #ifndef BUS_MCEERR_AR
68 #define BUS_MCEERR_AR 4
69 #endif
70 #ifndef BUS_MCEERR_AO
71 #define BUS_MCEERR_AO 5
72 #endif
73
74 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
75 KVM_CAP_INFO(SET_TSS_ADDR),
76 KVM_CAP_INFO(EXT_CPUID),
77 KVM_CAP_INFO(MP_STATE),
78 KVM_CAP_LAST_INFO
79 };
80
81 static bool has_msr_star;
82 static bool has_msr_hsave_pa;
83 static bool has_msr_tsc_aux;
84 static bool has_msr_tsc_adjust;
85 static bool has_msr_tsc_deadline;
86 static bool has_msr_feature_control;
87 static bool has_msr_misc_enable;
88 static bool has_msr_smbase;
89 static bool has_msr_bndcfgs;
90 static int lm_capable_kernel;
91 static bool has_msr_hv_hypercall;
92 static bool has_msr_hv_crash;
93 static bool has_msr_hv_reset;
94 static bool has_msr_hv_vpindex;
95 static bool has_msr_hv_runtime;
96 static bool has_msr_hv_synic;
97 static bool has_msr_hv_stimer;
98 static bool has_msr_xss;
99
100 static bool has_msr_architectural_pmu;
101 static uint32_t num_architectural_pmu_counters;
102
103 static int has_xsave;
104 static int has_xcrs;
105 static int has_pit_state2;
106
107 static bool has_msr_mcg_ext_ctl;
108
109 static struct kvm_cpuid2 *cpuid_cache;
110
111 int kvm_has_pit_state2(void)
112 {
113 return has_pit_state2;
114 }
115
116 bool kvm_has_smm(void)
117 {
118 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
119 }
120
121 bool kvm_has_adjust_clock_stable(void)
122 {
123 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
124
125 return (ret == KVM_CLOCK_TSC_STABLE);
126 }
127
128 bool kvm_allows_irq0_override(void)
129 {
130 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
131 }
132
133 static bool kvm_x2apic_api_set_flags(uint64_t flags)
134 {
135 KVMState *s = KVM_STATE(current_machine->accelerator);
136
137 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
138 }
139
140 #define MEMORIZE(fn, _result) \
141 ({ \
142 static bool _memorized; \
143 \
144 if (_memorized) { \
145 return _result; \
146 } \
147 _memorized = true; \
148 _result = fn; \
149 })
150
151 static bool has_x2apic_api;
152
153 bool kvm_has_x2apic_api(void)
154 {
155 return has_x2apic_api;
156 }
157
158 bool kvm_enable_x2apic(void)
159 {
160 return MEMORIZE(
161 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
162 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
163 has_x2apic_api);
164 }
165
166 static int kvm_get_tsc(CPUState *cs)
167 {
168 X86CPU *cpu = X86_CPU(cs);
169 CPUX86State *env = &cpu->env;
170 struct {
171 struct kvm_msrs info;
172 struct kvm_msr_entry entries[1];
173 } msr_data;
174 int ret;
175
176 if (env->tsc_valid) {
177 return 0;
178 }
179
180 msr_data.info.nmsrs = 1;
181 msr_data.entries[0].index = MSR_IA32_TSC;
182 env->tsc_valid = !runstate_is_running();
183
184 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
185 if (ret < 0) {
186 return ret;
187 }
188
189 assert(ret == 1);
190 env->tsc = msr_data.entries[0].data;
191 return 0;
192 }
193
194 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
195 {
196 kvm_get_tsc(cpu);
197 }
198
199 void kvm_synchronize_all_tsc(void)
200 {
201 CPUState *cpu;
202
203 if (kvm_enabled()) {
204 CPU_FOREACH(cpu) {
205 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
206 }
207 }
208 }
209
210 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
211 {
212 struct kvm_cpuid2 *cpuid;
213 int r, size;
214
215 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
216 cpuid = g_malloc0(size);
217 cpuid->nent = max;
218 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
219 if (r == 0 && cpuid->nent >= max) {
220 r = -E2BIG;
221 }
222 if (r < 0) {
223 if (r == -E2BIG) {
224 g_free(cpuid);
225 return NULL;
226 } else {
227 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
228 strerror(-r));
229 exit(1);
230 }
231 }
232 return cpuid;
233 }
234
235 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
236 * for all entries.
237 */
238 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
239 {
240 struct kvm_cpuid2 *cpuid;
241 int max = 1;
242
243 if (cpuid_cache != NULL) {
244 return cpuid_cache;
245 }
246 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
247 max *= 2;
248 }
249 cpuid_cache = cpuid;
250 return cpuid;
251 }
252
253 static const struct kvm_para_features {
254 int cap;
255 int feature;
256 } para_features[] = {
257 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
258 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
259 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
260 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
261 };
262
263 static int get_para_features(KVMState *s)
264 {
265 int i, features = 0;
266
267 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
268 if (kvm_check_extension(s, para_features[i].cap)) {
269 features |= (1 << para_features[i].feature);
270 }
271 }
272
273 return features;
274 }
275
276
277 /* Returns the value for a specific register on the cpuid entry
278 */
279 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
280 {
281 uint32_t ret = 0;
282 switch (reg) {
283 case R_EAX:
284 ret = entry->eax;
285 break;
286 case R_EBX:
287 ret = entry->ebx;
288 break;
289 case R_ECX:
290 ret = entry->ecx;
291 break;
292 case R_EDX:
293 ret = entry->edx;
294 break;
295 }
296 return ret;
297 }
298
299 /* Find matching entry for function/index on kvm_cpuid2 struct
300 */
301 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
302 uint32_t function,
303 uint32_t index)
304 {
305 int i;
306 for (i = 0; i < cpuid->nent; ++i) {
307 if (cpuid->entries[i].function == function &&
308 cpuid->entries[i].index == index) {
309 return &cpuid->entries[i];
310 }
311 }
312 /* not found: */
313 return NULL;
314 }
315
316 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
317 uint32_t index, int reg)
318 {
319 struct kvm_cpuid2 *cpuid;
320 uint32_t ret = 0;
321 uint32_t cpuid_1_edx;
322 bool found = false;
323
324 cpuid = get_supported_cpuid(s);
325
326 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
327 if (entry) {
328 found = true;
329 ret = cpuid_entry_get_reg(entry, reg);
330 }
331
332 /* Fixups for the data returned by KVM, below */
333
334 if (function == 1 && reg == R_EDX) {
335 /* KVM before 2.6.30 misreports the following features */
336 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
337 } else if (function == 1 && reg == R_ECX) {
338 /* We can set the hypervisor flag, even if KVM does not return it on
339 * GET_SUPPORTED_CPUID
340 */
341 ret |= CPUID_EXT_HYPERVISOR;
342 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
343 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
344 * and the irqchip is in the kernel.
345 */
346 if (kvm_irqchip_in_kernel() &&
347 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
348 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
349 }
350
351 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
352 * without the in-kernel irqchip
353 */
354 if (!kvm_irqchip_in_kernel()) {
355 ret &= ~CPUID_EXT_X2APIC;
356 }
357 } else if (function == 6 && reg == R_EAX) {
358 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
359 } else if (function == 0x80000001 && reg == R_EDX) {
360 /* On Intel, kvm returns cpuid according to the Intel spec,
361 * so add missing bits according to the AMD spec:
362 */
363 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
364 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
365 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
366 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
367 * be enabled without the in-kernel irqchip
368 */
369 if (!kvm_irqchip_in_kernel()) {
370 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
371 }
372 }
373
374 /* fallback for older kernels */
375 if ((function == KVM_CPUID_FEATURES) && !found) {
376 ret = get_para_features(s);
377 }
378
379 return ret;
380 }
381
382 typedef struct HWPoisonPage {
383 ram_addr_t ram_addr;
384 QLIST_ENTRY(HWPoisonPage) list;
385 } HWPoisonPage;
386
387 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
388 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
389
390 static void kvm_unpoison_all(void *param)
391 {
392 HWPoisonPage *page, *next_page;
393
394 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
395 QLIST_REMOVE(page, list);
396 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
397 g_free(page);
398 }
399 }
400
401 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
402 {
403 HWPoisonPage *page;
404
405 QLIST_FOREACH(page, &hwpoison_page_list, list) {
406 if (page->ram_addr == ram_addr) {
407 return;
408 }
409 }
410 page = g_new(HWPoisonPage, 1);
411 page->ram_addr = ram_addr;
412 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
413 }
414
415 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
416 int *max_banks)
417 {
418 int r;
419
420 r = kvm_check_extension(s, KVM_CAP_MCE);
421 if (r > 0) {
422 *max_banks = r;
423 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
424 }
425 return -ENOSYS;
426 }
427
428 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
429 {
430 CPUState *cs = CPU(cpu);
431 CPUX86State *env = &cpu->env;
432 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
433 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
434 uint64_t mcg_status = MCG_STATUS_MCIP;
435 int flags = 0;
436
437 if (code == BUS_MCEERR_AR) {
438 status |= MCI_STATUS_AR | 0x134;
439 mcg_status |= MCG_STATUS_EIPV;
440 } else {
441 status |= 0xc0;
442 mcg_status |= MCG_STATUS_RIPV;
443 }
444
445 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
446 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
447 * guest kernel back into env->mcg_ext_ctl.
448 */
449 cpu_synchronize_state(cs);
450 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
451 mcg_status |= MCG_STATUS_LMCE;
452 flags = 0;
453 }
454
455 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
456 (MCM_ADDR_PHYS << 6) | 0xc, flags);
457 }
458
459 static void hardware_memory_error(void)
460 {
461 fprintf(stderr, "Hardware memory error!\n");
462 exit(1);
463 }
464
465 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
466 {
467 X86CPU *cpu = X86_CPU(c);
468 CPUX86State *env = &cpu->env;
469 ram_addr_t ram_addr;
470 hwaddr paddr;
471
472 if ((env->mcg_cap & MCG_SER_P) && addr
473 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
474 ram_addr = qemu_ram_addr_from_host(addr);
475 if (ram_addr == RAM_ADDR_INVALID ||
476 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
477 fprintf(stderr, "Hardware memory error for memory used by "
478 "QEMU itself instead of guest system!\n");
479 /* Hope we are lucky for AO MCE */
480 if (code == BUS_MCEERR_AO) {
481 return 0;
482 } else {
483 hardware_memory_error();
484 }
485 }
486 kvm_hwpoison_page_add(ram_addr);
487 kvm_mce_inject(cpu, paddr, code);
488 } else {
489 if (code == BUS_MCEERR_AO) {
490 return 0;
491 } else if (code == BUS_MCEERR_AR) {
492 hardware_memory_error();
493 } else {
494 return 1;
495 }
496 }
497 return 0;
498 }
499
500 int kvm_arch_on_sigbus(int code, void *addr)
501 {
502 X86CPU *cpu = X86_CPU(first_cpu);
503
504 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
505 ram_addr_t ram_addr;
506 hwaddr paddr;
507
508 /* Hope we are lucky for AO MCE */
509 ram_addr = qemu_ram_addr_from_host(addr);
510 if (ram_addr == RAM_ADDR_INVALID ||
511 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
512 addr, &paddr)) {
513 fprintf(stderr, "Hardware memory error for memory used by "
514 "QEMU itself instead of guest system!: %p\n", addr);
515 return 0;
516 }
517 kvm_hwpoison_page_add(ram_addr);
518 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
519 } else {
520 if (code == BUS_MCEERR_AO) {
521 return 0;
522 } else if (code == BUS_MCEERR_AR) {
523 hardware_memory_error();
524 } else {
525 return 1;
526 }
527 }
528 return 0;
529 }
530
531 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
532 {
533 CPUX86State *env = &cpu->env;
534
535 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
536 unsigned int bank, bank_num = env->mcg_cap & 0xff;
537 struct kvm_x86_mce mce;
538
539 env->exception_injected = -1;
540
541 /*
542 * There must be at least one bank in use if an MCE is pending.
543 * Find it and use its values for the event injection.
544 */
545 for (bank = 0; bank < bank_num; bank++) {
546 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
547 break;
548 }
549 }
550 assert(bank < bank_num);
551
552 mce.bank = bank;
553 mce.status = env->mce_banks[bank * 4 + 1];
554 mce.mcg_status = env->mcg_status;
555 mce.addr = env->mce_banks[bank * 4 + 2];
556 mce.misc = env->mce_banks[bank * 4 + 3];
557
558 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
559 }
560 return 0;
561 }
562
563 static void cpu_update_state(void *opaque, int running, RunState state)
564 {
565 CPUX86State *env = opaque;
566
567 if (running) {
568 env->tsc_valid = false;
569 }
570 }
571
572 unsigned long kvm_arch_vcpu_id(CPUState *cs)
573 {
574 X86CPU *cpu = X86_CPU(cs);
575 return cpu->apic_id;
576 }
577
578 #ifndef KVM_CPUID_SIGNATURE_NEXT
579 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
580 #endif
581
582 static bool hyperv_hypercall_available(X86CPU *cpu)
583 {
584 return cpu->hyperv_vapic ||
585 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
586 }
587
588 static bool hyperv_enabled(X86CPU *cpu)
589 {
590 CPUState *cs = CPU(cpu);
591 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
592 (hyperv_hypercall_available(cpu) ||
593 cpu->hyperv_time ||
594 cpu->hyperv_relaxed_timing ||
595 cpu->hyperv_crash ||
596 cpu->hyperv_reset ||
597 cpu->hyperv_vpindex ||
598 cpu->hyperv_runtime ||
599 cpu->hyperv_synic ||
600 cpu->hyperv_stimer);
601 }
602
603 static int kvm_arch_set_tsc_khz(CPUState *cs)
604 {
605 X86CPU *cpu = X86_CPU(cs);
606 CPUX86State *env = &cpu->env;
607 int r;
608
609 if (!env->tsc_khz) {
610 return 0;
611 }
612
613 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
614 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
615 -ENOTSUP;
616 if (r < 0) {
617 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
618 * TSC frequency doesn't match the one we want.
619 */
620 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
621 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
622 -ENOTSUP;
623 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
624 error_report("warning: TSC frequency mismatch between "
625 "VM (%" PRId64 " kHz) and host (%d kHz), "
626 "and TSC scaling unavailable",
627 env->tsc_khz, cur_freq);
628 return r;
629 }
630 }
631
632 return 0;
633 }
634
635 static int hyperv_handle_properties(CPUState *cs)
636 {
637 X86CPU *cpu = X86_CPU(cs);
638 CPUX86State *env = &cpu->env;
639
640 if (cpu->hyperv_time &&
641 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
642 cpu->hyperv_time = false;
643 }
644
645 if (cpu->hyperv_relaxed_timing) {
646 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
647 }
648 if (cpu->hyperv_vapic) {
649 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
650 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
651 }
652 if (cpu->hyperv_time) {
653 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
654 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
655 env->features[FEAT_HYPERV_EAX] |= 0x200;
656 }
657 if (cpu->hyperv_crash && has_msr_hv_crash) {
658 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
659 }
660 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
661 if (cpu->hyperv_reset && has_msr_hv_reset) {
662 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
663 }
664 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
665 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
666 }
667 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
668 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
669 }
670 if (cpu->hyperv_synic) {
671 int sint;
672
673 if (!has_msr_hv_synic ||
674 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
675 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
676 return -ENOSYS;
677 }
678
679 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
680 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
681 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
682 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
683 }
684 }
685 if (cpu->hyperv_stimer) {
686 if (!has_msr_hv_stimer) {
687 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
688 return -ENOSYS;
689 }
690 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
691 }
692 return 0;
693 }
694
695 static Error *invtsc_mig_blocker;
696
697 #define KVM_MAX_CPUID_ENTRIES 100
698
699 int kvm_arch_init_vcpu(CPUState *cs)
700 {
701 struct {
702 struct kvm_cpuid2 cpuid;
703 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
704 } QEMU_PACKED cpuid_data;
705 X86CPU *cpu = X86_CPU(cs);
706 CPUX86State *env = &cpu->env;
707 uint32_t limit, i, j, cpuid_i;
708 uint32_t unused;
709 struct kvm_cpuid_entry2 *c;
710 uint32_t signature[3];
711 int kvm_base = KVM_CPUID_SIGNATURE;
712 int r;
713 Error *local_err = NULL;
714
715 memset(&cpuid_data, 0, sizeof(cpuid_data));
716
717 cpuid_i = 0;
718
719 /* Paravirtualization CPUIDs */
720 if (hyperv_enabled(cpu)) {
721 c = &cpuid_data.entries[cpuid_i++];
722 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
723 if (!cpu->hyperv_vendor_id) {
724 memcpy(signature, "Microsoft Hv", 12);
725 } else {
726 size_t len = strlen(cpu->hyperv_vendor_id);
727
728 if (len > 12) {
729 error_report("hv-vendor-id truncated to 12 characters");
730 len = 12;
731 }
732 memset(signature, 0, 12);
733 memcpy(signature, cpu->hyperv_vendor_id, len);
734 }
735 c->eax = HYPERV_CPUID_MIN;
736 c->ebx = signature[0];
737 c->ecx = signature[1];
738 c->edx = signature[2];
739
740 c = &cpuid_data.entries[cpuid_i++];
741 c->function = HYPERV_CPUID_INTERFACE;
742 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
743 c->eax = signature[0];
744 c->ebx = 0;
745 c->ecx = 0;
746 c->edx = 0;
747
748 c = &cpuid_data.entries[cpuid_i++];
749 c->function = HYPERV_CPUID_VERSION;
750 c->eax = 0x00001bbc;
751 c->ebx = 0x00060001;
752
753 c = &cpuid_data.entries[cpuid_i++];
754 c->function = HYPERV_CPUID_FEATURES;
755 r = hyperv_handle_properties(cs);
756 if (r) {
757 return r;
758 }
759 c->eax = env->features[FEAT_HYPERV_EAX];
760 c->ebx = env->features[FEAT_HYPERV_EBX];
761 c->edx = env->features[FEAT_HYPERV_EDX];
762
763 c = &cpuid_data.entries[cpuid_i++];
764 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
765 if (cpu->hyperv_relaxed_timing) {
766 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
767 }
768 if (cpu->hyperv_vapic) {
769 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
770 }
771 c->ebx = cpu->hyperv_spinlock_attempts;
772
773 c = &cpuid_data.entries[cpuid_i++];
774 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
775 c->eax = 0x40;
776 c->ebx = 0x40;
777
778 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
779 has_msr_hv_hypercall = true;
780 }
781
782 if (cpu->expose_kvm) {
783 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
784 c = &cpuid_data.entries[cpuid_i++];
785 c->function = KVM_CPUID_SIGNATURE | kvm_base;
786 c->eax = KVM_CPUID_FEATURES | kvm_base;
787 c->ebx = signature[0];
788 c->ecx = signature[1];
789 c->edx = signature[2];
790
791 c = &cpuid_data.entries[cpuid_i++];
792 c->function = KVM_CPUID_FEATURES | kvm_base;
793 c->eax = env->features[FEAT_KVM];
794 }
795
796 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
797
798 for (i = 0; i <= limit; i++) {
799 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
800 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
801 abort();
802 }
803 c = &cpuid_data.entries[cpuid_i++];
804
805 switch (i) {
806 case 2: {
807 /* Keep reading function 2 till all the input is received */
808 int times;
809
810 c->function = i;
811 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
812 KVM_CPUID_FLAG_STATE_READ_NEXT;
813 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
814 times = c->eax & 0xff;
815
816 for (j = 1; j < times; ++j) {
817 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
818 fprintf(stderr, "cpuid_data is full, no space for "
819 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
820 abort();
821 }
822 c = &cpuid_data.entries[cpuid_i++];
823 c->function = i;
824 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
825 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
826 }
827 break;
828 }
829 case 4:
830 case 0xb:
831 case 0xd:
832 for (j = 0; ; j++) {
833 if (i == 0xd && j == 64) {
834 break;
835 }
836 c->function = i;
837 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
838 c->index = j;
839 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
840
841 if (i == 4 && c->eax == 0) {
842 break;
843 }
844 if (i == 0xb && !(c->ecx & 0xff00)) {
845 break;
846 }
847 if (i == 0xd && c->eax == 0) {
848 continue;
849 }
850 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
851 fprintf(stderr, "cpuid_data is full, no space for "
852 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
853 abort();
854 }
855 c = &cpuid_data.entries[cpuid_i++];
856 }
857 break;
858 default:
859 c->function = i;
860 c->flags = 0;
861 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
862 break;
863 }
864 }
865
866 if (limit >= 0x0a) {
867 uint32_t ver;
868
869 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
870 if ((ver & 0xff) > 0) {
871 has_msr_architectural_pmu = true;
872 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
873
874 /* Shouldn't be more than 32, since that's the number of bits
875 * available in EBX to tell us _which_ counters are available.
876 * Play it safe.
877 */
878 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
879 num_architectural_pmu_counters = MAX_GP_COUNTERS;
880 }
881 }
882 }
883
884 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
885
886 for (i = 0x80000000; i <= limit; i++) {
887 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
888 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
889 abort();
890 }
891 c = &cpuid_data.entries[cpuid_i++];
892
893 c->function = i;
894 c->flags = 0;
895 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
896 }
897
898 /* Call Centaur's CPUID instructions they are supported. */
899 if (env->cpuid_xlevel2 > 0) {
900 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
901
902 for (i = 0xC0000000; i <= limit; i++) {
903 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
904 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
905 abort();
906 }
907 c = &cpuid_data.entries[cpuid_i++];
908
909 c->function = i;
910 c->flags = 0;
911 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
912 }
913 }
914
915 cpuid_data.cpuid.nent = cpuid_i;
916
917 if (((env->cpuid_version >> 8)&0xF) >= 6
918 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
919 (CPUID_MCE | CPUID_MCA)
920 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
921 uint64_t mcg_cap, unsupported_caps;
922 int banks;
923 int ret;
924
925 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
926 if (ret < 0) {
927 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
928 return ret;
929 }
930
931 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
932 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
933 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
934 return -ENOTSUP;
935 }
936
937 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
938 if (unsupported_caps) {
939 if (unsupported_caps & MCG_LMCE_P) {
940 error_report("kvm: LMCE not supported");
941 return -ENOTSUP;
942 }
943 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
944 unsupported_caps);
945 }
946
947 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
948 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
949 if (ret < 0) {
950 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
951 return ret;
952 }
953 }
954
955 qemu_add_vm_change_state_handler(cpu_update_state, env);
956
957 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
958 if (c) {
959 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
960 !!(c->ecx & CPUID_EXT_SMX);
961 }
962
963 if (env->mcg_cap & MCG_LMCE_P) {
964 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
965 }
966
967 if (!env->user_tsc_khz) {
968 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
969 invtsc_mig_blocker == NULL) {
970 /* for migration */
971 error_setg(&invtsc_mig_blocker,
972 "State blocked by non-migratable CPU device"
973 " (invtsc flag)");
974 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
975 if (local_err) {
976 error_report_err(local_err);
977 error_free(invtsc_mig_blocker);
978 goto fail;
979 }
980 /* for savevm */
981 vmstate_x86_cpu.unmigratable = 1;
982 }
983 }
984
985 r = kvm_arch_set_tsc_khz(cs);
986 if (r < 0) {
987 goto fail;
988 }
989
990 /* vcpu's TSC frequency is either specified by user, or following
991 * the value used by KVM if the former is not present. In the
992 * latter case, we query it from KVM and record in env->tsc_khz,
993 * so that vcpu's TSC frequency can be migrated later via this field.
994 */
995 if (!env->tsc_khz) {
996 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
997 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
998 -ENOTSUP;
999 if (r > 0) {
1000 env->tsc_khz = r;
1001 }
1002 }
1003
1004 if (cpu->vmware_cpuid_freq
1005 /* Guests depend on 0x40000000 to detect this feature, so only expose
1006 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1007 && cpu->expose_kvm
1008 && kvm_base == KVM_CPUID_SIGNATURE
1009 /* TSC clock must be stable and known for this feature. */
1010 && ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
1011 || env->user_tsc_khz != 0)
1012 && env->tsc_khz != 0) {
1013
1014 c = &cpuid_data.entries[cpuid_i++];
1015 c->function = KVM_CPUID_SIGNATURE | 0x10;
1016 c->eax = env->tsc_khz;
1017 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1018 * APIC_BUS_CYCLE_NS */
1019 c->ebx = 1000000;
1020 c->ecx = c->edx = 0;
1021
1022 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1023 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1024 }
1025
1026 cpuid_data.cpuid.nent = cpuid_i;
1027
1028 cpuid_data.cpuid.padding = 0;
1029 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1030 if (r) {
1031 goto fail;
1032 }
1033
1034 if (has_xsave) {
1035 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1036 }
1037 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1038
1039 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1040 has_msr_tsc_aux = false;
1041 }
1042
1043 return 0;
1044
1045 fail:
1046 migrate_del_blocker(invtsc_mig_blocker);
1047 return r;
1048 }
1049
1050 void kvm_arch_reset_vcpu(X86CPU *cpu)
1051 {
1052 CPUX86State *env = &cpu->env;
1053
1054 env->exception_injected = -1;
1055 env->interrupt_injected = -1;
1056 env->xcr0 = 1;
1057 if (kvm_irqchip_in_kernel()) {
1058 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1059 KVM_MP_STATE_UNINITIALIZED;
1060 } else {
1061 env->mp_state = KVM_MP_STATE_RUNNABLE;
1062 }
1063 }
1064
1065 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1066 {
1067 CPUX86State *env = &cpu->env;
1068
1069 /* APs get directly into wait-for-SIPI state. */
1070 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1071 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1072 }
1073 }
1074
1075 static int kvm_get_supported_msrs(KVMState *s)
1076 {
1077 static int kvm_supported_msrs;
1078 int ret = 0;
1079
1080 /* first time */
1081 if (kvm_supported_msrs == 0) {
1082 struct kvm_msr_list msr_list, *kvm_msr_list;
1083
1084 kvm_supported_msrs = -1;
1085
1086 /* Obtain MSR list from KVM. These are the MSRs that we must
1087 * save/restore */
1088 msr_list.nmsrs = 0;
1089 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1090 if (ret < 0 && ret != -E2BIG) {
1091 return ret;
1092 }
1093 /* Old kernel modules had a bug and could write beyond the provided
1094 memory. Allocate at least a safe amount of 1K. */
1095 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1096 msr_list.nmsrs *
1097 sizeof(msr_list.indices[0])));
1098
1099 kvm_msr_list->nmsrs = msr_list.nmsrs;
1100 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1101 if (ret >= 0) {
1102 int i;
1103
1104 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1105 if (kvm_msr_list->indices[i] == MSR_STAR) {
1106 has_msr_star = true;
1107 continue;
1108 }
1109 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
1110 has_msr_hsave_pa = true;
1111 continue;
1112 }
1113 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1114 has_msr_tsc_aux = true;
1115 continue;
1116 }
1117 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1118 has_msr_tsc_adjust = true;
1119 continue;
1120 }
1121 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1122 has_msr_tsc_deadline = true;
1123 continue;
1124 }
1125 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1126 has_msr_smbase = true;
1127 continue;
1128 }
1129 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1130 has_msr_misc_enable = true;
1131 continue;
1132 }
1133 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1134 has_msr_bndcfgs = true;
1135 continue;
1136 }
1137 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1138 has_msr_xss = true;
1139 continue;
1140 }
1141 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1142 has_msr_hv_crash = true;
1143 continue;
1144 }
1145 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1146 has_msr_hv_reset = true;
1147 continue;
1148 }
1149 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1150 has_msr_hv_vpindex = true;
1151 continue;
1152 }
1153 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1154 has_msr_hv_runtime = true;
1155 continue;
1156 }
1157 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1158 has_msr_hv_synic = true;
1159 continue;
1160 }
1161 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1162 has_msr_hv_stimer = true;
1163 continue;
1164 }
1165 }
1166 }
1167
1168 g_free(kvm_msr_list);
1169 }
1170
1171 return ret;
1172 }
1173
1174 static Notifier smram_machine_done;
1175 static KVMMemoryListener smram_listener;
1176 static AddressSpace smram_address_space;
1177 static MemoryRegion smram_as_root;
1178 static MemoryRegion smram_as_mem;
1179
1180 static void register_smram_listener(Notifier *n, void *unused)
1181 {
1182 MemoryRegion *smram =
1183 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1184
1185 /* Outer container... */
1186 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1187 memory_region_set_enabled(&smram_as_root, true);
1188
1189 /* ... with two regions inside: normal system memory with low
1190 * priority, and...
1191 */
1192 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1193 get_system_memory(), 0, ~0ull);
1194 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1195 memory_region_set_enabled(&smram_as_mem, true);
1196
1197 if (smram) {
1198 /* ... SMRAM with higher priority */
1199 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1200 memory_region_set_enabled(smram, true);
1201 }
1202
1203 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1204 kvm_memory_listener_register(kvm_state, &smram_listener,
1205 &smram_address_space, 1);
1206 }
1207
1208 int kvm_arch_init(MachineState *ms, KVMState *s)
1209 {
1210 uint64_t identity_base = 0xfffbc000;
1211 uint64_t shadow_mem;
1212 int ret;
1213 struct utsname utsname;
1214
1215 #ifdef KVM_CAP_XSAVE
1216 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1217 #endif
1218
1219 #ifdef KVM_CAP_XCRS
1220 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1221 #endif
1222
1223 #ifdef KVM_CAP_PIT_STATE2
1224 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1225 #endif
1226
1227 ret = kvm_get_supported_msrs(s);
1228 if (ret < 0) {
1229 return ret;
1230 }
1231
1232 uname(&utsname);
1233 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1234
1235 /*
1236 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1237 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1238 * Since these must be part of guest physical memory, we need to allocate
1239 * them, both by setting their start addresses in the kernel and by
1240 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1241 *
1242 * Older KVM versions may not support setting the identity map base. In
1243 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1244 * size.
1245 */
1246 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1247 /* Allows up to 16M BIOSes. */
1248 identity_base = 0xfeffc000;
1249
1250 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1251 if (ret < 0) {
1252 return ret;
1253 }
1254 }
1255
1256 /* Set TSS base one page after EPT identity map. */
1257 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1258 if (ret < 0) {
1259 return ret;
1260 }
1261
1262 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1263 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1264 if (ret < 0) {
1265 fprintf(stderr, "e820_add_entry() table is full\n");
1266 return ret;
1267 }
1268 qemu_register_reset(kvm_unpoison_all, NULL);
1269
1270 shadow_mem = machine_kvm_shadow_mem(ms);
1271 if (shadow_mem != -1) {
1272 shadow_mem /= 4096;
1273 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1274 if (ret < 0) {
1275 return ret;
1276 }
1277 }
1278
1279 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1280 smram_machine_done.notify = register_smram_listener;
1281 qemu_add_machine_init_done_notifier(&smram_machine_done);
1282 }
1283 return 0;
1284 }
1285
1286 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1287 {
1288 lhs->selector = rhs->selector;
1289 lhs->base = rhs->base;
1290 lhs->limit = rhs->limit;
1291 lhs->type = 3;
1292 lhs->present = 1;
1293 lhs->dpl = 3;
1294 lhs->db = 0;
1295 lhs->s = 1;
1296 lhs->l = 0;
1297 lhs->g = 0;
1298 lhs->avl = 0;
1299 lhs->unusable = 0;
1300 }
1301
1302 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1303 {
1304 unsigned flags = rhs->flags;
1305 lhs->selector = rhs->selector;
1306 lhs->base = rhs->base;
1307 lhs->limit = rhs->limit;
1308 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1309 lhs->present = (flags & DESC_P_MASK) != 0;
1310 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1311 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1312 lhs->s = (flags & DESC_S_MASK) != 0;
1313 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1314 lhs->g = (flags & DESC_G_MASK) != 0;
1315 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1316 lhs->unusable = !lhs->present;
1317 lhs->padding = 0;
1318 }
1319
1320 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1321 {
1322 lhs->selector = rhs->selector;
1323 lhs->base = rhs->base;
1324 lhs->limit = rhs->limit;
1325 if (rhs->unusable) {
1326 lhs->flags = 0;
1327 } else {
1328 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1329 (rhs->present * DESC_P_MASK) |
1330 (rhs->dpl << DESC_DPL_SHIFT) |
1331 (rhs->db << DESC_B_SHIFT) |
1332 (rhs->s * DESC_S_MASK) |
1333 (rhs->l << DESC_L_SHIFT) |
1334 (rhs->g * DESC_G_MASK) |
1335 (rhs->avl * DESC_AVL_MASK);
1336 }
1337 }
1338
1339 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1340 {
1341 if (set) {
1342 *kvm_reg = *qemu_reg;
1343 } else {
1344 *qemu_reg = *kvm_reg;
1345 }
1346 }
1347
1348 static int kvm_getput_regs(X86CPU *cpu, int set)
1349 {
1350 CPUX86State *env = &cpu->env;
1351 struct kvm_regs regs;
1352 int ret = 0;
1353
1354 if (!set) {
1355 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1356 if (ret < 0) {
1357 return ret;
1358 }
1359 }
1360
1361 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1362 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1363 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1364 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1365 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1366 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1367 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1368 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1369 #ifdef TARGET_X86_64
1370 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1371 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1372 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1373 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1374 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1375 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1376 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1377 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1378 #endif
1379
1380 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1381 kvm_getput_reg(&regs.rip, &env->eip, set);
1382
1383 if (set) {
1384 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1385 }
1386
1387 return ret;
1388 }
1389
1390 static int kvm_put_fpu(X86CPU *cpu)
1391 {
1392 CPUX86State *env = &cpu->env;
1393 struct kvm_fpu fpu;
1394 int i;
1395
1396 memset(&fpu, 0, sizeof fpu);
1397 fpu.fsw = env->fpus & ~(7 << 11);
1398 fpu.fsw |= (env->fpstt & 7) << 11;
1399 fpu.fcw = env->fpuc;
1400 fpu.last_opcode = env->fpop;
1401 fpu.last_ip = env->fpip;
1402 fpu.last_dp = env->fpdp;
1403 for (i = 0; i < 8; ++i) {
1404 fpu.ftwx |= (!env->fptags[i]) << i;
1405 }
1406 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1407 for (i = 0; i < CPU_NB_REGS; i++) {
1408 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1409 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1410 }
1411 fpu.mxcsr = env->mxcsr;
1412
1413 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1414 }
1415
1416 #define XSAVE_FCW_FSW 0
1417 #define XSAVE_FTW_FOP 1
1418 #define XSAVE_CWD_RIP 2
1419 #define XSAVE_CWD_RDP 4
1420 #define XSAVE_MXCSR 6
1421 #define XSAVE_ST_SPACE 8
1422 #define XSAVE_XMM_SPACE 40
1423 #define XSAVE_XSTATE_BV 128
1424 #define XSAVE_YMMH_SPACE 144
1425 #define XSAVE_BNDREGS 240
1426 #define XSAVE_BNDCSR 256
1427 #define XSAVE_OPMASK 272
1428 #define XSAVE_ZMM_Hi256 288
1429 #define XSAVE_Hi16_ZMM 416
1430 #define XSAVE_PKRU 672
1431
1432 #define XSAVE_BYTE_OFFSET(word_offset) \
1433 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1434
1435 #define ASSERT_OFFSET(word_offset, field) \
1436 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1437 offsetof(X86XSaveArea, field))
1438
1439 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1440 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1441 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1442 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1443 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1444 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1445 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1446 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1447 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1448 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1449 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1450 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1451 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1452 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1453 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1454
1455 static int kvm_put_xsave(X86CPU *cpu)
1456 {
1457 CPUX86State *env = &cpu->env;
1458 X86XSaveArea *xsave = env->kvm_xsave_buf;
1459 uint16_t cwd, swd, twd;
1460 int i;
1461
1462 if (!has_xsave) {
1463 return kvm_put_fpu(cpu);
1464 }
1465
1466 memset(xsave, 0, sizeof(struct kvm_xsave));
1467 twd = 0;
1468 swd = env->fpus & ~(7 << 11);
1469 swd |= (env->fpstt & 7) << 11;
1470 cwd = env->fpuc;
1471 for (i = 0; i < 8; ++i) {
1472 twd |= (!env->fptags[i]) << i;
1473 }
1474 xsave->legacy.fcw = cwd;
1475 xsave->legacy.fsw = swd;
1476 xsave->legacy.ftw = twd;
1477 xsave->legacy.fpop = env->fpop;
1478 xsave->legacy.fpip = env->fpip;
1479 xsave->legacy.fpdp = env->fpdp;
1480 memcpy(&xsave->legacy.fpregs, env->fpregs,
1481 sizeof env->fpregs);
1482 xsave->legacy.mxcsr = env->mxcsr;
1483 xsave->header.xstate_bv = env->xstate_bv;
1484 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1485 sizeof env->bnd_regs);
1486 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1487 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1488 sizeof env->opmask_regs);
1489
1490 for (i = 0; i < CPU_NB_REGS; i++) {
1491 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1492 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1493 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1494 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1495 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1496 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1497 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1498 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1499 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1500 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1501 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1502 }
1503
1504 #ifdef TARGET_X86_64
1505 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1506 16 * sizeof env->xmm_regs[16]);
1507 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1508 #endif
1509 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1510 }
1511
1512 static int kvm_put_xcrs(X86CPU *cpu)
1513 {
1514 CPUX86State *env = &cpu->env;
1515 struct kvm_xcrs xcrs = {};
1516
1517 if (!has_xcrs) {
1518 return 0;
1519 }
1520
1521 xcrs.nr_xcrs = 1;
1522 xcrs.flags = 0;
1523 xcrs.xcrs[0].xcr = 0;
1524 xcrs.xcrs[0].value = env->xcr0;
1525 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1526 }
1527
1528 static int kvm_put_sregs(X86CPU *cpu)
1529 {
1530 CPUX86State *env = &cpu->env;
1531 struct kvm_sregs sregs;
1532
1533 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1534 if (env->interrupt_injected >= 0) {
1535 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1536 (uint64_t)1 << (env->interrupt_injected % 64);
1537 }
1538
1539 if ((env->eflags & VM_MASK)) {
1540 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1541 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1542 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1543 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1544 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1545 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1546 } else {
1547 set_seg(&sregs.cs, &env->segs[R_CS]);
1548 set_seg(&sregs.ds, &env->segs[R_DS]);
1549 set_seg(&sregs.es, &env->segs[R_ES]);
1550 set_seg(&sregs.fs, &env->segs[R_FS]);
1551 set_seg(&sregs.gs, &env->segs[R_GS]);
1552 set_seg(&sregs.ss, &env->segs[R_SS]);
1553 }
1554
1555 set_seg(&sregs.tr, &env->tr);
1556 set_seg(&sregs.ldt, &env->ldt);
1557
1558 sregs.idt.limit = env->idt.limit;
1559 sregs.idt.base = env->idt.base;
1560 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1561 sregs.gdt.limit = env->gdt.limit;
1562 sregs.gdt.base = env->gdt.base;
1563 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1564
1565 sregs.cr0 = env->cr[0];
1566 sregs.cr2 = env->cr[2];
1567 sregs.cr3 = env->cr[3];
1568 sregs.cr4 = env->cr[4];
1569
1570 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1571 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1572
1573 sregs.efer = env->efer;
1574
1575 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1576 }
1577
1578 static void kvm_msr_buf_reset(X86CPU *cpu)
1579 {
1580 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1581 }
1582
1583 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1584 {
1585 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1586 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1587 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1588
1589 assert((void *)(entry + 1) <= limit);
1590
1591 entry->index = index;
1592 entry->reserved = 0;
1593 entry->data = value;
1594 msrs->nmsrs++;
1595 }
1596
1597 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1598 {
1599 kvm_msr_buf_reset(cpu);
1600 kvm_msr_entry_add(cpu, index, value);
1601
1602 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1603 }
1604
1605 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1606 {
1607 int ret;
1608
1609 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1610 assert(ret == 1);
1611 }
1612
1613 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1614 {
1615 CPUX86State *env = &cpu->env;
1616 int ret;
1617
1618 if (!has_msr_tsc_deadline) {
1619 return 0;
1620 }
1621
1622 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1623 if (ret < 0) {
1624 return ret;
1625 }
1626
1627 assert(ret == 1);
1628 return 0;
1629 }
1630
1631 /*
1632 * Provide a separate write service for the feature control MSR in order to
1633 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1634 * before writing any other state because forcibly leaving nested mode
1635 * invalidates the VCPU state.
1636 */
1637 static int kvm_put_msr_feature_control(X86CPU *cpu)
1638 {
1639 int ret;
1640
1641 if (!has_msr_feature_control) {
1642 return 0;
1643 }
1644
1645 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1646 cpu->env.msr_ia32_feature_control);
1647 if (ret < 0) {
1648 return ret;
1649 }
1650
1651 assert(ret == 1);
1652 return 0;
1653 }
1654
1655 static int kvm_put_msrs(X86CPU *cpu, int level)
1656 {
1657 CPUX86State *env = &cpu->env;
1658 int i;
1659 int ret;
1660
1661 kvm_msr_buf_reset(cpu);
1662
1663 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1664 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1665 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1666 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1667 if (has_msr_star) {
1668 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1669 }
1670 if (has_msr_hsave_pa) {
1671 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1672 }
1673 if (has_msr_tsc_aux) {
1674 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1675 }
1676 if (has_msr_tsc_adjust) {
1677 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1678 }
1679 if (has_msr_misc_enable) {
1680 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1681 env->msr_ia32_misc_enable);
1682 }
1683 if (has_msr_smbase) {
1684 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1685 }
1686 if (has_msr_bndcfgs) {
1687 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1688 }
1689 if (has_msr_xss) {
1690 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1691 }
1692 #ifdef TARGET_X86_64
1693 if (lm_capable_kernel) {
1694 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1695 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1696 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1697 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1698 }
1699 #endif
1700 /*
1701 * The following MSRs have side effects on the guest or are too heavy
1702 * for normal writeback. Limit them to reset or full state updates.
1703 */
1704 if (level >= KVM_PUT_RESET_STATE) {
1705 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1706 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1707 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1708 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1709 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1710 }
1711 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1712 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1713 }
1714 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1715 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1716 }
1717 if (has_msr_architectural_pmu) {
1718 /* Stop the counter. */
1719 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1720 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1721
1722 /* Set the counter values. */
1723 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1724 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1725 env->msr_fixed_counters[i]);
1726 }
1727 for (i = 0; i < num_architectural_pmu_counters; i++) {
1728 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1729 env->msr_gp_counters[i]);
1730 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1731 env->msr_gp_evtsel[i]);
1732 }
1733 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1734 env->msr_global_status);
1735 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1736 env->msr_global_ovf_ctrl);
1737
1738 /* Now start the PMU. */
1739 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1740 env->msr_fixed_ctr_ctrl);
1741 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1742 env->msr_global_ctrl);
1743 }
1744 if (has_msr_hv_hypercall) {
1745 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1746 env->msr_hv_guest_os_id);
1747 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1748 env->msr_hv_hypercall);
1749 }
1750 if (cpu->hyperv_vapic) {
1751 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1752 env->msr_hv_vapic);
1753 }
1754 if (cpu->hyperv_time) {
1755 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1756 }
1757 if (has_msr_hv_crash) {
1758 int j;
1759
1760 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1761 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1762 env->msr_hv_crash_params[j]);
1763
1764 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1765 HV_X64_MSR_CRASH_CTL_NOTIFY);
1766 }
1767 if (has_msr_hv_runtime) {
1768 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1769 }
1770 if (cpu->hyperv_synic) {
1771 int j;
1772
1773 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1774 env->msr_hv_synic_control);
1775 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1776 env->msr_hv_synic_version);
1777 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1778 env->msr_hv_synic_evt_page);
1779 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1780 env->msr_hv_synic_msg_page);
1781
1782 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1783 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1784 env->msr_hv_synic_sint[j]);
1785 }
1786 }
1787 if (has_msr_hv_stimer) {
1788 int j;
1789
1790 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1791 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1792 env->msr_hv_stimer_config[j]);
1793 }
1794
1795 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1796 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1797 env->msr_hv_stimer_count[j]);
1798 }
1799 }
1800 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1801 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1802
1803 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1804 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1805 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1806 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1807 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1808 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1809 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1810 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1811 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1812 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1813 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1814 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1815 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1816 /* The CPU GPs if we write to a bit above the physical limit of
1817 * the host CPU (and KVM emulates that)
1818 */
1819 uint64_t mask = env->mtrr_var[i].mask;
1820 mask &= phys_mask;
1821
1822 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1823 env->mtrr_var[i].base);
1824 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1825 }
1826 }
1827
1828 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1829 * kvm_put_msr_feature_control. */
1830 }
1831 if (env->mcg_cap) {
1832 int i;
1833
1834 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1835 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1836 if (has_msr_mcg_ext_ctl) {
1837 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1838 }
1839 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1840 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1841 }
1842 }
1843
1844 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1845 if (ret < 0) {
1846 return ret;
1847 }
1848
1849 assert(ret == cpu->kvm_msr_buf->nmsrs);
1850 return 0;
1851 }
1852
1853
1854 static int kvm_get_fpu(X86CPU *cpu)
1855 {
1856 CPUX86State *env = &cpu->env;
1857 struct kvm_fpu fpu;
1858 int i, ret;
1859
1860 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1861 if (ret < 0) {
1862 return ret;
1863 }
1864
1865 env->fpstt = (fpu.fsw >> 11) & 7;
1866 env->fpus = fpu.fsw;
1867 env->fpuc = fpu.fcw;
1868 env->fpop = fpu.last_opcode;
1869 env->fpip = fpu.last_ip;
1870 env->fpdp = fpu.last_dp;
1871 for (i = 0; i < 8; ++i) {
1872 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1873 }
1874 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1875 for (i = 0; i < CPU_NB_REGS; i++) {
1876 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1877 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1878 }
1879 env->mxcsr = fpu.mxcsr;
1880
1881 return 0;
1882 }
1883
1884 static int kvm_get_xsave(X86CPU *cpu)
1885 {
1886 CPUX86State *env = &cpu->env;
1887 X86XSaveArea *xsave = env->kvm_xsave_buf;
1888 int ret, i;
1889 uint16_t cwd, swd, twd;
1890
1891 if (!has_xsave) {
1892 return kvm_get_fpu(cpu);
1893 }
1894
1895 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1896 if (ret < 0) {
1897 return ret;
1898 }
1899
1900 cwd = xsave->legacy.fcw;
1901 swd = xsave->legacy.fsw;
1902 twd = xsave->legacy.ftw;
1903 env->fpop = xsave->legacy.fpop;
1904 env->fpstt = (swd >> 11) & 7;
1905 env->fpus = swd;
1906 env->fpuc = cwd;
1907 for (i = 0; i < 8; ++i) {
1908 env->fptags[i] = !((twd >> i) & 1);
1909 }
1910 env->fpip = xsave->legacy.fpip;
1911 env->fpdp = xsave->legacy.fpdp;
1912 env->mxcsr = xsave->legacy.mxcsr;
1913 memcpy(env->fpregs, &xsave->legacy.fpregs,
1914 sizeof env->fpregs);
1915 env->xstate_bv = xsave->header.xstate_bv;
1916 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1917 sizeof env->bnd_regs);
1918 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1919 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1920 sizeof env->opmask_regs);
1921
1922 for (i = 0; i < CPU_NB_REGS; i++) {
1923 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1924 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1925 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1926 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1927 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1928 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1929 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1930 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1931 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1932 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1933 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1934 }
1935
1936 #ifdef TARGET_X86_64
1937 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1938 16 * sizeof env->xmm_regs[16]);
1939 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1940 #endif
1941 return 0;
1942 }
1943
1944 static int kvm_get_xcrs(X86CPU *cpu)
1945 {
1946 CPUX86State *env = &cpu->env;
1947 int i, ret;
1948 struct kvm_xcrs xcrs;
1949
1950 if (!has_xcrs) {
1951 return 0;
1952 }
1953
1954 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1955 if (ret < 0) {
1956 return ret;
1957 }
1958
1959 for (i = 0; i < xcrs.nr_xcrs; i++) {
1960 /* Only support xcr0 now */
1961 if (xcrs.xcrs[i].xcr == 0) {
1962 env->xcr0 = xcrs.xcrs[i].value;
1963 break;
1964 }
1965 }
1966 return 0;
1967 }
1968
1969 static int kvm_get_sregs(X86CPU *cpu)
1970 {
1971 CPUX86State *env = &cpu->env;
1972 struct kvm_sregs sregs;
1973 uint32_t hflags;
1974 int bit, i, ret;
1975
1976 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1977 if (ret < 0) {
1978 return ret;
1979 }
1980
1981 /* There can only be one pending IRQ set in the bitmap at a time, so try
1982 to find it and save its number instead (-1 for none). */
1983 env->interrupt_injected = -1;
1984 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1985 if (sregs.interrupt_bitmap[i]) {
1986 bit = ctz64(sregs.interrupt_bitmap[i]);
1987 env->interrupt_injected = i * 64 + bit;
1988 break;
1989 }
1990 }
1991
1992 get_seg(&env->segs[R_CS], &sregs.cs);
1993 get_seg(&env->segs[R_DS], &sregs.ds);
1994 get_seg(&env->segs[R_ES], &sregs.es);
1995 get_seg(&env->segs[R_FS], &sregs.fs);
1996 get_seg(&env->segs[R_GS], &sregs.gs);
1997 get_seg(&env->segs[R_SS], &sregs.ss);
1998
1999 get_seg(&env->tr, &sregs.tr);
2000 get_seg(&env->ldt, &sregs.ldt);
2001
2002 env->idt.limit = sregs.idt.limit;
2003 env->idt.base = sregs.idt.base;
2004 env->gdt.limit = sregs.gdt.limit;
2005 env->gdt.base = sregs.gdt.base;
2006
2007 env->cr[0] = sregs.cr0;
2008 env->cr[2] = sregs.cr2;
2009 env->cr[3] = sregs.cr3;
2010 env->cr[4] = sregs.cr4;
2011
2012 env->efer = sregs.efer;
2013
2014 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2015
2016 #define HFLAG_COPY_MASK \
2017 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
2018 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
2019 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
2020 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
2021
2022 hflags = env->hflags & HFLAG_COPY_MASK;
2023 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
2024 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
2025 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
2026 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
2027 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
2028
2029 if (env->cr[4] & CR4_OSFXSR_MASK) {
2030 hflags |= HF_OSFXSR_MASK;
2031 }
2032
2033 if (env->efer & MSR_EFER_LMA) {
2034 hflags |= HF_LMA_MASK;
2035 }
2036
2037 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
2038 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2039 } else {
2040 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
2041 (DESC_B_SHIFT - HF_CS32_SHIFT);
2042 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
2043 (DESC_B_SHIFT - HF_SS32_SHIFT);
2044 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
2045 !(hflags & HF_CS32_MASK)) {
2046 hflags |= HF_ADDSEG_MASK;
2047 } else {
2048 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
2049 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
2050 }
2051 }
2052 env->hflags = hflags;
2053
2054 return 0;
2055 }
2056
2057 static int kvm_get_msrs(X86CPU *cpu)
2058 {
2059 CPUX86State *env = &cpu->env;
2060 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2061 int ret, i;
2062 uint64_t mtrr_top_bits;
2063
2064 kvm_msr_buf_reset(cpu);
2065
2066 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2067 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2068 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2069 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2070 if (has_msr_star) {
2071 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2072 }
2073 if (has_msr_hsave_pa) {
2074 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2075 }
2076 if (has_msr_tsc_aux) {
2077 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2078 }
2079 if (has_msr_tsc_adjust) {
2080 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2081 }
2082 if (has_msr_tsc_deadline) {
2083 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2084 }
2085 if (has_msr_misc_enable) {
2086 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2087 }
2088 if (has_msr_smbase) {
2089 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2090 }
2091 if (has_msr_feature_control) {
2092 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2093 }
2094 if (has_msr_bndcfgs) {
2095 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2096 }
2097 if (has_msr_xss) {
2098 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2099 }
2100
2101
2102 if (!env->tsc_valid) {
2103 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2104 env->tsc_valid = !runstate_is_running();
2105 }
2106
2107 #ifdef TARGET_X86_64
2108 if (lm_capable_kernel) {
2109 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2110 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2111 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2112 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2113 }
2114 #endif
2115 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2116 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2117 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2118 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2119 }
2120 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2121 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2122 }
2123 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2124 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2125 }
2126 if (has_msr_architectural_pmu) {
2127 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2128 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2129 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2130 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2131 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2132 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2133 }
2134 for (i = 0; i < num_architectural_pmu_counters; i++) {
2135 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2136 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2137 }
2138 }
2139
2140 if (env->mcg_cap) {
2141 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2142 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2143 if (has_msr_mcg_ext_ctl) {
2144 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2145 }
2146 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2147 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2148 }
2149 }
2150
2151 if (has_msr_hv_hypercall) {
2152 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2153 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2154 }
2155 if (cpu->hyperv_vapic) {
2156 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2157 }
2158 if (cpu->hyperv_time) {
2159 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2160 }
2161 if (has_msr_hv_crash) {
2162 int j;
2163
2164 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2165 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2166 }
2167 }
2168 if (has_msr_hv_runtime) {
2169 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2170 }
2171 if (cpu->hyperv_synic) {
2172 uint32_t msr;
2173
2174 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2175 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2176 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2177 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2178 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2179 kvm_msr_entry_add(cpu, msr, 0);
2180 }
2181 }
2182 if (has_msr_hv_stimer) {
2183 uint32_t msr;
2184
2185 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2186 msr++) {
2187 kvm_msr_entry_add(cpu, msr, 0);
2188 }
2189 }
2190 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2191 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2192 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2193 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2194 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2195 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2196 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2197 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2198 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2199 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2200 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2201 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2202 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2203 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2204 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2205 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2206 }
2207 }
2208
2209 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2210 if (ret < 0) {
2211 return ret;
2212 }
2213
2214 assert(ret == cpu->kvm_msr_buf->nmsrs);
2215 /*
2216 * MTRR masks: Each mask consists of 5 parts
2217 * a 10..0: must be zero
2218 * b 11 : valid bit
2219 * c n-1.12: actual mask bits
2220 * d 51..n: reserved must be zero
2221 * e 63.52: reserved must be zero
2222 *
2223 * 'n' is the number of physical bits supported by the CPU and is
2224 * apparently always <= 52. We know our 'n' but don't know what
2225 * the destinations 'n' is; it might be smaller, in which case
2226 * it masks (c) on loading. It might be larger, in which case
2227 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2228 * we're migrating to.
2229 */
2230
2231 if (cpu->fill_mtrr_mask) {
2232 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2233 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2234 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2235 } else {
2236 mtrr_top_bits = 0;
2237 }
2238
2239 for (i = 0; i < ret; i++) {
2240 uint32_t index = msrs[i].index;
2241 switch (index) {
2242 case MSR_IA32_SYSENTER_CS:
2243 env->sysenter_cs = msrs[i].data;
2244 break;
2245 case MSR_IA32_SYSENTER_ESP:
2246 env->sysenter_esp = msrs[i].data;
2247 break;
2248 case MSR_IA32_SYSENTER_EIP:
2249 env->sysenter_eip = msrs[i].data;
2250 break;
2251 case MSR_PAT:
2252 env->pat = msrs[i].data;
2253 break;
2254 case MSR_STAR:
2255 env->star = msrs[i].data;
2256 break;
2257 #ifdef TARGET_X86_64
2258 case MSR_CSTAR:
2259 env->cstar = msrs[i].data;
2260 break;
2261 case MSR_KERNELGSBASE:
2262 env->kernelgsbase = msrs[i].data;
2263 break;
2264 case MSR_FMASK:
2265 env->fmask = msrs[i].data;
2266 break;
2267 case MSR_LSTAR:
2268 env->lstar = msrs[i].data;
2269 break;
2270 #endif
2271 case MSR_IA32_TSC:
2272 env->tsc = msrs[i].data;
2273 break;
2274 case MSR_TSC_AUX:
2275 env->tsc_aux = msrs[i].data;
2276 break;
2277 case MSR_TSC_ADJUST:
2278 env->tsc_adjust = msrs[i].data;
2279 break;
2280 case MSR_IA32_TSCDEADLINE:
2281 env->tsc_deadline = msrs[i].data;
2282 break;
2283 case MSR_VM_HSAVE_PA:
2284 env->vm_hsave = msrs[i].data;
2285 break;
2286 case MSR_KVM_SYSTEM_TIME:
2287 env->system_time_msr = msrs[i].data;
2288 break;
2289 case MSR_KVM_WALL_CLOCK:
2290 env->wall_clock_msr = msrs[i].data;
2291 break;
2292 case MSR_MCG_STATUS:
2293 env->mcg_status = msrs[i].data;
2294 break;
2295 case MSR_MCG_CTL:
2296 env->mcg_ctl = msrs[i].data;
2297 break;
2298 case MSR_MCG_EXT_CTL:
2299 env->mcg_ext_ctl = msrs[i].data;
2300 break;
2301 case MSR_IA32_MISC_ENABLE:
2302 env->msr_ia32_misc_enable = msrs[i].data;
2303 break;
2304 case MSR_IA32_SMBASE:
2305 env->smbase = msrs[i].data;
2306 break;
2307 case MSR_IA32_FEATURE_CONTROL:
2308 env->msr_ia32_feature_control = msrs[i].data;
2309 break;
2310 case MSR_IA32_BNDCFGS:
2311 env->msr_bndcfgs = msrs[i].data;
2312 break;
2313 case MSR_IA32_XSS:
2314 env->xss = msrs[i].data;
2315 break;
2316 default:
2317 if (msrs[i].index >= MSR_MC0_CTL &&
2318 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2319 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2320 }
2321 break;
2322 case MSR_KVM_ASYNC_PF_EN:
2323 env->async_pf_en_msr = msrs[i].data;
2324 break;
2325 case MSR_KVM_PV_EOI_EN:
2326 env->pv_eoi_en_msr = msrs[i].data;
2327 break;
2328 case MSR_KVM_STEAL_TIME:
2329 env->steal_time_msr = msrs[i].data;
2330 break;
2331 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2332 env->msr_fixed_ctr_ctrl = msrs[i].data;
2333 break;
2334 case MSR_CORE_PERF_GLOBAL_CTRL:
2335 env->msr_global_ctrl = msrs[i].data;
2336 break;
2337 case MSR_CORE_PERF_GLOBAL_STATUS:
2338 env->msr_global_status = msrs[i].data;
2339 break;
2340 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2341 env->msr_global_ovf_ctrl = msrs[i].data;
2342 break;
2343 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2344 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2345 break;
2346 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2347 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2348 break;
2349 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2350 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2351 break;
2352 case HV_X64_MSR_HYPERCALL:
2353 env->msr_hv_hypercall = msrs[i].data;
2354 break;
2355 case HV_X64_MSR_GUEST_OS_ID:
2356 env->msr_hv_guest_os_id = msrs[i].data;
2357 break;
2358 case HV_X64_MSR_APIC_ASSIST_PAGE:
2359 env->msr_hv_vapic = msrs[i].data;
2360 break;
2361 case HV_X64_MSR_REFERENCE_TSC:
2362 env->msr_hv_tsc = msrs[i].data;
2363 break;
2364 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2365 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2366 break;
2367 case HV_X64_MSR_VP_RUNTIME:
2368 env->msr_hv_runtime = msrs[i].data;
2369 break;
2370 case HV_X64_MSR_SCONTROL:
2371 env->msr_hv_synic_control = msrs[i].data;
2372 break;
2373 case HV_X64_MSR_SVERSION:
2374 env->msr_hv_synic_version = msrs[i].data;
2375 break;
2376 case HV_X64_MSR_SIEFP:
2377 env->msr_hv_synic_evt_page = msrs[i].data;
2378 break;
2379 case HV_X64_MSR_SIMP:
2380 env->msr_hv_synic_msg_page = msrs[i].data;
2381 break;
2382 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2383 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2384 break;
2385 case HV_X64_MSR_STIMER0_CONFIG:
2386 case HV_X64_MSR_STIMER1_CONFIG:
2387 case HV_X64_MSR_STIMER2_CONFIG:
2388 case HV_X64_MSR_STIMER3_CONFIG:
2389 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2390 msrs[i].data;
2391 break;
2392 case HV_X64_MSR_STIMER0_COUNT:
2393 case HV_X64_MSR_STIMER1_COUNT:
2394 case HV_X64_MSR_STIMER2_COUNT:
2395 case HV_X64_MSR_STIMER3_COUNT:
2396 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2397 msrs[i].data;
2398 break;
2399 case MSR_MTRRdefType:
2400 env->mtrr_deftype = msrs[i].data;
2401 break;
2402 case MSR_MTRRfix64K_00000:
2403 env->mtrr_fixed[0] = msrs[i].data;
2404 break;
2405 case MSR_MTRRfix16K_80000:
2406 env->mtrr_fixed[1] = msrs[i].data;
2407 break;
2408 case MSR_MTRRfix16K_A0000:
2409 env->mtrr_fixed[2] = msrs[i].data;
2410 break;
2411 case MSR_MTRRfix4K_C0000:
2412 env->mtrr_fixed[3] = msrs[i].data;
2413 break;
2414 case MSR_MTRRfix4K_C8000:
2415 env->mtrr_fixed[4] = msrs[i].data;
2416 break;
2417 case MSR_MTRRfix4K_D0000:
2418 env->mtrr_fixed[5] = msrs[i].data;
2419 break;
2420 case MSR_MTRRfix4K_D8000:
2421 env->mtrr_fixed[6] = msrs[i].data;
2422 break;
2423 case MSR_MTRRfix4K_E0000:
2424 env->mtrr_fixed[7] = msrs[i].data;
2425 break;
2426 case MSR_MTRRfix4K_E8000:
2427 env->mtrr_fixed[8] = msrs[i].data;
2428 break;
2429 case MSR_MTRRfix4K_F0000:
2430 env->mtrr_fixed[9] = msrs[i].data;
2431 break;
2432 case MSR_MTRRfix4K_F8000:
2433 env->mtrr_fixed[10] = msrs[i].data;
2434 break;
2435 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2436 if (index & 1) {
2437 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2438 mtrr_top_bits;
2439 } else {
2440 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2441 }
2442 break;
2443 }
2444 }
2445
2446 return 0;
2447 }
2448
2449 static int kvm_put_mp_state(X86CPU *cpu)
2450 {
2451 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2452
2453 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2454 }
2455
2456 static int kvm_get_mp_state(X86CPU *cpu)
2457 {
2458 CPUState *cs = CPU(cpu);
2459 CPUX86State *env = &cpu->env;
2460 struct kvm_mp_state mp_state;
2461 int ret;
2462
2463 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2464 if (ret < 0) {
2465 return ret;
2466 }
2467 env->mp_state = mp_state.mp_state;
2468 if (kvm_irqchip_in_kernel()) {
2469 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2470 }
2471 return 0;
2472 }
2473
2474 static int kvm_get_apic(X86CPU *cpu)
2475 {
2476 DeviceState *apic = cpu->apic_state;
2477 struct kvm_lapic_state kapic;
2478 int ret;
2479
2480 if (apic && kvm_irqchip_in_kernel()) {
2481 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2482 if (ret < 0) {
2483 return ret;
2484 }
2485
2486 kvm_get_apic_state(apic, &kapic);
2487 }
2488 return 0;
2489 }
2490
2491 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2492 {
2493 CPUState *cs = CPU(cpu);
2494 CPUX86State *env = &cpu->env;
2495 struct kvm_vcpu_events events = {};
2496
2497 if (!kvm_has_vcpu_events()) {
2498 return 0;
2499 }
2500
2501 events.exception.injected = (env->exception_injected >= 0);
2502 events.exception.nr = env->exception_injected;
2503 events.exception.has_error_code = env->has_error_code;
2504 events.exception.error_code = env->error_code;
2505 events.exception.pad = 0;
2506
2507 events.interrupt.injected = (env->interrupt_injected >= 0);
2508 events.interrupt.nr = env->interrupt_injected;
2509 events.interrupt.soft = env->soft_interrupt;
2510
2511 events.nmi.injected = env->nmi_injected;
2512 events.nmi.pending = env->nmi_pending;
2513 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2514 events.nmi.pad = 0;
2515
2516 events.sipi_vector = env->sipi_vector;
2517 events.flags = 0;
2518
2519 if (has_msr_smbase) {
2520 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2521 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2522 if (kvm_irqchip_in_kernel()) {
2523 /* As soon as these are moved to the kernel, remove them
2524 * from cs->interrupt_request.
2525 */
2526 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2527 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2528 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2529 } else {
2530 /* Keep these in cs->interrupt_request. */
2531 events.smi.pending = 0;
2532 events.smi.latched_init = 0;
2533 }
2534 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2535 }
2536
2537 if (level >= KVM_PUT_RESET_STATE) {
2538 events.flags |=
2539 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2540 }
2541
2542 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2543 }
2544
2545 static int kvm_get_vcpu_events(X86CPU *cpu)
2546 {
2547 CPUX86State *env = &cpu->env;
2548 struct kvm_vcpu_events events;
2549 int ret;
2550
2551 if (!kvm_has_vcpu_events()) {
2552 return 0;
2553 }
2554
2555 memset(&events, 0, sizeof(events));
2556 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2557 if (ret < 0) {
2558 return ret;
2559 }
2560 env->exception_injected =
2561 events.exception.injected ? events.exception.nr : -1;
2562 env->has_error_code = events.exception.has_error_code;
2563 env->error_code = events.exception.error_code;
2564
2565 env->interrupt_injected =
2566 events.interrupt.injected ? events.interrupt.nr : -1;
2567 env->soft_interrupt = events.interrupt.soft;
2568
2569 env->nmi_injected = events.nmi.injected;
2570 env->nmi_pending = events.nmi.pending;
2571 if (events.nmi.masked) {
2572 env->hflags2 |= HF2_NMI_MASK;
2573 } else {
2574 env->hflags2 &= ~HF2_NMI_MASK;
2575 }
2576
2577 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2578 if (events.smi.smm) {
2579 env->hflags |= HF_SMM_MASK;
2580 } else {
2581 env->hflags &= ~HF_SMM_MASK;
2582 }
2583 if (events.smi.pending) {
2584 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2585 } else {
2586 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2587 }
2588 if (events.smi.smm_inside_nmi) {
2589 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2590 } else {
2591 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2592 }
2593 if (events.smi.latched_init) {
2594 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2595 } else {
2596 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2597 }
2598 }
2599
2600 env->sipi_vector = events.sipi_vector;
2601
2602 return 0;
2603 }
2604
2605 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2606 {
2607 CPUState *cs = CPU(cpu);
2608 CPUX86State *env = &cpu->env;
2609 int ret = 0;
2610 unsigned long reinject_trap = 0;
2611
2612 if (!kvm_has_vcpu_events()) {
2613 if (env->exception_injected == 1) {
2614 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2615 } else if (env->exception_injected == 3) {
2616 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2617 }
2618 env->exception_injected = -1;
2619 }
2620
2621 /*
2622 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2623 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2624 * by updating the debug state once again if single-stepping is on.
2625 * Another reason to call kvm_update_guest_debug here is a pending debug
2626 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2627 * reinject them via SET_GUEST_DEBUG.
2628 */
2629 if (reinject_trap ||
2630 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2631 ret = kvm_update_guest_debug(cs, reinject_trap);
2632 }
2633 return ret;
2634 }
2635
2636 static int kvm_put_debugregs(X86CPU *cpu)
2637 {
2638 CPUX86State *env = &cpu->env;
2639 struct kvm_debugregs dbgregs;
2640 int i;
2641
2642 if (!kvm_has_debugregs()) {
2643 return 0;
2644 }
2645
2646 for (i = 0; i < 4; i++) {
2647 dbgregs.db[i] = env->dr[i];
2648 }
2649 dbgregs.dr6 = env->dr[6];
2650 dbgregs.dr7 = env->dr[7];
2651 dbgregs.flags = 0;
2652
2653 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2654 }
2655
2656 static int kvm_get_debugregs(X86CPU *cpu)
2657 {
2658 CPUX86State *env = &cpu->env;
2659 struct kvm_debugregs dbgregs;
2660 int i, ret;
2661
2662 if (!kvm_has_debugregs()) {
2663 return 0;
2664 }
2665
2666 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2667 if (ret < 0) {
2668 return ret;
2669 }
2670 for (i = 0; i < 4; i++) {
2671 env->dr[i] = dbgregs.db[i];
2672 }
2673 env->dr[4] = env->dr[6] = dbgregs.dr6;
2674 env->dr[5] = env->dr[7] = dbgregs.dr7;
2675
2676 return 0;
2677 }
2678
2679 int kvm_arch_put_registers(CPUState *cpu, int level)
2680 {
2681 X86CPU *x86_cpu = X86_CPU(cpu);
2682 int ret;
2683
2684 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2685
2686 if (level >= KVM_PUT_RESET_STATE) {
2687 ret = kvm_put_msr_feature_control(x86_cpu);
2688 if (ret < 0) {
2689 return ret;
2690 }
2691 }
2692
2693 if (level == KVM_PUT_FULL_STATE) {
2694 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2695 * because TSC frequency mismatch shouldn't abort migration,
2696 * unless the user explicitly asked for a more strict TSC
2697 * setting (e.g. using an explicit "tsc-freq" option).
2698 */
2699 kvm_arch_set_tsc_khz(cpu);
2700 }
2701
2702 ret = kvm_getput_regs(x86_cpu, 1);
2703 if (ret < 0) {
2704 return ret;
2705 }
2706 ret = kvm_put_xsave(x86_cpu);
2707 if (ret < 0) {
2708 return ret;
2709 }
2710 ret = kvm_put_xcrs(x86_cpu);
2711 if (ret < 0) {
2712 return ret;
2713 }
2714 ret = kvm_put_sregs(x86_cpu);
2715 if (ret < 0) {
2716 return ret;
2717 }
2718 /* must be before kvm_put_msrs */
2719 ret = kvm_inject_mce_oldstyle(x86_cpu);
2720 if (ret < 0) {
2721 return ret;
2722 }
2723 ret = kvm_put_msrs(x86_cpu, level);
2724 if (ret < 0) {
2725 return ret;
2726 }
2727 if (level >= KVM_PUT_RESET_STATE) {
2728 ret = kvm_put_mp_state(x86_cpu);
2729 if (ret < 0) {
2730 return ret;
2731 }
2732 }
2733
2734 ret = kvm_put_tscdeadline_msr(x86_cpu);
2735 if (ret < 0) {
2736 return ret;
2737 }
2738
2739 ret = kvm_put_vcpu_events(x86_cpu, level);
2740 if (ret < 0) {
2741 return ret;
2742 }
2743 ret = kvm_put_debugregs(x86_cpu);
2744 if (ret < 0) {
2745 return ret;
2746 }
2747 /* must be last */
2748 ret = kvm_guest_debug_workarounds(x86_cpu);
2749 if (ret < 0) {
2750 return ret;
2751 }
2752 return 0;
2753 }
2754
2755 int kvm_arch_get_registers(CPUState *cs)
2756 {
2757 X86CPU *cpu = X86_CPU(cs);
2758 int ret;
2759
2760 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2761
2762 ret = kvm_getput_regs(cpu, 0);
2763 if (ret < 0) {
2764 goto out;
2765 }
2766 ret = kvm_get_xsave(cpu);
2767 if (ret < 0) {
2768 goto out;
2769 }
2770 ret = kvm_get_xcrs(cpu);
2771 if (ret < 0) {
2772 goto out;
2773 }
2774 ret = kvm_get_sregs(cpu);
2775 if (ret < 0) {
2776 goto out;
2777 }
2778 ret = kvm_get_msrs(cpu);
2779 if (ret < 0) {
2780 goto out;
2781 }
2782 ret = kvm_get_mp_state(cpu);
2783 if (ret < 0) {
2784 goto out;
2785 }
2786 ret = kvm_get_apic(cpu);
2787 if (ret < 0) {
2788 goto out;
2789 }
2790 ret = kvm_get_vcpu_events(cpu);
2791 if (ret < 0) {
2792 goto out;
2793 }
2794 ret = kvm_get_debugregs(cpu);
2795 if (ret < 0) {
2796 goto out;
2797 }
2798 ret = 0;
2799 out:
2800 cpu_sync_bndcs_hflags(&cpu->env);
2801 return ret;
2802 }
2803
2804 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2805 {
2806 X86CPU *x86_cpu = X86_CPU(cpu);
2807 CPUX86State *env = &x86_cpu->env;
2808 int ret;
2809
2810 /* Inject NMI */
2811 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2812 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2813 qemu_mutex_lock_iothread();
2814 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2815 qemu_mutex_unlock_iothread();
2816 DPRINTF("injected NMI\n");
2817 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2818 if (ret < 0) {
2819 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2820 strerror(-ret));
2821 }
2822 }
2823 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2824 qemu_mutex_lock_iothread();
2825 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2826 qemu_mutex_unlock_iothread();
2827 DPRINTF("injected SMI\n");
2828 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2829 if (ret < 0) {
2830 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2831 strerror(-ret));
2832 }
2833 }
2834 }
2835
2836 if (!kvm_pic_in_kernel()) {
2837 qemu_mutex_lock_iothread();
2838 }
2839
2840 /* Force the VCPU out of its inner loop to process any INIT requests
2841 * or (for userspace APIC, but it is cheap to combine the checks here)
2842 * pending TPR access reports.
2843 */
2844 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2845 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2846 !(env->hflags & HF_SMM_MASK)) {
2847 cpu->exit_request = 1;
2848 }
2849 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2850 cpu->exit_request = 1;
2851 }
2852 }
2853
2854 if (!kvm_pic_in_kernel()) {
2855 /* Try to inject an interrupt if the guest can accept it */
2856 if (run->ready_for_interrupt_injection &&
2857 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2858 (env->eflags & IF_MASK)) {
2859 int irq;
2860
2861 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2862 irq = cpu_get_pic_interrupt(env);
2863 if (irq >= 0) {
2864 struct kvm_interrupt intr;
2865
2866 intr.irq = irq;
2867 DPRINTF("injected interrupt %d\n", irq);
2868 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2869 if (ret < 0) {
2870 fprintf(stderr,
2871 "KVM: injection failed, interrupt lost (%s)\n",
2872 strerror(-ret));
2873 }
2874 }
2875 }
2876
2877 /* If we have an interrupt but the guest is not ready to receive an
2878 * interrupt, request an interrupt window exit. This will
2879 * cause a return to userspace as soon as the guest is ready to
2880 * receive interrupts. */
2881 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2882 run->request_interrupt_window = 1;
2883 } else {
2884 run->request_interrupt_window = 0;
2885 }
2886
2887 DPRINTF("setting tpr\n");
2888 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2889
2890 qemu_mutex_unlock_iothread();
2891 }
2892 }
2893
2894 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2895 {
2896 X86CPU *x86_cpu = X86_CPU(cpu);
2897 CPUX86State *env = &x86_cpu->env;
2898
2899 if (run->flags & KVM_RUN_X86_SMM) {
2900 env->hflags |= HF_SMM_MASK;
2901 } else {
2902 env->hflags &= ~HF_SMM_MASK;
2903 }
2904 if (run->if_flag) {
2905 env->eflags |= IF_MASK;
2906 } else {
2907 env->eflags &= ~IF_MASK;
2908 }
2909
2910 /* We need to protect the apic state against concurrent accesses from
2911 * different threads in case the userspace irqchip is used. */
2912 if (!kvm_irqchip_in_kernel()) {
2913 qemu_mutex_lock_iothread();
2914 }
2915 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2916 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2917 if (!kvm_irqchip_in_kernel()) {
2918 qemu_mutex_unlock_iothread();
2919 }
2920 return cpu_get_mem_attrs(env);
2921 }
2922
2923 int kvm_arch_process_async_events(CPUState *cs)
2924 {
2925 X86CPU *cpu = X86_CPU(cs);
2926 CPUX86State *env = &cpu->env;
2927
2928 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2929 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2930 assert(env->mcg_cap);
2931
2932 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2933
2934 kvm_cpu_synchronize_state(cs);
2935
2936 if (env->exception_injected == EXCP08_DBLE) {
2937 /* this means triple fault */
2938 qemu_system_reset_request();
2939 cs->exit_request = 1;
2940 return 0;
2941 }
2942 env->exception_injected = EXCP12_MCHK;
2943 env->has_error_code = 0;
2944
2945 cs->halted = 0;
2946 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2947 env->mp_state = KVM_MP_STATE_RUNNABLE;
2948 }
2949 }
2950
2951 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2952 !(env->hflags & HF_SMM_MASK)) {
2953 kvm_cpu_synchronize_state(cs);
2954 do_cpu_init(cpu);
2955 }
2956
2957 if (kvm_irqchip_in_kernel()) {
2958 return 0;
2959 }
2960
2961 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2962 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2963 apic_poll_irq(cpu->apic_state);
2964 }
2965 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2966 (env->eflags & IF_MASK)) ||
2967 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2968 cs->halted = 0;
2969 }
2970 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2971 kvm_cpu_synchronize_state(cs);
2972 do_cpu_sipi(cpu);
2973 }
2974 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2975 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2976 kvm_cpu_synchronize_state(cs);
2977 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2978 env->tpr_access_type);
2979 }
2980
2981 return cs->halted;
2982 }
2983
2984 static int kvm_handle_halt(X86CPU *cpu)
2985 {
2986 CPUState *cs = CPU(cpu);
2987 CPUX86State *env = &cpu->env;
2988
2989 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2990 (env->eflags & IF_MASK)) &&
2991 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2992 cs->halted = 1;
2993 return EXCP_HLT;
2994 }
2995
2996 return 0;
2997 }
2998
2999 static int kvm_handle_tpr_access(X86CPU *cpu)
3000 {
3001 CPUState *cs = CPU(cpu);
3002 struct kvm_run *run = cs->kvm_run;
3003
3004 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3005 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3006 : TPR_ACCESS_READ);
3007 return 1;
3008 }
3009
3010 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3011 {
3012 static const uint8_t int3 = 0xcc;
3013
3014 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3015 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3016 return -EINVAL;
3017 }
3018 return 0;
3019 }
3020
3021 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3022 {
3023 uint8_t int3;
3024
3025 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3026 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3027 return -EINVAL;
3028 }
3029 return 0;
3030 }
3031
3032 static struct {
3033 target_ulong addr;
3034 int len;
3035 int type;
3036 } hw_breakpoint[4];
3037
3038 static int nb_hw_breakpoint;
3039
3040 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3041 {
3042 int n;
3043
3044 for (n = 0; n < nb_hw_breakpoint; n++) {
3045 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3046 (hw_breakpoint[n].len == len || len == -1)) {
3047 return n;
3048 }
3049 }
3050 return -1;
3051 }
3052
3053 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3054 target_ulong len, int type)
3055 {
3056 switch (type) {
3057 case GDB_BREAKPOINT_HW:
3058 len = 1;
3059 break;
3060 case GDB_WATCHPOINT_WRITE:
3061 case GDB_WATCHPOINT_ACCESS:
3062 switch (len) {
3063 case 1:
3064 break;
3065 case 2:
3066 case 4:
3067 case 8:
3068 if (addr & (len - 1)) {
3069 return -EINVAL;
3070 }
3071 break;
3072 default:
3073 return -EINVAL;
3074 }
3075 break;
3076 default:
3077 return -ENOSYS;
3078 }
3079
3080 if (nb_hw_breakpoint == 4) {
3081 return -ENOBUFS;
3082 }
3083 if (find_hw_breakpoint(addr, len, type) >= 0) {
3084 return -EEXIST;
3085 }
3086 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3087 hw_breakpoint[nb_hw_breakpoint].len = len;
3088 hw_breakpoint[nb_hw_breakpoint].type = type;
3089 nb_hw_breakpoint++;
3090
3091 return 0;
3092 }
3093
3094 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3095 target_ulong len, int type)
3096 {
3097 int n;
3098
3099 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3100 if (n < 0) {
3101 return -ENOENT;
3102 }
3103 nb_hw_breakpoint--;
3104 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3105
3106 return 0;
3107 }
3108
3109 void kvm_arch_remove_all_hw_breakpoints(void)
3110 {
3111 nb_hw_breakpoint = 0;
3112 }
3113
3114 static CPUWatchpoint hw_watchpoint;
3115
3116 static int kvm_handle_debug(X86CPU *cpu,
3117 struct kvm_debug_exit_arch *arch_info)
3118 {
3119 CPUState *cs = CPU(cpu);
3120 CPUX86State *env = &cpu->env;
3121 int ret = 0;
3122 int n;
3123
3124 if (arch_info->exception == 1) {
3125 if (arch_info->dr6 & (1 << 14)) {
3126 if (cs->singlestep_enabled) {
3127 ret = EXCP_DEBUG;
3128 }
3129 } else {
3130 for (n = 0; n < 4; n++) {
3131 if (arch_info->dr6 & (1 << n)) {
3132 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3133 case 0x0:
3134 ret = EXCP_DEBUG;
3135 break;
3136 case 0x1:
3137 ret = EXCP_DEBUG;
3138 cs->watchpoint_hit = &hw_watchpoint;
3139 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3140 hw_watchpoint.flags = BP_MEM_WRITE;
3141 break;
3142 case 0x3:
3143 ret = EXCP_DEBUG;
3144 cs->watchpoint_hit = &hw_watchpoint;
3145 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3146 hw_watchpoint.flags = BP_MEM_ACCESS;
3147 break;
3148 }
3149 }
3150 }
3151 }
3152 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3153 ret = EXCP_DEBUG;
3154 }
3155 if (ret == 0) {
3156 cpu_synchronize_state(cs);
3157 assert(env->exception_injected == -1);
3158
3159 /* pass to guest */
3160 env->exception_injected = arch_info->exception;
3161 env->has_error_code = 0;
3162 }
3163
3164 return ret;
3165 }
3166
3167 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3168 {
3169 const uint8_t type_code[] = {
3170 [GDB_BREAKPOINT_HW] = 0x0,
3171 [GDB_WATCHPOINT_WRITE] = 0x1,
3172 [GDB_WATCHPOINT_ACCESS] = 0x3
3173 };
3174 const uint8_t len_code[] = {
3175 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3176 };
3177 int n;
3178
3179 if (kvm_sw_breakpoints_active(cpu)) {
3180 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3181 }
3182 if (nb_hw_breakpoint > 0) {
3183 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3184 dbg->arch.debugreg[7] = 0x0600;
3185 for (n = 0; n < nb_hw_breakpoint; n++) {
3186 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3187 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3188 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3189 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3190 }
3191 }
3192 }
3193
3194 static bool host_supports_vmx(void)
3195 {
3196 uint32_t ecx, unused;
3197
3198 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3199 return ecx & CPUID_EXT_VMX;
3200 }
3201
3202 #define VMX_INVALID_GUEST_STATE 0x80000021
3203
3204 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3205 {
3206 X86CPU *cpu = X86_CPU(cs);
3207 uint64_t code;
3208 int ret;
3209
3210 switch (run->exit_reason) {
3211 case KVM_EXIT_HLT:
3212 DPRINTF("handle_hlt\n");
3213 qemu_mutex_lock_iothread();
3214 ret = kvm_handle_halt(cpu);
3215 qemu_mutex_unlock_iothread();
3216 break;
3217 case KVM_EXIT_SET_TPR:
3218 ret = 0;
3219 break;
3220 case KVM_EXIT_TPR_ACCESS:
3221 qemu_mutex_lock_iothread();
3222 ret = kvm_handle_tpr_access(cpu);
3223 qemu_mutex_unlock_iothread();
3224 break;
3225 case KVM_EXIT_FAIL_ENTRY:
3226 code = run->fail_entry.hardware_entry_failure_reason;
3227 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3228 code);
3229 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3230 fprintf(stderr,
3231 "\nIf you're running a guest on an Intel machine without "
3232 "unrestricted mode\n"
3233 "support, the failure can be most likely due to the guest "
3234 "entering an invalid\n"
3235 "state for Intel VT. For example, the guest maybe running "
3236 "in big real mode\n"
3237 "which is not supported on less recent Intel processors."
3238 "\n\n");
3239 }
3240 ret = -1;
3241 break;
3242 case KVM_EXIT_EXCEPTION:
3243 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3244 run->ex.exception, run->ex.error_code);
3245 ret = -1;
3246 break;
3247 case KVM_EXIT_DEBUG:
3248 DPRINTF("kvm_exit_debug\n");
3249 qemu_mutex_lock_iothread();
3250 ret = kvm_handle_debug(cpu, &run->debug.arch);
3251 qemu_mutex_unlock_iothread();
3252 break;
3253 case KVM_EXIT_HYPERV:
3254 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3255 break;
3256 case KVM_EXIT_IOAPIC_EOI:
3257 ioapic_eoi_broadcast(run->eoi.vector);
3258 ret = 0;
3259 break;
3260 default:
3261 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3262 ret = -1;
3263 break;
3264 }
3265
3266 return ret;
3267 }
3268
3269 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3270 {
3271 X86CPU *cpu = X86_CPU(cs);
3272 CPUX86State *env = &cpu->env;
3273
3274 kvm_cpu_synchronize_state(cs);
3275 return !(env->cr[0] & CR0_PE_MASK) ||
3276 ((env->segs[R_CS].selector & 3) != 3);
3277 }
3278
3279 void kvm_arch_init_irq_routing(KVMState *s)
3280 {
3281 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3282 /* If kernel can't do irq routing, interrupt source
3283 * override 0->2 cannot be set up as required by HPET.
3284 * So we have to disable it.
3285 */
3286 no_hpet = 1;
3287 }
3288 /* We know at this point that we're using the in-kernel
3289 * irqchip, so we can use irqfds, and on x86 we know
3290 * we can use msi via irqfd and GSI routing.
3291 */
3292 kvm_msi_via_irqfd_allowed = true;
3293 kvm_gsi_routing_allowed = true;
3294
3295 if (kvm_irqchip_is_split()) {
3296 int i;
3297
3298 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3299 MSI routes for signaling interrupts to the local apics. */
3300 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3301 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3302 error_report("Could not enable split IRQ mode.");
3303 exit(1);
3304 }
3305 }
3306 }
3307 }
3308
3309 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3310 {
3311 int ret;
3312 if (machine_kernel_irqchip_split(ms)) {
3313 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3314 if (ret) {
3315 error_report("Could not enable split irqchip mode: %s",
3316 strerror(-ret));
3317 exit(1);
3318 } else {
3319 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3320 kvm_split_irqchip = true;
3321 return 1;
3322 }
3323 } else {
3324 return 0;
3325 }
3326 }
3327
3328 /* Classic KVM device assignment interface. Will remain x86 only. */
3329 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3330 uint32_t flags, uint32_t *dev_id)
3331 {
3332 struct kvm_assigned_pci_dev dev_data = {
3333 .segnr = dev_addr->domain,
3334 .busnr = dev_addr->bus,
3335 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3336 .flags = flags,
3337 };
3338 int ret;
3339
3340 dev_data.assigned_dev_id =
3341 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3342
3343 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3344 if (ret < 0) {
3345 return ret;
3346 }
3347
3348 *dev_id = dev_data.assigned_dev_id;
3349
3350 return 0;
3351 }
3352
3353 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3354 {
3355 struct kvm_assigned_pci_dev dev_data = {
3356 .assigned_dev_id = dev_id,
3357 };
3358
3359 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3360 }
3361
3362 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3363 uint32_t irq_type, uint32_t guest_irq)
3364 {
3365 struct kvm_assigned_irq assigned_irq = {
3366 .assigned_dev_id = dev_id,
3367 .guest_irq = guest_irq,
3368 .flags = irq_type,
3369 };
3370
3371 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3372 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3373 } else {
3374 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3375 }
3376 }
3377
3378 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3379 uint32_t guest_irq)
3380 {
3381 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3382 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3383
3384 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3385 }
3386
3387 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3388 {
3389 struct kvm_assigned_pci_dev dev_data = {
3390 .assigned_dev_id = dev_id,
3391 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3392 };
3393
3394 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3395 }
3396
3397 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3398 uint32_t type)
3399 {
3400 struct kvm_assigned_irq assigned_irq = {
3401 .assigned_dev_id = dev_id,
3402 .flags = type,
3403 };
3404
3405 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3406 }
3407
3408 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3409 {
3410 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3411 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3412 }
3413
3414 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3415 {
3416 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3417 KVM_DEV_IRQ_GUEST_MSI, virq);
3418 }
3419
3420 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3421 {
3422 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3423 KVM_DEV_IRQ_HOST_MSI);
3424 }
3425
3426 bool kvm_device_msix_supported(KVMState *s)
3427 {
3428 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3429 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3430 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3431 }
3432
3433 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3434 uint32_t nr_vectors)
3435 {
3436 struct kvm_assigned_msix_nr msix_nr = {
3437 .assigned_dev_id = dev_id,
3438 .entry_nr = nr_vectors,
3439 };
3440
3441 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3442 }
3443
3444 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3445 int virq)
3446 {
3447 struct kvm_assigned_msix_entry msix_entry = {
3448 .assigned_dev_id = dev_id,
3449 .gsi = virq,
3450 .entry = vector,
3451 };
3452
3453 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3454 }
3455
3456 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3457 {
3458 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3459 KVM_DEV_IRQ_GUEST_MSIX, 0);
3460 }
3461
3462 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3463 {
3464 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3465 KVM_DEV_IRQ_HOST_MSIX);
3466 }
3467
3468 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3469 uint64_t address, uint32_t data, PCIDevice *dev)
3470 {
3471 X86IOMMUState *iommu = x86_iommu_get_default();
3472
3473 if (iommu) {
3474 int ret;
3475 MSIMessage src, dst;
3476 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3477
3478 src.address = route->u.msi.address_hi;
3479 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3480 src.address |= route->u.msi.address_lo;
3481 src.data = route->u.msi.data;
3482
3483 ret = class->int_remap(iommu, &src, &dst, dev ? \
3484 pci_requester_id(dev) : \
3485 X86_IOMMU_SID_INVALID);
3486 if (ret) {
3487 trace_kvm_x86_fixup_msi_error(route->gsi);
3488 return 1;
3489 }
3490
3491 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3492 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3493 route->u.msi.data = dst.data;
3494 }
3495
3496 return 0;
3497 }
3498
3499 typedef struct MSIRouteEntry MSIRouteEntry;
3500
3501 struct MSIRouteEntry {
3502 PCIDevice *dev; /* Device pointer */
3503 int vector; /* MSI/MSIX vector index */
3504 int virq; /* Virtual IRQ index */
3505 QLIST_ENTRY(MSIRouteEntry) list;
3506 };
3507
3508 /* List of used GSI routes */
3509 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3510 QLIST_HEAD_INITIALIZER(msi_route_list);
3511
3512 static void kvm_update_msi_routes_all(void *private, bool global,
3513 uint32_t index, uint32_t mask)
3514 {
3515 int cnt = 0;
3516 MSIRouteEntry *entry;
3517 MSIMessage msg;
3518 /* TODO: explicit route update */
3519 QLIST_FOREACH(entry, &msi_route_list, list) {
3520 cnt++;
3521 msg = pci_get_msi_message(entry->dev, entry->vector);
3522 kvm_irqchip_update_msi_route(kvm_state, entry->virq,
3523 msg, entry->dev);
3524 }
3525 kvm_irqchip_commit_routes(kvm_state);
3526 trace_kvm_x86_update_msi_routes(cnt);
3527 }
3528
3529 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3530 int vector, PCIDevice *dev)
3531 {
3532 static bool notify_list_inited = false;
3533 MSIRouteEntry *entry;
3534
3535 if (!dev) {
3536 /* These are (possibly) IOAPIC routes only used for split
3537 * kernel irqchip mode, while what we are housekeeping are
3538 * PCI devices only. */
3539 return 0;
3540 }
3541
3542 entry = g_new0(MSIRouteEntry, 1);
3543 entry->dev = dev;
3544 entry->vector = vector;
3545 entry->virq = route->gsi;
3546 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3547
3548 trace_kvm_x86_add_msi_route(route->gsi);
3549
3550 if (!notify_list_inited) {
3551 /* For the first time we do add route, add ourselves into
3552 * IOMMU's IEC notify list if needed. */
3553 X86IOMMUState *iommu = x86_iommu_get_default();
3554 if (iommu) {
3555 x86_iommu_iec_register_notifier(iommu,
3556 kvm_update_msi_routes_all,
3557 NULL);
3558 }
3559 notify_list_inited = true;
3560 }
3561 return 0;
3562 }
3563
3564 int kvm_arch_release_virq_post(int virq)
3565 {
3566 MSIRouteEntry *entry, *next;
3567 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3568 if (entry->virq == virq) {
3569 trace_kvm_x86_remove_msi_route(virq);
3570 QLIST_REMOVE(entry, list);
3571 break;
3572 }
3573 }
3574 return 0;
3575 }
3576
3577 int kvm_arch_msi_data_to_gsi(uint32_t data)
3578 {
3579 abort();
3580 }
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