target/i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "qapi/error.h"
  17 #include <sys/ioctl.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include "standard-headers/asm-x86/kvm_para.h"
  22
  23 #include "qemu-common.h"
  24 #include "cpu.h"
  25 #include "sysemu/sysemu.h"
  26 #include "sysemu/hw_accel.h"
  27 #include "sysemu/kvm_int.h"
  28 #include "kvm_i386.h"
  29 #include "hyperv.h"
  30 #include "hyperv-proto.h"
  31
  32 #include "exec/gdbstub.h"
  33 #include "qemu/host-utils.h"
  34 #include "qemu/config-file.h"
  35 #include "qemu/error-report.h"
  36 #include "hw/i386/pc.h"
  37 #include "hw/i386/apic.h"
  38 #include "hw/i386/apic_internal.h"
  39 #include "hw/i386/apic-msidef.h"
  40 #include "hw/i386/intel_iommu.h"
  41 #include "hw/i386/x86-iommu.h"
  42
  43 #include "hw/pci/pci.h"
  44 #include "hw/pci/msi.h"
  45 #include "hw/pci/msix.h"
  46 #include "migration/blocker.h"
  47 #include "exec/memattrs.h"
  48 #include "trace.h"
  49
  50 //#define DEBUG_KVM
  51
  52 #ifdef DEBUG_KVM
  53 #define DPRINTF(fmt, ...) \
  54     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  55 #else
  56 #define DPRINTF(fmt, ...) \
  57     do { } while (0)
  58 #endif
  59
  60 #define MSR_KVM_WALL_CLOCK  0x11
  61 #define MSR_KVM_SYSTEM_TIME 0x12
  62
  63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
  64  * 255 kvm_msr_entry structs */
  65 #define MSR_BUF_SIZE 4096
  66
  67 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  68     KVM_CAP_INFO(SET_TSS_ADDR),
  69     KVM_CAP_INFO(EXT_CPUID),
  70     KVM_CAP_INFO(MP_STATE),
  71     KVM_CAP_LAST_INFO
  72 };
  73
  74 static bool has_msr_star;
  75 static bool has_msr_hsave_pa;
  76 static bool has_msr_tsc_aux;
  77 static bool has_msr_tsc_adjust;
  78 static bool has_msr_tsc_deadline;
  79 static bool has_msr_feature_control;
  80 static bool has_msr_misc_enable;
  81 static bool has_msr_smbase;
  82 static bool has_msr_bndcfgs;
  83 static int lm_capable_kernel;
  84 static bool has_msr_hv_hypercall;
  85 static bool has_msr_hv_crash;
  86 static bool has_msr_hv_reset;
  87 static bool has_msr_hv_vpindex;
  88 static bool hv_vpindex_settable;
  89 static bool has_msr_hv_runtime;
  90 static bool has_msr_hv_synic;
  91 static bool has_msr_hv_stimer;
  92 static bool has_msr_hv_frequencies;
  93 static bool has_msr_hv_reenlightenment;
  94 static bool has_msr_xss;
  95 static bool has_msr_spec_ctrl;
  96 static bool has_msr_virt_ssbd;
  97 static bool has_msr_smi_count;
  98 static bool has_msr_arch_capabs;
  99
 100 static uint32_t has_architectural_pmu_version;
 101 static uint32_t num_architectural_pmu_gp_counters;
 102 static uint32_t num_architectural_pmu_fixed_counters;
 103
 104 static int has_xsave;
 105 static int has_xcrs;
 106 static int has_pit_state2;
 107
 108 static bool has_msr_mcg_ext_ctl;
 109
 110 static struct kvm_cpuid2 *cpuid_cache;
 111 static struct kvm_msr_list *kvm_feature_msrs;
 112
 113 int kvm_has_pit_state2(void)
 114 {
 115     return has_pit_state2;
 116 }
 117
 118 bool kvm_has_smm(void)
 119 {
 120     return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
 121 }
 122
 123 bool kvm_has_adjust_clock_stable(void)
 124 {
 125     int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
 126
 127     return (ret == KVM_CLOCK_TSC_STABLE);
 128 }
 129
 130 bool kvm_allows_irq0_override(void)
 131 {
 132     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
 133 }
 134
 135 static bool kvm_x2apic_api_set_flags(uint64_t flags)
 136 {
 137     KVMState *s = KVM_STATE(current_machine->accelerator);
 138
 139     return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
 140 }
 141
 142 #define MEMORIZE(fn, _result) \
 143     ({ \
 144         static bool _memorized; \
 145         \
 146         if (_memorized) { \
 147             return _result; \
 148         } \
 149         _memorized = true; \
 150         _result = fn; \
 151     })
 152
 153 static bool has_x2apic_api;
 154
 155 bool kvm_has_x2apic_api(void)
 156 {
 157     return has_x2apic_api;
 158 }
 159
 160 bool kvm_enable_x2apic(void)
 161 {
 162     return MEMORIZE(
 163              kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
 164                                       KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
 165              has_x2apic_api);
 166 }
 167
 168 bool kvm_hv_vpindex_settable(void)
 169 {
 170     return hv_vpindex_settable;
 171 }
 172
 173 static int kvm_get_tsc(CPUState *cs)
 174 {
 175     X86CPU *cpu = X86_CPU(cs);
 176     CPUX86State *env = &cpu->env;
 177     struct {
 178         struct kvm_msrs info;
 179         struct kvm_msr_entry entries[1];
 180     } msr_data;
 181     int ret;
 182
 183     if (env->tsc_valid) {
 184         return 0;
 185     }
 186
 187     msr_data.info.nmsrs = 1;
 188     msr_data.entries[0].index = MSR_IA32_TSC;
 189     env->tsc_valid = !runstate_is_running();
 190
 191     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
 192     if (ret < 0) {
 193         return ret;
 194     }
 195
 196     assert(ret == 1);
 197     env->tsc = msr_data.entries[0].data;
 198     return 0;
 199 }
 200
 201 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
 202 {
 203     kvm_get_tsc(cpu);
 204 }
 205
 206 void kvm_synchronize_all_tsc(void)
 207 {
 208     CPUState *cpu;
 209
 210     if (kvm_enabled()) {
 211         CPU_FOREACH(cpu) {
 212             run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
 213         }
 214     }
 215 }
 216
 217 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
 218 {
 219     struct kvm_cpuid2 *cpuid;
 220     int r, size;
 221
 222     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
 223     cpuid = g_malloc0(size);
 224     cpuid->nent = max;
 225     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
 226     if (r == 0 && cpuid->nent >= max) {
 227         r = -E2BIG;
 228     }
 229     if (r < 0) {
 230         if (r == -E2BIG) {
 231             g_free(cpuid);
 232             return NULL;
 233         } else {
 234             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
 235                     strerror(-r));
 236             exit(1);
 237         }
 238     }
 239     return cpuid;
 240 }
 241
 242 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 243  * for all entries.
 244  */
 245 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 246 {
 247     struct kvm_cpuid2 *cpuid;
 248     int max = 1;
 249
 250     if (cpuid_cache != NULL) {
 251         return cpuid_cache;
 252     }
 253     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 254         max *= 2;
 255     }
 256     cpuid_cache = cpuid;
 257     return cpuid;
 258 }
 259
 260 static const struct kvm_para_features {
 261     int cap;
 262     int feature;
 263 } para_features[] = {
 264     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 265     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 266     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 267     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 268 };
 269
 270 static int get_para_features(KVMState *s)
 271 {
 272     int i, features = 0;
 273
 274     for (i = 0; i < ARRAY_SIZE(para_features); i++) {
 275         if (kvm_check_extension(s, para_features[i].cap)) {
 276             features |= (1 << para_features[i].feature);
 277         }
 278     }
 279
 280     return features;
 281 }
 282
 283 static bool host_tsx_blacklisted(void)
 284 {
 285     int family, model, stepping;\
 286     char vendor[CPUID_VENDOR_SZ + 1];
 287
 288     host_vendor_fms(vendor, &family, &model, &stepping);
 289
 290     /* Check if we are running on a Haswell host known to have broken TSX */
 291     return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
 292            (family == 6) &&
 293            ((model == 63 && stepping < 4) ||
 294             model == 60 || model == 69 || model == 70);
 295 }
 296
 297 /* Returns the value for a specific register on the cpuid entry
 298  */
 299 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 300 {
 301     uint32_t ret = 0;
 302     switch (reg) {
 303     case R_EAX:
 304         ret = entry->eax;
 305         break;
 306     case R_EBX:
 307         ret = entry->ebx;
 308         break;
 309     case R_ECX:
 310         ret = entry->ecx;
 311         break;
 312     case R_EDX:
 313         ret = entry->edx;
 314         break;
 315     }
 316     return ret;
 317 }
 318
 319 /* Find matching entry for function/index on kvm_cpuid2 struct
 320  */
 321 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 322                                                  uint32_t function,
 323                                                  uint32_t index)
 324 {
 325     int i;
 326     for (i = 0; i < cpuid->nent; ++i) {
 327         if (cpuid->entries[i].function == function &&
 328             cpuid->entries[i].index == index) {
 329             return &cpuid->entries[i];
 330         }
 331     }
 332     /* not found: */
 333     return NULL;
 334 }
 335
 336 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 337                                       uint32_t index, int reg)
 338 {
 339     struct kvm_cpuid2 *cpuid;
 340     uint32_t ret = 0;
 341     uint32_t cpuid_1_edx;
 342     bool found = false;
 343
 344     cpuid = get_supported_cpuid(s);
 345
 346     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 347     if (entry) {
 348         found = true;
 349         ret = cpuid_entry_get_reg(entry, reg);
 350     }
 351
 352     /* Fixups for the data returned by KVM, below */
 353
 354     if (function == 1 && reg == R_EDX) {
 355         /* KVM before 2.6.30 misreports the following features */
 356         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 357     } else if (function == 1 && reg == R_ECX) {
 358         /* We can set the hypervisor flag, even if KVM does not return it on
 359          * GET_SUPPORTED_CPUID
 360          */
 361         ret |= CPUID_EXT_HYPERVISOR;
 362         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 363          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 364          * and the irqchip is in the kernel.
 365          */
 366         if (kvm_irqchip_in_kernel() &&
 367                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 368             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 369         }
 370
 371         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 372          * without the in-kernel irqchip
 373          */
 374         if (!kvm_irqchip_in_kernel()) {
 375             ret &= ~CPUID_EXT_X2APIC;
 376         }
 377
 378         if (enable_cpu_pm) {
 379             int disable_exits = kvm_check_extension(s,
 380                                                     KVM_CAP_X86_DISABLE_EXITS);
 381
 382             if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
 383                 ret |= CPUID_EXT_MONITOR;
 384             }
 385         }
 386     } else if (function == 6 && reg == R_EAX) {
 387         ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
 388     } else if (function == 7 && index == 0 && reg == R_EBX) {
 389         if (host_tsx_blacklisted()) {
 390             ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
 391         }
 392     } else if (function == 0x80000001 && reg == R_ECX) {
 393         /*
 394          * It's safe to enable TOPOEXT even if it's not returned by
 395          * GET_SUPPORTED_CPUID.  Unconditionally enabling TOPOEXT here allows
 396          * us to keep CPU models including TOPOEXT runnable on older kernels.
 397          */
 398         ret |= CPUID_EXT3_TOPOEXT;
 399     } else if (function == 0x80000001 && reg == R_EDX) {
 400         /* On Intel, kvm returns cpuid according to the Intel spec,
 401          * so add missing bits according to the AMD spec:
 402          */
 403         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 404         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 405     } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
 406         /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
 407          * be enabled without the in-kernel irqchip
 408          */
 409         if (!kvm_irqchip_in_kernel()) {
 410             ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
 411         }
 412     } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
 413         ret |= 1U << KVM_HINTS_REALTIME;
 414         found = 1;
 415     }
 416
 417     /* fallback for older kernels */
 418     if ((function == KVM_CPUID_FEATURES) && !found) {
 419         ret = get_para_features(s);
 420     }
 421
 422     return ret;
 423 }
 424
 425 uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
 426 {
 427     struct {
 428         struct kvm_msrs info;
 429         struct kvm_msr_entry entries[1];
 430     } msr_data;
 431     uint32_t ret;
 432
 433     if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
 434         return 0;
 435     }
 436
 437     /* Check if requested MSR is supported feature MSR */
 438     int i;
 439     for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
 440         if (kvm_feature_msrs->indices[i] == index) {
 441             break;
 442         }
 443     if (i == kvm_feature_msrs->nmsrs) {
 444         return 0; /* if the feature MSR is not supported, simply return 0 */
 445     }
 446
 447     msr_data.info.nmsrs = 1;
 448     msr_data.entries[0].index = index;
 449
 450     ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
 451     if (ret != 1) {
 452         error_report("KVM get MSR (index=0x%x) feature failed, %s",
 453             index, strerror(-ret));
 454         exit(1);
 455     }
 456
 457     return msr_data.entries[0].data;
 458 }
 459
 460
 461 typedef struct HWPoisonPage {
 462     ram_addr_t ram_addr;
 463     QLIST_ENTRY(HWPoisonPage) list;
 464 } HWPoisonPage;
 465
 466 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 467     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 468
 469 static void kvm_unpoison_all(void *param)
 470 {
 471     HWPoisonPage *page, *next_page;
 472
 473     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 474         QLIST_REMOVE(page, list);
 475         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 476         g_free(page);
 477     }
 478 }
 479
 480 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 481 {
 482     HWPoisonPage *page;
 483
 484     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 485         if (page->ram_addr == ram_addr) {
 486             return;
 487         }
 488     }
 489     page = g_new(HWPoisonPage, 1);
 490     page->ram_addr = ram_addr;
 491     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 492 }
 493
 494 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 495                                      int *max_banks)
 496 {
 497     int r;
 498
 499     r = kvm_check_extension(s, KVM_CAP_MCE);
 500     if (r > 0) {
 501         *max_banks = r;
 502         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 503     }
 504     return -ENOSYS;
 505 }
 506
 507 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
 508 {
 509     CPUState *cs = CPU(cpu);
 510     CPUX86State *env = &cpu->env;
 511     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 512                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 513     uint64_t mcg_status = MCG_STATUS_MCIP;
 514     int flags = 0;
 515
 516     if (code == BUS_MCEERR_AR) {
 517         status |= MCI_STATUS_AR | 0x134;
 518         mcg_status |= MCG_STATUS_EIPV;
 519     } else {
 520         status |= 0xc0;
 521         mcg_status |= MCG_STATUS_RIPV;
 522     }
 523
 524     flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
 525     /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
 526      * guest kernel back into env->mcg_ext_ctl.
 527      */
 528     cpu_synchronize_state(cs);
 529     if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
 530         mcg_status |= MCG_STATUS_LMCE;
 531         flags = 0;
 532     }
 533
 534     cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
 535                        (MCM_ADDR_PHYS << 6) | 0xc, flags);
 536 }
 537
 538 static void hardware_memory_error(void)
 539 {
 540     fprintf(stderr, "Hardware memory error!\n");
 541     exit(1);
 542 }
 543
 544 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
 545 {
 546     X86CPU *cpu = X86_CPU(c);
 547     CPUX86State *env = &cpu->env;
 548     ram_addr_t ram_addr;
 549     hwaddr paddr;
 550
 551     /* If we get an action required MCE, it has been injected by KVM
 552      * while the VM was running.  An action optional MCE instead should
 553      * be coming from the main thread, which qemu_init_sigbus identifies
 554      * as the "early kill" thread.
 555      */
 556     assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
 557
 558     if ((env->mcg_cap & MCG_SER_P) && addr) {
 559         ram_addr = qemu_ram_addr_from_host(addr);
 560         if (ram_addr != RAM_ADDR_INVALID &&
 561             kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
 562             kvm_hwpoison_page_add(ram_addr);
 563             kvm_mce_inject(cpu, paddr, code);
 564             return;
 565         }
 566
 567         fprintf(stderr, "Hardware memory error for memory used by "
 568                 "QEMU itself instead of guest system!\n");
 569     }
 570
 571     if (code == BUS_MCEERR_AR) {
 572         hardware_memory_error();
 573     }
 574
 575     /* Hope we are lucky for AO MCE */
 576 }
 577
 578 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
 579 {
 580     CPUX86State *env = &cpu->env;
 581
 582     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 583         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 584         struct kvm_x86_mce mce;
 585
 586         env->exception_injected = -1;
 587
 588         /*
 589          * There must be at least one bank in use if an MCE is pending.
 590          * Find it and use its values for the event injection.
 591          */
 592         for (bank = 0; bank < bank_num; bank++) {
 593             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 594                 break;
 595             }
 596         }
 597         assert(bank < bank_num);
 598
 599         mce.bank = bank;
 600         mce.status = env->mce_banks[bank * 4 + 1];
 601         mce.mcg_status = env->mcg_status;
 602         mce.addr = env->mce_banks[bank * 4 + 2];
 603         mce.misc = env->mce_banks[bank * 4 + 3];
 604
 605         return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
 606     }
 607     return 0;
 608 }
 609
 610 static void cpu_update_state(void *opaque, int running, RunState state)
 611 {
 612     CPUX86State *env = opaque;
 613
 614     if (running) {
 615         env->tsc_valid = false;
 616     }
 617 }
 618
 619 unsigned long kvm_arch_vcpu_id(CPUState *cs)
 620 {
 621     X86CPU *cpu = X86_CPU(cs);
 622     return cpu->apic_id;
 623 }
 624
 625 #ifndef KVM_CPUID_SIGNATURE_NEXT
 626 #define KVM_CPUID_SIGNATURE_NEXT                0x40000100
 627 #endif
 628
 629 static bool hyperv_hypercall_available(X86CPU *cpu)
 630 {
 631     return cpu->hyperv_vapic ||
 632            (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
 633 }
 634
 635 static bool hyperv_enabled(X86CPU *cpu)
 636 {
 637     CPUState *cs = CPU(cpu);
 638     return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
 639            (hyperv_hypercall_available(cpu) ||
 640             cpu->hyperv_time  ||
 641             cpu->hyperv_relaxed_timing ||
 642             cpu->hyperv_crash ||
 643             cpu->hyperv_reset ||
 644             cpu->hyperv_vpindex ||
 645             cpu->hyperv_runtime ||
 646             cpu->hyperv_synic ||
 647             cpu->hyperv_stimer ||
 648             cpu->hyperv_reenlightenment ||
 649             cpu->hyperv_tlbflush ||
 650             cpu->hyperv_ipi);
 651 }
 652
 653 static int kvm_arch_set_tsc_khz(CPUState *cs)
 654 {
 655     X86CPU *cpu = X86_CPU(cs);
 656     CPUX86State *env = &cpu->env;
 657     int r;
 658
 659     if (!env->tsc_khz) {
 660         return 0;
 661     }
 662
 663     r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
 664         kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
 665         -ENOTSUP;
 666     if (r < 0) {
 667         /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
 668          * TSC frequency doesn't match the one we want.
 669          */
 670         int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
 671                        kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
 672                        -ENOTSUP;
 673         if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
 674             warn_report("TSC frequency mismatch between "
 675                         "VM (%" PRId64 " kHz) and host (%d kHz), "
 676                         "and TSC scaling unavailable",
 677                         env->tsc_khz, cur_freq);
 678             return r;
 679         }
 680     }
 681
 682     return 0;
 683 }
 684
 685 static bool tsc_is_stable_and_known(CPUX86State *env)
 686 {
 687     if (!env->tsc_khz) {
 688         return false;
 689     }
 690     return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
 691         || env->user_tsc_khz;
 692 }
 693
 694 static int hyperv_handle_properties(CPUState *cs)
 695 {
 696     X86CPU *cpu = X86_CPU(cs);
 697     CPUX86State *env = &cpu->env;
 698
 699     if (cpu->hyperv_relaxed_timing) {
 700         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 701     }
 702     if (cpu->hyperv_vapic) {
 703         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 704         env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
 705     }
 706     if (cpu->hyperv_time) {
 707         if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
 708             fprintf(stderr, "Hyper-V clocksources "
 709                     "(requested by 'hv-time' cpu flag) "
 710                     "are not supported by kernel\n");
 711             return -ENOSYS;
 712         }
 713         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 714         env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
 715         env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
 716     }
 717     if (cpu->hyperv_frequencies) {
 718         if (!has_msr_hv_frequencies) {
 719             fprintf(stderr, "Hyper-V frequency MSRs "
 720                     "(requested by 'hv-frequencies' cpu flag) "
 721                     "are not supported by kernel\n");
 722             return -ENOSYS;
 723         }
 724         env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
 725         env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
 726     }
 727     if (cpu->hyperv_crash) {
 728         if (!has_msr_hv_crash) {
 729             fprintf(stderr, "Hyper-V crash MSRs "
 730                     "(requested by 'hv-crash' cpu flag) "
 731                     "are not supported by kernel\n");
 732             return -ENOSYS;
 733         }
 734         env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
 735     }
 736     if (cpu->hyperv_reenlightenment) {
 737         if (!has_msr_hv_reenlightenment) {
 738             fprintf(stderr,
 739                     "Hyper-V Reenlightenment MSRs "
 740                     "(requested by 'hv-reenlightenment' cpu flag) "
 741                     "are not supported by kernel\n");
 742             return -ENOSYS;
 743         }
 744         env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
 745     }
 746     env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
 747     if (cpu->hyperv_reset) {
 748         if (!has_msr_hv_reset) {
 749             fprintf(stderr, "Hyper-V reset MSR "
 750                     "(requested by 'hv-reset' cpu flag) "
 751                     "is not supported by kernel\n");
 752             return -ENOSYS;
 753         }
 754         env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
 755     }
 756     if (cpu->hyperv_vpindex) {
 757         if (!has_msr_hv_vpindex) {
 758             fprintf(stderr, "Hyper-V VP_INDEX MSR "
 759                     "(requested by 'hv-vpindex' cpu flag) "
 760                     "is not supported by kernel\n");
 761             return -ENOSYS;
 762         }
 763         env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
 764     }
 765     if (cpu->hyperv_runtime) {
 766         if (!has_msr_hv_runtime) {
 767             fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
 768                     "(requested by 'hv-runtime' cpu flag) "
 769                     "is not supported by kernel\n");
 770             return -ENOSYS;
 771         }
 772         env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
 773     }
 774     if (cpu->hyperv_synic) {
 775         unsigned int cap = KVM_CAP_HYPERV_SYNIC;
 776         if (!cpu->hyperv_synic_kvm_only) {
 777             if (!cpu->hyperv_vpindex) {
 778                 fprintf(stderr, "Hyper-V SynIC "
 779                         "(requested by 'hv-synic' cpu flag) "
 780                         "requires Hyper-V VP_INDEX ('hv-vpindex')\n");
 781             return -ENOSYS;
 782             }
 783             cap = KVM_CAP_HYPERV_SYNIC2;
 784         }
 785
 786         if (!has_msr_hv_synic || !kvm_check_extension(cs->kvm_state, cap)) {
 787             fprintf(stderr, "Hyper-V SynIC (requested by 'hv-synic' cpu flag) "
 788                     "is not supported by kernel\n");
 789             return -ENOSYS;
 790         }
 791
 792         env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
 793     }
 794     if (cpu->hyperv_stimer) {
 795         if (!has_msr_hv_stimer) {
 796             fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
 797             return -ENOSYS;
 798         }
 799         env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
 800     }
 801     return 0;
 802 }
 803
 804 static int hyperv_init_vcpu(X86CPU *cpu)
 805 {
 806     CPUState *cs = CPU(cpu);
 807     int ret;
 808
 809     if (cpu->hyperv_vpindex && !hv_vpindex_settable) {
 810         /*
 811          * the kernel doesn't support setting vp_index; assert that its value
 812          * is in sync
 813          */
 814         struct {
 815             struct kvm_msrs info;
 816             struct kvm_msr_entry entries[1];
 817         } msr_data = {
 818             .info.nmsrs = 1,
 819             .entries[0].index = HV_X64_MSR_VP_INDEX,
 820         };
 821
 822         ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
 823         if (ret < 0) {
 824             return ret;
 825         }
 826         assert(ret == 1);
 827
 828         if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
 829             error_report("kernel's vp_index != QEMU's vp_index");
 830             return -ENXIO;
 831         }
 832     }
 833
 834     if (cpu->hyperv_synic) {
 835         uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
 836             KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
 837         ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
 838         if (ret < 0) {
 839             error_report("failed to turn on HyperV SynIC in KVM: %s",
 840                          strerror(-ret));
 841             return ret;
 842         }
 843
 844         if (!cpu->hyperv_synic_kvm_only) {
 845             ret = hyperv_x86_synic_add(cpu);
 846             if (ret < 0) {
 847                 error_report("failed to create HyperV SynIC: %s",
 848                              strerror(-ret));
 849                 return ret;
 850             }
 851         }
 852     }
 853
 854     return 0;
 855 }
 856
 857 static Error *invtsc_mig_blocker;
 858 static Error *vmx_mig_blocker;
 859
 860 #define KVM_MAX_CPUID_ENTRIES  100
 861
 862 int kvm_arch_init_vcpu(CPUState *cs)
 863 {
 864     struct {
 865         struct kvm_cpuid2 cpuid;
 866         struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
 867     } QEMU_PACKED cpuid_data;
 868     X86CPU *cpu = X86_CPU(cs);
 869     CPUX86State *env = &cpu->env;
 870     uint32_t limit, i, j, cpuid_i;
 871     uint32_t unused;
 872     struct kvm_cpuid_entry2 *c;
 873     uint32_t signature[3];
 874     uint16_t evmcs_version;
 875     int kvm_base = KVM_CPUID_SIGNATURE;
 876     int r;
 877     Error *local_err = NULL;
 878
 879     memset(&cpuid_data, 0, sizeof(cpuid_data));
 880
 881     cpuid_i = 0;
 882
 883     r = kvm_arch_set_tsc_khz(cs);
 884     if (r < 0) {
 885         goto fail;
 886     }
 887
 888     /* vcpu's TSC frequency is either specified by user, or following
 889      * the value used by KVM if the former is not present. In the
 890      * latter case, we query it from KVM and record in env->tsc_khz,
 891      * so that vcpu's TSC frequency can be migrated later via this field.
 892      */
 893     if (!env->tsc_khz) {
 894         r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
 895             kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
 896             -ENOTSUP;
 897         if (r > 0) {
 898             env->tsc_khz = r;
 899         }
 900     }
 901
 902     /* Paravirtualization CPUIDs */
 903     if (hyperv_enabled(cpu)) {
 904         c = &cpuid_data.entries[cpuid_i++];
 905         c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
 906         if (!cpu->hyperv_vendor_id) {
 907             memcpy(signature, "Microsoft Hv", 12);
 908         } else {
 909             size_t len = strlen(cpu->hyperv_vendor_id);
 910
 911             if (len > 12) {
 912                 error_report("hv-vendor-id truncated to 12 characters");
 913                 len = 12;
 914             }
 915             memset(signature, 0, 12);
 916             memcpy(signature, cpu->hyperv_vendor_id, len);
 917         }
 918         c->eax = cpu->hyperv_evmcs ?
 919             HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
 920         c->ebx = signature[0];
 921         c->ecx = signature[1];
 922         c->edx = signature[2];
 923
 924         c = &cpuid_data.entries[cpuid_i++];
 925         c->function = HV_CPUID_INTERFACE;
 926         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 927         c->eax = signature[0];
 928         c->ebx = 0;
 929         c->ecx = 0;
 930         c->edx = 0;
 931
 932         c = &cpuid_data.entries[cpuid_i++];
 933         c->function = HV_CPUID_VERSION;
 934         c->eax = 0x00001bbc;
 935         c->ebx = 0x00060001;
 936
 937         c = &cpuid_data.entries[cpuid_i++];
 938         c->function = HV_CPUID_FEATURES;
 939         r = hyperv_handle_properties(cs);
 940         if (r) {
 941             return r;
 942         }
 943         c->eax = env->features[FEAT_HYPERV_EAX];
 944         c->ebx = env->features[FEAT_HYPERV_EBX];
 945         c->edx = env->features[FEAT_HYPERV_EDX];
 946
 947         c = &cpuid_data.entries[cpuid_i++];
 948         c->function = HV_CPUID_ENLIGHTMENT_INFO;
 949         if (cpu->hyperv_relaxed_timing) {
 950             c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
 951         }
 952         if (cpu->hyperv_vapic) {
 953             c->eax |= HV_APIC_ACCESS_RECOMMENDED;
 954         }
 955         if (cpu->hyperv_tlbflush) {
 956             if (kvm_check_extension(cs->kvm_state,
 957                                     KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
 958                 fprintf(stderr, "Hyper-V TLB flush support "
 959                         "(requested by 'hv-tlbflush' cpu flag) "
 960                         " is not supported by kernel\n");
 961                 return -ENOSYS;
 962             }
 963             c->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
 964             c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
 965         }
 966         if (cpu->hyperv_ipi) {
 967             if (kvm_check_extension(cs->kvm_state,
 968                                     KVM_CAP_HYPERV_SEND_IPI) <= 0) {
 969                 fprintf(stderr, "Hyper-V IPI send support "
 970                         "(requested by 'hv-ipi' cpu flag) "
 971                         " is not supported by kernel\n");
 972                 return -ENOSYS;
 973             }
 974             c->eax |= HV_CLUSTER_IPI_RECOMMENDED;
 975             c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
 976         }
 977         if (cpu->hyperv_evmcs) {
 978             if (kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
 979                                     (uintptr_t)&evmcs_version)) {
 980                 fprintf(stderr, "Hyper-V Enlightened VMCS "
 981                         "(requested by 'hv-evmcs' cpu flag) "
 982                         "is not supported by kernel\n");
 983                 return -ENOSYS;
 984             }
 985             c->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
 986         }
 987         c->ebx = cpu->hyperv_spinlock_attempts;
 988
 989         c = &cpuid_data.entries[cpuid_i++];
 990         c->function = HV_CPUID_IMPLEMENT_LIMITS;
 991
 992         c->eax = cpu->hv_max_vps;
 993         c->ebx = 0x40;
 994
 995         kvm_base = KVM_CPUID_SIGNATURE_NEXT;
 996         has_msr_hv_hypercall = true;
 997
 998         if (cpu->hyperv_evmcs) {
 999             __u32 function;
1000
1001             /* Create zeroed 0x40000006..0x40000009 leaves */
1002             for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1003                  function < HV_CPUID_NESTED_FEATURES; function++) {
1004                 c = &cpuid_data.entries[cpuid_i++];
1005                 c->function = function;
1006             }
1007
1008             c = &cpuid_data.entries[cpuid_i++];
1009             c->function = HV_CPUID_NESTED_FEATURES;
1010             c->eax = evmcs_version;
1011         }
1012     }
1013
1014     if (cpu->expose_kvm) {
1015         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1016         c = &cpuid_data.entries[cpuid_i++];
1017         c->function = KVM_CPUID_SIGNATURE | kvm_base;
1018         c->eax = KVM_CPUID_FEATURES | kvm_base;
1019         c->ebx = signature[0];
1020         c->ecx = signature[1];
1021         c->edx = signature[2];
1022
1023         c = &cpuid_data.entries[cpuid_i++];
1024         c->function = KVM_CPUID_FEATURES | kvm_base;
1025         c->eax = env->features[FEAT_KVM];
1026         c->edx = env->features[FEAT_KVM_HINTS];
1027     }
1028
1029     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1030
1031     for (i = 0; i <= limit; i++) {
1032         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1033             fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1034             abort();
1035         }
1036         c = &cpuid_data.entries[cpuid_i++];
1037
1038         switch (i) {
1039         case 2: {
1040             /* Keep reading function 2 till all the input is received */
1041             int times;
1042
1043             c->function = i;
1044             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1045                        KVM_CPUID_FLAG_STATE_READ_NEXT;
1046             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1047             times = c->eax & 0xff;
1048
1049             for (j = 1; j < times; ++j) {
1050                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1051                     fprintf(stderr, "cpuid_data is full, no space for "
1052                             "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1053                     abort();
1054                 }
1055                 c = &cpuid_data.entries[cpuid_i++];
1056                 c->function = i;
1057                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1058                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1059             }
1060             break;
1061         }
1062         case 4:
1063         case 0xb:
1064         case 0xd:
1065             for (j = 0; ; j++) {
1066                 if (i == 0xd && j == 64) {
1067                     break;
1068                 }
1069                 c->function = i;
1070                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1071                 c->index = j;
1072                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1073
1074                 if (i == 4 && c->eax == 0) {
1075                     break;
1076                 }
1077                 if (i == 0xb && !(c->ecx & 0xff00)) {
1078                     break;
1079                 }
1080                 if (i == 0xd && c->eax == 0) {
1081                     continue;
1082                 }
1083                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1084                     fprintf(stderr, "cpuid_data is full, no space for "
1085                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1086                     abort();
1087                 }
1088                 c = &cpuid_data.entries[cpuid_i++];
1089             }
1090             break;
1091         case 0x14: {
1092             uint32_t times;
1093
1094             c->function = i;
1095             c->index = 0;
1096             c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1097             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1098             times = c->eax;
1099
1100             for (j = 1; j <= times; ++j) {
1101                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1102                     fprintf(stderr, "cpuid_data is full, no space for "
1103                                 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1104                     abort();
1105                 }
1106                 c = &cpuid_data.entries[cpuid_i++];
1107                 c->function = i;
1108                 c->index = j;
1109                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1110                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1111             }
1112             break;
1113         }
1114         default:
1115             c->function = i;
1116             c->flags = 0;
1117             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1118             break;
1119         }
1120     }
1121
1122     if (limit >= 0x0a) {
1123         uint32_t eax, edx;
1124
1125         cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1126
1127         has_architectural_pmu_version = eax & 0xff;
1128         if (has_architectural_pmu_version > 0) {
1129             num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1130
1131             /* Shouldn't be more than 32, since that's the number of bits
1132              * available in EBX to tell us _which_ counters are available.
1133              * Play it safe.
1134              */
1135             if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1136                 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1137             }
1138
1139             if (has_architectural_pmu_version > 1) {
1140                 num_architectural_pmu_fixed_counters = edx & 0x1f;
1141
1142                 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1143                     num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1144                 }
1145             }
1146         }
1147     }
1148
1149     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1150
1151     for (i = 0x80000000; i <= limit; i++) {
1152         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1153             fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1154             abort();
1155         }
1156         c = &cpuid_data.entries[cpuid_i++];
1157
1158         switch (i) {
1159         case 0x8000001d:
1160             /* Query for all AMD cache information leaves */
1161             for (j = 0; ; j++) {
1162                 c->function = i;
1163                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1164                 c->index = j;
1165                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1166
1167                 if (c->eax == 0) {
1168                     break;
1169                 }
1170                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1171                     fprintf(stderr, "cpuid_data is full, no space for "
1172                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1173                     abort();
1174                 }
1175                 c = &cpuid_data.entries[cpuid_i++];
1176             }
1177             break;
1178         default:
1179             c->function = i;
1180             c->flags = 0;
1181             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1182             break;
1183         }
1184     }
1185
1186     /* Call Centaur's CPUID instructions they are supported. */
1187     if (env->cpuid_xlevel2 > 0) {
1188         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1189
1190         for (i = 0xC0000000; i <= limit; i++) {
1191             if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1192                 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1193                 abort();
1194             }
1195             c = &cpuid_data.entries[cpuid_i++];
1196
1197             c->function = i;
1198             c->flags = 0;
1199             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1200         }
1201     }
1202
1203     cpuid_data.cpuid.nent = cpuid_i;
1204
1205     if (((env->cpuid_version >> 8)&0xF) >= 6
1206         && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1207            (CPUID_MCE | CPUID_MCA)
1208         && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1209         uint64_t mcg_cap, unsupported_caps;
1210         int banks;
1211         int ret;
1212
1213         ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1214         if (ret < 0) {
1215             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1216             return ret;
1217         }
1218
1219         if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1220             error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1221                          (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1222             return -ENOTSUP;
1223         }
1224
1225         unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1226         if (unsupported_caps) {
1227             if (unsupported_caps & MCG_LMCE_P) {
1228                 error_report("kvm: LMCE not supported");
1229                 return -ENOTSUP;
1230             }
1231             warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1232                         unsupported_caps);
1233         }
1234
1235         env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1236         ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1237         if (ret < 0) {
1238             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1239             return ret;
1240         }
1241     }
1242
1243     qemu_add_vm_change_state_handler(cpu_update_state, env);
1244
1245     c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1246     if (c) {
1247         has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1248                                   !!(c->ecx & CPUID_EXT_SMX);
1249     }
1250
1251     if ((env->features[FEAT_1_ECX] & CPUID_EXT_VMX) && !vmx_mig_blocker) {
1252         error_setg(&vmx_mig_blocker,
1253                    "Nested VMX virtualization does not support live migration yet");
1254         r = migrate_add_blocker(vmx_mig_blocker, &local_err);
1255         if (local_err) {
1256             error_report_err(local_err);
1257             error_free(vmx_mig_blocker);
1258             return r;
1259         }
1260     }
1261
1262     if (env->mcg_cap & MCG_LMCE_P) {
1263         has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1264     }
1265
1266     if (!env->user_tsc_khz) {
1267         if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1268             invtsc_mig_blocker == NULL) {
1269             error_setg(&invtsc_mig_blocker,
1270                        "State blocked by non-migratable CPU device"
1271                        " (invtsc flag)");
1272             r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1273             if (local_err) {
1274                 error_report_err(local_err);
1275                 error_free(invtsc_mig_blocker);
1276                 return r;
1277             }
1278         }
1279     }
1280
1281     if (cpu->vmware_cpuid_freq
1282         /* Guests depend on 0x40000000 to detect this feature, so only expose
1283          * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1284         && cpu->expose_kvm
1285         && kvm_base == KVM_CPUID_SIGNATURE
1286         /* TSC clock must be stable and known for this feature. */
1287         && tsc_is_stable_and_known(env)) {
1288
1289         c = &cpuid_data.entries[cpuid_i++];
1290         c->function = KVM_CPUID_SIGNATURE | 0x10;
1291         c->eax = env->tsc_khz;
1292         /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1293          * APIC_BUS_CYCLE_NS */
1294         c->ebx = 1000000;
1295         c->ecx = c->edx = 0;
1296
1297         c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1298         c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1299     }
1300
1301     cpuid_data.cpuid.nent = cpuid_i;
1302
1303     cpuid_data.cpuid.padding = 0;
1304     r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1305     if (r) {
1306         goto fail;
1307     }
1308
1309     if (has_xsave) {
1310         env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1311     }
1312     cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1313
1314     if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1315         has_msr_tsc_aux = false;
1316     }
1317
1318     r = hyperv_init_vcpu(cpu);
1319     if (r) {
1320         goto fail;
1321     }
1322
1323     return 0;
1324
1325  fail:
1326     migrate_del_blocker(invtsc_mig_blocker);
1327     return r;
1328 }
1329
1330 void kvm_arch_reset_vcpu(X86CPU *cpu)
1331 {
1332     CPUX86State *env = &cpu->env;
1333
1334     env->xcr0 = 1;
1335     if (kvm_irqchip_in_kernel()) {
1336         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1337                                           KVM_MP_STATE_UNINITIALIZED;
1338     } else {
1339         env->mp_state = KVM_MP_STATE_RUNNABLE;
1340     }
1341
1342     if (cpu->hyperv_synic) {
1343         int i;
1344         for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1345             env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1346         }
1347
1348         hyperv_x86_synic_reset(cpu);
1349     }
1350 }
1351
1352 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1353 {
1354     CPUX86State *env = &cpu->env;
1355
1356     /* APs get directly into wait-for-SIPI state.  */
1357     if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1358         env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1359     }
1360 }
1361
1362 static int kvm_get_supported_feature_msrs(KVMState *s)
1363 {
1364     int ret = 0;
1365
1366     if (kvm_feature_msrs != NULL) {
1367         return 0;
1368     }
1369
1370     if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1371         return 0;
1372     }
1373
1374     struct kvm_msr_list msr_list;
1375
1376     msr_list.nmsrs = 0;
1377     ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1378     if (ret < 0 && ret != -E2BIG) {
1379         error_report("Fetch KVM feature MSR list failed: %s",
1380             strerror(-ret));
1381         return ret;
1382     }
1383
1384     assert(msr_list.nmsrs > 0);
1385     kvm_feature_msrs = (struct kvm_msr_list *) \
1386         g_malloc0(sizeof(msr_list) +
1387                  msr_list.nmsrs * sizeof(msr_list.indices[0]));
1388
1389     kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1390     ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1391
1392     if (ret < 0) {
1393         error_report("Fetch KVM feature MSR list failed: %s",
1394             strerror(-ret));
1395         g_free(kvm_feature_msrs);
1396         kvm_feature_msrs = NULL;
1397         return ret;
1398     }
1399
1400     return 0;
1401 }
1402
1403 static int kvm_get_supported_msrs(KVMState *s)
1404 {
1405     static int kvm_supported_msrs;
1406     int ret = 0;
1407
1408     /* first time */
1409     if (kvm_supported_msrs == 0) {
1410         struct kvm_msr_list msr_list, *kvm_msr_list;
1411
1412         kvm_supported_msrs = -1;
1413
1414         /* Obtain MSR list from KVM.  These are the MSRs that we must
1415          * save/restore */
1416         msr_list.nmsrs = 0;
1417         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1418         if (ret < 0 && ret != -E2BIG) {
1419             return ret;
1420         }
1421         /* Old kernel modules had a bug and could write beyond the provided
1422            memory. Allocate at least a safe amount of 1K. */
1423         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1424                                               msr_list.nmsrs *
1425                                               sizeof(msr_list.indices[0])));
1426
1427         kvm_msr_list->nmsrs = msr_list.nmsrs;
1428         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1429         if (ret >= 0) {
1430             int i;
1431
1432             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1433                 switch (kvm_msr_list->indices[i]) {
1434                 case MSR_STAR:
1435                     has_msr_star = true;
1436                     break;
1437                 case MSR_VM_HSAVE_PA:
1438                     has_msr_hsave_pa = true;
1439                     break;
1440                 case MSR_TSC_AUX:
1441                     has_msr_tsc_aux = true;
1442                     break;
1443                 case MSR_TSC_ADJUST:
1444                     has_msr_tsc_adjust = true;
1445                     break;
1446                 case MSR_IA32_TSCDEADLINE:
1447                     has_msr_tsc_deadline = true;
1448                     break;
1449                 case MSR_IA32_SMBASE:
1450                     has_msr_smbase = true;
1451                     break;
1452                 case MSR_SMI_COUNT:
1453                     has_msr_smi_count = true;
1454                     break;
1455                 case MSR_IA32_MISC_ENABLE:
1456                     has_msr_misc_enable = true;
1457                     break;
1458                 case MSR_IA32_BNDCFGS:
1459                     has_msr_bndcfgs = true;
1460                     break;
1461                 case MSR_IA32_XSS:
1462                     has_msr_xss = true;
1463                     break;
1464                 case HV_X64_MSR_CRASH_CTL:
1465                     has_msr_hv_crash = true;
1466                     break;
1467                 case HV_X64_MSR_RESET:
1468                     has_msr_hv_reset = true;
1469                     break;
1470                 case HV_X64_MSR_VP_INDEX:
1471                     has_msr_hv_vpindex = true;
1472                     break;
1473                 case HV_X64_MSR_VP_RUNTIME:
1474                     has_msr_hv_runtime = true;
1475                     break;
1476                 case HV_X64_MSR_SCONTROL:
1477                     has_msr_hv_synic = true;
1478                     break;
1479                 case HV_X64_MSR_STIMER0_CONFIG:
1480                     has_msr_hv_stimer = true;
1481                     break;
1482                 case HV_X64_MSR_TSC_FREQUENCY:
1483                     has_msr_hv_frequencies = true;
1484                     break;
1485                 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1486                     has_msr_hv_reenlightenment = true;
1487                     break;
1488                 case MSR_IA32_SPEC_CTRL:
1489                     has_msr_spec_ctrl = true;
1490                     break;
1491                 case MSR_VIRT_SSBD:
1492                     has_msr_virt_ssbd = true;
1493                     break;
1494                 case MSR_IA32_ARCH_CAPABILITIES:
1495                     has_msr_arch_capabs = true;
1496                     break;
1497                 }
1498             }
1499         }
1500
1501         g_free(kvm_msr_list);
1502     }
1503
1504     return ret;
1505 }
1506
1507 static Notifier smram_machine_done;
1508 static KVMMemoryListener smram_listener;
1509 static AddressSpace smram_address_space;
1510 static MemoryRegion smram_as_root;
1511 static MemoryRegion smram_as_mem;
1512
1513 static void register_smram_listener(Notifier *n, void *unused)
1514 {
1515     MemoryRegion *smram =
1516         (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1517
1518     /* Outer container... */
1519     memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1520     memory_region_set_enabled(&smram_as_root, true);
1521
1522     /* ... with two regions inside: normal system memory with low
1523      * priority, and...
1524      */
1525     memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1526                              get_system_memory(), 0, ~0ull);
1527     memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1528     memory_region_set_enabled(&smram_as_mem, true);
1529
1530     if (smram) {
1531         /* ... SMRAM with higher priority */
1532         memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1533         memory_region_set_enabled(smram, true);
1534     }
1535
1536     address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1537     kvm_memory_listener_register(kvm_state, &smram_listener,
1538                                  &smram_address_space, 1);
1539 }
1540
1541 int kvm_arch_init(MachineState *ms, KVMState *s)
1542 {
1543     uint64_t identity_base = 0xfffbc000;
1544     uint64_t shadow_mem;
1545     int ret;
1546     struct utsname utsname;
1547
1548     has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1549     has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1550     has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1551
1552     hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1553
1554     ret = kvm_get_supported_msrs(s);
1555     if (ret < 0) {
1556         return ret;
1557     }
1558
1559     kvm_get_supported_feature_msrs(s);
1560
1561     uname(&utsname);
1562     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1563
1564     /*
1565      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1566      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
1567      * Since these must be part of guest physical memory, we need to allocate
1568      * them, both by setting their start addresses in the kernel and by
1569      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1570      *
1571      * Older KVM versions may not support setting the identity map base. In
1572      * that case we need to stick with the default, i.e. a 256K maximum BIOS
1573      * size.
1574      */
1575     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1576         /* Allows up to 16M BIOSes. */
1577         identity_base = 0xfeffc000;
1578
1579         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1580         if (ret < 0) {
1581             return ret;
1582         }
1583     }
1584
1585     /* Set TSS base one page after EPT identity map. */
1586     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1587     if (ret < 0) {
1588         return ret;
1589     }
1590
1591     /* Tell fw_cfg to notify the BIOS to reserve the range. */
1592     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1593     if (ret < 0) {
1594         fprintf(stderr, "e820_add_entry() table is full\n");
1595         return ret;
1596     }
1597     qemu_register_reset(kvm_unpoison_all, NULL);
1598
1599     shadow_mem = machine_kvm_shadow_mem(ms);
1600     if (shadow_mem != -1) {
1601         shadow_mem /= 4096;
1602         ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1603         if (ret < 0) {
1604             return ret;
1605         }
1606     }
1607
1608     if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1609         object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1610         pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1611         smram_machine_done.notify = register_smram_listener;
1612         qemu_add_machine_init_done_notifier(&smram_machine_done);
1613     }
1614
1615     if (enable_cpu_pm) {
1616         int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1617         int ret;
1618
1619 /* Work around for kernel header with a typo. TODO: fix header and drop. */
1620 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1621 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1622 #endif
1623         if (disable_exits) {
1624             disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1625                               KVM_X86_DISABLE_EXITS_HLT |
1626                               KVM_X86_DISABLE_EXITS_PAUSE);
1627         }
1628
1629         ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1630                                 disable_exits);
1631         if (ret < 0) {
1632             error_report("kvm: guest stopping CPU not supported: %s",
1633                          strerror(-ret));
1634         }
1635     }
1636
1637     return 0;
1638 }
1639
1640 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1641 {
1642     lhs->selector = rhs->selector;
1643     lhs->base = rhs->base;
1644     lhs->limit = rhs->limit;
1645     lhs->type = 3;
1646     lhs->present = 1;
1647     lhs->dpl = 3;
1648     lhs->db = 0;
1649     lhs->s = 1;
1650     lhs->l = 0;
1651     lhs->g = 0;
1652     lhs->avl = 0;
1653     lhs->unusable = 0;
1654 }
1655
1656 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1657 {
1658     unsigned flags = rhs->flags;
1659     lhs->selector = rhs->selector;
1660     lhs->base = rhs->base;
1661     lhs->limit = rhs->limit;
1662     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1663     lhs->present = (flags & DESC_P_MASK) != 0;
1664     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1665     lhs->db = (flags >> DESC_B_SHIFT) & 1;
1666     lhs->s = (flags & DESC_S_MASK) != 0;
1667     lhs->l = (flags >> DESC_L_SHIFT) & 1;
1668     lhs->g = (flags & DESC_G_MASK) != 0;
1669     lhs->avl = (flags & DESC_AVL_MASK) != 0;
1670     lhs->unusable = !lhs->present;
1671     lhs->padding = 0;
1672 }
1673
1674 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1675 {
1676     lhs->selector = rhs->selector;
1677     lhs->base = rhs->base;
1678     lhs->limit = rhs->limit;
1679     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1680                  ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1681                  (rhs->dpl << DESC_DPL_SHIFT) |
1682                  (rhs->db << DESC_B_SHIFT) |
1683                  (rhs->s * DESC_S_MASK) |
1684                  (rhs->l << DESC_L_SHIFT) |
1685                  (rhs->g * DESC_G_MASK) |
1686                  (rhs->avl * DESC_AVL_MASK);
1687 }
1688
1689 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1690 {
1691     if (set) {
1692         *kvm_reg = *qemu_reg;
1693     } else {
1694         *qemu_reg = *kvm_reg;
1695     }
1696 }
1697
1698 static int kvm_getput_regs(X86CPU *cpu, int set)
1699 {
1700     CPUX86State *env = &cpu->env;
1701     struct kvm_regs regs;
1702     int ret = 0;
1703
1704     if (!set) {
1705         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1706         if (ret < 0) {
1707             return ret;
1708         }
1709     }
1710
1711     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1712     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1713     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1714     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1715     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1716     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1717     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1718     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1719 #ifdef TARGET_X86_64
1720     kvm_getput_reg(&regs.r8, &env->regs[8], set);
1721     kvm_getput_reg(&regs.r9, &env->regs[9], set);
1722     kvm_getput_reg(&regs.r10, &env->regs[10], set);
1723     kvm_getput_reg(&regs.r11, &env->regs[11], set);
1724     kvm_getput_reg(&regs.r12, &env->regs[12], set);
1725     kvm_getput_reg(&regs.r13, &env->regs[13], set);
1726     kvm_getput_reg(&regs.r14, &env->regs[14], set);
1727     kvm_getput_reg(&regs.r15, &env->regs[15], set);
1728 #endif
1729
1730     kvm_getput_reg(&regs.rflags, &env->eflags, set);
1731     kvm_getput_reg(&regs.rip, &env->eip, set);
1732
1733     if (set) {
1734         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1735     }
1736
1737     return ret;
1738 }
1739
1740 static int kvm_put_fpu(X86CPU *cpu)
1741 {
1742     CPUX86State *env = &cpu->env;
1743     struct kvm_fpu fpu;
1744     int i;
1745
1746     memset(&fpu, 0, sizeof fpu);
1747     fpu.fsw = env->fpus & ~(7 << 11);
1748     fpu.fsw |= (env->fpstt & 7) << 11;
1749     fpu.fcw = env->fpuc;
1750     fpu.last_opcode = env->fpop;
1751     fpu.last_ip = env->fpip;
1752     fpu.last_dp = env->fpdp;
1753     for (i = 0; i < 8; ++i) {
1754         fpu.ftwx |= (!env->fptags[i]) << i;
1755     }
1756     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1757     for (i = 0; i < CPU_NB_REGS; i++) {
1758         stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1759         stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1760     }
1761     fpu.mxcsr = env->mxcsr;
1762
1763     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1764 }
1765
1766 #define XSAVE_FCW_FSW     0
1767 #define XSAVE_FTW_FOP     1
1768 #define XSAVE_CWD_RIP     2
1769 #define XSAVE_CWD_RDP     4
1770 #define XSAVE_MXCSR       6
1771 #define XSAVE_ST_SPACE    8
1772 #define XSAVE_XMM_SPACE   40
1773 #define XSAVE_XSTATE_BV   128
1774 #define XSAVE_YMMH_SPACE  144
1775 #define XSAVE_BNDREGS     240
1776 #define XSAVE_BNDCSR      256
1777 #define XSAVE_OPMASK      272
1778 #define XSAVE_ZMM_Hi256   288
1779 #define XSAVE_Hi16_ZMM    416
1780 #define XSAVE_PKRU        672
1781
1782 #define XSAVE_BYTE_OFFSET(word_offset) \
1783     ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
1784
1785 #define ASSERT_OFFSET(word_offset, field) \
1786     QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1787                       offsetof(X86XSaveArea, field))
1788
1789 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1790 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1791 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1792 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1793 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1794 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1795 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1796 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1797 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1798 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1799 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1800 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1801 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1802 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1803 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1804
1805 static int kvm_put_xsave(X86CPU *cpu)
1806 {
1807     CPUX86State *env = &cpu->env;
1808     X86XSaveArea *xsave = env->xsave_buf;
1809
1810     if (!has_xsave) {
1811         return kvm_put_fpu(cpu);
1812     }
1813     x86_cpu_xsave_all_areas(cpu, xsave);
1814
1815     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1816 }
1817
1818 static int kvm_put_xcrs(X86CPU *cpu)
1819 {
1820     CPUX86State *env = &cpu->env;
1821     struct kvm_xcrs xcrs = {};
1822
1823     if (!has_xcrs) {
1824         return 0;
1825     }
1826
1827     xcrs.nr_xcrs = 1;
1828     xcrs.flags = 0;
1829     xcrs.xcrs[0].xcr = 0;
1830     xcrs.xcrs[0].value = env->xcr0;
1831     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1832 }
1833
1834 static int kvm_put_sregs(X86CPU *cpu)
1835 {
1836     CPUX86State *env = &cpu->env;
1837     struct kvm_sregs sregs;
1838
1839     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1840     if (env->interrupt_injected >= 0) {
1841         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1842                 (uint64_t)1 << (env->interrupt_injected % 64);
1843     }
1844
1845     if ((env->eflags & VM_MASK)) {
1846         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1847         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1848         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1849         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1850         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1851         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1852     } else {
1853         set_seg(&sregs.cs, &env->segs[R_CS]);
1854         set_seg(&sregs.ds, &env->segs[R_DS]);
1855         set_seg(&sregs.es, &env->segs[R_ES]);
1856         set_seg(&sregs.fs, &env->segs[R_FS]);
1857         set_seg(&sregs.gs, &env->segs[R_GS]);
1858         set_seg(&sregs.ss, &env->segs[R_SS]);
1859     }
1860
1861     set_seg(&sregs.tr, &env->tr);
1862     set_seg(&sregs.ldt, &env->ldt);
1863
1864     sregs.idt.limit = env->idt.limit;
1865     sregs.idt.base = env->idt.base;
1866     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1867     sregs.gdt.limit = env->gdt.limit;
1868     sregs.gdt.base = env->gdt.base;
1869     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1870
1871     sregs.cr0 = env->cr[0];
1872     sregs.cr2 = env->cr[2];
1873     sregs.cr3 = env->cr[3];
1874     sregs.cr4 = env->cr[4];
1875
1876     sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1877     sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1878
1879     sregs.efer = env->efer;
1880
1881     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1882 }
1883
1884 static void kvm_msr_buf_reset(X86CPU *cpu)
1885 {
1886     memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1887 }
1888
1889 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1890 {
1891     struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1892     void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1893     struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1894
1895     assert((void *)(entry + 1) <= limit);
1896
1897     entry->index = index;
1898     entry->reserved = 0;
1899     entry->data = value;
1900     msrs->nmsrs++;
1901 }
1902
1903 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1904 {
1905     kvm_msr_buf_reset(cpu);
1906     kvm_msr_entry_add(cpu, index, value);
1907
1908     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1909 }
1910
1911 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1912 {
1913     int ret;
1914
1915     ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1916     assert(ret == 1);
1917 }
1918
1919 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1920 {
1921     CPUX86State *env = &cpu->env;
1922     int ret;
1923
1924     if (!has_msr_tsc_deadline) {
1925         return 0;
1926     }
1927
1928     ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1929     if (ret < 0) {
1930         return ret;
1931     }
1932
1933     assert(ret == 1);
1934     return 0;
1935 }
1936
1937 /*
1938  * Provide a separate write service for the feature control MSR in order to
1939  * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1940  * before writing any other state because forcibly leaving nested mode
1941  * invalidates the VCPU state.
1942  */
1943 static int kvm_put_msr_feature_control(X86CPU *cpu)
1944 {
1945     int ret;
1946
1947     if (!has_msr_feature_control) {
1948         return 0;
1949     }
1950
1951     ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1952                           cpu->env.msr_ia32_feature_control);
1953     if (ret < 0) {
1954         return ret;
1955     }
1956
1957     assert(ret == 1);
1958     return 0;
1959 }
1960
1961 static int kvm_put_msrs(X86CPU *cpu, int level)
1962 {
1963     CPUX86State *env = &cpu->env;
1964     int i;
1965     int ret;
1966
1967     kvm_msr_buf_reset(cpu);
1968
1969     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1970     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1971     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1972     kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1973     if (has_msr_star) {
1974         kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1975     }
1976     if (has_msr_hsave_pa) {
1977         kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1978     }
1979     if (has_msr_tsc_aux) {
1980         kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1981     }
1982     if (has_msr_tsc_adjust) {
1983         kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1984     }
1985     if (has_msr_misc_enable) {
1986         kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1987                           env->msr_ia32_misc_enable);
1988     }
1989     if (has_msr_smbase) {
1990         kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1991     }
1992     if (has_msr_smi_count) {
1993         kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1994     }
1995     if (has_msr_bndcfgs) {
1996         kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1997     }
1998     if (has_msr_xss) {
1999         kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
2000     }
2001     if (has_msr_spec_ctrl) {
2002         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2003     }
2004     if (has_msr_virt_ssbd) {
2005         kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2006     }
2007
2008 #ifdef TARGET_X86_64
2009     if (lm_capable_kernel) {
2010         kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2011         kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2012         kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2013         kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
2014     }
2015 #endif
2016
2017     /* If host supports feature MSR, write down. */
2018     if (has_msr_arch_capabs) {
2019         kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2020                           env->features[FEAT_ARCH_CAPABILITIES]);
2021     }
2022
2023     /*
2024      * The following MSRs have side effects on the guest or are too heavy
2025      * for normal writeback. Limit them to reset or full state updates.
2026      */
2027     if (level >= KVM_PUT_RESET_STATE) {
2028         kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2029         kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2030         kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
2031         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2032             kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
2033         }
2034         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2035             kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2036         }
2037         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2038             kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2039         }
2040         if (has_architectural_pmu_version > 0) {
2041             if (has_architectural_pmu_version > 1) {
2042                 /* Stop the counter.  */
2043                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2044                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2045             }
2046
2047             /* Set the counter values.  */
2048             for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2049                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2050                                   env->msr_fixed_counters[i]);
2051             }
2052             for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2053                 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2054                                   env->msr_gp_counters[i]);
2055                 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2056                                   env->msr_gp_evtsel[i]);
2057             }
2058             if (has_architectural_pmu_version > 1) {
2059                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2060                                   env->msr_global_status);
2061                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2062                                   env->msr_global_ovf_ctrl);
2063
2064                 /* Now start the PMU.  */
2065                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2066                                   env->msr_fixed_ctr_ctrl);
2067                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2068                                   env->msr_global_ctrl);
2069             }
2070         }
2071         /*
2072          * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2073          * only sync them to KVM on the first cpu
2074          */
2075         if (current_cpu == first_cpu) {
2076             if (has_msr_hv_hypercall) {
2077                 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2078                                   env->msr_hv_guest_os_id);
2079                 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2080                                   env->msr_hv_hypercall);
2081             }
2082             if (cpu->hyperv_time) {
2083                 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2084                                   env->msr_hv_tsc);
2085             }
2086             if (cpu->hyperv_reenlightenment) {
2087                 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2088                                   env->msr_hv_reenlightenment_control);
2089                 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2090                                   env->msr_hv_tsc_emulation_control);
2091                 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2092                                   env->msr_hv_tsc_emulation_status);
2093             }
2094         }
2095         if (cpu->hyperv_vapic) {
2096             kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2097                               env->msr_hv_vapic);
2098         }
2099         if (has_msr_hv_crash) {
2100             int j;
2101
2102             for (j = 0; j < HV_CRASH_PARAMS; j++)
2103                 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2104                                   env->msr_hv_crash_params[j]);
2105
2106             kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2107         }
2108         if (has_msr_hv_runtime) {
2109             kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2110         }
2111         if (cpu->hyperv_vpindex && hv_vpindex_settable) {
2112             kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2113                               hyperv_vp_index(CPU(cpu)));
2114         }
2115         if (cpu->hyperv_synic) {
2116             int j;
2117
2118             kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2119
2120             kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2121                               env->msr_hv_synic_control);
2122             kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
2123                               env->msr_hv_synic_evt_page);
2124             kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
2125                               env->msr_hv_synic_msg_page);
2126
2127             for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
2128                 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
2129                                   env->msr_hv_synic_sint[j]);
2130             }
2131         }
2132         if (has_msr_hv_stimer) {
2133             int j;
2134
2135             for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
2136                 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
2137                                 env->msr_hv_stimer_config[j]);
2138             }
2139
2140             for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2141                 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2142                                 env->msr_hv_stimer_count[j]);
2143             }
2144         }
2145         if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2146             uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2147
2148             kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2149             kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2150             kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2151             kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2152             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2153             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2154             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2155             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2156             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2157             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2158             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2159             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2160             for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2161                 /* The CPU GPs if we write to a bit above the physical limit of
2162                  * the host CPU (and KVM emulates that)
2163                  */
2164                 uint64_t mask = env->mtrr_var[i].mask;
2165                 mask &= phys_mask;
2166
2167                 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2168                                   env->mtrr_var[i].base);
2169                 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2170             }
2171         }
2172         if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2173             int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2174                                                     0x14, 1, R_EAX) & 0x7;
2175
2176             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2177                             env->msr_rtit_ctrl);
2178             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2179                             env->msr_rtit_status);
2180             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2181                             env->msr_rtit_output_base);
2182             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2183                             env->msr_rtit_output_mask);
2184             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2185                             env->msr_rtit_cr3_match);
2186             for (i = 0; i < addr_num; i++) {
2187                 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2188                             env->msr_rtit_addrs[i]);
2189             }
2190         }
2191
2192         /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2193          *       kvm_put_msr_feature_control. */
2194     }
2195     if (env->mcg_cap) {
2196         int i;
2197
2198         kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2199         kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2200         if (has_msr_mcg_ext_ctl) {
2201             kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2202         }
2203         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2204             kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2205         }
2206     }
2207
2208     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2209     if (ret < 0) {
2210         return ret;
2211     }
2212
2213     if (ret < cpu->kvm_msr_buf->nmsrs) {
2214         struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2215         error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2216                      (uint32_t)e->index, (uint64_t)e->data);
2217     }
2218
2219     assert(ret == cpu->kvm_msr_buf->nmsrs);
2220     return 0;
2221 }
2222
2223
2224 static int kvm_get_fpu(X86CPU *cpu)
2225 {
2226     CPUX86State *env = &cpu->env;
2227     struct kvm_fpu fpu;
2228     int i, ret;
2229
2230     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
2231     if (ret < 0) {
2232         return ret;
2233     }
2234
2235     env->fpstt = (fpu.fsw >> 11) & 7;
2236     env->fpus = fpu.fsw;
2237     env->fpuc = fpu.fcw;
2238     env->fpop = fpu.last_opcode;
2239     env->fpip = fpu.last_ip;
2240     env->fpdp = fpu.last_dp;
2241     for (i = 0; i < 8; ++i) {
2242         env->fptags[i] = !((fpu.ftwx >> i) & 1);
2243     }
2244     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
2245     for (i = 0; i < CPU_NB_REGS; i++) {
2246         env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2247         env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
2248     }
2249     env->mxcsr = fpu.mxcsr;
2250
2251     return 0;
2252 }
2253
2254 static int kvm_get_xsave(X86CPU *cpu)
2255 {
2256     CPUX86State *env = &cpu->env;
2257     X86XSaveArea *xsave = env->xsave_buf;
2258     int ret;
2259
2260     if (!has_xsave) {
2261         return kvm_get_fpu(cpu);
2262     }
2263
2264     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
2265     if (ret < 0) {
2266         return ret;
2267     }
2268     x86_cpu_xrstor_all_areas(cpu, xsave);
2269
2270     return 0;
2271 }
2272
2273 static int kvm_get_xcrs(X86CPU *cpu)
2274 {
2275     CPUX86State *env = &cpu->env;
2276     int i, ret;
2277     struct kvm_xcrs xcrs;
2278
2279     if (!has_xcrs) {
2280         return 0;
2281     }
2282
2283     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
2284     if (ret < 0) {
2285         return ret;
2286     }
2287
2288     for (i = 0; i < xcrs.nr_xcrs; i++) {
2289         /* Only support xcr0 now */
2290         if (xcrs.xcrs[i].xcr == 0) {
2291             env->xcr0 = xcrs.xcrs[i].value;
2292             break;
2293         }
2294     }
2295     return 0;
2296 }
2297
2298 static int kvm_get_sregs(X86CPU *cpu)
2299 {
2300     CPUX86State *env = &cpu->env;
2301     struct kvm_sregs sregs;
2302     int bit, i, ret;
2303
2304     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
2305     if (ret < 0) {
2306         return ret;
2307     }
2308
2309     /* There can only be one pending IRQ set in the bitmap at a time, so try
2310        to find it and save its number instead (-1 for none). */
2311     env->interrupt_injected = -1;
2312     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2313         if (sregs.interrupt_bitmap[i]) {
2314             bit = ctz64(sregs.interrupt_bitmap[i]);
2315             env->interrupt_injected = i * 64 + bit;
2316             break;
2317         }
2318     }
2319
2320     get_seg(&env->segs[R_CS], &sregs.cs);
2321     get_seg(&env->segs[R_DS], &sregs.ds);
2322     get_seg(&env->segs[R_ES], &sregs.es);
2323     get_seg(&env->segs[R_FS], &sregs.fs);
2324     get_seg(&env->segs[R_GS], &sregs.gs);
2325     get_seg(&env->segs[R_SS], &sregs.ss);
2326
2327     get_seg(&env->tr, &sregs.tr);
2328     get_seg(&env->ldt, &sregs.ldt);
2329
2330     env->idt.limit = sregs.idt.limit;
2331     env->idt.base = sregs.idt.base;
2332     env->gdt.limit = sregs.gdt.limit;
2333     env->gdt.base = sregs.gdt.base;
2334
2335     env->cr[0] = sregs.cr0;
2336     env->cr[2] = sregs.cr2;
2337     env->cr[3] = sregs.cr3;
2338     env->cr[4] = sregs.cr4;
2339
2340     env->efer = sregs.efer;
2341
2342     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2343     x86_update_hflags(env);
2344
2345     return 0;
2346 }
2347
2348 static int kvm_get_msrs(X86CPU *cpu)
2349 {
2350     CPUX86State *env = &cpu->env;
2351     struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2352     int ret, i;
2353     uint64_t mtrr_top_bits;
2354
2355     kvm_msr_buf_reset(cpu);
2356
2357     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2358     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2359     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2360     kvm_msr_entry_add(cpu, MSR_PAT, 0);
2361     if (has_msr_star) {
2362         kvm_msr_entry_add(cpu, MSR_STAR, 0);
2363     }
2364     if (has_msr_hsave_pa) {
2365         kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2366     }
2367     if (has_msr_tsc_aux) {
2368         kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2369     }
2370     if (has_msr_tsc_adjust) {
2371         kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2372     }
2373     if (has_msr_tsc_deadline) {
2374         kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2375     }
2376     if (has_msr_misc_enable) {
2377         kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2378     }
2379     if (has_msr_smbase) {
2380         kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2381     }
2382     if (has_msr_smi_count) {
2383         kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2384     }
2385     if (has_msr_feature_control) {
2386         kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2387     }
2388     if (has_msr_bndcfgs) {
2389         kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2390     }
2391     if (has_msr_xss) {
2392         kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2393     }
2394     if (has_msr_spec_ctrl) {
2395         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2396     }
2397     if (has_msr_virt_ssbd) {
2398         kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2399     }
2400     if (!env->tsc_valid) {
2401         kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2402         env->tsc_valid = !runstate_is_running();
2403     }
2404
2405 #ifdef TARGET_X86_64
2406     if (lm_capable_kernel) {
2407         kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2408         kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2409         kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2410         kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2411     }
2412 #endif
2413     kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2414     kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2415     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2416         kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2417     }
2418     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2419         kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2420     }
2421     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2422         kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2423     }
2424     if (has_architectural_pmu_version > 0) {
2425         if (has_architectural_pmu_version > 1) {
2426             kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2427             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2428             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2429             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2430         }
2431         for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2432             kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2433         }
2434         for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2435             kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2436             kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2437         }
2438     }
2439
2440     if (env->mcg_cap) {
2441         kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2442         kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2443         if (has_msr_mcg_ext_ctl) {
2444             kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2445         }
2446         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2447             kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2448         }
2449     }
2450
2451     if (has_msr_hv_hypercall) {
2452         kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2453         kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2454     }
2455     if (cpu->hyperv_vapic) {
2456         kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2457     }
2458     if (cpu->hyperv_time) {
2459         kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2460     }
2461     if (cpu->hyperv_reenlightenment) {
2462         kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2463         kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2464         kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2465     }
2466     if (has_msr_hv_crash) {
2467         int j;
2468
2469         for (j = 0; j < HV_CRASH_PARAMS; j++) {
2470             kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2471         }
2472     }
2473     if (has_msr_hv_runtime) {
2474         kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2475     }
2476     if (cpu->hyperv_synic) {
2477         uint32_t msr;
2478
2479         kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2480         kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2481         kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2482         for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2483             kvm_msr_entry_add(cpu, msr, 0);
2484         }
2485     }
2486     if (has_msr_hv_stimer) {
2487         uint32_t msr;
2488
2489         for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2490              msr++) {
2491             kvm_msr_entry_add(cpu, msr, 0);
2492         }
2493     }
2494     if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2495         kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2496         kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2497         kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2498         kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2499         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2500         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2501         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2502         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2503         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2504         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2505         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2506         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2507         for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2508             kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2509             kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2510         }
2511     }
2512
2513     if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2514         int addr_num =
2515             kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2516
2517         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2518         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2519         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2520         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2521         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2522         for (i = 0; i < addr_num; i++) {
2523             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2524         }
2525     }
2526
2527     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2528     if (ret < 0) {
2529         return ret;
2530     }
2531
2532     if (ret < cpu->kvm_msr_buf->nmsrs) {
2533         struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2534         error_report("error: failed to get MSR 0x%" PRIx32,
2535                      (uint32_t)e->index);
2536     }
2537
2538     assert(ret == cpu->kvm_msr_buf->nmsrs);
2539     /*
2540      * MTRR masks: Each mask consists of 5 parts
2541      * a  10..0: must be zero
2542      * b  11   : valid bit
2543      * c n-1.12: actual mask bits
2544      * d  51..n: reserved must be zero
2545      * e  63.52: reserved must be zero
2546      *
2547      * 'n' is the number of physical bits supported by the CPU and is
2548      * apparently always <= 52.   We know our 'n' but don't know what
2549      * the destinations 'n' is; it might be smaller, in which case
2550      * it masks (c) on loading. It might be larger, in which case
2551      * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2552      * we're migrating to.
2553      */
2554
2555     if (cpu->fill_mtrr_mask) {
2556         QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2557         assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2558         mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2559     } else {
2560         mtrr_top_bits = 0;
2561     }
2562
2563     for (i = 0; i < ret; i++) {
2564         uint32_t index = msrs[i].index;
2565         switch (index) {
2566         case MSR_IA32_SYSENTER_CS:
2567             env->sysenter_cs = msrs[i].data;
2568             break;
2569         case MSR_IA32_SYSENTER_ESP:
2570             env->sysenter_esp = msrs[i].data;
2571             break;
2572         case MSR_IA32_SYSENTER_EIP:
2573             env->sysenter_eip = msrs[i].data;
2574             break;
2575         case MSR_PAT:
2576             env->pat = msrs[i].data;
2577             break;
2578         case MSR_STAR:
2579             env->star = msrs[i].data;
2580             break;
2581 #ifdef TARGET_X86_64
2582         case MSR_CSTAR:
2583             env->cstar = msrs[i].data;
2584             break;
2585         case MSR_KERNELGSBASE:
2586             env->kernelgsbase = msrs[i].data;
2587             break;
2588         case MSR_FMASK:
2589             env->fmask = msrs[i].data;
2590             break;
2591         case MSR_LSTAR:
2592             env->lstar = msrs[i].data;
2593             break;
2594 #endif
2595         case MSR_IA32_TSC:
2596             env->tsc = msrs[i].data;
2597             break;
2598         case MSR_TSC_AUX:
2599             env->tsc_aux = msrs[i].data;
2600             break;
2601         case MSR_TSC_ADJUST:
2602             env->tsc_adjust = msrs[i].data;
2603             break;
2604         case MSR_IA32_TSCDEADLINE:
2605             env->tsc_deadline = msrs[i].data;
2606             break;
2607         case MSR_VM_HSAVE_PA:
2608             env->vm_hsave = msrs[i].data;
2609             break;
2610         case MSR_KVM_SYSTEM_TIME:
2611             env->system_time_msr = msrs[i].data;
2612             break;
2613         case MSR_KVM_WALL_CLOCK:
2614             env->wall_clock_msr = msrs[i].data;
2615             break;
2616         case MSR_MCG_STATUS:
2617             env->mcg_status = msrs[i].data;
2618             break;
2619         case MSR_MCG_CTL:
2620             env->mcg_ctl = msrs[i].data;
2621             break;
2622         case MSR_MCG_EXT_CTL:
2623             env->mcg_ext_ctl = msrs[i].data;
2624             break;
2625         case MSR_IA32_MISC_ENABLE:
2626             env->msr_ia32_misc_enable = msrs[i].data;
2627             break;
2628         case MSR_IA32_SMBASE:
2629             env->smbase = msrs[i].data;
2630             break;
2631         case MSR_SMI_COUNT:
2632             env->msr_smi_count = msrs[i].data;
2633             break;
2634         case MSR_IA32_FEATURE_CONTROL:
2635             env->msr_ia32_feature_control = msrs[i].data;
2636             break;
2637         case MSR_IA32_BNDCFGS:
2638             env->msr_bndcfgs = msrs[i].data;
2639             break;
2640         case MSR_IA32_XSS:
2641             env->xss = msrs[i].data;
2642             break;
2643         default:
2644             if (msrs[i].index >= MSR_MC0_CTL &&
2645                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2646                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2647             }
2648             break;
2649         case MSR_KVM_ASYNC_PF_EN:
2650             env->async_pf_en_msr = msrs[i].data;
2651             break;
2652         case MSR_KVM_PV_EOI_EN:
2653             env->pv_eoi_en_msr = msrs[i].data;
2654             break;
2655         case MSR_KVM_STEAL_TIME:
2656             env->steal_time_msr = msrs[i].data;
2657             break;
2658         case MSR_CORE_PERF_FIXED_CTR_CTRL:
2659             env->msr_fixed_ctr_ctrl = msrs[i].data;
2660             break;
2661         case MSR_CORE_PERF_GLOBAL_CTRL:
2662             env->msr_global_ctrl = msrs[i].data;
2663             break;
2664         case MSR_CORE_PERF_GLOBAL_STATUS:
2665             env->msr_global_status = msrs[i].data;
2666             break;
2667         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2668             env->msr_global_ovf_ctrl = msrs[i].data;
2669             break;
2670         case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2671             env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2672             break;
2673         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2674             env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2675             break;
2676         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2677             env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2678             break;
2679         case HV_X64_MSR_HYPERCALL:
2680             env->msr_hv_hypercall = msrs[i].data;
2681             break;
2682         case HV_X64_MSR_GUEST_OS_ID:
2683             env->msr_hv_guest_os_id = msrs[i].data;
2684             break;
2685         case HV_X64_MSR_APIC_ASSIST_PAGE:
2686             env->msr_hv_vapic = msrs[i].data;
2687             break;
2688         case HV_X64_MSR_REFERENCE_TSC:
2689             env->msr_hv_tsc = msrs[i].data;
2690             break;
2691         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2692             env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2693             break;
2694         case HV_X64_MSR_VP_RUNTIME:
2695             env->msr_hv_runtime = msrs[i].data;
2696             break;
2697         case HV_X64_MSR_SCONTROL:
2698             env->msr_hv_synic_control = msrs[i].data;
2699             break;
2700         case HV_X64_MSR_SIEFP:
2701             env->msr_hv_synic_evt_page = msrs[i].data;
2702             break;
2703         case HV_X64_MSR_SIMP:
2704             env->msr_hv_synic_msg_page = msrs[i].data;
2705             break;
2706         case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2707             env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2708             break;
2709         case HV_X64_MSR_STIMER0_CONFIG:
2710         case HV_X64_MSR_STIMER1_CONFIG:
2711         case HV_X64_MSR_STIMER2_CONFIG:
2712         case HV_X64_MSR_STIMER3_CONFIG:
2713             env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2714                                 msrs[i].data;
2715             break;
2716         case HV_X64_MSR_STIMER0_COUNT:
2717         case HV_X64_MSR_STIMER1_COUNT:
2718         case HV_X64_MSR_STIMER2_COUNT:
2719         case HV_X64_MSR_STIMER3_COUNT:
2720             env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2721                                 msrs[i].data;
2722             break;
2723         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2724             env->msr_hv_reenlightenment_control = msrs[i].data;
2725             break;
2726         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2727             env->msr_hv_tsc_emulation_control = msrs[i].data;
2728             break;
2729         case HV_X64_MSR_TSC_EMULATION_STATUS:
2730             env->msr_hv_tsc_emulation_status = msrs[i].data;
2731             break;
2732         case MSR_MTRRdefType:
2733             env->mtrr_deftype = msrs[i].data;
2734             break;
2735         case MSR_MTRRfix64K_00000:
2736             env->mtrr_fixed[0] = msrs[i].data;
2737             break;
2738         case MSR_MTRRfix16K_80000:
2739             env->mtrr_fixed[1] = msrs[i].data;
2740             break;
2741         case MSR_MTRRfix16K_A0000:
2742             env->mtrr_fixed[2] = msrs[i].data;
2743             break;
2744         case MSR_MTRRfix4K_C0000:
2745             env->mtrr_fixed[3] = msrs[i].data;
2746             break;
2747         case MSR_MTRRfix4K_C8000:
2748             env->mtrr_fixed[4] = msrs[i].data;
2749             break;
2750         case MSR_MTRRfix4K_D0000:
2751             env->mtrr_fixed[5] = msrs[i].data;
2752             break;
2753         case MSR_MTRRfix4K_D8000:
2754             env->mtrr_fixed[6] = msrs[i].data;
2755             break;
2756         case MSR_MTRRfix4K_E0000:
2757             env->mtrr_fixed[7] = msrs[i].data;
2758             break;
2759         case MSR_MTRRfix4K_E8000:
2760             env->mtrr_fixed[8] = msrs[i].data;
2761             break;
2762         case MSR_MTRRfix4K_F0000:
2763             env->mtrr_fixed[9] = msrs[i].data;
2764             break;
2765         case MSR_MTRRfix4K_F8000:
2766             env->mtrr_fixed[10] = msrs[i].data;
2767             break;
2768         case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2769             if (index & 1) {
2770                 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2771                                                                mtrr_top_bits;
2772             } else {
2773                 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2774             }
2775             break;
2776         case MSR_IA32_SPEC_CTRL:
2777             env->spec_ctrl = msrs[i].data;
2778             break;
2779         case MSR_VIRT_SSBD:
2780             env->virt_ssbd = msrs[i].data;
2781             break;
2782         case MSR_IA32_RTIT_CTL:
2783             env->msr_rtit_ctrl = msrs[i].data;
2784             break;
2785         case MSR_IA32_RTIT_STATUS:
2786             env->msr_rtit_status = msrs[i].data;
2787             break;
2788         case MSR_IA32_RTIT_OUTPUT_BASE:
2789             env->msr_rtit_output_base = msrs[i].data;
2790             break;
2791         case MSR_IA32_RTIT_OUTPUT_MASK:
2792             env->msr_rtit_output_mask = msrs[i].data;
2793             break;
2794         case MSR_IA32_RTIT_CR3_MATCH:
2795             env->msr_rtit_cr3_match = msrs[i].data;
2796             break;
2797         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2798             env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2799             break;
2800         }
2801     }
2802
2803     return 0;
2804 }
2805
2806 static int kvm_put_mp_state(X86CPU *cpu)
2807 {
2808     struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2809
2810     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2811 }
2812
2813 static int kvm_get_mp_state(X86CPU *cpu)
2814 {
2815     CPUState *cs = CPU(cpu);
2816     CPUX86State *env = &cpu->env;
2817     struct kvm_mp_state mp_state;
2818     int ret;
2819
2820     ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2821     if (ret < 0) {
2822         return ret;
2823     }
2824     env->mp_state = mp_state.mp_state;
2825     if (kvm_irqchip_in_kernel()) {
2826         cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2827     }
2828     return 0;
2829 }
2830
2831 static int kvm_get_apic(X86CPU *cpu)
2832 {
2833     DeviceState *apic = cpu->apic_state;
2834     struct kvm_lapic_state kapic;
2835     int ret;
2836
2837     if (apic && kvm_irqchip_in_kernel()) {
2838         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2839         if (ret < 0) {
2840             return ret;
2841         }
2842
2843         kvm_get_apic_state(apic, &kapic);
2844     }
2845     return 0;
2846 }
2847
2848 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2849 {
2850     CPUState *cs = CPU(cpu);
2851     CPUX86State *env = &cpu->env;
2852     struct kvm_vcpu_events events = {};
2853
2854     if (!kvm_has_vcpu_events()) {
2855         return 0;
2856     }
2857
2858     events.exception.injected = (env->exception_injected >= 0);
2859     events.exception.nr = env->exception_injected;
2860     events.exception.has_error_code = env->has_error_code;
2861     events.exception.error_code = env->error_code;
2862
2863     events.interrupt.injected = (env->interrupt_injected >= 0);
2864     events.interrupt.nr = env->interrupt_injected;
2865     events.interrupt.soft = env->soft_interrupt;
2866
2867     events.nmi.injected = env->nmi_injected;
2868     events.nmi.pending = env->nmi_pending;
2869     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2870
2871     events.sipi_vector = env->sipi_vector;
2872     events.flags = 0;
2873
2874     if (has_msr_smbase) {
2875         events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2876         events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2877         if (kvm_irqchip_in_kernel()) {
2878             /* As soon as these are moved to the kernel, remove them
2879              * from cs->interrupt_request.
2880              */
2881             events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2882             events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2883             cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2884         } else {
2885             /* Keep these in cs->interrupt_request.  */
2886             events.smi.pending = 0;
2887             events.smi.latched_init = 0;
2888         }
2889         /* Stop SMI delivery on old machine types to avoid a reboot
2890          * on an inward migration of an old VM.
2891          */
2892         if (!cpu->kvm_no_smi_migration) {
2893             events.flags |= KVM_VCPUEVENT_VALID_SMM;
2894         }
2895     }
2896
2897     if (level >= KVM_PUT_RESET_STATE) {
2898         events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2899         if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2900             events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2901         }
2902     }
2903
2904     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2905 }
2906
2907 static int kvm_get_vcpu_events(X86CPU *cpu)
2908 {
2909     CPUX86State *env = &cpu->env;
2910     struct kvm_vcpu_events events;
2911     int ret;
2912
2913     if (!kvm_has_vcpu_events()) {
2914         return 0;
2915     }
2916
2917     memset(&events, 0, sizeof(events));
2918     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2919     if (ret < 0) {
2920        return ret;
2921     }
2922     env->exception_injected =
2923        events.exception.injected ? events.exception.nr : -1;
2924     env->has_error_code = events.exception.has_error_code;
2925     env->error_code = events.exception.error_code;
2926
2927     env->interrupt_injected =
2928         events.interrupt.injected ? events.interrupt.nr : -1;
2929     env->soft_interrupt = events.interrupt.soft;
2930
2931     env->nmi_injected = events.nmi.injected;
2932     env->nmi_pending = events.nmi.pending;
2933     if (events.nmi.masked) {
2934         env->hflags2 |= HF2_NMI_MASK;
2935     } else {
2936         env->hflags2 &= ~HF2_NMI_MASK;
2937     }
2938
2939     if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2940         if (events.smi.smm) {
2941             env->hflags |= HF_SMM_MASK;
2942         } else {
2943             env->hflags &= ~HF_SMM_MASK;
2944         }
2945         if (events.smi.pending) {
2946             cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2947         } else {
2948             cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2949         }
2950         if (events.smi.smm_inside_nmi) {
2951             env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2952         } else {
2953             env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2954         }
2955         if (events.smi.latched_init) {
2956             cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2957         } else {
2958             cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2959         }
2960     }
2961
2962     env->sipi_vector = events.sipi_vector;
2963
2964     return 0;
2965 }
2966
2967 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2968 {
2969     CPUState *cs = CPU(cpu);
2970     CPUX86State *env = &cpu->env;
2971     int ret = 0;
2972     unsigned long reinject_trap = 0;
2973
2974     if (!kvm_has_vcpu_events()) {
2975         if (env->exception_injected == 1) {
2976             reinject_trap = KVM_GUESTDBG_INJECT_DB;
2977         } else if (env->exception_injected == 3) {
2978             reinject_trap = KVM_GUESTDBG_INJECT_BP;
2979         }
2980         env->exception_injected = -1;
2981     }
2982
2983     /*
2984      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2985      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2986      * by updating the debug state once again if single-stepping is on.
2987      * Another reason to call kvm_update_guest_debug here is a pending debug
2988      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2989      * reinject them via SET_GUEST_DEBUG.
2990      */
2991     if (reinject_trap ||
2992         (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2993         ret = kvm_update_guest_debug(cs, reinject_trap);
2994     }
2995     return ret;
2996 }
2997
2998 static int kvm_put_debugregs(X86CPU *cpu)
2999 {
3000     CPUX86State *env = &cpu->env;
3001     struct kvm_debugregs dbgregs;
3002     int i;
3003
3004     if (!kvm_has_debugregs()) {
3005         return 0;
3006     }
3007
3008     for (i = 0; i < 4; i++) {
3009         dbgregs.db[i] = env->dr[i];
3010     }
3011     dbgregs.dr6 = env->dr[6];
3012     dbgregs.dr7 = env->dr[7];
3013     dbgregs.flags = 0;
3014
3015     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
3016 }
3017
3018 static int kvm_get_debugregs(X86CPU *cpu)
3019 {
3020     CPUX86State *env = &cpu->env;
3021     struct kvm_debugregs dbgregs;
3022     int i, ret;
3023
3024     if (!kvm_has_debugregs()) {
3025         return 0;
3026     }
3027
3028     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
3029     if (ret < 0) {
3030         return ret;
3031     }
3032     for (i = 0; i < 4; i++) {
3033         env->dr[i] = dbgregs.db[i];
3034     }
3035     env->dr[4] = env->dr[6] = dbgregs.dr6;
3036     env->dr[5] = env->dr[7] = dbgregs.dr7;
3037
3038     return 0;
3039 }
3040
3041 int kvm_arch_put_registers(CPUState *cpu, int level)
3042 {
3043     X86CPU *x86_cpu = X86_CPU(cpu);
3044     int ret;
3045
3046     assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
3047
3048     if (level >= KVM_PUT_RESET_STATE) {
3049         ret = kvm_put_msr_feature_control(x86_cpu);
3050         if (ret < 0) {
3051             return ret;
3052         }
3053     }
3054
3055     if (level == KVM_PUT_FULL_STATE) {
3056         /* We don't check for kvm_arch_set_tsc_khz() errors here,
3057          * because TSC frequency mismatch shouldn't abort migration,
3058          * unless the user explicitly asked for a more strict TSC
3059          * setting (e.g. using an explicit "tsc-freq" option).
3060          */
3061         kvm_arch_set_tsc_khz(cpu);
3062     }
3063
3064     ret = kvm_getput_regs(x86_cpu, 1);
3065     if (ret < 0) {
3066         return ret;
3067     }
3068     ret = kvm_put_xsave(x86_cpu);
3069     if (ret < 0) {
3070         return ret;
3071     }
3072     ret = kvm_put_xcrs(x86_cpu);
3073     if (ret < 0) {
3074         return ret;
3075     }
3076     ret = kvm_put_sregs(x86_cpu);
3077     if (ret < 0) {
3078         return ret;
3079     }
3080     /* must be before kvm_put_msrs */
3081     ret = kvm_inject_mce_oldstyle(x86_cpu);
3082     if (ret < 0) {
3083         return ret;
3084     }
3085     ret = kvm_put_msrs(x86_cpu, level);
3086     if (ret < 0) {
3087         return ret;
3088     }
3089     ret = kvm_put_vcpu_events(x86_cpu, level);
3090     if (ret < 0) {
3091         return ret;
3092     }
3093     if (level >= KVM_PUT_RESET_STATE) {
3094         ret = kvm_put_mp_state(x86_cpu);
3095         if (ret < 0) {
3096             return ret;
3097         }
3098     }
3099
3100     ret = kvm_put_tscdeadline_msr(x86_cpu);
3101     if (ret < 0) {
3102         return ret;
3103     }
3104     ret = kvm_put_debugregs(x86_cpu);
3105     if (ret < 0) {
3106         return ret;
3107     }
3108     /* must be last */
3109     ret = kvm_guest_debug_workarounds(x86_cpu);
3110     if (ret < 0) {
3111         return ret;
3112     }
3113     return 0;
3114 }
3115
3116 int kvm_arch_get_registers(CPUState *cs)
3117 {
3118     X86CPU *cpu = X86_CPU(cs);
3119     int ret;
3120
3121     assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
3122
3123     ret = kvm_get_vcpu_events(cpu);
3124     if (ret < 0) {
3125         goto out;
3126     }
3127     /*
3128      * KVM_GET_MPSTATE can modify CS and RIP, call it before
3129      * KVM_GET_REGS and KVM_GET_SREGS.
3130      */
3131     ret = kvm_get_mp_state(cpu);
3132     if (ret < 0) {
3133         goto out;
3134     }
3135     ret = kvm_getput_regs(cpu, 0);
3136     if (ret < 0) {
3137         goto out;
3138     }
3139     ret = kvm_get_xsave(cpu);
3140     if (ret < 0) {
3141         goto out;
3142     }
3143     ret = kvm_get_xcrs(cpu);
3144     if (ret < 0) {
3145         goto out;
3146     }
3147     ret = kvm_get_sregs(cpu);
3148     if (ret < 0) {
3149         goto out;
3150     }
3151     ret = kvm_get_msrs(cpu);
3152     if (ret < 0) {
3153         goto out;
3154     }
3155     ret = kvm_get_apic(cpu);
3156     if (ret < 0) {
3157         goto out;
3158     }
3159     ret = kvm_get_debugregs(cpu);
3160     if (ret < 0) {
3161         goto out;
3162     }
3163     ret = 0;
3164  out:
3165     cpu_sync_bndcs_hflags(&cpu->env);
3166     return ret;
3167 }
3168
3169 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
3170 {
3171     X86CPU *x86_cpu = X86_CPU(cpu);
3172     CPUX86State *env = &x86_cpu->env;
3173     int ret;
3174
3175     /* Inject NMI */
3176     if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3177         if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3178             qemu_mutex_lock_iothread();
3179             cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3180             qemu_mutex_unlock_iothread();
3181             DPRINTF("injected NMI\n");
3182             ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3183             if (ret < 0) {
3184                 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3185                         strerror(-ret));
3186             }
3187         }
3188         if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3189             qemu_mutex_lock_iothread();
3190             cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3191             qemu_mutex_unlock_iothread();
3192             DPRINTF("injected SMI\n");
3193             ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3194             if (ret < 0) {
3195                 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3196                         strerror(-ret));
3197             }
3198         }
3199     }
3200
3201     if (!kvm_pic_in_kernel()) {
3202         qemu_mutex_lock_iothread();
3203     }
3204
3205     /* Force the VCPU out of its inner loop to process any INIT requests
3206      * or (for userspace APIC, but it is cheap to combine the checks here)
3207      * pending TPR access reports.
3208      */
3209     if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
3210         if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3211             !(env->hflags & HF_SMM_MASK)) {
3212             cpu->exit_request = 1;
3213         }
3214         if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3215             cpu->exit_request = 1;
3216         }
3217     }
3218
3219     if (!kvm_pic_in_kernel()) {
3220         /* Try to inject an interrupt if the guest can accept it */
3221         if (run->ready_for_interrupt_injection &&
3222             (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
3223             (env->eflags & IF_MASK)) {
3224             int irq;
3225
3226             cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
3227             irq = cpu_get_pic_interrupt(env);
3228             if (irq >= 0) {
3229                 struct kvm_interrupt intr;
3230
3231                 intr.irq = irq;
3232                 DPRINTF("injected interrupt %d\n", irq);
3233                 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
3234                 if (ret < 0) {
3235                     fprintf(stderr,
3236                             "KVM: injection failed, interrupt lost (%s)\n",
3237                             strerror(-ret));
3238                 }
3239             }
3240         }
3241
3242         /* If we have an interrupt but the guest is not ready to receive an
3243          * interrupt, request an interrupt window exit.  This will
3244          * cause a return to userspace as soon as the guest is ready to
3245          * receive interrupts. */
3246         if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
3247             run->request_interrupt_window = 1;
3248         } else {
3249             run->request_interrupt_window = 0;
3250         }
3251
3252         DPRINTF("setting tpr\n");
3253         run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
3254
3255         qemu_mutex_unlock_iothread();
3256     }
3257 }
3258
3259 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
3260 {
3261     X86CPU *x86_cpu = X86_CPU(cpu);
3262     CPUX86State *env = &x86_cpu->env;
3263
3264     if (run->flags & KVM_RUN_X86_SMM) {
3265         env->hflags |= HF_SMM_MASK;
3266     } else {
3267         env->hflags &= ~HF_SMM_MASK;
3268     }
3269     if (run->if_flag) {
3270         env->eflags |= IF_MASK;
3271     } else {
3272         env->eflags &= ~IF_MASK;
3273     }
3274
3275     /* We need to protect the apic state against concurrent accesses from
3276      * different threads in case the userspace irqchip is used. */
3277     if (!kvm_irqchip_in_kernel()) {
3278         qemu_mutex_lock_iothread();
3279     }
3280     cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3281     cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
3282     if (!kvm_irqchip_in_kernel()) {
3283         qemu_mutex_unlock_iothread();
3284     }
3285     return cpu_get_mem_attrs(env);
3286 }
3287
3288 int kvm_arch_process_async_events(CPUState *cs)
3289 {
3290     X86CPU *cpu = X86_CPU(cs);
3291     CPUX86State *env = &cpu->env;
3292
3293     if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
3294         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3295         assert(env->mcg_cap);
3296
3297         cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
3298
3299         kvm_cpu_synchronize_state(cs);
3300
3301         if (env->exception_injected == EXCP08_DBLE) {
3302             /* this means triple fault */
3303             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
3304             cs->exit_request = 1;
3305             return 0;
3306         }
3307         env->exception_injected = EXCP12_MCHK;
3308         env->has_error_code = 0;
3309
3310         cs->halted = 0;
3311         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3312             env->mp_state = KVM_MP_STATE_RUNNABLE;
3313         }
3314     }
3315
3316     if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3317         !(env->hflags & HF_SMM_MASK)) {
3318         kvm_cpu_synchronize_state(cs);
3319         do_cpu_init(cpu);
3320     }
3321
3322     if (kvm_irqchip_in_kernel()) {
3323         return 0;
3324     }
3325
3326     if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3327         cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
3328         apic_poll_irq(cpu->apic_state);
3329     }
3330     if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3331          (env->eflags & IF_MASK)) ||
3332         (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3333         cs->halted = 0;
3334     }
3335     if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
3336         kvm_cpu_synchronize_state(cs);
3337         do_cpu_sipi(cpu);
3338     }
3339     if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3340         cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
3341         kvm_cpu_synchronize_state(cs);
3342         apic_handle_tpr_access_report(cpu->apic_state, env->eip,
3343                                       env->tpr_access_type);
3344     }
3345
3346     return cs->halted;
3347 }
3348
3349 static int kvm_handle_halt(X86CPU *cpu)
3350 {
3351     CPUState *cs = CPU(cpu);
3352     CPUX86State *env = &cpu->env;
3353
3354     if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3355           (env->eflags & IF_MASK)) &&
3356         !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3357         cs->halted = 1;
3358         return EXCP_HLT;
3359     }
3360
3361     return 0;
3362 }
3363
3364 static int kvm_handle_tpr_access(X86CPU *cpu)
3365 {
3366     CPUState *cs = CPU(cpu);
3367     struct kvm_run *run = cs->kvm_run;
3368
3369     apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3370                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
3371                                                            : TPR_ACCESS_READ);
3372     return 1;
3373 }
3374
3375 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3376 {
3377     static const uint8_t int3 = 0xcc;
3378
3379     if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3380         cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3381         return -EINVAL;
3382     }
3383     return 0;
3384 }
3385
3386 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3387 {
3388     uint8_t int3;
3389
3390     if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3391         cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3392         return -EINVAL;
3393     }
3394     return 0;
3395 }
3396
3397 static struct {
3398     target_ulong addr;
3399     int len;
3400     int type;
3401 } hw_breakpoint[4];
3402
3403 static int nb_hw_breakpoint;
3404
3405 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3406 {
3407     int n;
3408
3409     for (n = 0; n < nb_hw_breakpoint; n++) {
3410         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3411             (hw_breakpoint[n].len == len || len == -1)) {
3412             return n;
3413         }
3414     }
3415     return -1;
3416 }
3417
3418 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3419                                   target_ulong len, int type)
3420 {
3421     switch (type) {
3422     case GDB_BREAKPOINT_HW:
3423         len = 1;
3424         break;
3425     case GDB_WATCHPOINT_WRITE:
3426     case GDB_WATCHPOINT_ACCESS:
3427         switch (len) {
3428         case 1:
3429             break;
3430         case 2:
3431         case 4:
3432         case 8:
3433             if (addr & (len - 1)) {
3434                 return -EINVAL;
3435             }
3436             break;
3437         default:
3438             return -EINVAL;
3439         }
3440         break;
3441     default:
3442         return -ENOSYS;
3443     }
3444
3445     if (nb_hw_breakpoint == 4) {
3446         return -ENOBUFS;
3447     }
3448     if (find_hw_breakpoint(addr, len, type) >= 0) {
3449         return -EEXIST;
3450     }
3451     hw_breakpoint[nb_hw_breakpoint].addr = addr;
3452     hw_breakpoint[nb_hw_breakpoint].len = len;
3453     hw_breakpoint[nb_hw_breakpoint].type = type;
3454     nb_hw_breakpoint++;
3455
3456     return 0;
3457 }
3458
3459 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3460                                   target_ulong len, int type)
3461 {
3462     int n;
3463
3464     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3465     if (n < 0) {
3466         return -ENOENT;
3467     }
3468     nb_hw_breakpoint--;
3469     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3470
3471     return 0;
3472 }
3473
3474 void kvm_arch_remove_all_hw_breakpoints(void)
3475 {
3476     nb_hw_breakpoint = 0;
3477 }
3478
3479 static CPUWatchpoint hw_watchpoint;
3480
3481 static int kvm_handle_debug(X86CPU *cpu,
3482                             struct kvm_debug_exit_arch *arch_info)
3483 {
3484     CPUState *cs = CPU(cpu);
3485     CPUX86State *env = &cpu->env;
3486     int ret = 0;
3487     int n;
3488
3489     if (arch_info->exception == 1) {
3490         if (arch_info->dr6 & (1 << 14)) {
3491             if (cs->singlestep_enabled) {
3492                 ret = EXCP_DEBUG;
3493             }
3494         } else {
3495             for (n = 0; n < 4; n++) {
3496                 if (arch_info->dr6 & (1 << n)) {
3497                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3498                     case 0x0:
3499                         ret = EXCP_DEBUG;
3500                         break;
3501                     case 0x1:
3502                         ret = EXCP_DEBUG;
3503                         cs->watchpoint_hit = &hw_watchpoint;
3504                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3505                         hw_watchpoint.flags = BP_MEM_WRITE;
3506                         break;
3507                     case 0x3:
3508                         ret = EXCP_DEBUG;
3509                         cs->watchpoint_hit = &hw_watchpoint;
3510                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3511                         hw_watchpoint.flags = BP_MEM_ACCESS;
3512                         break;
3513                     }
3514                 }
3515             }
3516         }
3517     } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3518         ret = EXCP_DEBUG;
3519     }
3520     if (ret == 0) {
3521         cpu_synchronize_state(cs);
3522         assert(env->exception_injected == -1);
3523
3524         /* pass to guest */
3525         env->exception_injected = arch_info->exception;
3526         env->has_error_code = 0;
3527     }
3528
3529     return ret;
3530 }
3531
3532 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3533 {
3534     const uint8_t type_code[] = {
3535         [GDB_BREAKPOINT_HW] = 0x0,
3536         [GDB_WATCHPOINT_WRITE] = 0x1,
3537         [GDB_WATCHPOINT_ACCESS] = 0x3
3538     };
3539     const uint8_t len_code[] = {
3540         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3541     };
3542     int n;
3543
3544     if (kvm_sw_breakpoints_active(cpu)) {
3545         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3546     }
3547     if (nb_hw_breakpoint > 0) {
3548         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3549         dbg->arch.debugreg[7] = 0x0600;
3550         for (n = 0; n < nb_hw_breakpoint; n++) {
3551             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3552             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3553                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3554                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3555         }
3556     }
3557 }
3558
3559 static bool host_supports_vmx(void)
3560 {
3561     uint32_t ecx, unused;
3562
3563     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3564     return ecx & CPUID_EXT_VMX;
3565 }
3566
3567 #define VMX_INVALID_GUEST_STATE 0x80000021
3568
3569 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3570 {
3571     X86CPU *cpu = X86_CPU(cs);
3572     uint64_t code;
3573     int ret;
3574
3575     switch (run->exit_reason) {
3576     case KVM_EXIT_HLT:
3577         DPRINTF("handle_hlt\n");
3578         qemu_mutex_lock_iothread();
3579         ret = kvm_handle_halt(cpu);
3580         qemu_mutex_unlock_iothread();
3581         break;
3582     case KVM_EXIT_SET_TPR:
3583         ret = 0;
3584         break;
3585     case KVM_EXIT_TPR_ACCESS:
3586         qemu_mutex_lock_iothread();
3587         ret = kvm_handle_tpr_access(cpu);
3588         qemu_mutex_unlock_iothread();
3589         break;
3590     case KVM_EXIT_FAIL_ENTRY:
3591         code = run->fail_entry.hardware_entry_failure_reason;
3592         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3593                 code);
3594         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3595             fprintf(stderr,
3596                     "\nIf you're running a guest on an Intel machine without "
3597                         "unrestricted mode\n"
3598                     "support, the failure can be most likely due to the guest "
3599                         "entering an invalid\n"
3600                     "state for Intel VT. For example, the guest maybe running "
3601                         "in big real mode\n"
3602                     "which is not supported on less recent Intel processors."
3603                         "\n\n");
3604         }
3605         ret = -1;
3606         break;
3607     case KVM_EXIT_EXCEPTION:
3608         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3609                 run->ex.exception, run->ex.error_code);
3610         ret = -1;
3611         break;
3612     case KVM_EXIT_DEBUG:
3613         DPRINTF("kvm_exit_debug\n");
3614         qemu_mutex_lock_iothread();
3615         ret = kvm_handle_debug(cpu, &run->debug.arch);
3616         qemu_mutex_unlock_iothread();
3617         break;
3618     case KVM_EXIT_HYPERV:
3619         ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3620         break;
3621     case KVM_EXIT_IOAPIC_EOI:
3622         ioapic_eoi_broadcast(run->eoi.vector);
3623         ret = 0;
3624         break;
3625     default:
3626         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3627         ret = -1;
3628         break;
3629     }
3630
3631     return ret;
3632 }
3633
3634 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3635 {
3636     X86CPU *cpu = X86_CPU(cs);
3637     CPUX86State *env = &cpu->env;
3638
3639     kvm_cpu_synchronize_state(cs);
3640     return !(env->cr[0] & CR0_PE_MASK) ||
3641            ((env->segs[R_CS].selector  & 3) != 3);
3642 }
3643
3644 void kvm_arch_init_irq_routing(KVMState *s)
3645 {
3646     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3647         /* If kernel can't do irq routing, interrupt source
3648          * override 0->2 cannot be set up as required by HPET.
3649          * So we have to disable it.
3650          */
3651         no_hpet = 1;
3652     }
3653     /* We know at this point that we're using the in-kernel
3654      * irqchip, so we can use irqfds, and on x86 we know
3655      * we can use msi via irqfd and GSI routing.
3656      */
3657     kvm_msi_via_irqfd_allowed = true;
3658     kvm_gsi_routing_allowed = true;
3659
3660     if (kvm_irqchip_is_split()) {
3661         int i;
3662
3663         /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3664            MSI routes for signaling interrupts to the local apics. */
3665         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3666             if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3667                 error_report("Could not enable split IRQ mode.");
3668                 exit(1);
3669             }
3670         }
3671     }
3672 }
3673
3674 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3675 {
3676     int ret;
3677     if (machine_kernel_irqchip_split(ms)) {
3678         ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3679         if (ret) {
3680             error_report("Could not enable split irqchip mode: %s",
3681                          strerror(-ret));
3682             exit(1);
3683         } else {
3684             DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3685             kvm_split_irqchip = true;
3686             return 1;
3687         }
3688     } else {
3689         return 0;
3690     }
3691 }
3692
3693 /* Classic KVM device assignment interface. Will remain x86 only. */
3694 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3695                           uint32_t flags, uint32_t *dev_id)
3696 {
3697     struct kvm_assigned_pci_dev dev_data = {
3698         .segnr = dev_addr->domain,
3699         .busnr = dev_addr->bus,
3700         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3701         .flags = flags,
3702     };
3703     int ret;
3704
3705     dev_data.assigned_dev_id =
3706         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3707
3708     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3709     if (ret < 0) {
3710         return ret;
3711     }
3712
3713     *dev_id = dev_data.assigned_dev_id;
3714
3715     return 0;
3716 }
3717
3718 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3719 {
3720     struct kvm_assigned_pci_dev dev_data = {
3721         .assigned_dev_id = dev_id,
3722     };
3723
3724     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3725 }
3726
3727 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3728                                    uint32_t irq_type, uint32_t guest_irq)
3729 {
3730     struct kvm_assigned_irq assigned_irq = {
3731         .assigned_dev_id = dev_id,
3732         .guest_irq = guest_irq,
3733         .flags = irq_type,
3734     };
3735
3736     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3737         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3738     } else {
3739         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3740     }
3741 }
3742
3743 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3744                            uint32_t guest_irq)
3745 {
3746     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3747         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3748
3749     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3750 }
3751
3752 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3753 {
3754     struct kvm_assigned_pci_dev dev_data = {
3755         .assigned_dev_id = dev_id,
3756         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3757     };
3758
3759     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3760 }
3761
3762 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3763                                      uint32_t type)
3764 {
3765     struct kvm_assigned_irq assigned_irq = {
3766         .assigned_dev_id = dev_id,
3767         .flags = type,
3768     };
3769
3770     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3771 }
3772
3773 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3774 {
3775     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3776         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3777 }
3778
3779 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3780 {
3781     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3782                                               KVM_DEV_IRQ_GUEST_MSI, virq);
3783 }
3784
3785 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3786 {
3787     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3788                                                 KVM_DEV_IRQ_HOST_MSI);
3789 }
3790
3791 bool kvm_device_msix_supported(KVMState *s)
3792 {
3793     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3794      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3795     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3796 }
3797
3798 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3799                                  uint32_t nr_vectors)
3800 {
3801     struct kvm_assigned_msix_nr msix_nr = {
3802         .assigned_dev_id = dev_id,
3803         .entry_nr = nr_vectors,
3804     };
3805
3806     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3807 }
3808
3809 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3810                                int virq)
3811 {
3812     struct kvm_assigned_msix_entry msix_entry = {
3813         .assigned_dev_id = dev_id,
3814         .gsi = virq,
3815         .entry = vector,
3816     };
3817
3818     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3819 }
3820
3821 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3822 {
3823     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3824                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
3825 }
3826
3827 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3828 {
3829     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3830                                                 KVM_DEV_IRQ_HOST_MSIX);
3831 }
3832
3833 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3834                              uint64_t address, uint32_t data, PCIDevice *dev)
3835 {
3836     X86IOMMUState *iommu = x86_iommu_get_default();
3837
3838     if (iommu) {
3839         int ret;
3840         MSIMessage src, dst;
3841         X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3842
3843         if (!class->int_remap) {
3844             return 0;
3845         }
3846
3847         src.address = route->u.msi.address_hi;
3848         src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3849         src.address |= route->u.msi.address_lo;
3850         src.data = route->u.msi.data;
3851
3852         ret = class->int_remap(iommu, &src, &dst, dev ? \
3853                                pci_requester_id(dev) : \
3854                                X86_IOMMU_SID_INVALID);
3855         if (ret) {
3856             trace_kvm_x86_fixup_msi_error(route->gsi);
3857             return 1;
3858         }
3859
3860         route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3861         route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3862         route->u.msi.data = dst.data;
3863     }
3864
3865     return 0;
3866 }
3867
3868 typedef struct MSIRouteEntry MSIRouteEntry;
3869
3870 struct MSIRouteEntry {
3871     PCIDevice *dev;             /* Device pointer */
3872     int vector;                 /* MSI/MSIX vector index */
3873     int virq;                   /* Virtual IRQ index */
3874     QLIST_ENTRY(MSIRouteEntry) list;
3875 };
3876
3877 /* List of used GSI routes */
3878 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3879     QLIST_HEAD_INITIALIZER(msi_route_list);
3880
3881 static void kvm_update_msi_routes_all(void *private, bool global,
3882                                       uint32_t index, uint32_t mask)
3883 {
3884     int cnt = 0;
3885     MSIRouteEntry *entry;
3886     MSIMessage msg;
3887     PCIDevice *dev;
3888
3889     /* TODO: explicit route update */
3890     QLIST_FOREACH(entry, &msi_route_list, list) {
3891         cnt++;
3892         dev = entry->dev;
3893         if (!msix_enabled(dev) && !msi_enabled(dev)) {
3894             continue;
3895         }
3896         msg = pci_get_msi_message(dev, entry->vector);
3897         kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3898     }
3899     kvm_irqchip_commit_routes(kvm_state);
3900     trace_kvm_x86_update_msi_routes(cnt);
3901 }
3902
3903 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3904                                 int vector, PCIDevice *dev)
3905 {
3906     static bool notify_list_inited = false;
3907     MSIRouteEntry *entry;
3908
3909     if (!dev) {
3910         /* These are (possibly) IOAPIC routes only used for split
3911          * kernel irqchip mode, while what we are housekeeping are
3912          * PCI devices only. */
3913         return 0;
3914     }
3915
3916     entry = g_new0(MSIRouteEntry, 1);
3917     entry->dev = dev;
3918     entry->vector = vector;
3919     entry->virq = route->gsi;
3920     QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3921
3922     trace_kvm_x86_add_msi_route(route->gsi);
3923
3924     if (!notify_list_inited) {
3925         /* For the first time we do add route, add ourselves into
3926          * IOMMU's IEC notify list if needed. */
3927         X86IOMMUState *iommu = x86_iommu_get_default();
3928         if (iommu) {
3929             x86_iommu_iec_register_notifier(iommu,
3930                                             kvm_update_msi_routes_all,
3931                                             NULL);
3932         }
3933         notify_list_inited = true;
3934     }
3935     return 0;
3936 }
3937
3938 int kvm_arch_release_virq_post(int virq)
3939 {
3940     MSIRouteEntry *entry, *next;
3941     QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3942         if (entry->virq == virq) {
3943             trace_kvm_x86_remove_msi_route(virq);
3944             QLIST_REMOVE(entry, list);
3945             g_free(entry);
3946             break;
3947         }
3948     }
3949     return 0;
3950 }
3951
3952 int kvm_arch_msi_data_to_gsi(uint32_t data)
3953 {
3954     abort();
3955 }