target/i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "qapi/error.h"
  17 #include <sys/ioctl.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include "standard-headers/asm-x86/kvm_para.h"
  22
  23 #include "qemu-common.h"
  24 #include "cpu.h"
  25 #include "sysemu/sysemu.h"
  26 #include "sysemu/hw_accel.h"
  27 #include "sysemu/kvm_int.h"
  28 #include "kvm_i386.h"
  29 #include "hyperv.h"
  30 #include "hyperv-proto.h"
  31
  32 #include "exec/gdbstub.h"
  33 #include "qemu/host-utils.h"
  34 #include "qemu/config-file.h"
  35 #include "qemu/error-report.h"
  36 #include "hw/i386/pc.h"
  37 #include "hw/i386/apic.h"
  38 #include "hw/i386/apic_internal.h"
  39 #include "hw/i386/apic-msidef.h"
  40 #include "hw/i386/intel_iommu.h"
  41 #include "hw/i386/x86-iommu.h"
  42
  43 #include "hw/pci/pci.h"
  44 #include "hw/pci/msi.h"
  45 #include "hw/pci/msix.h"
  46 #include "migration/blocker.h"
  47 #include "exec/memattrs.h"
  48 #include "trace.h"
  49
  50 //#define DEBUG_KVM
  51
  52 #ifdef DEBUG_KVM
  53 #define DPRINTF(fmt, ...) \
  54     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  55 #else
  56 #define DPRINTF(fmt, ...) \
  57     do { } while (0)
  58 #endif
  59
  60 #define MSR_KVM_WALL_CLOCK  0x11
  61 #define MSR_KVM_SYSTEM_TIME 0x12
  62
  63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
  64  * 255 kvm_msr_entry structs */
  65 #define MSR_BUF_SIZE 4096
  66
  67 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  68     KVM_CAP_INFO(SET_TSS_ADDR),
  69     KVM_CAP_INFO(EXT_CPUID),
  70     KVM_CAP_INFO(MP_STATE),
  71     KVM_CAP_LAST_INFO
  72 };
  73
  74 static bool has_msr_star;
  75 static bool has_msr_hsave_pa;
  76 static bool has_msr_tsc_aux;
  77 static bool has_msr_tsc_adjust;
  78 static bool has_msr_tsc_deadline;
  79 static bool has_msr_feature_control;
  80 static bool has_msr_misc_enable;
  81 static bool has_msr_smbase;
  82 static bool has_msr_bndcfgs;
  83 static int lm_capable_kernel;
  84 static bool has_msr_hv_hypercall;
  85 static bool has_msr_hv_crash;
  86 static bool has_msr_hv_reset;
  87 static bool has_msr_hv_vpindex;
  88 static bool hv_vpindex_settable;
  89 static bool has_msr_hv_runtime;
  90 static bool has_msr_hv_synic;
  91 static bool has_msr_hv_stimer;
  92 static bool has_msr_hv_frequencies;
  93 static bool has_msr_hv_reenlightenment;
  94 static bool has_msr_xss;
  95 static bool has_msr_spec_ctrl;
  96 static bool has_msr_virt_ssbd;
  97 static bool has_msr_smi_count;
  98 static bool has_msr_arch_capabs;
  99
 100 static uint32_t has_architectural_pmu_version;
 101 static uint32_t num_architectural_pmu_gp_counters;
 102 static uint32_t num_architectural_pmu_fixed_counters;
 103
 104 static int has_xsave;
 105 static int has_xcrs;
 106 static int has_pit_state2;
 107
 108 static bool has_msr_mcg_ext_ctl;
 109
 110 static struct kvm_cpuid2 *cpuid_cache;
 111 static struct kvm_msr_list *kvm_feature_msrs;
 112
 113 int kvm_has_pit_state2(void)
 114 {
 115     return has_pit_state2;
 116 }
 117
 118 bool kvm_has_smm(void)
 119 {
 120     return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
 121 }
 122
 123 bool kvm_has_adjust_clock_stable(void)
 124 {
 125     int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
 126
 127     return (ret == KVM_CLOCK_TSC_STABLE);
 128 }
 129
 130 bool kvm_allows_irq0_override(void)
 131 {
 132     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
 133 }
 134
 135 static bool kvm_x2apic_api_set_flags(uint64_t flags)
 136 {
 137     KVMState *s = KVM_STATE(current_machine->accelerator);
 138
 139     return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
 140 }
 141
 142 #define MEMORIZE(fn, _result) \
 143     ({ \
 144         static bool _memorized; \
 145         \
 146         if (_memorized) { \
 147             return _result; \
 148         } \
 149         _memorized = true; \
 150         _result = fn; \
 151     })
 152
 153 static bool has_x2apic_api;
 154
 155 bool kvm_has_x2apic_api(void)
 156 {
 157     return has_x2apic_api;
 158 }
 159
 160 bool kvm_enable_x2apic(void)
 161 {
 162     return MEMORIZE(
 163              kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
 164                                       KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
 165              has_x2apic_api);
 166 }
 167
 168 bool kvm_hv_vpindex_settable(void)
 169 {
 170     return hv_vpindex_settable;
 171 }
 172
 173 static int kvm_get_tsc(CPUState *cs)
 174 {
 175     X86CPU *cpu = X86_CPU(cs);
 176     CPUX86State *env = &cpu->env;
 177     struct {
 178         struct kvm_msrs info;
 179         struct kvm_msr_entry entries[1];
 180     } msr_data;
 181     int ret;
 182
 183     if (env->tsc_valid) {
 184         return 0;
 185     }
 186
 187     msr_data.info.nmsrs = 1;
 188     msr_data.entries[0].index = MSR_IA32_TSC;
 189     env->tsc_valid = !runstate_is_running();
 190
 191     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
 192     if (ret < 0) {
 193         return ret;
 194     }
 195
 196     assert(ret == 1);
 197     env->tsc = msr_data.entries[0].data;
 198     return 0;
 199 }
 200
 201 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
 202 {
 203     kvm_get_tsc(cpu);
 204 }
 205
 206 void kvm_synchronize_all_tsc(void)
 207 {
 208     CPUState *cpu;
 209
 210     if (kvm_enabled()) {
 211         CPU_FOREACH(cpu) {
 212             run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
 213         }
 214     }
 215 }
 216
 217 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
 218 {
 219     struct kvm_cpuid2 *cpuid;
 220     int r, size;
 221
 222     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
 223     cpuid = g_malloc0(size);
 224     cpuid->nent = max;
 225     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
 226     if (r == 0 && cpuid->nent >= max) {
 227         r = -E2BIG;
 228     }
 229     if (r < 0) {
 230         if (r == -E2BIG) {
 231             g_free(cpuid);
 232             return NULL;
 233         } else {
 234             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
 235                     strerror(-r));
 236             exit(1);
 237         }
 238     }
 239     return cpuid;
 240 }
 241
 242 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 243  * for all entries.
 244  */
 245 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 246 {
 247     struct kvm_cpuid2 *cpuid;
 248     int max = 1;
 249
 250     if (cpuid_cache != NULL) {
 251         return cpuid_cache;
 252     }
 253     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 254         max *= 2;
 255     }
 256     cpuid_cache = cpuid;
 257     return cpuid;
 258 }
 259
 260 static const struct kvm_para_features {
 261     int cap;
 262     int feature;
 263 } para_features[] = {
 264     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 265     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 266     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 267     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 268 };
 269
 270 static int get_para_features(KVMState *s)
 271 {
 272     int i, features = 0;
 273
 274     for (i = 0; i < ARRAY_SIZE(para_features); i++) {
 275         if (kvm_check_extension(s, para_features[i].cap)) {
 276             features |= (1 << para_features[i].feature);
 277         }
 278     }
 279
 280     return features;
 281 }
 282
 283 static bool host_tsx_blacklisted(void)
 284 {
 285     int family, model, stepping;\
 286     char vendor[CPUID_VENDOR_SZ + 1];
 287
 288     host_vendor_fms(vendor, &family, &model, &stepping);
 289
 290     /* Check if we are running on a Haswell host known to have broken TSX */
 291     return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
 292            (family == 6) &&
 293            ((model == 63 && stepping < 4) ||
 294             model == 60 || model == 69 || model == 70);
 295 }
 296
 297 /* Returns the value for a specific register on the cpuid entry
 298  */
 299 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 300 {
 301     uint32_t ret = 0;
 302     switch (reg) {
 303     case R_EAX:
 304         ret = entry->eax;
 305         break;
 306     case R_EBX:
 307         ret = entry->ebx;
 308         break;
 309     case R_ECX:
 310         ret = entry->ecx;
 311         break;
 312     case R_EDX:
 313         ret = entry->edx;
 314         break;
 315     }
 316     return ret;
 317 }
 318
 319 /* Find matching entry for function/index on kvm_cpuid2 struct
 320  */
 321 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 322                                                  uint32_t function,
 323                                                  uint32_t index)
 324 {
 325     int i;
 326     for (i = 0; i < cpuid->nent; ++i) {
 327         if (cpuid->entries[i].function == function &&
 328             cpuid->entries[i].index == index) {
 329             return &cpuid->entries[i];
 330         }
 331     }
 332     /* not found: */
 333     return NULL;
 334 }
 335
 336 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 337                                       uint32_t index, int reg)
 338 {
 339     struct kvm_cpuid2 *cpuid;
 340     uint32_t ret = 0;
 341     uint32_t cpuid_1_edx;
 342     bool found = false;
 343
 344     cpuid = get_supported_cpuid(s);
 345
 346     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 347     if (entry) {
 348         found = true;
 349         ret = cpuid_entry_get_reg(entry, reg);
 350     }
 351
 352     /* Fixups for the data returned by KVM, below */
 353
 354     if (function == 1 && reg == R_EDX) {
 355         /* KVM before 2.6.30 misreports the following features */
 356         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 357     } else if (function == 1 && reg == R_ECX) {
 358         /* We can set the hypervisor flag, even if KVM does not return it on
 359          * GET_SUPPORTED_CPUID
 360          */
 361         ret |= CPUID_EXT_HYPERVISOR;
 362         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 363          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 364          * and the irqchip is in the kernel.
 365          */
 366         if (kvm_irqchip_in_kernel() &&
 367                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 368             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 369         }
 370
 371         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 372          * without the in-kernel irqchip
 373          */
 374         if (!kvm_irqchip_in_kernel()) {
 375             ret &= ~CPUID_EXT_X2APIC;
 376         }
 377
 378         if (enable_cpu_pm) {
 379             int disable_exits = kvm_check_extension(s,
 380                                                     KVM_CAP_X86_DISABLE_EXITS);
 381
 382             if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
 383                 ret |= CPUID_EXT_MONITOR;
 384             }
 385         }
 386     } else if (function == 6 && reg == R_EAX) {
 387         ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
 388     } else if (function == 7 && index == 0 && reg == R_EBX) {
 389         if (host_tsx_blacklisted()) {
 390             ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
 391         }
 392     } else if (function == 0x80000001 && reg == R_ECX) {
 393         /*
 394          * It's safe to enable TOPOEXT even if it's not returned by
 395          * GET_SUPPORTED_CPUID.  Unconditionally enabling TOPOEXT here allows
 396          * us to keep CPU models including TOPOEXT runnable on older kernels.
 397          */
 398         ret |= CPUID_EXT3_TOPOEXT;
 399     } else if (function == 0x80000001 && reg == R_EDX) {
 400         /* On Intel, kvm returns cpuid according to the Intel spec,
 401          * so add missing bits according to the AMD spec:
 402          */
 403         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 404         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 405     } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
 406         /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
 407          * be enabled without the in-kernel irqchip
 408          */
 409         if (!kvm_irqchip_in_kernel()) {
 410             ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
 411         }
 412     } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
 413         ret |= 1U << KVM_HINTS_REALTIME;
 414         found = 1;
 415     }
 416
 417     /* fallback for older kernels */
 418     if ((function == KVM_CPUID_FEATURES) && !found) {
 419         ret = get_para_features(s);
 420     }
 421
 422     return ret;
 423 }
 424
 425 uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
 426 {
 427     struct {
 428         struct kvm_msrs info;
 429         struct kvm_msr_entry entries[1];
 430     } msr_data;
 431     uint32_t ret;
 432
 433     if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
 434         return 0;
 435     }
 436
 437     /* Check if requested MSR is supported feature MSR */
 438     int i;
 439     for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
 440         if (kvm_feature_msrs->indices[i] == index) {
 441             break;
 442         }
 443     if (i == kvm_feature_msrs->nmsrs) {
 444         return 0; /* if the feature MSR is not supported, simply return 0 */
 445     }
 446
 447     msr_data.info.nmsrs = 1;
 448     msr_data.entries[0].index = index;
 449
 450     ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
 451     if (ret != 1) {
 452         error_report("KVM get MSR (index=0x%x) feature failed, %s",
 453             index, strerror(-ret));
 454         exit(1);
 455     }
 456
 457     return msr_data.entries[0].data;
 458 }
 459
 460
 461 typedef struct HWPoisonPage {
 462     ram_addr_t ram_addr;
 463     QLIST_ENTRY(HWPoisonPage) list;
 464 } HWPoisonPage;
 465
 466 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 467     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 468
 469 static void kvm_unpoison_all(void *param)
 470 {
 471     HWPoisonPage *page, *next_page;
 472
 473     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 474         QLIST_REMOVE(page, list);
 475         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 476         g_free(page);
 477     }
 478 }
 479
 480 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 481 {
 482     HWPoisonPage *page;
 483
 484     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 485         if (page->ram_addr == ram_addr) {
 486             return;
 487         }
 488     }
 489     page = g_new(HWPoisonPage, 1);
 490     page->ram_addr = ram_addr;
 491     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 492 }
 493
 494 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 495                                      int *max_banks)
 496 {
 497     int r;
 498
 499     r = kvm_check_extension(s, KVM_CAP_MCE);
 500     if (r > 0) {
 501         *max_banks = r;
 502         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 503     }
 504     return -ENOSYS;
 505 }
 506
 507 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
 508 {
 509     CPUState *cs = CPU(cpu);
 510     CPUX86State *env = &cpu->env;
 511     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 512                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 513     uint64_t mcg_status = MCG_STATUS_MCIP;
 514     int flags = 0;
 515
 516     if (code == BUS_MCEERR_AR) {
 517         status |= MCI_STATUS_AR | 0x134;
 518         mcg_status |= MCG_STATUS_EIPV;
 519     } else {
 520         status |= 0xc0;
 521         mcg_status |= MCG_STATUS_RIPV;
 522     }
 523
 524     flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
 525     /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
 526      * guest kernel back into env->mcg_ext_ctl.
 527      */
 528     cpu_synchronize_state(cs);
 529     if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
 530         mcg_status |= MCG_STATUS_LMCE;
 531         flags = 0;
 532     }
 533
 534     cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
 535                        (MCM_ADDR_PHYS << 6) | 0xc, flags);
 536 }
 537
 538 static void hardware_memory_error(void)
 539 {
 540     fprintf(stderr, "Hardware memory error!\n");
 541     exit(1);
 542 }
 543
 544 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
 545 {
 546     X86CPU *cpu = X86_CPU(c);
 547     CPUX86State *env = &cpu->env;
 548     ram_addr_t ram_addr;
 549     hwaddr paddr;
 550
 551     /* If we get an action required MCE, it has been injected by KVM
 552      * while the VM was running.  An action optional MCE instead should
 553      * be coming from the main thread, which qemu_init_sigbus identifies
 554      * as the "early kill" thread.
 555      */
 556     assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
 557
 558     if ((env->mcg_cap & MCG_SER_P) && addr) {
 559         ram_addr = qemu_ram_addr_from_host(addr);
 560         if (ram_addr != RAM_ADDR_INVALID &&
 561             kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
 562             kvm_hwpoison_page_add(ram_addr);
 563             kvm_mce_inject(cpu, paddr, code);
 564             return;
 565         }
 566
 567         fprintf(stderr, "Hardware memory error for memory used by "
 568                 "QEMU itself instead of guest system!\n");
 569     }
 570
 571     if (code == BUS_MCEERR_AR) {
 572         hardware_memory_error();
 573     }
 574
 575     /* Hope we are lucky for AO MCE */
 576 }
 577
 578 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
 579 {
 580     CPUX86State *env = &cpu->env;
 581
 582     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 583         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 584         struct kvm_x86_mce mce;
 585
 586         env->exception_injected = -1;
 587
 588         /*
 589          * There must be at least one bank in use if an MCE is pending.
 590          * Find it and use its values for the event injection.
 591          */
 592         for (bank = 0; bank < bank_num; bank++) {
 593             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 594                 break;
 595             }
 596         }
 597         assert(bank < bank_num);
 598
 599         mce.bank = bank;
 600         mce.status = env->mce_banks[bank * 4 + 1];
 601         mce.mcg_status = env->mcg_status;
 602         mce.addr = env->mce_banks[bank * 4 + 2];
 603         mce.misc = env->mce_banks[bank * 4 + 3];
 604
 605         return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
 606     }
 607     return 0;
 608 }
 609
 610 static void cpu_update_state(void *opaque, int running, RunState state)
 611 {
 612     CPUX86State *env = opaque;
 613
 614     if (running) {
 615         env->tsc_valid = false;
 616     }
 617 }
 618
 619 unsigned long kvm_arch_vcpu_id(CPUState *cs)
 620 {
 621     X86CPU *cpu = X86_CPU(cs);
 622     return cpu->apic_id;
 623 }
 624
 625 #ifndef KVM_CPUID_SIGNATURE_NEXT
 626 #define KVM_CPUID_SIGNATURE_NEXT                0x40000100
 627 #endif
 628
 629 static bool hyperv_hypercall_available(X86CPU *cpu)
 630 {
 631     return cpu->hyperv_vapic ||
 632            (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
 633 }
 634
 635 static bool hyperv_enabled(X86CPU *cpu)
 636 {
 637     CPUState *cs = CPU(cpu);
 638     return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
 639            (hyperv_hypercall_available(cpu) ||
 640             cpu->hyperv_time  ||
 641             cpu->hyperv_relaxed_timing ||
 642             cpu->hyperv_crash ||
 643             cpu->hyperv_reset ||
 644             cpu->hyperv_vpindex ||
 645             cpu->hyperv_runtime ||
 646             cpu->hyperv_synic ||
 647             cpu->hyperv_stimer ||
 648             cpu->hyperv_reenlightenment ||
 649             cpu->hyperv_tlbflush ||
 650             cpu->hyperv_ipi);
 651 }
 652
 653 static int kvm_arch_set_tsc_khz(CPUState *cs)
 654 {
 655     X86CPU *cpu = X86_CPU(cs);
 656     CPUX86State *env = &cpu->env;
 657     int r;
 658
 659     if (!env->tsc_khz) {
 660         return 0;
 661     }
 662
 663     r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
 664         kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
 665         -ENOTSUP;
 666     if (r < 0) {
 667         /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
 668          * TSC frequency doesn't match the one we want.
 669          */
 670         int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
 671                        kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
 672                        -ENOTSUP;
 673         if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
 674             warn_report("TSC frequency mismatch between "
 675                         "VM (%" PRId64 " kHz) and host (%d kHz), "
 676                         "and TSC scaling unavailable",
 677                         env->tsc_khz, cur_freq);
 678             return r;
 679         }
 680     }
 681
 682     return 0;
 683 }
 684
 685 static bool tsc_is_stable_and_known(CPUX86State *env)
 686 {
 687     if (!env->tsc_khz) {
 688         return false;
 689     }
 690     return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
 691         || env->user_tsc_khz;
 692 }
 693
 694 static int hyperv_handle_properties(CPUState *cs)
 695 {
 696     X86CPU *cpu = X86_CPU(cs);
 697     CPUX86State *env = &cpu->env;
 698
 699     if (cpu->hyperv_relaxed_timing) {
 700         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 701     }
 702     if (cpu->hyperv_vapic) {
 703         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 704         env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
 705     }
 706     if (cpu->hyperv_time) {
 707         if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
 708             fprintf(stderr, "Hyper-V clocksources "
 709                     "(requested by 'hv-time' cpu flag) "
 710                     "are not supported by kernel\n");
 711             return -ENOSYS;
 712         }
 713         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 714         env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
 715         env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
 716     }
 717     if (cpu->hyperv_frequencies) {
 718         if (!has_msr_hv_frequencies) {
 719             fprintf(stderr, "Hyper-V frequency MSRs "
 720                     "(requested by 'hv-frequencies' cpu flag) "
 721                     "are not supported by kernel\n");
 722             return -ENOSYS;
 723         }
 724         env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
 725         env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
 726     }
 727     if (cpu->hyperv_crash) {
 728         if (!has_msr_hv_crash) {
 729             fprintf(stderr, "Hyper-V crash MSRs "
 730                     "(requested by 'hv-crash' cpu flag) "
 731                     "are not supported by kernel\n");
 732             return -ENOSYS;
 733         }
 734         env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
 735     }
 736     if (cpu->hyperv_reenlightenment) {
 737         if (!has_msr_hv_reenlightenment) {
 738             fprintf(stderr,
 739                     "Hyper-V Reenlightenment MSRs "
 740                     "(requested by 'hv-reenlightenment' cpu flag) "
 741                     "are not supported by kernel\n");
 742             return -ENOSYS;
 743         }
 744         env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
 745     }
 746     env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
 747     if (cpu->hyperv_reset) {
 748         if (!has_msr_hv_reset) {
 749             fprintf(stderr, "Hyper-V reset MSR "
 750                     "(requested by 'hv-reset' cpu flag) "
 751                     "is not supported by kernel\n");
 752             return -ENOSYS;
 753         }
 754         env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
 755     }
 756     if (cpu->hyperv_vpindex) {
 757         if (!has_msr_hv_vpindex) {
 758             fprintf(stderr, "Hyper-V VP_INDEX MSR "
 759                     "(requested by 'hv-vpindex' cpu flag) "
 760                     "is not supported by kernel\n");
 761             return -ENOSYS;
 762         }
 763         env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
 764     }
 765     if (cpu->hyperv_runtime) {
 766         if (!has_msr_hv_runtime) {
 767             fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
 768                     "(requested by 'hv-runtime' cpu flag) "
 769                     "is not supported by kernel\n");
 770             return -ENOSYS;
 771         }
 772         env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
 773     }
 774     if (cpu->hyperv_synic) {
 775         unsigned int cap = KVM_CAP_HYPERV_SYNIC;
 776         if (!cpu->hyperv_synic_kvm_only) {
 777             if (!cpu->hyperv_vpindex) {
 778                 fprintf(stderr, "Hyper-V SynIC "
 779                         "(requested by 'hv-synic' cpu flag) "
 780                         "requires Hyper-V VP_INDEX ('hv-vpindex')\n");
 781             return -ENOSYS;
 782             }
 783             cap = KVM_CAP_HYPERV_SYNIC2;
 784         }
 785
 786         if (!has_msr_hv_synic || !kvm_check_extension(cs->kvm_state, cap)) {
 787             fprintf(stderr, "Hyper-V SynIC (requested by 'hv-synic' cpu flag) "
 788                     "is not supported by kernel\n");
 789             return -ENOSYS;
 790         }
 791
 792         env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
 793     }
 794     if (cpu->hyperv_stimer) {
 795         if (!has_msr_hv_stimer) {
 796             fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
 797             return -ENOSYS;
 798         }
 799         env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
 800     }
 801     return 0;
 802 }
 803
 804 static int hyperv_init_vcpu(X86CPU *cpu)
 805 {
 806     CPUState *cs = CPU(cpu);
 807     int ret;
 808
 809     if (cpu->hyperv_vpindex && !hv_vpindex_settable) {
 810         /*
 811          * the kernel doesn't support setting vp_index; assert that its value
 812          * is in sync
 813          */
 814         struct {
 815             struct kvm_msrs info;
 816             struct kvm_msr_entry entries[1];
 817         } msr_data = {
 818             .info.nmsrs = 1,
 819             .entries[0].index = HV_X64_MSR_VP_INDEX,
 820         };
 821
 822         ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
 823         if (ret < 0) {
 824             return ret;
 825         }
 826         assert(ret == 1);
 827
 828         if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
 829             error_report("kernel's vp_index != QEMU's vp_index");
 830             return -ENXIO;
 831         }
 832     }
 833
 834     if (cpu->hyperv_synic) {
 835         uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
 836             KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
 837         ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
 838         if (ret < 0) {
 839             error_report("failed to turn on HyperV SynIC in KVM: %s",
 840                          strerror(-ret));
 841             return ret;
 842         }
 843
 844         if (!cpu->hyperv_synic_kvm_only) {
 845             ret = hyperv_x86_synic_add(cpu);
 846             if (ret < 0) {
 847                 error_report("failed to create HyperV SynIC: %s",
 848                              strerror(-ret));
 849                 return ret;
 850             }
 851         }
 852     }
 853
 854     return 0;
 855 }
 856
 857 static Error *invtsc_mig_blocker;
 858 static Error *vmx_mig_blocker;
 859
 860 #define KVM_MAX_CPUID_ENTRIES  100
 861
 862 int kvm_arch_init_vcpu(CPUState *cs)
 863 {
 864     struct {
 865         struct kvm_cpuid2 cpuid;
 866         struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
 867     } cpuid_data;
 868     /*
 869      * The kernel defines these structs with padding fields so there
 870      * should be no extra padding in our cpuid_data struct.
 871      */
 872     QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
 873                       sizeof(struct kvm_cpuid2) +
 874                       sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
 875
 876     X86CPU *cpu = X86_CPU(cs);
 877     CPUX86State *env = &cpu->env;
 878     uint32_t limit, i, j, cpuid_i;
 879     uint32_t unused;
 880     struct kvm_cpuid_entry2 *c;
 881     uint32_t signature[3];
 882     uint16_t evmcs_version;
 883     int kvm_base = KVM_CPUID_SIGNATURE;
 884     int r;
 885     Error *local_err = NULL;
 886
 887     memset(&cpuid_data, 0, sizeof(cpuid_data));
 888
 889     cpuid_i = 0;
 890
 891     r = kvm_arch_set_tsc_khz(cs);
 892     if (r < 0) {
 893         goto fail;
 894     }
 895
 896     /* vcpu's TSC frequency is either specified by user, or following
 897      * the value used by KVM if the former is not present. In the
 898      * latter case, we query it from KVM and record in env->tsc_khz,
 899      * so that vcpu's TSC frequency can be migrated later via this field.
 900      */
 901     if (!env->tsc_khz) {
 902         r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
 903             kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
 904             -ENOTSUP;
 905         if (r > 0) {
 906             env->tsc_khz = r;
 907         }
 908     }
 909
 910     /* Paravirtualization CPUIDs */
 911     if (hyperv_enabled(cpu)) {
 912         c = &cpuid_data.entries[cpuid_i++];
 913         c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
 914         if (!cpu->hyperv_vendor_id) {
 915             memcpy(signature, "Microsoft Hv", 12);
 916         } else {
 917             size_t len = strlen(cpu->hyperv_vendor_id);
 918
 919             if (len > 12) {
 920                 error_report("hv-vendor-id truncated to 12 characters");
 921                 len = 12;
 922             }
 923             memset(signature, 0, 12);
 924             memcpy(signature, cpu->hyperv_vendor_id, len);
 925         }
 926         c->eax = cpu->hyperv_evmcs ?
 927             HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
 928         c->ebx = signature[0];
 929         c->ecx = signature[1];
 930         c->edx = signature[2];
 931
 932         c = &cpuid_data.entries[cpuid_i++];
 933         c->function = HV_CPUID_INTERFACE;
 934         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 935         c->eax = signature[0];
 936         c->ebx = 0;
 937         c->ecx = 0;
 938         c->edx = 0;
 939
 940         c = &cpuid_data.entries[cpuid_i++];
 941         c->function = HV_CPUID_VERSION;
 942         c->eax = 0x00001bbc;
 943         c->ebx = 0x00060001;
 944
 945         c = &cpuid_data.entries[cpuid_i++];
 946         c->function = HV_CPUID_FEATURES;
 947         r = hyperv_handle_properties(cs);
 948         if (r) {
 949             return r;
 950         }
 951         c->eax = env->features[FEAT_HYPERV_EAX];
 952         c->ebx = env->features[FEAT_HYPERV_EBX];
 953         c->edx = env->features[FEAT_HYPERV_EDX];
 954
 955         c = &cpuid_data.entries[cpuid_i++];
 956         c->function = HV_CPUID_ENLIGHTMENT_INFO;
 957         if (cpu->hyperv_relaxed_timing) {
 958             c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
 959         }
 960         if (cpu->hyperv_vapic) {
 961             c->eax |= HV_APIC_ACCESS_RECOMMENDED;
 962         }
 963         if (cpu->hyperv_tlbflush) {
 964             if (kvm_check_extension(cs->kvm_state,
 965                                     KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
 966                 fprintf(stderr, "Hyper-V TLB flush support "
 967                         "(requested by 'hv-tlbflush' cpu flag) "
 968                         " is not supported by kernel\n");
 969                 return -ENOSYS;
 970             }
 971             c->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
 972             c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
 973         }
 974         if (cpu->hyperv_ipi) {
 975             if (kvm_check_extension(cs->kvm_state,
 976                                     KVM_CAP_HYPERV_SEND_IPI) <= 0) {
 977                 fprintf(stderr, "Hyper-V IPI send support "
 978                         "(requested by 'hv-ipi' cpu flag) "
 979                         " is not supported by kernel\n");
 980                 return -ENOSYS;
 981             }
 982             c->eax |= HV_CLUSTER_IPI_RECOMMENDED;
 983             c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
 984         }
 985         if (cpu->hyperv_evmcs) {
 986             if (kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
 987                                     (uintptr_t)&evmcs_version)) {
 988                 fprintf(stderr, "Hyper-V Enlightened VMCS "
 989                         "(requested by 'hv-evmcs' cpu flag) "
 990                         "is not supported by kernel\n");
 991                 return -ENOSYS;
 992             }
 993             c->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
 994         }
 995         c->ebx = cpu->hyperv_spinlock_attempts;
 996
 997         c = &cpuid_data.entries[cpuid_i++];
 998         c->function = HV_CPUID_IMPLEMENT_LIMITS;
 999
1000         c->eax = cpu->hv_max_vps;
1001         c->ebx = 0x40;
1002
1003         kvm_base = KVM_CPUID_SIGNATURE_NEXT;
1004         has_msr_hv_hypercall = true;
1005
1006         if (cpu->hyperv_evmcs) {
1007             __u32 function;
1008
1009             /* Create zeroed 0x40000006..0x40000009 leaves */
1010             for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1011                  function < HV_CPUID_NESTED_FEATURES; function++) {
1012                 c = &cpuid_data.entries[cpuid_i++];
1013                 c->function = function;
1014             }
1015
1016             c = &cpuid_data.entries[cpuid_i++];
1017             c->function = HV_CPUID_NESTED_FEATURES;
1018             c->eax = evmcs_version;
1019         }
1020     }
1021
1022     if (cpu->expose_kvm) {
1023         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1024         c = &cpuid_data.entries[cpuid_i++];
1025         c->function = KVM_CPUID_SIGNATURE | kvm_base;
1026         c->eax = KVM_CPUID_FEATURES | kvm_base;
1027         c->ebx = signature[0];
1028         c->ecx = signature[1];
1029         c->edx = signature[2];
1030
1031         c = &cpuid_data.entries[cpuid_i++];
1032         c->function = KVM_CPUID_FEATURES | kvm_base;
1033         c->eax = env->features[FEAT_KVM];
1034         c->edx = env->features[FEAT_KVM_HINTS];
1035     }
1036
1037     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1038
1039     for (i = 0; i <= limit; i++) {
1040         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1041             fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1042             abort();
1043         }
1044         c = &cpuid_data.entries[cpuid_i++];
1045
1046         switch (i) {
1047         case 2: {
1048             /* Keep reading function 2 till all the input is received */
1049             int times;
1050
1051             c->function = i;
1052             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1053                        KVM_CPUID_FLAG_STATE_READ_NEXT;
1054             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1055             times = c->eax & 0xff;
1056
1057             for (j = 1; j < times; ++j) {
1058                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1059                     fprintf(stderr, "cpuid_data is full, no space for "
1060                             "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1061                     abort();
1062                 }
1063                 c = &cpuid_data.entries[cpuid_i++];
1064                 c->function = i;
1065                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1066                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1067             }
1068             break;
1069         }
1070         case 4:
1071         case 0xb:
1072         case 0xd:
1073             for (j = 0; ; j++) {
1074                 if (i == 0xd && j == 64) {
1075                     break;
1076                 }
1077                 c->function = i;
1078                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1079                 c->index = j;
1080                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1081
1082                 if (i == 4 && c->eax == 0) {
1083                     break;
1084                 }
1085                 if (i == 0xb && !(c->ecx & 0xff00)) {
1086                     break;
1087                 }
1088                 if (i == 0xd && c->eax == 0) {
1089                     continue;
1090                 }
1091                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1092                     fprintf(stderr, "cpuid_data is full, no space for "
1093                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1094                     abort();
1095                 }
1096                 c = &cpuid_data.entries[cpuid_i++];
1097             }
1098             break;
1099         case 0x14: {
1100             uint32_t times;
1101
1102             c->function = i;
1103             c->index = 0;
1104             c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1105             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1106             times = c->eax;
1107
1108             for (j = 1; j <= times; ++j) {
1109                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1110                     fprintf(stderr, "cpuid_data is full, no space for "
1111                                 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1112                     abort();
1113                 }
1114                 c = &cpuid_data.entries[cpuid_i++];
1115                 c->function = i;
1116                 c->index = j;
1117                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1118                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1119             }
1120             break;
1121         }
1122         default:
1123             c->function = i;
1124             c->flags = 0;
1125             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1126             break;
1127         }
1128     }
1129
1130     if (limit >= 0x0a) {
1131         uint32_t eax, edx;
1132
1133         cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1134
1135         has_architectural_pmu_version = eax & 0xff;
1136         if (has_architectural_pmu_version > 0) {
1137             num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1138
1139             /* Shouldn't be more than 32, since that's the number of bits
1140              * available in EBX to tell us _which_ counters are available.
1141              * Play it safe.
1142              */
1143             if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1144                 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1145             }
1146
1147             if (has_architectural_pmu_version > 1) {
1148                 num_architectural_pmu_fixed_counters = edx & 0x1f;
1149
1150                 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1151                     num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1152                 }
1153             }
1154         }
1155     }
1156
1157     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1158
1159     for (i = 0x80000000; i <= limit; i++) {
1160         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1161             fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1162             abort();
1163         }
1164         c = &cpuid_data.entries[cpuid_i++];
1165
1166         switch (i) {
1167         case 0x8000001d:
1168             /* Query for all AMD cache information leaves */
1169             for (j = 0; ; j++) {
1170                 c->function = i;
1171                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1172                 c->index = j;
1173                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1174
1175                 if (c->eax == 0) {
1176                     break;
1177                 }
1178                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1179                     fprintf(stderr, "cpuid_data is full, no space for "
1180                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1181                     abort();
1182                 }
1183                 c = &cpuid_data.entries[cpuid_i++];
1184             }
1185             break;
1186         default:
1187             c->function = i;
1188             c->flags = 0;
1189             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1190             break;
1191         }
1192     }
1193
1194     /* Call Centaur's CPUID instructions they are supported. */
1195     if (env->cpuid_xlevel2 > 0) {
1196         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1197
1198         for (i = 0xC0000000; i <= limit; i++) {
1199             if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1200                 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1201                 abort();
1202             }
1203             c = &cpuid_data.entries[cpuid_i++];
1204
1205             c->function = i;
1206             c->flags = 0;
1207             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1208         }
1209     }
1210
1211     cpuid_data.cpuid.nent = cpuid_i;
1212
1213     if (((env->cpuid_version >> 8)&0xF) >= 6
1214         && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1215            (CPUID_MCE | CPUID_MCA)
1216         && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1217         uint64_t mcg_cap, unsupported_caps;
1218         int banks;
1219         int ret;
1220
1221         ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1222         if (ret < 0) {
1223             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1224             return ret;
1225         }
1226
1227         if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1228             error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1229                          (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1230             return -ENOTSUP;
1231         }
1232
1233         unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1234         if (unsupported_caps) {
1235             if (unsupported_caps & MCG_LMCE_P) {
1236                 error_report("kvm: LMCE not supported");
1237                 return -ENOTSUP;
1238             }
1239             warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1240                         unsupported_caps);
1241         }
1242
1243         env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1244         ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1245         if (ret < 0) {
1246             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1247             return ret;
1248         }
1249     }
1250
1251     qemu_add_vm_change_state_handler(cpu_update_state, env);
1252
1253     c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1254     if (c) {
1255         has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1256                                   !!(c->ecx & CPUID_EXT_SMX);
1257     }
1258
1259     if ((env->features[FEAT_1_ECX] & CPUID_EXT_VMX) && !vmx_mig_blocker) {
1260         error_setg(&vmx_mig_blocker,
1261                    "Nested VMX virtualization does not support live migration yet");
1262         r = migrate_add_blocker(vmx_mig_blocker, &local_err);
1263         if (local_err) {
1264             error_report_err(local_err);
1265             error_free(vmx_mig_blocker);
1266             return r;
1267         }
1268     }
1269
1270     if (env->mcg_cap & MCG_LMCE_P) {
1271         has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1272     }
1273
1274     if (!env->user_tsc_khz) {
1275         if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1276             invtsc_mig_blocker == NULL) {
1277             error_setg(&invtsc_mig_blocker,
1278                        "State blocked by non-migratable CPU device"
1279                        " (invtsc flag)");
1280             r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1281             if (local_err) {
1282                 error_report_err(local_err);
1283                 error_free(invtsc_mig_blocker);
1284                 return r;
1285             }
1286         }
1287     }
1288
1289     if (cpu->vmware_cpuid_freq
1290         /* Guests depend on 0x40000000 to detect this feature, so only expose
1291          * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1292         && cpu->expose_kvm
1293         && kvm_base == KVM_CPUID_SIGNATURE
1294         /* TSC clock must be stable and known for this feature. */
1295         && tsc_is_stable_and_known(env)) {
1296
1297         c = &cpuid_data.entries[cpuid_i++];
1298         c->function = KVM_CPUID_SIGNATURE | 0x10;
1299         c->eax = env->tsc_khz;
1300         /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1301          * APIC_BUS_CYCLE_NS */
1302         c->ebx = 1000000;
1303         c->ecx = c->edx = 0;
1304
1305         c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1306         c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1307     }
1308
1309     cpuid_data.cpuid.nent = cpuid_i;
1310
1311     cpuid_data.cpuid.padding = 0;
1312     r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1313     if (r) {
1314         goto fail;
1315     }
1316
1317     if (has_xsave) {
1318         env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1319     }
1320     cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1321
1322     if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1323         has_msr_tsc_aux = false;
1324     }
1325
1326     r = hyperv_init_vcpu(cpu);
1327     if (r) {
1328         goto fail;
1329     }
1330
1331     return 0;
1332
1333  fail:
1334     migrate_del_blocker(invtsc_mig_blocker);
1335     return r;
1336 }
1337
1338 void kvm_arch_reset_vcpu(X86CPU *cpu)
1339 {
1340     CPUX86State *env = &cpu->env;
1341
1342     env->xcr0 = 1;
1343     if (kvm_irqchip_in_kernel()) {
1344         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1345                                           KVM_MP_STATE_UNINITIALIZED;
1346     } else {
1347         env->mp_state = KVM_MP_STATE_RUNNABLE;
1348     }
1349
1350     if (cpu->hyperv_synic) {
1351         int i;
1352         for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1353             env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1354         }
1355
1356         hyperv_x86_synic_reset(cpu);
1357     }
1358 }
1359
1360 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1361 {
1362     CPUX86State *env = &cpu->env;
1363
1364     /* APs get directly into wait-for-SIPI state.  */
1365     if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1366         env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1367     }
1368 }
1369
1370 static int kvm_get_supported_feature_msrs(KVMState *s)
1371 {
1372     int ret = 0;
1373
1374     if (kvm_feature_msrs != NULL) {
1375         return 0;
1376     }
1377
1378     if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1379         return 0;
1380     }
1381
1382     struct kvm_msr_list msr_list;
1383
1384     msr_list.nmsrs = 0;
1385     ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1386     if (ret < 0 && ret != -E2BIG) {
1387         error_report("Fetch KVM feature MSR list failed: %s",
1388             strerror(-ret));
1389         return ret;
1390     }
1391
1392     assert(msr_list.nmsrs > 0);
1393     kvm_feature_msrs = (struct kvm_msr_list *) \
1394         g_malloc0(sizeof(msr_list) +
1395                  msr_list.nmsrs * sizeof(msr_list.indices[0]));
1396
1397     kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1398     ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1399
1400     if (ret < 0) {
1401         error_report("Fetch KVM feature MSR list failed: %s",
1402             strerror(-ret));
1403         g_free(kvm_feature_msrs);
1404         kvm_feature_msrs = NULL;
1405         return ret;
1406     }
1407
1408     return 0;
1409 }
1410
1411 static int kvm_get_supported_msrs(KVMState *s)
1412 {
1413     static int kvm_supported_msrs;
1414     int ret = 0;
1415
1416     /* first time */
1417     if (kvm_supported_msrs == 0) {
1418         struct kvm_msr_list msr_list, *kvm_msr_list;
1419
1420         kvm_supported_msrs = -1;
1421
1422         /* Obtain MSR list from KVM.  These are the MSRs that we must
1423          * save/restore */
1424         msr_list.nmsrs = 0;
1425         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1426         if (ret < 0 && ret != -E2BIG) {
1427             return ret;
1428         }
1429         /* Old kernel modules had a bug and could write beyond the provided
1430            memory. Allocate at least a safe amount of 1K. */
1431         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1432                                               msr_list.nmsrs *
1433                                               sizeof(msr_list.indices[0])));
1434
1435         kvm_msr_list->nmsrs = msr_list.nmsrs;
1436         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1437         if (ret >= 0) {
1438             int i;
1439
1440             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1441                 switch (kvm_msr_list->indices[i]) {
1442                 case MSR_STAR:
1443                     has_msr_star = true;
1444                     break;
1445                 case MSR_VM_HSAVE_PA:
1446                     has_msr_hsave_pa = true;
1447                     break;
1448                 case MSR_TSC_AUX:
1449                     has_msr_tsc_aux = true;
1450                     break;
1451                 case MSR_TSC_ADJUST:
1452                     has_msr_tsc_adjust = true;
1453                     break;
1454                 case MSR_IA32_TSCDEADLINE:
1455                     has_msr_tsc_deadline = true;
1456                     break;
1457                 case MSR_IA32_SMBASE:
1458                     has_msr_smbase = true;
1459                     break;
1460                 case MSR_SMI_COUNT:
1461                     has_msr_smi_count = true;
1462                     break;
1463                 case MSR_IA32_MISC_ENABLE:
1464                     has_msr_misc_enable = true;
1465                     break;
1466                 case MSR_IA32_BNDCFGS:
1467                     has_msr_bndcfgs = true;
1468                     break;
1469                 case MSR_IA32_XSS:
1470                     has_msr_xss = true;
1471                     break;
1472                 case HV_X64_MSR_CRASH_CTL:
1473                     has_msr_hv_crash = true;
1474                     break;
1475                 case HV_X64_MSR_RESET:
1476                     has_msr_hv_reset = true;
1477                     break;
1478                 case HV_X64_MSR_VP_INDEX:
1479                     has_msr_hv_vpindex = true;
1480                     break;
1481                 case HV_X64_MSR_VP_RUNTIME:
1482                     has_msr_hv_runtime = true;
1483                     break;
1484                 case HV_X64_MSR_SCONTROL:
1485                     has_msr_hv_synic = true;
1486                     break;
1487                 case HV_X64_MSR_STIMER0_CONFIG:
1488                     has_msr_hv_stimer = true;
1489                     break;
1490                 case HV_X64_MSR_TSC_FREQUENCY:
1491                     has_msr_hv_frequencies = true;
1492                     break;
1493                 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1494                     has_msr_hv_reenlightenment = true;
1495                     break;
1496                 case MSR_IA32_SPEC_CTRL:
1497                     has_msr_spec_ctrl = true;
1498                     break;
1499                 case MSR_VIRT_SSBD:
1500                     has_msr_virt_ssbd = true;
1501                     break;
1502                 case MSR_IA32_ARCH_CAPABILITIES:
1503                     has_msr_arch_capabs = true;
1504                     break;
1505                 }
1506             }
1507         }
1508
1509         g_free(kvm_msr_list);
1510     }
1511
1512     return ret;
1513 }
1514
1515 static Notifier smram_machine_done;
1516 static KVMMemoryListener smram_listener;
1517 static AddressSpace smram_address_space;
1518 static MemoryRegion smram_as_root;
1519 static MemoryRegion smram_as_mem;
1520
1521 static void register_smram_listener(Notifier *n, void *unused)
1522 {
1523     MemoryRegion *smram =
1524         (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1525
1526     /* Outer container... */
1527     memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1528     memory_region_set_enabled(&smram_as_root, true);
1529
1530     /* ... with two regions inside: normal system memory with low
1531      * priority, and...
1532      */
1533     memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1534                              get_system_memory(), 0, ~0ull);
1535     memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1536     memory_region_set_enabled(&smram_as_mem, true);
1537
1538     if (smram) {
1539         /* ... SMRAM with higher priority */
1540         memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1541         memory_region_set_enabled(smram, true);
1542     }
1543
1544     address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1545     kvm_memory_listener_register(kvm_state, &smram_listener,
1546                                  &smram_address_space, 1);
1547 }
1548
1549 int kvm_arch_init(MachineState *ms, KVMState *s)
1550 {
1551     uint64_t identity_base = 0xfffbc000;
1552     uint64_t shadow_mem;
1553     int ret;
1554     struct utsname utsname;
1555
1556     has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1557     has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1558     has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1559
1560     hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1561
1562     ret = kvm_get_supported_msrs(s);
1563     if (ret < 0) {
1564         return ret;
1565     }
1566
1567     kvm_get_supported_feature_msrs(s);
1568
1569     uname(&utsname);
1570     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1571
1572     /*
1573      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1574      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
1575      * Since these must be part of guest physical memory, we need to allocate
1576      * them, both by setting their start addresses in the kernel and by
1577      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1578      *
1579      * Older KVM versions may not support setting the identity map base. In
1580      * that case we need to stick with the default, i.e. a 256K maximum BIOS
1581      * size.
1582      */
1583     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1584         /* Allows up to 16M BIOSes. */
1585         identity_base = 0xfeffc000;
1586
1587         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1588         if (ret < 0) {
1589             return ret;
1590         }
1591     }
1592
1593     /* Set TSS base one page after EPT identity map. */
1594     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1595     if (ret < 0) {
1596         return ret;
1597     }
1598
1599     /* Tell fw_cfg to notify the BIOS to reserve the range. */
1600     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1601     if (ret < 0) {
1602         fprintf(stderr, "e820_add_entry() table is full\n");
1603         return ret;
1604     }
1605     qemu_register_reset(kvm_unpoison_all, NULL);
1606
1607     shadow_mem = machine_kvm_shadow_mem(ms);
1608     if (shadow_mem != -1) {
1609         shadow_mem /= 4096;
1610         ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1611         if (ret < 0) {
1612             return ret;
1613         }
1614     }
1615
1616     if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1617         object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1618         pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1619         smram_machine_done.notify = register_smram_listener;
1620         qemu_add_machine_init_done_notifier(&smram_machine_done);
1621     }
1622
1623     if (enable_cpu_pm) {
1624         int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1625         int ret;
1626
1627 /* Work around for kernel header with a typo. TODO: fix header and drop. */
1628 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1629 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1630 #endif
1631         if (disable_exits) {
1632             disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1633                               KVM_X86_DISABLE_EXITS_HLT |
1634                               KVM_X86_DISABLE_EXITS_PAUSE);
1635         }
1636
1637         ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1638                                 disable_exits);
1639         if (ret < 0) {
1640             error_report("kvm: guest stopping CPU not supported: %s",
1641                          strerror(-ret));
1642         }
1643     }
1644
1645     return 0;
1646 }
1647
1648 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1649 {
1650     lhs->selector = rhs->selector;
1651     lhs->base = rhs->base;
1652     lhs->limit = rhs->limit;
1653     lhs->type = 3;
1654     lhs->present = 1;
1655     lhs->dpl = 3;
1656     lhs->db = 0;
1657     lhs->s = 1;
1658     lhs->l = 0;
1659     lhs->g = 0;
1660     lhs->avl = 0;
1661     lhs->unusable = 0;
1662 }
1663
1664 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1665 {
1666     unsigned flags = rhs->flags;
1667     lhs->selector = rhs->selector;
1668     lhs->base = rhs->base;
1669     lhs->limit = rhs->limit;
1670     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1671     lhs->present = (flags & DESC_P_MASK) != 0;
1672     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1673     lhs->db = (flags >> DESC_B_SHIFT) & 1;
1674     lhs->s = (flags & DESC_S_MASK) != 0;
1675     lhs->l = (flags >> DESC_L_SHIFT) & 1;
1676     lhs->g = (flags & DESC_G_MASK) != 0;
1677     lhs->avl = (flags & DESC_AVL_MASK) != 0;
1678     lhs->unusable = !lhs->present;
1679     lhs->padding = 0;
1680 }
1681
1682 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1683 {
1684     lhs->selector = rhs->selector;
1685     lhs->base = rhs->base;
1686     lhs->limit = rhs->limit;
1687     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1688                  ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1689                  (rhs->dpl << DESC_DPL_SHIFT) |
1690                  (rhs->db << DESC_B_SHIFT) |
1691                  (rhs->s * DESC_S_MASK) |
1692                  (rhs->l << DESC_L_SHIFT) |
1693                  (rhs->g * DESC_G_MASK) |
1694                  (rhs->avl * DESC_AVL_MASK);
1695 }
1696
1697 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1698 {
1699     if (set) {
1700         *kvm_reg = *qemu_reg;
1701     } else {
1702         *qemu_reg = *kvm_reg;
1703     }
1704 }
1705
1706 static int kvm_getput_regs(X86CPU *cpu, int set)
1707 {
1708     CPUX86State *env = &cpu->env;
1709     struct kvm_regs regs;
1710     int ret = 0;
1711
1712     if (!set) {
1713         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1714         if (ret < 0) {
1715             return ret;
1716         }
1717     }
1718
1719     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1720     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1721     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1722     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1723     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1724     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1725     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1726     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1727 #ifdef TARGET_X86_64
1728     kvm_getput_reg(&regs.r8, &env->regs[8], set);
1729     kvm_getput_reg(&regs.r9, &env->regs[9], set);
1730     kvm_getput_reg(&regs.r10, &env->regs[10], set);
1731     kvm_getput_reg(&regs.r11, &env->regs[11], set);
1732     kvm_getput_reg(&regs.r12, &env->regs[12], set);
1733     kvm_getput_reg(&regs.r13, &env->regs[13], set);
1734     kvm_getput_reg(&regs.r14, &env->regs[14], set);
1735     kvm_getput_reg(&regs.r15, &env->regs[15], set);
1736 #endif
1737
1738     kvm_getput_reg(&regs.rflags, &env->eflags, set);
1739     kvm_getput_reg(&regs.rip, &env->eip, set);
1740
1741     if (set) {
1742         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1743     }
1744
1745     return ret;
1746 }
1747
1748 static int kvm_put_fpu(X86CPU *cpu)
1749 {
1750     CPUX86State *env = &cpu->env;
1751     struct kvm_fpu fpu;
1752     int i;
1753
1754     memset(&fpu, 0, sizeof fpu);
1755     fpu.fsw = env->fpus & ~(7 << 11);
1756     fpu.fsw |= (env->fpstt & 7) << 11;
1757     fpu.fcw = env->fpuc;
1758     fpu.last_opcode = env->fpop;
1759     fpu.last_ip = env->fpip;
1760     fpu.last_dp = env->fpdp;
1761     for (i = 0; i < 8; ++i) {
1762         fpu.ftwx |= (!env->fptags[i]) << i;
1763     }
1764     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1765     for (i = 0; i < CPU_NB_REGS; i++) {
1766         stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1767         stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1768     }
1769     fpu.mxcsr = env->mxcsr;
1770
1771     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1772 }
1773
1774 #define XSAVE_FCW_FSW     0
1775 #define XSAVE_FTW_FOP     1
1776 #define XSAVE_CWD_RIP     2
1777 #define XSAVE_CWD_RDP     4
1778 #define XSAVE_MXCSR       6
1779 #define XSAVE_ST_SPACE    8
1780 #define XSAVE_XMM_SPACE   40
1781 #define XSAVE_XSTATE_BV   128
1782 #define XSAVE_YMMH_SPACE  144
1783 #define XSAVE_BNDREGS     240
1784 #define XSAVE_BNDCSR      256
1785 #define XSAVE_OPMASK      272
1786 #define XSAVE_ZMM_Hi256   288
1787 #define XSAVE_Hi16_ZMM    416
1788 #define XSAVE_PKRU        672
1789
1790 #define XSAVE_BYTE_OFFSET(word_offset) \
1791     ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
1792
1793 #define ASSERT_OFFSET(word_offset, field) \
1794     QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1795                       offsetof(X86XSaveArea, field))
1796
1797 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1798 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1799 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1800 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1801 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1802 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1803 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1804 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1805 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1806 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1807 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1808 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1809 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1810 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1811 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1812
1813 static int kvm_put_xsave(X86CPU *cpu)
1814 {
1815     CPUX86State *env = &cpu->env;
1816     X86XSaveArea *xsave = env->xsave_buf;
1817
1818     if (!has_xsave) {
1819         return kvm_put_fpu(cpu);
1820     }
1821     x86_cpu_xsave_all_areas(cpu, xsave);
1822
1823     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1824 }
1825
1826 static int kvm_put_xcrs(X86CPU *cpu)
1827 {
1828     CPUX86State *env = &cpu->env;
1829     struct kvm_xcrs xcrs = {};
1830
1831     if (!has_xcrs) {
1832         return 0;
1833     }
1834
1835     xcrs.nr_xcrs = 1;
1836     xcrs.flags = 0;
1837     xcrs.xcrs[0].xcr = 0;
1838     xcrs.xcrs[0].value = env->xcr0;
1839     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1840 }
1841
1842 static int kvm_put_sregs(X86CPU *cpu)
1843 {
1844     CPUX86State *env = &cpu->env;
1845     struct kvm_sregs sregs;
1846
1847     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1848     if (env->interrupt_injected >= 0) {
1849         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1850                 (uint64_t)1 << (env->interrupt_injected % 64);
1851     }
1852
1853     if ((env->eflags & VM_MASK)) {
1854         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1855         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1856         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1857         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1858         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1859         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1860     } else {
1861         set_seg(&sregs.cs, &env->segs[R_CS]);
1862         set_seg(&sregs.ds, &env->segs[R_DS]);
1863         set_seg(&sregs.es, &env->segs[R_ES]);
1864         set_seg(&sregs.fs, &env->segs[R_FS]);
1865         set_seg(&sregs.gs, &env->segs[R_GS]);
1866         set_seg(&sregs.ss, &env->segs[R_SS]);
1867     }
1868
1869     set_seg(&sregs.tr, &env->tr);
1870     set_seg(&sregs.ldt, &env->ldt);
1871
1872     sregs.idt.limit = env->idt.limit;
1873     sregs.idt.base = env->idt.base;
1874     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1875     sregs.gdt.limit = env->gdt.limit;
1876     sregs.gdt.base = env->gdt.base;
1877     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1878
1879     sregs.cr0 = env->cr[0];
1880     sregs.cr2 = env->cr[2];
1881     sregs.cr3 = env->cr[3];
1882     sregs.cr4 = env->cr[4];
1883
1884     sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1885     sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1886
1887     sregs.efer = env->efer;
1888
1889     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1890 }
1891
1892 static void kvm_msr_buf_reset(X86CPU *cpu)
1893 {
1894     memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1895 }
1896
1897 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1898 {
1899     struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1900     void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1901     struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1902
1903     assert((void *)(entry + 1) <= limit);
1904
1905     entry->index = index;
1906     entry->reserved = 0;
1907     entry->data = value;
1908     msrs->nmsrs++;
1909 }
1910
1911 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1912 {
1913     kvm_msr_buf_reset(cpu);
1914     kvm_msr_entry_add(cpu, index, value);
1915
1916     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1917 }
1918
1919 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1920 {
1921     int ret;
1922
1923     ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1924     assert(ret == 1);
1925 }
1926
1927 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1928 {
1929     CPUX86State *env = &cpu->env;
1930     int ret;
1931
1932     if (!has_msr_tsc_deadline) {
1933         return 0;
1934     }
1935
1936     ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1937     if (ret < 0) {
1938         return ret;
1939     }
1940
1941     assert(ret == 1);
1942     return 0;
1943 }
1944
1945 /*
1946  * Provide a separate write service for the feature control MSR in order to
1947  * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1948  * before writing any other state because forcibly leaving nested mode
1949  * invalidates the VCPU state.
1950  */
1951 static int kvm_put_msr_feature_control(X86CPU *cpu)
1952 {
1953     int ret;
1954
1955     if (!has_msr_feature_control) {
1956         return 0;
1957     }
1958
1959     ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1960                           cpu->env.msr_ia32_feature_control);
1961     if (ret < 0) {
1962         return ret;
1963     }
1964
1965     assert(ret == 1);
1966     return 0;
1967 }
1968
1969 static int kvm_put_msrs(X86CPU *cpu, int level)
1970 {
1971     CPUX86State *env = &cpu->env;
1972     int i;
1973     int ret;
1974
1975     kvm_msr_buf_reset(cpu);
1976
1977     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1978     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1979     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1980     kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1981     if (has_msr_star) {
1982         kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1983     }
1984     if (has_msr_hsave_pa) {
1985         kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1986     }
1987     if (has_msr_tsc_aux) {
1988         kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1989     }
1990     if (has_msr_tsc_adjust) {
1991         kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1992     }
1993     if (has_msr_misc_enable) {
1994         kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1995                           env->msr_ia32_misc_enable);
1996     }
1997     if (has_msr_smbase) {
1998         kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1999     }
2000     if (has_msr_smi_count) {
2001         kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2002     }
2003     if (has_msr_bndcfgs) {
2004         kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
2005     }
2006     if (has_msr_xss) {
2007         kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
2008     }
2009     if (has_msr_spec_ctrl) {
2010         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2011     }
2012     if (has_msr_virt_ssbd) {
2013         kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2014     }
2015
2016 #ifdef TARGET_X86_64
2017     if (lm_capable_kernel) {
2018         kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2019         kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2020         kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2021         kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
2022     }
2023 #endif
2024
2025     /* If host supports feature MSR, write down. */
2026     if (has_msr_arch_capabs) {
2027         kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2028                           env->features[FEAT_ARCH_CAPABILITIES]);
2029     }
2030
2031     /*
2032      * The following MSRs have side effects on the guest or are too heavy
2033      * for normal writeback. Limit them to reset or full state updates.
2034      */
2035     if (level >= KVM_PUT_RESET_STATE) {
2036         kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2037         kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2038         kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
2039         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2040             kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
2041         }
2042         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2043             kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2044         }
2045         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2046             kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2047         }
2048         if (has_architectural_pmu_version > 0) {
2049             if (has_architectural_pmu_version > 1) {
2050                 /* Stop the counter.  */
2051                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2052                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2053             }
2054
2055             /* Set the counter values.  */
2056             for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2057                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2058                                   env->msr_fixed_counters[i]);
2059             }
2060             for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2061                 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2062                                   env->msr_gp_counters[i]);
2063                 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2064                                   env->msr_gp_evtsel[i]);
2065             }
2066             if (has_architectural_pmu_version > 1) {
2067                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2068                                   env->msr_global_status);
2069                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2070                                   env->msr_global_ovf_ctrl);
2071
2072                 /* Now start the PMU.  */
2073                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2074                                   env->msr_fixed_ctr_ctrl);
2075                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2076                                   env->msr_global_ctrl);
2077             }
2078         }
2079         /*
2080          * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2081          * only sync them to KVM on the first cpu
2082          */
2083         if (current_cpu == first_cpu) {
2084             if (has_msr_hv_hypercall) {
2085                 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2086                                   env->msr_hv_guest_os_id);
2087                 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2088                                   env->msr_hv_hypercall);
2089             }
2090             if (cpu->hyperv_time) {
2091                 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2092                                   env->msr_hv_tsc);
2093             }
2094             if (cpu->hyperv_reenlightenment) {
2095                 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2096                                   env->msr_hv_reenlightenment_control);
2097                 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2098                                   env->msr_hv_tsc_emulation_control);
2099                 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2100                                   env->msr_hv_tsc_emulation_status);
2101             }
2102         }
2103         if (cpu->hyperv_vapic) {
2104             kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2105                               env->msr_hv_vapic);
2106         }
2107         if (has_msr_hv_crash) {
2108             int j;
2109
2110             for (j = 0; j < HV_CRASH_PARAMS; j++)
2111                 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2112                                   env->msr_hv_crash_params[j]);
2113
2114             kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2115         }
2116         if (has_msr_hv_runtime) {
2117             kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2118         }
2119         if (cpu->hyperv_vpindex && hv_vpindex_settable) {
2120             kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2121                               hyperv_vp_index(CPU(cpu)));
2122         }
2123         if (cpu->hyperv_synic) {
2124             int j;
2125
2126             kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2127
2128             kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2129                               env->msr_hv_synic_control);
2130             kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
2131                               env->msr_hv_synic_evt_page);
2132             kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
2133                               env->msr_hv_synic_msg_page);
2134
2135             for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
2136                 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
2137                                   env->msr_hv_synic_sint[j]);
2138             }
2139         }
2140         if (has_msr_hv_stimer) {
2141             int j;
2142
2143             for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
2144                 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
2145                                 env->msr_hv_stimer_config[j]);
2146             }
2147
2148             for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2149                 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2150                                 env->msr_hv_stimer_count[j]);
2151             }
2152         }
2153         if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2154             uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2155
2156             kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2157             kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2158             kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2159             kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2160             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2161             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2162             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2163             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2164             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2165             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2166             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2167             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2168             for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2169                 /* The CPU GPs if we write to a bit above the physical limit of
2170                  * the host CPU (and KVM emulates that)
2171                  */
2172                 uint64_t mask = env->mtrr_var[i].mask;
2173                 mask &= phys_mask;
2174
2175                 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2176                                   env->mtrr_var[i].base);
2177                 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2178             }
2179         }
2180         if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2181             int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2182                                                     0x14, 1, R_EAX) & 0x7;
2183
2184             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2185                             env->msr_rtit_ctrl);
2186             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2187                             env->msr_rtit_status);
2188             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2189                             env->msr_rtit_output_base);
2190             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2191                             env->msr_rtit_output_mask);
2192             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2193                             env->msr_rtit_cr3_match);
2194             for (i = 0; i < addr_num; i++) {
2195                 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2196                             env->msr_rtit_addrs[i]);
2197             }
2198         }
2199
2200         /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2201          *       kvm_put_msr_feature_control. */
2202     }
2203     if (env->mcg_cap) {
2204         int i;
2205
2206         kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2207         kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2208         if (has_msr_mcg_ext_ctl) {
2209             kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2210         }
2211         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2212             kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2213         }
2214     }
2215
2216     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2217     if (ret < 0) {
2218         return ret;
2219     }
2220
2221     if (ret < cpu->kvm_msr_buf->nmsrs) {
2222         struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2223         error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2224                      (uint32_t)e->index, (uint64_t)e->data);
2225     }
2226
2227     assert(ret == cpu->kvm_msr_buf->nmsrs);
2228     return 0;
2229 }
2230
2231
2232 static int kvm_get_fpu(X86CPU *cpu)
2233 {
2234     CPUX86State *env = &cpu->env;
2235     struct kvm_fpu fpu;
2236     int i, ret;
2237
2238     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
2239     if (ret < 0) {
2240         return ret;
2241     }
2242
2243     env->fpstt = (fpu.fsw >> 11) & 7;
2244     env->fpus = fpu.fsw;
2245     env->fpuc = fpu.fcw;
2246     env->fpop = fpu.last_opcode;
2247     env->fpip = fpu.last_ip;
2248     env->fpdp = fpu.last_dp;
2249     for (i = 0; i < 8; ++i) {
2250         env->fptags[i] = !((fpu.ftwx >> i) & 1);
2251     }
2252     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
2253     for (i = 0; i < CPU_NB_REGS; i++) {
2254         env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2255         env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
2256     }
2257     env->mxcsr = fpu.mxcsr;
2258
2259     return 0;
2260 }
2261
2262 static int kvm_get_xsave(X86CPU *cpu)
2263 {
2264     CPUX86State *env = &cpu->env;
2265     X86XSaveArea *xsave = env->xsave_buf;
2266     int ret;
2267
2268     if (!has_xsave) {
2269         return kvm_get_fpu(cpu);
2270     }
2271
2272     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
2273     if (ret < 0) {
2274         return ret;
2275     }
2276     x86_cpu_xrstor_all_areas(cpu, xsave);
2277
2278     return 0;
2279 }
2280
2281 static int kvm_get_xcrs(X86CPU *cpu)
2282 {
2283     CPUX86State *env = &cpu->env;
2284     int i, ret;
2285     struct kvm_xcrs xcrs;
2286
2287     if (!has_xcrs) {
2288         return 0;
2289     }
2290
2291     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
2292     if (ret < 0) {
2293         return ret;
2294     }
2295
2296     for (i = 0; i < xcrs.nr_xcrs; i++) {
2297         /* Only support xcr0 now */
2298         if (xcrs.xcrs[i].xcr == 0) {
2299             env->xcr0 = xcrs.xcrs[i].value;
2300             break;
2301         }
2302     }
2303     return 0;
2304 }
2305
2306 static int kvm_get_sregs(X86CPU *cpu)
2307 {
2308     CPUX86State *env = &cpu->env;
2309     struct kvm_sregs sregs;
2310     int bit, i, ret;
2311
2312     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
2313     if (ret < 0) {
2314         return ret;
2315     }
2316
2317     /* There can only be one pending IRQ set in the bitmap at a time, so try
2318        to find it and save its number instead (-1 for none). */
2319     env->interrupt_injected = -1;
2320     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2321         if (sregs.interrupt_bitmap[i]) {
2322             bit = ctz64(sregs.interrupt_bitmap[i]);
2323             env->interrupt_injected = i * 64 + bit;
2324             break;
2325         }
2326     }
2327
2328     get_seg(&env->segs[R_CS], &sregs.cs);
2329     get_seg(&env->segs[R_DS], &sregs.ds);
2330     get_seg(&env->segs[R_ES], &sregs.es);
2331     get_seg(&env->segs[R_FS], &sregs.fs);
2332     get_seg(&env->segs[R_GS], &sregs.gs);
2333     get_seg(&env->segs[R_SS], &sregs.ss);
2334
2335     get_seg(&env->tr, &sregs.tr);
2336     get_seg(&env->ldt, &sregs.ldt);
2337
2338     env->idt.limit = sregs.idt.limit;
2339     env->idt.base = sregs.idt.base;
2340     env->gdt.limit = sregs.gdt.limit;
2341     env->gdt.base = sregs.gdt.base;
2342
2343     env->cr[0] = sregs.cr0;
2344     env->cr[2] = sregs.cr2;
2345     env->cr[3] = sregs.cr3;
2346     env->cr[4] = sregs.cr4;
2347
2348     env->efer = sregs.efer;
2349
2350     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2351     x86_update_hflags(env);
2352
2353     return 0;
2354 }
2355
2356 static int kvm_get_msrs(X86CPU *cpu)
2357 {
2358     CPUX86State *env = &cpu->env;
2359     struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2360     int ret, i;
2361     uint64_t mtrr_top_bits;
2362
2363     kvm_msr_buf_reset(cpu);
2364
2365     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2366     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2367     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2368     kvm_msr_entry_add(cpu, MSR_PAT, 0);
2369     if (has_msr_star) {
2370         kvm_msr_entry_add(cpu, MSR_STAR, 0);
2371     }
2372     if (has_msr_hsave_pa) {
2373         kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2374     }
2375     if (has_msr_tsc_aux) {
2376         kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2377     }
2378     if (has_msr_tsc_adjust) {
2379         kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2380     }
2381     if (has_msr_tsc_deadline) {
2382         kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2383     }
2384     if (has_msr_misc_enable) {
2385         kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2386     }
2387     if (has_msr_smbase) {
2388         kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2389     }
2390     if (has_msr_smi_count) {
2391         kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2392     }
2393     if (has_msr_feature_control) {
2394         kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2395     }
2396     if (has_msr_bndcfgs) {
2397         kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2398     }
2399     if (has_msr_xss) {
2400         kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2401     }
2402     if (has_msr_spec_ctrl) {
2403         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2404     }
2405     if (has_msr_virt_ssbd) {
2406         kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2407     }
2408     if (!env->tsc_valid) {
2409         kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2410         env->tsc_valid = !runstate_is_running();
2411     }
2412
2413 #ifdef TARGET_X86_64
2414     if (lm_capable_kernel) {
2415         kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2416         kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2417         kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2418         kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2419     }
2420 #endif
2421     kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2422     kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2423     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2424         kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2425     }
2426     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2427         kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2428     }
2429     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2430         kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2431     }
2432     if (has_architectural_pmu_version > 0) {
2433         if (has_architectural_pmu_version > 1) {
2434             kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2435             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2436             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2437             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2438         }
2439         for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2440             kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2441         }
2442         for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2443             kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2444             kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2445         }
2446     }
2447
2448     if (env->mcg_cap) {
2449         kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2450         kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2451         if (has_msr_mcg_ext_ctl) {
2452             kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2453         }
2454         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2455             kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2456         }
2457     }
2458
2459     if (has_msr_hv_hypercall) {
2460         kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2461         kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2462     }
2463     if (cpu->hyperv_vapic) {
2464         kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2465     }
2466     if (cpu->hyperv_time) {
2467         kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2468     }
2469     if (cpu->hyperv_reenlightenment) {
2470         kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2471         kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2472         kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2473     }
2474     if (has_msr_hv_crash) {
2475         int j;
2476
2477         for (j = 0; j < HV_CRASH_PARAMS; j++) {
2478             kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2479         }
2480     }
2481     if (has_msr_hv_runtime) {
2482         kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2483     }
2484     if (cpu->hyperv_synic) {
2485         uint32_t msr;
2486
2487         kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2488         kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2489         kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2490         for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2491             kvm_msr_entry_add(cpu, msr, 0);
2492         }
2493     }
2494     if (has_msr_hv_stimer) {
2495         uint32_t msr;
2496
2497         for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2498              msr++) {
2499             kvm_msr_entry_add(cpu, msr, 0);
2500         }
2501     }
2502     if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2503         kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2504         kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2505         kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2506         kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2507         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2508         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2509         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2510         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2511         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2512         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2513         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2514         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2515         for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2516             kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2517             kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2518         }
2519     }
2520
2521     if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2522         int addr_num =
2523             kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2524
2525         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2526         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2527         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2528         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2529         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2530         for (i = 0; i < addr_num; i++) {
2531             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2532         }
2533     }
2534
2535     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2536     if (ret < 0) {
2537         return ret;
2538     }
2539
2540     if (ret < cpu->kvm_msr_buf->nmsrs) {
2541         struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2542         error_report("error: failed to get MSR 0x%" PRIx32,
2543                      (uint32_t)e->index);
2544     }
2545
2546     assert(ret == cpu->kvm_msr_buf->nmsrs);
2547     /*
2548      * MTRR masks: Each mask consists of 5 parts
2549      * a  10..0: must be zero
2550      * b  11   : valid bit
2551      * c n-1.12: actual mask bits
2552      * d  51..n: reserved must be zero
2553      * e  63.52: reserved must be zero
2554      *
2555      * 'n' is the number of physical bits supported by the CPU and is
2556      * apparently always <= 52.   We know our 'n' but don't know what
2557      * the destinations 'n' is; it might be smaller, in which case
2558      * it masks (c) on loading. It might be larger, in which case
2559      * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2560      * we're migrating to.
2561      */
2562
2563     if (cpu->fill_mtrr_mask) {
2564         QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2565         assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2566         mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2567     } else {
2568         mtrr_top_bits = 0;
2569     }
2570
2571     for (i = 0; i < ret; i++) {
2572         uint32_t index = msrs[i].index;
2573         switch (index) {
2574         case MSR_IA32_SYSENTER_CS:
2575             env->sysenter_cs = msrs[i].data;
2576             break;
2577         case MSR_IA32_SYSENTER_ESP:
2578             env->sysenter_esp = msrs[i].data;
2579             break;
2580         case MSR_IA32_SYSENTER_EIP:
2581             env->sysenter_eip = msrs[i].data;
2582             break;
2583         case MSR_PAT:
2584             env->pat = msrs[i].data;
2585             break;
2586         case MSR_STAR:
2587             env->star = msrs[i].data;
2588             break;
2589 #ifdef TARGET_X86_64
2590         case MSR_CSTAR:
2591             env->cstar = msrs[i].data;
2592             break;
2593         case MSR_KERNELGSBASE:
2594             env->kernelgsbase = msrs[i].data;
2595             break;
2596         case MSR_FMASK:
2597             env->fmask = msrs[i].data;
2598             break;
2599         case MSR_LSTAR:
2600             env->lstar = msrs[i].data;
2601             break;
2602 #endif
2603         case MSR_IA32_TSC:
2604             env->tsc = msrs[i].data;
2605             break;
2606         case MSR_TSC_AUX:
2607             env->tsc_aux = msrs[i].data;
2608             break;
2609         case MSR_TSC_ADJUST:
2610             env->tsc_adjust = msrs[i].data;
2611             break;
2612         case MSR_IA32_TSCDEADLINE:
2613             env->tsc_deadline = msrs[i].data;
2614             break;
2615         case MSR_VM_HSAVE_PA:
2616             env->vm_hsave = msrs[i].data;
2617             break;
2618         case MSR_KVM_SYSTEM_TIME:
2619             env->system_time_msr = msrs[i].data;
2620             break;
2621         case MSR_KVM_WALL_CLOCK:
2622             env->wall_clock_msr = msrs[i].data;
2623             break;
2624         case MSR_MCG_STATUS:
2625             env->mcg_status = msrs[i].data;
2626             break;
2627         case MSR_MCG_CTL:
2628             env->mcg_ctl = msrs[i].data;
2629             break;
2630         case MSR_MCG_EXT_CTL:
2631             env->mcg_ext_ctl = msrs[i].data;
2632             break;
2633         case MSR_IA32_MISC_ENABLE:
2634             env->msr_ia32_misc_enable = msrs[i].data;
2635             break;
2636         case MSR_IA32_SMBASE:
2637             env->smbase = msrs[i].data;
2638             break;
2639         case MSR_SMI_COUNT:
2640             env->msr_smi_count = msrs[i].data;
2641             break;
2642         case MSR_IA32_FEATURE_CONTROL:
2643             env->msr_ia32_feature_control = msrs[i].data;
2644             break;
2645         case MSR_IA32_BNDCFGS:
2646             env->msr_bndcfgs = msrs[i].data;
2647             break;
2648         case MSR_IA32_XSS:
2649             env->xss = msrs[i].data;
2650             break;
2651         default:
2652             if (msrs[i].index >= MSR_MC0_CTL &&
2653                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2654                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2655             }
2656             break;
2657         case MSR_KVM_ASYNC_PF_EN:
2658             env->async_pf_en_msr = msrs[i].data;
2659             break;
2660         case MSR_KVM_PV_EOI_EN:
2661             env->pv_eoi_en_msr = msrs[i].data;
2662             break;
2663         case MSR_KVM_STEAL_TIME:
2664             env->steal_time_msr = msrs[i].data;
2665             break;
2666         case MSR_CORE_PERF_FIXED_CTR_CTRL:
2667             env->msr_fixed_ctr_ctrl = msrs[i].data;
2668             break;
2669         case MSR_CORE_PERF_GLOBAL_CTRL:
2670             env->msr_global_ctrl = msrs[i].data;
2671             break;
2672         case MSR_CORE_PERF_GLOBAL_STATUS:
2673             env->msr_global_status = msrs[i].data;
2674             break;
2675         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2676             env->msr_global_ovf_ctrl = msrs[i].data;
2677             break;
2678         case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2679             env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2680             break;
2681         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2682             env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2683             break;
2684         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2685             env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2686             break;
2687         case HV_X64_MSR_HYPERCALL:
2688             env->msr_hv_hypercall = msrs[i].data;
2689             break;
2690         case HV_X64_MSR_GUEST_OS_ID:
2691             env->msr_hv_guest_os_id = msrs[i].data;
2692             break;
2693         case HV_X64_MSR_APIC_ASSIST_PAGE:
2694             env->msr_hv_vapic = msrs[i].data;
2695             break;
2696         case HV_X64_MSR_REFERENCE_TSC:
2697             env->msr_hv_tsc = msrs[i].data;
2698             break;
2699         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2700             env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2701             break;
2702         case HV_X64_MSR_VP_RUNTIME:
2703             env->msr_hv_runtime = msrs[i].data;
2704             break;
2705         case HV_X64_MSR_SCONTROL:
2706             env->msr_hv_synic_control = msrs[i].data;
2707             break;
2708         case HV_X64_MSR_SIEFP:
2709             env->msr_hv_synic_evt_page = msrs[i].data;
2710             break;
2711         case HV_X64_MSR_SIMP:
2712             env->msr_hv_synic_msg_page = msrs[i].data;
2713             break;
2714         case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2715             env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2716             break;
2717         case HV_X64_MSR_STIMER0_CONFIG:
2718         case HV_X64_MSR_STIMER1_CONFIG:
2719         case HV_X64_MSR_STIMER2_CONFIG:
2720         case HV_X64_MSR_STIMER3_CONFIG:
2721             env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2722                                 msrs[i].data;
2723             break;
2724         case HV_X64_MSR_STIMER0_COUNT:
2725         case HV_X64_MSR_STIMER1_COUNT:
2726         case HV_X64_MSR_STIMER2_COUNT:
2727         case HV_X64_MSR_STIMER3_COUNT:
2728             env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2729                                 msrs[i].data;
2730             break;
2731         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2732             env->msr_hv_reenlightenment_control = msrs[i].data;
2733             break;
2734         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2735             env->msr_hv_tsc_emulation_control = msrs[i].data;
2736             break;
2737         case HV_X64_MSR_TSC_EMULATION_STATUS:
2738             env->msr_hv_tsc_emulation_status = msrs[i].data;
2739             break;
2740         case MSR_MTRRdefType:
2741             env->mtrr_deftype = msrs[i].data;
2742             break;
2743         case MSR_MTRRfix64K_00000:
2744             env->mtrr_fixed[0] = msrs[i].data;
2745             break;
2746         case MSR_MTRRfix16K_80000:
2747             env->mtrr_fixed[1] = msrs[i].data;
2748             break;
2749         case MSR_MTRRfix16K_A0000:
2750             env->mtrr_fixed[2] = msrs[i].data;
2751             break;
2752         case MSR_MTRRfix4K_C0000:
2753             env->mtrr_fixed[3] = msrs[i].data;
2754             break;
2755         case MSR_MTRRfix4K_C8000:
2756             env->mtrr_fixed[4] = msrs[i].data;
2757             break;
2758         case MSR_MTRRfix4K_D0000:
2759             env->mtrr_fixed[5] = msrs[i].data;
2760             break;
2761         case MSR_MTRRfix4K_D8000:
2762             env->mtrr_fixed[6] = msrs[i].data;
2763             break;
2764         case MSR_MTRRfix4K_E0000:
2765             env->mtrr_fixed[7] = msrs[i].data;
2766             break;
2767         case MSR_MTRRfix4K_E8000:
2768             env->mtrr_fixed[8] = msrs[i].data;
2769             break;
2770         case MSR_MTRRfix4K_F0000:
2771             env->mtrr_fixed[9] = msrs[i].data;
2772             break;
2773         case MSR_MTRRfix4K_F8000:
2774             env->mtrr_fixed[10] = msrs[i].data;
2775             break;
2776         case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2777             if (index & 1) {
2778                 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2779                                                                mtrr_top_bits;
2780             } else {
2781                 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2782             }
2783             break;
2784         case MSR_IA32_SPEC_CTRL:
2785             env->spec_ctrl = msrs[i].data;
2786             break;
2787         case MSR_VIRT_SSBD:
2788             env->virt_ssbd = msrs[i].data;
2789             break;
2790         case MSR_IA32_RTIT_CTL:
2791             env->msr_rtit_ctrl = msrs[i].data;
2792             break;
2793         case MSR_IA32_RTIT_STATUS:
2794             env->msr_rtit_status = msrs[i].data;
2795             break;
2796         case MSR_IA32_RTIT_OUTPUT_BASE:
2797             env->msr_rtit_output_base = msrs[i].data;
2798             break;
2799         case MSR_IA32_RTIT_OUTPUT_MASK:
2800             env->msr_rtit_output_mask = msrs[i].data;
2801             break;
2802         case MSR_IA32_RTIT_CR3_MATCH:
2803             env->msr_rtit_cr3_match = msrs[i].data;
2804             break;
2805         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2806             env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2807             break;
2808         }
2809     }
2810
2811     return 0;
2812 }
2813
2814 static int kvm_put_mp_state(X86CPU *cpu)
2815 {
2816     struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2817
2818     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2819 }
2820
2821 static int kvm_get_mp_state(X86CPU *cpu)
2822 {
2823     CPUState *cs = CPU(cpu);
2824     CPUX86State *env = &cpu->env;
2825     struct kvm_mp_state mp_state;
2826     int ret;
2827
2828     ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2829     if (ret < 0) {
2830         return ret;
2831     }
2832     env->mp_state = mp_state.mp_state;
2833     if (kvm_irqchip_in_kernel()) {
2834         cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2835     }
2836     return 0;
2837 }
2838
2839 static int kvm_get_apic(X86CPU *cpu)
2840 {
2841     DeviceState *apic = cpu->apic_state;
2842     struct kvm_lapic_state kapic;
2843     int ret;
2844
2845     if (apic && kvm_irqchip_in_kernel()) {
2846         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2847         if (ret < 0) {
2848             return ret;
2849         }
2850
2851         kvm_get_apic_state(apic, &kapic);
2852     }
2853     return 0;
2854 }
2855
2856 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2857 {
2858     CPUState *cs = CPU(cpu);
2859     CPUX86State *env = &cpu->env;
2860     struct kvm_vcpu_events events = {};
2861
2862     if (!kvm_has_vcpu_events()) {
2863         return 0;
2864     }
2865
2866     events.exception.injected = (env->exception_injected >= 0);
2867     events.exception.nr = env->exception_injected;
2868     events.exception.has_error_code = env->has_error_code;
2869     events.exception.error_code = env->error_code;
2870
2871     events.interrupt.injected = (env->interrupt_injected >= 0);
2872     events.interrupt.nr = env->interrupt_injected;
2873     events.interrupt.soft = env->soft_interrupt;
2874
2875     events.nmi.injected = env->nmi_injected;
2876     events.nmi.pending = env->nmi_pending;
2877     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2878
2879     events.sipi_vector = env->sipi_vector;
2880     events.flags = 0;
2881
2882     if (has_msr_smbase) {
2883         events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2884         events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2885         if (kvm_irqchip_in_kernel()) {
2886             /* As soon as these are moved to the kernel, remove them
2887              * from cs->interrupt_request.
2888              */
2889             events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2890             events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2891             cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2892         } else {
2893             /* Keep these in cs->interrupt_request.  */
2894             events.smi.pending = 0;
2895             events.smi.latched_init = 0;
2896         }
2897         /* Stop SMI delivery on old machine types to avoid a reboot
2898          * on an inward migration of an old VM.
2899          */
2900         if (!cpu->kvm_no_smi_migration) {
2901             events.flags |= KVM_VCPUEVENT_VALID_SMM;
2902         }
2903     }
2904
2905     if (level >= KVM_PUT_RESET_STATE) {
2906         events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2907         if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2908             events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2909         }
2910     }
2911
2912     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2913 }
2914
2915 static int kvm_get_vcpu_events(X86CPU *cpu)
2916 {
2917     CPUX86State *env = &cpu->env;
2918     struct kvm_vcpu_events events;
2919     int ret;
2920
2921     if (!kvm_has_vcpu_events()) {
2922         return 0;
2923     }
2924
2925     memset(&events, 0, sizeof(events));
2926     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2927     if (ret < 0) {
2928        return ret;
2929     }
2930     env->exception_injected =
2931        events.exception.injected ? events.exception.nr : -1;
2932     env->has_error_code = events.exception.has_error_code;
2933     env->error_code = events.exception.error_code;
2934
2935     env->interrupt_injected =
2936         events.interrupt.injected ? events.interrupt.nr : -1;
2937     env->soft_interrupt = events.interrupt.soft;
2938
2939     env->nmi_injected = events.nmi.injected;
2940     env->nmi_pending = events.nmi.pending;
2941     if (events.nmi.masked) {
2942         env->hflags2 |= HF2_NMI_MASK;
2943     } else {
2944         env->hflags2 &= ~HF2_NMI_MASK;
2945     }
2946
2947     if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2948         if (events.smi.smm) {
2949             env->hflags |= HF_SMM_MASK;
2950         } else {
2951             env->hflags &= ~HF_SMM_MASK;
2952         }
2953         if (events.smi.pending) {
2954             cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2955         } else {
2956             cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2957         }
2958         if (events.smi.smm_inside_nmi) {
2959             env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2960         } else {
2961             env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2962         }
2963         if (events.smi.latched_init) {
2964             cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2965         } else {
2966             cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2967         }
2968     }
2969
2970     env->sipi_vector = events.sipi_vector;
2971
2972     return 0;
2973 }
2974
2975 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2976 {
2977     CPUState *cs = CPU(cpu);
2978     CPUX86State *env = &cpu->env;
2979     int ret = 0;
2980     unsigned long reinject_trap = 0;
2981
2982     if (!kvm_has_vcpu_events()) {
2983         if (env->exception_injected == 1) {
2984             reinject_trap = KVM_GUESTDBG_INJECT_DB;
2985         } else if (env->exception_injected == 3) {
2986             reinject_trap = KVM_GUESTDBG_INJECT_BP;
2987         }
2988         env->exception_injected = -1;
2989     }
2990
2991     /*
2992      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2993      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2994      * by updating the debug state once again if single-stepping is on.
2995      * Another reason to call kvm_update_guest_debug here is a pending debug
2996      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2997      * reinject them via SET_GUEST_DEBUG.
2998      */
2999     if (reinject_trap ||
3000         (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
3001         ret = kvm_update_guest_debug(cs, reinject_trap);
3002     }
3003     return ret;
3004 }
3005
3006 static int kvm_put_debugregs(X86CPU *cpu)
3007 {
3008     CPUX86State *env = &cpu->env;
3009     struct kvm_debugregs dbgregs;
3010     int i;
3011
3012     if (!kvm_has_debugregs()) {
3013         return 0;
3014     }
3015
3016     for (i = 0; i < 4; i++) {
3017         dbgregs.db[i] = env->dr[i];
3018     }
3019     dbgregs.dr6 = env->dr[6];
3020     dbgregs.dr7 = env->dr[7];
3021     dbgregs.flags = 0;
3022
3023     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
3024 }
3025
3026 static int kvm_get_debugregs(X86CPU *cpu)
3027 {
3028     CPUX86State *env = &cpu->env;
3029     struct kvm_debugregs dbgregs;
3030     int i, ret;
3031
3032     if (!kvm_has_debugregs()) {
3033         return 0;
3034     }
3035
3036     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
3037     if (ret < 0) {
3038         return ret;
3039     }
3040     for (i = 0; i < 4; i++) {
3041         env->dr[i] = dbgregs.db[i];
3042     }
3043     env->dr[4] = env->dr[6] = dbgregs.dr6;
3044     env->dr[5] = env->dr[7] = dbgregs.dr7;
3045
3046     return 0;
3047 }
3048
3049 int kvm_arch_put_registers(CPUState *cpu, int level)
3050 {
3051     X86CPU *x86_cpu = X86_CPU(cpu);
3052     int ret;
3053
3054     assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
3055
3056     if (level >= KVM_PUT_RESET_STATE) {
3057         ret = kvm_put_msr_feature_control(x86_cpu);
3058         if (ret < 0) {
3059             return ret;
3060         }
3061     }
3062
3063     if (level == KVM_PUT_FULL_STATE) {
3064         /* We don't check for kvm_arch_set_tsc_khz() errors here,
3065          * because TSC frequency mismatch shouldn't abort migration,
3066          * unless the user explicitly asked for a more strict TSC
3067          * setting (e.g. using an explicit "tsc-freq" option).
3068          */
3069         kvm_arch_set_tsc_khz(cpu);
3070     }
3071
3072     ret = kvm_getput_regs(x86_cpu, 1);
3073     if (ret < 0) {
3074         return ret;
3075     }
3076     ret = kvm_put_xsave(x86_cpu);
3077     if (ret < 0) {
3078         return ret;
3079     }
3080     ret = kvm_put_xcrs(x86_cpu);
3081     if (ret < 0) {
3082         return ret;
3083     }
3084     ret = kvm_put_sregs(x86_cpu);
3085     if (ret < 0) {
3086         return ret;
3087     }
3088     /* must be before kvm_put_msrs */
3089     ret = kvm_inject_mce_oldstyle(x86_cpu);
3090     if (ret < 0) {
3091         return ret;
3092     }
3093     ret = kvm_put_msrs(x86_cpu, level);
3094     if (ret < 0) {
3095         return ret;
3096     }
3097     ret = kvm_put_vcpu_events(x86_cpu, level);
3098     if (ret < 0) {
3099         return ret;
3100     }
3101     if (level >= KVM_PUT_RESET_STATE) {
3102         ret = kvm_put_mp_state(x86_cpu);
3103         if (ret < 0) {
3104             return ret;
3105         }
3106     }
3107
3108     ret = kvm_put_tscdeadline_msr(x86_cpu);
3109     if (ret < 0) {
3110         return ret;
3111     }
3112     ret = kvm_put_debugregs(x86_cpu);
3113     if (ret < 0) {
3114         return ret;
3115     }
3116     /* must be last */
3117     ret = kvm_guest_debug_workarounds(x86_cpu);
3118     if (ret < 0) {
3119         return ret;
3120     }
3121     return 0;
3122 }
3123
3124 int kvm_arch_get_registers(CPUState *cs)
3125 {
3126     X86CPU *cpu = X86_CPU(cs);
3127     int ret;
3128
3129     assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
3130
3131     ret = kvm_get_vcpu_events(cpu);
3132     if (ret < 0) {
3133         goto out;
3134     }
3135     /*
3136      * KVM_GET_MPSTATE can modify CS and RIP, call it before
3137      * KVM_GET_REGS and KVM_GET_SREGS.
3138      */
3139     ret = kvm_get_mp_state(cpu);
3140     if (ret < 0) {
3141         goto out;
3142     }
3143     ret = kvm_getput_regs(cpu, 0);
3144     if (ret < 0) {
3145         goto out;
3146     }
3147     ret = kvm_get_xsave(cpu);
3148     if (ret < 0) {
3149         goto out;
3150     }
3151     ret = kvm_get_xcrs(cpu);
3152     if (ret < 0) {
3153         goto out;
3154     }
3155     ret = kvm_get_sregs(cpu);
3156     if (ret < 0) {
3157         goto out;
3158     }
3159     ret = kvm_get_msrs(cpu);
3160     if (ret < 0) {
3161         goto out;
3162     }
3163     ret = kvm_get_apic(cpu);
3164     if (ret < 0) {
3165         goto out;
3166     }
3167     ret = kvm_get_debugregs(cpu);
3168     if (ret < 0) {
3169         goto out;
3170     }
3171     ret = 0;
3172  out:
3173     cpu_sync_bndcs_hflags(&cpu->env);
3174     return ret;
3175 }
3176
3177 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
3178 {
3179     X86CPU *x86_cpu = X86_CPU(cpu);
3180     CPUX86State *env = &x86_cpu->env;
3181     int ret;
3182
3183     /* Inject NMI */
3184     if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3185         if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3186             qemu_mutex_lock_iothread();
3187             cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3188             qemu_mutex_unlock_iothread();
3189             DPRINTF("injected NMI\n");
3190             ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3191             if (ret < 0) {
3192                 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3193                         strerror(-ret));
3194             }
3195         }
3196         if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3197             qemu_mutex_lock_iothread();
3198             cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3199             qemu_mutex_unlock_iothread();
3200             DPRINTF("injected SMI\n");
3201             ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3202             if (ret < 0) {
3203                 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3204                         strerror(-ret));
3205             }
3206         }
3207     }
3208
3209     if (!kvm_pic_in_kernel()) {
3210         qemu_mutex_lock_iothread();
3211     }
3212
3213     /* Force the VCPU out of its inner loop to process any INIT requests
3214      * or (for userspace APIC, but it is cheap to combine the checks here)
3215      * pending TPR access reports.
3216      */
3217     if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
3218         if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3219             !(env->hflags & HF_SMM_MASK)) {
3220             cpu->exit_request = 1;
3221         }
3222         if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3223             cpu->exit_request = 1;
3224         }
3225     }
3226
3227     if (!kvm_pic_in_kernel()) {
3228         /* Try to inject an interrupt if the guest can accept it */
3229         if (run->ready_for_interrupt_injection &&
3230             (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
3231             (env->eflags & IF_MASK)) {
3232             int irq;
3233
3234             cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
3235             irq = cpu_get_pic_interrupt(env);
3236             if (irq >= 0) {
3237                 struct kvm_interrupt intr;
3238
3239                 intr.irq = irq;
3240                 DPRINTF("injected interrupt %d\n", irq);
3241                 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
3242                 if (ret < 0) {
3243                     fprintf(stderr,
3244                             "KVM: injection failed, interrupt lost (%s)\n",
3245                             strerror(-ret));
3246                 }
3247             }
3248         }
3249
3250         /* If we have an interrupt but the guest is not ready to receive an
3251          * interrupt, request an interrupt window exit.  This will
3252          * cause a return to userspace as soon as the guest is ready to
3253          * receive interrupts. */
3254         if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
3255             run->request_interrupt_window = 1;
3256         } else {
3257             run->request_interrupt_window = 0;
3258         }
3259
3260         DPRINTF("setting tpr\n");
3261         run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
3262
3263         qemu_mutex_unlock_iothread();
3264     }
3265 }
3266
3267 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
3268 {
3269     X86CPU *x86_cpu = X86_CPU(cpu);
3270     CPUX86State *env = &x86_cpu->env;
3271
3272     if (run->flags & KVM_RUN_X86_SMM) {
3273         env->hflags |= HF_SMM_MASK;
3274     } else {
3275         env->hflags &= ~HF_SMM_MASK;
3276     }
3277     if (run->if_flag) {
3278         env->eflags |= IF_MASK;
3279     } else {
3280         env->eflags &= ~IF_MASK;
3281     }
3282
3283     /* We need to protect the apic state against concurrent accesses from
3284      * different threads in case the userspace irqchip is used. */
3285     if (!kvm_irqchip_in_kernel()) {
3286         qemu_mutex_lock_iothread();
3287     }
3288     cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3289     cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
3290     if (!kvm_irqchip_in_kernel()) {
3291         qemu_mutex_unlock_iothread();
3292     }
3293     return cpu_get_mem_attrs(env);
3294 }
3295
3296 int kvm_arch_process_async_events(CPUState *cs)
3297 {
3298     X86CPU *cpu = X86_CPU(cs);
3299     CPUX86State *env = &cpu->env;
3300
3301     if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
3302         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3303         assert(env->mcg_cap);
3304
3305         cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
3306
3307         kvm_cpu_synchronize_state(cs);
3308
3309         if (env->exception_injected == EXCP08_DBLE) {
3310             /* this means triple fault */
3311             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
3312             cs->exit_request = 1;
3313             return 0;
3314         }
3315         env->exception_injected = EXCP12_MCHK;
3316         env->has_error_code = 0;
3317
3318         cs->halted = 0;
3319         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3320             env->mp_state = KVM_MP_STATE_RUNNABLE;
3321         }
3322     }
3323
3324     if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3325         !(env->hflags & HF_SMM_MASK)) {
3326         kvm_cpu_synchronize_state(cs);
3327         do_cpu_init(cpu);
3328     }
3329
3330     if (kvm_irqchip_in_kernel()) {
3331         return 0;
3332     }
3333
3334     if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3335         cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
3336         apic_poll_irq(cpu->apic_state);
3337     }
3338     if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3339          (env->eflags & IF_MASK)) ||
3340         (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3341         cs->halted = 0;
3342     }
3343     if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
3344         kvm_cpu_synchronize_state(cs);
3345         do_cpu_sipi(cpu);
3346     }
3347     if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3348         cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
3349         kvm_cpu_synchronize_state(cs);
3350         apic_handle_tpr_access_report(cpu->apic_state, env->eip,
3351                                       env->tpr_access_type);
3352     }
3353
3354     return cs->halted;
3355 }
3356
3357 static int kvm_handle_halt(X86CPU *cpu)
3358 {
3359     CPUState *cs = CPU(cpu);
3360     CPUX86State *env = &cpu->env;
3361
3362     if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3363           (env->eflags & IF_MASK)) &&
3364         !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3365         cs->halted = 1;
3366         return EXCP_HLT;
3367     }
3368
3369     return 0;
3370 }
3371
3372 static int kvm_handle_tpr_access(X86CPU *cpu)
3373 {
3374     CPUState *cs = CPU(cpu);
3375     struct kvm_run *run = cs->kvm_run;
3376
3377     apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3378                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
3379                                                            : TPR_ACCESS_READ);
3380     return 1;
3381 }
3382
3383 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3384 {
3385     static const uint8_t int3 = 0xcc;
3386
3387     if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3388         cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3389         return -EINVAL;
3390     }
3391     return 0;
3392 }
3393
3394 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3395 {
3396     uint8_t int3;
3397
3398     if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3399         cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3400         return -EINVAL;
3401     }
3402     return 0;
3403 }
3404
3405 static struct {
3406     target_ulong addr;
3407     int len;
3408     int type;
3409 } hw_breakpoint[4];
3410
3411 static int nb_hw_breakpoint;
3412
3413 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3414 {
3415     int n;
3416
3417     for (n = 0; n < nb_hw_breakpoint; n++) {
3418         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3419             (hw_breakpoint[n].len == len || len == -1)) {
3420             return n;
3421         }
3422     }
3423     return -1;
3424 }
3425
3426 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3427                                   target_ulong len, int type)
3428 {
3429     switch (type) {
3430     case GDB_BREAKPOINT_HW:
3431         len = 1;
3432         break;
3433     case GDB_WATCHPOINT_WRITE:
3434     case GDB_WATCHPOINT_ACCESS:
3435         switch (len) {
3436         case 1:
3437             break;
3438         case 2:
3439         case 4:
3440         case 8:
3441             if (addr & (len - 1)) {
3442                 return -EINVAL;
3443             }
3444             break;
3445         default:
3446             return -EINVAL;
3447         }
3448         break;
3449     default:
3450         return -ENOSYS;
3451     }
3452
3453     if (nb_hw_breakpoint == 4) {
3454         return -ENOBUFS;
3455     }
3456     if (find_hw_breakpoint(addr, len, type) >= 0) {
3457         return -EEXIST;
3458     }
3459     hw_breakpoint[nb_hw_breakpoint].addr = addr;
3460     hw_breakpoint[nb_hw_breakpoint].len = len;
3461     hw_breakpoint[nb_hw_breakpoint].type = type;
3462     nb_hw_breakpoint++;
3463
3464     return 0;
3465 }
3466
3467 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3468                                   target_ulong len, int type)
3469 {
3470     int n;
3471
3472     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3473     if (n < 0) {
3474         return -ENOENT;
3475     }
3476     nb_hw_breakpoint--;
3477     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3478
3479     return 0;
3480 }
3481
3482 void kvm_arch_remove_all_hw_breakpoints(void)
3483 {
3484     nb_hw_breakpoint = 0;
3485 }
3486
3487 static CPUWatchpoint hw_watchpoint;
3488
3489 static int kvm_handle_debug(X86CPU *cpu,
3490                             struct kvm_debug_exit_arch *arch_info)
3491 {
3492     CPUState *cs = CPU(cpu);
3493     CPUX86State *env = &cpu->env;
3494     int ret = 0;
3495     int n;
3496
3497     if (arch_info->exception == 1) {
3498         if (arch_info->dr6 & (1 << 14)) {
3499             if (cs->singlestep_enabled) {
3500                 ret = EXCP_DEBUG;
3501             }
3502         } else {
3503             for (n = 0; n < 4; n++) {
3504                 if (arch_info->dr6 & (1 << n)) {
3505                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3506                     case 0x0:
3507                         ret = EXCP_DEBUG;
3508                         break;
3509                     case 0x1:
3510                         ret = EXCP_DEBUG;
3511                         cs->watchpoint_hit = &hw_watchpoint;
3512                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3513                         hw_watchpoint.flags = BP_MEM_WRITE;
3514                         break;
3515                     case 0x3:
3516                         ret = EXCP_DEBUG;
3517                         cs->watchpoint_hit = &hw_watchpoint;
3518                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3519                         hw_watchpoint.flags = BP_MEM_ACCESS;
3520                         break;
3521                     }
3522                 }
3523             }
3524         }
3525     } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3526         ret = EXCP_DEBUG;
3527     }
3528     if (ret == 0) {
3529         cpu_synchronize_state(cs);
3530         assert(env->exception_injected == -1);
3531
3532         /* pass to guest */
3533         env->exception_injected = arch_info->exception;
3534         env->has_error_code = 0;
3535     }
3536
3537     return ret;
3538 }
3539
3540 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3541 {
3542     const uint8_t type_code[] = {
3543         [GDB_BREAKPOINT_HW] = 0x0,
3544         [GDB_WATCHPOINT_WRITE] = 0x1,
3545         [GDB_WATCHPOINT_ACCESS] = 0x3
3546     };
3547     const uint8_t len_code[] = {
3548         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3549     };
3550     int n;
3551
3552     if (kvm_sw_breakpoints_active(cpu)) {
3553         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3554     }
3555     if (nb_hw_breakpoint > 0) {
3556         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3557         dbg->arch.debugreg[7] = 0x0600;
3558         for (n = 0; n < nb_hw_breakpoint; n++) {
3559             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3560             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3561                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3562                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3563         }
3564     }
3565 }
3566
3567 static bool host_supports_vmx(void)
3568 {
3569     uint32_t ecx, unused;
3570
3571     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3572     return ecx & CPUID_EXT_VMX;
3573 }
3574
3575 #define VMX_INVALID_GUEST_STATE 0x80000021
3576
3577 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3578 {
3579     X86CPU *cpu = X86_CPU(cs);
3580     uint64_t code;
3581     int ret;
3582
3583     switch (run->exit_reason) {
3584     case KVM_EXIT_HLT:
3585         DPRINTF("handle_hlt\n");
3586         qemu_mutex_lock_iothread();
3587         ret = kvm_handle_halt(cpu);
3588         qemu_mutex_unlock_iothread();
3589         break;
3590     case KVM_EXIT_SET_TPR:
3591         ret = 0;
3592         break;
3593     case KVM_EXIT_TPR_ACCESS:
3594         qemu_mutex_lock_iothread();
3595         ret = kvm_handle_tpr_access(cpu);
3596         qemu_mutex_unlock_iothread();
3597         break;
3598     case KVM_EXIT_FAIL_ENTRY:
3599         code = run->fail_entry.hardware_entry_failure_reason;
3600         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3601                 code);
3602         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3603             fprintf(stderr,
3604                     "\nIf you're running a guest on an Intel machine without "
3605                         "unrestricted mode\n"
3606                     "support, the failure can be most likely due to the guest "
3607                         "entering an invalid\n"
3608                     "state for Intel VT. For example, the guest maybe running "
3609                         "in big real mode\n"
3610                     "which is not supported on less recent Intel processors."
3611                         "\n\n");
3612         }
3613         ret = -1;
3614         break;
3615     case KVM_EXIT_EXCEPTION:
3616         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3617                 run->ex.exception, run->ex.error_code);
3618         ret = -1;
3619         break;
3620     case KVM_EXIT_DEBUG:
3621         DPRINTF("kvm_exit_debug\n");
3622         qemu_mutex_lock_iothread();
3623         ret = kvm_handle_debug(cpu, &run->debug.arch);
3624         qemu_mutex_unlock_iothread();
3625         break;
3626     case KVM_EXIT_HYPERV:
3627         ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3628         break;
3629     case KVM_EXIT_IOAPIC_EOI:
3630         ioapic_eoi_broadcast(run->eoi.vector);
3631         ret = 0;
3632         break;
3633     default:
3634         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3635         ret = -1;
3636         break;
3637     }
3638
3639     return ret;
3640 }
3641
3642 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3643 {
3644     X86CPU *cpu = X86_CPU(cs);
3645     CPUX86State *env = &cpu->env;
3646
3647     kvm_cpu_synchronize_state(cs);
3648     return !(env->cr[0] & CR0_PE_MASK) ||
3649            ((env->segs[R_CS].selector  & 3) != 3);
3650 }
3651
3652 void kvm_arch_init_irq_routing(KVMState *s)
3653 {
3654     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3655         /* If kernel can't do irq routing, interrupt source
3656          * override 0->2 cannot be set up as required by HPET.
3657          * So we have to disable it.
3658          */
3659         no_hpet = 1;
3660     }
3661     /* We know at this point that we're using the in-kernel
3662      * irqchip, so we can use irqfds, and on x86 we know
3663      * we can use msi via irqfd and GSI routing.
3664      */
3665     kvm_msi_via_irqfd_allowed = true;
3666     kvm_gsi_routing_allowed = true;
3667
3668     if (kvm_irqchip_is_split()) {
3669         int i;
3670
3671         /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3672            MSI routes for signaling interrupts to the local apics. */
3673         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3674             if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3675                 error_report("Could not enable split IRQ mode.");
3676                 exit(1);
3677             }
3678         }
3679     }
3680 }
3681
3682 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3683 {
3684     int ret;
3685     if (machine_kernel_irqchip_split(ms)) {
3686         ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3687         if (ret) {
3688             error_report("Could not enable split irqchip mode: %s",
3689                          strerror(-ret));
3690             exit(1);
3691         } else {
3692             DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3693             kvm_split_irqchip = true;
3694             return 1;
3695         }
3696     } else {
3697         return 0;
3698     }
3699 }
3700
3701 /* Classic KVM device assignment interface. Will remain x86 only. */
3702 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3703                           uint32_t flags, uint32_t *dev_id)
3704 {
3705     struct kvm_assigned_pci_dev dev_data = {
3706         .segnr = dev_addr->domain,
3707         .busnr = dev_addr->bus,
3708         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3709         .flags = flags,
3710     };
3711     int ret;
3712
3713     dev_data.assigned_dev_id =
3714         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3715
3716     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3717     if (ret < 0) {
3718         return ret;
3719     }
3720
3721     *dev_id = dev_data.assigned_dev_id;
3722
3723     return 0;
3724 }
3725
3726 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3727 {
3728     struct kvm_assigned_pci_dev dev_data = {
3729         .assigned_dev_id = dev_id,
3730     };
3731
3732     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3733 }
3734
3735 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3736                                    uint32_t irq_type, uint32_t guest_irq)
3737 {
3738     struct kvm_assigned_irq assigned_irq = {
3739         .assigned_dev_id = dev_id,
3740         .guest_irq = guest_irq,
3741         .flags = irq_type,
3742     };
3743
3744     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3745         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3746     } else {
3747         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3748     }
3749 }
3750
3751 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3752                            uint32_t guest_irq)
3753 {
3754     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3755         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3756
3757     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3758 }
3759
3760 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3761 {
3762     struct kvm_assigned_pci_dev dev_data = {
3763         .assigned_dev_id = dev_id,
3764         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3765     };
3766
3767     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3768 }
3769
3770 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3771                                      uint32_t type)
3772 {
3773     struct kvm_assigned_irq assigned_irq = {
3774         .assigned_dev_id = dev_id,
3775         .flags = type,
3776     };
3777
3778     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3779 }
3780
3781 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3782 {
3783     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3784         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3785 }
3786
3787 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3788 {
3789     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3790                                               KVM_DEV_IRQ_GUEST_MSI, virq);
3791 }
3792
3793 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3794 {
3795     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3796                                                 KVM_DEV_IRQ_HOST_MSI);
3797 }
3798
3799 bool kvm_device_msix_supported(KVMState *s)
3800 {
3801     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3802      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3803     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3804 }
3805
3806 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3807                                  uint32_t nr_vectors)
3808 {
3809     struct kvm_assigned_msix_nr msix_nr = {
3810         .assigned_dev_id = dev_id,
3811         .entry_nr = nr_vectors,
3812     };
3813
3814     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3815 }
3816
3817 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3818                                int virq)
3819 {
3820     struct kvm_assigned_msix_entry msix_entry = {
3821         .assigned_dev_id = dev_id,
3822         .gsi = virq,
3823         .entry = vector,
3824     };
3825
3826     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3827 }
3828
3829 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3830 {
3831     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3832                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
3833 }
3834
3835 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3836 {
3837     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3838                                                 KVM_DEV_IRQ_HOST_MSIX);
3839 }
3840
3841 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3842                              uint64_t address, uint32_t data, PCIDevice *dev)
3843 {
3844     X86IOMMUState *iommu = x86_iommu_get_default();
3845
3846     if (iommu) {
3847         int ret;
3848         MSIMessage src, dst;
3849         X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3850
3851         if (!class->int_remap) {
3852             return 0;
3853         }
3854
3855         src.address = route->u.msi.address_hi;
3856         src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3857         src.address |= route->u.msi.address_lo;
3858         src.data = route->u.msi.data;
3859
3860         ret = class->int_remap(iommu, &src, &dst, dev ? \
3861                                pci_requester_id(dev) : \
3862                                X86_IOMMU_SID_INVALID);
3863         if (ret) {
3864             trace_kvm_x86_fixup_msi_error(route->gsi);
3865             return 1;
3866         }
3867
3868         route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3869         route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3870         route->u.msi.data = dst.data;
3871     }
3872
3873     return 0;
3874 }
3875
3876 typedef struct MSIRouteEntry MSIRouteEntry;
3877
3878 struct MSIRouteEntry {
3879     PCIDevice *dev;             /* Device pointer */
3880     int vector;                 /* MSI/MSIX vector index */
3881     int virq;                   /* Virtual IRQ index */
3882     QLIST_ENTRY(MSIRouteEntry) list;
3883 };
3884
3885 /* List of used GSI routes */
3886 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3887     QLIST_HEAD_INITIALIZER(msi_route_list);
3888
3889 static void kvm_update_msi_routes_all(void *private, bool global,
3890                                       uint32_t index, uint32_t mask)
3891 {
3892     int cnt = 0;
3893     MSIRouteEntry *entry;
3894     MSIMessage msg;
3895     PCIDevice *dev;
3896
3897     /* TODO: explicit route update */
3898     QLIST_FOREACH(entry, &msi_route_list, list) {
3899         cnt++;
3900         dev = entry->dev;
3901         if (!msix_enabled(dev) && !msi_enabled(dev)) {
3902             continue;
3903         }
3904         msg = pci_get_msi_message(dev, entry->vector);
3905         kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3906     }
3907     kvm_irqchip_commit_routes(kvm_state);
3908     trace_kvm_x86_update_msi_routes(cnt);
3909 }
3910
3911 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3912                                 int vector, PCIDevice *dev)
3913 {
3914     static bool notify_list_inited = false;
3915     MSIRouteEntry *entry;
3916
3917     if (!dev) {
3918         /* These are (possibly) IOAPIC routes only used for split
3919          * kernel irqchip mode, while what we are housekeeping are
3920          * PCI devices only. */
3921         return 0;
3922     }
3923
3924     entry = g_new0(MSIRouteEntry, 1);
3925     entry->dev = dev;
3926     entry->vector = vector;
3927     entry->virq = route->gsi;
3928     QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3929
3930     trace_kvm_x86_add_msi_route(route->gsi);
3931
3932     if (!notify_list_inited) {
3933         /* For the first time we do add route, add ourselves into
3934          * IOMMU's IEC notify list if needed. */
3935         X86IOMMUState *iommu = x86_iommu_get_default();
3936         if (iommu) {
3937             x86_iommu_iec_register_notifier(iommu,
3938                                             kvm_update_msi_routes_all,
3939                                             NULL);
3940         }
3941         notify_list_inited = true;
3942     }
3943     return 0;
3944 }
3945
3946 int kvm_arch_release_virq_post(int virq)
3947 {
3948     MSIRouteEntry *entry, *next;
3949     QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3950         if (entry->virq == virq) {
3951             trace_kvm_x86_remove_msi_route(virq);
3952             QLIST_REMOVE(entry, list);
3953             g_free(entry);
3954             break;
3955         }
3956     }
3957     return 0;
3958 }
3959
3960 int kvm_arch_msi_data_to_gsi(uint32_t data)
3961 {
3962     abort();
3963 }