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Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170124b' into...
[mirror_qemu.git] / target / i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30
31 #include "exec/gdbstub.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/config-file.h"
34 #include "qemu/error-report.h"
35 #include "hw/i386/pc.h"
36 #include "hw/i386/apic.h"
37 #include "hw/i386/apic_internal.h"
38 #include "hw/i386/apic-msidef.h"
39 #include "hw/i386/intel_iommu.h"
40 #include "hw/i386/x86-iommu.h"
41
42 #include "exec/ioport.h"
43 #include "standard-headers/asm-x86/hyperv.h"
44 #include "hw/pci/pci.h"
45 #include "hw/pci/msi.h"
46 #include "migration/migration.h"
47 #include "exec/memattrs.h"
48 #include "trace.h"
49
50 //#define DEBUG_KVM
51
52 #ifdef DEBUG_KVM
53 #define DPRINTF(fmt, ...) \
54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55 #else
56 #define DPRINTF(fmt, ...) \
57 do { } while (0)
58 #endif
59
60 #define MSR_KVM_WALL_CLOCK 0x11
61 #define MSR_KVM_SYSTEM_TIME 0x12
62
63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65 #define MSR_BUF_SIZE 4096
66
67 #ifndef BUS_MCEERR_AR
68 #define BUS_MCEERR_AR 4
69 #endif
70 #ifndef BUS_MCEERR_AO
71 #define BUS_MCEERR_AO 5
72 #endif
73
74 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
75 KVM_CAP_INFO(SET_TSS_ADDR),
76 KVM_CAP_INFO(EXT_CPUID),
77 KVM_CAP_INFO(MP_STATE),
78 KVM_CAP_LAST_INFO
79 };
80
81 static bool has_msr_star;
82 static bool has_msr_hsave_pa;
83 static bool has_msr_tsc_aux;
84 static bool has_msr_tsc_adjust;
85 static bool has_msr_tsc_deadline;
86 static bool has_msr_feature_control;
87 static bool has_msr_misc_enable;
88 static bool has_msr_smbase;
89 static bool has_msr_bndcfgs;
90 static int lm_capable_kernel;
91 static bool has_msr_hv_hypercall;
92 static bool has_msr_hv_crash;
93 static bool has_msr_hv_reset;
94 static bool has_msr_hv_vpindex;
95 static bool has_msr_hv_runtime;
96 static bool has_msr_hv_synic;
97 static bool has_msr_hv_stimer;
98 static bool has_msr_xss;
99
100 static bool has_msr_architectural_pmu;
101 static uint32_t num_architectural_pmu_counters;
102
103 static int has_xsave;
104 static int has_xcrs;
105 static int has_pit_state2;
106
107 static bool has_msr_mcg_ext_ctl;
108
109 static struct kvm_cpuid2 *cpuid_cache;
110
111 int kvm_has_pit_state2(void)
112 {
113 return has_pit_state2;
114 }
115
116 bool kvm_has_smm(void)
117 {
118 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
119 }
120
121 bool kvm_has_adjust_clock_stable(void)
122 {
123 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
124
125 return (ret == KVM_CLOCK_TSC_STABLE);
126 }
127
128 bool kvm_allows_irq0_override(void)
129 {
130 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
131 }
132
133 static bool kvm_x2apic_api_set_flags(uint64_t flags)
134 {
135 KVMState *s = KVM_STATE(current_machine->accelerator);
136
137 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
138 }
139
140 #define MEMORIZE(fn, _result) \
141 ({ \
142 static bool _memorized; \
143 \
144 if (_memorized) { \
145 return _result; \
146 } \
147 _memorized = true; \
148 _result = fn; \
149 })
150
151 static bool has_x2apic_api;
152
153 bool kvm_has_x2apic_api(void)
154 {
155 return has_x2apic_api;
156 }
157
158 bool kvm_enable_x2apic(void)
159 {
160 return MEMORIZE(
161 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
162 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
163 has_x2apic_api);
164 }
165
166 static int kvm_get_tsc(CPUState *cs)
167 {
168 X86CPU *cpu = X86_CPU(cs);
169 CPUX86State *env = &cpu->env;
170 struct {
171 struct kvm_msrs info;
172 struct kvm_msr_entry entries[1];
173 } msr_data;
174 int ret;
175
176 if (env->tsc_valid) {
177 return 0;
178 }
179
180 msr_data.info.nmsrs = 1;
181 msr_data.entries[0].index = MSR_IA32_TSC;
182 env->tsc_valid = !runstate_is_running();
183
184 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
185 if (ret < 0) {
186 return ret;
187 }
188
189 assert(ret == 1);
190 env->tsc = msr_data.entries[0].data;
191 return 0;
192 }
193
194 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
195 {
196 kvm_get_tsc(cpu);
197 }
198
199 void kvm_synchronize_all_tsc(void)
200 {
201 CPUState *cpu;
202
203 if (kvm_enabled()) {
204 CPU_FOREACH(cpu) {
205 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
206 }
207 }
208 }
209
210 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
211 {
212 struct kvm_cpuid2 *cpuid;
213 int r, size;
214
215 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
216 cpuid = g_malloc0(size);
217 cpuid->nent = max;
218 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
219 if (r == 0 && cpuid->nent >= max) {
220 r = -E2BIG;
221 }
222 if (r < 0) {
223 if (r == -E2BIG) {
224 g_free(cpuid);
225 return NULL;
226 } else {
227 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
228 strerror(-r));
229 exit(1);
230 }
231 }
232 return cpuid;
233 }
234
235 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
236 * for all entries.
237 */
238 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
239 {
240 struct kvm_cpuid2 *cpuid;
241 int max = 1;
242
243 if (cpuid_cache != NULL) {
244 return cpuid_cache;
245 }
246 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
247 max *= 2;
248 }
249 cpuid_cache = cpuid;
250 return cpuid;
251 }
252
253 static const struct kvm_para_features {
254 int cap;
255 int feature;
256 } para_features[] = {
257 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
258 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
259 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
260 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
261 };
262
263 static int get_para_features(KVMState *s)
264 {
265 int i, features = 0;
266
267 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
268 if (kvm_check_extension(s, para_features[i].cap)) {
269 features |= (1 << para_features[i].feature);
270 }
271 }
272
273 return features;
274 }
275
276
277 /* Returns the value for a specific register on the cpuid entry
278 */
279 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
280 {
281 uint32_t ret = 0;
282 switch (reg) {
283 case R_EAX:
284 ret = entry->eax;
285 break;
286 case R_EBX:
287 ret = entry->ebx;
288 break;
289 case R_ECX:
290 ret = entry->ecx;
291 break;
292 case R_EDX:
293 ret = entry->edx;
294 break;
295 }
296 return ret;
297 }
298
299 /* Find matching entry for function/index on kvm_cpuid2 struct
300 */
301 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
302 uint32_t function,
303 uint32_t index)
304 {
305 int i;
306 for (i = 0; i < cpuid->nent; ++i) {
307 if (cpuid->entries[i].function == function &&
308 cpuid->entries[i].index == index) {
309 return &cpuid->entries[i];
310 }
311 }
312 /* not found: */
313 return NULL;
314 }
315
316 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
317 uint32_t index, int reg)
318 {
319 struct kvm_cpuid2 *cpuid;
320 uint32_t ret = 0;
321 uint32_t cpuid_1_edx;
322 bool found = false;
323
324 cpuid = get_supported_cpuid(s);
325
326 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
327 if (entry) {
328 found = true;
329 ret = cpuid_entry_get_reg(entry, reg);
330 }
331
332 /* Fixups for the data returned by KVM, below */
333
334 if (function == 1 && reg == R_EDX) {
335 /* KVM before 2.6.30 misreports the following features */
336 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
337 } else if (function == 1 && reg == R_ECX) {
338 /* We can set the hypervisor flag, even if KVM does not return it on
339 * GET_SUPPORTED_CPUID
340 */
341 ret |= CPUID_EXT_HYPERVISOR;
342 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
343 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
344 * and the irqchip is in the kernel.
345 */
346 if (kvm_irqchip_in_kernel() &&
347 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
348 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
349 }
350
351 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
352 * without the in-kernel irqchip
353 */
354 if (!kvm_irqchip_in_kernel()) {
355 ret &= ~CPUID_EXT_X2APIC;
356 }
357 } else if (function == 6 && reg == R_EAX) {
358 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
359 } else if (function == 0x80000001 && reg == R_EDX) {
360 /* On Intel, kvm returns cpuid according to the Intel spec,
361 * so add missing bits according to the AMD spec:
362 */
363 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
364 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
365 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
366 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
367 * be enabled without the in-kernel irqchip
368 */
369 if (!kvm_irqchip_in_kernel()) {
370 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
371 }
372 }
373
374 /* fallback for older kernels */
375 if ((function == KVM_CPUID_FEATURES) && !found) {
376 ret = get_para_features(s);
377 }
378
379 return ret;
380 }
381
382 typedef struct HWPoisonPage {
383 ram_addr_t ram_addr;
384 QLIST_ENTRY(HWPoisonPage) list;
385 } HWPoisonPage;
386
387 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
388 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
389
390 static void kvm_unpoison_all(void *param)
391 {
392 HWPoisonPage *page, *next_page;
393
394 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
395 QLIST_REMOVE(page, list);
396 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
397 g_free(page);
398 }
399 }
400
401 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
402 {
403 HWPoisonPage *page;
404
405 QLIST_FOREACH(page, &hwpoison_page_list, list) {
406 if (page->ram_addr == ram_addr) {
407 return;
408 }
409 }
410 page = g_new(HWPoisonPage, 1);
411 page->ram_addr = ram_addr;
412 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
413 }
414
415 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
416 int *max_banks)
417 {
418 int r;
419
420 r = kvm_check_extension(s, KVM_CAP_MCE);
421 if (r > 0) {
422 *max_banks = r;
423 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
424 }
425 return -ENOSYS;
426 }
427
428 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
429 {
430 CPUState *cs = CPU(cpu);
431 CPUX86State *env = &cpu->env;
432 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
433 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
434 uint64_t mcg_status = MCG_STATUS_MCIP;
435 int flags = 0;
436
437 if (code == BUS_MCEERR_AR) {
438 status |= MCI_STATUS_AR | 0x134;
439 mcg_status |= MCG_STATUS_EIPV;
440 } else {
441 status |= 0xc0;
442 mcg_status |= MCG_STATUS_RIPV;
443 }
444
445 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
446 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
447 * guest kernel back into env->mcg_ext_ctl.
448 */
449 cpu_synchronize_state(cs);
450 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
451 mcg_status |= MCG_STATUS_LMCE;
452 flags = 0;
453 }
454
455 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
456 (MCM_ADDR_PHYS << 6) | 0xc, flags);
457 }
458
459 static void hardware_memory_error(void)
460 {
461 fprintf(stderr, "Hardware memory error!\n");
462 exit(1);
463 }
464
465 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
466 {
467 X86CPU *cpu = X86_CPU(c);
468 CPUX86State *env = &cpu->env;
469 ram_addr_t ram_addr;
470 hwaddr paddr;
471
472 if ((env->mcg_cap & MCG_SER_P) && addr
473 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
474 ram_addr = qemu_ram_addr_from_host(addr);
475 if (ram_addr == RAM_ADDR_INVALID ||
476 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
477 fprintf(stderr, "Hardware memory error for memory used by "
478 "QEMU itself instead of guest system!\n");
479 /* Hope we are lucky for AO MCE */
480 if (code == BUS_MCEERR_AO) {
481 return 0;
482 } else {
483 hardware_memory_error();
484 }
485 }
486 kvm_hwpoison_page_add(ram_addr);
487 kvm_mce_inject(cpu, paddr, code);
488 } else {
489 if (code == BUS_MCEERR_AO) {
490 return 0;
491 } else if (code == BUS_MCEERR_AR) {
492 hardware_memory_error();
493 } else {
494 return 1;
495 }
496 }
497 return 0;
498 }
499
500 int kvm_arch_on_sigbus(int code, void *addr)
501 {
502 X86CPU *cpu = X86_CPU(first_cpu);
503
504 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
505 ram_addr_t ram_addr;
506 hwaddr paddr;
507
508 /* Hope we are lucky for AO MCE */
509 ram_addr = qemu_ram_addr_from_host(addr);
510 if (ram_addr == RAM_ADDR_INVALID ||
511 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
512 addr, &paddr)) {
513 fprintf(stderr, "Hardware memory error for memory used by "
514 "QEMU itself instead of guest system!: %p\n", addr);
515 return 0;
516 }
517 kvm_hwpoison_page_add(ram_addr);
518 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
519 } else {
520 if (code == BUS_MCEERR_AO) {
521 return 0;
522 } else if (code == BUS_MCEERR_AR) {
523 hardware_memory_error();
524 } else {
525 return 1;
526 }
527 }
528 return 0;
529 }
530
531 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
532 {
533 CPUX86State *env = &cpu->env;
534
535 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
536 unsigned int bank, bank_num = env->mcg_cap & 0xff;
537 struct kvm_x86_mce mce;
538
539 env->exception_injected = -1;
540
541 /*
542 * There must be at least one bank in use if an MCE is pending.
543 * Find it and use its values for the event injection.
544 */
545 for (bank = 0; bank < bank_num; bank++) {
546 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
547 break;
548 }
549 }
550 assert(bank < bank_num);
551
552 mce.bank = bank;
553 mce.status = env->mce_banks[bank * 4 + 1];
554 mce.mcg_status = env->mcg_status;
555 mce.addr = env->mce_banks[bank * 4 + 2];
556 mce.misc = env->mce_banks[bank * 4 + 3];
557
558 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
559 }
560 return 0;
561 }
562
563 static void cpu_update_state(void *opaque, int running, RunState state)
564 {
565 CPUX86State *env = opaque;
566
567 if (running) {
568 env->tsc_valid = false;
569 }
570 }
571
572 unsigned long kvm_arch_vcpu_id(CPUState *cs)
573 {
574 X86CPU *cpu = X86_CPU(cs);
575 return cpu->apic_id;
576 }
577
578 #ifndef KVM_CPUID_SIGNATURE_NEXT
579 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
580 #endif
581
582 static bool hyperv_hypercall_available(X86CPU *cpu)
583 {
584 return cpu->hyperv_vapic ||
585 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
586 }
587
588 static bool hyperv_enabled(X86CPU *cpu)
589 {
590 CPUState *cs = CPU(cpu);
591 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
592 (hyperv_hypercall_available(cpu) ||
593 cpu->hyperv_time ||
594 cpu->hyperv_relaxed_timing ||
595 cpu->hyperv_crash ||
596 cpu->hyperv_reset ||
597 cpu->hyperv_vpindex ||
598 cpu->hyperv_runtime ||
599 cpu->hyperv_synic ||
600 cpu->hyperv_stimer);
601 }
602
603 static int kvm_arch_set_tsc_khz(CPUState *cs)
604 {
605 X86CPU *cpu = X86_CPU(cs);
606 CPUX86State *env = &cpu->env;
607 int r;
608
609 if (!env->tsc_khz) {
610 return 0;
611 }
612
613 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
614 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
615 -ENOTSUP;
616 if (r < 0) {
617 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
618 * TSC frequency doesn't match the one we want.
619 */
620 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
621 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
622 -ENOTSUP;
623 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
624 error_report("warning: TSC frequency mismatch between "
625 "VM (%" PRId64 " kHz) and host (%d kHz), "
626 "and TSC scaling unavailable",
627 env->tsc_khz, cur_freq);
628 return r;
629 }
630 }
631
632 return 0;
633 }
634
635 static int hyperv_handle_properties(CPUState *cs)
636 {
637 X86CPU *cpu = X86_CPU(cs);
638 CPUX86State *env = &cpu->env;
639
640 if (cpu->hyperv_time &&
641 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
642 cpu->hyperv_time = false;
643 }
644
645 if (cpu->hyperv_relaxed_timing) {
646 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
647 }
648 if (cpu->hyperv_vapic) {
649 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
650 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
651 }
652 if (cpu->hyperv_time) {
653 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
654 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
655 env->features[FEAT_HYPERV_EAX] |= 0x200;
656 }
657 if (cpu->hyperv_crash && has_msr_hv_crash) {
658 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
659 }
660 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
661 if (cpu->hyperv_reset && has_msr_hv_reset) {
662 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
663 }
664 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
665 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
666 }
667 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
668 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
669 }
670 if (cpu->hyperv_synic) {
671 int sint;
672
673 if (!has_msr_hv_synic ||
674 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
675 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
676 return -ENOSYS;
677 }
678
679 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
680 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
681 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
682 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
683 }
684 }
685 if (cpu->hyperv_stimer) {
686 if (!has_msr_hv_stimer) {
687 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
688 return -ENOSYS;
689 }
690 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
691 }
692 return 0;
693 }
694
695 static Error *invtsc_mig_blocker;
696
697 #define KVM_MAX_CPUID_ENTRIES 100
698
699 int kvm_arch_init_vcpu(CPUState *cs)
700 {
701 struct {
702 struct kvm_cpuid2 cpuid;
703 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
704 } QEMU_PACKED cpuid_data;
705 X86CPU *cpu = X86_CPU(cs);
706 CPUX86State *env = &cpu->env;
707 uint32_t limit, i, j, cpuid_i;
708 uint32_t unused;
709 struct kvm_cpuid_entry2 *c;
710 uint32_t signature[3];
711 int kvm_base = KVM_CPUID_SIGNATURE;
712 int r;
713 Error *local_err = NULL;
714
715 memset(&cpuid_data, 0, sizeof(cpuid_data));
716
717 cpuid_i = 0;
718
719 /* Paravirtualization CPUIDs */
720 if (hyperv_enabled(cpu)) {
721 c = &cpuid_data.entries[cpuid_i++];
722 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
723 if (!cpu->hyperv_vendor_id) {
724 memcpy(signature, "Microsoft Hv", 12);
725 } else {
726 size_t len = strlen(cpu->hyperv_vendor_id);
727
728 if (len > 12) {
729 error_report("hv-vendor-id truncated to 12 characters");
730 len = 12;
731 }
732 memset(signature, 0, 12);
733 memcpy(signature, cpu->hyperv_vendor_id, len);
734 }
735 c->eax = HYPERV_CPUID_MIN;
736 c->ebx = signature[0];
737 c->ecx = signature[1];
738 c->edx = signature[2];
739
740 c = &cpuid_data.entries[cpuid_i++];
741 c->function = HYPERV_CPUID_INTERFACE;
742 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
743 c->eax = signature[0];
744 c->ebx = 0;
745 c->ecx = 0;
746 c->edx = 0;
747
748 c = &cpuid_data.entries[cpuid_i++];
749 c->function = HYPERV_CPUID_VERSION;
750 c->eax = 0x00001bbc;
751 c->ebx = 0x00060001;
752
753 c = &cpuid_data.entries[cpuid_i++];
754 c->function = HYPERV_CPUID_FEATURES;
755 r = hyperv_handle_properties(cs);
756 if (r) {
757 return r;
758 }
759 c->eax = env->features[FEAT_HYPERV_EAX];
760 c->ebx = env->features[FEAT_HYPERV_EBX];
761 c->edx = env->features[FEAT_HYPERV_EDX];
762
763 c = &cpuid_data.entries[cpuid_i++];
764 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
765 if (cpu->hyperv_relaxed_timing) {
766 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
767 }
768 if (cpu->hyperv_vapic) {
769 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
770 }
771 c->ebx = cpu->hyperv_spinlock_attempts;
772
773 c = &cpuid_data.entries[cpuid_i++];
774 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
775 c->eax = 0x40;
776 c->ebx = 0x40;
777
778 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
779 has_msr_hv_hypercall = true;
780 }
781
782 if (cpu->expose_kvm) {
783 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
784 c = &cpuid_data.entries[cpuid_i++];
785 c->function = KVM_CPUID_SIGNATURE | kvm_base;
786 c->eax = KVM_CPUID_FEATURES | kvm_base;
787 c->ebx = signature[0];
788 c->ecx = signature[1];
789 c->edx = signature[2];
790
791 c = &cpuid_data.entries[cpuid_i++];
792 c->function = KVM_CPUID_FEATURES | kvm_base;
793 c->eax = env->features[FEAT_KVM];
794 }
795
796 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
797
798 for (i = 0; i <= limit; i++) {
799 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
800 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
801 abort();
802 }
803 c = &cpuid_data.entries[cpuid_i++];
804
805 switch (i) {
806 case 2: {
807 /* Keep reading function 2 till all the input is received */
808 int times;
809
810 c->function = i;
811 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
812 KVM_CPUID_FLAG_STATE_READ_NEXT;
813 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
814 times = c->eax & 0xff;
815
816 for (j = 1; j < times; ++j) {
817 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
818 fprintf(stderr, "cpuid_data is full, no space for "
819 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
820 abort();
821 }
822 c = &cpuid_data.entries[cpuid_i++];
823 c->function = i;
824 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
825 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
826 }
827 break;
828 }
829 case 4:
830 case 0xb:
831 case 0xd:
832 for (j = 0; ; j++) {
833 if (i == 0xd && j == 64) {
834 break;
835 }
836 c->function = i;
837 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
838 c->index = j;
839 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
840
841 if (i == 4 && c->eax == 0) {
842 break;
843 }
844 if (i == 0xb && !(c->ecx & 0xff00)) {
845 break;
846 }
847 if (i == 0xd && c->eax == 0) {
848 continue;
849 }
850 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
851 fprintf(stderr, "cpuid_data is full, no space for "
852 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
853 abort();
854 }
855 c = &cpuid_data.entries[cpuid_i++];
856 }
857 break;
858 default:
859 c->function = i;
860 c->flags = 0;
861 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
862 break;
863 }
864 }
865
866 if (limit >= 0x0a) {
867 uint32_t ver;
868
869 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
870 if ((ver & 0xff) > 0) {
871 has_msr_architectural_pmu = true;
872 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
873
874 /* Shouldn't be more than 32, since that's the number of bits
875 * available in EBX to tell us _which_ counters are available.
876 * Play it safe.
877 */
878 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
879 num_architectural_pmu_counters = MAX_GP_COUNTERS;
880 }
881 }
882 }
883
884 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
885
886 for (i = 0x80000000; i <= limit; i++) {
887 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
888 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
889 abort();
890 }
891 c = &cpuid_data.entries[cpuid_i++];
892
893 c->function = i;
894 c->flags = 0;
895 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
896 }
897
898 /* Call Centaur's CPUID instructions they are supported. */
899 if (env->cpuid_xlevel2 > 0) {
900 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
901
902 for (i = 0xC0000000; i <= limit; i++) {
903 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
904 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
905 abort();
906 }
907 c = &cpuid_data.entries[cpuid_i++];
908
909 c->function = i;
910 c->flags = 0;
911 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
912 }
913 }
914
915 cpuid_data.cpuid.nent = cpuid_i;
916
917 if (((env->cpuid_version >> 8)&0xF) >= 6
918 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
919 (CPUID_MCE | CPUID_MCA)
920 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
921 uint64_t mcg_cap, unsupported_caps;
922 int banks;
923 int ret;
924
925 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
926 if (ret < 0) {
927 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
928 return ret;
929 }
930
931 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
932 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
933 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
934 return -ENOTSUP;
935 }
936
937 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
938 if (unsupported_caps) {
939 if (unsupported_caps & MCG_LMCE_P) {
940 error_report("kvm: LMCE not supported");
941 return -ENOTSUP;
942 }
943 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
944 unsupported_caps);
945 }
946
947 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
948 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
949 if (ret < 0) {
950 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
951 return ret;
952 }
953 }
954
955 qemu_add_vm_change_state_handler(cpu_update_state, env);
956
957 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
958 if (c) {
959 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
960 !!(c->ecx & CPUID_EXT_SMX);
961 }
962
963 if (env->mcg_cap & MCG_LMCE_P) {
964 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
965 }
966
967 if (!env->user_tsc_khz) {
968 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
969 invtsc_mig_blocker == NULL) {
970 /* for migration */
971 error_setg(&invtsc_mig_blocker,
972 "State blocked by non-migratable CPU device"
973 " (invtsc flag)");
974 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
975 if (local_err) {
976 error_report_err(local_err);
977 error_free(invtsc_mig_blocker);
978 goto fail;
979 }
980 /* for savevm */
981 vmstate_x86_cpu.unmigratable = 1;
982 }
983 }
984
985 cpuid_data.cpuid.padding = 0;
986 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
987 if (r) {
988 goto fail;
989 }
990
991 r = kvm_arch_set_tsc_khz(cs);
992 if (r < 0) {
993 goto fail;
994 }
995
996 /* vcpu's TSC frequency is either specified by user, or following
997 * the value used by KVM if the former is not present. In the
998 * latter case, we query it from KVM and record in env->tsc_khz,
999 * so that vcpu's TSC frequency can be migrated later via this field.
1000 */
1001 if (!env->tsc_khz) {
1002 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1003 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1004 -ENOTSUP;
1005 if (r > 0) {
1006 env->tsc_khz = r;
1007 }
1008 }
1009
1010 if (has_xsave) {
1011 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1012 }
1013 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1014
1015 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1016 has_msr_tsc_aux = false;
1017 }
1018
1019 return 0;
1020
1021 fail:
1022 migrate_del_blocker(invtsc_mig_blocker);
1023 return r;
1024 }
1025
1026 void kvm_arch_reset_vcpu(X86CPU *cpu)
1027 {
1028 CPUX86State *env = &cpu->env;
1029
1030 env->exception_injected = -1;
1031 env->interrupt_injected = -1;
1032 env->xcr0 = 1;
1033 if (kvm_irqchip_in_kernel()) {
1034 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1035 KVM_MP_STATE_UNINITIALIZED;
1036 } else {
1037 env->mp_state = KVM_MP_STATE_RUNNABLE;
1038 }
1039 }
1040
1041 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1042 {
1043 CPUX86State *env = &cpu->env;
1044
1045 /* APs get directly into wait-for-SIPI state. */
1046 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1047 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1048 }
1049 }
1050
1051 static int kvm_get_supported_msrs(KVMState *s)
1052 {
1053 static int kvm_supported_msrs;
1054 int ret = 0;
1055
1056 /* first time */
1057 if (kvm_supported_msrs == 0) {
1058 struct kvm_msr_list msr_list, *kvm_msr_list;
1059
1060 kvm_supported_msrs = -1;
1061
1062 /* Obtain MSR list from KVM. These are the MSRs that we must
1063 * save/restore */
1064 msr_list.nmsrs = 0;
1065 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1066 if (ret < 0 && ret != -E2BIG) {
1067 return ret;
1068 }
1069 /* Old kernel modules had a bug and could write beyond the provided
1070 memory. Allocate at least a safe amount of 1K. */
1071 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1072 msr_list.nmsrs *
1073 sizeof(msr_list.indices[0])));
1074
1075 kvm_msr_list->nmsrs = msr_list.nmsrs;
1076 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1077 if (ret >= 0) {
1078 int i;
1079
1080 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1081 if (kvm_msr_list->indices[i] == MSR_STAR) {
1082 has_msr_star = true;
1083 continue;
1084 }
1085 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
1086 has_msr_hsave_pa = true;
1087 continue;
1088 }
1089 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1090 has_msr_tsc_aux = true;
1091 continue;
1092 }
1093 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1094 has_msr_tsc_adjust = true;
1095 continue;
1096 }
1097 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1098 has_msr_tsc_deadline = true;
1099 continue;
1100 }
1101 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1102 has_msr_smbase = true;
1103 continue;
1104 }
1105 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1106 has_msr_misc_enable = true;
1107 continue;
1108 }
1109 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1110 has_msr_bndcfgs = true;
1111 continue;
1112 }
1113 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1114 has_msr_xss = true;
1115 continue;
1116 }
1117 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1118 has_msr_hv_crash = true;
1119 continue;
1120 }
1121 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1122 has_msr_hv_reset = true;
1123 continue;
1124 }
1125 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1126 has_msr_hv_vpindex = true;
1127 continue;
1128 }
1129 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1130 has_msr_hv_runtime = true;
1131 continue;
1132 }
1133 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1134 has_msr_hv_synic = true;
1135 continue;
1136 }
1137 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1138 has_msr_hv_stimer = true;
1139 continue;
1140 }
1141 }
1142 }
1143
1144 g_free(kvm_msr_list);
1145 }
1146
1147 return ret;
1148 }
1149
1150 static Notifier smram_machine_done;
1151 static KVMMemoryListener smram_listener;
1152 static AddressSpace smram_address_space;
1153 static MemoryRegion smram_as_root;
1154 static MemoryRegion smram_as_mem;
1155
1156 static void register_smram_listener(Notifier *n, void *unused)
1157 {
1158 MemoryRegion *smram =
1159 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1160
1161 /* Outer container... */
1162 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1163 memory_region_set_enabled(&smram_as_root, true);
1164
1165 /* ... with two regions inside: normal system memory with low
1166 * priority, and...
1167 */
1168 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1169 get_system_memory(), 0, ~0ull);
1170 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1171 memory_region_set_enabled(&smram_as_mem, true);
1172
1173 if (smram) {
1174 /* ... SMRAM with higher priority */
1175 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1176 memory_region_set_enabled(smram, true);
1177 }
1178
1179 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1180 kvm_memory_listener_register(kvm_state, &smram_listener,
1181 &smram_address_space, 1);
1182 }
1183
1184 int kvm_arch_init(MachineState *ms, KVMState *s)
1185 {
1186 uint64_t identity_base = 0xfffbc000;
1187 uint64_t shadow_mem;
1188 int ret;
1189 struct utsname utsname;
1190
1191 #ifdef KVM_CAP_XSAVE
1192 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1193 #endif
1194
1195 #ifdef KVM_CAP_XCRS
1196 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1197 #endif
1198
1199 #ifdef KVM_CAP_PIT_STATE2
1200 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1201 #endif
1202
1203 ret = kvm_get_supported_msrs(s);
1204 if (ret < 0) {
1205 return ret;
1206 }
1207
1208 uname(&utsname);
1209 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1210
1211 /*
1212 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1213 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1214 * Since these must be part of guest physical memory, we need to allocate
1215 * them, both by setting their start addresses in the kernel and by
1216 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1217 *
1218 * Older KVM versions may not support setting the identity map base. In
1219 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1220 * size.
1221 */
1222 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1223 /* Allows up to 16M BIOSes. */
1224 identity_base = 0xfeffc000;
1225
1226 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1227 if (ret < 0) {
1228 return ret;
1229 }
1230 }
1231
1232 /* Set TSS base one page after EPT identity map. */
1233 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1234 if (ret < 0) {
1235 return ret;
1236 }
1237
1238 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1239 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1240 if (ret < 0) {
1241 fprintf(stderr, "e820_add_entry() table is full\n");
1242 return ret;
1243 }
1244 qemu_register_reset(kvm_unpoison_all, NULL);
1245
1246 shadow_mem = machine_kvm_shadow_mem(ms);
1247 if (shadow_mem != -1) {
1248 shadow_mem /= 4096;
1249 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1250 if (ret < 0) {
1251 return ret;
1252 }
1253 }
1254
1255 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1256 smram_machine_done.notify = register_smram_listener;
1257 qemu_add_machine_init_done_notifier(&smram_machine_done);
1258 }
1259 return 0;
1260 }
1261
1262 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1263 {
1264 lhs->selector = rhs->selector;
1265 lhs->base = rhs->base;
1266 lhs->limit = rhs->limit;
1267 lhs->type = 3;
1268 lhs->present = 1;
1269 lhs->dpl = 3;
1270 lhs->db = 0;
1271 lhs->s = 1;
1272 lhs->l = 0;
1273 lhs->g = 0;
1274 lhs->avl = 0;
1275 lhs->unusable = 0;
1276 }
1277
1278 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1279 {
1280 unsigned flags = rhs->flags;
1281 lhs->selector = rhs->selector;
1282 lhs->base = rhs->base;
1283 lhs->limit = rhs->limit;
1284 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1285 lhs->present = (flags & DESC_P_MASK) != 0;
1286 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1287 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1288 lhs->s = (flags & DESC_S_MASK) != 0;
1289 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1290 lhs->g = (flags & DESC_G_MASK) != 0;
1291 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1292 lhs->unusable = !lhs->present;
1293 lhs->padding = 0;
1294 }
1295
1296 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1297 {
1298 lhs->selector = rhs->selector;
1299 lhs->base = rhs->base;
1300 lhs->limit = rhs->limit;
1301 if (rhs->unusable) {
1302 lhs->flags = 0;
1303 } else {
1304 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1305 (rhs->present * DESC_P_MASK) |
1306 (rhs->dpl << DESC_DPL_SHIFT) |
1307 (rhs->db << DESC_B_SHIFT) |
1308 (rhs->s * DESC_S_MASK) |
1309 (rhs->l << DESC_L_SHIFT) |
1310 (rhs->g * DESC_G_MASK) |
1311 (rhs->avl * DESC_AVL_MASK);
1312 }
1313 }
1314
1315 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1316 {
1317 if (set) {
1318 *kvm_reg = *qemu_reg;
1319 } else {
1320 *qemu_reg = *kvm_reg;
1321 }
1322 }
1323
1324 static int kvm_getput_regs(X86CPU *cpu, int set)
1325 {
1326 CPUX86State *env = &cpu->env;
1327 struct kvm_regs regs;
1328 int ret = 0;
1329
1330 if (!set) {
1331 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1332 if (ret < 0) {
1333 return ret;
1334 }
1335 }
1336
1337 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1338 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1339 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1340 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1341 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1342 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1343 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1344 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1345 #ifdef TARGET_X86_64
1346 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1347 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1348 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1349 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1350 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1351 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1352 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1353 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1354 #endif
1355
1356 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1357 kvm_getput_reg(&regs.rip, &env->eip, set);
1358
1359 if (set) {
1360 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1361 }
1362
1363 return ret;
1364 }
1365
1366 static int kvm_put_fpu(X86CPU *cpu)
1367 {
1368 CPUX86State *env = &cpu->env;
1369 struct kvm_fpu fpu;
1370 int i;
1371
1372 memset(&fpu, 0, sizeof fpu);
1373 fpu.fsw = env->fpus & ~(7 << 11);
1374 fpu.fsw |= (env->fpstt & 7) << 11;
1375 fpu.fcw = env->fpuc;
1376 fpu.last_opcode = env->fpop;
1377 fpu.last_ip = env->fpip;
1378 fpu.last_dp = env->fpdp;
1379 for (i = 0; i < 8; ++i) {
1380 fpu.ftwx |= (!env->fptags[i]) << i;
1381 }
1382 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1383 for (i = 0; i < CPU_NB_REGS; i++) {
1384 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1385 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1386 }
1387 fpu.mxcsr = env->mxcsr;
1388
1389 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1390 }
1391
1392 #define XSAVE_FCW_FSW 0
1393 #define XSAVE_FTW_FOP 1
1394 #define XSAVE_CWD_RIP 2
1395 #define XSAVE_CWD_RDP 4
1396 #define XSAVE_MXCSR 6
1397 #define XSAVE_ST_SPACE 8
1398 #define XSAVE_XMM_SPACE 40
1399 #define XSAVE_XSTATE_BV 128
1400 #define XSAVE_YMMH_SPACE 144
1401 #define XSAVE_BNDREGS 240
1402 #define XSAVE_BNDCSR 256
1403 #define XSAVE_OPMASK 272
1404 #define XSAVE_ZMM_Hi256 288
1405 #define XSAVE_Hi16_ZMM 416
1406 #define XSAVE_PKRU 672
1407
1408 #define XSAVE_BYTE_OFFSET(word_offset) \
1409 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1410
1411 #define ASSERT_OFFSET(word_offset, field) \
1412 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1413 offsetof(X86XSaveArea, field))
1414
1415 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1416 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1417 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1418 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1419 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1420 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1421 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1422 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1423 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1424 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1425 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1426 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1427 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1428 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1429 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1430
1431 static int kvm_put_xsave(X86CPU *cpu)
1432 {
1433 CPUX86State *env = &cpu->env;
1434 X86XSaveArea *xsave = env->kvm_xsave_buf;
1435 uint16_t cwd, swd, twd;
1436 int i;
1437
1438 if (!has_xsave) {
1439 return kvm_put_fpu(cpu);
1440 }
1441
1442 memset(xsave, 0, sizeof(struct kvm_xsave));
1443 twd = 0;
1444 swd = env->fpus & ~(7 << 11);
1445 swd |= (env->fpstt & 7) << 11;
1446 cwd = env->fpuc;
1447 for (i = 0; i < 8; ++i) {
1448 twd |= (!env->fptags[i]) << i;
1449 }
1450 xsave->legacy.fcw = cwd;
1451 xsave->legacy.fsw = swd;
1452 xsave->legacy.ftw = twd;
1453 xsave->legacy.fpop = env->fpop;
1454 xsave->legacy.fpip = env->fpip;
1455 xsave->legacy.fpdp = env->fpdp;
1456 memcpy(&xsave->legacy.fpregs, env->fpregs,
1457 sizeof env->fpregs);
1458 xsave->legacy.mxcsr = env->mxcsr;
1459 xsave->header.xstate_bv = env->xstate_bv;
1460 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1461 sizeof env->bnd_regs);
1462 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1463 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1464 sizeof env->opmask_regs);
1465
1466 for (i = 0; i < CPU_NB_REGS; i++) {
1467 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1468 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1469 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1470 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1471 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1472 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1473 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1474 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1475 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1476 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1477 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1478 }
1479
1480 #ifdef TARGET_X86_64
1481 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1482 16 * sizeof env->xmm_regs[16]);
1483 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1484 #endif
1485 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1486 }
1487
1488 static int kvm_put_xcrs(X86CPU *cpu)
1489 {
1490 CPUX86State *env = &cpu->env;
1491 struct kvm_xcrs xcrs = {};
1492
1493 if (!has_xcrs) {
1494 return 0;
1495 }
1496
1497 xcrs.nr_xcrs = 1;
1498 xcrs.flags = 0;
1499 xcrs.xcrs[0].xcr = 0;
1500 xcrs.xcrs[0].value = env->xcr0;
1501 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1502 }
1503
1504 static int kvm_put_sregs(X86CPU *cpu)
1505 {
1506 CPUX86State *env = &cpu->env;
1507 struct kvm_sregs sregs;
1508
1509 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1510 if (env->interrupt_injected >= 0) {
1511 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1512 (uint64_t)1 << (env->interrupt_injected % 64);
1513 }
1514
1515 if ((env->eflags & VM_MASK)) {
1516 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1517 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1518 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1519 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1520 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1521 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1522 } else {
1523 set_seg(&sregs.cs, &env->segs[R_CS]);
1524 set_seg(&sregs.ds, &env->segs[R_DS]);
1525 set_seg(&sregs.es, &env->segs[R_ES]);
1526 set_seg(&sregs.fs, &env->segs[R_FS]);
1527 set_seg(&sregs.gs, &env->segs[R_GS]);
1528 set_seg(&sregs.ss, &env->segs[R_SS]);
1529 }
1530
1531 set_seg(&sregs.tr, &env->tr);
1532 set_seg(&sregs.ldt, &env->ldt);
1533
1534 sregs.idt.limit = env->idt.limit;
1535 sregs.idt.base = env->idt.base;
1536 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1537 sregs.gdt.limit = env->gdt.limit;
1538 sregs.gdt.base = env->gdt.base;
1539 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1540
1541 sregs.cr0 = env->cr[0];
1542 sregs.cr2 = env->cr[2];
1543 sregs.cr3 = env->cr[3];
1544 sregs.cr4 = env->cr[4];
1545
1546 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1547 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1548
1549 sregs.efer = env->efer;
1550
1551 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1552 }
1553
1554 static void kvm_msr_buf_reset(X86CPU *cpu)
1555 {
1556 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1557 }
1558
1559 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1560 {
1561 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1562 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1563 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1564
1565 assert((void *)(entry + 1) <= limit);
1566
1567 entry->index = index;
1568 entry->reserved = 0;
1569 entry->data = value;
1570 msrs->nmsrs++;
1571 }
1572
1573 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1574 {
1575 kvm_msr_buf_reset(cpu);
1576 kvm_msr_entry_add(cpu, index, value);
1577
1578 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1579 }
1580
1581 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1582 {
1583 int ret;
1584
1585 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1586 assert(ret == 1);
1587 }
1588
1589 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1590 {
1591 CPUX86State *env = &cpu->env;
1592 int ret;
1593
1594 if (!has_msr_tsc_deadline) {
1595 return 0;
1596 }
1597
1598 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1599 if (ret < 0) {
1600 return ret;
1601 }
1602
1603 assert(ret == 1);
1604 return 0;
1605 }
1606
1607 /*
1608 * Provide a separate write service for the feature control MSR in order to
1609 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1610 * before writing any other state because forcibly leaving nested mode
1611 * invalidates the VCPU state.
1612 */
1613 static int kvm_put_msr_feature_control(X86CPU *cpu)
1614 {
1615 int ret;
1616
1617 if (!has_msr_feature_control) {
1618 return 0;
1619 }
1620
1621 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1622 cpu->env.msr_ia32_feature_control);
1623 if (ret < 0) {
1624 return ret;
1625 }
1626
1627 assert(ret == 1);
1628 return 0;
1629 }
1630
1631 static int kvm_put_msrs(X86CPU *cpu, int level)
1632 {
1633 CPUX86State *env = &cpu->env;
1634 int i;
1635 int ret;
1636
1637 kvm_msr_buf_reset(cpu);
1638
1639 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1640 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1641 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1642 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1643 if (has_msr_star) {
1644 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1645 }
1646 if (has_msr_hsave_pa) {
1647 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1648 }
1649 if (has_msr_tsc_aux) {
1650 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1651 }
1652 if (has_msr_tsc_adjust) {
1653 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1654 }
1655 if (has_msr_misc_enable) {
1656 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1657 env->msr_ia32_misc_enable);
1658 }
1659 if (has_msr_smbase) {
1660 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1661 }
1662 if (has_msr_bndcfgs) {
1663 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1664 }
1665 if (has_msr_xss) {
1666 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1667 }
1668 #ifdef TARGET_X86_64
1669 if (lm_capable_kernel) {
1670 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1671 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1672 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1673 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1674 }
1675 #endif
1676 /*
1677 * The following MSRs have side effects on the guest or are too heavy
1678 * for normal writeback. Limit them to reset or full state updates.
1679 */
1680 if (level >= KVM_PUT_RESET_STATE) {
1681 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1682 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1683 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1684 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1685 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1686 }
1687 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1688 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1689 }
1690 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1691 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1692 }
1693 if (has_msr_architectural_pmu) {
1694 /* Stop the counter. */
1695 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1696 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1697
1698 /* Set the counter values. */
1699 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1700 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1701 env->msr_fixed_counters[i]);
1702 }
1703 for (i = 0; i < num_architectural_pmu_counters; i++) {
1704 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1705 env->msr_gp_counters[i]);
1706 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1707 env->msr_gp_evtsel[i]);
1708 }
1709 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1710 env->msr_global_status);
1711 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1712 env->msr_global_ovf_ctrl);
1713
1714 /* Now start the PMU. */
1715 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1716 env->msr_fixed_ctr_ctrl);
1717 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1718 env->msr_global_ctrl);
1719 }
1720 if (has_msr_hv_hypercall) {
1721 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1722 env->msr_hv_guest_os_id);
1723 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1724 env->msr_hv_hypercall);
1725 }
1726 if (cpu->hyperv_vapic) {
1727 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1728 env->msr_hv_vapic);
1729 }
1730 if (cpu->hyperv_time) {
1731 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1732 }
1733 if (has_msr_hv_crash) {
1734 int j;
1735
1736 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1737 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1738 env->msr_hv_crash_params[j]);
1739
1740 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1741 HV_X64_MSR_CRASH_CTL_NOTIFY);
1742 }
1743 if (has_msr_hv_runtime) {
1744 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1745 }
1746 if (cpu->hyperv_synic) {
1747 int j;
1748
1749 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1750 env->msr_hv_synic_control);
1751 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1752 env->msr_hv_synic_version);
1753 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1754 env->msr_hv_synic_evt_page);
1755 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1756 env->msr_hv_synic_msg_page);
1757
1758 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1759 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1760 env->msr_hv_synic_sint[j]);
1761 }
1762 }
1763 if (has_msr_hv_stimer) {
1764 int j;
1765
1766 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1767 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1768 env->msr_hv_stimer_config[j]);
1769 }
1770
1771 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1772 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1773 env->msr_hv_stimer_count[j]);
1774 }
1775 }
1776 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1777 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1778
1779 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1780 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1781 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1782 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1783 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1784 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1785 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1786 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1787 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1788 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1789 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1790 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1791 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1792 /* The CPU GPs if we write to a bit above the physical limit of
1793 * the host CPU (and KVM emulates that)
1794 */
1795 uint64_t mask = env->mtrr_var[i].mask;
1796 mask &= phys_mask;
1797
1798 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1799 env->mtrr_var[i].base);
1800 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1801 }
1802 }
1803
1804 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1805 * kvm_put_msr_feature_control. */
1806 }
1807 if (env->mcg_cap) {
1808 int i;
1809
1810 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1811 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1812 if (has_msr_mcg_ext_ctl) {
1813 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1814 }
1815 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1816 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1817 }
1818 }
1819
1820 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1821 if (ret < 0) {
1822 return ret;
1823 }
1824
1825 assert(ret == cpu->kvm_msr_buf->nmsrs);
1826 return 0;
1827 }
1828
1829
1830 static int kvm_get_fpu(X86CPU *cpu)
1831 {
1832 CPUX86State *env = &cpu->env;
1833 struct kvm_fpu fpu;
1834 int i, ret;
1835
1836 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1837 if (ret < 0) {
1838 return ret;
1839 }
1840
1841 env->fpstt = (fpu.fsw >> 11) & 7;
1842 env->fpus = fpu.fsw;
1843 env->fpuc = fpu.fcw;
1844 env->fpop = fpu.last_opcode;
1845 env->fpip = fpu.last_ip;
1846 env->fpdp = fpu.last_dp;
1847 for (i = 0; i < 8; ++i) {
1848 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1849 }
1850 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1851 for (i = 0; i < CPU_NB_REGS; i++) {
1852 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1853 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1854 }
1855 env->mxcsr = fpu.mxcsr;
1856
1857 return 0;
1858 }
1859
1860 static int kvm_get_xsave(X86CPU *cpu)
1861 {
1862 CPUX86State *env = &cpu->env;
1863 X86XSaveArea *xsave = env->kvm_xsave_buf;
1864 int ret, i;
1865 uint16_t cwd, swd, twd;
1866
1867 if (!has_xsave) {
1868 return kvm_get_fpu(cpu);
1869 }
1870
1871 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1872 if (ret < 0) {
1873 return ret;
1874 }
1875
1876 cwd = xsave->legacy.fcw;
1877 swd = xsave->legacy.fsw;
1878 twd = xsave->legacy.ftw;
1879 env->fpop = xsave->legacy.fpop;
1880 env->fpstt = (swd >> 11) & 7;
1881 env->fpus = swd;
1882 env->fpuc = cwd;
1883 for (i = 0; i < 8; ++i) {
1884 env->fptags[i] = !((twd >> i) & 1);
1885 }
1886 env->fpip = xsave->legacy.fpip;
1887 env->fpdp = xsave->legacy.fpdp;
1888 env->mxcsr = xsave->legacy.mxcsr;
1889 memcpy(env->fpregs, &xsave->legacy.fpregs,
1890 sizeof env->fpregs);
1891 env->xstate_bv = xsave->header.xstate_bv;
1892 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1893 sizeof env->bnd_regs);
1894 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1895 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1896 sizeof env->opmask_regs);
1897
1898 for (i = 0; i < CPU_NB_REGS; i++) {
1899 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1900 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1901 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1902 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1903 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1904 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1905 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1906 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1907 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1908 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1909 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1910 }
1911
1912 #ifdef TARGET_X86_64
1913 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1914 16 * sizeof env->xmm_regs[16]);
1915 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1916 #endif
1917 return 0;
1918 }
1919
1920 static int kvm_get_xcrs(X86CPU *cpu)
1921 {
1922 CPUX86State *env = &cpu->env;
1923 int i, ret;
1924 struct kvm_xcrs xcrs;
1925
1926 if (!has_xcrs) {
1927 return 0;
1928 }
1929
1930 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1931 if (ret < 0) {
1932 return ret;
1933 }
1934
1935 for (i = 0; i < xcrs.nr_xcrs; i++) {
1936 /* Only support xcr0 now */
1937 if (xcrs.xcrs[i].xcr == 0) {
1938 env->xcr0 = xcrs.xcrs[i].value;
1939 break;
1940 }
1941 }
1942 return 0;
1943 }
1944
1945 static int kvm_get_sregs(X86CPU *cpu)
1946 {
1947 CPUX86State *env = &cpu->env;
1948 struct kvm_sregs sregs;
1949 uint32_t hflags;
1950 int bit, i, ret;
1951
1952 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1953 if (ret < 0) {
1954 return ret;
1955 }
1956
1957 /* There can only be one pending IRQ set in the bitmap at a time, so try
1958 to find it and save its number instead (-1 for none). */
1959 env->interrupt_injected = -1;
1960 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1961 if (sregs.interrupt_bitmap[i]) {
1962 bit = ctz64(sregs.interrupt_bitmap[i]);
1963 env->interrupt_injected = i * 64 + bit;
1964 break;
1965 }
1966 }
1967
1968 get_seg(&env->segs[R_CS], &sregs.cs);
1969 get_seg(&env->segs[R_DS], &sregs.ds);
1970 get_seg(&env->segs[R_ES], &sregs.es);
1971 get_seg(&env->segs[R_FS], &sregs.fs);
1972 get_seg(&env->segs[R_GS], &sregs.gs);
1973 get_seg(&env->segs[R_SS], &sregs.ss);
1974
1975 get_seg(&env->tr, &sregs.tr);
1976 get_seg(&env->ldt, &sregs.ldt);
1977
1978 env->idt.limit = sregs.idt.limit;
1979 env->idt.base = sregs.idt.base;
1980 env->gdt.limit = sregs.gdt.limit;
1981 env->gdt.base = sregs.gdt.base;
1982
1983 env->cr[0] = sregs.cr0;
1984 env->cr[2] = sregs.cr2;
1985 env->cr[3] = sregs.cr3;
1986 env->cr[4] = sregs.cr4;
1987
1988 env->efer = sregs.efer;
1989
1990 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1991
1992 #define HFLAG_COPY_MASK \
1993 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1994 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1995 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1996 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1997
1998 hflags = env->hflags & HFLAG_COPY_MASK;
1999 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
2000 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
2001 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
2002 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
2003 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
2004
2005 if (env->cr[4] & CR4_OSFXSR_MASK) {
2006 hflags |= HF_OSFXSR_MASK;
2007 }
2008
2009 if (env->efer & MSR_EFER_LMA) {
2010 hflags |= HF_LMA_MASK;
2011 }
2012
2013 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
2014 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2015 } else {
2016 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
2017 (DESC_B_SHIFT - HF_CS32_SHIFT);
2018 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
2019 (DESC_B_SHIFT - HF_SS32_SHIFT);
2020 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
2021 !(hflags & HF_CS32_MASK)) {
2022 hflags |= HF_ADDSEG_MASK;
2023 } else {
2024 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
2025 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
2026 }
2027 }
2028 env->hflags = hflags;
2029
2030 return 0;
2031 }
2032
2033 static int kvm_get_msrs(X86CPU *cpu)
2034 {
2035 CPUX86State *env = &cpu->env;
2036 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2037 int ret, i;
2038 uint64_t mtrr_top_bits;
2039
2040 kvm_msr_buf_reset(cpu);
2041
2042 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2043 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2044 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2045 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2046 if (has_msr_star) {
2047 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2048 }
2049 if (has_msr_hsave_pa) {
2050 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2051 }
2052 if (has_msr_tsc_aux) {
2053 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2054 }
2055 if (has_msr_tsc_adjust) {
2056 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2057 }
2058 if (has_msr_tsc_deadline) {
2059 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2060 }
2061 if (has_msr_misc_enable) {
2062 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2063 }
2064 if (has_msr_smbase) {
2065 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2066 }
2067 if (has_msr_feature_control) {
2068 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2069 }
2070 if (has_msr_bndcfgs) {
2071 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2072 }
2073 if (has_msr_xss) {
2074 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2075 }
2076
2077
2078 if (!env->tsc_valid) {
2079 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2080 env->tsc_valid = !runstate_is_running();
2081 }
2082
2083 #ifdef TARGET_X86_64
2084 if (lm_capable_kernel) {
2085 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2086 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2087 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2088 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2089 }
2090 #endif
2091 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2092 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2093 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2094 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2095 }
2096 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2097 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2098 }
2099 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2100 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2101 }
2102 if (has_msr_architectural_pmu) {
2103 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2104 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2105 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2106 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2107 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2108 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2109 }
2110 for (i = 0; i < num_architectural_pmu_counters; i++) {
2111 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2112 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2113 }
2114 }
2115
2116 if (env->mcg_cap) {
2117 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2118 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2119 if (has_msr_mcg_ext_ctl) {
2120 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2121 }
2122 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2123 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2124 }
2125 }
2126
2127 if (has_msr_hv_hypercall) {
2128 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2129 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2130 }
2131 if (cpu->hyperv_vapic) {
2132 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2133 }
2134 if (cpu->hyperv_time) {
2135 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2136 }
2137 if (has_msr_hv_crash) {
2138 int j;
2139
2140 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2141 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2142 }
2143 }
2144 if (has_msr_hv_runtime) {
2145 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2146 }
2147 if (cpu->hyperv_synic) {
2148 uint32_t msr;
2149
2150 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2151 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2152 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2153 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2154 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2155 kvm_msr_entry_add(cpu, msr, 0);
2156 }
2157 }
2158 if (has_msr_hv_stimer) {
2159 uint32_t msr;
2160
2161 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2162 msr++) {
2163 kvm_msr_entry_add(cpu, msr, 0);
2164 }
2165 }
2166 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2167 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2168 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2169 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2170 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2171 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2172 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2173 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2174 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2175 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2176 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2177 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2178 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2179 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2180 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2181 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2182 }
2183 }
2184
2185 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2186 if (ret < 0) {
2187 return ret;
2188 }
2189
2190 assert(ret == cpu->kvm_msr_buf->nmsrs);
2191 /*
2192 * MTRR masks: Each mask consists of 5 parts
2193 * a 10..0: must be zero
2194 * b 11 : valid bit
2195 * c n-1.12: actual mask bits
2196 * d 51..n: reserved must be zero
2197 * e 63.52: reserved must be zero
2198 *
2199 * 'n' is the number of physical bits supported by the CPU and is
2200 * apparently always <= 52. We know our 'n' but don't know what
2201 * the destinations 'n' is; it might be smaller, in which case
2202 * it masks (c) on loading. It might be larger, in which case
2203 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2204 * we're migrating to.
2205 */
2206
2207 if (cpu->fill_mtrr_mask) {
2208 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2209 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2210 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2211 } else {
2212 mtrr_top_bits = 0;
2213 }
2214
2215 for (i = 0; i < ret; i++) {
2216 uint32_t index = msrs[i].index;
2217 switch (index) {
2218 case MSR_IA32_SYSENTER_CS:
2219 env->sysenter_cs = msrs[i].data;
2220 break;
2221 case MSR_IA32_SYSENTER_ESP:
2222 env->sysenter_esp = msrs[i].data;
2223 break;
2224 case MSR_IA32_SYSENTER_EIP:
2225 env->sysenter_eip = msrs[i].data;
2226 break;
2227 case MSR_PAT:
2228 env->pat = msrs[i].data;
2229 break;
2230 case MSR_STAR:
2231 env->star = msrs[i].data;
2232 break;
2233 #ifdef TARGET_X86_64
2234 case MSR_CSTAR:
2235 env->cstar = msrs[i].data;
2236 break;
2237 case MSR_KERNELGSBASE:
2238 env->kernelgsbase = msrs[i].data;
2239 break;
2240 case MSR_FMASK:
2241 env->fmask = msrs[i].data;
2242 break;
2243 case MSR_LSTAR:
2244 env->lstar = msrs[i].data;
2245 break;
2246 #endif
2247 case MSR_IA32_TSC:
2248 env->tsc = msrs[i].data;
2249 break;
2250 case MSR_TSC_AUX:
2251 env->tsc_aux = msrs[i].data;
2252 break;
2253 case MSR_TSC_ADJUST:
2254 env->tsc_adjust = msrs[i].data;
2255 break;
2256 case MSR_IA32_TSCDEADLINE:
2257 env->tsc_deadline = msrs[i].data;
2258 break;
2259 case MSR_VM_HSAVE_PA:
2260 env->vm_hsave = msrs[i].data;
2261 break;
2262 case MSR_KVM_SYSTEM_TIME:
2263 env->system_time_msr = msrs[i].data;
2264 break;
2265 case MSR_KVM_WALL_CLOCK:
2266 env->wall_clock_msr = msrs[i].data;
2267 break;
2268 case MSR_MCG_STATUS:
2269 env->mcg_status = msrs[i].data;
2270 break;
2271 case MSR_MCG_CTL:
2272 env->mcg_ctl = msrs[i].data;
2273 break;
2274 case MSR_MCG_EXT_CTL:
2275 env->mcg_ext_ctl = msrs[i].data;
2276 break;
2277 case MSR_IA32_MISC_ENABLE:
2278 env->msr_ia32_misc_enable = msrs[i].data;
2279 break;
2280 case MSR_IA32_SMBASE:
2281 env->smbase = msrs[i].data;
2282 break;
2283 case MSR_IA32_FEATURE_CONTROL:
2284 env->msr_ia32_feature_control = msrs[i].data;
2285 break;
2286 case MSR_IA32_BNDCFGS:
2287 env->msr_bndcfgs = msrs[i].data;
2288 break;
2289 case MSR_IA32_XSS:
2290 env->xss = msrs[i].data;
2291 break;
2292 default:
2293 if (msrs[i].index >= MSR_MC0_CTL &&
2294 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2295 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2296 }
2297 break;
2298 case MSR_KVM_ASYNC_PF_EN:
2299 env->async_pf_en_msr = msrs[i].data;
2300 break;
2301 case MSR_KVM_PV_EOI_EN:
2302 env->pv_eoi_en_msr = msrs[i].data;
2303 break;
2304 case MSR_KVM_STEAL_TIME:
2305 env->steal_time_msr = msrs[i].data;
2306 break;
2307 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2308 env->msr_fixed_ctr_ctrl = msrs[i].data;
2309 break;
2310 case MSR_CORE_PERF_GLOBAL_CTRL:
2311 env->msr_global_ctrl = msrs[i].data;
2312 break;
2313 case MSR_CORE_PERF_GLOBAL_STATUS:
2314 env->msr_global_status = msrs[i].data;
2315 break;
2316 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2317 env->msr_global_ovf_ctrl = msrs[i].data;
2318 break;
2319 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2320 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2321 break;
2322 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2323 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2324 break;
2325 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2326 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2327 break;
2328 case HV_X64_MSR_HYPERCALL:
2329 env->msr_hv_hypercall = msrs[i].data;
2330 break;
2331 case HV_X64_MSR_GUEST_OS_ID:
2332 env->msr_hv_guest_os_id = msrs[i].data;
2333 break;
2334 case HV_X64_MSR_APIC_ASSIST_PAGE:
2335 env->msr_hv_vapic = msrs[i].data;
2336 break;
2337 case HV_X64_MSR_REFERENCE_TSC:
2338 env->msr_hv_tsc = msrs[i].data;
2339 break;
2340 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2341 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2342 break;
2343 case HV_X64_MSR_VP_RUNTIME:
2344 env->msr_hv_runtime = msrs[i].data;
2345 break;
2346 case HV_X64_MSR_SCONTROL:
2347 env->msr_hv_synic_control = msrs[i].data;
2348 break;
2349 case HV_X64_MSR_SVERSION:
2350 env->msr_hv_synic_version = msrs[i].data;
2351 break;
2352 case HV_X64_MSR_SIEFP:
2353 env->msr_hv_synic_evt_page = msrs[i].data;
2354 break;
2355 case HV_X64_MSR_SIMP:
2356 env->msr_hv_synic_msg_page = msrs[i].data;
2357 break;
2358 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2359 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2360 break;
2361 case HV_X64_MSR_STIMER0_CONFIG:
2362 case HV_X64_MSR_STIMER1_CONFIG:
2363 case HV_X64_MSR_STIMER2_CONFIG:
2364 case HV_X64_MSR_STIMER3_CONFIG:
2365 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2366 msrs[i].data;
2367 break;
2368 case HV_X64_MSR_STIMER0_COUNT:
2369 case HV_X64_MSR_STIMER1_COUNT:
2370 case HV_X64_MSR_STIMER2_COUNT:
2371 case HV_X64_MSR_STIMER3_COUNT:
2372 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2373 msrs[i].data;
2374 break;
2375 case MSR_MTRRdefType:
2376 env->mtrr_deftype = msrs[i].data;
2377 break;
2378 case MSR_MTRRfix64K_00000:
2379 env->mtrr_fixed[0] = msrs[i].data;
2380 break;
2381 case MSR_MTRRfix16K_80000:
2382 env->mtrr_fixed[1] = msrs[i].data;
2383 break;
2384 case MSR_MTRRfix16K_A0000:
2385 env->mtrr_fixed[2] = msrs[i].data;
2386 break;
2387 case MSR_MTRRfix4K_C0000:
2388 env->mtrr_fixed[3] = msrs[i].data;
2389 break;
2390 case MSR_MTRRfix4K_C8000:
2391 env->mtrr_fixed[4] = msrs[i].data;
2392 break;
2393 case MSR_MTRRfix4K_D0000:
2394 env->mtrr_fixed[5] = msrs[i].data;
2395 break;
2396 case MSR_MTRRfix4K_D8000:
2397 env->mtrr_fixed[6] = msrs[i].data;
2398 break;
2399 case MSR_MTRRfix4K_E0000:
2400 env->mtrr_fixed[7] = msrs[i].data;
2401 break;
2402 case MSR_MTRRfix4K_E8000:
2403 env->mtrr_fixed[8] = msrs[i].data;
2404 break;
2405 case MSR_MTRRfix4K_F0000:
2406 env->mtrr_fixed[9] = msrs[i].data;
2407 break;
2408 case MSR_MTRRfix4K_F8000:
2409 env->mtrr_fixed[10] = msrs[i].data;
2410 break;
2411 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2412 if (index & 1) {
2413 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2414 mtrr_top_bits;
2415 } else {
2416 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2417 }
2418 break;
2419 }
2420 }
2421
2422 return 0;
2423 }
2424
2425 static int kvm_put_mp_state(X86CPU *cpu)
2426 {
2427 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2428
2429 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2430 }
2431
2432 static int kvm_get_mp_state(X86CPU *cpu)
2433 {
2434 CPUState *cs = CPU(cpu);
2435 CPUX86State *env = &cpu->env;
2436 struct kvm_mp_state mp_state;
2437 int ret;
2438
2439 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2440 if (ret < 0) {
2441 return ret;
2442 }
2443 env->mp_state = mp_state.mp_state;
2444 if (kvm_irqchip_in_kernel()) {
2445 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2446 }
2447 return 0;
2448 }
2449
2450 static int kvm_get_apic(X86CPU *cpu)
2451 {
2452 DeviceState *apic = cpu->apic_state;
2453 struct kvm_lapic_state kapic;
2454 int ret;
2455
2456 if (apic && kvm_irqchip_in_kernel()) {
2457 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2458 if (ret < 0) {
2459 return ret;
2460 }
2461
2462 kvm_get_apic_state(apic, &kapic);
2463 }
2464 return 0;
2465 }
2466
2467 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2468 {
2469 CPUState *cs = CPU(cpu);
2470 CPUX86State *env = &cpu->env;
2471 struct kvm_vcpu_events events = {};
2472
2473 if (!kvm_has_vcpu_events()) {
2474 return 0;
2475 }
2476
2477 events.exception.injected = (env->exception_injected >= 0);
2478 events.exception.nr = env->exception_injected;
2479 events.exception.has_error_code = env->has_error_code;
2480 events.exception.error_code = env->error_code;
2481 events.exception.pad = 0;
2482
2483 events.interrupt.injected = (env->interrupt_injected >= 0);
2484 events.interrupt.nr = env->interrupt_injected;
2485 events.interrupt.soft = env->soft_interrupt;
2486
2487 events.nmi.injected = env->nmi_injected;
2488 events.nmi.pending = env->nmi_pending;
2489 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2490 events.nmi.pad = 0;
2491
2492 events.sipi_vector = env->sipi_vector;
2493 events.flags = 0;
2494
2495 if (has_msr_smbase) {
2496 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2497 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2498 if (kvm_irqchip_in_kernel()) {
2499 /* As soon as these are moved to the kernel, remove them
2500 * from cs->interrupt_request.
2501 */
2502 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2503 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2504 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2505 } else {
2506 /* Keep these in cs->interrupt_request. */
2507 events.smi.pending = 0;
2508 events.smi.latched_init = 0;
2509 }
2510 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2511 }
2512
2513 if (level >= KVM_PUT_RESET_STATE) {
2514 events.flags |=
2515 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2516 }
2517
2518 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2519 }
2520
2521 static int kvm_get_vcpu_events(X86CPU *cpu)
2522 {
2523 CPUX86State *env = &cpu->env;
2524 struct kvm_vcpu_events events;
2525 int ret;
2526
2527 if (!kvm_has_vcpu_events()) {
2528 return 0;
2529 }
2530
2531 memset(&events, 0, sizeof(events));
2532 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2533 if (ret < 0) {
2534 return ret;
2535 }
2536 env->exception_injected =
2537 events.exception.injected ? events.exception.nr : -1;
2538 env->has_error_code = events.exception.has_error_code;
2539 env->error_code = events.exception.error_code;
2540
2541 env->interrupt_injected =
2542 events.interrupt.injected ? events.interrupt.nr : -1;
2543 env->soft_interrupt = events.interrupt.soft;
2544
2545 env->nmi_injected = events.nmi.injected;
2546 env->nmi_pending = events.nmi.pending;
2547 if (events.nmi.masked) {
2548 env->hflags2 |= HF2_NMI_MASK;
2549 } else {
2550 env->hflags2 &= ~HF2_NMI_MASK;
2551 }
2552
2553 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2554 if (events.smi.smm) {
2555 env->hflags |= HF_SMM_MASK;
2556 } else {
2557 env->hflags &= ~HF_SMM_MASK;
2558 }
2559 if (events.smi.pending) {
2560 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2561 } else {
2562 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2563 }
2564 if (events.smi.smm_inside_nmi) {
2565 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2566 } else {
2567 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2568 }
2569 if (events.smi.latched_init) {
2570 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2571 } else {
2572 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2573 }
2574 }
2575
2576 env->sipi_vector = events.sipi_vector;
2577
2578 return 0;
2579 }
2580
2581 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2582 {
2583 CPUState *cs = CPU(cpu);
2584 CPUX86State *env = &cpu->env;
2585 int ret = 0;
2586 unsigned long reinject_trap = 0;
2587
2588 if (!kvm_has_vcpu_events()) {
2589 if (env->exception_injected == 1) {
2590 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2591 } else if (env->exception_injected == 3) {
2592 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2593 }
2594 env->exception_injected = -1;
2595 }
2596
2597 /*
2598 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2599 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2600 * by updating the debug state once again if single-stepping is on.
2601 * Another reason to call kvm_update_guest_debug here is a pending debug
2602 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2603 * reinject them via SET_GUEST_DEBUG.
2604 */
2605 if (reinject_trap ||
2606 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2607 ret = kvm_update_guest_debug(cs, reinject_trap);
2608 }
2609 return ret;
2610 }
2611
2612 static int kvm_put_debugregs(X86CPU *cpu)
2613 {
2614 CPUX86State *env = &cpu->env;
2615 struct kvm_debugregs dbgregs;
2616 int i;
2617
2618 if (!kvm_has_debugregs()) {
2619 return 0;
2620 }
2621
2622 for (i = 0; i < 4; i++) {
2623 dbgregs.db[i] = env->dr[i];
2624 }
2625 dbgregs.dr6 = env->dr[6];
2626 dbgregs.dr7 = env->dr[7];
2627 dbgregs.flags = 0;
2628
2629 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2630 }
2631
2632 static int kvm_get_debugregs(X86CPU *cpu)
2633 {
2634 CPUX86State *env = &cpu->env;
2635 struct kvm_debugregs dbgregs;
2636 int i, ret;
2637
2638 if (!kvm_has_debugregs()) {
2639 return 0;
2640 }
2641
2642 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2643 if (ret < 0) {
2644 return ret;
2645 }
2646 for (i = 0; i < 4; i++) {
2647 env->dr[i] = dbgregs.db[i];
2648 }
2649 env->dr[4] = env->dr[6] = dbgregs.dr6;
2650 env->dr[5] = env->dr[7] = dbgregs.dr7;
2651
2652 return 0;
2653 }
2654
2655 int kvm_arch_put_registers(CPUState *cpu, int level)
2656 {
2657 X86CPU *x86_cpu = X86_CPU(cpu);
2658 int ret;
2659
2660 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2661
2662 if (level >= KVM_PUT_RESET_STATE) {
2663 ret = kvm_put_msr_feature_control(x86_cpu);
2664 if (ret < 0) {
2665 return ret;
2666 }
2667 }
2668
2669 if (level == KVM_PUT_FULL_STATE) {
2670 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2671 * because TSC frequency mismatch shouldn't abort migration,
2672 * unless the user explicitly asked for a more strict TSC
2673 * setting (e.g. using an explicit "tsc-freq" option).
2674 */
2675 kvm_arch_set_tsc_khz(cpu);
2676 }
2677
2678 ret = kvm_getput_regs(x86_cpu, 1);
2679 if (ret < 0) {
2680 return ret;
2681 }
2682 ret = kvm_put_xsave(x86_cpu);
2683 if (ret < 0) {
2684 return ret;
2685 }
2686 ret = kvm_put_xcrs(x86_cpu);
2687 if (ret < 0) {
2688 return ret;
2689 }
2690 ret = kvm_put_sregs(x86_cpu);
2691 if (ret < 0) {
2692 return ret;
2693 }
2694 /* must be before kvm_put_msrs */
2695 ret = kvm_inject_mce_oldstyle(x86_cpu);
2696 if (ret < 0) {
2697 return ret;
2698 }
2699 ret = kvm_put_msrs(x86_cpu, level);
2700 if (ret < 0) {
2701 return ret;
2702 }
2703 if (level >= KVM_PUT_RESET_STATE) {
2704 ret = kvm_put_mp_state(x86_cpu);
2705 if (ret < 0) {
2706 return ret;
2707 }
2708 }
2709
2710 ret = kvm_put_tscdeadline_msr(x86_cpu);
2711 if (ret < 0) {
2712 return ret;
2713 }
2714
2715 ret = kvm_put_vcpu_events(x86_cpu, level);
2716 if (ret < 0) {
2717 return ret;
2718 }
2719 ret = kvm_put_debugregs(x86_cpu);
2720 if (ret < 0) {
2721 return ret;
2722 }
2723 /* must be last */
2724 ret = kvm_guest_debug_workarounds(x86_cpu);
2725 if (ret < 0) {
2726 return ret;
2727 }
2728 return 0;
2729 }
2730
2731 int kvm_arch_get_registers(CPUState *cs)
2732 {
2733 X86CPU *cpu = X86_CPU(cs);
2734 int ret;
2735
2736 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2737
2738 ret = kvm_getput_regs(cpu, 0);
2739 if (ret < 0) {
2740 goto out;
2741 }
2742 ret = kvm_get_xsave(cpu);
2743 if (ret < 0) {
2744 goto out;
2745 }
2746 ret = kvm_get_xcrs(cpu);
2747 if (ret < 0) {
2748 goto out;
2749 }
2750 ret = kvm_get_sregs(cpu);
2751 if (ret < 0) {
2752 goto out;
2753 }
2754 ret = kvm_get_msrs(cpu);
2755 if (ret < 0) {
2756 goto out;
2757 }
2758 ret = kvm_get_mp_state(cpu);
2759 if (ret < 0) {
2760 goto out;
2761 }
2762 ret = kvm_get_apic(cpu);
2763 if (ret < 0) {
2764 goto out;
2765 }
2766 ret = kvm_get_vcpu_events(cpu);
2767 if (ret < 0) {
2768 goto out;
2769 }
2770 ret = kvm_get_debugregs(cpu);
2771 if (ret < 0) {
2772 goto out;
2773 }
2774 ret = 0;
2775 out:
2776 cpu_sync_bndcs_hflags(&cpu->env);
2777 return ret;
2778 }
2779
2780 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2781 {
2782 X86CPU *x86_cpu = X86_CPU(cpu);
2783 CPUX86State *env = &x86_cpu->env;
2784 int ret;
2785
2786 /* Inject NMI */
2787 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2788 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2789 qemu_mutex_lock_iothread();
2790 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2791 qemu_mutex_unlock_iothread();
2792 DPRINTF("injected NMI\n");
2793 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2794 if (ret < 0) {
2795 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2796 strerror(-ret));
2797 }
2798 }
2799 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2800 qemu_mutex_lock_iothread();
2801 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2802 qemu_mutex_unlock_iothread();
2803 DPRINTF("injected SMI\n");
2804 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2805 if (ret < 0) {
2806 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2807 strerror(-ret));
2808 }
2809 }
2810 }
2811
2812 if (!kvm_pic_in_kernel()) {
2813 qemu_mutex_lock_iothread();
2814 }
2815
2816 /* Force the VCPU out of its inner loop to process any INIT requests
2817 * or (for userspace APIC, but it is cheap to combine the checks here)
2818 * pending TPR access reports.
2819 */
2820 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2821 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2822 !(env->hflags & HF_SMM_MASK)) {
2823 cpu->exit_request = 1;
2824 }
2825 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2826 cpu->exit_request = 1;
2827 }
2828 }
2829
2830 if (!kvm_pic_in_kernel()) {
2831 /* Try to inject an interrupt if the guest can accept it */
2832 if (run->ready_for_interrupt_injection &&
2833 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2834 (env->eflags & IF_MASK)) {
2835 int irq;
2836
2837 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2838 irq = cpu_get_pic_interrupt(env);
2839 if (irq >= 0) {
2840 struct kvm_interrupt intr;
2841
2842 intr.irq = irq;
2843 DPRINTF("injected interrupt %d\n", irq);
2844 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2845 if (ret < 0) {
2846 fprintf(stderr,
2847 "KVM: injection failed, interrupt lost (%s)\n",
2848 strerror(-ret));
2849 }
2850 }
2851 }
2852
2853 /* If we have an interrupt but the guest is not ready to receive an
2854 * interrupt, request an interrupt window exit. This will
2855 * cause a return to userspace as soon as the guest is ready to
2856 * receive interrupts. */
2857 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2858 run->request_interrupt_window = 1;
2859 } else {
2860 run->request_interrupt_window = 0;
2861 }
2862
2863 DPRINTF("setting tpr\n");
2864 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2865
2866 qemu_mutex_unlock_iothread();
2867 }
2868 }
2869
2870 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2871 {
2872 X86CPU *x86_cpu = X86_CPU(cpu);
2873 CPUX86State *env = &x86_cpu->env;
2874
2875 if (run->flags & KVM_RUN_X86_SMM) {
2876 env->hflags |= HF_SMM_MASK;
2877 } else {
2878 env->hflags &= ~HF_SMM_MASK;
2879 }
2880 if (run->if_flag) {
2881 env->eflags |= IF_MASK;
2882 } else {
2883 env->eflags &= ~IF_MASK;
2884 }
2885
2886 /* We need to protect the apic state against concurrent accesses from
2887 * different threads in case the userspace irqchip is used. */
2888 if (!kvm_irqchip_in_kernel()) {
2889 qemu_mutex_lock_iothread();
2890 }
2891 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2892 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2893 if (!kvm_irqchip_in_kernel()) {
2894 qemu_mutex_unlock_iothread();
2895 }
2896 return cpu_get_mem_attrs(env);
2897 }
2898
2899 int kvm_arch_process_async_events(CPUState *cs)
2900 {
2901 X86CPU *cpu = X86_CPU(cs);
2902 CPUX86State *env = &cpu->env;
2903
2904 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2905 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2906 assert(env->mcg_cap);
2907
2908 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2909
2910 kvm_cpu_synchronize_state(cs);
2911
2912 if (env->exception_injected == EXCP08_DBLE) {
2913 /* this means triple fault */
2914 qemu_system_reset_request();
2915 cs->exit_request = 1;
2916 return 0;
2917 }
2918 env->exception_injected = EXCP12_MCHK;
2919 env->has_error_code = 0;
2920
2921 cs->halted = 0;
2922 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2923 env->mp_state = KVM_MP_STATE_RUNNABLE;
2924 }
2925 }
2926
2927 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2928 !(env->hflags & HF_SMM_MASK)) {
2929 kvm_cpu_synchronize_state(cs);
2930 do_cpu_init(cpu);
2931 }
2932
2933 if (kvm_irqchip_in_kernel()) {
2934 return 0;
2935 }
2936
2937 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2938 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2939 apic_poll_irq(cpu->apic_state);
2940 }
2941 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2942 (env->eflags & IF_MASK)) ||
2943 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2944 cs->halted = 0;
2945 }
2946 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2947 kvm_cpu_synchronize_state(cs);
2948 do_cpu_sipi(cpu);
2949 }
2950 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2951 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2952 kvm_cpu_synchronize_state(cs);
2953 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2954 env->tpr_access_type);
2955 }
2956
2957 return cs->halted;
2958 }
2959
2960 static int kvm_handle_halt(X86CPU *cpu)
2961 {
2962 CPUState *cs = CPU(cpu);
2963 CPUX86State *env = &cpu->env;
2964
2965 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2966 (env->eflags & IF_MASK)) &&
2967 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2968 cs->halted = 1;
2969 return EXCP_HLT;
2970 }
2971
2972 return 0;
2973 }
2974
2975 static int kvm_handle_tpr_access(X86CPU *cpu)
2976 {
2977 CPUState *cs = CPU(cpu);
2978 struct kvm_run *run = cs->kvm_run;
2979
2980 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2981 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2982 : TPR_ACCESS_READ);
2983 return 1;
2984 }
2985
2986 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2987 {
2988 static const uint8_t int3 = 0xcc;
2989
2990 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2991 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2992 return -EINVAL;
2993 }
2994 return 0;
2995 }
2996
2997 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2998 {
2999 uint8_t int3;
3000
3001 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3002 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3003 return -EINVAL;
3004 }
3005 return 0;
3006 }
3007
3008 static struct {
3009 target_ulong addr;
3010 int len;
3011 int type;
3012 } hw_breakpoint[4];
3013
3014 static int nb_hw_breakpoint;
3015
3016 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3017 {
3018 int n;
3019
3020 for (n = 0; n < nb_hw_breakpoint; n++) {
3021 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3022 (hw_breakpoint[n].len == len || len == -1)) {
3023 return n;
3024 }
3025 }
3026 return -1;
3027 }
3028
3029 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3030 target_ulong len, int type)
3031 {
3032 switch (type) {
3033 case GDB_BREAKPOINT_HW:
3034 len = 1;
3035 break;
3036 case GDB_WATCHPOINT_WRITE:
3037 case GDB_WATCHPOINT_ACCESS:
3038 switch (len) {
3039 case 1:
3040 break;
3041 case 2:
3042 case 4:
3043 case 8:
3044 if (addr & (len - 1)) {
3045 return -EINVAL;
3046 }
3047 break;
3048 default:
3049 return -EINVAL;
3050 }
3051 break;
3052 default:
3053 return -ENOSYS;
3054 }
3055
3056 if (nb_hw_breakpoint == 4) {
3057 return -ENOBUFS;
3058 }
3059 if (find_hw_breakpoint(addr, len, type) >= 0) {
3060 return -EEXIST;
3061 }
3062 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3063 hw_breakpoint[nb_hw_breakpoint].len = len;
3064 hw_breakpoint[nb_hw_breakpoint].type = type;
3065 nb_hw_breakpoint++;
3066
3067 return 0;
3068 }
3069
3070 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3071 target_ulong len, int type)
3072 {
3073 int n;
3074
3075 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3076 if (n < 0) {
3077 return -ENOENT;
3078 }
3079 nb_hw_breakpoint--;
3080 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3081
3082 return 0;
3083 }
3084
3085 void kvm_arch_remove_all_hw_breakpoints(void)
3086 {
3087 nb_hw_breakpoint = 0;
3088 }
3089
3090 static CPUWatchpoint hw_watchpoint;
3091
3092 static int kvm_handle_debug(X86CPU *cpu,
3093 struct kvm_debug_exit_arch *arch_info)
3094 {
3095 CPUState *cs = CPU(cpu);
3096 CPUX86State *env = &cpu->env;
3097 int ret = 0;
3098 int n;
3099
3100 if (arch_info->exception == 1) {
3101 if (arch_info->dr6 & (1 << 14)) {
3102 if (cs->singlestep_enabled) {
3103 ret = EXCP_DEBUG;
3104 }
3105 } else {
3106 for (n = 0; n < 4; n++) {
3107 if (arch_info->dr6 & (1 << n)) {
3108 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3109 case 0x0:
3110 ret = EXCP_DEBUG;
3111 break;
3112 case 0x1:
3113 ret = EXCP_DEBUG;
3114 cs->watchpoint_hit = &hw_watchpoint;
3115 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3116 hw_watchpoint.flags = BP_MEM_WRITE;
3117 break;
3118 case 0x3:
3119 ret = EXCP_DEBUG;
3120 cs->watchpoint_hit = &hw_watchpoint;
3121 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3122 hw_watchpoint.flags = BP_MEM_ACCESS;
3123 break;
3124 }
3125 }
3126 }
3127 }
3128 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3129 ret = EXCP_DEBUG;
3130 }
3131 if (ret == 0) {
3132 cpu_synchronize_state(cs);
3133 assert(env->exception_injected == -1);
3134
3135 /* pass to guest */
3136 env->exception_injected = arch_info->exception;
3137 env->has_error_code = 0;
3138 }
3139
3140 return ret;
3141 }
3142
3143 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3144 {
3145 const uint8_t type_code[] = {
3146 [GDB_BREAKPOINT_HW] = 0x0,
3147 [GDB_WATCHPOINT_WRITE] = 0x1,
3148 [GDB_WATCHPOINT_ACCESS] = 0x3
3149 };
3150 const uint8_t len_code[] = {
3151 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3152 };
3153 int n;
3154
3155 if (kvm_sw_breakpoints_active(cpu)) {
3156 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3157 }
3158 if (nb_hw_breakpoint > 0) {
3159 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3160 dbg->arch.debugreg[7] = 0x0600;
3161 for (n = 0; n < nb_hw_breakpoint; n++) {
3162 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3163 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3164 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3165 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3166 }
3167 }
3168 }
3169
3170 static bool host_supports_vmx(void)
3171 {
3172 uint32_t ecx, unused;
3173
3174 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3175 return ecx & CPUID_EXT_VMX;
3176 }
3177
3178 #define VMX_INVALID_GUEST_STATE 0x80000021
3179
3180 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3181 {
3182 X86CPU *cpu = X86_CPU(cs);
3183 uint64_t code;
3184 int ret;
3185
3186 switch (run->exit_reason) {
3187 case KVM_EXIT_HLT:
3188 DPRINTF("handle_hlt\n");
3189 qemu_mutex_lock_iothread();
3190 ret = kvm_handle_halt(cpu);
3191 qemu_mutex_unlock_iothread();
3192 break;
3193 case KVM_EXIT_SET_TPR:
3194 ret = 0;
3195 break;
3196 case KVM_EXIT_TPR_ACCESS:
3197 qemu_mutex_lock_iothread();
3198 ret = kvm_handle_tpr_access(cpu);
3199 qemu_mutex_unlock_iothread();
3200 break;
3201 case KVM_EXIT_FAIL_ENTRY:
3202 code = run->fail_entry.hardware_entry_failure_reason;
3203 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3204 code);
3205 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3206 fprintf(stderr,
3207 "\nIf you're running a guest on an Intel machine without "
3208 "unrestricted mode\n"
3209 "support, the failure can be most likely due to the guest "
3210 "entering an invalid\n"
3211 "state for Intel VT. For example, the guest maybe running "
3212 "in big real mode\n"
3213 "which is not supported on less recent Intel processors."
3214 "\n\n");
3215 }
3216 ret = -1;
3217 break;
3218 case KVM_EXIT_EXCEPTION:
3219 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3220 run->ex.exception, run->ex.error_code);
3221 ret = -1;
3222 break;
3223 case KVM_EXIT_DEBUG:
3224 DPRINTF("kvm_exit_debug\n");
3225 qemu_mutex_lock_iothread();
3226 ret = kvm_handle_debug(cpu, &run->debug.arch);
3227 qemu_mutex_unlock_iothread();
3228 break;
3229 case KVM_EXIT_HYPERV:
3230 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3231 break;
3232 case KVM_EXIT_IOAPIC_EOI:
3233 ioapic_eoi_broadcast(run->eoi.vector);
3234 ret = 0;
3235 break;
3236 default:
3237 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3238 ret = -1;
3239 break;
3240 }
3241
3242 return ret;
3243 }
3244
3245 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3246 {
3247 X86CPU *cpu = X86_CPU(cs);
3248 CPUX86State *env = &cpu->env;
3249
3250 kvm_cpu_synchronize_state(cs);
3251 return !(env->cr[0] & CR0_PE_MASK) ||
3252 ((env->segs[R_CS].selector & 3) != 3);
3253 }
3254
3255 void kvm_arch_init_irq_routing(KVMState *s)
3256 {
3257 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3258 /* If kernel can't do irq routing, interrupt source
3259 * override 0->2 cannot be set up as required by HPET.
3260 * So we have to disable it.
3261 */
3262 no_hpet = 1;
3263 }
3264 /* We know at this point that we're using the in-kernel
3265 * irqchip, so we can use irqfds, and on x86 we know
3266 * we can use msi via irqfd and GSI routing.
3267 */
3268 kvm_msi_via_irqfd_allowed = true;
3269 kvm_gsi_routing_allowed = true;
3270
3271 if (kvm_irqchip_is_split()) {
3272 int i;
3273
3274 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3275 MSI routes for signaling interrupts to the local apics. */
3276 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3277 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3278 error_report("Could not enable split IRQ mode.");
3279 exit(1);
3280 }
3281 }
3282 }
3283 }
3284
3285 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3286 {
3287 int ret;
3288 if (machine_kernel_irqchip_split(ms)) {
3289 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3290 if (ret) {
3291 error_report("Could not enable split irqchip mode: %s",
3292 strerror(-ret));
3293 exit(1);
3294 } else {
3295 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3296 kvm_split_irqchip = true;
3297 return 1;
3298 }
3299 } else {
3300 return 0;
3301 }
3302 }
3303
3304 /* Classic KVM device assignment interface. Will remain x86 only. */
3305 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3306 uint32_t flags, uint32_t *dev_id)
3307 {
3308 struct kvm_assigned_pci_dev dev_data = {
3309 .segnr = dev_addr->domain,
3310 .busnr = dev_addr->bus,
3311 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3312 .flags = flags,
3313 };
3314 int ret;
3315
3316 dev_data.assigned_dev_id =
3317 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3318
3319 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3320 if (ret < 0) {
3321 return ret;
3322 }
3323
3324 *dev_id = dev_data.assigned_dev_id;
3325
3326 return 0;
3327 }
3328
3329 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3330 {
3331 struct kvm_assigned_pci_dev dev_data = {
3332 .assigned_dev_id = dev_id,
3333 };
3334
3335 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3336 }
3337
3338 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3339 uint32_t irq_type, uint32_t guest_irq)
3340 {
3341 struct kvm_assigned_irq assigned_irq = {
3342 .assigned_dev_id = dev_id,
3343 .guest_irq = guest_irq,
3344 .flags = irq_type,
3345 };
3346
3347 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3348 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3349 } else {
3350 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3351 }
3352 }
3353
3354 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3355 uint32_t guest_irq)
3356 {
3357 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3358 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3359
3360 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3361 }
3362
3363 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3364 {
3365 struct kvm_assigned_pci_dev dev_data = {
3366 .assigned_dev_id = dev_id,
3367 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3368 };
3369
3370 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3371 }
3372
3373 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3374 uint32_t type)
3375 {
3376 struct kvm_assigned_irq assigned_irq = {
3377 .assigned_dev_id = dev_id,
3378 .flags = type,
3379 };
3380
3381 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3382 }
3383
3384 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3385 {
3386 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3387 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3388 }
3389
3390 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3391 {
3392 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3393 KVM_DEV_IRQ_GUEST_MSI, virq);
3394 }
3395
3396 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3397 {
3398 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3399 KVM_DEV_IRQ_HOST_MSI);
3400 }
3401
3402 bool kvm_device_msix_supported(KVMState *s)
3403 {
3404 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3405 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3406 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3407 }
3408
3409 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3410 uint32_t nr_vectors)
3411 {
3412 struct kvm_assigned_msix_nr msix_nr = {
3413 .assigned_dev_id = dev_id,
3414 .entry_nr = nr_vectors,
3415 };
3416
3417 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3418 }
3419
3420 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3421 int virq)
3422 {
3423 struct kvm_assigned_msix_entry msix_entry = {
3424 .assigned_dev_id = dev_id,
3425 .gsi = virq,
3426 .entry = vector,
3427 };
3428
3429 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3430 }
3431
3432 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3433 {
3434 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3435 KVM_DEV_IRQ_GUEST_MSIX, 0);
3436 }
3437
3438 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3439 {
3440 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3441 KVM_DEV_IRQ_HOST_MSIX);
3442 }
3443
3444 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3445 uint64_t address, uint32_t data, PCIDevice *dev)
3446 {
3447 X86IOMMUState *iommu = x86_iommu_get_default();
3448
3449 if (iommu) {
3450 int ret;
3451 MSIMessage src, dst;
3452 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3453
3454 src.address = route->u.msi.address_hi;
3455 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3456 src.address |= route->u.msi.address_lo;
3457 src.data = route->u.msi.data;
3458
3459 ret = class->int_remap(iommu, &src, &dst, dev ? \
3460 pci_requester_id(dev) : \
3461 X86_IOMMU_SID_INVALID);
3462 if (ret) {
3463 trace_kvm_x86_fixup_msi_error(route->gsi);
3464 return 1;
3465 }
3466
3467 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3468 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3469 route->u.msi.data = dst.data;
3470 }
3471
3472 return 0;
3473 }
3474
3475 typedef struct MSIRouteEntry MSIRouteEntry;
3476
3477 struct MSIRouteEntry {
3478 PCIDevice *dev; /* Device pointer */
3479 int vector; /* MSI/MSIX vector index */
3480 int virq; /* Virtual IRQ index */
3481 QLIST_ENTRY(MSIRouteEntry) list;
3482 };
3483
3484 /* List of used GSI routes */
3485 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3486 QLIST_HEAD_INITIALIZER(msi_route_list);
3487
3488 static void kvm_update_msi_routes_all(void *private, bool global,
3489 uint32_t index, uint32_t mask)
3490 {
3491 int cnt = 0;
3492 MSIRouteEntry *entry;
3493 MSIMessage msg;
3494 /* TODO: explicit route update */
3495 QLIST_FOREACH(entry, &msi_route_list, list) {
3496 cnt++;
3497 msg = pci_get_msi_message(entry->dev, entry->vector);
3498 kvm_irqchip_update_msi_route(kvm_state, entry->virq,
3499 msg, entry->dev);
3500 }
3501 kvm_irqchip_commit_routes(kvm_state);
3502 trace_kvm_x86_update_msi_routes(cnt);
3503 }
3504
3505 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3506 int vector, PCIDevice *dev)
3507 {
3508 static bool notify_list_inited = false;
3509 MSIRouteEntry *entry;
3510
3511 if (!dev) {
3512 /* These are (possibly) IOAPIC routes only used for split
3513 * kernel irqchip mode, while what we are housekeeping are
3514 * PCI devices only. */
3515 return 0;
3516 }
3517
3518 entry = g_new0(MSIRouteEntry, 1);
3519 entry->dev = dev;
3520 entry->vector = vector;
3521 entry->virq = route->gsi;
3522 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3523
3524 trace_kvm_x86_add_msi_route(route->gsi);
3525
3526 if (!notify_list_inited) {
3527 /* For the first time we do add route, add ourselves into
3528 * IOMMU's IEC notify list if needed. */
3529 X86IOMMUState *iommu = x86_iommu_get_default();
3530 if (iommu) {
3531 x86_iommu_iec_register_notifier(iommu,
3532 kvm_update_msi_routes_all,
3533 NULL);
3534 }
3535 notify_list_inited = true;
3536 }
3537 return 0;
3538 }
3539
3540 int kvm_arch_release_virq_post(int virq)
3541 {
3542 MSIRouteEntry *entry, *next;
3543 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3544 if (entry->virq == virq) {
3545 trace_kvm_x86_remove_msi_route(virq);
3546 QLIST_REMOVE(entry, list);
3547 break;
3548 }
3549 }
3550 return 0;
3551 }
3552
3553 int kvm_arch_msi_data_to_gsi(uint32_t data)
3554 {
3555 abort();
3556 }
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