target/i386/tcg/decode-new.h

   1 /*
   2  * Decode table flags, mostly based on Intel SDM.
   3  *
   4  *  Copyright (c) 2022 Red Hat, Inc.
   5  *
   6  * Author: Paolo Bonzini <pbonzini@redhat.com>
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2.1 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 typedef enum X86OpType {
  23     X86_TYPE_None,
  24
  25     X86_TYPE_A, /* Implicit */
  26     X86_TYPE_B, /* VEX.vvvv selects a GPR */
  27     X86_TYPE_C, /* REG in the modrm byte selects a control register */
  28     X86_TYPE_D, /* REG in the modrm byte selects a debug register */
  29     X86_TYPE_E, /* ALU modrm operand */
  30     X86_TYPE_F, /* EFLAGS/RFLAGS */
  31     X86_TYPE_G, /* REG in the modrm byte selects a GPR */
  32     X86_TYPE_H, /* For AVX, VEX.vvvv selects an XMM/YMM register */
  33     X86_TYPE_I, /* Immediate */
  34     X86_TYPE_J, /* Relative offset for a jump */
  35     X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */
  36     X86_TYPE_M, /* modrm byte selects a memory operand */
  37     X86_TYPE_N, /* R/M in the modrm byte selects an MMX register */
  38     X86_TYPE_O, /* Absolute address encoded in the instruction */
  39     X86_TYPE_P, /* reg in the modrm byte selects an MMX register */
  40     X86_TYPE_Q, /* MMX modrm operand */
  41     X86_TYPE_R, /* R/M in the modrm byte selects a register */
  42     X86_TYPE_S, /* reg selects a segment register */
  43     X86_TYPE_U, /* R/M in the modrm byte selects an XMM/YMM register */
  44     X86_TYPE_V, /* reg in the modrm byte selects an XMM/YMM register */
  45     X86_TYPE_W, /* XMM/YMM modrm operand */
  46     X86_TYPE_X, /* string source */
  47     X86_TYPE_Y, /* string destination */
  48
  49     /* Custom */
  50     X86_TYPE_WM, /* modrm byte selects an XMM/YMM memory operand */
  51     X86_TYPE_2op, /* 2-operand RMW instruction */
  52     X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */
  53     X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */
  54     X86_TYPE_1,
  55     X86_TYPE_2,
  56     X86_TYPE_3,
  57     X86_TYPE_4,
  58     X86_TYPE_5,
  59     X86_TYPE_6,
  60     X86_TYPE_7,
  61     X86_TYPE_ES, /* Hard-coded segment registers */
  62     X86_TYPE_CS,
  63     X86_TYPE_SS,
  64     X86_TYPE_DS,
  65     X86_TYPE_FS,
  66     X86_TYPE_GS,
  67 } X86OpType;
  68
  69 typedef enum X86OpSize {
  70     X86_SIZE_None,
  71
  72     X86_SIZE_a,  /* BOUND operand */
  73     X86_SIZE_b,  /* byte */
  74     X86_SIZE_d,  /* 32-bit */
  75     X86_SIZE_dq, /* SSE/AVX 128-bit */
  76     X86_SIZE_p,  /* Far pointer */
  77     X86_SIZE_pd, /* SSE/AVX packed double precision */
  78     X86_SIZE_pi, /* MMX */
  79     X86_SIZE_ps, /* SSE/AVX packed single precision */
  80     X86_SIZE_q,  /* 64-bit */
  81     X86_SIZE_qq, /* AVX 256-bit */
  82     X86_SIZE_s,  /* Descriptor */
  83     X86_SIZE_sd, /* SSE/AVX scalar double precision */
  84     X86_SIZE_ss, /* SSE/AVX scalar single precision */
  85     X86_SIZE_si, /* 32-bit GPR */
  86     X86_SIZE_v,  /* 16/32/64-bit, based on operand size */
  87     X86_SIZE_w,  /* 16-bit */
  88     X86_SIZE_x,  /* 128/256-bit, based on operand size */
  89     X86_SIZE_y,  /* 32/64-bit, based on operand size */
  90     X86_SIZE_z,  /* 16-bit for 16-bit operand size, else 32-bit */
  91
  92     /* Custom */
  93     X86_SIZE_d64,
  94     X86_SIZE_f64,
  95     X86_SIZE_xh, /* SSE/AVX packed half register */
  96 } X86OpSize;
  97
  98 typedef enum X86CPUIDFeature {
  99     X86_FEAT_None,
 100     X86_FEAT_3DNOW,
 101     X86_FEAT_ADX,
 102     X86_FEAT_AES,
 103     X86_FEAT_AVX,
 104     X86_FEAT_AVX2,
 105     X86_FEAT_BMI1,
 106     X86_FEAT_BMI2,
 107     X86_FEAT_F16C,
 108     X86_FEAT_FMA,
 109     X86_FEAT_MOVBE,
 110     X86_FEAT_PCLMULQDQ,
 111     X86_FEAT_SHA_NI,
 112     X86_FEAT_SSE,
 113     X86_FEAT_SSE2,
 114     X86_FEAT_SSE3,
 115     X86_FEAT_SSSE3,
 116     X86_FEAT_SSE41,
 117     X86_FEAT_SSE42,
 118     X86_FEAT_SSE4A,
 119 } X86CPUIDFeature;
 120
 121 /* Execution flags */
 122
 123 typedef enum X86OpUnit {
 124     X86_OP_SKIP,    /* not valid or managed by emission function */
 125     X86_OP_SEG,     /* segment selector */
 126     X86_OP_CR,      /* control register */
 127     X86_OP_DR,      /* debug register */
 128     X86_OP_INT,     /* loaded into/stored from s->T0/T1 */
 129     X86_OP_IMM,     /* immediate */
 130     X86_OP_SSE,     /* address in either s->ptrX or s->A0 depending on has_ea */
 131     X86_OP_MMX,     /* address in either s->ptrX or s->A0 depending on has_ea */
 132 } X86OpUnit;
 133
 134 typedef enum X86InsnCheck {
 135     /* Illegal or exclusive to 64-bit mode */
 136     X86_CHECK_i64 = 1,
 137     X86_CHECK_o64 = 2,
 138
 139     /* Fault outside protected mode */
 140     X86_CHECK_prot = 4,
 141
 142     /* Privileged instruction checks */
 143     X86_CHECK_cpl0 = 8,
 144     X86_CHECK_vm86_iopl = 16,
 145     X86_CHECK_cpl_iopl = 32,
 146     X86_CHECK_iopl = X86_CHECK_cpl_iopl | X86_CHECK_vm86_iopl,
 147
 148     /* Fault if VEX.L=1 */
 149     X86_CHECK_VEX128 = 64,
 150
 151     /* Fault if VEX.W=1 */
 152     X86_CHECK_W0 = 128,
 153
 154     /* Fault if VEX.W=0 */
 155     X86_CHECK_W1 = 256,
 156 } X86InsnCheck;
 157
 158 typedef enum X86InsnSpecial {
 159     X86_SPECIAL_None,
 160
 161     /* Accepts LOCK prefix; LOCKed operations do not load or writeback operand 0 */
 162     X86_SPECIAL_HasLock,
 163
 164     /* Always locked if it has a memory operand (XCHG) */
 165     X86_SPECIAL_Locked,
 166
 167     /*
 168      * Rd/Mb or Rd/Mw in the manual: register operand 0 is treated as 32 bits
 169      * (and writeback zero-extends it to 64 bits if applicable).  PREFIX_DATA
 170      * does not trigger 16-bit writeback and, as a side effect, high-byte
 171      * registers are never used.
 172      */
 173     X86_SPECIAL_Op0_Rd,
 174
 175     /*
 176      * Ry/Mb in the manual (PINSRB).  However, the high bits are never used by
 177      * the instruction in either the register or memory cases; the *real* effect
 178      * of this modifier is that high-byte registers are never used, even without
 179      * a REX prefix.  Therefore, PINSRW does not need it despite having Ry/Mw.
 180      */
 181     X86_SPECIAL_Op2_Ry,
 182
 183     /*
 184      * Register operand 2 is extended to full width, while a memory operand
 185      * is doubled in size if VEX.L=1.
 186      */
 187     X86_SPECIAL_AVXExtMov,
 188
 189     /*
 190      * MMX instruction exists with no prefix; if there is no prefix, V/H/W/U operands
 191      * become P/P/Q/N, and size "x" becomes "q".
 192      */
 193     X86_SPECIAL_MMX,
 194
 195     /* When loaded into s->T0, register operand 1 is zero/sign extended.  */
 196     X86_SPECIAL_SExtT0,
 197     X86_SPECIAL_ZExtT0,
 198 } X86InsnSpecial;
 199
 200 /*
 201  * Special cases for instructions that operate on XMM/YMM registers.  Intel
 202  * retconned all of them to have VEX exception classes other than 0 and 13, so
 203  * all these only matter for instructions that have a VEX exception class.
 204  * Based on tables in the "AVX and SSE Instruction Exception Specification"
 205  * section of the manual.
 206  */
 207 typedef enum X86VEXSpecial {
 208     /* Legacy SSE instructions that allow unaligned operands */
 209     X86_VEX_SSEUnaligned,
 210
 211     /*
 212      * Used for instructions that distinguish the XMM operand type with an
 213      * instruction prefix; legacy SSE encodings will allow unaligned operands
 214      * for scalar operands only (identified by a REP prefix).  In this case,
 215      * the decoding table uses "x" for the vector operands instead of specifying
 216      * pd/ps/sd/ss individually.
 217      */
 218     X86_VEX_REPScalar,
 219
 220     /*
 221      * VEX instructions that only support 256-bit operands with AVX2 (Table 2-17
 222      * column 3).  Columns 2 and 4 (instructions limited to 256- and 127-bit
 223      * operands respectively) are implicit in the presence of dq and qq
 224      * operands, and thus handled by decode_op_size.
 225      */
 226     X86_VEX_AVX2_256,
 227 } X86VEXSpecial;
 228
 229
 230 typedef struct X86OpEntry  X86OpEntry;
 231 typedef struct X86DecodedInsn X86DecodedInsn;
 232
 233 /* Decode function for multibyte opcodes.  */
 234 typedef void (*X86DecodeFunc)(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b);
 235
 236 /* Code generation function.  */
 237 typedef void (*X86GenFunc)(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode);
 238
 239 struct X86OpEntry {
 240     /* Based on the is_decode flags.  */
 241     union {
 242         X86GenFunc gen;
 243         X86DecodeFunc decode;
 244     };
 245     /* op0 is always written, op1 and op2 are always read.  */
 246     X86OpType    op0:8;
 247     X86OpSize    s0:8;
 248     X86OpType    op1:8;
 249     X86OpSize    s1:8;
 250     X86OpType    op2:8;
 251     X86OpSize    s2:8;
 252     /* Must be I and b respectively if present.  */
 253     X86OpType    op3:8;
 254     X86OpSize    s3:8;
 255
 256     X86InsnSpecial special:8;
 257     X86CPUIDFeature cpuid:8;
 258     unsigned     vex_class:8;
 259     X86VEXSpecial vex_special:8;
 260     unsigned     valid_prefix:16;
 261     unsigned     check:16;
 262     unsigned     intercept:8;
 263     bool         is_decode:1;
 264 };
 265
 266 typedef struct X86DecodedOp {
 267     int8_t n;
 268     MemOp ot;     /* For b/c/d/p/s/q/v/w/y/z */
 269     X86OpUnit unit;
 270     bool has_ea;
 271     int offset;   /* For MMX and SSE */
 272
 273     /*
 274      * This field is used internally by macros OP0_PTR/OP1_PTR/OP2_PTR,
 275      * do not access directly!
 276      */
 277     TCGv_ptr v_ptr;
 278 } X86DecodedOp;
 279
 280 struct X86DecodedInsn {
 281     X86OpEntry e;
 282     X86DecodedOp op[3];
 283     target_ulong immediate;
 284     AddressParts mem;
 285
 286     TCGv cc_dst, cc_src, cc_src2;
 287     TCGv_i32 cc_op_dynamic;
 288     int8_t cc_op;
 289
 290     uint8_t b;
 291 };
 292