target/lm32/cpu.h

   1 /*
   2  *  LatticeMico32 virtual CPU header.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef LM32_CPU_H
  21 #define LM32_CPU_H
  22
  23 #include "qemu-common.h"
  24 #include "cpu-qom.h"
  25 #include "exec/cpu-defs.h"
  26
  27 typedef struct CPULM32State CPULM32State;
  28
  29 static inline int cpu_mmu_index(CPULM32State *env, bool ifetch)
  30 {
  31     return 0;
  32 }
  33
  34 /* Exceptions indices */
  35 enum {
  36     EXCP_RESET = 0,
  37     EXCP_BREAKPOINT,
  38     EXCP_INSN_BUS_ERROR,
  39     EXCP_WATCHPOINT,
  40     EXCP_DATA_BUS_ERROR,
  41     EXCP_DIVIDE_BY_ZERO,
  42     EXCP_IRQ,
  43     EXCP_SYSTEMCALL
  44 };
  45
  46 /* Registers */
  47 enum {
  48     R_R0 = 0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R10,
  49     R_R11, R_R12, R_R13, R_R14, R_R15, R_R16, R_R17, R_R18, R_R19, R_R20,
  50     R_R21, R_R22, R_R23, R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30,
  51     R_R31
  52 };
  53
  54 /* Register aliases */
  55 enum {
  56     R_GP = R_R26,
  57     R_FP = R_R27,
  58     R_SP = R_R28,
  59     R_RA = R_R29,
  60     R_EA = R_R30,
  61     R_BA = R_R31
  62 };
  63
  64 /* IE flags */
  65 enum {
  66     IE_IE  = (1<<0),
  67     IE_EIE = (1<<1),
  68     IE_BIE = (1<<2),
  69 };
  70
  71 /* DC flags */
  72 enum {
  73     DC_SS  = (1<<0),
  74     DC_RE  = (1<<1),
  75     DC_C0  = (1<<2),
  76     DC_C1  = (1<<3),
  77     DC_C2  = (1<<4),
  78     DC_C3  = (1<<5),
  79 };
  80
  81 /* CFG mask */
  82 enum {
  83     CFG_M         = (1<<0),
  84     CFG_D         = (1<<1),
  85     CFG_S         = (1<<2),
  86     CFG_U         = (1<<3),
  87     CFG_X         = (1<<4),
  88     CFG_CC        = (1<<5),
  89     CFG_IC        = (1<<6),
  90     CFG_DC        = (1<<7),
  91     CFG_G         = (1<<8),
  92     CFG_H         = (1<<9),
  93     CFG_R         = (1<<10),
  94     CFG_J         = (1<<11),
  95     CFG_INT_SHIFT = 12,
  96     CFG_BP_SHIFT  = 18,
  97     CFG_WP_SHIFT  = 22,
  98     CFG_REV_SHIFT = 26,
  99 };
 100
 101 /* CSRs */
 102 enum {
 103     CSR_IE   = 0x00,
 104     CSR_IM   = 0x01,
 105     CSR_IP   = 0x02,
 106     CSR_ICC  = 0x03,
 107     CSR_DCC  = 0x04,
 108     CSR_CC   = 0x05,
 109     CSR_CFG  = 0x06,
 110     CSR_EBA  = 0x07,
 111     CSR_DC   = 0x08,
 112     CSR_DEBA = 0x09,
 113     CSR_JTX  = 0x0e,
 114     CSR_JRX  = 0x0f,
 115     CSR_BP0  = 0x10,
 116     CSR_BP1  = 0x11,
 117     CSR_BP2  = 0x12,
 118     CSR_BP3  = 0x13,
 119     CSR_WP0  = 0x18,
 120     CSR_WP1  = 0x19,
 121     CSR_WP2  = 0x1a,
 122     CSR_WP3  = 0x1b,
 123 };
 124
 125 enum {
 126     LM32_FEATURE_MULTIPLY     =  1,
 127     LM32_FEATURE_DIVIDE       =  2,
 128     LM32_FEATURE_SHIFT        =  4,
 129     LM32_FEATURE_SIGN_EXTEND  =  8,
 130     LM32_FEATURE_I_CACHE      = 16,
 131     LM32_FEATURE_D_CACHE      = 32,
 132     LM32_FEATURE_CYCLE_COUNT  = 64,
 133 };
 134
 135 enum {
 136     LM32_FLAG_IGNORE_MSB = 1,
 137 };
 138
 139 struct CPULM32State {
 140     /* general registers */
 141     uint32_t regs[32];
 142
 143     /* special registers */
 144     uint32_t pc;        /* program counter */
 145     uint32_t ie;        /* interrupt enable */
 146     uint32_t icc;       /* instruction cache control */
 147     uint32_t dcc;       /* data cache control */
 148     uint32_t cc;        /* cycle counter */
 149     uint32_t cfg;       /* configuration */
 150
 151     /* debug registers */
 152     uint32_t dc;        /* debug control */
 153     uint32_t bp[4];     /* breakpoints */
 154     uint32_t wp[4];     /* watchpoints */
 155
 156     struct CPUBreakpoint *cpu_breakpoint[4];
 157     struct CPUWatchpoint *cpu_watchpoint[4];
 158
 159     /* Fields up to this point are cleared by a CPU reset */
 160     struct {} end_reset_fields;
 161
 162     CPU_COMMON
 163
 164     /* Fields from here on are preserved across CPU reset. */
 165     uint32_t eba;       /* exception base address */
 166     uint32_t deba;      /* debug exception base address */
 167
 168     /* interrupt controller handle for callbacks */
 169     DeviceState *pic_state;
 170     /* JTAG UART handle for callbacks */
 171     DeviceState *juart_state;
 172
 173     /* processor core features */
 174     uint32_t flags;
 175
 176 };
 177
 178 /**
 179  * LM32CPU:
 180  * @env: #CPULM32State
 181  *
 182  * A LatticeMico32 CPU.
 183  */
 184 struct LM32CPU {
 185     /*< private >*/
 186     CPUState parent_obj;
 187     /*< public >*/
 188
 189     CPULM32State env;
 190
 191     uint32_t revision;
 192     uint8_t num_interrupts;
 193     uint8_t num_breakpoints;
 194     uint8_t num_watchpoints;
 195     uint32_t features;
 196 };
 197
 198 static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env)
 199 {
 200     return container_of(env, LM32CPU, env);
 201 }
 202
 203 #define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e))
 204
 205 #define ENV_OFFSET offsetof(LM32CPU, env)
 206
 207 #ifndef CONFIG_USER_ONLY
 208 extern const struct VMStateDescription vmstate_lm32_cpu;
 209 #endif
 210
 211 void lm32_cpu_do_interrupt(CPUState *cpu);
 212 bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req);
 213 void lm32_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 214 hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 215 int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 216 int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 217
 218 typedef enum {
 219     LM32_WP_DISABLED = 0,
 220     LM32_WP_READ,
 221     LM32_WP_WRITE,
 222     LM32_WP_READ_WRITE,
 223 } lm32_wp_t;
 224
 225 static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx)
 226 {
 227     assert(idx < 4);
 228     return (dc >> (idx+1)*2) & 0x3;
 229 }
 230
 231 /* you can call this signal handler from your SIGBUS and SIGSEGV
 232    signal handlers to inform the virtual CPU of exceptions. non zero
 233    is returned if the signal was handled by the virtual CPU.  */
 234 int cpu_lm32_signal_handler(int host_signum, void *pinfo,
 235                           void *puc);
 236 void lm32_cpu_list(void);
 237 void lm32_translate_init(void);
 238 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
 239 void QEMU_NORETURN raise_exception(CPULM32State *env, int index);
 240 void lm32_debug_excp_handler(CPUState *cs);
 241 void lm32_breakpoint_insert(CPULM32State *env, int index, target_ulong address);
 242 void lm32_breakpoint_remove(CPULM32State *env, int index);
 243 void lm32_watchpoint_insert(CPULM32State *env, int index, target_ulong address,
 244         lm32_wp_t wp_type);
 245 void lm32_watchpoint_remove(CPULM32State *env, int index);
 246 bool lm32_cpu_do_semihosting(CPUState *cs);
 247
 248 #define LM32_CPU_TYPE_SUFFIX "-" TYPE_LM32_CPU
 249 #define LM32_CPU_TYPE_NAME(model) model LM32_CPU_TYPE_SUFFIX
 250 #define CPU_RESOLVING_TYPE TYPE_LM32_CPU
 251
 252 #define cpu_list lm32_cpu_list
 253 #define cpu_signal_handler cpu_lm32_signal_handler
 254
 255 bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 256                        MMUAccessType access_type, int mmu_idx,
 257                        bool probe, uintptr_t retaddr);
 258
 259 typedef CPULM32State CPUArchState;
 260 typedef LM32CPU ArchCPU;
 261
 262 #include "exec/cpu-all.h"
 263
 264 static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
 265                                         target_ulong *cs_base, uint32_t *flags)
 266 {
 267     *pc = env->pc;
 268     *cs_base = 0;
 269     *flags = 0;
 270 }
 271
 272 #endif