2 * LatticeMico32 virtual CPU header.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
25 #include "exec/cpu-defs.h"
27 typedef struct CPULM32State CPULM32State
;
29 static inline int cpu_mmu_index(CPULM32State
*env
, bool ifetch
)
34 /* Exceptions indices */
48 R_R0
= 0, R_R1
, R_R2
, R_R3
, R_R4
, R_R5
, R_R6
, R_R7
, R_R8
, R_R9
, R_R10
,
49 R_R11
, R_R12
, R_R13
, R_R14
, R_R15
, R_R16
, R_R17
, R_R18
, R_R19
, R_R20
,
50 R_R21
, R_R22
, R_R23
, R_R24
, R_R25
, R_R26
, R_R27
, R_R28
, R_R29
, R_R30
,
54 /* Register aliases */
126 LM32_FEATURE_MULTIPLY
= 1,
127 LM32_FEATURE_DIVIDE
= 2,
128 LM32_FEATURE_SHIFT
= 4,
129 LM32_FEATURE_SIGN_EXTEND
= 8,
130 LM32_FEATURE_I_CACHE
= 16,
131 LM32_FEATURE_D_CACHE
= 32,
132 LM32_FEATURE_CYCLE_COUNT
= 64,
136 LM32_FLAG_IGNORE_MSB
= 1,
139 struct CPULM32State
{
140 /* general registers */
143 /* special registers */
144 uint32_t pc
; /* program counter */
145 uint32_t ie
; /* interrupt enable */
146 uint32_t icc
; /* instruction cache control */
147 uint32_t dcc
; /* data cache control */
148 uint32_t cc
; /* cycle counter */
149 uint32_t cfg
; /* configuration */
151 /* debug registers */
152 uint32_t dc
; /* debug control */
153 uint32_t bp
[4]; /* breakpoints */
154 uint32_t wp
[4]; /* watchpoints */
156 struct CPUBreakpoint
*cpu_breakpoint
[4];
157 struct CPUWatchpoint
*cpu_watchpoint
[4];
159 /* Fields up to this point are cleared by a CPU reset */
160 struct {} end_reset_fields
;
162 /* Fields from here on are preserved across CPU reset. */
163 uint32_t eba
; /* exception base address */
164 uint32_t deba
; /* debug exception base address */
166 /* interrupt controller handle for callbacks */
167 DeviceState
*pic_state
;
168 /* JTAG UART handle for callbacks */
169 DeviceState
*juart_state
;
171 /* processor core features */
178 * @env: #CPULM32State
180 * A LatticeMico32 CPU.
187 CPUNegativeOffsetState neg
;
191 uint8_t num_interrupts
;
192 uint8_t num_breakpoints
;
193 uint8_t num_watchpoints
;
198 #ifndef CONFIG_USER_ONLY
199 extern const struct VMStateDescription vmstate_lm32_cpu
;
202 void lm32_cpu_do_interrupt(CPUState
*cpu
);
203 bool lm32_cpu_exec_interrupt(CPUState
*cs
, int int_req
);
204 void lm32_cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
205 hwaddr
lm32_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
206 int lm32_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
207 int lm32_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
210 LM32_WP_DISABLED
= 0,
216 static inline lm32_wp_t
lm32_wp_type(uint32_t dc
, int idx
)
219 return (dc
>> (idx
+1)*2) & 0x3;
222 /* you can call this signal handler from your SIGBUS and SIGSEGV
223 signal handlers to inform the virtual CPU of exceptions. non zero
224 is returned if the signal was handled by the virtual CPU. */
225 int cpu_lm32_signal_handler(int host_signum
, void *pinfo
,
227 void lm32_cpu_list(void);
228 void lm32_translate_init(void);
229 void cpu_lm32_set_phys_msb_ignore(CPULM32State
*env
, int value
);
230 void QEMU_NORETURN
raise_exception(CPULM32State
*env
, int index
);
231 void lm32_debug_excp_handler(CPUState
*cs
);
232 void lm32_breakpoint_insert(CPULM32State
*env
, int index
, target_ulong address
);
233 void lm32_breakpoint_remove(CPULM32State
*env
, int index
);
234 void lm32_watchpoint_insert(CPULM32State
*env
, int index
, target_ulong address
,
236 void lm32_watchpoint_remove(CPULM32State
*env
, int index
);
237 bool lm32_cpu_do_semihosting(CPUState
*cs
);
239 #define LM32_CPU_TYPE_SUFFIX "-" TYPE_LM32_CPU
240 #define LM32_CPU_TYPE_NAME(model) model LM32_CPU_TYPE_SUFFIX
241 #define CPU_RESOLVING_TYPE TYPE_LM32_CPU
243 #define cpu_list lm32_cpu_list
244 #define cpu_signal_handler cpu_lm32_signal_handler
246 bool lm32_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
247 MMUAccessType access_type
, int mmu_idx
,
248 bool probe
, uintptr_t retaddr
);
250 typedef CPULM32State CPUArchState
;
251 typedef LM32CPU ArchCPU
;
253 #include "exec/cpu-all.h"
255 static inline void cpu_get_tb_cpu_state(CPULM32State
*env
, target_ulong
*pc
,
256 target_ulong
*cs_base
, uint32_t *flags
)