1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2021 Loongson Technology Corporation Limited
8 #include "qemu/osdep.h"
10 #include "qemu/qemu-print.h"
11 #include "qapi/error.h"
12 #include "qemu/module.h"
13 #include "sysemu/qtest.h"
14 #include "exec/exec-all.h"
15 #include "qapi/qapi-commands-machine-target.h"
17 #include "internals.h"
18 #include "fpu/softfloat-helpers.h"
21 const char * const regnames
[32] = {
22 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
23 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
24 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
25 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
28 const char * const fregnames
[32] = {
29 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
30 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
31 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
32 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
35 static const char * const excp_names
[] = {
36 [EXCCODE_INT
] = "Interrupt",
37 [EXCCODE_PIL
] = "Page invalid exception for load",
38 [EXCCODE_PIS
] = "Page invalid exception for store",
39 [EXCCODE_PIF
] = "Page invalid exception for fetch",
40 [EXCCODE_PME
] = "Page modified exception",
41 [EXCCODE_PNR
] = "Page Not Readable exception",
42 [EXCCODE_PNX
] = "Page Not Executable exception",
43 [EXCCODE_PPI
] = "Page Privilege error",
44 [EXCCODE_ADEF
] = "Address error for instruction fetch",
45 [EXCCODE_ADEM
] = "Address error for Memory access",
46 [EXCCODE_SYS
] = "Syscall",
47 [EXCCODE_BRK
] = "Break",
48 [EXCCODE_INE
] = "Instruction Non-Existent",
49 [EXCCODE_IPE
] = "Instruction privilege error",
50 [EXCCODE_FPE
] = "Floating Point Exception",
51 [EXCCODE_DBP
] = "Debug breakpoint",
54 const char *loongarch_exception_name(int32_t exception
)
56 assert(excp_names
[exception
]);
57 return excp_names
[exception
];
60 void G_NORETURN
do_raise_exception(CPULoongArchState
*env
,
64 CPUState
*cs
= env_cpu(env
);
66 qemu_log_mask(CPU_LOG_INT
, "%s: %d (%s)\n",
69 loongarch_exception_name(exception
));
70 cs
->exception_index
= exception
;
72 cpu_loop_exit_restore(cs
, pc
);
75 static void loongarch_cpu_set_pc(CPUState
*cs
, vaddr value
)
77 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
78 CPULoongArchState
*env
= &cpu
->env
;
83 void loongarch_cpu_set_irq(void *opaque
, int irq
, int level
)
85 LoongArchCPU
*cpu
= opaque
;
86 CPULoongArchState
*env
= &cpu
->env
;
87 CPUState
*cs
= CPU(cpu
);
89 if (irq
< 0 || irq
>= N_IRQS
) {
93 env
->CSR_ESTAT
= deposit64(env
->CSR_ESTAT
, irq
, 1, level
!= 0);
95 if (FIELD_EX64(env
->CSR_ESTAT
, CSR_ESTAT
, IS
)) {
96 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
98 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
102 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState
*env
)
106 ret
= (FIELD_EX64(env
->CSR_CRMD
, CSR_CRMD
, IE
) &&
107 !(FIELD_EX64(env
->CSR_DBG
, CSR_DBG
, DST
)));
112 /* Check if there is pending and not masked out interrupt */
113 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState
*env
)
119 pending
= FIELD_EX64(env
->CSR_ESTAT
, CSR_ESTAT
, IS
);
120 status
= FIELD_EX64(env
->CSR_ECFG
, CSR_ECFG
, LIE
);
122 r
= (pending
& status
) != 0;
126 static void loongarch_cpu_do_interrupt(CPUState
*cs
)
128 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
129 CPULoongArchState
*env
= &cpu
->env
;
130 bool update_badinstr
= 1;
133 bool tlbfill
= FIELD_EX64(env
->CSR_TLBRERA
, CSR_TLBRERA
, ISTLBR
);
134 uint32_t vec_size
= FIELD_EX64(env
->CSR_ECFG
, CSR_ECFG
, VS
);
136 if (cs
->exception_index
!= EXCCODE_INT
) {
137 if (cs
->exception_index
< 0 ||
138 cs
->exception_index
> ARRAY_SIZE(excp_names
)) {
141 name
= excp_names
[cs
->exception_index
];
144 qemu_log_mask(CPU_LOG_INT
,
145 "%s enter: pc " TARGET_FMT_lx
" ERA " TARGET_FMT_lx
146 " TLBRERA " TARGET_FMT_lx
" %s exception\n", __func__
,
147 env
->pc
, env
->CSR_ERA
, env
->CSR_TLBRERA
, name
);
150 switch (cs
->exception_index
) {
152 env
->CSR_DBG
= FIELD_DP64(env
->CSR_DBG
, CSR_DBG
, DCL
, 1);
153 env
->CSR_DBG
= FIELD_DP64(env
->CSR_DBG
, CSR_DBG
, ECODE
, 0xC);
156 env
->CSR_DERA
= env
->pc
;
157 env
->CSR_DBG
= FIELD_DP64(env
->CSR_DBG
, CSR_DBG
, DST
, 1);
158 env
->pc
= env
->CSR_EENTRY
+ 0x480;
161 if (FIELD_EX64(env
->CSR_DBG
, CSR_DBG
, DST
)) {
162 env
->CSR_DBG
= FIELD_DP64(env
->CSR_DBG
, CSR_DBG
, DEI
, 1);
167 cause
= cs
->exception_index
;
182 cause
= cs
->exception_index
;
185 qemu_log("Error: exception(%d) '%s' has not been supported\n",
186 cs
->exception_index
, excp_names
[cs
->exception_index
]);
190 if (update_badinstr
) {
191 env
->CSR_BADI
= cpu_ldl_code(env
, env
->pc
);
194 /* Save PLV and IE */
196 env
->CSR_TLBRPRMD
= FIELD_DP64(env
->CSR_TLBRPRMD
, CSR_TLBRPRMD
, PPLV
,
197 FIELD_EX64(env
->CSR_CRMD
,
199 env
->CSR_TLBRPRMD
= FIELD_DP64(env
->CSR_TLBRPRMD
, CSR_TLBRPRMD
, PIE
,
200 FIELD_EX64(env
->CSR_CRMD
, CSR_CRMD
, IE
));
201 /* set the DA mode */
202 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, DA
, 1);
203 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, PG
, 0);
204 env
->CSR_TLBRERA
= FIELD_DP64(env
->CSR_TLBRERA
, CSR_TLBRERA
,
207 env
->CSR_ESTAT
= FIELD_DP64(env
->CSR_ESTAT
, CSR_ESTAT
, ECODE
, cause
);
208 env
->CSR_PRMD
= FIELD_DP64(env
->CSR_PRMD
, CSR_PRMD
, PPLV
,
209 FIELD_EX64(env
->CSR_CRMD
, CSR_CRMD
, PLV
));
210 env
->CSR_PRMD
= FIELD_DP64(env
->CSR_PRMD
, CSR_PRMD
, PIE
,
211 FIELD_EX64(env
->CSR_CRMD
, CSR_CRMD
, IE
));
212 env
->CSR_ERA
= env
->pc
;
215 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, PLV
, 0);
216 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, IE
, 0);
218 if (cs
->exception_index
== EXCCODE_INT
) {
221 uint32_t pending
= FIELD_EX64(env
->CSR_ESTAT
, CSR_ESTAT
, IS
);
222 pending
&= FIELD_EX64(env
->CSR_ECFG
, CSR_ECFG
, LIE
);
224 /* Find the highest-priority interrupt. */
225 vector
= 31 - clz32(pending
);
226 env
->pc
= env
->CSR_EENTRY
+ (EXCCODE_EXTERNAL_INT
+ vector
) * vec_size
;
227 qemu_log_mask(CPU_LOG_INT
,
228 "%s: PC " TARGET_FMT_lx
" ERA " TARGET_FMT_lx
229 " cause %d\n" " A " TARGET_FMT_lx
" D "
230 TARGET_FMT_lx
" vector = %d ExC " TARGET_FMT_lx
"ExS"
232 __func__
, env
->pc
, env
->CSR_ERA
,
233 cause
, env
->CSR_BADV
, env
->CSR_DERA
, vector
,
234 env
->CSR_ECFG
, env
->CSR_ESTAT
);
237 env
->pc
= env
->CSR_TLBRENTRY
;
239 env
->pc
= env
->CSR_EENTRY
;
240 env
->pc
+= cause
* vec_size
;
242 qemu_log_mask(CPU_LOG_INT
,
243 "%s: PC " TARGET_FMT_lx
" ERA " TARGET_FMT_lx
244 " cause %d%s\n, ESTAT " TARGET_FMT_lx
245 " EXCFG " TARGET_FMT_lx
" BADVA " TARGET_FMT_lx
246 "BADI " TARGET_FMT_lx
" SYS_NUM " TARGET_FMT_lu
247 " cpu %d asid " TARGET_FMT_lx
"\n", __func__
, env
->pc
,
248 tlbfill
? env
->CSR_TLBRERA
: env
->CSR_ERA
,
249 cause
, tlbfill
? "(refill)" : "", env
->CSR_ESTAT
,
251 tlbfill
? env
->CSR_TLBRBADV
: env
->CSR_BADV
,
252 env
->CSR_BADI
, env
->gpr
[11], cs
->cpu_index
,
255 cs
->exception_index
= -1;
258 static void loongarch_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
259 vaddr addr
, unsigned size
,
260 MMUAccessType access_type
,
261 int mmu_idx
, MemTxAttrs attrs
,
262 MemTxResult response
,
265 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
266 CPULoongArchState
*env
= &cpu
->env
;
268 if (access_type
== MMU_INST_FETCH
) {
269 do_raise_exception(env
, EXCCODE_ADEF
, retaddr
);
271 do_raise_exception(env
, EXCCODE_ADEM
, retaddr
);
275 static bool loongarch_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
277 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
278 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
279 CPULoongArchState
*env
= &cpu
->env
;
281 if (cpu_loongarch_hw_interrupts_enabled(env
) &&
282 cpu_loongarch_hw_interrupts_pending(env
)) {
284 cs
->exception_index
= EXCCODE_INT
;
285 loongarch_cpu_do_interrupt(cs
);
293 static void loongarch_cpu_synchronize_from_tb(CPUState
*cs
,
294 const TranslationBlock
*tb
)
296 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
297 CPULoongArchState
*env
= &cpu
->env
;
301 #endif /* CONFIG_TCG */
303 static bool loongarch_cpu_has_work(CPUState
*cs
)
305 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
306 CPULoongArchState
*env
= &cpu
->env
;
307 bool has_work
= false;
309 if ((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
310 cpu_loongarch_hw_interrupts_pending(env
)) {
317 static void loongarch_la464_initfn(Object
*obj
)
319 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
320 CPULoongArchState
*env
= &cpu
->env
;
323 for (i
= 0; i
< 21; i
++) {
324 env
->cpucfg
[i
] = 0x0;
327 env
->cpucfg
[0] = 0x14c010; /* PRID */
330 data
= FIELD_DP32(data
, CPUCFG1
, ARCH
, 2);
331 data
= FIELD_DP32(data
, CPUCFG1
, PGMMU
, 1);
332 data
= FIELD_DP32(data
, CPUCFG1
, IOCSR
, 1);
333 data
= FIELD_DP32(data
, CPUCFG1
, PALEN
, 0x2f);
334 data
= FIELD_DP32(data
, CPUCFG1
, VALEN
, 0x2f);
335 data
= FIELD_DP32(data
, CPUCFG1
, UAL
, 1);
336 data
= FIELD_DP32(data
, CPUCFG1
, RI
, 1);
337 data
= FIELD_DP32(data
, CPUCFG1
, EP
, 1);
338 data
= FIELD_DP32(data
, CPUCFG1
, RPLV
, 1);
339 data
= FIELD_DP32(data
, CPUCFG1
, HP
, 1);
340 data
= FIELD_DP32(data
, CPUCFG1
, IOCSR_BRD
, 1);
341 env
->cpucfg
[1] = data
;
344 data
= FIELD_DP32(data
, CPUCFG2
, FP
, 1);
345 data
= FIELD_DP32(data
, CPUCFG2
, FP_SP
, 1);
346 data
= FIELD_DP32(data
, CPUCFG2
, FP_DP
, 1);
347 data
= FIELD_DP32(data
, CPUCFG2
, FP_VER
, 1);
348 data
= FIELD_DP32(data
, CPUCFG2
, LLFTP
, 1);
349 data
= FIELD_DP32(data
, CPUCFG2
, LLFTP_VER
, 1);
350 data
= FIELD_DP32(data
, CPUCFG2
, LAM
, 1);
351 env
->cpucfg
[2] = data
;
353 env
->cpucfg
[4] = 100 * 1000 * 1000; /* Crystal frequency */
356 data
= FIELD_DP32(data
, CPUCFG5
, CC_MUL
, 1);
357 data
= FIELD_DP32(data
, CPUCFG5
, CC_DIV
, 1);
358 env
->cpucfg
[5] = data
;
361 data
= FIELD_DP32(data
, CPUCFG16
, L1_IUPRE
, 1);
362 data
= FIELD_DP32(data
, CPUCFG16
, L1_DPRE
, 1);
363 data
= FIELD_DP32(data
, CPUCFG16
, L2_IUPRE
, 1);
364 data
= FIELD_DP32(data
, CPUCFG16
, L2_IUUNIFY
, 1);
365 data
= FIELD_DP32(data
, CPUCFG16
, L2_IUPRIV
, 1);
366 data
= FIELD_DP32(data
, CPUCFG16
, L3_IUPRE
, 1);
367 data
= FIELD_DP32(data
, CPUCFG16
, L3_IUUNIFY
, 1);
368 data
= FIELD_DP32(data
, CPUCFG16
, L3_IUINCL
, 1);
369 env
->cpucfg
[16] = data
;
372 data
= FIELD_DP32(data
, CPUCFG17
, L1IU_WAYS
, 3);
373 data
= FIELD_DP32(data
, CPUCFG17
, L1IU_SETS
, 8);
374 data
= FIELD_DP32(data
, CPUCFG17
, L1IU_SIZE
, 6);
375 env
->cpucfg
[17] = data
;
378 data
= FIELD_DP32(data
, CPUCFG18
, L1D_WAYS
, 3);
379 data
= FIELD_DP32(data
, CPUCFG18
, L1D_SETS
, 8);
380 data
= FIELD_DP32(data
, CPUCFG18
, L1D_SIZE
, 6);
381 env
->cpucfg
[18] = data
;
384 data
= FIELD_DP32(data
, CPUCFG19
, L2IU_WAYS
, 15);
385 data
= FIELD_DP32(data
, CPUCFG19
, L2IU_SETS
, 8);
386 data
= FIELD_DP32(data
, CPUCFG19
, L2IU_SIZE
, 6);
387 env
->cpucfg
[19] = data
;
390 data
= FIELD_DP32(data
, CPUCFG20
, L3IU_WAYS
, 15);
391 data
= FIELD_DP32(data
, CPUCFG20
, L3IU_SETS
, 14);
392 data
= FIELD_DP32(data
, CPUCFG20
, L3IU_SETS
, 6);
393 env
->cpucfg
[20] = data
;
395 env
->CSR_ASID
= FIELD_DP64(0, CSR_ASID
, ASIDBITS
, 0xa);
398 static void loongarch_cpu_list_entry(gpointer data
, gpointer user_data
)
400 const char *typename
= object_class_get_name(OBJECT_CLASS(data
));
402 qemu_printf("%s\n", typename
);
405 void loongarch_cpu_list(void)
408 list
= object_class_get_list_sorted(TYPE_LOONGARCH_CPU
, false);
409 g_slist_foreach(list
, loongarch_cpu_list_entry
, NULL
);
413 static void loongarch_cpu_reset(DeviceState
*dev
)
415 CPUState
*cs
= CPU(dev
);
416 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
417 LoongArchCPUClass
*lacc
= LOONGARCH_CPU_GET_CLASS(cpu
);
418 CPULoongArchState
*env
= &cpu
->env
;
420 lacc
->parent_reset(dev
);
422 env
->fcsr0_mask
= FCSR0_M1
| FCSR0_M2
| FCSR0_M3
;
426 /* Set csr registers value after reset */
427 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, PLV
, 0);
428 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, IE
, 0);
429 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, DA
, 1);
430 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, PG
, 0);
431 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, DATF
, 1);
432 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, DATM
, 1);
434 env
->CSR_EUEN
= FIELD_DP64(env
->CSR_EUEN
, CSR_EUEN
, FPE
, 0);
435 env
->CSR_EUEN
= FIELD_DP64(env
->CSR_EUEN
, CSR_EUEN
, SXE
, 0);
436 env
->CSR_EUEN
= FIELD_DP64(env
->CSR_EUEN
, CSR_EUEN
, ASXE
, 0);
437 env
->CSR_EUEN
= FIELD_DP64(env
->CSR_EUEN
, CSR_EUEN
, BTE
, 0);
441 env
->CSR_ECFG
= FIELD_DP64(env
->CSR_ECFG
, CSR_ECFG
, VS
, 0);
442 env
->CSR_ECFG
= FIELD_DP64(env
->CSR_ECFG
, CSR_ECFG
, LIE
, 0);
444 env
->CSR_ESTAT
= env
->CSR_ESTAT
& (~MAKE_64BIT_MASK(0, 2));
445 env
->CSR_RVACFG
= FIELD_DP64(env
->CSR_RVACFG
, CSR_RVACFG
, RBITS
, 0);
446 env
->CSR_TCFG
= FIELD_DP64(env
->CSR_TCFG
, CSR_TCFG
, EN
, 0);
447 env
->CSR_LLBCTL
= FIELD_DP64(env
->CSR_LLBCTL
, CSR_LLBCTL
, KLO
, 0);
448 env
->CSR_TLBRERA
= FIELD_DP64(env
->CSR_TLBRERA
, CSR_TLBRERA
, ISTLBR
, 0);
449 env
->CSR_MERRCTL
= FIELD_DP64(env
->CSR_MERRCTL
, CSR_MERRCTL
, ISMERR
, 0);
451 env
->CSR_PRCFG3
= FIELD_DP64(env
->CSR_PRCFG3
, CSR_PRCFG3
, TLB_TYPE
, 2);
452 env
->CSR_PRCFG3
= FIELD_DP64(env
->CSR_PRCFG3
, CSR_PRCFG3
, MTLB_ENTRY
, 63);
453 env
->CSR_PRCFG3
= FIELD_DP64(env
->CSR_PRCFG3
, CSR_PRCFG3
, STLB_WAYS
, 7);
454 env
->CSR_PRCFG3
= FIELD_DP64(env
->CSR_PRCFG3
, CSR_PRCFG3
, STLB_SETS
, 8);
456 for (n
= 0; n
< 4; n
++) {
457 env
->CSR_DMW
[n
] = FIELD_DP64(env
->CSR_DMW
[n
], CSR_DMW
, PLV0
, 0);
458 env
->CSR_DMW
[n
] = FIELD_DP64(env
->CSR_DMW
[n
], CSR_DMW
, PLV1
, 0);
459 env
->CSR_DMW
[n
] = FIELD_DP64(env
->CSR_DMW
[n
], CSR_DMW
, PLV2
, 0);
460 env
->CSR_DMW
[n
] = FIELD_DP64(env
->CSR_DMW
[n
], CSR_DMW
, PLV3
, 0);
463 env
->pc
= 0x1c000000;
465 restore_fp_status(env
);
466 cs
->exception_index
= -1;
469 static void loongarch_cpu_disas_set_info(CPUState
*s
, disassemble_info
*info
)
471 info
->print_insn
= print_insn_loongarch
;
474 static void loongarch_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
476 CPUState
*cs
= CPU(dev
);
477 LoongArchCPUClass
*lacc
= LOONGARCH_CPU_GET_CLASS(dev
);
478 Error
*local_err
= NULL
;
480 cpu_exec_realizefn(cs
, &local_err
);
481 if (local_err
!= NULL
) {
482 error_propagate(errp
, local_err
);
489 lacc
->parent_realize(dev
, errp
);
492 static void loongarch_cpu_init(Object
*obj
)
494 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
496 cpu_set_cpustate_pointers(cpu
);
497 qdev_init_gpio_in(DEVICE(cpu
), loongarch_cpu_set_irq
, N_IRQS
);
500 static ObjectClass
*loongarch_cpu_class_by_name(const char *cpu_model
)
505 typename
= g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model
);
506 oc
= object_class_by_name(typename
);
511 void loongarch_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
513 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
514 CPULoongArchState
*env
= &cpu
->env
;
517 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
518 qemu_fprintf(f
, " FCSR0 0x%08x fp_status 0x%02x\n", env
->fcsr0
,
519 get_float_exception_flags(&env
->fp_status
));
522 for (i
= 0; i
< 32; i
++) {
524 qemu_fprintf(f
, " GPR%02d:", i
);
526 qemu_fprintf(f
, " %s %016" PRIx64
, regnames
[i
], env
->gpr
[i
]);
528 qemu_fprintf(f
, "\n");
532 qemu_fprintf(f
, "CRMD=%016" PRIx64
"\n", env
->CSR_CRMD
);
533 qemu_fprintf(f
, "PRMD=%016" PRIx64
"\n", env
->CSR_PRMD
);
534 qemu_fprintf(f
, "EUEN=%016" PRIx64
"\n", env
->CSR_EUEN
);
535 qemu_fprintf(f
, "ESTAT=%016" PRIx64
"\n", env
->CSR_ESTAT
);
536 qemu_fprintf(f
, "ERA=%016" PRIx64
"\n", env
->CSR_ERA
);
537 qemu_fprintf(f
, "BADV=%016" PRIx64
"\n", env
->CSR_BADV
);
538 qemu_fprintf(f
, "BADI=%016" PRIx64
"\n", env
->CSR_BADI
);
539 qemu_fprintf(f
, "EENTRY=%016" PRIx64
"\n", env
->CSR_EENTRY
);
540 qemu_fprintf(f
, "PRCFG1=%016" PRIx64
", PRCFG2=%016" PRIx64
","
541 " PRCFG3=%016" PRIx64
"\n",
542 env
->CSR_PRCFG1
, env
->CSR_PRCFG3
, env
->CSR_PRCFG3
);
543 qemu_fprintf(f
, "TLBRENTRY=%016" PRIx64
"\n", env
->CSR_TLBRENTRY
);
544 qemu_fprintf(f
, "TLBRBADV=%016" PRIx64
"\n", env
->CSR_TLBRBADV
);
545 qemu_fprintf(f
, "TLBRERA=%016" PRIx64
"\n", env
->CSR_TLBRERA
);
548 if (flags
& CPU_DUMP_FPU
) {
549 for (i
= 0; i
< 32; i
++) {
550 qemu_fprintf(f
, " %s %016" PRIx64
, fregnames
[i
], env
->fpr
[i
]);
552 qemu_fprintf(f
, "\n");
559 #include "hw/core/tcg-cpu-ops.h"
561 static struct TCGCPUOps loongarch_tcg_ops
= {
562 .initialize
= loongarch_translate_init
,
563 .synchronize_from_tb
= loongarch_cpu_synchronize_from_tb
,
565 .tlb_fill
= loongarch_cpu_tlb_fill
,
566 .cpu_exec_interrupt
= loongarch_cpu_exec_interrupt
,
567 .do_interrupt
= loongarch_cpu_do_interrupt
,
568 .do_transaction_failed
= loongarch_cpu_do_transaction_failed
,
570 #endif /* CONFIG_TCG */
572 #include "hw/core/sysemu-cpu-ops.h"
574 static const struct SysemuCPUOps loongarch_sysemu_ops
= {
575 .get_phys_page_debug
= loongarch_cpu_get_phys_page_debug
,
578 static void loongarch_cpu_class_init(ObjectClass
*c
, void *data
)
580 LoongArchCPUClass
*lacc
= LOONGARCH_CPU_CLASS(c
);
581 CPUClass
*cc
= CPU_CLASS(c
);
582 DeviceClass
*dc
= DEVICE_CLASS(c
);
584 device_class_set_parent_realize(dc
, loongarch_cpu_realizefn
,
585 &lacc
->parent_realize
);
586 device_class_set_parent_reset(dc
, loongarch_cpu_reset
, &lacc
->parent_reset
);
588 cc
->class_by_name
= loongarch_cpu_class_by_name
;
589 cc
->has_work
= loongarch_cpu_has_work
;
590 cc
->dump_state
= loongarch_cpu_dump_state
;
591 cc
->set_pc
= loongarch_cpu_set_pc
;
592 dc
->vmsd
= &vmstate_loongarch_cpu
;
593 cc
->sysemu_ops
= &loongarch_sysemu_ops
;
594 cc
->disas_set_info
= loongarch_cpu_disas_set_info
;
596 cc
->tcg_ops
= &loongarch_tcg_ops
;
600 #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
602 .parent = TYPE_LOONGARCH_CPU, \
603 .instance_init = initfn, \
604 .name = LOONGARCH_CPU_TYPE_NAME(model), \
607 static const TypeInfo loongarch_cpu_type_infos
[] = {
609 .name
= TYPE_LOONGARCH_CPU
,
611 .instance_size
= sizeof(LoongArchCPU
),
612 .instance_init
= loongarch_cpu_init
,
615 .class_size
= sizeof(LoongArchCPUClass
),
616 .class_init
= loongarch_cpu_class_init
,
618 DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn
),
621 DEFINE_TYPES(loongarch_cpu_type_infos
)
623 static void loongarch_cpu_add_definition(gpointer data
, gpointer user_data
)
625 ObjectClass
*oc
= data
;
626 CpuDefinitionInfoList
**cpu_list
= user_data
;
627 CpuDefinitionInfo
*info
= g_new0(CpuDefinitionInfo
, 1);
628 const char *typename
= object_class_get_name(oc
);
630 info
->name
= g_strndup(typename
,
631 strlen(typename
) - strlen("-" TYPE_LOONGARCH_CPU
));
632 info
->q_typename
= g_strdup(typename
);
634 QAPI_LIST_PREPEND(*cpu_list
, info
);
637 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
639 CpuDefinitionInfoList
*cpu_list
= NULL
;
642 list
= object_class_get_list(TYPE_LOONGARCH_CPU
, false);
643 g_slist_foreach(list
, loongarch_cpu_add_definition
, &cpu_list
);