1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2021 Loongson Technology Corporation Limited
8 #include "qemu/osdep.h"
10 #include "qemu/qemu-print.h"
11 #include "qapi/error.h"
12 #include "qemu/module.h"
13 #include "sysemu/qtest.h"
14 #include "sysemu/tcg.h"
15 #include "sysemu/kvm.h"
16 #include "kvm/kvm_loongarch.h"
17 #include "exec/exec-all.h"
19 #include "internals.h"
20 #include "fpu/softfloat-helpers.h"
22 #ifndef CONFIG_USER_ONLY
23 #include "sysemu/reset.h"
27 #include <linux/kvm.h>
30 #include "exec/cpu_ldst.h"
34 const char * const regnames
[32] = {
35 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
36 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
37 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
38 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
41 const char * const fregnames
[32] = {
42 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
43 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
44 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
45 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
48 static const char * const excp_names
[] = {
49 [EXCCODE_INT
] = "Interrupt",
50 [EXCCODE_PIL
] = "Page invalid exception for load",
51 [EXCCODE_PIS
] = "Page invalid exception for store",
52 [EXCCODE_PIF
] = "Page invalid exception for fetch",
53 [EXCCODE_PME
] = "Page modified exception",
54 [EXCCODE_PNR
] = "Page Not Readable exception",
55 [EXCCODE_PNX
] = "Page Not Executable exception",
56 [EXCCODE_PPI
] = "Page Privilege error",
57 [EXCCODE_ADEF
] = "Address error for instruction fetch",
58 [EXCCODE_ADEM
] = "Address error for Memory access",
59 [EXCCODE_SYS
] = "Syscall",
60 [EXCCODE_BRK
] = "Break",
61 [EXCCODE_INE
] = "Instruction Non-Existent",
62 [EXCCODE_IPE
] = "Instruction privilege error",
63 [EXCCODE_FPD
] = "Floating Point Disabled",
64 [EXCCODE_FPE
] = "Floating Point Exception",
65 [EXCCODE_DBP
] = "Debug breakpoint",
66 [EXCCODE_BCE
] = "Bound Check Exception",
67 [EXCCODE_SXD
] = "128 bit vector instructions Disable exception",
68 [EXCCODE_ASXD
] = "256 bit vector instructions Disable exception",
71 const char *loongarch_exception_name(int32_t exception
)
73 assert(excp_names
[exception
]);
74 return excp_names
[exception
];
77 void G_NORETURN
do_raise_exception(CPULoongArchState
*env
,
81 CPUState
*cs
= env_cpu(env
);
83 qemu_log_mask(CPU_LOG_INT
, "%s: %d (%s)\n",
86 loongarch_exception_name(exception
));
87 cs
->exception_index
= exception
;
89 cpu_loop_exit_restore(cs
, pc
);
92 static void loongarch_cpu_set_pc(CPUState
*cs
, vaddr value
)
94 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
95 CPULoongArchState
*env
= &cpu
->env
;
100 static vaddr
loongarch_cpu_get_pc(CPUState
*cs
)
102 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
103 CPULoongArchState
*env
= &cpu
->env
;
108 #ifndef CONFIG_USER_ONLY
109 #include "hw/loongarch/virt.h"
111 void loongarch_cpu_set_irq(void *opaque
, int irq
, int level
)
113 LoongArchCPU
*cpu
= opaque
;
114 CPULoongArchState
*env
= &cpu
->env
;
115 CPUState
*cs
= CPU(cpu
);
117 if (irq
< 0 || irq
>= N_IRQS
) {
122 kvm_loongarch_set_interrupt(cpu
, irq
, level
);
123 } else if (tcg_enabled()) {
124 env
->CSR_ESTAT
= deposit64(env
->CSR_ESTAT
, irq
, 1, level
!= 0);
125 if (FIELD_EX64(env
->CSR_ESTAT
, CSR_ESTAT
, IS
)) {
126 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
128 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
133 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState
*env
)
137 ret
= (FIELD_EX64(env
->CSR_CRMD
, CSR_CRMD
, IE
) &&
138 !(FIELD_EX64(env
->CSR_DBG
, CSR_DBG
, DST
)));
143 /* Check if there is pending and not masked out interrupt */
144 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState
*env
)
149 pending
= FIELD_EX64(env
->CSR_ESTAT
, CSR_ESTAT
, IS
);
150 status
= FIELD_EX64(env
->CSR_ECFG
, CSR_ECFG
, LIE
);
152 return (pending
& status
) != 0;
157 #ifndef CONFIG_USER_ONLY
158 static void loongarch_cpu_do_interrupt(CPUState
*cs
)
160 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
161 CPULoongArchState
*env
= &cpu
->env
;
162 bool update_badinstr
= 1;
165 bool tlbfill
= FIELD_EX64(env
->CSR_TLBRERA
, CSR_TLBRERA
, ISTLBR
);
166 uint32_t vec_size
= FIELD_EX64(env
->CSR_ECFG
, CSR_ECFG
, VS
);
168 if (cs
->exception_index
!= EXCCODE_INT
) {
169 if (cs
->exception_index
< 0 ||
170 cs
->exception_index
>= ARRAY_SIZE(excp_names
)) {
173 name
= excp_names
[cs
->exception_index
];
176 qemu_log_mask(CPU_LOG_INT
,
177 "%s enter: pc " TARGET_FMT_lx
" ERA " TARGET_FMT_lx
178 " TLBRERA " TARGET_FMT_lx
" %s exception\n", __func__
,
179 env
->pc
, env
->CSR_ERA
, env
->CSR_TLBRERA
, name
);
182 switch (cs
->exception_index
) {
184 env
->CSR_DBG
= FIELD_DP64(env
->CSR_DBG
, CSR_DBG
, DCL
, 1);
185 env
->CSR_DBG
= FIELD_DP64(env
->CSR_DBG
, CSR_DBG
, ECODE
, 0xC);
188 env
->CSR_DERA
= env
->pc
;
189 env
->CSR_DBG
= FIELD_DP64(env
->CSR_DBG
, CSR_DBG
, DST
, 1);
190 set_pc(env
, env
->CSR_EENTRY
+ 0x480);
193 if (FIELD_EX64(env
->CSR_DBG
, CSR_DBG
, DST
)) {
194 env
->CSR_DBG
= FIELD_DP64(env
->CSR_DBG
, CSR_DBG
, DEI
, 1);
200 cause
= cs
->exception_index
;
211 env
->CSR_BADV
= env
->pc
;
221 cause
= cs
->exception_index
;
224 qemu_log("Error: exception(%d) has not been supported\n",
225 cs
->exception_index
);
229 if (update_badinstr
) {
230 env
->CSR_BADI
= cpu_ldl_code(env
, env
->pc
);
233 /* Save PLV and IE */
235 env
->CSR_TLBRPRMD
= FIELD_DP64(env
->CSR_TLBRPRMD
, CSR_TLBRPRMD
, PPLV
,
236 FIELD_EX64(env
->CSR_CRMD
,
238 env
->CSR_TLBRPRMD
= FIELD_DP64(env
->CSR_TLBRPRMD
, CSR_TLBRPRMD
, PIE
,
239 FIELD_EX64(env
->CSR_CRMD
, CSR_CRMD
, IE
));
240 /* set the DA mode */
241 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, DA
, 1);
242 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, PG
, 0);
243 env
->CSR_TLBRERA
= FIELD_DP64(env
->CSR_TLBRERA
, CSR_TLBRERA
,
246 env
->CSR_ESTAT
= FIELD_DP64(env
->CSR_ESTAT
, CSR_ESTAT
, ECODE
,
247 EXCODE_MCODE(cause
));
248 env
->CSR_ESTAT
= FIELD_DP64(env
->CSR_ESTAT
, CSR_ESTAT
, ESUBCODE
,
249 EXCODE_SUBCODE(cause
));
250 env
->CSR_PRMD
= FIELD_DP64(env
->CSR_PRMD
, CSR_PRMD
, PPLV
,
251 FIELD_EX64(env
->CSR_CRMD
, CSR_CRMD
, PLV
));
252 env
->CSR_PRMD
= FIELD_DP64(env
->CSR_PRMD
, CSR_PRMD
, PIE
,
253 FIELD_EX64(env
->CSR_CRMD
, CSR_CRMD
, IE
));
254 env
->CSR_ERA
= env
->pc
;
257 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, PLV
, 0);
258 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, IE
, 0);
261 vec_size
= (1 << vec_size
) * 4;
264 if (cs
->exception_index
== EXCCODE_INT
) {
267 uint32_t pending
= FIELD_EX64(env
->CSR_ESTAT
, CSR_ESTAT
, IS
);
268 pending
&= FIELD_EX64(env
->CSR_ECFG
, CSR_ECFG
, LIE
);
270 /* Find the highest-priority interrupt. */
271 vector
= 31 - clz32(pending
);
272 set_pc(env
, env
->CSR_EENTRY
+ \
273 (EXCCODE_EXTERNAL_INT
+ vector
) * vec_size
);
274 qemu_log_mask(CPU_LOG_INT
,
275 "%s: PC " TARGET_FMT_lx
" ERA " TARGET_FMT_lx
276 " cause %d\n" " A " TARGET_FMT_lx
" D "
277 TARGET_FMT_lx
" vector = %d ExC " TARGET_FMT_lx
"ExS"
279 __func__
, env
->pc
, env
->CSR_ERA
,
280 cause
, env
->CSR_BADV
, env
->CSR_DERA
, vector
,
281 env
->CSR_ECFG
, env
->CSR_ESTAT
);
284 set_pc(env
, env
->CSR_TLBRENTRY
);
286 set_pc(env
, env
->CSR_EENTRY
+ EXCODE_MCODE(cause
) * vec_size
);
288 qemu_log_mask(CPU_LOG_INT
,
289 "%s: PC " TARGET_FMT_lx
" ERA " TARGET_FMT_lx
290 " cause %d%s\n, ESTAT " TARGET_FMT_lx
291 " EXCFG " TARGET_FMT_lx
" BADVA " TARGET_FMT_lx
292 "BADI " TARGET_FMT_lx
" SYS_NUM " TARGET_FMT_lu
293 " cpu %d asid " TARGET_FMT_lx
"\n", __func__
, env
->pc
,
294 tlbfill
? env
->CSR_TLBRERA
: env
->CSR_ERA
,
295 cause
, tlbfill
? "(refill)" : "", env
->CSR_ESTAT
,
297 tlbfill
? env
->CSR_TLBRBADV
: env
->CSR_BADV
,
298 env
->CSR_BADI
, env
->gpr
[11], cs
->cpu_index
,
301 cs
->exception_index
= -1;
304 static void loongarch_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
305 vaddr addr
, unsigned size
,
306 MMUAccessType access_type
,
307 int mmu_idx
, MemTxAttrs attrs
,
308 MemTxResult response
,
311 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
312 CPULoongArchState
*env
= &cpu
->env
;
314 if (access_type
== MMU_INST_FETCH
) {
315 do_raise_exception(env
, EXCCODE_ADEF
, retaddr
);
317 do_raise_exception(env
, EXCCODE_ADEM
, retaddr
);
321 static bool loongarch_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
323 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
324 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
325 CPULoongArchState
*env
= &cpu
->env
;
327 if (cpu_loongarch_hw_interrupts_enabled(env
) &&
328 cpu_loongarch_hw_interrupts_pending(env
)) {
330 cs
->exception_index
= EXCCODE_INT
;
331 loongarch_cpu_do_interrupt(cs
);
339 static void loongarch_cpu_synchronize_from_tb(CPUState
*cs
,
340 const TranslationBlock
*tb
)
342 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
343 CPULoongArchState
*env
= &cpu
->env
;
345 tcg_debug_assert(!(cs
->tcg_cflags
& CF_PCREL
));
349 static void loongarch_restore_state_to_opc(CPUState
*cs
,
350 const TranslationBlock
*tb
,
351 const uint64_t *data
)
353 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
354 CPULoongArchState
*env
= &cpu
->env
;
356 set_pc(env
, data
[0]);
358 #endif /* CONFIG_TCG */
360 static bool loongarch_cpu_has_work(CPUState
*cs
)
362 #ifdef CONFIG_USER_ONLY
365 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
366 CPULoongArchState
*env
= &cpu
->env
;
367 bool has_work
= false;
369 if ((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
370 cpu_loongarch_hw_interrupts_pending(env
)) {
378 static void loongarch_la464_initfn(Object
*obj
)
380 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
381 CPULoongArchState
*env
= &cpu
->env
;
384 for (i
= 0; i
< 21; i
++) {
385 env
->cpucfg
[i
] = 0x0;
388 cpu
->dtb_compatible
= "loongarch,Loongson-3A5000";
389 env
->cpucfg
[0] = 0x14c010; /* PRID */
392 data
= FIELD_DP32(data
, CPUCFG1
, ARCH
, 2);
393 data
= FIELD_DP32(data
, CPUCFG1
, PGMMU
, 1);
394 data
= FIELD_DP32(data
, CPUCFG1
, IOCSR
, 1);
395 data
= FIELD_DP32(data
, CPUCFG1
, PALEN
, 0x2f);
396 data
= FIELD_DP32(data
, CPUCFG1
, VALEN
, 0x2f);
397 data
= FIELD_DP32(data
, CPUCFG1
, UAL
, 1);
398 data
= FIELD_DP32(data
, CPUCFG1
, RI
, 1);
399 data
= FIELD_DP32(data
, CPUCFG1
, EP
, 1);
400 data
= FIELD_DP32(data
, CPUCFG1
, RPLV
, 1);
401 data
= FIELD_DP32(data
, CPUCFG1
, HP
, 1);
402 data
= FIELD_DP32(data
, CPUCFG1
, IOCSR_BRD
, 1);
403 env
->cpucfg
[1] = data
;
406 data
= FIELD_DP32(data
, CPUCFG2
, FP
, 1);
407 data
= FIELD_DP32(data
, CPUCFG2
, FP_SP
, 1);
408 data
= FIELD_DP32(data
, CPUCFG2
, FP_DP
, 1);
409 data
= FIELD_DP32(data
, CPUCFG2
, FP_VER
, 1);
410 data
= FIELD_DP32(data
, CPUCFG2
, LSX
, 1),
411 data
= FIELD_DP32(data
, CPUCFG2
, LASX
, 1),
412 data
= FIELD_DP32(data
, CPUCFG2
, LLFTP
, 1);
413 data
= FIELD_DP32(data
, CPUCFG2
, LLFTP_VER
, 1);
414 data
= FIELD_DP32(data
, CPUCFG2
, LSPW
, 1);
415 data
= FIELD_DP32(data
, CPUCFG2
, LAM
, 1);
416 env
->cpucfg
[2] = data
;
418 env
->cpucfg
[4] = 100 * 1000 * 1000; /* Crystal frequency */
421 data
= FIELD_DP32(data
, CPUCFG5
, CC_MUL
, 1);
422 data
= FIELD_DP32(data
, CPUCFG5
, CC_DIV
, 1);
423 env
->cpucfg
[5] = data
;
426 data
= FIELD_DP32(data
, CPUCFG16
, L1_IUPRE
, 1);
427 data
= FIELD_DP32(data
, CPUCFG16
, L1_DPRE
, 1);
428 data
= FIELD_DP32(data
, CPUCFG16
, L2_IUPRE
, 1);
429 data
= FIELD_DP32(data
, CPUCFG16
, L2_IUUNIFY
, 1);
430 data
= FIELD_DP32(data
, CPUCFG16
, L2_IUPRIV
, 1);
431 data
= FIELD_DP32(data
, CPUCFG16
, L3_IUPRE
, 1);
432 data
= FIELD_DP32(data
, CPUCFG16
, L3_IUUNIFY
, 1);
433 data
= FIELD_DP32(data
, CPUCFG16
, L3_IUINCL
, 1);
434 env
->cpucfg
[16] = data
;
437 data
= FIELD_DP32(data
, CPUCFG17
, L1IU_WAYS
, 3);
438 data
= FIELD_DP32(data
, CPUCFG17
, L1IU_SETS
, 8);
439 data
= FIELD_DP32(data
, CPUCFG17
, L1IU_SIZE
, 6);
440 env
->cpucfg
[17] = data
;
443 data
= FIELD_DP32(data
, CPUCFG18
, L1D_WAYS
, 3);
444 data
= FIELD_DP32(data
, CPUCFG18
, L1D_SETS
, 8);
445 data
= FIELD_DP32(data
, CPUCFG18
, L1D_SIZE
, 6);
446 env
->cpucfg
[18] = data
;
449 data
= FIELD_DP32(data
, CPUCFG19
, L2IU_WAYS
, 15);
450 data
= FIELD_DP32(data
, CPUCFG19
, L2IU_SETS
, 8);
451 data
= FIELD_DP32(data
, CPUCFG19
, L2IU_SIZE
, 6);
452 env
->cpucfg
[19] = data
;
455 data
= FIELD_DP32(data
, CPUCFG20
, L3IU_WAYS
, 15);
456 data
= FIELD_DP32(data
, CPUCFG20
, L3IU_SETS
, 14);
457 data
= FIELD_DP32(data
, CPUCFG20
, L3IU_SIZE
, 6);
458 env
->cpucfg
[20] = data
;
460 env
->CSR_ASID
= FIELD_DP64(0, CSR_ASID
, ASIDBITS
, 0xa);
461 loongarch_cpu_post_init(obj
);
464 static void loongarch_la132_initfn(Object
*obj
)
466 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
467 CPULoongArchState
*env
= &cpu
->env
;
471 for (i
= 0; i
< 21; i
++) {
472 env
->cpucfg
[i
] = 0x0;
475 cpu
->dtb_compatible
= "loongarch,Loongson-1C103";
476 env
->cpucfg
[0] = 0x148042; /* PRID */
479 data
= FIELD_DP32(data
, CPUCFG1
, ARCH
, 1); /* LA32 */
480 data
= FIELD_DP32(data
, CPUCFG1
, PGMMU
, 1);
481 data
= FIELD_DP32(data
, CPUCFG1
, IOCSR
, 1);
482 data
= FIELD_DP32(data
, CPUCFG1
, PALEN
, 0x1f); /* 32 bits */
483 data
= FIELD_DP32(data
, CPUCFG1
, VALEN
, 0x1f); /* 32 bits */
484 data
= FIELD_DP32(data
, CPUCFG1
, UAL
, 1);
485 data
= FIELD_DP32(data
, CPUCFG1
, RI
, 0);
486 data
= FIELD_DP32(data
, CPUCFG1
, EP
, 0);
487 data
= FIELD_DP32(data
, CPUCFG1
, RPLV
, 0);
488 data
= FIELD_DP32(data
, CPUCFG1
, HP
, 1);
489 data
= FIELD_DP32(data
, CPUCFG1
, IOCSR_BRD
, 1);
490 env
->cpucfg
[1] = data
;
493 static void loongarch_max_initfn(Object
*obj
)
495 /* '-cpu max' for TCG: we use cpu la464. */
496 loongarch_la464_initfn(obj
);
499 static void loongarch_cpu_reset_hold(Object
*obj
)
501 CPUState
*cs
= CPU(obj
);
502 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
503 LoongArchCPUClass
*lacc
= LOONGARCH_CPU_GET_CLASS(cpu
);
504 CPULoongArchState
*env
= &cpu
->env
;
506 if (lacc
->parent_phases
.hold
) {
507 lacc
->parent_phases
.hold(obj
);
510 env
->fcsr0_mask
= FCSR0_M1
| FCSR0_M2
| FCSR0_M3
;
514 /* Set csr registers value after reset */
515 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, PLV
, 0);
516 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, IE
, 0);
517 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, DA
, 1);
518 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, PG
, 0);
519 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, DATF
, 1);
520 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, DATM
, 1);
522 env
->CSR_EUEN
= FIELD_DP64(env
->CSR_EUEN
, CSR_EUEN
, FPE
, 0);
523 env
->CSR_EUEN
= FIELD_DP64(env
->CSR_EUEN
, CSR_EUEN
, SXE
, 0);
524 env
->CSR_EUEN
= FIELD_DP64(env
->CSR_EUEN
, CSR_EUEN
, ASXE
, 0);
525 env
->CSR_EUEN
= FIELD_DP64(env
->CSR_EUEN
, CSR_EUEN
, BTE
, 0);
529 env
->CSR_ECFG
= FIELD_DP64(env
->CSR_ECFG
, CSR_ECFG
, VS
, 0);
530 env
->CSR_ECFG
= FIELD_DP64(env
->CSR_ECFG
, CSR_ECFG
, LIE
, 0);
532 env
->CSR_ESTAT
= env
->CSR_ESTAT
& (~MAKE_64BIT_MASK(0, 2));
533 env
->CSR_RVACFG
= FIELD_DP64(env
->CSR_RVACFG
, CSR_RVACFG
, RBITS
, 0);
534 env
->CSR_CPUID
= cs
->cpu_index
;
535 env
->CSR_TCFG
= FIELD_DP64(env
->CSR_TCFG
, CSR_TCFG
, EN
, 0);
536 env
->CSR_LLBCTL
= FIELD_DP64(env
->CSR_LLBCTL
, CSR_LLBCTL
, KLO
, 0);
537 env
->CSR_TLBRERA
= FIELD_DP64(env
->CSR_TLBRERA
, CSR_TLBRERA
, ISTLBR
, 0);
538 env
->CSR_MERRCTL
= FIELD_DP64(env
->CSR_MERRCTL
, CSR_MERRCTL
, ISMERR
, 0);
539 env
->CSR_TID
= cs
->cpu_index
;
541 env
->CSR_PRCFG3
= FIELD_DP64(env
->CSR_PRCFG3
, CSR_PRCFG3
, TLB_TYPE
, 2);
542 env
->CSR_PRCFG3
= FIELD_DP64(env
->CSR_PRCFG3
, CSR_PRCFG3
, MTLB_ENTRY
, 63);
543 env
->CSR_PRCFG3
= FIELD_DP64(env
->CSR_PRCFG3
, CSR_PRCFG3
, STLB_WAYS
, 7);
544 env
->CSR_PRCFG3
= FIELD_DP64(env
->CSR_PRCFG3
, CSR_PRCFG3
, STLB_SETS
, 8);
546 for (n
= 0; n
< 4; n
++) {
547 env
->CSR_DMW
[n
] = FIELD_DP64(env
->CSR_DMW
[n
], CSR_DMW
, PLV0
, 0);
548 env
->CSR_DMW
[n
] = FIELD_DP64(env
->CSR_DMW
[n
], CSR_DMW
, PLV1
, 0);
549 env
->CSR_DMW
[n
] = FIELD_DP64(env
->CSR_DMW
[n
], CSR_DMW
, PLV2
, 0);
550 env
->CSR_DMW
[n
] = FIELD_DP64(env
->CSR_DMW
[n
], CSR_DMW
, PLV3
, 0);
553 #ifndef CONFIG_USER_ONLY
554 env
->pc
= 0x1c000000;
555 memset(env
->tlb
, 0, sizeof(env
->tlb
));
557 kvm_arch_reset_vcpu(env
);
562 restore_fp_status(env
);
564 cs
->exception_index
= -1;
567 static void loongarch_cpu_disas_set_info(CPUState
*s
, disassemble_info
*info
)
569 info
->print_insn
= print_insn_loongarch
;
572 static void loongarch_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
574 CPUState
*cs
= CPU(dev
);
575 LoongArchCPUClass
*lacc
= LOONGARCH_CPU_GET_CLASS(dev
);
576 Error
*local_err
= NULL
;
578 cpu_exec_realizefn(cs
, &local_err
);
579 if (local_err
!= NULL
) {
580 error_propagate(errp
, local_err
);
584 loongarch_cpu_register_gdb_regs_for_features(cs
);
589 lacc
->parent_realize(dev
, errp
);
592 static bool loongarch_get_lsx(Object
*obj
, Error
**errp
)
594 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
597 if (FIELD_EX32(cpu
->env
.cpucfg
[2], CPUCFG2
, LSX
)) {
605 static void loongarch_set_lsx(Object
*obj
, bool value
, Error
**errp
)
607 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
610 cpu
->env
.cpucfg
[2] = FIELD_DP32(cpu
->env
.cpucfg
[2], CPUCFG2
, LSX
, 1);
612 cpu
->env
.cpucfg
[2] = FIELD_DP32(cpu
->env
.cpucfg
[2], CPUCFG2
, LSX
, 0);
613 cpu
->env
.cpucfg
[2] = FIELD_DP32(cpu
->env
.cpucfg
[2], CPUCFG2
, LASX
, 0);
617 static bool loongarch_get_lasx(Object
*obj
, Error
**errp
)
619 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
622 if (FIELD_EX32(cpu
->env
.cpucfg
[2], CPUCFG2
, LASX
)) {
630 static void loongarch_set_lasx(Object
*obj
, bool value
, Error
**errp
)
632 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
635 if (!FIELD_EX32(cpu
->env
.cpucfg
[2], CPUCFG2
, LSX
)) {
636 cpu
->env
.cpucfg
[2] = FIELD_DP32(cpu
->env
.cpucfg
[2], CPUCFG2
, LSX
, 1);
638 cpu
->env
.cpucfg
[2] = FIELD_DP32(cpu
->env
.cpucfg
[2], CPUCFG2
, LASX
, 1);
640 cpu
->env
.cpucfg
[2] = FIELD_DP32(cpu
->env
.cpucfg
[2], CPUCFG2
, LASX
, 0);
644 void loongarch_cpu_post_init(Object
*obj
)
646 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
648 if (FIELD_EX32(cpu
->env
.cpucfg
[2], CPUCFG2
, LSX
)) {
649 object_property_add_bool(obj
, "lsx", loongarch_get_lsx
,
652 if (FIELD_EX32(cpu
->env
.cpucfg
[2], CPUCFG2
, LASX
)) {
653 object_property_add_bool(obj
, "lasx", loongarch_get_lasx
,
658 static void loongarch_cpu_init(Object
*obj
)
660 #ifndef CONFIG_USER_ONLY
661 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
663 qdev_init_gpio_in(DEVICE(cpu
), loongarch_cpu_set_irq
, N_IRQS
);
665 timer_init_ns(&cpu
->timer
, QEMU_CLOCK_VIRTUAL
,
666 &loongarch_constant_timer_cb
, cpu
);
671 static ObjectClass
*loongarch_cpu_class_by_name(const char *cpu_model
)
675 oc
= object_class_by_name(cpu_model
);
677 g_autofree
char *typename
678 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model
);
679 oc
= object_class_by_name(typename
);
685 void loongarch_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
687 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
688 CPULoongArchState
*env
= &cpu
->env
;
691 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
692 qemu_fprintf(f
, " FCSR0 0x%08x fp_status 0x%02x\n", env
->fcsr0
,
693 get_float_exception_flags(&env
->fp_status
));
696 for (i
= 0; i
< 32; i
++) {
698 qemu_fprintf(f
, " GPR%02d:", i
);
700 qemu_fprintf(f
, " %s %016" PRIx64
, regnames
[i
], env
->gpr
[i
]);
702 qemu_fprintf(f
, "\n");
706 qemu_fprintf(f
, "CRMD=%016" PRIx64
"\n", env
->CSR_CRMD
);
707 qemu_fprintf(f
, "PRMD=%016" PRIx64
"\n", env
->CSR_PRMD
);
708 qemu_fprintf(f
, "EUEN=%016" PRIx64
"\n", env
->CSR_EUEN
);
709 qemu_fprintf(f
, "ESTAT=%016" PRIx64
"\n", env
->CSR_ESTAT
);
710 qemu_fprintf(f
, "ERA=%016" PRIx64
"\n", env
->CSR_ERA
);
711 qemu_fprintf(f
, "BADV=%016" PRIx64
"\n", env
->CSR_BADV
);
712 qemu_fprintf(f
, "BADI=%016" PRIx64
"\n", env
->CSR_BADI
);
713 qemu_fprintf(f
, "EENTRY=%016" PRIx64
"\n", env
->CSR_EENTRY
);
714 qemu_fprintf(f
, "PRCFG1=%016" PRIx64
", PRCFG2=%016" PRIx64
","
715 " PRCFG3=%016" PRIx64
"\n",
716 env
->CSR_PRCFG1
, env
->CSR_PRCFG3
, env
->CSR_PRCFG3
);
717 qemu_fprintf(f
, "TLBRENTRY=%016" PRIx64
"\n", env
->CSR_TLBRENTRY
);
718 qemu_fprintf(f
, "TLBRBADV=%016" PRIx64
"\n", env
->CSR_TLBRBADV
);
719 qemu_fprintf(f
, "TLBRERA=%016" PRIx64
"\n", env
->CSR_TLBRERA
);
720 qemu_fprintf(f
, "TCFG=%016" PRIx64
"\n", env
->CSR_TCFG
);
721 qemu_fprintf(f
, "TVAL=%016" PRIx64
"\n", env
->CSR_TVAL
);
724 if (flags
& CPU_DUMP_FPU
) {
725 for (i
= 0; i
< 32; i
++) {
726 qemu_fprintf(f
, " %s %016" PRIx64
, fregnames
[i
], env
->fpr
[i
].vreg
.D(0));
728 qemu_fprintf(f
, "\n");
735 #include "hw/core/tcg-cpu-ops.h"
737 static TCGCPUOps loongarch_tcg_ops
= {
738 .initialize
= loongarch_translate_init
,
739 .synchronize_from_tb
= loongarch_cpu_synchronize_from_tb
,
740 .restore_state_to_opc
= loongarch_restore_state_to_opc
,
742 #ifndef CONFIG_USER_ONLY
743 .tlb_fill
= loongarch_cpu_tlb_fill
,
744 .cpu_exec_interrupt
= loongarch_cpu_exec_interrupt
,
745 .do_interrupt
= loongarch_cpu_do_interrupt
,
746 .do_transaction_failed
= loongarch_cpu_do_transaction_failed
,
749 #endif /* CONFIG_TCG */
751 #ifndef CONFIG_USER_ONLY
752 #include "hw/core/sysemu-cpu-ops.h"
754 static const struct SysemuCPUOps loongarch_sysemu_ops
= {
756 .get_phys_page_debug
= loongarch_cpu_get_phys_page_debug
,
760 static int64_t loongarch_cpu_get_arch_id(CPUState
*cs
)
762 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
768 static void loongarch_cpu_class_init(ObjectClass
*c
, void *data
)
770 LoongArchCPUClass
*lacc
= LOONGARCH_CPU_CLASS(c
);
771 CPUClass
*cc
= CPU_CLASS(c
);
772 DeviceClass
*dc
= DEVICE_CLASS(c
);
773 ResettableClass
*rc
= RESETTABLE_CLASS(c
);
775 device_class_set_parent_realize(dc
, loongarch_cpu_realizefn
,
776 &lacc
->parent_realize
);
777 resettable_class_set_parent_phases(rc
, NULL
, loongarch_cpu_reset_hold
, NULL
,
778 &lacc
->parent_phases
);
780 cc
->class_by_name
= loongarch_cpu_class_by_name
;
781 cc
->has_work
= loongarch_cpu_has_work
;
782 cc
->dump_state
= loongarch_cpu_dump_state
;
783 cc
->set_pc
= loongarch_cpu_set_pc
;
784 cc
->get_pc
= loongarch_cpu_get_pc
;
785 #ifndef CONFIG_USER_ONLY
786 cc
->get_arch_id
= loongarch_cpu_get_arch_id
;
787 dc
->vmsd
= &vmstate_loongarch_cpu
;
788 cc
->sysemu_ops
= &loongarch_sysemu_ops
;
790 cc
->disas_set_info
= loongarch_cpu_disas_set_info
;
791 cc
->gdb_read_register
= loongarch_cpu_gdb_read_register
;
792 cc
->gdb_write_register
= loongarch_cpu_gdb_write_register
;
793 cc
->gdb_stop_before_watchpoint
= true;
796 cc
->tcg_ops
= &loongarch_tcg_ops
;
800 static const gchar
*loongarch32_gdb_arch_name(CPUState
*cs
)
802 return "loongarch32";
805 static void loongarch32_cpu_class_init(ObjectClass
*c
, void *data
)
807 CPUClass
*cc
= CPU_CLASS(c
);
809 cc
->gdb_num_core_regs
= 35;
810 cc
->gdb_core_xml_file
= "loongarch-base32.xml";
811 cc
->gdb_arch_name
= loongarch32_gdb_arch_name
;
814 static const gchar
*loongarch64_gdb_arch_name(CPUState
*cs
)
816 return "loongarch64";
819 static void loongarch64_cpu_class_init(ObjectClass
*c
, void *data
)
821 CPUClass
*cc
= CPU_CLASS(c
);
823 cc
->gdb_num_core_regs
= 35;
824 cc
->gdb_core_xml_file
= "loongarch-base64.xml";
825 cc
->gdb_arch_name
= loongarch64_gdb_arch_name
;
828 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \
830 .parent = TYPE_LOONGARCH##size##_CPU, \
831 .instance_init = initfn, \
832 .name = LOONGARCH_CPU_TYPE_NAME(model), \
835 static const TypeInfo loongarch_cpu_type_infos
[] = {
837 .name
= TYPE_LOONGARCH_CPU
,
839 .instance_size
= sizeof(LoongArchCPU
),
840 .instance_align
= __alignof(LoongArchCPU
),
841 .instance_init
= loongarch_cpu_init
,
844 .class_size
= sizeof(LoongArchCPUClass
),
845 .class_init
= loongarch_cpu_class_init
,
848 .name
= TYPE_LOONGARCH32_CPU
,
849 .parent
= TYPE_LOONGARCH_CPU
,
852 .class_init
= loongarch32_cpu_class_init
,
855 .name
= TYPE_LOONGARCH64_CPU
,
856 .parent
= TYPE_LOONGARCH_CPU
,
859 .class_init
= loongarch64_cpu_class_init
,
861 DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn
),
862 DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn
),
863 DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn
),
866 DEFINE_TYPES(loongarch_cpu_type_infos
)