target/loongarch/cpu.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * QEMU LoongArch CPU
   4  *
   5  * Copyright (c) 2021 Loongson Technology Corporation Limited
   6  */
   7
   8 #ifndef LOONGARCH_CPU_H
   9 #define LOONGARCH_CPU_H
  10
  11 #include "qemu/int128.h"
  12 #include "exec/cpu-defs.h"
  13 #include "fpu/softfloat-types.h"
  14 #include "hw/registerfields.h"
  15 #include "qemu/timer.h"
  16 #ifndef CONFIG_USER_ONLY
  17 #include "exec/memory.h"
  18 #endif
  19 #include "cpu-csr.h"
  20
  21 #define IOCSRF_TEMP             0
  22 #define IOCSRF_NODECNT          1
  23 #define IOCSRF_MSI              2
  24 #define IOCSRF_EXTIOI           3
  25 #define IOCSRF_CSRIPI           4
  26 #define IOCSRF_FREQCSR          5
  27 #define IOCSRF_FREQSCALE        6
  28 #define IOCSRF_DVFSV1           7
  29 #define IOCSRF_GMOD             9
  30 #define IOCSRF_VM               11
  31
  32 #define VERSION_REG             0x0
  33 #define FEATURE_REG             0x8
  34 #define VENDOR_REG              0x10
  35 #define CPUNAME_REG             0x20
  36 #define MISC_FUNC_REG           0x420
  37 #define IOCSRM_EXTIOI_EN        48
  38
  39 #define IOCSR_MEM_SIZE          0x428
  40
  41 #define TCG_GUEST_DEFAULT_MO (0)
  42
  43 #define FCSR0_M1    0x1f         /* FCSR1 mask, Enables */
  44 #define FCSR0_M2    0x1f1f0000   /* FCSR2 mask, Cause and Flags */
  45 #define FCSR0_M3    0x300        /* FCSR3 mask, Round Mode */
  46 #define FCSR0_RM    8            /* Round Mode bit num on fcsr0 */
  47
  48 FIELD(FCSR0, ENABLES, 0, 5)
  49 FIELD(FCSR0, RM, 8, 2)
  50 FIELD(FCSR0, FLAGS, 16, 5)
  51 FIELD(FCSR0, CAUSE, 24, 5)
  52
  53 #define GET_FP_CAUSE(REG)      FIELD_EX32(REG, FCSR0, CAUSE)
  54 #define SET_FP_CAUSE(REG, V) \
  55     do { \
  56         (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
  57     } while (0)
  58 #define UPDATE_FP_CAUSE(REG, V) \
  59     do { \
  60         (REG) |= FIELD_DP32(0, FCSR0, CAUSE, V); \
  61     } while (0)
  62
  63 #define GET_FP_ENABLES(REG)    FIELD_EX32(REG, FCSR0, ENABLES)
  64 #define SET_FP_ENABLES(REG, V) \
  65     do { \
  66         (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \
  67     } while (0)
  68
  69 #define GET_FP_FLAGS(REG)      FIELD_EX32(REG, FCSR0, FLAGS)
  70 #define SET_FP_FLAGS(REG, V) \
  71     do { \
  72         (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \
  73     } while (0)
  74
  75 #define UPDATE_FP_FLAGS(REG, V) \
  76     do { \
  77         (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \
  78     } while (0)
  79
  80 #define FP_INEXACT        1
  81 #define FP_UNDERFLOW      2
  82 #define FP_OVERFLOW       4
  83 #define FP_DIV0           8
  84 #define FP_INVALID        16
  85
  86 #define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )
  87 #define EXCODE_MCODE(code)    ( (code) & 0x3f )
  88 #define EXCODE_SUBCODE(code)  ( (code) >> 6 )
  89
  90 #define  EXCCODE_EXTERNAL_INT        64   /* plus external interrupt number */
  91 #define  EXCCODE_INT                 EXCODE(0, 0)
  92 #define  EXCCODE_PIL                 EXCODE(1, 0)
  93 #define  EXCCODE_PIS                 EXCODE(2, 0)
  94 #define  EXCCODE_PIF                 EXCODE(3, 0)
  95 #define  EXCCODE_PME                 EXCODE(4, 0)
  96 #define  EXCCODE_PNR                 EXCODE(5, 0)
  97 #define  EXCCODE_PNX                 EXCODE(6, 0)
  98 #define  EXCCODE_PPI                 EXCODE(7, 0)
  99 #define  EXCCODE_ADEF                EXCODE(8, 0) /* Different exception subcode */
 100 #define  EXCCODE_ADEM                EXCODE(8, 1)
 101 #define  EXCCODE_ALE                 EXCODE(9, 0)
 102 #define  EXCCODE_BCE                 EXCODE(10, 0)
 103 #define  EXCCODE_SYS                 EXCODE(11, 0)
 104 #define  EXCCODE_BRK                 EXCODE(12, 0)
 105 #define  EXCCODE_INE                 EXCODE(13, 0)
 106 #define  EXCCODE_IPE                 EXCODE(14, 0)
 107 #define  EXCCODE_FPD                 EXCODE(15, 0)
 108 #define  EXCCODE_SXD                 EXCODE(16, 0)
 109 #define  EXCCODE_ASXD                EXCODE(17, 0)
 110 #define  EXCCODE_FPE                 EXCODE(18, 0) /* Different exception subcode */
 111 #define  EXCCODE_VFPE                EXCODE(18, 1)
 112 #define  EXCCODE_WPEF                EXCODE(19, 0) /* Different exception subcode */
 113 #define  EXCCODE_WPEM                EXCODE(19, 1)
 114 #define  EXCCODE_BTD                 EXCODE(20, 0)
 115 #define  EXCCODE_BTE                 EXCODE(21, 0)
 116 #define  EXCCODE_DBP                 EXCODE(26, 0) /* Reserved subcode used for debug */
 117
 118 /* cpucfg[0] bits */
 119 FIELD(CPUCFG0, PRID, 0, 32)
 120
 121 /* cpucfg[1] bits */
 122 FIELD(CPUCFG1, ARCH, 0, 2)
 123 FIELD(CPUCFG1, PGMMU, 2, 1)
 124 FIELD(CPUCFG1, IOCSR, 3, 1)
 125 FIELD(CPUCFG1, PALEN, 4, 8)
 126 FIELD(CPUCFG1, VALEN, 12, 8)
 127 FIELD(CPUCFG1, UAL, 20, 1)
 128 FIELD(CPUCFG1, RI, 21, 1)
 129 FIELD(CPUCFG1, EP, 22, 1)
 130 FIELD(CPUCFG1, RPLV, 23, 1)
 131 FIELD(CPUCFG1, HP, 24, 1)
 132 FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
 133 FIELD(CPUCFG1, MSG_INT, 26, 1)
 134
 135 /* cpucfg[2] bits */
 136 FIELD(CPUCFG2, FP, 0, 1)
 137 FIELD(CPUCFG2, FP_SP, 1, 1)
 138 FIELD(CPUCFG2, FP_DP, 2, 1)
 139 FIELD(CPUCFG2, FP_VER, 3, 3)
 140 FIELD(CPUCFG2, LSX, 6, 1)
 141 FIELD(CPUCFG2, LASX, 7, 1)
 142 FIELD(CPUCFG2, COMPLEX, 8, 1)
 143 FIELD(CPUCFG2, CRYPTO, 9, 1)
 144 FIELD(CPUCFG2, LVZ, 10, 1)
 145 FIELD(CPUCFG2, LVZ_VER, 11, 3)
 146 FIELD(CPUCFG2, LLFTP, 14, 1)
 147 FIELD(CPUCFG2, LLFTP_VER, 15, 3)
 148 FIELD(CPUCFG2, LBT_X86, 18, 1)
 149 FIELD(CPUCFG2, LBT_ARM, 19, 1)
 150 FIELD(CPUCFG2, LBT_MIPS, 20, 1)
 151 FIELD(CPUCFG2, LSPW, 21, 1)
 152 FIELD(CPUCFG2, LAM, 22, 1)
 153
 154 /* cpucfg[3] bits */
 155 FIELD(CPUCFG3, CCDMA, 0, 1)
 156 FIELD(CPUCFG3, SFB, 1, 1)
 157 FIELD(CPUCFG3, UCACC, 2, 1)
 158 FIELD(CPUCFG3, LLEXC, 3, 1)
 159 FIELD(CPUCFG3, SCDLY, 4, 1)
 160 FIELD(CPUCFG3, LLDBAR, 5, 1)
 161 FIELD(CPUCFG3, ITLBHMC, 6, 1)
 162 FIELD(CPUCFG3, ICHMC, 7, 1)
 163 FIELD(CPUCFG3, SPW_LVL, 8, 3)
 164 FIELD(CPUCFG3, SPW_HP_HF, 11, 1)
 165 FIELD(CPUCFG3, RVA, 12, 1)
 166 FIELD(CPUCFG3, RVAMAX, 13, 4)
 167
 168 /* cpucfg[4] bits */
 169 FIELD(CPUCFG4, CC_FREQ, 0, 32)
 170
 171 /* cpucfg[5] bits */
 172 FIELD(CPUCFG5, CC_MUL, 0, 16)
 173 FIELD(CPUCFG5, CC_DIV, 16, 16)
 174
 175 /* cpucfg[6] bits */
 176 FIELD(CPUCFG6, PMP, 0, 1)
 177 FIELD(CPUCFG6, PMVER, 1, 3)
 178 FIELD(CPUCFG6, PMNUM, 4, 4)
 179 FIELD(CPUCFG6, PMBITS, 8, 6)
 180 FIELD(CPUCFG6, UPM, 14, 1)
 181
 182 /* cpucfg[16] bits */
 183 FIELD(CPUCFG16, L1_IUPRE, 0, 1)
 184 FIELD(CPUCFG16, L1_IUUNIFY, 1, 1)
 185 FIELD(CPUCFG16, L1_DPRE, 2, 1)
 186 FIELD(CPUCFG16, L2_IUPRE, 3, 1)
 187 FIELD(CPUCFG16, L2_IUUNIFY, 4, 1)
 188 FIELD(CPUCFG16, L2_IUPRIV, 5, 1)
 189 FIELD(CPUCFG16, L2_IUINCL, 6, 1)
 190 FIELD(CPUCFG16, L2_DPRE, 7, 1)
 191 FIELD(CPUCFG16, L2_DPRIV, 8, 1)
 192 FIELD(CPUCFG16, L2_DINCL, 9, 1)
 193 FIELD(CPUCFG16, L3_IUPRE, 10, 1)
 194 FIELD(CPUCFG16, L3_IUUNIFY, 11, 1)
 195 FIELD(CPUCFG16, L3_IUPRIV, 12, 1)
 196 FIELD(CPUCFG16, L3_IUINCL, 13, 1)
 197 FIELD(CPUCFG16, L3_DPRE, 14, 1)
 198 FIELD(CPUCFG16, L3_DPRIV, 15, 1)
 199 FIELD(CPUCFG16, L3_DINCL, 16, 1)
 200
 201 /* cpucfg[17] bits */
 202 FIELD(CPUCFG17, L1IU_WAYS, 0, 16)
 203 FIELD(CPUCFG17, L1IU_SETS, 16, 8)
 204 FIELD(CPUCFG17, L1IU_SIZE, 24, 7)
 205
 206 /* cpucfg[18] bits */
 207 FIELD(CPUCFG18, L1D_WAYS, 0, 16)
 208 FIELD(CPUCFG18, L1D_SETS, 16, 8)
 209 FIELD(CPUCFG18, L1D_SIZE, 24, 7)
 210
 211 /* cpucfg[19] bits */
 212 FIELD(CPUCFG19, L2IU_WAYS, 0, 16)
 213 FIELD(CPUCFG19, L2IU_SETS, 16, 8)
 214 FIELD(CPUCFG19, L2IU_SIZE, 24, 7)
 215
 216 /* cpucfg[20] bits */
 217 FIELD(CPUCFG20, L3IU_WAYS, 0, 16)
 218 FIELD(CPUCFG20, L3IU_SETS, 16, 8)
 219 FIELD(CPUCFG20, L3IU_SIZE, 24, 7)
 220
 221 /*CSR_CRMD */
 222 FIELD(CSR_CRMD, PLV, 0, 2)
 223 FIELD(CSR_CRMD, IE, 2, 1)
 224 FIELD(CSR_CRMD, DA, 3, 1)
 225 FIELD(CSR_CRMD, PG, 4, 1)
 226 FIELD(CSR_CRMD, DATF, 5, 2)
 227 FIELD(CSR_CRMD, DATM, 7, 2)
 228 FIELD(CSR_CRMD, WE, 9, 1)
 229
 230 extern const char * const regnames[32];
 231 extern const char * const fregnames[32];
 232
 233 #define N_IRQS      13
 234 #define IRQ_TIMER   11
 235 #define IRQ_IPI     12
 236
 237 #define LOONGARCH_STLB         2048 /* 2048 STLB */
 238 #define LOONGARCH_MTLB         64   /* 64 MTLB */
 239 #define LOONGARCH_TLB_MAX      (LOONGARCH_STLB + LOONGARCH_MTLB)
 240
 241 /*
 242  * define the ASID PS E VPPN field of TLB
 243  */
 244 FIELD(TLB_MISC, E, 0, 1)
 245 FIELD(TLB_MISC, ASID, 1, 10)
 246 FIELD(TLB_MISC, VPPN, 13, 35)
 247 FIELD(TLB_MISC, PS, 48, 6)
 248
 249 #define LSX_LEN   (128)
 250 typedef union VReg {
 251     int8_t   B[LSX_LEN / 8];
 252     int16_t  H[LSX_LEN / 16];
 253     int32_t  W[LSX_LEN / 32];
 254     int64_t  D[LSX_LEN / 64];
 255     uint8_t  UB[LSX_LEN / 8];
 256     uint16_t UH[LSX_LEN / 16];
 257     uint32_t UW[LSX_LEN / 32];
 258     uint64_t UD[LSX_LEN / 64];
 259     Int128   Q[LSX_LEN / 128];
 260 }VReg;
 261
 262 typedef union fpr_t fpr_t;
 263 union fpr_t {
 264     VReg  vreg;
 265 };
 266
 267 struct LoongArchTLB {
 268     uint64_t tlb_misc;
 269     /* Fields corresponding to CSR_TLBELO0/1 */
 270     uint64_t tlb_entry0;
 271     uint64_t tlb_entry1;
 272 };
 273 typedef struct LoongArchTLB LoongArchTLB;
 274
 275 typedef struct CPUArchState {
 276     uint64_t gpr[32];
 277     uint64_t pc;
 278
 279     fpr_t fpr[32];
 280     float_status fp_status;
 281     bool cf[8];
 282
 283     uint32_t fcsr0;
 284     uint32_t fcsr0_mask;
 285
 286     uint32_t cpucfg[21];
 287
 288     uint64_t lladdr; /* LL virtual address compared against SC */
 289     uint64_t llval;
 290
 291     /* LoongArch CSRs */
 292     uint64_t CSR_CRMD;
 293     uint64_t CSR_PRMD;
 294     uint64_t CSR_EUEN;
 295     uint64_t CSR_MISC;
 296     uint64_t CSR_ECFG;
 297     uint64_t CSR_ESTAT;
 298     uint64_t CSR_ERA;
 299     uint64_t CSR_BADV;
 300     uint64_t CSR_BADI;
 301     uint64_t CSR_EENTRY;
 302     uint64_t CSR_TLBIDX;
 303     uint64_t CSR_TLBEHI;
 304     uint64_t CSR_TLBELO0;
 305     uint64_t CSR_TLBELO1;
 306     uint64_t CSR_ASID;
 307     uint64_t CSR_PGDL;
 308     uint64_t CSR_PGDH;
 309     uint64_t CSR_PGD;
 310     uint64_t CSR_PWCL;
 311     uint64_t CSR_PWCH;
 312     uint64_t CSR_STLBPS;
 313     uint64_t CSR_RVACFG;
 314     uint64_t CSR_PRCFG1;
 315     uint64_t CSR_PRCFG2;
 316     uint64_t CSR_PRCFG3;
 317     uint64_t CSR_SAVE[16];
 318     uint64_t CSR_TID;
 319     uint64_t CSR_TCFG;
 320     uint64_t CSR_TVAL;
 321     uint64_t CSR_CNTC;
 322     uint64_t CSR_TICLR;
 323     uint64_t CSR_LLBCTL;
 324     uint64_t CSR_IMPCTL1;
 325     uint64_t CSR_IMPCTL2;
 326     uint64_t CSR_TLBRENTRY;
 327     uint64_t CSR_TLBRBADV;
 328     uint64_t CSR_TLBRERA;
 329     uint64_t CSR_TLBRSAVE;
 330     uint64_t CSR_TLBRELO0;
 331     uint64_t CSR_TLBRELO1;
 332     uint64_t CSR_TLBREHI;
 333     uint64_t CSR_TLBRPRMD;
 334     uint64_t CSR_MERRCTL;
 335     uint64_t CSR_MERRINFO1;
 336     uint64_t CSR_MERRINFO2;
 337     uint64_t CSR_MERRENTRY;
 338     uint64_t CSR_MERRERA;
 339     uint64_t CSR_MERRSAVE;
 340     uint64_t CSR_CTAG;
 341     uint64_t CSR_DMW[4];
 342     uint64_t CSR_DBG;
 343     uint64_t CSR_DERA;
 344     uint64_t CSR_DSAVE;
 345
 346 #ifndef CONFIG_USER_ONLY
 347     LoongArchTLB  tlb[LOONGARCH_TLB_MAX];
 348
 349     AddressSpace address_space_iocsr;
 350     MemoryRegion system_iocsr;
 351     MemoryRegion iocsr_mem;
 352     bool load_elf;
 353     uint64_t elf_address;
 354     /* Store ipistate to access from this struct */
 355     DeviceState *ipistate;
 356 #endif
 357 } CPULoongArchState;
 358
 359 /**
 360  * LoongArchCPU:
 361  * @env: #CPULoongArchState
 362  *
 363  * A LoongArch CPU.
 364  */
 365 struct ArchCPU {
 366     /*< private >*/
 367     CPUState parent_obj;
 368     /*< public >*/
 369
 370     CPUNegativeOffsetState neg;
 371     CPULoongArchState env;
 372     QEMUTimer timer;
 373
 374     /* 'compatible' string for this CPU for Linux device trees */
 375     const char *dtb_compatible;
 376 };
 377
 378 #define TYPE_LOONGARCH_CPU "loongarch-cpu"
 379
 380 OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
 381                         LOONGARCH_CPU)
 382
 383 /**
 384  * LoongArchCPUClass:
 385  * @parent_realize: The parent class' realize handler.
 386  * @parent_phases: The parent class' reset phase handlers.
 387  *
 388  * A LoongArch CPU model.
 389  */
 390 struct LoongArchCPUClass {
 391     /*< private >*/
 392     CPUClass parent_class;
 393     /*< public >*/
 394
 395     DeviceRealize parent_realize;
 396     ResettablePhases parent_phases;
 397 };
 398
 399 /*
 400  * LoongArch CPUs has 4 privilege levels.
 401  * 0 for kernel mode, 3 for user mode.
 402  * Define an extra index for DA(direct addressing) mode.
 403  */
 404 #define MMU_PLV_KERNEL   0
 405 #define MMU_PLV_USER     3
 406 #define MMU_IDX_KERNEL   MMU_PLV_KERNEL
 407 #define MMU_IDX_USER     MMU_PLV_USER
 408 #define MMU_IDX_DA       4
 409
 410 static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
 411 {
 412 #ifdef CONFIG_USER_ONLY
 413     return MMU_IDX_USER;
 414 #else
 415     if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
 416         return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
 417     }
 418     return MMU_IDX_DA;
 419 #endif
 420 }
 421
 422 /*
 423  * LoongArch CPUs hardware flags.
 424  */
 425 #define HW_FLAGS_PLV_MASK   R_CSR_CRMD_PLV_MASK  /* 0x03 */
 426 #define HW_FLAGS_CRMD_PG    R_CSR_CRMD_PG_MASK   /* 0x10 */
 427 #define HW_FLAGS_EUEN_FPE   0x04
 428 #define HW_FLAGS_EUEN_SXE   0x08
 429
 430 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
 431                                         uint64_t *cs_base, uint32_t *flags)
 432 {
 433     *pc = env->pc;
 434     *cs_base = 0;
 435     *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
 436     *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
 437     *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
 438 }
 439
 440 void loongarch_cpu_list(void);
 441
 442 #define cpu_list loongarch_cpu_list
 443
 444 #include "exec/cpu-all.h"
 445
 446 #define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
 447 #define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
 448 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
 449
 450 #endif /* LOONGARCH_CPU_H */