target/m68k/cpu.h

   1 /*
   2  * m68k virtual CPU header
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery
   5  *  Written by Paul Brook
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef M68K_CPU_H
  22 #define M68K_CPU_H
  23
  24 #include "qemu-common.h"
  25 #include "exec/cpu-defs.h"
  26 #include "cpu-qom.h"
  27
  28 #define OS_BYTE     0
  29 #define OS_WORD     1
  30 #define OS_LONG     2
  31 #define OS_SINGLE   3
  32 #define OS_DOUBLE   4
  33 #define OS_EXTENDED 5
  34 #define OS_PACKED   6
  35 #define OS_UNSIZED  7
  36
  37 #define MAX_QREGS 32
  38
  39 #define EXCP_ACCESS         2   /* Access (MMU) error.  */
  40 #define EXCP_ADDRESS        3   /* Address error.  */
  41 #define EXCP_ILLEGAL        4   /* Illegal instruction.  */
  42 #define EXCP_DIV0           5   /* Divide by zero */
  43 #define EXCP_CHK            6   /* CHK, CHK2 Instructions */
  44 #define EXCP_TRAPCC         7   /* FTRAPcc, TRAPcc, TRAPV Instructions */
  45 #define EXCP_PRIVILEGE      8   /* Privilege violation.  */
  46 #define EXCP_TRACE          9
  47 #define EXCP_LINEA          10  /* Unimplemented line-A (MAC) opcode.  */
  48 #define EXCP_LINEF          11  /* Unimplemented line-F (FPU) opcode.  */
  49 #define EXCP_DEBUGNBP       12  /* Non-breakpoint debug interrupt.  */
  50 #define EXCP_DEBEGBP        13  /* Breakpoint debug interrupt.  */
  51 #define EXCP_FORMAT         14  /* RTE format error.  */
  52 #define EXCP_UNINITIALIZED  15
  53 #define EXCP_SPURIOUS       24  /* Spurious interrupt */
  54 #define EXCP_INT_LEVEL_1    25  /* Level 1 Interrupt autovector */
  55 #define EXCP_INT_LEVEL_7    31  /* Level 7 Interrupt autovector */
  56 #define EXCP_TRAP0          32   /* User trap #0.  */
  57 #define EXCP_TRAP15         47   /* User trap #15.  */
  58 #define EXCP_FP_BSUN        48 /* Branch Set on Unordered */
  59 #define EXCP_FP_INEX        49 /* Inexact result */
  60 #define EXCP_FP_DZ          50 /* Divide by Zero */
  61 #define EXCP_FP_UNFL        51 /* Underflow */
  62 #define EXCP_FP_OPERR       52 /* Operand Error */
  63 #define EXCP_FP_OVFL        53 /* Overflow */
  64 #define EXCP_FP_SNAN        54 /* Signaling Not-A-Number */
  65 #define EXCP_FP_UNIMP       55 /* Unimplemented Data type */
  66 #define EXCP_MMU_CONF       56  /* MMU Configuration Error */
  67 #define EXCP_MMU_ILLEGAL    57  /* MMU Illegal Operation Error */
  68 #define EXCP_MMU_ACCESS     58  /* MMU Access Level Violation Error */
  69
  70 #define EXCP_RTE            0x100
  71 #define EXCP_HALT_INSN      0x101
  72
  73 #define M68K_DTTR0   0
  74 #define M68K_DTTR1   1
  75 #define M68K_ITTR0   2
  76 #define M68K_ITTR1   3
  77
  78 #define M68K_MAX_TTR 2
  79 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]
  80
  81 #define TARGET_INSN_START_EXTRA_WORDS 1
  82
  83 typedef CPU_LDoubleU FPReg;
  84
  85 typedef struct CPUM68KState {
  86     uint32_t dregs[8];
  87     uint32_t aregs[8];
  88     uint32_t pc;
  89     uint32_t sr;
  90
  91     /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
  92     int current_sp;
  93     uint32_t sp[3];
  94
  95     /* Condition flags.  */
  96     uint32_t cc_op;
  97     uint32_t cc_x; /* always 0/1 */
  98     uint32_t cc_n; /* in bit 31 (i.e. negative) */
  99     uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */
 100     uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
 101     uint32_t cc_z; /* == 0 or unused */
 102
 103     FPReg fregs[8];
 104     FPReg fp_result;
 105     uint32_t fpcr;
 106     uint32_t fpsr;
 107     float_status fp_status;
 108
 109     uint64_t mactmp;
 110     /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
 111        two 8-bit parts.  We store a single 64-bit value and
 112        rearrange/extend this when changing modes.  */
 113     uint64_t macc[4];
 114     uint32_t macsr;
 115     uint32_t mac_mask;
 116
 117     /* MMU status.  */
 118     struct {
 119         uint32_t ar;
 120         uint32_t ssw;
 121         /* 68040 */
 122         uint16_t tcr;
 123         uint32_t urp;
 124         uint32_t srp;
 125         bool fault;
 126         uint32_t ttr[4];
 127         uint32_t mmusr;
 128     } mmu;
 129
 130     /* Control registers.  */
 131     uint32_t vbr;
 132     uint32_t mbar;
 133     uint32_t rambar0;
 134     uint32_t cacr;
 135     uint32_t sfc;
 136     uint32_t dfc;
 137
 138     int pending_vector;
 139     int pending_level;
 140
 141     uint32_t qregs[MAX_QREGS];
 142
 143     /* Fields up to this point are cleared by a CPU reset */
 144     struct {} end_reset_fields;
 145
 146     CPU_COMMON
 147
 148     /* Fields from here on are preserved across CPU reset. */
 149     uint32_t features;
 150 } CPUM68KState;
 151
 152 /**
 153  * M68kCPU:
 154  * @env: #CPUM68KState
 155  *
 156  * A Motorola 68k CPU.
 157  */
 158 struct M68kCPU {
 159     /*< private >*/
 160     CPUState parent_obj;
 161     /*< public >*/
 162
 163     CPUM68KState env;
 164 };
 165
 166 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
 167 {
 168     return container_of(env, M68kCPU, env);
 169 }
 170
 171 #define ENV_OFFSET offsetof(M68kCPU, env)
 172
 173 void m68k_cpu_do_interrupt(CPUState *cpu);
 174 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
 175 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 176 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 177 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 178 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 179
 180 void m68k_tcg_init(void);
 181 void m68k_cpu_init_gdb(M68kCPU *cpu);
 182 /* you can call this signal handler from your SIGBUS and SIGSEGV
 183    signal handlers to inform the virtual CPU of exceptions. non zero
 184    is returned if the signal was handled by the virtual CPU.  */
 185 int cpu_m68k_signal_handler(int host_signum, void *pinfo,
 186                            void *puc);
 187 uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
 188 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
 189 void cpu_m68k_set_sr(CPUM68KState *env, uint32_t);
 190 void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);
 191
 192
 193 /* Instead of computing the condition codes after each m68k instruction,
 194  * QEMU just stores one operand (called CC_SRC), the result
 195  * (called CC_DEST) and the type of operation (called CC_OP). When the
 196  * condition codes are needed, the condition codes can be calculated
 197  * using this information. Condition codes are not generated if they
 198  * are only needed for conditional branches.
 199  */
 200 typedef enum {
 201     /* Translator only -- use env->cc_op.  */
 202     CC_OP_DYNAMIC,
 203
 204     /* Each flag bit computed into cc_[xcnvz].  */
 205     CC_OP_FLAGS,
 206
 207     /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v.  */
 208     CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
 209     CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,
 210
 211     /* X in cc_x, {N,Z,C,V} via cc_n/cc_v.  */
 212     CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,
 213
 214     /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n.  */
 215     CC_OP_LOGIC,
 216
 217     CC_OP_NB
 218 } CCOp;
 219
 220 #define CCF_C 0x01
 221 #define CCF_V 0x02
 222 #define CCF_Z 0x04
 223 #define CCF_N 0x08
 224 #define CCF_X 0x10
 225
 226 #define SR_I_SHIFT 8
 227 #define SR_I  0x0700
 228 #define SR_M  0x1000
 229 #define SR_S  0x2000
 230 #define SR_T_SHIFT 14
 231 #define SR_T  0xc000
 232
 233 #define M68K_SSP    0
 234 #define M68K_USP    1
 235 #define M68K_ISP    2
 236
 237 /* bits for 68040 special status word */
 238 #define M68K_CP_040  0x8000
 239 #define M68K_CU_040  0x4000
 240 #define M68K_CT_040  0x2000
 241 #define M68K_CM_040  0x1000
 242 #define M68K_MA_040  0x0800
 243 #define M68K_ATC_040 0x0400
 244 #define M68K_LK_040  0x0200
 245 #define M68K_RW_040  0x0100
 246 #define M68K_SIZ_040 0x0060
 247 #define M68K_TT_040  0x0018
 248 #define M68K_TM_040  0x0007
 249
 250 #define M68K_TM_040_DATA  0x0001
 251 #define M68K_TM_040_CODE  0x0002
 252 #define M68K_TM_040_SUPER 0x0004
 253
 254 /* bits for 68040 write back status word */
 255 #define M68K_WBV_040   0x80
 256 #define M68K_WBSIZ_040 0x60
 257 #define M68K_WBBYT_040 0x20
 258 #define M68K_WBWRD_040 0x40
 259 #define M68K_WBLNG_040 0x00
 260 #define M68K_WBTT_040  0x18
 261 #define M68K_WBTM_040  0x07
 262
 263 /* bus access size codes */
 264 #define M68K_BA_SIZE_MASK    0x60
 265 #define M68K_BA_SIZE_BYTE    0x20
 266 #define M68K_BA_SIZE_WORD    0x40
 267 #define M68K_BA_SIZE_LONG    0x00
 268 #define M68K_BA_SIZE_LINE    0x60
 269
 270 /* bus access transfer type codes */
 271 #define M68K_BA_TT_MOVE16    0x08
 272
 273 /* bits for 68040 MMU status register (mmusr) */
 274 #define M68K_MMU_B_040   0x0800
 275 #define M68K_MMU_G_040   0x0400
 276 #define M68K_MMU_U1_040  0x0200
 277 #define M68K_MMU_U0_040  0x0100
 278 #define M68K_MMU_S_040   0x0080
 279 #define M68K_MMU_CM_040  0x0060
 280 #define M68K_MMU_M_040   0x0010
 281 #define M68K_MMU_WP_040  0x0004
 282 #define M68K_MMU_T_040   0x0002
 283 #define M68K_MMU_R_040   0x0001
 284
 285 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \
 286                               M68K_MMU_U0_040 | M68K_MMU_S_040 | \
 287                               M68K_MMU_CM_040 | M68K_MMU_M_040 | \
 288                               M68K_MMU_WP_040)
 289
 290 /* bits for 68040 MMU Translation Control Register */
 291 #define M68K_TCR_ENABLED 0x8000
 292 #define M68K_TCR_PAGE_8K 0x4000
 293
 294 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */
 295 #define M68K_DESC_WRITEPROT 0x00000004
 296 #define M68K_DESC_USED      0x00000008
 297 #define M68K_DESC_MODIFIED  0x00000010
 298 #define M68K_DESC_CACHEMODE 0x00000060
 299 #define M68K_DESC_CM_WRTHRU 0x00000000
 300 #define M68K_DESC_CM_COPYBK 0x00000020
 301 #define M68K_DESC_CM_SERIAL 0x00000040
 302 #define M68K_DESC_CM_NCACHE 0x00000060
 303 #define M68K_DESC_SUPERONLY 0x00000080
 304 #define M68K_DESC_USERATTR  0x00000300
 305 #define M68K_DESC_USERATTR_SHIFT     8
 306 #define M68K_DESC_GLOBAL    0x00000400
 307 #define M68K_DESC_URESERVED 0x00000800
 308
 309 #define M68K_ROOT_POINTER_ENTRIES   128
 310 #define M68K_4K_PAGE_MASK           (~0xff)
 311 #define M68K_POINTER_BASE(entry)    (entry & ~0x1ff)
 312 #define M68K_ROOT_INDEX(addr)       ((address >> 23) & 0x1fc)
 313 #define M68K_POINTER_INDEX(addr)    ((address >> 16) & 0x1fc)
 314 #define M68K_4K_PAGE_BASE(entry)    (next & M68K_4K_PAGE_MASK)
 315 #define M68K_4K_PAGE_INDEX(addr)    ((address >> 10) & 0xfc)
 316 #define M68K_8K_PAGE_MASK           (~0x7f)
 317 #define M68K_8K_PAGE_BASE(entry)    (next & M68K_8K_PAGE_MASK)
 318 #define M68K_8K_PAGE_INDEX(addr)    ((address >> 11) & 0x7c)
 319 #define M68K_UDT_VALID(entry)       (entry & 2)
 320 #define M68K_PDT_VALID(entry)       (entry & 3)
 321 #define M68K_PDT_INDIRECT(entry)    ((entry & 3) == 2)
 322 #define M68K_INDIRECT_POINTER(addr) (addr & ~3)
 323 #define M68K_TTS_POINTER_SHIFT      18
 324 #define M68K_TTS_ROOT_SHIFT         25
 325
 326 /* bits for 68040 MMU Transparent Translation Registers */
 327 #define M68K_TTR_ADDR_BASE 0xff000000
 328 #define M68K_TTR_ADDR_MASK 0x00ff0000
 329 #define M68K_TTR_ADDR_MASK_SHIFT    8
 330 #define M68K_TTR_ENABLED   0x00008000
 331 #define M68K_TTR_SFIELD    0x00006000
 332 #define M68K_TTR_SFIELD_USER   0x0000
 333 #define M68K_TTR_SFIELD_SUPER  0x2000
 334
 335 /* m68k Control Registers */
 336
 337 /* ColdFire */
 338 /* Memory Management Control Registers */
 339 #define M68K_CR_ASID     0x003
 340 #define M68K_CR_ACR0     0x004
 341 #define M68K_CR_ACR1     0x005
 342 #define M68K_CR_ACR2     0x006
 343 #define M68K_CR_ACR3     0x007
 344 #define M68K_CR_MMUBAR   0x008
 345
 346 /* Processor Miscellaneous Registers */
 347 #define M68K_CR_PC       0x80F
 348
 349 /* Local Memory and Module Control Registers */
 350 #define M68K_CR_ROMBAR0  0xC00
 351 #define M68K_CR_ROMBAR1  0xC01
 352 #define M68K_CR_RAMBAR0  0xC04
 353 #define M68K_CR_RAMBAR1  0xC05
 354 #define M68K_CR_MPCR     0xC0C
 355 #define M68K_CR_EDRAMBAR 0xC0D
 356 #define M68K_CR_SECMBAR  0xC0E
 357 #define M68K_CR_MBAR     0xC0F
 358
 359 /* Local Memory Address Permutation Control Registers */
 360 #define M68K_CR_PCR1U0   0xD02
 361 #define M68K_CR_PCR1L0   0xD03
 362 #define M68K_CR_PCR2U0   0xD04
 363 #define M68K_CR_PCR2L0   0xD05
 364 #define M68K_CR_PCR3U0   0xD06
 365 #define M68K_CR_PCR3L0   0xD07
 366 #define M68K_CR_PCR1U1   0xD0A
 367 #define M68K_CR_PCR1L1   0xD0B
 368 #define M68K_CR_PCR2U1   0xD0C
 369 #define M68K_CR_PCR2L1   0xD0D
 370 #define M68K_CR_PCR3U1   0xD0E
 371 #define M68K_CR_PCR3L1   0xD0F
 372
 373 /* MC680x0 */
 374 /* MC680[1234]0/CPU32 */
 375 #define M68K_CR_SFC      0x000
 376 #define M68K_CR_DFC      0x001
 377 #define M68K_CR_USP      0x800
 378 #define M68K_CR_VBR      0x801 /* + Coldfire */
 379
 380 /* MC680[234]0 */
 381 #define M68K_CR_CACR     0x002 /* + Coldfire */
 382 #define M68K_CR_CAAR     0x802 /* MC68020 and MC68030 only */
 383 #define M68K_CR_MSP      0x803
 384 #define M68K_CR_ISP      0x804
 385
 386 /* MC68040/MC68LC040 */
 387 #define M68K_CR_TC       0x003
 388 #define M68K_CR_ITT0     0x004
 389 #define M68K_CR_ITT1     0x005
 390 #define M68K_CR_DTT0     0x006
 391 #define M68K_CR_DTT1     0x007
 392 #define M68K_CR_MMUSR    0x805
 393 #define M68K_CR_URP      0x806
 394 #define M68K_CR_SRP      0x807
 395
 396 /* MC68EC040 */
 397 #define M68K_CR_IACR0    0x004
 398 #define M68K_CR_IACR1    0x005
 399 #define M68K_CR_DACR0    0x006
 400 #define M68K_CR_DACR1    0x007
 401
 402 #define M68K_FPIAR_SHIFT  0
 403 #define M68K_FPIAR        (1 << M68K_FPIAR_SHIFT)
 404 #define M68K_FPSR_SHIFT   1
 405 #define M68K_FPSR         (1 << M68K_FPSR_SHIFT)
 406 #define M68K_FPCR_SHIFT   2
 407 #define M68K_FPCR         (1 << M68K_FPCR_SHIFT)
 408
 409 /* Floating-Point Status Register */
 410
 411 /* Condition Code */
 412 #define FPSR_CC_MASK  0x0f000000
 413 #define FPSR_CC_A     0x01000000 /* Not-A-Number */
 414 #define FPSR_CC_I     0x02000000 /* Infinity */
 415 #define FPSR_CC_Z     0x04000000 /* Zero */
 416 #define FPSR_CC_N     0x08000000 /* Negative */
 417
 418 /* Quotient */
 419
 420 #define FPSR_QT_MASK  0x00ff0000
 421 #define FPSR_QT_SHIFT 16
 422
 423 /* Floating-Point Control Register */
 424 /* Rounding mode */
 425 #define FPCR_RND_MASK   0x0030
 426 #define FPCR_RND_N      0x0000
 427 #define FPCR_RND_Z      0x0010
 428 #define FPCR_RND_M      0x0020
 429 #define FPCR_RND_P      0x0030
 430
 431 /* Rounding precision */
 432 #define FPCR_PREC_MASK  0x00c0
 433 #define FPCR_PREC_X     0x0000
 434 #define FPCR_PREC_S     0x0040
 435 #define FPCR_PREC_D     0x0080
 436 #define FPCR_PREC_U     0x00c0
 437
 438 #define FPCR_EXCP_MASK 0xff00
 439
 440 /* CACR fields are implementation defined, but some bits are common.  */
 441 #define M68K_CACR_EUSP  0x10
 442
 443 #define MACSR_PAV0  0x100
 444 #define MACSR_OMC   0x080
 445 #define MACSR_SU    0x040
 446 #define MACSR_FI    0x020
 447 #define MACSR_RT    0x010
 448 #define MACSR_N     0x008
 449 #define MACSR_Z     0x004
 450 #define MACSR_V     0x002
 451 #define MACSR_EV    0x001
 452
 453 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
 454 void m68k_switch_sp(CPUM68KState *env);
 455
 456 void do_m68k_semihosting(CPUM68KState *env, int nr);
 457
 458 /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
 459    Each feature covers the subset of instructions common to the
 460    ISA revisions mentioned.  */
 461
 462 enum m68k_features {
 463     M68K_FEATURE_M68000,
 464     M68K_FEATURE_CF_ISA_A,
 465     M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
 466     M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
 467     M68K_FEATURE_BRAL, /* Long unconditional branch.  (ISA A+ or B).  */
 468     M68K_FEATURE_CF_FPU,
 469     M68K_FEATURE_CF_MAC,
 470     M68K_FEATURE_CF_EMAC,
 471     M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
 472     M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
 473     M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
 474     M68K_FEATURE_WORD_INDEX, /* word sized address index registers.  */
 475     M68K_FEATURE_SCALED_INDEX, /* scaled address index registers.  */
 476     M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
 477     M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
 478     M68K_FEATURE_BCCL, /* Long conditional branches.  */
 479     M68K_FEATURE_BITFIELD, /* Bit field insns.  */
 480     M68K_FEATURE_FPU,
 481     M68K_FEATURE_CAS,
 482     M68K_FEATURE_BKPT,
 483     M68K_FEATURE_RTD,
 484     M68K_FEATURE_CHK2,
 485     M68K_FEATURE_M68040, /* instructions specific to MC68040 */
 486     M68K_FEATURE_MOVEP,
 487 };
 488
 489 static inline int m68k_feature(CPUM68KState *env, int feature)
 490 {
 491     return (env->features & (1u << feature)) != 0;
 492 }
 493
 494 void m68k_cpu_list(void);
 495
 496 void register_m68k_insns (CPUM68KState *env);
 497
 498 enum {
 499     /* 1 bit to define user level / supervisor access */
 500     ACCESS_SUPER = 0x01,
 501     /* 1 bit to indicate direction */
 502     ACCESS_STORE = 0x02,
 503     /* 1 bit to indicate debug access */
 504     ACCESS_DEBUG = 0x04,
 505     /* PTEST instruction */
 506     ACCESS_PTEST = 0x08,
 507     /* Type of instruction that generated the access */
 508     ACCESS_CODE  = 0x10, /* Code fetch access                */
 509     ACCESS_DATA  = 0x20, /* Data load/store access        */
 510 };
 511
 512 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
 513 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
 514 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU
 515
 516 #define cpu_signal_handler cpu_m68k_signal_handler
 517 #define cpu_list m68k_cpu_list
 518
 519 /* MMU modes definitions */
 520 #define MMU_MODE0_SUFFIX _kernel
 521 #define MMU_MODE1_SUFFIX _user
 522 #define MMU_KERNEL_IDX 0
 523 #define MMU_USER_IDX 1
 524 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
 525 {
 526     return (env->sr & SR_S) == 0 ? 1 : 0;
 527 }
 528
 529 bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 530                        MMUAccessType access_type, int mmu_idx,
 531                        bool probe, uintptr_t retaddr);
 532 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
 533                                  unsigned size, MMUAccessType access_type,
 534                                  int mmu_idx, MemTxAttrs attrs,
 535                                  MemTxResult response, uintptr_t retaddr);
 536
 537 typedef CPUM68KState CPUArchState;
 538 typedef M68kCPU ArchCPU;
 539
 540 #include "exec/cpu-all.h"
 541
 542 /* TB flags */
 543 #define TB_FLAGS_MACSR          0x0f
 544 #define TB_FLAGS_MSR_S_BIT      13
 545 #define TB_FLAGS_MSR_S          (1 << TB_FLAGS_MSR_S_BIT)
 546 #define TB_FLAGS_SFC_S_BIT      14
 547 #define TB_FLAGS_SFC_S          (1 << TB_FLAGS_SFC_S_BIT)
 548 #define TB_FLAGS_DFC_S_BIT      15
 549 #define TB_FLAGS_DFC_S          (1 << TB_FLAGS_DFC_S_BIT)
 550
 551 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
 552                                         target_ulong *cs_base, uint32_t *flags)
 553 {
 554     *pc = env->pc;
 555     *cs_base = 0;
 556     *flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
 557     if (env->sr & SR_S) {
 558         *flags |= TB_FLAGS_MSR_S;
 559         *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
 560         *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
 561     }
 562 }
 563
 564 void dump_mmu(CPUM68KState *env);
 565
 566 #endif