4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
28 #include "exec/translator.h"
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
33 #include "trace-tcg.h"
36 //#define DEBUG_DISPATCH 1
38 #define DEFO32(name, offset) static TCGv QREG_##name;
39 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
44 static TCGv_i32 cpu_halted
;
45 static TCGv_i32 cpu_exception_index
;
47 static char cpu_reg_names
[2 * 8 * 3 + 5 * 4];
48 static TCGv cpu_dregs
[8];
49 static TCGv cpu_aregs
[8];
50 static TCGv_i64 cpu_macc
[4];
52 #define REG(insn, pos) (((insn) >> (pos)) & 7)
53 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
54 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
55 #define MACREG(acc) cpu_macc[acc]
56 #define QREG_SP get_areg(s, 7)
58 static TCGv NULL_QREG
;
59 #define IS_NULL_QREG(t) (t == NULL_QREG)
60 /* Used to distinguish stores from bad addressing modes. */
61 static TCGv store_dummy
;
63 #include "exec/gen-icount.h"
65 void m68k_tcg_init(void)
70 #define DEFO32(name, offset) \
71 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
72 offsetof(CPUM68KState, offset), #name);
73 #define DEFO64(name, offset) \
74 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
75 offsetof(CPUM68KState, offset), #name);
80 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
81 -offsetof(M68kCPU
, env
) +
82 offsetof(CPUState
, halted
), "HALTED");
83 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
84 -offsetof(M68kCPU
, env
) +
85 offsetof(CPUState
, exception_index
),
89 for (i
= 0; i
< 8; i
++) {
91 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
92 offsetof(CPUM68KState
, dregs
[i
]), p
);
95 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
96 offsetof(CPUM68KState
, aregs
[i
]), p
);
99 for (i
= 0; i
< 4; i
++) {
100 sprintf(p
, "ACC%d", i
);
101 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
102 offsetof(CPUM68KState
, macc
[i
]), p
);
106 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
107 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
110 /* internal defines */
111 typedef struct DisasContext
{
113 target_ulong insn_pc
; /* Start of the current instruction. */
116 CCOp cc_op
; /* Current CC operation */
119 struct TranslationBlock
*tb
;
120 int singlestep_enabled
;
127 static TCGv
get_areg(DisasContext
*s
, unsigned regno
)
129 if (s
->writeback_mask
& (1 << regno
)) {
130 return s
->writeback
[regno
];
132 return cpu_aregs
[regno
];
136 static void delay_set_areg(DisasContext
*s
, unsigned regno
,
137 TCGv val
, bool give_temp
)
139 if (s
->writeback_mask
& (1 << regno
)) {
141 tcg_temp_free(s
->writeback
[regno
]);
142 s
->writeback
[regno
] = val
;
144 tcg_gen_mov_i32(s
->writeback
[regno
], val
);
147 s
->writeback_mask
|= 1 << regno
;
149 s
->writeback
[regno
] = val
;
151 TCGv tmp
= tcg_temp_new();
152 s
->writeback
[regno
] = tmp
;
153 tcg_gen_mov_i32(tmp
, val
);
158 static void do_writebacks(DisasContext
*s
)
160 unsigned mask
= s
->writeback_mask
;
162 s
->writeback_mask
= 0;
164 unsigned regno
= ctz32(mask
);
165 tcg_gen_mov_i32(cpu_aregs
[regno
], s
->writeback
[regno
]);
166 tcg_temp_free(s
->writeback
[regno
]);
172 /* is_jmp field values */
173 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
174 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
175 #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
176 #define DISAS_JUMP_NEXT DISAS_TARGET_3
178 #if defined(CONFIG_USER_ONLY)
181 #define IS_USER(s) s->user
184 /* XXX: move that elsewhere */
185 /* ??? Fix exceptions. */
186 static void *gen_throws_exception
;
187 #define gen_last_qop NULL
189 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
191 #ifdef DEBUG_DISPATCH
192 #define DISAS_INSN(name) \
193 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
195 static void disas_##name(CPUM68KState *env, DisasContext *s, \
198 qemu_log("Dispatch " #name "\n"); \
199 real_disas_##name(env, s, insn); \
201 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
204 #define DISAS_INSN(name) \
205 static void disas_##name(CPUM68KState *env, DisasContext *s, \
209 static const uint8_t cc_op_live
[CC_OP_NB
] = {
210 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
211 [CC_OP_ADDB
... CC_OP_ADDL
] = CCF_X
| CCF_N
| CCF_V
,
212 [CC_OP_SUBB
... CC_OP_SUBL
] = CCF_X
| CCF_N
| CCF_V
,
213 [CC_OP_CMPB
... CC_OP_CMPL
] = CCF_X
| CCF_N
| CCF_V
,
214 [CC_OP_LOGIC
] = CCF_X
| CCF_N
217 static void set_cc_op(DisasContext
*s
, CCOp op
)
219 CCOp old_op
= s
->cc_op
;
228 /* Discard CC computation that will no longer be used.
229 Note that X and N are never dead. */
230 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
232 tcg_gen_discard_i32(QREG_CC_C
);
235 tcg_gen_discard_i32(QREG_CC_Z
);
238 tcg_gen_discard_i32(QREG_CC_V
);
242 /* Update the CPU env CC_OP state. */
243 static void update_cc_op(DisasContext
*s
)
245 if (!s
->cc_op_synced
) {
247 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
251 /* Generate a jump to an immediate address. */
252 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
255 tcg_gen_movi_i32(QREG_PC
, dest
);
256 s
->is_jmp
= DISAS_JUMP
;
259 /* Generate a jump to the address in qreg DEST. */
260 static void gen_jmp(DisasContext
*s
, TCGv dest
)
263 tcg_gen_mov_i32(QREG_PC
, dest
);
264 s
->is_jmp
= DISAS_JUMP
;
267 static void gen_raise_exception(int nr
)
269 TCGv_i32 tmp
= tcg_const_i32(nr
);
271 gen_helper_raise_exception(cpu_env
, tmp
);
272 tcg_temp_free_i32(tmp
);
275 static void gen_exception(DisasContext
*s
, uint32_t where
, int nr
)
278 gen_jmp_im(s
, where
);
279 gen_raise_exception(nr
);
282 static inline void gen_addr_fault(DisasContext
*s
)
284 gen_exception(s
, s
->insn_pc
, EXCP_ADDRESS
);
287 /* Generate a load from the specified address. Narrow values are
288 sign extended to full register width. */
289 static inline TCGv
gen_load(DisasContext
* s
, int opsize
, TCGv addr
, int sign
)
292 int index
= IS_USER(s
);
293 tmp
= tcg_temp_new_i32();
297 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
299 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
303 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
305 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
308 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
311 g_assert_not_reached();
313 gen_throws_exception
= gen_last_qop
;
317 /* Generate a store. */
318 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
)
320 int index
= IS_USER(s
);
323 tcg_gen_qemu_st8(val
, addr
, index
);
326 tcg_gen_qemu_st16(val
, addr
, index
);
329 tcg_gen_qemu_st32(val
, addr
, index
);
332 g_assert_not_reached();
334 gen_throws_exception
= gen_last_qop
;
343 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
344 otherwise generate a store. */
345 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
348 if (what
== EA_STORE
) {
349 gen_store(s
, opsize
, addr
, val
);
352 return gen_load(s
, opsize
, addr
, what
== EA_LOADS
);
356 /* Read a 16-bit immediate constant */
357 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
360 im
= cpu_lduw_code(env
, s
->pc
);
365 /* Read an 8-bit immediate constant */
366 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
368 return read_im16(env
, s
);
371 /* Read a 32-bit immediate constant. */
372 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
375 im
= read_im16(env
, s
) << 16;
376 im
|= 0xffff & read_im16(env
, s
);
380 /* Read a 64-bit immediate constant. */
381 static inline uint64_t read_im64(CPUM68KState
*env
, DisasContext
*s
)
384 im
= (uint64_t)read_im32(env
, s
) << 32;
385 im
|= (uint64_t)read_im32(env
, s
);
389 /* Calculate and address index. */
390 static TCGv
gen_addr_index(DisasContext
*s
, uint16_t ext
, TCGv tmp
)
395 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
396 if ((ext
& 0x800) == 0) {
397 tcg_gen_ext16s_i32(tmp
, add
);
400 scale
= (ext
>> 9) & 3;
402 tcg_gen_shli_i32(tmp
, add
, scale
);
408 /* Handle a base + index + displacement effective addresss.
409 A NULL_QREG base means pc-relative. */
410 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
419 ext
= read_im16(env
, s
);
421 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
424 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
) &&
425 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
430 /* full extension word format */
431 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
434 if ((ext
& 0x30) > 0x10) {
435 /* base displacement */
436 if ((ext
& 0x30) == 0x20) {
437 bd
= (int16_t)read_im16(env
, s
);
439 bd
= read_im32(env
, s
);
444 tmp
= tcg_temp_new();
445 if ((ext
& 0x44) == 0) {
447 add
= gen_addr_index(s
, ext
, tmp
);
451 if ((ext
& 0x80) == 0) {
452 /* base not suppressed */
453 if (IS_NULL_QREG(base
)) {
454 base
= tcg_const_i32(offset
+ bd
);
457 if (!IS_NULL_QREG(add
)) {
458 tcg_gen_add_i32(tmp
, add
, base
);
464 if (!IS_NULL_QREG(add
)) {
466 tcg_gen_addi_i32(tmp
, add
, bd
);
470 add
= tcg_const_i32(bd
);
472 if ((ext
& 3) != 0) {
473 /* memory indirect */
474 base
= gen_load(s
, OS_LONG
, add
, 0);
475 if ((ext
& 0x44) == 4) {
476 add
= gen_addr_index(s
, ext
, tmp
);
477 tcg_gen_add_i32(tmp
, add
, base
);
483 /* outer displacement */
484 if ((ext
& 3) == 2) {
485 od
= (int16_t)read_im16(env
, s
);
487 od
= read_im32(env
, s
);
493 tcg_gen_addi_i32(tmp
, add
, od
);
498 /* brief extension word format */
499 tmp
= tcg_temp_new();
500 add
= gen_addr_index(s
, ext
, tmp
);
501 if (!IS_NULL_QREG(base
)) {
502 tcg_gen_add_i32(tmp
, add
, base
);
504 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
506 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
513 /* Sign or zero extend a value. */
515 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
520 tcg_gen_ext8s_i32(res
, val
);
522 tcg_gen_ext8u_i32(res
, val
);
527 tcg_gen_ext16s_i32(res
, val
);
529 tcg_gen_ext16u_i32(res
, val
);
533 tcg_gen_mov_i32(res
, val
);
536 g_assert_not_reached();
540 /* Evaluate all the CC flags. */
542 static void gen_flush_flags(DisasContext
*s
)
553 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
554 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
555 /* Compute signed overflow for addition. */
558 tcg_gen_sub_i32(t0
, QREG_CC_N
, QREG_CC_V
);
559 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_ADDB
, 1);
560 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
561 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
563 tcg_gen_andc_i32(QREG_CC_V
, t1
, QREG_CC_V
);
570 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
571 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
572 /* Compute signed overflow for subtraction. */
575 tcg_gen_add_i32(t0
, QREG_CC_N
, QREG_CC_V
);
576 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_SUBB
, 1);
577 tcg_gen_xor_i32(t1
, QREG_CC_N
, t0
);
578 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
580 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t1
);
587 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_C
, QREG_CC_N
, QREG_CC_V
);
588 tcg_gen_sub_i32(QREG_CC_Z
, QREG_CC_N
, QREG_CC_V
);
589 gen_ext(QREG_CC_Z
, QREG_CC_Z
, s
->cc_op
- CC_OP_CMPB
, 1);
590 /* Compute signed overflow for subtraction. */
592 tcg_gen_xor_i32(t0
, QREG_CC_Z
, QREG_CC_N
);
593 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, QREG_CC_N
);
594 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t0
);
596 tcg_gen_mov_i32(QREG_CC_N
, QREG_CC_Z
);
600 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
601 tcg_gen_movi_i32(QREG_CC_C
, 0);
602 tcg_gen_movi_i32(QREG_CC_V
, 0);
606 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
611 t0
= tcg_const_i32(s
->cc_op
);
612 gen_helper_flush_flags(cpu_env
, t0
);
618 /* Note that flush_flags also assigned to env->cc_op. */
619 s
->cc_op
= CC_OP_FLAGS
;
622 static inline TCGv
gen_extend(TCGv val
, int opsize
, int sign
)
626 if (opsize
== OS_LONG
) {
629 tmp
= tcg_temp_new();
630 gen_ext(tmp
, val
, opsize
, sign
);
636 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
638 gen_ext(QREG_CC_N
, val
, opsize
, 1);
639 set_cc_op(s
, CC_OP_LOGIC
);
642 static void gen_update_cc_cmp(DisasContext
*s
, TCGv dest
, TCGv src
, int opsize
)
644 tcg_gen_mov_i32(QREG_CC_N
, dest
);
645 tcg_gen_mov_i32(QREG_CC_V
, src
);
646 set_cc_op(s
, CC_OP_CMPB
+ opsize
);
649 static void gen_update_cc_add(TCGv dest
, TCGv src
, int opsize
)
651 gen_ext(QREG_CC_N
, dest
, opsize
, 1);
652 tcg_gen_mov_i32(QREG_CC_V
, src
);
655 static inline int opsize_bytes(int opsize
)
658 case OS_BYTE
: return 1;
659 case OS_WORD
: return 2;
660 case OS_LONG
: return 4;
661 case OS_SINGLE
: return 4;
662 case OS_DOUBLE
: return 8;
663 case OS_EXTENDED
: return 12;
664 case OS_PACKED
: return 12;
666 g_assert_not_reached();
670 static inline int insn_opsize(int insn
)
672 switch ((insn
>> 6) & 3) {
673 case 0: return OS_BYTE
;
674 case 1: return OS_WORD
;
675 case 2: return OS_LONG
;
677 g_assert_not_reached();
681 static inline int ext_opsize(int ext
, int pos
)
683 switch ((ext
>> pos
) & 7) {
684 case 0: return OS_LONG
;
685 case 1: return OS_SINGLE
;
686 case 2: return OS_EXTENDED
;
687 case 3: return OS_PACKED
;
688 case 4: return OS_WORD
;
689 case 5: return OS_DOUBLE
;
690 case 6: return OS_BYTE
;
692 g_assert_not_reached();
696 /* Assign value to a register. If the width is less than the register width
697 only the low part of the register is set. */
698 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
703 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
704 tmp
= tcg_temp_new();
705 tcg_gen_ext8u_i32(tmp
, val
);
706 tcg_gen_or_i32(reg
, reg
, tmp
);
710 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
711 tmp
= tcg_temp_new();
712 tcg_gen_ext16u_i32(tmp
, val
);
713 tcg_gen_or_i32(reg
, reg
, tmp
);
718 tcg_gen_mov_i32(reg
, val
);
721 g_assert_not_reached();
725 /* Generate code for an "effective address". Does not adjust the base
726 register for autoincrement addressing modes. */
727 static TCGv
gen_lea_mode(CPUM68KState
*env
, DisasContext
*s
,
728 int mode
, int reg0
, int opsize
)
736 case 0: /* Data register direct. */
737 case 1: /* Address register direct. */
739 case 3: /* Indirect postincrement. */
740 if (opsize
== OS_UNSIZED
) {
744 case 2: /* Indirect register */
745 return get_areg(s
, reg0
);
746 case 4: /* Indirect predecrememnt. */
747 if (opsize
== OS_UNSIZED
) {
750 reg
= get_areg(s
, reg0
);
751 tmp
= tcg_temp_new();
752 if (reg0
== 7 && opsize
== OS_BYTE
&&
753 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
754 tcg_gen_subi_i32(tmp
, reg
, 2);
756 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
759 case 5: /* Indirect displacement. */
760 reg
= get_areg(s
, reg0
);
761 tmp
= tcg_temp_new();
762 ext
= read_im16(env
, s
);
763 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
765 case 6: /* Indirect index + displacement. */
766 reg
= get_areg(s
, reg0
);
767 return gen_lea_indexed(env
, s
, reg
);
770 case 0: /* Absolute short. */
771 offset
= (int16_t)read_im16(env
, s
);
772 return tcg_const_i32(offset
);
773 case 1: /* Absolute long. */
774 offset
= read_im32(env
, s
);
775 return tcg_const_i32(offset
);
776 case 2: /* pc displacement */
778 offset
+= (int16_t)read_im16(env
, s
);
779 return tcg_const_i32(offset
);
780 case 3: /* pc index+displacement. */
781 return gen_lea_indexed(env
, s
, NULL_QREG
);
782 case 4: /* Immediate. */
787 /* Should never happen. */
791 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
794 int mode
= extract32(insn
, 3, 3);
795 int reg0
= REG(insn
, 0);
796 return gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
799 /* Generate code to load/store a value from/into an EA. If WHAT > 0 this is
800 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
801 ADDRP is non-null for readwrite operands. */
802 static TCGv
gen_ea_mode(CPUM68KState
*env
, DisasContext
*s
, int mode
, int reg0
,
803 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
)
805 TCGv reg
, tmp
, result
;
809 case 0: /* Data register direct. */
810 reg
= cpu_dregs
[reg0
];
811 if (what
== EA_STORE
) {
812 gen_partset_reg(opsize
, reg
, val
);
815 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
817 case 1: /* Address register direct. */
818 reg
= get_areg(s
, reg0
);
819 if (what
== EA_STORE
) {
820 tcg_gen_mov_i32(reg
, val
);
823 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
825 case 2: /* Indirect register */
826 reg
= get_areg(s
, reg0
);
827 return gen_ldst(s
, opsize
, reg
, val
, what
);
828 case 3: /* Indirect postincrement. */
829 reg
= get_areg(s
, reg0
);
830 result
= gen_ldst(s
, opsize
, reg
, val
, what
);
831 if (what
== EA_STORE
|| !addrp
) {
832 TCGv tmp
= tcg_temp_new();
833 if (reg0
== 7 && opsize
== OS_BYTE
&&
834 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
835 tcg_gen_addi_i32(tmp
, reg
, 2);
837 tcg_gen_addi_i32(tmp
, reg
, opsize_bytes(opsize
));
839 delay_set_areg(s
, reg0
, tmp
, true);
842 case 4: /* Indirect predecrememnt. */
843 if (addrp
&& what
== EA_STORE
) {
846 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
847 if (IS_NULL_QREG(tmp
)) {
854 result
= gen_ldst(s
, opsize
, tmp
, val
, what
);
855 if (what
== EA_STORE
|| !addrp
) {
856 delay_set_areg(s
, reg0
, tmp
, false);
859 case 5: /* Indirect displacement. */
860 case 6: /* Indirect index + displacement. */
862 if (addrp
&& what
== EA_STORE
) {
865 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
866 if (IS_NULL_QREG(tmp
)) {
873 return gen_ldst(s
, opsize
, tmp
, val
, what
);
876 case 0: /* Absolute short. */
877 case 1: /* Absolute long. */
878 case 2: /* pc displacement */
879 case 3: /* pc index+displacement. */
881 case 4: /* Immediate. */
882 /* Sign extend values for consistency. */
885 if (what
== EA_LOADS
) {
886 offset
= (int8_t)read_im8(env
, s
);
888 offset
= read_im8(env
, s
);
892 if (what
== EA_LOADS
) {
893 offset
= (int16_t)read_im16(env
, s
);
895 offset
= read_im16(env
, s
);
899 offset
= read_im32(env
, s
);
902 g_assert_not_reached();
904 return tcg_const_i32(offset
);
909 /* Should never happen. */
913 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
914 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
)
916 int mode
= extract32(insn
, 3, 3);
917 int reg0
= REG(insn
, 0);
918 return gen_ea_mode(env
, s
, mode
, reg0
, opsize
, val
, addrp
, what
);
921 static TCGv_ptr
gen_fp_ptr(int freg
)
923 TCGv_ptr fp
= tcg_temp_new_ptr();
924 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fregs
[freg
]));
928 static TCGv_ptr
gen_fp_result_ptr(void)
930 TCGv_ptr fp
= tcg_temp_new_ptr();
931 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fp_result
));
935 static void gen_fp_move(TCGv_ptr dest
, TCGv_ptr src
)
940 t32
= tcg_temp_new();
941 tcg_gen_ld16u_i32(t32
, src
, offsetof(FPReg
, l
.upper
));
942 tcg_gen_st16_i32(t32
, dest
, offsetof(FPReg
, l
.upper
));
945 t64
= tcg_temp_new_i64();
946 tcg_gen_ld_i64(t64
, src
, offsetof(FPReg
, l
.lower
));
947 tcg_gen_st_i64(t64
, dest
, offsetof(FPReg
, l
.lower
));
948 tcg_temp_free_i64(t64
);
951 static void gen_load_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
)
955 int index
= IS_USER(s
);
957 t64
= tcg_temp_new_i64();
958 tmp
= tcg_temp_new();
961 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
962 gen_helper_exts32(cpu_env
, fp
, tmp
);
965 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
966 gen_helper_exts32(cpu_env
, fp
, tmp
);
969 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
970 gen_helper_exts32(cpu_env
, fp
, tmp
);
973 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
974 gen_helper_extf32(cpu_env
, fp
, tmp
);
977 tcg_gen_qemu_ld64(t64
, addr
, index
);
978 gen_helper_extf64(cpu_env
, fp
, t64
);
979 tcg_temp_free_i64(t64
);
982 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
983 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
986 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
987 tcg_gen_shri_i32(tmp
, tmp
, 16);
988 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
989 tcg_gen_addi_i32(tmp
, addr
, 4);
990 tcg_gen_qemu_ld64(t64
, tmp
, index
);
991 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
994 /* unimplemented data type on 68040/ColdFire
995 * FIXME if needed for another FPU
997 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1000 g_assert_not_reached();
1003 tcg_temp_free_i64(t64
);
1004 gen_throws_exception
= gen_last_qop
;
1007 static void gen_store_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
)
1011 int index
= IS_USER(s
);
1013 t64
= tcg_temp_new_i64();
1014 tmp
= tcg_temp_new();
1017 gen_helper_reds32(tmp
, cpu_env
, fp
);
1018 tcg_gen_qemu_st8(tmp
, addr
, index
);
1021 gen_helper_reds32(tmp
, cpu_env
, fp
);
1022 tcg_gen_qemu_st16(tmp
, addr
, index
);
1025 gen_helper_reds32(tmp
, cpu_env
, fp
);
1026 tcg_gen_qemu_st32(tmp
, addr
, index
);
1029 gen_helper_redf32(tmp
, cpu_env
, fp
);
1030 tcg_gen_qemu_st32(tmp
, addr
, index
);
1033 gen_helper_redf64(t64
, cpu_env
, fp
);
1034 tcg_gen_qemu_st64(t64
, addr
, index
);
1037 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1038 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1041 tcg_gen_ld16u_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1042 tcg_gen_shli_i32(tmp
, tmp
, 16);
1043 tcg_gen_qemu_st32(tmp
, addr
, index
);
1044 tcg_gen_addi_i32(tmp
, addr
, 4);
1045 tcg_gen_ld_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1046 tcg_gen_qemu_st64(t64
, tmp
, index
);
1049 /* unimplemented data type on 68040/ColdFire
1050 * FIXME if needed for another FPU
1052 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1055 g_assert_not_reached();
1058 tcg_temp_free_i64(t64
);
1059 gen_throws_exception
= gen_last_qop
;
1062 static void gen_ldst_fp(DisasContext
*s
, int opsize
, TCGv addr
,
1063 TCGv_ptr fp
, ea_what what
)
1065 if (what
== EA_STORE
) {
1066 gen_store_fp(s
, opsize
, addr
, fp
);
1068 gen_load_fp(s
, opsize
, addr
, fp
);
1072 static int gen_ea_mode_fp(CPUM68KState
*env
, DisasContext
*s
, int mode
,
1073 int reg0
, int opsize
, TCGv_ptr fp
, ea_what what
)
1075 TCGv reg
, addr
, tmp
;
1079 case 0: /* Data register direct. */
1080 reg
= cpu_dregs
[reg0
];
1081 if (what
== EA_STORE
) {
1086 gen_helper_reds32(reg
, cpu_env
, fp
);
1089 gen_helper_redf32(reg
, cpu_env
, fp
);
1092 g_assert_not_reached();
1095 tmp
= tcg_temp_new();
1098 tcg_gen_ext8s_i32(tmp
, reg
);
1099 gen_helper_exts32(cpu_env
, fp
, tmp
);
1102 tcg_gen_ext16s_i32(tmp
, reg
);
1103 gen_helper_exts32(cpu_env
, fp
, tmp
);
1106 gen_helper_exts32(cpu_env
, fp
, reg
);
1109 gen_helper_extf32(cpu_env
, fp
, reg
);
1112 g_assert_not_reached();
1117 case 1: /* Address register direct. */
1119 case 2: /* Indirect register */
1120 addr
= get_areg(s
, reg0
);
1121 gen_ldst_fp(s
, opsize
, addr
, fp
, what
);
1123 case 3: /* Indirect postincrement. */
1124 addr
= cpu_aregs
[reg0
];
1125 gen_ldst_fp(s
, opsize
, addr
, fp
, what
);
1126 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(opsize
));
1128 case 4: /* Indirect predecrememnt. */
1129 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1130 if (IS_NULL_QREG(addr
)) {
1133 gen_ldst_fp(s
, opsize
, addr
, fp
, what
);
1134 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
1136 case 5: /* Indirect displacement. */
1137 case 6: /* Indirect index + displacement. */
1139 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1140 if (IS_NULL_QREG(addr
)) {
1143 gen_ldst_fp(s
, opsize
, addr
, fp
, what
);
1147 case 0: /* Absolute short. */
1148 case 1: /* Absolute long. */
1149 case 2: /* pc displacement */
1150 case 3: /* pc index+displacement. */
1152 case 4: /* Immediate. */
1153 if (what
== EA_STORE
) {
1158 tmp
= tcg_const_i32((int8_t)read_im8(env
, s
));
1159 gen_helper_exts32(cpu_env
, fp
, tmp
);
1163 tmp
= tcg_const_i32((int16_t)read_im16(env
, s
));
1164 gen_helper_exts32(cpu_env
, fp
, tmp
);
1168 tmp
= tcg_const_i32(read_im32(env
, s
));
1169 gen_helper_exts32(cpu_env
, fp
, tmp
);
1173 tmp
= tcg_const_i32(read_im32(env
, s
));
1174 gen_helper_extf32(cpu_env
, fp
, tmp
);
1178 t64
= tcg_const_i64(read_im64(env
, s
));
1179 gen_helper_extf64(cpu_env
, fp
, t64
);
1180 tcg_temp_free_i64(t64
);
1183 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1184 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1187 tmp
= tcg_const_i32(read_im32(env
, s
) >> 16);
1188 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1190 t64
= tcg_const_i64(read_im64(env
, s
));
1191 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1192 tcg_temp_free_i64(t64
);
1195 /* unimplemented data type on 68040/ColdFire
1196 * FIXME if needed for another FPU
1198 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1201 g_assert_not_reached();
1211 static int gen_ea_fp(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1212 int opsize
, TCGv_ptr fp
, ea_what what
)
1214 int mode
= extract32(insn
, 3, 3);
1215 int reg0
= REG(insn
, 0);
1216 return gen_ea_mode_fp(env
, s
, mode
, reg0
, opsize
, fp
, what
);
1227 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
1233 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1234 if (op
== CC_OP_CMPB
|| op
== CC_OP_CMPW
|| op
== CC_OP_CMPL
) {
1241 tcond
= TCG_COND_LEU
;
1245 tcond
= TCG_COND_LTU
;
1249 tcond
= TCG_COND_EQ
;
1254 c
->v2
= tcg_const_i32(0);
1255 c
->v1
= tmp
= tcg_temp_new();
1256 tcg_gen_sub_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1257 gen_ext(tmp
, tmp
, op
- CC_OP_CMPB
, 1);
1261 tcond
= TCG_COND_LT
;
1265 tcond
= TCG_COND_LE
;
1272 c
->v2
= tcg_const_i32(0);
1278 tcond
= TCG_COND_NEVER
;
1280 case 14: /* GT (!(Z || (N ^ V))) */
1281 case 15: /* LE (Z || (N ^ V)) */
1282 /* Logic operations clear V, which simplifies LE to (Z || N),
1283 and since Z and N are co-located, this becomes a normal
1285 if (op
== CC_OP_LOGIC
) {
1287 tcond
= TCG_COND_LE
;
1291 case 12: /* GE (!(N ^ V)) */
1292 case 13: /* LT (N ^ V) */
1293 /* Logic operations clear V, which simplifies this to N. */
1294 if (op
!= CC_OP_LOGIC
) {
1298 case 10: /* PL (!N) */
1299 case 11: /* MI (N) */
1300 /* Several cases represent N normally. */
1301 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1302 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1303 op
== CC_OP_LOGIC
) {
1305 tcond
= TCG_COND_LT
;
1309 case 6: /* NE (!Z) */
1310 case 7: /* EQ (Z) */
1311 /* Some cases fold Z into N. */
1312 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1313 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1314 op
== CC_OP_LOGIC
) {
1315 tcond
= TCG_COND_EQ
;
1320 case 4: /* CC (!C) */
1321 case 5: /* CS (C) */
1322 /* Some cases fold C into X. */
1323 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1324 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
) {
1325 tcond
= TCG_COND_NE
;
1330 case 8: /* VC (!V) */
1331 case 9: /* VS (V) */
1332 /* Logic operations clear V and C. */
1333 if (op
== CC_OP_LOGIC
) {
1334 tcond
= TCG_COND_NEVER
;
1341 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1348 /* Invalid, or handled above. */
1350 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1351 case 3: /* LS (C || Z) */
1352 c
->v1
= tmp
= tcg_temp_new();
1354 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1355 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
1356 tcond
= TCG_COND_NE
;
1358 case 4: /* CC (!C) */
1359 case 5: /* CS (C) */
1361 tcond
= TCG_COND_NE
;
1363 case 6: /* NE (!Z) */
1364 case 7: /* EQ (Z) */
1366 tcond
= TCG_COND_EQ
;
1368 case 8: /* VC (!V) */
1369 case 9: /* VS (V) */
1371 tcond
= TCG_COND_LT
;
1373 case 10: /* PL (!N) */
1374 case 11: /* MI (N) */
1376 tcond
= TCG_COND_LT
;
1378 case 12: /* GE (!(N ^ V)) */
1379 case 13: /* LT (N ^ V) */
1380 c
->v1
= tmp
= tcg_temp_new();
1382 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1383 tcond
= TCG_COND_LT
;
1385 case 14: /* GT (!(Z || (N ^ V))) */
1386 case 15: /* LE (Z || (N ^ V)) */
1387 c
->v1
= tmp
= tcg_temp_new();
1389 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1390 tcg_gen_neg_i32(tmp
, tmp
);
1391 tmp2
= tcg_temp_new();
1392 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
1393 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1394 tcg_temp_free(tmp2
);
1395 tcond
= TCG_COND_LT
;
1400 if ((cond
& 1) == 0) {
1401 tcond
= tcg_invert_cond(tcond
);
1406 static void free_cond(DisasCompare
*c
)
1409 tcg_temp_free(c
->v1
);
1412 tcg_temp_free(c
->v2
);
1416 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
1420 gen_cc_cond(&c
, s
, cond
);
1422 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
1426 /* Force a TB lookup after an instruction that changes the CPU state. */
1427 static void gen_lookup_tb(DisasContext
*s
)
1430 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
1431 s
->is_jmp
= DISAS_UPDATE
;
1434 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1435 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1436 op_sign ? EA_LOADS : EA_LOADU); \
1437 if (IS_NULL_QREG(result)) { \
1438 gen_addr_fault(s); \
1443 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1444 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
1445 if (IS_NULL_QREG(ea_result)) { \
1446 gen_addr_fault(s); \
1451 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
1453 #ifndef CONFIG_USER_ONLY
1454 return (s
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
1455 (s
->insn_pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
1461 /* Generate a jump to an immediate address. */
1462 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
1464 if (unlikely(s
->singlestep_enabled
)) {
1465 gen_exception(s
, dest
, EXCP_DEBUG
);
1466 } else if (use_goto_tb(s
, dest
)) {
1468 tcg_gen_movi_i32(QREG_PC
, dest
);
1469 tcg_gen_exit_tb((uintptr_t)s
->tb
+ n
);
1471 gen_jmp_im(s
, dest
);
1474 s
->is_jmp
= DISAS_TB_JUMP
;
1483 cond
= (insn
>> 8) & 0xf;
1484 gen_cc_cond(&c
, s
, cond
);
1486 tmp
= tcg_temp_new();
1487 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
1490 tcg_gen_neg_i32(tmp
, tmp
);
1491 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
1503 reg
= DREG(insn
, 0);
1505 offset
= (int16_t)read_im16(env
, s
);
1506 l1
= gen_new_label();
1507 gen_jmpcc(s
, (insn
>> 8) & 0xf, l1
);
1509 tmp
= tcg_temp_new();
1510 tcg_gen_ext16s_i32(tmp
, reg
);
1511 tcg_gen_addi_i32(tmp
, tmp
, -1);
1512 gen_partset_reg(OS_WORD
, reg
, tmp
);
1513 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, -1, l1
);
1514 gen_jmp_tb(s
, 1, base
+ offset
);
1516 gen_jmp_tb(s
, 0, s
->pc
);
1519 DISAS_INSN(undef_mac
)
1521 gen_exception(s
, s
->pc
- 2, EXCP_LINEA
);
1524 DISAS_INSN(undef_fpu
)
1526 gen_exception(s
, s
->pc
- 2, EXCP_LINEF
);
1531 /* ??? This is both instructions that are as yet unimplemented
1532 for the 680x0 series, as well as those that are implemented
1533 but actually illegal for CPU32 or pre-68020. */
1534 qemu_log_mask(LOG_UNIMP
, "Illegal instruction: %04x @ %08x",
1536 gen_exception(s
, s
->pc
- 2, EXCP_UNSUPPORTED
);
1546 sign
= (insn
& 0x100) != 0;
1547 reg
= DREG(insn
, 9);
1548 tmp
= tcg_temp_new();
1550 tcg_gen_ext16s_i32(tmp
, reg
);
1552 tcg_gen_ext16u_i32(tmp
, reg
);
1553 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1554 tcg_gen_mul_i32(tmp
, tmp
, src
);
1555 tcg_gen_mov_i32(reg
, tmp
);
1556 gen_logic_cc(s
, tmp
, OS_LONG
);
1566 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1568 sign
= (insn
& 0x100) != 0;
1570 /* dest.l / src.w */
1572 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1573 destr
= tcg_const_i32(REG(insn
, 9));
1575 gen_helper_divsw(cpu_env
, destr
, src
);
1577 gen_helper_divuw(cpu_env
, destr
, src
);
1579 tcg_temp_free(destr
);
1581 set_cc_op(s
, CC_OP_FLAGS
);
1590 ext
= read_im16(env
, s
);
1592 sign
= (ext
& 0x0800) != 0;
1595 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
1596 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
1600 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1602 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1603 num
= tcg_const_i32(REG(ext
, 12));
1604 reg
= tcg_const_i32(REG(ext
, 0));
1606 gen_helper_divsll(cpu_env
, num
, reg
, den
);
1608 gen_helper_divull(cpu_env
, num
, reg
, den
);
1612 set_cc_op(s
, CC_OP_FLAGS
);
1616 /* divX.l <EA>, Dq 32/32 -> 32q */
1617 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1619 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1620 num
= tcg_const_i32(REG(ext
, 12));
1621 reg
= tcg_const_i32(REG(ext
, 0));
1623 gen_helper_divsl(cpu_env
, num
, reg
, den
);
1625 gen_helper_divul(cpu_env
, num
, reg
, den
);
1630 set_cc_op(s
, CC_OP_FLAGS
);
1633 static void bcd_add(TCGv dest
, TCGv src
)
1637 /* dest10 = dest10 + src10 + X
1641 * t3 = t2 + dest + X
1645 * t7 = (t6 >> 2) | (t6 >> 3)
1649 /* t1 = (src + 0x066) + dest + X
1650 * = result with some possible exceding 0x6
1653 t0
= tcg_const_i32(0x066);
1654 tcg_gen_add_i32(t0
, t0
, src
);
1656 t1
= tcg_temp_new();
1657 tcg_gen_add_i32(t1
, t0
, dest
);
1658 tcg_gen_add_i32(t1
, t1
, QREG_CC_X
);
1660 /* we will remove exceding 0x6 where there is no carry */
1662 /* t0 = (src + 0x0066) ^ dest
1663 * = t1 without carries
1666 tcg_gen_xor_i32(t0
, t0
, dest
);
1668 /* extract the carries
1670 * = only the carries
1673 tcg_gen_xor_i32(t0
, t0
, t1
);
1675 /* generate 0x1 where there is no carry
1676 * and for each 0x10, generate a 0x6
1679 tcg_gen_shri_i32(t0
, t0
, 3);
1680 tcg_gen_not_i32(t0
, t0
);
1681 tcg_gen_andi_i32(t0
, t0
, 0x22);
1682 tcg_gen_add_i32(dest
, t0
, t0
);
1683 tcg_gen_add_i32(dest
, dest
, t0
);
1686 /* remove the exceding 0x6
1687 * for digits that have not generated a carry
1690 tcg_gen_sub_i32(dest
, t1
, dest
);
1694 static void bcd_sub(TCGv dest
, TCGv src
)
1698 /* dest10 = dest10 - src10 - X
1699 * = bcd_add(dest + 1 - X, 0x199 - src)
1702 /* t0 = 0x066 + (0x199 - src) */
1704 t0
= tcg_temp_new();
1705 tcg_gen_subfi_i32(t0
, 0x1ff, src
);
1707 /* t1 = t0 + dest + 1 - X*/
1709 t1
= tcg_temp_new();
1710 tcg_gen_add_i32(t1
, t0
, dest
);
1711 tcg_gen_addi_i32(t1
, t1
, 1);
1712 tcg_gen_sub_i32(t1
, t1
, QREG_CC_X
);
1714 /* t2 = t0 ^ dest */
1716 t2
= tcg_temp_new();
1717 tcg_gen_xor_i32(t2
, t0
, dest
);
1721 tcg_gen_xor_i32(t0
, t1
, t2
);
1724 * t0 = (t2 >> 2) | (t2 >> 3)
1726 * to fit on 8bit operands, changed in:
1728 * t2 = ~(t0 >> 3) & 0x22
1733 tcg_gen_shri_i32(t2
, t0
, 3);
1734 tcg_gen_not_i32(t2
, t2
);
1735 tcg_gen_andi_i32(t2
, t2
, 0x22);
1736 tcg_gen_add_i32(t0
, t2
, t2
);
1737 tcg_gen_add_i32(t0
, t0
, t2
);
1740 /* return t1 - t0 */
1742 tcg_gen_sub_i32(dest
, t1
, t0
);
1747 static void bcd_flags(TCGv val
)
1749 tcg_gen_andi_i32(QREG_CC_C
, val
, 0x0ff);
1750 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_C
);
1752 tcg_gen_extract_i32(QREG_CC_C
, val
, 8, 1);
1754 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
1757 DISAS_INSN(abcd_reg
)
1762 gen_flush_flags(s
); /* !Z is sticky */
1764 src
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
1765 dest
= gen_extend(DREG(insn
, 9), OS_BYTE
, 0);
1767 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1772 DISAS_INSN(abcd_mem
)
1774 TCGv src
, dest
, addr
;
1776 gen_flush_flags(s
); /* !Z is sticky */
1778 /* Indirect pre-decrement load (mode 4) */
1780 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1781 NULL_QREG
, NULL
, EA_LOADU
);
1782 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1783 NULL_QREG
, &addr
, EA_LOADU
);
1787 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
, EA_STORE
);
1792 DISAS_INSN(sbcd_reg
)
1796 gen_flush_flags(s
); /* !Z is sticky */
1798 src
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
1799 dest
= gen_extend(DREG(insn
, 9), OS_BYTE
, 0);
1803 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1808 DISAS_INSN(sbcd_mem
)
1810 TCGv src
, dest
, addr
;
1812 gen_flush_flags(s
); /* !Z is sticky */
1814 /* Indirect pre-decrement load (mode 4) */
1816 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1817 NULL_QREG
, NULL
, EA_LOADU
);
1818 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1819 NULL_QREG
, &addr
, EA_LOADU
);
1823 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
, EA_STORE
);
1833 gen_flush_flags(s
); /* !Z is sticky */
1835 SRC_EA(env
, src
, OS_BYTE
, 0, &addr
);
1837 dest
= tcg_const_i32(0);
1840 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1844 tcg_temp_free(dest
);
1857 add
= (insn
& 0x4000) != 0;
1858 opsize
= insn_opsize(insn
);
1859 reg
= gen_extend(DREG(insn
, 9), opsize
, 1);
1860 dest
= tcg_temp_new();
1862 SRC_EA(env
, tmp
, opsize
, 1, &addr
);
1866 SRC_EA(env
, src
, opsize
, 1, NULL
);
1869 tcg_gen_add_i32(dest
, tmp
, src
);
1870 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1871 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
1873 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1874 tcg_gen_sub_i32(dest
, tmp
, src
);
1875 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
1877 gen_update_cc_add(dest
, src
, opsize
);
1879 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1881 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
1883 tcg_temp_free(dest
);
1886 /* Reverse the order of the bits in REG. */
1890 reg
= DREG(insn
, 0);
1891 gen_helper_bitrev(reg
, reg
);
1894 DISAS_INSN(bitop_reg
)
1904 if ((insn
& 0x38) != 0)
1908 op
= (insn
>> 6) & 3;
1909 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1912 src2
= tcg_temp_new();
1913 if (opsize
== OS_BYTE
)
1914 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 7);
1916 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 31);
1918 tmp
= tcg_const_i32(1);
1919 tcg_gen_shl_i32(tmp
, tmp
, src2
);
1920 tcg_temp_free(src2
);
1922 tcg_gen_and_i32(QREG_CC_Z
, src1
, tmp
);
1924 dest
= tcg_temp_new();
1927 tcg_gen_xor_i32(dest
, src1
, tmp
);
1930 tcg_gen_andc_i32(dest
, src1
, tmp
);
1933 tcg_gen_or_i32(dest
, src1
, tmp
);
1940 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1942 tcg_temp_free(dest
);
1948 reg
= DREG(insn
, 0);
1950 gen_helper_sats(reg
, reg
, QREG_CC_V
);
1951 gen_logic_cc(s
, reg
, OS_LONG
);
1954 static void gen_push(DisasContext
*s
, TCGv val
)
1958 tmp
= tcg_temp_new();
1959 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1960 gen_store(s
, OS_LONG
, tmp
, val
);
1961 tcg_gen_mov_i32(QREG_SP
, tmp
);
1965 static TCGv
mreg(int reg
)
1969 return cpu_dregs
[reg
];
1972 return cpu_aregs
[reg
& 7];
1977 TCGv addr
, incr
, tmp
, r
[16];
1978 int is_load
= (insn
& 0x0400) != 0;
1979 int opsize
= (insn
& 0x40) != 0 ? OS_LONG
: OS_WORD
;
1980 uint16_t mask
= read_im16(env
, s
);
1981 int mode
= extract32(insn
, 3, 3);
1982 int reg0
= REG(insn
, 0);
1985 tmp
= cpu_aregs
[reg0
];
1988 case 0: /* data register direct */
1989 case 1: /* addr register direct */
1994 case 2: /* indirect */
1997 case 3: /* indirect post-increment */
1999 /* post-increment is not allowed */
2004 case 4: /* indirect pre-decrement */
2006 /* pre-decrement is not allowed */
2009 /* We want a bare copy of the address reg, without any pre-decrement
2010 adjustment, as gen_lea would provide. */
2014 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
2015 if (IS_NULL_QREG(tmp
)) {
2021 addr
= tcg_temp_new();
2022 tcg_gen_mov_i32(addr
, tmp
);
2023 incr
= tcg_const_i32(opsize_bytes(opsize
));
2026 /* memory to register */
2027 for (i
= 0; i
< 16; i
++) {
2028 if (mask
& (1 << i
)) {
2029 r
[i
] = gen_load(s
, opsize
, addr
, 1);
2030 tcg_gen_add_i32(addr
, addr
, incr
);
2033 for (i
= 0; i
< 16; i
++) {
2034 if (mask
& (1 << i
)) {
2035 tcg_gen_mov_i32(mreg(i
), r
[i
]);
2036 tcg_temp_free(r
[i
]);
2040 /* post-increment: movem (An)+,X */
2041 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2044 /* register to memory */
2046 /* pre-decrement: movem X,-(An) */
2047 for (i
= 15; i
>= 0; i
--) {
2048 if ((mask
<< i
) & 0x8000) {
2049 tcg_gen_sub_i32(addr
, addr
, incr
);
2050 if (reg0
+ 8 == i
&&
2051 m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
)) {
2052 /* M68020+: if the addressing register is the
2053 * register moved to memory, the value written
2054 * is the initial value decremented by the size of
2055 * the operation, regardless of how many actual
2056 * stores have been performed until this point.
2057 * M68000/M68010: the value is the initial value.
2059 tmp
= tcg_temp_new();
2060 tcg_gen_sub_i32(tmp
, cpu_aregs
[reg0
], incr
);
2061 gen_store(s
, opsize
, addr
, tmp
);
2064 gen_store(s
, opsize
, addr
, mreg(i
));
2068 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2070 for (i
= 0; i
< 16; i
++) {
2071 if (mask
& (1 << i
)) {
2072 gen_store(s
, opsize
, addr
, mreg(i
));
2073 tcg_gen_add_i32(addr
, addr
, incr
);
2079 tcg_temp_free(incr
);
2080 tcg_temp_free(addr
);
2083 DISAS_INSN(bitop_im
)
2093 if ((insn
& 0x38) != 0)
2097 op
= (insn
>> 6) & 3;
2099 bitnum
= read_im16(env
, s
);
2100 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2101 if (bitnum
& 0xfe00) {
2102 disas_undef(env
, s
, insn
);
2106 if (bitnum
& 0xff00) {
2107 disas_undef(env
, s
, insn
);
2112 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
2115 if (opsize
== OS_BYTE
)
2121 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
2124 tmp
= tcg_temp_new();
2127 tcg_gen_xori_i32(tmp
, src1
, mask
);
2130 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
2133 tcg_gen_ori_i32(tmp
, src1
, mask
);
2138 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
2143 DISAS_INSN(arith_im
)
2152 op
= (insn
>> 9) & 7;
2153 opsize
= insn_opsize(insn
);
2156 im
= tcg_const_i32((int8_t)read_im8(env
, s
));
2159 im
= tcg_const_i32((int16_t)read_im16(env
, s
));
2162 im
= tcg_const_i32(read_im32(env
, s
));
2167 SRC_EA(env
, src1
, opsize
, 1, (op
== 6) ? NULL
: &addr
);
2168 dest
= tcg_temp_new();
2171 tcg_gen_or_i32(dest
, src1
, im
);
2172 gen_logic_cc(s
, dest
, opsize
);
2175 tcg_gen_and_i32(dest
, src1
, im
);
2176 gen_logic_cc(s
, dest
, opsize
);
2179 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, src1
, im
);
2180 tcg_gen_sub_i32(dest
, src1
, im
);
2181 gen_update_cc_add(dest
, im
, opsize
);
2182 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2185 tcg_gen_add_i32(dest
, src1
, im
);
2186 gen_update_cc_add(dest
, im
, opsize
);
2187 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
2188 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2191 tcg_gen_xor_i32(dest
, src1
, im
);
2192 gen_logic_cc(s
, dest
, opsize
);
2195 gen_update_cc_cmp(s
, src1
, im
, opsize
);
2202 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2204 tcg_temp_free(dest
);
2216 switch ((insn
>> 9) & 3) {
2230 g_assert_not_reached();
2233 ext
= read_im16(env
, s
);
2235 /* cas Dc,Du,<EA> */
2237 addr
= gen_lea(env
, s
, insn
, opsize
);
2238 if (IS_NULL_QREG(addr
)) {
2243 cmp
= gen_extend(DREG(ext
, 0), opsize
, 1);
2245 /* if <EA> == Dc then
2247 * Dc = <EA> (because <EA> == Dc)
2252 load
= tcg_temp_new();
2253 tcg_gen_atomic_cmpxchg_i32(load
, addr
, cmp
, DREG(ext
, 6),
2255 /* update flags before setting cmp to load */
2256 gen_update_cc_cmp(s
, load
, cmp
, opsize
);
2257 gen_partset_reg(opsize
, DREG(ext
, 0), load
);
2259 tcg_temp_free(load
);
2261 switch (extract32(insn
, 3, 3)) {
2262 case 3: /* Indirect postincrement. */
2263 tcg_gen_addi_i32(AREG(insn
, 0), addr
, opsize_bytes(opsize
));
2265 case 4: /* Indirect predecrememnt. */
2266 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2273 uint16_t ext1
, ext2
;
2277 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2279 ext1
= read_im16(env
, s
);
2281 if (ext1
& 0x8000) {
2282 /* Address Register */
2283 addr1
= AREG(ext1
, 12);
2286 addr1
= DREG(ext1
, 12);
2289 ext2
= read_im16(env
, s
);
2290 if (ext2
& 0x8000) {
2291 /* Address Register */
2292 addr2
= AREG(ext2
, 12);
2295 addr2
= DREG(ext2
, 12);
2298 /* if (R1) == Dc1 && (R2) == Dc2 then
2306 regs
= tcg_const_i32(REG(ext2
, 6) |
2307 (REG(ext1
, 6) << 3) |
2308 (REG(ext2
, 0) << 6) |
2309 (REG(ext1
, 0) << 9));
2310 if (tb_cflags(s
->tb
) & CF_PARALLEL
) {
2311 gen_helper_exit_atomic(cpu_env
);
2313 gen_helper_cas2w(cpu_env
, regs
, addr1
, addr2
);
2315 tcg_temp_free(regs
);
2317 /* Note that cas2w also assigned to env->cc_op. */
2318 s
->cc_op
= CC_OP_CMPW
;
2319 s
->cc_op_synced
= 1;
2324 uint16_t ext1
, ext2
;
2325 TCGv addr1
, addr2
, regs
;
2327 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2329 ext1
= read_im16(env
, s
);
2331 if (ext1
& 0x8000) {
2332 /* Address Register */
2333 addr1
= AREG(ext1
, 12);
2336 addr1
= DREG(ext1
, 12);
2339 ext2
= read_im16(env
, s
);
2340 if (ext2
& 0x8000) {
2341 /* Address Register */
2342 addr2
= AREG(ext2
, 12);
2345 addr2
= DREG(ext2
, 12);
2348 /* if (R1) == Dc1 && (R2) == Dc2 then
2356 regs
= tcg_const_i32(REG(ext2
, 6) |
2357 (REG(ext1
, 6) << 3) |
2358 (REG(ext2
, 0) << 6) |
2359 (REG(ext1
, 0) << 9));
2360 if (tb_cflags(s
->tb
) & CF_PARALLEL
) {
2361 gen_helper_cas2l_parallel(cpu_env
, regs
, addr1
, addr2
);
2363 gen_helper_cas2l(cpu_env
, regs
, addr1
, addr2
);
2365 tcg_temp_free(regs
);
2367 /* Note that cas2l also assigned to env->cc_op. */
2368 s
->cc_op
= CC_OP_CMPL
;
2369 s
->cc_op_synced
= 1;
2376 reg
= DREG(insn
, 0);
2377 tcg_gen_bswap32_i32(reg
, reg
);
2387 switch (insn
>> 12) {
2388 case 1: /* move.b */
2391 case 2: /* move.l */
2394 case 3: /* move.w */
2400 SRC_EA(env
, src
, opsize
, 1, NULL
);
2401 op
= (insn
>> 6) & 7;
2404 /* The value will already have been sign extended. */
2405 dest
= AREG(insn
, 9);
2406 tcg_gen_mov_i32(dest
, src
);
2410 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
2411 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
2412 /* This will be correct because loads sign extend. */
2413 gen_logic_cc(s
, src
, opsize
);
2424 opsize
= insn_opsize(insn
);
2425 SRC_EA(env
, src
, opsize
, 1, &addr
);
2427 gen_flush_flags(s
); /* compute old Z */
2429 /* Perform substract with borrow.
2430 * (X, N) = -(src + X);
2433 z
= tcg_const_i32(0);
2434 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, z
, QREG_CC_X
, z
);
2435 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, z
, z
, QREG_CC_N
, QREG_CC_X
);
2437 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2439 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2441 /* Compute signed-overflow for negation. The normal formula for
2442 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2443 * this simplies to res & src.
2446 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_N
, src
);
2448 /* Copy the rest of the results into place. */
2449 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2450 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2452 set_cc_op(s
, CC_OP_FLAGS
);
2454 /* result is in QREG_CC_N */
2456 DEST_EA(env
, insn
, opsize
, QREG_CC_N
, &addr
);
2464 reg
= AREG(insn
, 9);
2465 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2466 if (IS_NULL_QREG(tmp
)) {
2470 tcg_gen_mov_i32(reg
, tmp
);
2478 zero
= tcg_const_i32(0);
2480 opsize
= insn_opsize(insn
);
2481 DEST_EA(env
, insn
, opsize
, zero
, NULL
);
2482 gen_logic_cc(s
, zero
, opsize
);
2483 tcg_temp_free(zero
);
2486 static TCGv
gen_get_ccr(DisasContext
*s
)
2492 dest
= tcg_temp_new();
2493 gen_helper_get_ccr(dest
, cpu_env
);
2497 DISAS_INSN(move_from_ccr
)
2501 ccr
= gen_get_ccr(s
);
2502 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
2512 opsize
= insn_opsize(insn
);
2513 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2514 dest
= tcg_temp_new();
2515 tcg_gen_neg_i32(dest
, src1
);
2516 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2517 gen_update_cc_add(dest
, src1
, opsize
);
2518 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, dest
, 0);
2519 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2520 tcg_temp_free(dest
);
2523 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
2526 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
2527 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
2528 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
2529 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
2530 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
2532 gen_helper_set_sr(cpu_env
, tcg_const_i32(val
));
2534 set_cc_op(s
, CC_OP_FLAGS
);
2537 static void gen_set_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
2540 if ((insn
& 0x38) == 0) {
2542 gen_helper_set_ccr(cpu_env
, DREG(insn
, 0));
2544 gen_helper_set_sr(cpu_env
, DREG(insn
, 0));
2546 set_cc_op(s
, CC_OP_FLAGS
);
2547 } else if ((insn
& 0x3f) == 0x3c) {
2549 val
= read_im16(env
, s
);
2550 gen_set_sr_im(s
, val
, ccr_only
);
2552 disas_undef(env
, s
, insn
);
2557 DISAS_INSN(move_to_ccr
)
2559 gen_set_sr(env
, s
, insn
, 1);
2569 opsize
= insn_opsize(insn
);
2570 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2571 dest
= tcg_temp_new();
2572 tcg_gen_not_i32(dest
, src1
);
2573 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2574 gen_logic_cc(s
, dest
, opsize
);
2583 src1
= tcg_temp_new();
2584 src2
= tcg_temp_new();
2585 reg
= DREG(insn
, 0);
2586 tcg_gen_shli_i32(src1
, reg
, 16);
2587 tcg_gen_shri_i32(src2
, reg
, 16);
2588 tcg_gen_or_i32(reg
, src1
, src2
);
2589 tcg_temp_free(src2
);
2590 tcg_temp_free(src1
);
2591 gen_logic_cc(s
, reg
, OS_LONG
);
2596 gen_exception(s
, s
->pc
- 2, EXCP_DEBUG
);
2603 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2604 if (IS_NULL_QREG(tmp
)) {
2617 reg
= DREG(insn
, 0);
2618 op
= (insn
>> 6) & 7;
2619 tmp
= tcg_temp_new();
2621 tcg_gen_ext16s_i32(tmp
, reg
);
2623 tcg_gen_ext8s_i32(tmp
, reg
);
2625 gen_partset_reg(OS_WORD
, reg
, tmp
);
2627 tcg_gen_mov_i32(reg
, tmp
);
2628 gen_logic_cc(s
, tmp
, OS_LONG
);
2637 opsize
= insn_opsize(insn
);
2638 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
2639 gen_logic_cc(s
, tmp
, opsize
);
2644 /* Implemented as a NOP. */
2649 gen_exception(s
, s
->pc
- 2, EXCP_ILLEGAL
);
2652 /* ??? This should be atomic. */
2659 dest
= tcg_temp_new();
2660 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
2661 gen_logic_cc(s
, src1
, OS_BYTE
);
2662 tcg_gen_ori_i32(dest
, src1
, 0x80);
2663 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
2664 tcg_temp_free(dest
);
2673 ext
= read_im16(env
, s
);
2678 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
2679 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
2683 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2686 tcg_gen_muls2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2688 tcg_gen_mulu2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2690 /* if Dl == Dh, 68040 returns low word */
2691 tcg_gen_mov_i32(DREG(ext
, 0), QREG_CC_N
);
2692 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_Z
);
2693 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
);
2695 tcg_gen_movi_i32(QREG_CC_V
, 0);
2696 tcg_gen_movi_i32(QREG_CC_C
, 0);
2698 set_cc_op(s
, CC_OP_FLAGS
);
2701 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2702 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2703 tcg_gen_movi_i32(QREG_CC_C
, 0);
2705 tcg_gen_muls2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2706 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2707 tcg_gen_sari_i32(QREG_CC_Z
, QREG_CC_N
, 31);
2708 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_Z
);
2710 tcg_gen_mulu2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2711 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2712 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_C
);
2714 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
2715 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_N
);
2717 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
2719 set_cc_op(s
, CC_OP_FLAGS
);
2721 /* The upper 32 bits of the product are discarded, so
2722 muls.l and mulu.l are functionally equivalent. */
2723 tcg_gen_mul_i32(DREG(ext
, 12), src1
, DREG(ext
, 12));
2724 gen_logic_cc(s
, DREG(ext
, 12), OS_LONG
);
2728 static void gen_link(DisasContext
*s
, uint16_t insn
, int32_t offset
)
2733 reg
= AREG(insn
, 0);
2734 tmp
= tcg_temp_new();
2735 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2736 gen_store(s
, OS_LONG
, tmp
, reg
);
2737 if ((insn
& 7) != 7) {
2738 tcg_gen_mov_i32(reg
, tmp
);
2740 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
2748 offset
= read_im16(env
, s
);
2749 gen_link(s
, insn
, offset
);
2756 offset
= read_im32(env
, s
);
2757 gen_link(s
, insn
, offset
);
2766 src
= tcg_temp_new();
2767 reg
= AREG(insn
, 0);
2768 tcg_gen_mov_i32(src
, reg
);
2769 tmp
= gen_load(s
, OS_LONG
, src
, 0);
2770 tcg_gen_mov_i32(reg
, tmp
);
2771 tcg_gen_addi_i32(QREG_SP
, src
, 4);
2782 int16_t offset
= read_im16(env
, s
);
2784 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
2785 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, offset
+ 4);
2793 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
2794 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
2802 /* Load the target address first to ensure correct exception
2804 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2805 if (IS_NULL_QREG(tmp
)) {
2809 if ((insn
& 0x40) == 0) {
2811 gen_push(s
, tcg_const_i32(s
->pc
));
2825 if ((insn
& 070) == 010) {
2826 /* Operation on address register is always long. */
2829 opsize
= insn_opsize(insn
);
2831 SRC_EA(env
, src
, opsize
, 1, &addr
);
2832 imm
= (insn
>> 9) & 7;
2836 val
= tcg_const_i32(imm
);
2837 dest
= tcg_temp_new();
2838 tcg_gen_mov_i32(dest
, src
);
2839 if ((insn
& 0x38) == 0x08) {
2840 /* Don't update condition codes if the destination is an
2841 address register. */
2842 if (insn
& 0x0100) {
2843 tcg_gen_sub_i32(dest
, dest
, val
);
2845 tcg_gen_add_i32(dest
, dest
, val
);
2848 if (insn
& 0x0100) {
2849 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
2850 tcg_gen_sub_i32(dest
, dest
, val
);
2851 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2853 tcg_gen_add_i32(dest
, dest
, val
);
2854 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
2855 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2857 gen_update_cc_add(dest
, val
, opsize
);
2860 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2861 tcg_temp_free(dest
);
2867 case 2: /* One extension word. */
2870 case 3: /* Two extension words. */
2873 case 4: /* No extension words. */
2876 disas_undef(env
, s
, insn
);
2888 op
= (insn
>> 8) & 0xf;
2889 offset
= (int8_t)insn
;
2891 offset
= (int16_t)read_im16(env
, s
);
2892 } else if (offset
== -1) {
2893 offset
= read_im32(env
, s
);
2897 gen_push(s
, tcg_const_i32(s
->pc
));
2901 l1
= gen_new_label();
2902 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
2903 gen_jmp_tb(s
, 1, base
+ offset
);
2905 gen_jmp_tb(s
, 0, s
->pc
);
2907 /* Unconditional branch. */
2908 gen_jmp_tb(s
, 0, base
+ offset
);
2914 tcg_gen_movi_i32(DREG(insn
, 9), (int8_t)insn
);
2915 gen_logic_cc(s
, DREG(insn
, 9), OS_LONG
);
2928 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
2929 reg
= DREG(insn
, 9);
2930 tcg_gen_mov_i32(reg
, src
);
2931 gen_logic_cc(s
, src
, opsize
);
2942 opsize
= insn_opsize(insn
);
2943 reg
= gen_extend(DREG(insn
, 9), opsize
, 0);
2944 dest
= tcg_temp_new();
2946 SRC_EA(env
, src
, opsize
, 0, &addr
);
2947 tcg_gen_or_i32(dest
, src
, reg
);
2948 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2950 SRC_EA(env
, src
, opsize
, 0, NULL
);
2951 tcg_gen_or_i32(dest
, src
, reg
);
2952 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
2954 gen_logic_cc(s
, dest
, opsize
);
2955 tcg_temp_free(dest
);
2963 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
2964 reg
= AREG(insn
, 9);
2965 tcg_gen_sub_i32(reg
, reg
, src
);
2968 static inline void gen_subx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
2972 gen_flush_flags(s
); /* compute old Z */
2974 /* Perform substract with borrow.
2975 * (X, N) = dest - (src + X);
2978 tmp
= tcg_const_i32(0);
2979 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, tmp
, QREG_CC_X
, tmp
);
2980 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, dest
, tmp
, QREG_CC_N
, QREG_CC_X
);
2981 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2982 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2984 /* Compute signed-overflow for substract. */
2986 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, dest
);
2987 tcg_gen_xor_i32(tmp
, dest
, src
);
2988 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
2991 /* Copy the rest of the results into place. */
2992 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2993 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2995 set_cc_op(s
, CC_OP_FLAGS
);
2997 /* result is in QREG_CC_N */
3000 DISAS_INSN(subx_reg
)
3006 opsize
= insn_opsize(insn
);
3008 src
= gen_extend(DREG(insn
, 0), opsize
, 1);
3009 dest
= gen_extend(DREG(insn
, 9), opsize
, 1);
3011 gen_subx(s
, src
, dest
, opsize
);
3013 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3016 DISAS_INSN(subx_mem
)
3024 opsize
= insn_opsize(insn
);
3026 addr_src
= AREG(insn
, 0);
3027 tcg_gen_subi_i32(addr_src
, addr_src
, opsize
);
3028 src
= gen_load(s
, opsize
, addr_src
, 1);
3030 addr_dest
= AREG(insn
, 9);
3031 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize
);
3032 dest
= gen_load(s
, opsize
, addr_dest
, 1);
3034 gen_subx(s
, src
, dest
, opsize
);
3036 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
);
3044 val
= (insn
>> 9) & 7;
3047 src
= tcg_const_i32(val
);
3048 gen_logic_cc(s
, src
, OS_LONG
);
3049 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
3059 opsize
= insn_opsize(insn
);
3060 SRC_EA(env
, src
, opsize
, 1, NULL
);
3061 reg
= gen_extend(DREG(insn
, 9), opsize
, 1);
3062 gen_update_cc_cmp(s
, reg
, src
, opsize
);
3076 SRC_EA(env
, src
, opsize
, 1, NULL
);
3077 reg
= AREG(insn
, 9);
3078 gen_update_cc_cmp(s
, reg
, src
, OS_LONG
);
3083 int opsize
= insn_opsize(insn
);
3086 /* Post-increment load (mode 3) from Ay. */
3087 src
= gen_ea_mode(env
, s
, 3, REG(insn
, 0), opsize
,
3088 NULL_QREG
, NULL
, EA_LOADS
);
3089 /* Post-increment load (mode 3) from Ax. */
3090 dst
= gen_ea_mode(env
, s
, 3, REG(insn
, 9), opsize
,
3091 NULL_QREG
, NULL
, EA_LOADS
);
3093 gen_update_cc_cmp(s
, dst
, src
, opsize
);
3103 opsize
= insn_opsize(insn
);
3105 SRC_EA(env
, src
, opsize
, 0, &addr
);
3106 dest
= tcg_temp_new();
3107 tcg_gen_xor_i32(dest
, src
, DREG(insn
, 9));
3108 gen_logic_cc(s
, dest
, opsize
);
3109 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3110 tcg_temp_free(dest
);
3113 static void do_exg(TCGv reg1
, TCGv reg2
)
3115 TCGv temp
= tcg_temp_new();
3116 tcg_gen_mov_i32(temp
, reg1
);
3117 tcg_gen_mov_i32(reg1
, reg2
);
3118 tcg_gen_mov_i32(reg2
, temp
);
3119 tcg_temp_free(temp
);
3124 /* exchange Dx and Dy */
3125 do_exg(DREG(insn
, 9), DREG(insn
, 0));
3130 /* exchange Ax and Ay */
3131 do_exg(AREG(insn
, 9), AREG(insn
, 0));
3136 /* exchange Dx and Ay */
3137 do_exg(DREG(insn
, 9), AREG(insn
, 0));
3148 dest
= tcg_temp_new();
3150 opsize
= insn_opsize(insn
);
3151 reg
= DREG(insn
, 9);
3153 SRC_EA(env
, src
, opsize
, 0, &addr
);
3154 tcg_gen_and_i32(dest
, src
, reg
);
3155 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3157 SRC_EA(env
, src
, opsize
, 0, NULL
);
3158 tcg_gen_and_i32(dest
, src
, reg
);
3159 gen_partset_reg(opsize
, reg
, dest
);
3161 gen_logic_cc(s
, dest
, opsize
);
3162 tcg_temp_free(dest
);
3170 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3171 reg
= AREG(insn
, 9);
3172 tcg_gen_add_i32(reg
, reg
, src
);
3175 static inline void gen_addx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3179 gen_flush_flags(s
); /* compute old Z */
3181 /* Perform addition with carry.
3182 * (X, N) = src + dest + X;
3185 tmp
= tcg_const_i32(0);
3186 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_X
, tmp
, dest
, tmp
);
3187 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_N
, QREG_CC_X
, src
, tmp
);
3188 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3190 /* Compute signed-overflow for addition. */
3192 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3193 tcg_gen_xor_i32(tmp
, dest
, src
);
3194 tcg_gen_andc_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3197 /* Copy the rest of the results into place. */
3198 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3199 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3201 set_cc_op(s
, CC_OP_FLAGS
);
3203 /* result is in QREG_CC_N */
3206 DISAS_INSN(addx_reg
)
3212 opsize
= insn_opsize(insn
);
3214 dest
= gen_extend(DREG(insn
, 9), opsize
, 1);
3215 src
= gen_extend(DREG(insn
, 0), opsize
, 1);
3217 gen_addx(s
, src
, dest
, opsize
);
3219 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3222 DISAS_INSN(addx_mem
)
3230 opsize
= insn_opsize(insn
);
3232 addr_src
= AREG(insn
, 0);
3233 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3234 src
= gen_load(s
, opsize
, addr_src
, 1);
3236 addr_dest
= AREG(insn
, 9);
3237 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3238 dest
= gen_load(s
, opsize
, addr_dest
, 1);
3240 gen_addx(s
, src
, dest
, opsize
);
3242 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
);
3245 static inline void shift_im(DisasContext
*s
, uint16_t insn
, int opsize
)
3247 int count
= (insn
>> 9) & 7;
3248 int logical
= insn
& 8;
3249 int left
= insn
& 0x100;
3250 int bits
= opsize_bytes(opsize
) * 8;
3251 TCGv reg
= gen_extend(DREG(insn
, 0), opsize
, !logical
);
3257 tcg_gen_movi_i32(QREG_CC_V
, 0);
3259 tcg_gen_shri_i32(QREG_CC_C
, reg
, bits
- count
);
3260 tcg_gen_shli_i32(QREG_CC_N
, reg
, count
);
3262 /* Note that ColdFire always clears V (done above),
3263 while M68000 sets if the most significant bit is changed at
3264 any time during the shift operation */
3265 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3266 /* if shift count >= bits, V is (reg != 0) */
3267 if (count
>= bits
) {
3268 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, reg
, QREG_CC_V
);
3270 TCGv t0
= tcg_temp_new();
3271 tcg_gen_sari_i32(QREG_CC_V
, reg
, bits
- 1);
3272 tcg_gen_sari_i32(t0
, reg
, bits
- count
- 1);
3273 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, t0
);
3276 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3279 tcg_gen_shri_i32(QREG_CC_C
, reg
, count
- 1);
3281 tcg_gen_shri_i32(QREG_CC_N
, reg
, count
);
3283 tcg_gen_sari_i32(QREG_CC_N
, reg
, count
);
3287 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3288 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3289 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3290 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3292 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3293 set_cc_op(s
, CC_OP_FLAGS
);
3296 static inline void shift_reg(DisasContext
*s
, uint16_t insn
, int opsize
)
3298 int logical
= insn
& 8;
3299 int left
= insn
& 0x100;
3300 int bits
= opsize_bytes(opsize
) * 8;
3301 TCGv reg
= gen_extend(DREG(insn
, 0), opsize
, !logical
);
3305 t64
= tcg_temp_new_i64();
3306 s64
= tcg_temp_new_i64();
3307 s32
= tcg_temp_new();
3309 /* Note that m68k truncates the shift count modulo 64, not 32.
3310 In addition, a 64-bit shift makes it easy to find "the last
3311 bit shifted out", for the carry flag. */
3312 tcg_gen_andi_i32(s32
, DREG(insn
, 9), 63);
3313 tcg_gen_extu_i32_i64(s64
, s32
);
3314 tcg_gen_extu_i32_i64(t64
, reg
);
3316 /* Optimistically set V=0. Also used as a zero source below. */
3317 tcg_gen_movi_i32(QREG_CC_V
, 0);
3319 tcg_gen_shl_i64(t64
, t64
, s64
);
3321 if (opsize
== OS_LONG
) {
3322 tcg_gen_extr_i64_i32(QREG_CC_N
, QREG_CC_C
, t64
);
3323 /* Note that C=0 if shift count is 0, and we get that for free. */
3325 TCGv zero
= tcg_const_i32(0);
3326 tcg_gen_extrl_i64_i32(QREG_CC_N
, t64
);
3327 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_N
, bits
);
3328 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3329 s32
, zero
, zero
, QREG_CC_C
);
3330 tcg_temp_free(zero
);
3332 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3334 /* X = C, but only if the shift count was non-zero. */
3335 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3336 QREG_CC_C
, QREG_CC_X
);
3338 /* M68000 sets V if the most significant bit is changed at
3339 * any time during the shift operation. Do this via creating
3340 * an extension of the sign bit, comparing, and discarding
3341 * the bits below the sign bit. I.e.
3342 * int64_t s = (intN_t)reg;
3343 * int64_t t = (int64_t)(intN_t)reg << count;
3344 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3346 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3347 TCGv_i64 tt
= tcg_const_i64(32);
3348 /* if shift is greater than 32, use 32 */
3349 tcg_gen_movcond_i64(TCG_COND_GT
, s64
, s64
, tt
, tt
, s64
);
3350 tcg_temp_free_i64(tt
);
3351 /* Sign extend the input to 64 bits; re-do the shift. */
3352 tcg_gen_ext_i32_i64(t64
, reg
);
3353 tcg_gen_shl_i64(s64
, t64
, s64
);
3354 /* Clear all bits that are unchanged. */
3355 tcg_gen_xor_i64(t64
, t64
, s64
);
3356 /* Ignore the bits below the sign bit. */
3357 tcg_gen_andi_i64(t64
, t64
, -1ULL << (bits
- 1));
3358 /* If any bits remain set, we have overflow. */
3359 tcg_gen_setcondi_i64(TCG_COND_NE
, t64
, t64
, 0);
3360 tcg_gen_extrl_i64_i32(QREG_CC_V
, t64
);
3361 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3364 tcg_gen_shli_i64(t64
, t64
, 32);
3366 tcg_gen_shr_i64(t64
, t64
, s64
);
3368 tcg_gen_sar_i64(t64
, t64
, s64
);
3370 tcg_gen_extr_i64_i32(QREG_CC_C
, QREG_CC_N
, t64
);
3372 /* Note that C=0 if shift count is 0, and we get that for free. */
3373 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_C
, 31);
3375 /* X = C, but only if the shift count was non-zero. */
3376 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3377 QREG_CC_C
, QREG_CC_X
);
3379 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3380 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3383 tcg_temp_free_i64(s64
);
3384 tcg_temp_free_i64(t64
);
3386 /* Write back the result. */
3387 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3388 set_cc_op(s
, CC_OP_FLAGS
);
3391 DISAS_INSN(shift8_im
)
3393 shift_im(s
, insn
, OS_BYTE
);
3396 DISAS_INSN(shift16_im
)
3398 shift_im(s
, insn
, OS_WORD
);
3401 DISAS_INSN(shift_im
)
3403 shift_im(s
, insn
, OS_LONG
);
3406 DISAS_INSN(shift8_reg
)
3408 shift_reg(s
, insn
, OS_BYTE
);
3411 DISAS_INSN(shift16_reg
)
3413 shift_reg(s
, insn
, OS_WORD
);
3416 DISAS_INSN(shift_reg
)
3418 shift_reg(s
, insn
, OS_LONG
);
3421 DISAS_INSN(shift_mem
)
3423 int logical
= insn
& 8;
3424 int left
= insn
& 0x100;
3428 SRC_EA(env
, src
, OS_WORD
, !logical
, &addr
);
3429 tcg_gen_movi_i32(QREG_CC_V
, 0);
3431 tcg_gen_shri_i32(QREG_CC_C
, src
, 15);
3432 tcg_gen_shli_i32(QREG_CC_N
, src
, 1);
3434 /* Note that ColdFire always clears V,
3435 while M68000 sets if the most significant bit is changed at
3436 any time during the shift operation */
3437 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3438 src
= gen_extend(src
, OS_WORD
, 1);
3439 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3442 tcg_gen_mov_i32(QREG_CC_C
, src
);
3444 tcg_gen_shri_i32(QREG_CC_N
, src
, 1);
3446 tcg_gen_sari_i32(QREG_CC_N
, src
, 1);
3450 gen_ext(QREG_CC_N
, QREG_CC_N
, OS_WORD
, 1);
3451 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3452 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3453 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3455 DEST_EA(env
, insn
, OS_WORD
, QREG_CC_N
, &addr
);
3456 set_cc_op(s
, CC_OP_FLAGS
);
3459 static void rotate(TCGv reg
, TCGv shift
, int left
, int size
)
3463 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3464 tcg_gen_ext8u_i32(reg
, reg
);
3465 tcg_gen_muli_i32(reg
, reg
, 0x01010101);
3468 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3469 tcg_gen_deposit_i32(reg
, reg
, reg
, 16, 16);
3474 tcg_gen_rotl_i32(reg
, reg
, shift
);
3476 tcg_gen_rotr_i32(reg
, reg
, shift
);
3484 tcg_gen_ext8s_i32(reg
, reg
);
3487 tcg_gen_ext16s_i32(reg
, reg
);
3493 /* QREG_CC_X is not affected */
3495 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3496 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3499 tcg_gen_andi_i32(QREG_CC_C
, reg
, 1);
3501 tcg_gen_shri_i32(QREG_CC_C
, reg
, 31);
3504 tcg_gen_movi_i32(QREG_CC_V
, 0); /* always cleared */
3507 static void rotate_x_flags(TCGv reg
, TCGv X
, int size
)
3511 tcg_gen_ext8s_i32(reg
, reg
);
3514 tcg_gen_ext16s_i32(reg
, reg
);
3519 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3520 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3521 tcg_gen_mov_i32(QREG_CC_X
, X
);
3522 tcg_gen_mov_i32(QREG_CC_C
, X
);
3523 tcg_gen_movi_i32(QREG_CC_V
, 0);
3526 /* Result of rotate_x() is valid if 0 <= shift <= size */
3527 static TCGv
rotate_x(TCGv reg
, TCGv shift
, int left
, int size
)
3529 TCGv X
, shl
, shr
, shx
, sz
, zero
;
3531 sz
= tcg_const_i32(size
);
3533 shr
= tcg_temp_new();
3534 shl
= tcg_temp_new();
3535 shx
= tcg_temp_new();
3537 tcg_gen_mov_i32(shl
, shift
); /* shl = shift */
3538 tcg_gen_movi_i32(shr
, size
+ 1);
3539 tcg_gen_sub_i32(shr
, shr
, shift
); /* shr = size + 1 - shift */
3540 tcg_gen_subi_i32(shx
, shift
, 1); /* shx = shift - 1 */
3541 /* shx = shx < 0 ? size : shx; */
3542 zero
= tcg_const_i32(0);
3543 tcg_gen_movcond_i32(TCG_COND_LT
, shx
, shx
, zero
, sz
, shx
);
3544 tcg_temp_free(zero
);
3546 tcg_gen_mov_i32(shr
, shift
); /* shr = shift */
3547 tcg_gen_movi_i32(shl
, size
+ 1);
3548 tcg_gen_sub_i32(shl
, shl
, shift
); /* shl = size + 1 - shift */
3549 tcg_gen_sub_i32(shx
, sz
, shift
); /* shx = size - shift */
3552 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3554 tcg_gen_shl_i32(shl
, reg
, shl
);
3555 tcg_gen_shr_i32(shr
, reg
, shr
);
3556 tcg_gen_or_i32(reg
, shl
, shr
);
3559 tcg_gen_shl_i32(shx
, QREG_CC_X
, shx
);
3560 tcg_gen_or_i32(reg
, reg
, shx
);
3563 /* X = (reg >> size) & 1 */
3566 tcg_gen_shr_i32(X
, reg
, sz
);
3567 tcg_gen_andi_i32(X
, X
, 1);
3573 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3574 static TCGv
rotate32_x(TCGv reg
, TCGv shift
, int left
)
3576 TCGv_i64 t0
, shift64
;
3577 TCGv X
, lo
, hi
, zero
;
3579 shift64
= tcg_temp_new_i64();
3580 tcg_gen_extu_i32_i64(shift64
, shift
);
3582 t0
= tcg_temp_new_i64();
3585 lo
= tcg_temp_new();
3586 hi
= tcg_temp_new();
3589 /* create [reg:X:..] */
3591 tcg_gen_shli_i32(lo
, QREG_CC_X
, 31);
3592 tcg_gen_concat_i32_i64(t0
, lo
, reg
);
3596 tcg_gen_rotl_i64(t0
, t0
, shift64
);
3597 tcg_temp_free_i64(shift64
);
3599 /* result is [reg:..:reg:X] */
3601 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3602 tcg_gen_andi_i32(X
, lo
, 1);
3604 tcg_gen_shri_i32(lo
, lo
, 1);
3606 /* create [..:X:reg] */
3608 tcg_gen_concat_i32_i64(t0
, reg
, QREG_CC_X
);
3610 tcg_gen_rotr_i64(t0
, t0
, shift64
);
3611 tcg_temp_free_i64(shift64
);
3613 /* result is value: [X:reg:..:reg] */
3615 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3619 tcg_gen_shri_i32(X
, hi
, 31);
3621 /* extract result */
3623 tcg_gen_shli_i32(hi
, hi
, 1);
3625 tcg_temp_free_i64(t0
);
3626 tcg_gen_or_i32(lo
, lo
, hi
);
3629 /* if shift == 0, register and X are not affected */
3631 zero
= tcg_const_i32(0);
3632 tcg_gen_movcond_i32(TCG_COND_EQ
, X
, shift
, zero
, QREG_CC_X
, X
);
3633 tcg_gen_movcond_i32(TCG_COND_EQ
, reg
, shift
, zero
, reg
, lo
);
3634 tcg_temp_free(zero
);
3640 DISAS_INSN(rotate_im
)
3644 int left
= (insn
& 0x100);
3646 tmp
= (insn
>> 9) & 7;
3651 shift
= tcg_const_i32(tmp
);
3653 rotate(DREG(insn
, 0), shift
, left
, 32);
3655 TCGv X
= rotate32_x(DREG(insn
, 0), shift
, left
);
3656 rotate_x_flags(DREG(insn
, 0), X
, 32);
3659 tcg_temp_free(shift
);
3661 set_cc_op(s
, CC_OP_FLAGS
);
3664 DISAS_INSN(rotate8_im
)
3666 int left
= (insn
& 0x100);
3671 reg
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
3673 tmp
= (insn
>> 9) & 7;
3678 shift
= tcg_const_i32(tmp
);
3680 rotate(reg
, shift
, left
, 8);
3682 TCGv X
= rotate_x(reg
, shift
, left
, 8);
3683 rotate_x_flags(reg
, X
, 8);
3686 tcg_temp_free(shift
);
3687 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3688 set_cc_op(s
, CC_OP_FLAGS
);
3691 DISAS_INSN(rotate16_im
)
3693 int left
= (insn
& 0x100);
3698 reg
= gen_extend(DREG(insn
, 0), OS_WORD
, 0);
3699 tmp
= (insn
>> 9) & 7;
3704 shift
= tcg_const_i32(tmp
);
3706 rotate(reg
, shift
, left
, 16);
3708 TCGv X
= rotate_x(reg
, shift
, left
, 16);
3709 rotate_x_flags(reg
, X
, 16);
3712 tcg_temp_free(shift
);
3713 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3714 set_cc_op(s
, CC_OP_FLAGS
);
3717 DISAS_INSN(rotate_reg
)
3722 int left
= (insn
& 0x100);
3724 reg
= DREG(insn
, 0);
3725 src
= DREG(insn
, 9);
3726 /* shift in [0..63] */
3727 t0
= tcg_temp_new();
3728 tcg_gen_andi_i32(t0
, src
, 63);
3729 t1
= tcg_temp_new_i32();
3731 tcg_gen_andi_i32(t1
, src
, 31);
3732 rotate(reg
, t1
, left
, 32);
3733 /* if shift == 0, clear C */
3734 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3735 t0
, QREG_CC_V
/* 0 */,
3736 QREG_CC_V
/* 0 */, QREG_CC_C
);
3740 tcg_gen_movi_i32(t1
, 33);
3741 tcg_gen_remu_i32(t1
, t0
, t1
);
3742 X
= rotate32_x(DREG(insn
, 0), t1
, left
);
3743 rotate_x_flags(DREG(insn
, 0), X
, 32);
3748 set_cc_op(s
, CC_OP_FLAGS
);
3751 DISAS_INSN(rotate8_reg
)
3756 int left
= (insn
& 0x100);
3758 reg
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
3759 src
= DREG(insn
, 9);
3760 /* shift in [0..63] */
3761 t0
= tcg_temp_new_i32();
3762 tcg_gen_andi_i32(t0
, src
, 63);
3763 t1
= tcg_temp_new_i32();
3765 tcg_gen_andi_i32(t1
, src
, 7);
3766 rotate(reg
, t1
, left
, 8);
3767 /* if shift == 0, clear C */
3768 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3769 t0
, QREG_CC_V
/* 0 */,
3770 QREG_CC_V
/* 0 */, QREG_CC_C
);
3774 tcg_gen_movi_i32(t1
, 9);
3775 tcg_gen_remu_i32(t1
, t0
, t1
);
3776 X
= rotate_x(reg
, t1
, left
, 8);
3777 rotate_x_flags(reg
, X
, 8);
3782 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3783 set_cc_op(s
, CC_OP_FLAGS
);
3786 DISAS_INSN(rotate16_reg
)
3791 int left
= (insn
& 0x100);
3793 reg
= gen_extend(DREG(insn
, 0), OS_WORD
, 0);
3794 src
= DREG(insn
, 9);
3795 /* shift in [0..63] */
3796 t0
= tcg_temp_new_i32();
3797 tcg_gen_andi_i32(t0
, src
, 63);
3798 t1
= tcg_temp_new_i32();
3800 tcg_gen_andi_i32(t1
, src
, 15);
3801 rotate(reg
, t1
, left
, 16);
3802 /* if shift == 0, clear C */
3803 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3804 t0
, QREG_CC_V
/* 0 */,
3805 QREG_CC_V
/* 0 */, QREG_CC_C
);
3809 tcg_gen_movi_i32(t1
, 17);
3810 tcg_gen_remu_i32(t1
, t0
, t1
);
3811 X
= rotate_x(reg
, t1
, left
, 16);
3812 rotate_x_flags(reg
, X
, 16);
3817 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3818 set_cc_op(s
, CC_OP_FLAGS
);
3821 DISAS_INSN(rotate_mem
)
3826 int left
= (insn
& 0x100);
3828 SRC_EA(env
, src
, OS_WORD
, 0, &addr
);
3830 shift
= tcg_const_i32(1);
3831 if (insn
& 0x0200) {
3832 rotate(src
, shift
, left
, 16);
3834 TCGv X
= rotate_x(src
, shift
, left
, 16);
3835 rotate_x_flags(src
, X
, 16);
3838 tcg_temp_free(shift
);
3839 DEST_EA(env
, insn
, OS_WORD
, src
, &addr
);
3840 set_cc_op(s
, CC_OP_FLAGS
);
3843 DISAS_INSN(bfext_reg
)
3845 int ext
= read_im16(env
, s
);
3846 int is_sign
= insn
& 0x200;
3847 TCGv src
= DREG(insn
, 0);
3848 TCGv dst
= DREG(ext
, 12);
3849 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
3850 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
3851 int pos
= 32 - ofs
- len
; /* little bit-endian */
3852 TCGv tmp
= tcg_temp_new();
3855 /* In general, we're going to rotate the field so that it's at the
3856 top of the word and then right-shift by the compliment of the
3857 width to extend the field. */
3859 /* Variable width. */
3861 /* Variable offset. */
3862 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
3863 tcg_gen_rotl_i32(tmp
, src
, tmp
);
3865 tcg_gen_rotli_i32(tmp
, src
, ofs
);
3868 shift
= tcg_temp_new();
3869 tcg_gen_neg_i32(shift
, DREG(ext
, 0));
3870 tcg_gen_andi_i32(shift
, shift
, 31);
3871 tcg_gen_sar_i32(QREG_CC_N
, tmp
, shift
);
3873 tcg_gen_mov_i32(dst
, QREG_CC_N
);
3875 tcg_gen_shr_i32(dst
, tmp
, shift
);
3877 tcg_temp_free(shift
);
3879 /* Immediate width. */
3881 /* Variable offset */
3882 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
3883 tcg_gen_rotl_i32(tmp
, src
, tmp
);
3887 /* Immediate offset. If the field doesn't wrap around the
3888 end of the word, rely on (s)extract completely. */
3890 tcg_gen_rotli_i32(tmp
, src
, ofs
);
3896 tcg_gen_sextract_i32(QREG_CC_N
, src
, pos
, len
);
3898 tcg_gen_mov_i32(dst
, QREG_CC_N
);
3900 tcg_gen_extract_i32(dst
, src
, pos
, len
);
3905 set_cc_op(s
, CC_OP_LOGIC
);
3908 DISAS_INSN(bfext_mem
)
3910 int ext
= read_im16(env
, s
);
3911 int is_sign
= insn
& 0x200;
3912 TCGv dest
= DREG(ext
, 12);
3913 TCGv addr
, len
, ofs
;
3915 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
3916 if (IS_NULL_QREG(addr
)) {
3924 len
= tcg_const_i32(extract32(ext
, 0, 5));
3929 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
3933 gen_helper_bfexts_mem(dest
, cpu_env
, addr
, ofs
, len
);
3934 tcg_gen_mov_i32(QREG_CC_N
, dest
);
3936 TCGv_i64 tmp
= tcg_temp_new_i64();
3937 gen_helper_bfextu_mem(tmp
, cpu_env
, addr
, ofs
, len
);
3938 tcg_gen_extr_i64_i32(dest
, QREG_CC_N
, tmp
);
3939 tcg_temp_free_i64(tmp
);
3941 set_cc_op(s
, CC_OP_LOGIC
);
3943 if (!(ext
& 0x20)) {
3946 if (!(ext
& 0x800)) {
3951 DISAS_INSN(bfop_reg
)
3953 int ext
= read_im16(env
, s
);
3954 TCGv src
= DREG(insn
, 0);
3955 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
3956 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
3957 TCGv mask
, tofs
, tlen
;
3961 if ((insn
& 0x0f00) == 0x0d00) { /* bfffo */
3962 tofs
= tcg_temp_new();
3963 tlen
= tcg_temp_new();
3966 if ((ext
& 0x820) == 0) {
3967 /* Immediate width and offset. */
3968 uint32_t maski
= 0x7fffffffu
>> (len
- 1);
3969 if (ofs
+ len
<= 32) {
3970 tcg_gen_shli_i32(QREG_CC_N
, src
, ofs
);
3972 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
3974 tcg_gen_andi_i32(QREG_CC_N
, QREG_CC_N
, ~maski
);
3975 mask
= tcg_const_i32(ror32(maski
, ofs
));
3976 if (!TCGV_IS_UNUSED(tofs
)) {
3977 tcg_gen_movi_i32(tofs
, ofs
);
3978 tcg_gen_movi_i32(tlen
, len
);
3981 TCGv tmp
= tcg_temp_new();
3983 /* Variable width */
3984 tcg_gen_subi_i32(tmp
, DREG(ext
, 0), 1);
3985 tcg_gen_andi_i32(tmp
, tmp
, 31);
3986 mask
= tcg_const_i32(0x7fffffffu
);
3987 tcg_gen_shr_i32(mask
, mask
, tmp
);
3988 if (!TCGV_IS_UNUSED(tlen
)) {
3989 tcg_gen_addi_i32(tlen
, tmp
, 1);
3992 /* Immediate width */
3993 mask
= tcg_const_i32(0x7fffffffu
>> (len
- 1));
3994 if (!TCGV_IS_UNUSED(tlen
)) {
3995 tcg_gen_movi_i32(tlen
, len
);
3999 /* Variable offset */
4000 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4001 tcg_gen_rotl_i32(QREG_CC_N
, src
, tmp
);
4002 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4003 tcg_gen_rotr_i32(mask
, mask
, tmp
);
4004 if (!TCGV_IS_UNUSED(tofs
)) {
4005 tcg_gen_mov_i32(tofs
, tmp
);
4008 /* Immediate offset (and variable width) */
4009 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4010 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4011 tcg_gen_rotri_i32(mask
, mask
, ofs
);
4012 if (!TCGV_IS_UNUSED(tofs
)) {
4013 tcg_gen_movi_i32(tofs
, ofs
);
4018 set_cc_op(s
, CC_OP_LOGIC
);
4020 switch (insn
& 0x0f00) {
4021 case 0x0a00: /* bfchg */
4022 tcg_gen_eqv_i32(src
, src
, mask
);
4024 case 0x0c00: /* bfclr */
4025 tcg_gen_and_i32(src
, src
, mask
);
4027 case 0x0d00: /* bfffo */
4028 gen_helper_bfffo_reg(DREG(ext
, 12), QREG_CC_N
, tofs
, tlen
);
4029 tcg_temp_free(tlen
);
4030 tcg_temp_free(tofs
);
4032 case 0x0e00: /* bfset */
4033 tcg_gen_orc_i32(src
, src
, mask
);
4035 case 0x0800: /* bftst */
4036 /* flags already set; no other work to do. */
4039 g_assert_not_reached();
4041 tcg_temp_free(mask
);
4044 DISAS_INSN(bfop_mem
)
4046 int ext
= read_im16(env
, s
);
4047 TCGv addr
, len
, ofs
;
4050 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4051 if (IS_NULL_QREG(addr
)) {
4059 len
= tcg_const_i32(extract32(ext
, 0, 5));
4064 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4067 switch (insn
& 0x0f00) {
4068 case 0x0a00: /* bfchg */
4069 gen_helper_bfchg_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4071 case 0x0c00: /* bfclr */
4072 gen_helper_bfclr_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4074 case 0x0d00: /* bfffo */
4075 t64
= tcg_temp_new_i64();
4076 gen_helper_bfffo_mem(t64
, cpu_env
, addr
, ofs
, len
);
4077 tcg_gen_extr_i64_i32(DREG(ext
, 12), QREG_CC_N
, t64
);
4078 tcg_temp_free_i64(t64
);
4080 case 0x0e00: /* bfset */
4081 gen_helper_bfset_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4083 case 0x0800: /* bftst */
4084 gen_helper_bfexts_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4087 g_assert_not_reached();
4089 set_cc_op(s
, CC_OP_LOGIC
);
4091 if (!(ext
& 0x20)) {
4094 if (!(ext
& 0x800)) {
4099 DISAS_INSN(bfins_reg
)
4101 int ext
= read_im16(env
, s
);
4102 TCGv dst
= DREG(insn
, 0);
4103 TCGv src
= DREG(ext
, 12);
4104 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4105 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4106 int pos
= 32 - ofs
- len
; /* little bit-endian */
4109 tmp
= tcg_temp_new();
4112 /* Variable width */
4113 tcg_gen_neg_i32(tmp
, DREG(ext
, 0));
4114 tcg_gen_andi_i32(tmp
, tmp
, 31);
4115 tcg_gen_shl_i32(QREG_CC_N
, src
, tmp
);
4117 /* Immediate width */
4118 tcg_gen_shli_i32(QREG_CC_N
, src
, 32 - len
);
4120 set_cc_op(s
, CC_OP_LOGIC
);
4122 /* Immediate width and offset */
4123 if ((ext
& 0x820) == 0) {
4124 /* Check for suitability for deposit. */
4126 tcg_gen_deposit_i32(dst
, dst
, src
, pos
, len
);
4128 uint32_t maski
= -2U << (len
- 1);
4129 uint32_t roti
= (ofs
+ len
) & 31;
4130 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4131 tcg_gen_rotri_i32(tmp
, tmp
, roti
);
4132 tcg_gen_andi_i32(dst
, dst
, ror32(maski
, roti
));
4133 tcg_gen_or_i32(dst
, dst
, tmp
);
4136 TCGv mask
= tcg_temp_new();
4137 TCGv rot
= tcg_temp_new();
4140 /* Variable width */
4141 tcg_gen_subi_i32(rot
, DREG(ext
, 0), 1);
4142 tcg_gen_andi_i32(rot
, rot
, 31);
4143 tcg_gen_movi_i32(mask
, -2);
4144 tcg_gen_shl_i32(mask
, mask
, rot
);
4145 tcg_gen_mov_i32(rot
, DREG(ext
, 0));
4146 tcg_gen_andc_i32(tmp
, src
, mask
);
4148 /* Immediate width (variable offset) */
4149 uint32_t maski
= -2U << (len
- 1);
4150 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4151 tcg_gen_movi_i32(mask
, maski
);
4152 tcg_gen_movi_i32(rot
, len
& 31);
4155 /* Variable offset */
4156 tcg_gen_add_i32(rot
, rot
, DREG(ext
, 6));
4158 /* Immediate offset (variable width) */
4159 tcg_gen_addi_i32(rot
, rot
, ofs
);
4161 tcg_gen_andi_i32(rot
, rot
, 31);
4162 tcg_gen_rotr_i32(mask
, mask
, rot
);
4163 tcg_gen_rotr_i32(tmp
, tmp
, rot
);
4164 tcg_gen_and_i32(dst
, dst
, mask
);
4165 tcg_gen_or_i32(dst
, dst
, tmp
);
4168 tcg_temp_free(mask
);
4173 DISAS_INSN(bfins_mem
)
4175 int ext
= read_im16(env
, s
);
4176 TCGv src
= DREG(ext
, 12);
4177 TCGv addr
, len
, ofs
;
4179 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4180 if (IS_NULL_QREG(addr
)) {
4188 len
= tcg_const_i32(extract32(ext
, 0, 5));
4193 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4196 gen_helper_bfins_mem(QREG_CC_N
, cpu_env
, addr
, src
, ofs
, len
);
4197 set_cc_op(s
, CC_OP_LOGIC
);
4199 if (!(ext
& 0x20)) {
4202 if (!(ext
& 0x800)) {
4210 reg
= DREG(insn
, 0);
4211 gen_logic_cc(s
, reg
, OS_LONG
);
4212 gen_helper_ff1(reg
, reg
);
4215 static TCGv
gen_get_sr(DisasContext
*s
)
4220 ccr
= gen_get_ccr(s
);
4221 sr
= tcg_temp_new();
4222 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
4223 tcg_gen_or_i32(sr
, sr
, ccr
);
4233 ext
= read_im16(env
, s
);
4234 if (ext
!= 0x46FC) {
4235 gen_exception(s
, addr
, EXCP_UNSUPPORTED
);
4238 ext
= read_im16(env
, s
);
4239 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
4240 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
4243 gen_push(s
, gen_get_sr(s
));
4244 gen_set_sr_im(s
, ext
, 0);
4247 DISAS_INSN(move_from_sr
)
4251 if (IS_USER(s
) && !m68k_feature(env
, M68K_FEATURE_M68000
)) {
4252 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4256 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
4259 DISAS_INSN(move_to_sr
)
4262 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4265 gen_set_sr(env
, s
, insn
, 0);
4269 DISAS_INSN(move_from_usp
)
4272 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4275 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
4276 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4279 DISAS_INSN(move_to_usp
)
4282 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4285 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
4286 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4291 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
4299 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4303 ext
= read_im16(env
, s
);
4305 gen_set_sr_im(s
, ext
, 0);
4306 tcg_gen_movi_i32(cpu_halted
, 1);
4307 gen_exception(s
, s
->pc
, EXCP_HLT
);
4313 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4316 gen_exception(s
, s
->pc
- 2, EXCP_RTE
);
4325 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4329 ext
= read_im16(env
, s
);
4332 reg
= AREG(ext
, 12);
4334 reg
= DREG(ext
, 12);
4336 gen_helper_movec(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4343 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4346 /* ICache fetch. Implement as no-op. */
4352 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4355 /* Cache push/invalidate. Implement as no-op. */
4360 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4365 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
4368 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4371 /* TODO: Implement wdebug. */
4372 cpu_abort(CPU(cpu
), "WDEBUG not implemented");
4377 gen_exception(s
, s
->pc
- 2, EXCP_TRAP0
+ (insn
& 0xf));
4380 static void gen_load_fcr(DisasContext
*s
, TCGv res
, int reg
)
4384 tcg_gen_movi_i32(res
, 0);
4387 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4390 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpcr
));
4395 static void gen_store_fcr(DisasContext
*s
, TCGv val
, int reg
)
4401 tcg_gen_st_i32(val
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4404 gen_helper_set_fpcr(cpu_env
, val
);
4409 static void gen_qemu_store_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4411 int index
= IS_USER(s
);
4414 tmp
= tcg_temp_new();
4415 gen_load_fcr(s
, tmp
, reg
);
4416 tcg_gen_qemu_st32(tmp
, addr
, index
);
4420 static void gen_qemu_load_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4422 int index
= IS_USER(s
);
4425 tmp
= tcg_temp_new();
4426 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
4427 gen_store_fcr(s
, tmp
, reg
);
4432 static void gen_op_fmove_fcr(CPUM68KState
*env
, DisasContext
*s
,
4433 uint32_t insn
, uint32_t ext
)
4435 int mask
= (ext
>> 10) & 7;
4436 int is_write
= (ext
>> 13) & 1;
4437 int mode
= extract32(insn
, 3, 3);
4443 if (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&& mask
!= M68K_FPCR
) {
4444 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4448 gen_load_fcr(s
, DREG(insn
, 0), mask
);
4450 gen_store_fcr(s
, DREG(insn
, 0), mask
);
4453 case 1: /* An, only with FPIAR */
4454 if (mask
!= M68K_FPIAR
) {
4455 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4459 gen_load_fcr(s
, AREG(insn
, 0), mask
);
4461 gen_store_fcr(s
, AREG(insn
, 0), mask
);
4468 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
4469 if (IS_NULL_QREG(tmp
)) {
4474 addr
= tcg_temp_new();
4475 tcg_gen_mov_i32(addr
, tmp
);
4479 * 0b100 Floating-Point Control Register
4480 * 0b010 Floating-Point Status Register
4481 * 0b001 Floating-Point Instruction Address Register
4485 if (is_write
&& mode
== 4) {
4486 for (i
= 2; i
>= 0; i
--, mask
>>= 1) {
4488 gen_qemu_store_fcr(s
, addr
, 1 << i
);
4490 tcg_gen_subi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
4494 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4496 for (i
= 0; i
< 3; i
++, mask
>>= 1) {
4499 gen_qemu_store_fcr(s
, addr
, 1 << i
);
4501 gen_qemu_load_fcr(s
, addr
, 1 << i
);
4503 if (mask
!= 1 || mode
== 3) {
4504 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
4509 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4512 tcg_temp_free_i32(addr
);
4515 static void gen_op_fmovem(CPUM68KState
*env
, DisasContext
*s
,
4516 uint32_t insn
, uint32_t ext
)
4520 int mode
= (ext
>> 11) & 0x3;
4521 int is_load
= ((ext
& 0x2000) == 0);
4523 if (m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
4524 opsize
= OS_EXTENDED
;
4526 opsize
= OS_DOUBLE
; /* FIXME */
4529 addr
= gen_lea(env
, s
, insn
, opsize
);
4530 if (IS_NULL_QREG(addr
)) {
4535 tmp
= tcg_temp_new();
4537 /* Dynamic register list */
4538 tcg_gen_ext8u_i32(tmp
, DREG(ext
, 4));
4540 /* Static register list */
4541 tcg_gen_movi_i32(tmp
, ext
& 0xff);
4544 if (!is_load
&& (mode
& 2) == 0) {
4545 /* predecrement addressing mode
4546 * only available to store register to memory
4548 if (opsize
== OS_EXTENDED
) {
4549 gen_helper_fmovemx_st_predec(tmp
, cpu_env
, addr
, tmp
);
4551 gen_helper_fmovemd_st_predec(tmp
, cpu_env
, addr
, tmp
);
4554 /* postincrement addressing mode */
4555 if (opsize
== OS_EXTENDED
) {
4557 gen_helper_fmovemx_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
4559 gen_helper_fmovemx_st_postinc(tmp
, cpu_env
, addr
, tmp
);
4563 gen_helper_fmovemd_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
4565 gen_helper_fmovemd_st_postinc(tmp
, cpu_env
, addr
, tmp
);
4569 if ((insn
& 070) == 030 || (insn
& 070) == 040) {
4570 tcg_gen_mov_i32(AREG(insn
, 0), tmp
);
4575 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
4576 immediately before the next FP instruction is executed. */
4582 TCGv_ptr cpu_src
, cpu_dest
;
4584 ext
= read_im16(env
, s
);
4585 opmode
= ext
& 0x7f;
4586 switch ((ext
>> 13) & 7) {
4592 if (insn
== 0xf200 && (ext
& 0xfc00) == 0x5c00) {
4594 TCGv rom_offset
= tcg_const_i32(opmode
);
4595 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
4596 gen_helper_fconst(cpu_env
, cpu_dest
, rom_offset
);
4597 tcg_temp_free_ptr(cpu_dest
);
4598 tcg_temp_free(rom_offset
);
4602 case 3: /* fmove out */
4603 cpu_src
= gen_fp_ptr(REG(ext
, 7));
4604 opsize
= ext_opsize(ext
, 10);
4605 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
, EA_STORE
) == -1) {
4608 gen_helper_ftst(cpu_env
, cpu_src
);
4609 tcg_temp_free_ptr(cpu_src
);
4611 case 4: /* fmove to control register. */
4612 case 5: /* fmove from control register. */
4613 gen_op_fmove_fcr(env
, s
, insn
, ext
);
4615 case 6: /* fmovem */
4617 if ((ext
& 0x1000) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
4620 gen_op_fmovem(env
, s
, insn
, ext
);
4623 if (ext
& (1 << 14)) {
4624 /* Source effective address. */
4625 opsize
= ext_opsize(ext
, 10);
4626 cpu_src
= gen_fp_result_ptr();
4627 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
, EA_LOADS
) == -1) {
4632 /* Source register. */
4633 opsize
= OS_EXTENDED
;
4634 cpu_src
= gen_fp_ptr(REG(ext
, 10));
4636 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
4639 gen_fp_move(cpu_dest
, cpu_src
);
4641 case 0x40: /* fsmove */
4642 gen_helper_fsround(cpu_env
, cpu_dest
, cpu_src
);
4644 case 0x44: /* fdmove */
4645 gen_helper_fdround(cpu_env
, cpu_dest
, cpu_src
);
4648 gen_helper_firound(cpu_env
, cpu_dest
, cpu_src
);
4650 case 3: /* fintrz */
4651 gen_helper_fitrunc(cpu_env
, cpu_dest
, cpu_src
);
4654 gen_helper_fsqrt(cpu_env
, cpu_dest
, cpu_src
);
4656 case 0x41: /* fssqrt */
4657 gen_helper_fssqrt(cpu_env
, cpu_dest
, cpu_src
);
4659 case 0x45: /* fdsqrt */
4660 gen_helper_fdsqrt(cpu_env
, cpu_dest
, cpu_src
);
4662 case 0x18: /* fabs */
4663 gen_helper_fabs(cpu_env
, cpu_dest
, cpu_src
);
4665 case 0x58: /* fsabs */
4666 gen_helper_fsabs(cpu_env
, cpu_dest
, cpu_src
);
4668 case 0x5c: /* fdabs */
4669 gen_helper_fdabs(cpu_env
, cpu_dest
, cpu_src
);
4671 case 0x1a: /* fneg */
4672 gen_helper_fneg(cpu_env
, cpu_dest
, cpu_src
);
4674 case 0x5a: /* fsneg */
4675 gen_helper_fsneg(cpu_env
, cpu_dest
, cpu_src
);
4677 case 0x5e: /* fdneg */
4678 gen_helper_fdneg(cpu_env
, cpu_dest
, cpu_src
);
4680 case 0x20: /* fdiv */
4681 gen_helper_fdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4683 case 0x60: /* fsdiv */
4684 gen_helper_fsdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4686 case 0x64: /* fddiv */
4687 gen_helper_fddiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4689 case 0x22: /* fadd */
4690 gen_helper_fadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4692 case 0x62: /* fsadd */
4693 gen_helper_fsadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4695 case 0x66: /* fdadd */
4696 gen_helper_fdadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4698 case 0x23: /* fmul */
4699 gen_helper_fmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4701 case 0x63: /* fsmul */
4702 gen_helper_fsmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4704 case 0x67: /* fdmul */
4705 gen_helper_fdmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4707 case 0x24: /* fsgldiv */
4708 gen_helper_fsgldiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4710 case 0x27: /* fsglmul */
4711 gen_helper_fsglmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4713 case 0x28: /* fsub */
4714 gen_helper_fsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4716 case 0x68: /* fssub */
4717 gen_helper_fssub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4719 case 0x6c: /* fdsub */
4720 gen_helper_fdsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4722 case 0x38: /* fcmp */
4723 gen_helper_fcmp(cpu_env
, cpu_src
, cpu_dest
);
4725 case 0x3a: /* ftst */
4726 gen_helper_ftst(cpu_env
, cpu_src
);
4731 tcg_temp_free_ptr(cpu_src
);
4732 gen_helper_ftst(cpu_env
, cpu_dest
);
4733 tcg_temp_free_ptr(cpu_dest
);
4736 /* FIXME: Is this right for offset addressing modes? */
4738 disas_undef_fpu(env
, s
, insn
);
4741 static void gen_fcc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
4746 c
->v2
= tcg_const_i32(0);
4748 /* TODO: Raise BSUN exception. */
4749 fpsr
= tcg_temp_new();
4750 gen_load_fcr(s
, fpsr
, M68K_FPSR
);
4753 case 16: /* Signaling False */
4755 c
->tcond
= TCG_COND_NEVER
;
4757 case 1: /* EQual Z */
4758 case 17: /* Signaling EQual Z */
4759 c
->v1
= tcg_temp_new();
4761 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
4762 c
->tcond
= TCG_COND_NE
;
4764 case 2: /* Ordered Greater Than !(A || Z || N) */
4765 case 18: /* Greater Than !(A || Z || N) */
4766 c
->v1
= tcg_temp_new();
4768 tcg_gen_andi_i32(c
->v1
, fpsr
,
4769 FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
4770 c
->tcond
= TCG_COND_EQ
;
4772 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
4773 case 19: /* Greater than or Equal Z || !(A || N) */
4774 c
->v1
= tcg_temp_new();
4776 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
4777 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
4778 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_Z
| FPSR_CC_N
);
4779 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
4780 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
4781 c
->tcond
= TCG_COND_NE
;
4783 case 4: /* Ordered Less Than !(!N || A || Z); */
4784 case 20: /* Less Than !(!N || A || Z); */
4785 c
->v1
= tcg_temp_new();
4787 tcg_gen_xori_i32(c
->v1
, fpsr
, FPSR_CC_N
);
4788 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_N
| FPSR_CC_A
| FPSR_CC_Z
);
4789 c
->tcond
= TCG_COND_EQ
;
4791 case 5: /* Ordered Less than or Equal Z || (N && !A) */
4792 case 21: /* Less than or Equal Z || (N && !A) */
4793 c
->v1
= tcg_temp_new();
4795 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
4796 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
4797 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
4798 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_Z
| FPSR_CC_N
);
4799 c
->tcond
= TCG_COND_NE
;
4801 case 6: /* Ordered Greater or Less than !(A || Z) */
4802 case 22: /* Greater or Less than !(A || Z) */
4803 c
->v1
= tcg_temp_new();
4805 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
4806 c
->tcond
= TCG_COND_EQ
;
4808 case 7: /* Ordered !A */
4809 case 23: /* Greater, Less or Equal !A */
4810 c
->v1
= tcg_temp_new();
4812 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
4813 c
->tcond
= TCG_COND_EQ
;
4815 case 8: /* Unordered A */
4816 case 24: /* Not Greater, Less or Equal A */
4817 c
->v1
= tcg_temp_new();
4819 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
4820 c
->tcond
= TCG_COND_NE
;
4822 case 9: /* Unordered or Equal A || Z */
4823 case 25: /* Not Greater or Less then A || Z */
4824 c
->v1
= tcg_temp_new();
4826 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
4827 c
->tcond
= TCG_COND_NE
;
4829 case 10: /* Unordered or Greater Than A || !(N || Z)) */
4830 case 26: /* Not Less or Equal A || !(N || Z)) */
4831 c
->v1
= tcg_temp_new();
4833 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
4834 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
4835 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_A
| FPSR_CC_N
);
4836 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
4837 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
4838 c
->tcond
= TCG_COND_NE
;
4840 case 11: /* Unordered or Greater or Equal A || Z || !N */
4841 case 27: /* Not Less Than A || Z || !N */
4842 c
->v1
= tcg_temp_new();
4844 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
4845 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
4846 c
->tcond
= TCG_COND_NE
;
4848 case 12: /* Unordered or Less Than A || (N && !Z) */
4849 case 28: /* Not Greater than or Equal A || (N && !Z) */
4850 c
->v1
= tcg_temp_new();
4852 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
4853 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
4854 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
4855 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_A
| FPSR_CC_N
);
4856 c
->tcond
= TCG_COND_NE
;
4858 case 13: /* Unordered or Less or Equal A || Z || N */
4859 case 29: /* Not Greater Than A || Z || N */
4860 c
->v1
= tcg_temp_new();
4862 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
4863 c
->tcond
= TCG_COND_NE
;
4865 case 14: /* Not Equal !Z */
4866 case 30: /* Signaling Not Equal !Z */
4867 c
->v1
= tcg_temp_new();
4869 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
4870 c
->tcond
= TCG_COND_EQ
;
4873 case 31: /* Signaling True */
4875 c
->tcond
= TCG_COND_ALWAYS
;
4878 tcg_temp_free(fpsr
);
4881 static void gen_fjmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
4885 gen_fcc_cond(&c
, s
, cond
);
4886 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
4897 offset
= (int16_t)read_im16(env
, s
);
4898 if (insn
& (1 << 6)) {
4899 offset
= (offset
<< 16) | read_im16(env
, s
);
4902 l1
= gen_new_label();
4904 gen_fjmpcc(s
, insn
& 0x3f, l1
);
4905 gen_jmp_tb(s
, 0, s
->pc
);
4907 gen_jmp_tb(s
, 1, base
+ offset
);
4917 ext
= read_im16(env
, s
);
4919 gen_fcc_cond(&c
, s
, cond
);
4921 tmp
= tcg_temp_new();
4922 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
4925 tcg_gen_neg_i32(tmp
, tmp
);
4926 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
4930 DISAS_INSN(frestore
)
4932 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
4934 /* TODO: Implement frestore. */
4935 cpu_abort(CPU(cpu
), "FRESTORE not implemented");
4940 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
4942 /* TODO: Implement fsave. */
4943 cpu_abort(CPU(cpu
), "FSAVE not implemented");
4946 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
4948 TCGv tmp
= tcg_temp_new();
4949 if (s
->env
->macsr
& MACSR_FI
) {
4951 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
4953 tcg_gen_shli_i32(tmp
, val
, 16);
4954 } else if (s
->env
->macsr
& MACSR_SU
) {
4956 tcg_gen_sari_i32(tmp
, val
, 16);
4958 tcg_gen_ext16s_i32(tmp
, val
);
4961 tcg_gen_shri_i32(tmp
, val
, 16);
4963 tcg_gen_ext16u_i32(tmp
, val
);
4968 static void gen_mac_clear_flags(void)
4970 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
4971 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
4987 s
->mactmp
= tcg_temp_new_i64();
4991 ext
= read_im16(env
, s
);
4993 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
4994 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
4995 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
4996 disas_undef(env
, s
, insn
);
5000 /* MAC with load. */
5001 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
5002 addr
= tcg_temp_new();
5003 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
5004 /* Load the value now to ensure correct exception behavior.
5005 Perform writeback after reading the MAC inputs. */
5006 loadval
= gen_load(s
, OS_LONG
, addr
, 0);
5009 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
5010 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
5012 loadval
= addr
= NULL_QREG
;
5013 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5014 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5017 gen_mac_clear_flags();
5020 /* Disabled because conditional branches clobber temporary vars. */
5021 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
5022 /* Skip the multiply if we know we will ignore it. */
5023 l1
= gen_new_label();
5024 tmp
= tcg_temp_new();
5025 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
5026 gen_op_jmp_nz32(tmp
, l1
);
5030 if ((ext
& 0x0800) == 0) {
5032 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
5033 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
5035 if (s
->env
->macsr
& MACSR_FI
) {
5036 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
5038 if (s
->env
->macsr
& MACSR_SU
)
5039 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
5041 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
5042 switch ((ext
>> 9) & 3) {
5044 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
5047 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
5053 /* Save the overflow flag from the multiply. */
5054 saved_flags
= tcg_temp_new();
5055 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
5057 saved_flags
= NULL_QREG
;
5061 /* Disabled because conditional branches clobber temporary vars. */
5062 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
5063 /* Skip the accumulate if the value is already saturated. */
5064 l1
= gen_new_label();
5065 tmp
= tcg_temp_new();
5066 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5067 gen_op_jmp_nz32(tmp
, l1
);
5072 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5074 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5076 if (s
->env
->macsr
& MACSR_FI
)
5077 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5078 else if (s
->env
->macsr
& MACSR_SU
)
5079 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5081 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5084 /* Disabled because conditional branches clobber temporary vars. */
5090 /* Dual accumulate variant. */
5091 acc
= (ext
>> 2) & 3;
5092 /* Restore the overflow flag from the multiplier. */
5093 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
5095 /* Disabled because conditional branches clobber temporary vars. */
5096 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
5097 /* Skip the accumulate if the value is already saturated. */
5098 l1
= gen_new_label();
5099 tmp
= tcg_temp_new();
5100 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5101 gen_op_jmp_nz32(tmp
, l1
);
5105 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5107 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5108 if (s
->env
->macsr
& MACSR_FI
)
5109 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5110 else if (s
->env
->macsr
& MACSR_SU
)
5111 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5113 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5115 /* Disabled because conditional branches clobber temporary vars. */
5120 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
5124 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5125 tcg_gen_mov_i32(rw
, loadval
);
5126 /* FIXME: Should address writeback happen with the masked or
5128 switch ((insn
>> 3) & 7) {
5129 case 3: /* Post-increment. */
5130 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
5132 case 4: /* Pre-decrement. */
5133 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5138 DISAS_INSN(from_mac
)
5144 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5145 accnum
= (insn
>> 9) & 3;
5146 acc
= MACREG(accnum
);
5147 if (s
->env
->macsr
& MACSR_FI
) {
5148 gen_helper_get_macf(rx
, cpu_env
, acc
);
5149 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
5150 tcg_gen_extrl_i64_i32(rx
, acc
);
5151 } else if (s
->env
->macsr
& MACSR_SU
) {
5152 gen_helper_get_macs(rx
, acc
);
5154 gen_helper_get_macu(rx
, acc
);
5157 tcg_gen_movi_i64(acc
, 0);
5158 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5162 DISAS_INSN(move_mac
)
5164 /* FIXME: This can be done without a helper. */
5168 dest
= tcg_const_i32((insn
>> 9) & 3);
5169 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
5170 gen_mac_clear_flags();
5171 gen_helper_mac_set_flags(cpu_env
, dest
);
5174 DISAS_INSN(from_macsr
)
5178 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5179 tcg_gen_mov_i32(reg
, QREG_MACSR
);
5182 DISAS_INSN(from_mask
)
5185 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5186 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
5189 DISAS_INSN(from_mext
)
5193 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5194 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5195 if (s
->env
->macsr
& MACSR_FI
)
5196 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
5198 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
5201 DISAS_INSN(macsr_to_ccr
)
5203 TCGv tmp
= tcg_temp_new();
5204 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 0xf);
5205 gen_helper_set_sr(cpu_env
, tmp
);
5207 set_cc_op(s
, CC_OP_FLAGS
);
5215 accnum
= (insn
>> 9) & 3;
5216 acc
= MACREG(accnum
);
5217 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5218 if (s
->env
->macsr
& MACSR_FI
) {
5219 tcg_gen_ext_i32_i64(acc
, val
);
5220 tcg_gen_shli_i64(acc
, acc
, 8);
5221 } else if (s
->env
->macsr
& MACSR_SU
) {
5222 tcg_gen_ext_i32_i64(acc
, val
);
5224 tcg_gen_extu_i32_i64(acc
, val
);
5226 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5227 gen_mac_clear_flags();
5228 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
5231 DISAS_INSN(to_macsr
)
5234 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5235 gen_helper_set_macsr(cpu_env
, val
);
5242 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5243 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
5250 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5251 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5252 if (s
->env
->macsr
& MACSR_FI
)
5253 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
5254 else if (s
->env
->macsr
& MACSR_SU
)
5255 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
5257 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
5260 static disas_proc opcode_table
[65536];
5263 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
5269 /* Sanity check. All set bits must be included in the mask. */
5270 if (opcode
& ~mask
) {
5272 "qemu internal error: bogus opcode definition %04x/%04x\n",
5276 /* This could probably be cleverer. For now just optimize the case where
5277 the top bits are known. */
5278 /* Find the first zero bit in the mask. */
5280 while ((i
& mask
) != 0)
5282 /* Iterate over all combinations of this and lower bits. */
5287 from
= opcode
& ~(i
- 1);
5289 for (i
= from
; i
< to
; i
++) {
5290 if ((i
& mask
) == opcode
)
5291 opcode_table
[i
] = proc
;
5295 /* Register m68k opcode handlers. Order is important.
5296 Later insn override earlier ones. */
5297 void register_m68k_insns (CPUM68KState
*env
)
5299 /* Build the opcode table only once to avoid
5300 multithreading issues. */
5301 if (opcode_table
[0] != NULL
) {
5305 /* use BASE() for instruction available
5306 * for CF_ISA_A and M68000.
5308 #define BASE(name, opcode, mask) \
5309 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5310 #define INSN(name, opcode, mask, feature) do { \
5311 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5312 BASE(name, opcode, mask); \
5314 BASE(undef
, 0000, 0000);
5315 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
5316 INSN(arith_im
, 0000, ff00
, M68000
);
5317 INSN(undef
, 00c0
, ffc0
, M68000
);
5318 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
5319 BASE(bitop_reg
, 0100, f1c0
);
5320 BASE(bitop_reg
, 0140, f1c0
);
5321 BASE(bitop_reg
, 0180, f1c0
);
5322 BASE(bitop_reg
, 01c0
, f1c0
);
5323 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
5324 INSN(arith_im
, 0200, ff00
, M68000
);
5325 INSN(undef
, 02c0
, ffc0
, M68000
);
5326 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
5327 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
5328 INSN(arith_im
, 0400, ff00
, M68000
);
5329 INSN(undef
, 04c0
, ffc0
, M68000
);
5330 INSN(arith_im
, 0600, ff00
, M68000
);
5331 INSN(undef
, 06c0
, ffc0
, M68000
);
5332 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
5333 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
5334 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
5335 INSN(arith_im
, 0c00
, ff00
, M68000
);
5336 BASE(bitop_im
, 0800, ffc0
);
5337 BASE(bitop_im
, 0840, ffc0
);
5338 BASE(bitop_im
, 0880, ffc0
);
5339 BASE(bitop_im
, 08c0
, ffc0
);
5340 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
5341 INSN(arith_im
, 0a00
, ff00
, M68000
);
5342 INSN(cas
, 0ac0
, ffc0
, CAS
);
5343 INSN(cas
, 0cc0
, ffc0
, CAS
);
5344 INSN(cas
, 0ec0
, ffc0
, CAS
);
5345 INSN(cas2w
, 0cfc
, ffff
, CAS
);
5346 INSN(cas2l
, 0efc
, ffff
, CAS
);
5347 BASE(move
, 1000, f000
);
5348 BASE(move
, 2000, f000
);
5349 BASE(move
, 3000, f000
);
5350 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
5351 INSN(negx
, 4080, fff8
, CF_ISA_A
);
5352 INSN(negx
, 4000, ff00
, M68000
);
5353 INSN(undef
, 40c0
, ffc0
, M68000
);
5354 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
5355 INSN(move_from_sr
, 40c0
, ffc0
, M68000
);
5356 BASE(lea
, 41c0
, f1c0
);
5357 BASE(clr
, 4200, ff00
);
5358 BASE(undef
, 42c0
, ffc0
);
5359 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
5360 INSN(move_from_ccr
, 42c0
, ffc0
, M68000
);
5361 INSN(neg
, 4480, fff8
, CF_ISA_A
);
5362 INSN(neg
, 4400, ff00
, M68000
);
5363 INSN(undef
, 44c0
, ffc0
, M68000
);
5364 BASE(move_to_ccr
, 44c0
, ffc0
);
5365 INSN(not, 4680, fff8
, CF_ISA_A
);
5366 INSN(not, 4600, ff00
, M68000
);
5367 INSN(undef
, 46c0
, ffc0
, M68000
);
5368 INSN(move_to_sr
, 46c0
, ffc0
, CF_ISA_A
);
5369 INSN(nbcd
, 4800, ffc0
, M68000
);
5370 INSN(linkl
, 4808, fff8
, M68000
);
5371 BASE(pea
, 4840, ffc0
);
5372 BASE(swap
, 4840, fff8
);
5373 INSN(bkpt
, 4848, fff8
, BKPT
);
5374 INSN(movem
, 48d0
, fbf8
, CF_ISA_A
);
5375 INSN(movem
, 48e8
, fbf8
, CF_ISA_A
);
5376 INSN(movem
, 4880, fb80
, M68000
);
5377 BASE(ext
, 4880, fff8
);
5378 BASE(ext
, 48c0
, fff8
);
5379 BASE(ext
, 49c0
, fff8
);
5380 BASE(tst
, 4a00
, ff00
);
5381 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
5382 INSN(tas
, 4ac0
, ffc0
, M68000
);
5383 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
5384 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
5385 BASE(illegal
, 4afc
, ffff
);
5386 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
5387 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
5388 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
5389 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
5390 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
5391 BASE(trap
, 4e40
, fff0
);
5392 BASE(link
, 4e50
, fff8
);
5393 BASE(unlk
, 4e58
, fff8
);
5394 INSN(move_to_usp
, 4e60
, fff8
, USP
);
5395 INSN(move_from_usp
, 4e68
, fff8
, USP
);
5396 BASE(nop
, 4e71
, ffff
);
5397 BASE(stop
, 4e72
, ffff
);
5398 BASE(rte
, 4e73
, ffff
);
5399 INSN(rtd
, 4e74
, ffff
, RTD
);
5400 BASE(rts
, 4e75
, ffff
);
5401 INSN(movec
, 4e7b
, ffff
, CF_ISA_A
);
5402 BASE(jump
, 4e80
, ffc0
);
5403 BASE(jump
, 4ec0
, ffc0
);
5404 INSN(addsubq
, 5000, f080
, M68000
);
5405 BASE(addsubq
, 5080, f0c0
);
5406 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
); /* Scc.B Dx */
5407 INSN(scc
, 50c0
, f0c0
, M68000
); /* Scc.B <EA> */
5408 INSN(dbcc
, 50c8
, f0f8
, M68000
);
5409 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
5411 /* Branch instructions. */
5412 BASE(branch
, 6000, f000
);
5413 /* Disable long branch instructions, then add back the ones we want. */
5414 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
5415 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
5416 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
5417 INSN(branch
, 60ff
, ffff
, BRAL
);
5418 INSN(branch
, 60ff
, f0ff
, BCCL
);
5420 BASE(moveq
, 7000, f100
);
5421 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
5422 BASE(or, 8000, f000
);
5423 BASE(divw
, 80c0
, f0c0
);
5424 INSN(sbcd_reg
, 8100, f1f8
, M68000
);
5425 INSN(sbcd_mem
, 8108, f1f8
, M68000
);
5426 BASE(addsub
, 9000, f000
);
5427 INSN(undef
, 90c0
, f0c0
, CF_ISA_A
);
5428 INSN(subx_reg
, 9180, f1f8
, CF_ISA_A
);
5429 INSN(subx_reg
, 9100, f138
, M68000
);
5430 INSN(subx_mem
, 9108, f138
, M68000
);
5431 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
5432 INSN(suba
, 90c0
, f0c0
, M68000
);
5434 BASE(undef_mac
, a000
, f000
);
5435 INSN(mac
, a000
, f100
, CF_EMAC
);
5436 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
5437 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
5438 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
5439 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
5440 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
5441 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
5442 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
5443 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
5444 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
5445 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
5447 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
5448 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
5449 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
5450 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
5451 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
5452 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
5453 INSN(cmp
, b000
, f100
, M68000
);
5454 INSN(eor
, b100
, f100
, M68000
);
5455 INSN(cmpm
, b108
, f138
, M68000
);
5456 INSN(cmpa
, b0c0
, f0c0
, M68000
);
5457 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
5458 BASE(and, c000
, f000
);
5459 INSN(exg_dd
, c140
, f1f8
, M68000
);
5460 INSN(exg_aa
, c148
, f1f8
, M68000
);
5461 INSN(exg_da
, c188
, f1f8
, M68000
);
5462 BASE(mulw
, c0c0
, f0c0
);
5463 INSN(abcd_reg
, c100
, f1f8
, M68000
);
5464 INSN(abcd_mem
, c108
, f1f8
, M68000
);
5465 BASE(addsub
, d000
, f000
);
5466 INSN(undef
, d0c0
, f0c0
, CF_ISA_A
);
5467 INSN(addx_reg
, d180
, f1f8
, CF_ISA_A
);
5468 INSN(addx_reg
, d100
, f138
, M68000
);
5469 INSN(addx_mem
, d108
, f138
, M68000
);
5470 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
5471 INSN(adda
, d0c0
, f0c0
, M68000
);
5472 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
5473 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
5474 INSN(shift8_im
, e000
, f0f0
, M68000
);
5475 INSN(shift16_im
, e040
, f0f0
, M68000
);
5476 INSN(shift_im
, e080
, f0f0
, M68000
);
5477 INSN(shift8_reg
, e020
, f0f0
, M68000
);
5478 INSN(shift16_reg
, e060
, f0f0
, M68000
);
5479 INSN(shift_reg
, e0a0
, f0f0
, M68000
);
5480 INSN(shift_mem
, e0c0
, fcc0
, M68000
);
5481 INSN(rotate_im
, e090
, f0f0
, M68000
);
5482 INSN(rotate8_im
, e010
, f0f0
, M68000
);
5483 INSN(rotate16_im
, e050
, f0f0
, M68000
);
5484 INSN(rotate_reg
, e0b0
, f0f0
, M68000
);
5485 INSN(rotate8_reg
, e030
, f0f0
, M68000
);
5486 INSN(rotate16_reg
, e070
, f0f0
, M68000
);
5487 INSN(rotate_mem
, e4c0
, fcc0
, M68000
);
5488 INSN(bfext_mem
, e9c0
, fdc0
, BITFIELD
); /* bfextu & bfexts */
5489 INSN(bfext_reg
, e9c0
, fdf8
, BITFIELD
);
5490 INSN(bfins_mem
, efc0
, ffc0
, BITFIELD
);
5491 INSN(bfins_reg
, efc0
, fff8
, BITFIELD
);
5492 INSN(bfop_mem
, eac0
, ffc0
, BITFIELD
); /* bfchg */
5493 INSN(bfop_reg
, eac0
, fff8
, BITFIELD
); /* bfchg */
5494 INSN(bfop_mem
, ecc0
, ffc0
, BITFIELD
); /* bfclr */
5495 INSN(bfop_reg
, ecc0
, fff8
, BITFIELD
); /* bfclr */
5496 INSN(bfop_mem
, edc0
, ffc0
, BITFIELD
); /* bfffo */
5497 INSN(bfop_reg
, edc0
, fff8
, BITFIELD
); /* bfffo */
5498 INSN(bfop_mem
, eec0
, ffc0
, BITFIELD
); /* bfset */
5499 INSN(bfop_reg
, eec0
, fff8
, BITFIELD
); /* bfset */
5500 INSN(bfop_mem
, e8c0
, ffc0
, BITFIELD
); /* bftst */
5501 INSN(bfop_reg
, e8c0
, fff8
, BITFIELD
); /* bftst */
5502 BASE(undef_fpu
, f000
, f000
);
5503 INSN(fpu
, f200
, ffc0
, CF_FPU
);
5504 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
5505 INSN(frestore
, f340
, ffc0
, CF_FPU
);
5506 INSN(fsave
, f300
, ffc0
, CF_FPU
);
5507 INSN(fpu
, f200
, ffc0
, FPU
);
5508 INSN(fscc
, f240
, ffc0
, FPU
);
5509 INSN(fbcc
, f280
, ff80
, FPU
);
5510 INSN(frestore
, f340
, ffc0
, FPU
);
5511 INSN(fsave
, f300
, ffc0
, FPU
);
5512 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
5513 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
5514 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
5515 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
5519 /* ??? Some of this implementation is not exception safe. We should always
5520 write back the result to memory before setting the condition codes. */
5521 static void disas_m68k_insn(CPUM68KState
* env
, DisasContext
*s
)
5523 uint16_t insn
= read_im16(env
, s
);
5524 opcode_table
[insn
](env
, s
, insn
);
5528 /* generate intermediate code for basic block 'tb'. */
5529 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
)
5531 CPUM68KState
*env
= cs
->env_ptr
;
5532 DisasContext dc1
, *dc
= &dc1
;
5533 target_ulong pc_start
;
5538 /* generate intermediate code */
5544 dc
->is_jmp
= DISAS_NEXT
;
5546 dc
->cc_op
= CC_OP_DYNAMIC
;
5547 dc
->cc_op_synced
= 1;
5548 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
5549 dc
->user
= (env
->sr
& SR_S
) == 0;
5551 dc
->writeback_mask
= 0;
5553 max_insns
= tb_cflags(tb
) & CF_COUNT_MASK
;
5554 if (max_insns
== 0) {
5555 max_insns
= CF_COUNT_MASK
;
5557 if (max_insns
> TCG_MAX_INSNS
) {
5558 max_insns
= TCG_MAX_INSNS
;
5563 pc_offset
= dc
->pc
- pc_start
;
5564 gen_throws_exception
= NULL
;
5565 tcg_gen_insn_start(dc
->pc
, dc
->cc_op
);
5568 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
5569 gen_exception(dc
, dc
->pc
, EXCP_DEBUG
);
5570 dc
->is_jmp
= DISAS_JUMP
;
5571 /* The address covered by the breakpoint must be included in
5572 [tb->pc, tb->pc + tb->size) in order to for it to be
5573 properly cleared -- thus we increment the PC here so that
5574 the logic setting tb->size below does the right thing. */
5579 if (num_insns
== max_insns
&& (tb_cflags(tb
) & CF_LAST_IO
)) {
5583 dc
->insn_pc
= dc
->pc
;
5584 disas_m68k_insn(env
, dc
);
5585 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
5586 !cs
->singlestep_enabled
&&
5588 (pc_offset
) < (TARGET_PAGE_SIZE
- 32) &&
5589 num_insns
< max_insns
);
5591 if (tb_cflags(tb
) & CF_LAST_IO
)
5593 if (unlikely(cs
->singlestep_enabled
)) {
5594 /* Make sure the pc is updated, and raise a debug exception. */
5597 tcg_gen_movi_i32(QREG_PC
, dc
->pc
);
5599 gen_helper_raise_exception(cpu_env
, tcg_const_i32(EXCP_DEBUG
));
5601 switch(dc
->is_jmp
) {
5604 gen_jmp_tb(dc
, 0, dc
->pc
);
5610 /* indicate that the hash table must be used to find the next TB */
5614 /* nothing more to generate */
5618 gen_tb_end(tb
, num_insns
);
5621 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
5622 && qemu_log_in_addr_range(pc_start
)) {
5624 qemu_log("----------------\n");
5625 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
5626 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
);
5631 tb
->size
= dc
->pc
- pc_start
;
5632 tb
->icount
= num_insns
;
5635 static double floatx80_to_double(CPUM68KState
*env
, uint16_t high
, uint64_t low
)
5637 floatx80 a
= { .high
= high
, .low
= low
};
5643 u
.f64
= floatx80_to_float64(a
, &env
->fp_status
);
5647 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
5650 M68kCPU
*cpu
= M68K_CPU(cs
);
5651 CPUM68KState
*env
= &cpu
->env
;
5654 for (i
= 0; i
< 8; i
++) {
5655 cpu_fprintf(f
, "D%d = %08x A%d = %08x "
5656 "F%d = %04x %016"PRIx64
" (%12g)\n",
5657 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
5658 i
, env
->fregs
[i
].l
.upper
, env
->fregs
[i
].l
.lower
,
5659 floatx80_to_double(env
, env
->fregs
[i
].l
.upper
,
5660 env
->fregs
[i
].l
.lower
));
5662 cpu_fprintf (f
, "PC = %08x ", env
->pc
);
5663 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
5664 cpu_fprintf(f
, "SR = %04x %c%c%c%c%c ", sr
, (sr
& CCF_X
) ? 'X' : '-',
5665 (sr
& CCF_N
) ? 'N' : '-', (sr
& CCF_Z
) ? 'Z' : '-',
5666 (sr
& CCF_V
) ? 'V' : '-', (sr
& CCF_C
) ? 'C' : '-');
5667 cpu_fprintf(f
, "FPSR = %08x %c%c%c%c ", env
->fpsr
,
5668 (env
->fpsr
& FPSR_CC_A
) ? 'A' : '-',
5669 (env
->fpsr
& FPSR_CC_I
) ? 'I' : '-',
5670 (env
->fpsr
& FPSR_CC_Z
) ? 'Z' : '-',
5671 (env
->fpsr
& FPSR_CC_N
) ? 'N' : '-');
5672 cpu_fprintf(f
, "\n "
5673 "FPCR = %04x ", env
->fpcr
);
5674 switch (env
->fpcr
& FPCR_PREC_MASK
) {
5676 cpu_fprintf(f
, "X ");
5679 cpu_fprintf(f
, "S ");
5682 cpu_fprintf(f
, "D ");
5685 switch (env
->fpcr
& FPCR_RND_MASK
) {
5687 cpu_fprintf(f
, "RN ");
5690 cpu_fprintf(f
, "RZ ");
5693 cpu_fprintf(f
, "RM ");
5696 cpu_fprintf(f
, "RP ");
5701 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,
5704 int cc_op
= data
[1];
5706 if (cc_op
!= CC_OP_DYNAMIC
) {