4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
28 #include "exec/translator.h"
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
33 #include "trace-tcg.h"
36 //#define DEBUG_DISPATCH 1
38 #define DEFO32(name, offset) static TCGv QREG_##name;
39 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
44 static TCGv_i32 cpu_halted
;
45 static TCGv_i32 cpu_exception_index
;
47 static TCGv_env cpu_env
;
49 static char cpu_reg_names
[2 * 8 * 3 + 5 * 4];
50 static TCGv cpu_dregs
[8];
51 static TCGv cpu_aregs
[8];
52 static TCGv_i64 cpu_macc
[4];
54 #define REG(insn, pos) (((insn) >> (pos)) & 7)
55 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
56 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
57 #define MACREG(acc) cpu_macc[acc]
58 #define QREG_SP get_areg(s, 7)
60 static TCGv NULL_QREG
;
61 #define IS_NULL_QREG(t) (t == NULL_QREG)
62 /* Used to distinguish stores from bad addressing modes. */
63 static TCGv store_dummy
;
65 #include "exec/gen-icount.h"
67 void m68k_tcg_init(void)
72 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
73 tcg_ctx
->tcg_env
= cpu_env
;
75 #define DEFO32(name, offset) \
76 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
77 offsetof(CPUM68KState, offset), #name);
78 #define DEFO64(name, offset) \
79 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
80 offsetof(CPUM68KState, offset), #name);
85 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
86 -offsetof(M68kCPU
, env
) +
87 offsetof(CPUState
, halted
), "HALTED");
88 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
89 -offsetof(M68kCPU
, env
) +
90 offsetof(CPUState
, exception_index
),
94 for (i
= 0; i
< 8; i
++) {
96 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
97 offsetof(CPUM68KState
, dregs
[i
]), p
);
100 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
101 offsetof(CPUM68KState
, aregs
[i
]), p
);
104 for (i
= 0; i
< 4; i
++) {
105 sprintf(p
, "ACC%d", i
);
106 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
107 offsetof(CPUM68KState
, macc
[i
]), p
);
111 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
112 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
115 /* internal defines */
116 typedef struct DisasContext
{
118 target_ulong insn_pc
; /* Start of the current instruction. */
121 CCOp cc_op
; /* Current CC operation */
124 struct TranslationBlock
*tb
;
125 int singlestep_enabled
;
132 static TCGv
get_areg(DisasContext
*s
, unsigned regno
)
134 if (s
->writeback_mask
& (1 << regno
)) {
135 return s
->writeback
[regno
];
137 return cpu_aregs
[regno
];
141 static void delay_set_areg(DisasContext
*s
, unsigned regno
,
142 TCGv val
, bool give_temp
)
144 if (s
->writeback_mask
& (1 << regno
)) {
146 tcg_temp_free(s
->writeback
[regno
]);
147 s
->writeback
[regno
] = val
;
149 tcg_gen_mov_i32(s
->writeback
[regno
], val
);
152 s
->writeback_mask
|= 1 << regno
;
154 s
->writeback
[regno
] = val
;
156 TCGv tmp
= tcg_temp_new();
157 s
->writeback
[regno
] = tmp
;
158 tcg_gen_mov_i32(tmp
, val
);
163 static void do_writebacks(DisasContext
*s
)
165 unsigned mask
= s
->writeback_mask
;
167 s
->writeback_mask
= 0;
169 unsigned regno
= ctz32(mask
);
170 tcg_gen_mov_i32(cpu_aregs
[regno
], s
->writeback
[regno
]);
171 tcg_temp_free(s
->writeback
[regno
]);
177 /* is_jmp field values */
178 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
179 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
180 #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
181 #define DISAS_JUMP_NEXT DISAS_TARGET_3
183 #if defined(CONFIG_USER_ONLY)
186 #define IS_USER(s) s->user
189 /* XXX: move that elsewhere */
190 /* ??? Fix exceptions. */
191 static void *gen_throws_exception
;
192 #define gen_last_qop NULL
194 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
196 #ifdef DEBUG_DISPATCH
197 #define DISAS_INSN(name) \
198 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
200 static void disas_##name(CPUM68KState *env, DisasContext *s, \
203 qemu_log("Dispatch " #name "\n"); \
204 real_disas_##name(env, s, insn); \
206 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
209 #define DISAS_INSN(name) \
210 static void disas_##name(CPUM68KState *env, DisasContext *s, \
214 static const uint8_t cc_op_live
[CC_OP_NB
] = {
215 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
216 [CC_OP_ADDB
... CC_OP_ADDL
] = CCF_X
| CCF_N
| CCF_V
,
217 [CC_OP_SUBB
... CC_OP_SUBL
] = CCF_X
| CCF_N
| CCF_V
,
218 [CC_OP_CMPB
... CC_OP_CMPL
] = CCF_X
| CCF_N
| CCF_V
,
219 [CC_OP_LOGIC
] = CCF_X
| CCF_N
222 static void set_cc_op(DisasContext
*s
, CCOp op
)
224 CCOp old_op
= s
->cc_op
;
233 /* Discard CC computation that will no longer be used.
234 Note that X and N are never dead. */
235 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
237 tcg_gen_discard_i32(QREG_CC_C
);
240 tcg_gen_discard_i32(QREG_CC_Z
);
243 tcg_gen_discard_i32(QREG_CC_V
);
247 /* Update the CPU env CC_OP state. */
248 static void update_cc_op(DisasContext
*s
)
250 if (!s
->cc_op_synced
) {
252 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
256 /* Generate a jump to an immediate address. */
257 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
260 tcg_gen_movi_i32(QREG_PC
, dest
);
261 s
->is_jmp
= DISAS_JUMP
;
264 /* Generate a jump to the address in qreg DEST. */
265 static void gen_jmp(DisasContext
*s
, TCGv dest
)
268 tcg_gen_mov_i32(QREG_PC
, dest
);
269 s
->is_jmp
= DISAS_JUMP
;
272 static void gen_raise_exception(int nr
)
274 TCGv_i32 tmp
= tcg_const_i32(nr
);
276 gen_helper_raise_exception(cpu_env
, tmp
);
277 tcg_temp_free_i32(tmp
);
280 static void gen_exception(DisasContext
*s
, uint32_t where
, int nr
)
283 gen_jmp_im(s
, where
);
284 gen_raise_exception(nr
);
287 static inline void gen_addr_fault(DisasContext
*s
)
289 gen_exception(s
, s
->insn_pc
, EXCP_ADDRESS
);
292 /* Generate a load from the specified address. Narrow values are
293 sign extended to full register width. */
294 static inline TCGv
gen_load(DisasContext
* s
, int opsize
, TCGv addr
, int sign
)
297 int index
= IS_USER(s
);
298 tmp
= tcg_temp_new_i32();
302 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
304 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
308 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
310 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
313 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
316 g_assert_not_reached();
318 gen_throws_exception
= gen_last_qop
;
322 /* Generate a store. */
323 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
)
325 int index
= IS_USER(s
);
328 tcg_gen_qemu_st8(val
, addr
, index
);
331 tcg_gen_qemu_st16(val
, addr
, index
);
334 tcg_gen_qemu_st32(val
, addr
, index
);
337 g_assert_not_reached();
339 gen_throws_exception
= gen_last_qop
;
348 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
349 otherwise generate a store. */
350 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
353 if (what
== EA_STORE
) {
354 gen_store(s
, opsize
, addr
, val
);
357 return gen_load(s
, opsize
, addr
, what
== EA_LOADS
);
361 /* Read a 16-bit immediate constant */
362 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
365 im
= cpu_lduw_code(env
, s
->pc
);
370 /* Read an 8-bit immediate constant */
371 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
373 return read_im16(env
, s
);
376 /* Read a 32-bit immediate constant. */
377 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
380 im
= read_im16(env
, s
) << 16;
381 im
|= 0xffff & read_im16(env
, s
);
385 /* Read a 64-bit immediate constant. */
386 static inline uint64_t read_im64(CPUM68KState
*env
, DisasContext
*s
)
389 im
= (uint64_t)read_im32(env
, s
) << 32;
390 im
|= (uint64_t)read_im32(env
, s
);
394 /* Calculate and address index. */
395 static TCGv
gen_addr_index(DisasContext
*s
, uint16_t ext
, TCGv tmp
)
400 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
401 if ((ext
& 0x800) == 0) {
402 tcg_gen_ext16s_i32(tmp
, add
);
405 scale
= (ext
>> 9) & 3;
407 tcg_gen_shli_i32(tmp
, add
, scale
);
413 /* Handle a base + index + displacement effective addresss.
414 A NULL_QREG base means pc-relative. */
415 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
424 ext
= read_im16(env
, s
);
426 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
429 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
) &&
430 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
435 /* full extension word format */
436 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
439 if ((ext
& 0x30) > 0x10) {
440 /* base displacement */
441 if ((ext
& 0x30) == 0x20) {
442 bd
= (int16_t)read_im16(env
, s
);
444 bd
= read_im32(env
, s
);
449 tmp
= tcg_temp_new();
450 if ((ext
& 0x44) == 0) {
452 add
= gen_addr_index(s
, ext
, tmp
);
456 if ((ext
& 0x80) == 0) {
457 /* base not suppressed */
458 if (IS_NULL_QREG(base
)) {
459 base
= tcg_const_i32(offset
+ bd
);
462 if (!IS_NULL_QREG(add
)) {
463 tcg_gen_add_i32(tmp
, add
, base
);
469 if (!IS_NULL_QREG(add
)) {
471 tcg_gen_addi_i32(tmp
, add
, bd
);
475 add
= tcg_const_i32(bd
);
477 if ((ext
& 3) != 0) {
478 /* memory indirect */
479 base
= gen_load(s
, OS_LONG
, add
, 0);
480 if ((ext
& 0x44) == 4) {
481 add
= gen_addr_index(s
, ext
, tmp
);
482 tcg_gen_add_i32(tmp
, add
, base
);
488 /* outer displacement */
489 if ((ext
& 3) == 2) {
490 od
= (int16_t)read_im16(env
, s
);
492 od
= read_im32(env
, s
);
498 tcg_gen_addi_i32(tmp
, add
, od
);
503 /* brief extension word format */
504 tmp
= tcg_temp_new();
505 add
= gen_addr_index(s
, ext
, tmp
);
506 if (!IS_NULL_QREG(base
)) {
507 tcg_gen_add_i32(tmp
, add
, base
);
509 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
511 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
518 /* Sign or zero extend a value. */
520 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
525 tcg_gen_ext8s_i32(res
, val
);
527 tcg_gen_ext8u_i32(res
, val
);
532 tcg_gen_ext16s_i32(res
, val
);
534 tcg_gen_ext16u_i32(res
, val
);
538 tcg_gen_mov_i32(res
, val
);
541 g_assert_not_reached();
545 /* Evaluate all the CC flags. */
547 static void gen_flush_flags(DisasContext
*s
)
558 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
559 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
560 /* Compute signed overflow for addition. */
563 tcg_gen_sub_i32(t0
, QREG_CC_N
, QREG_CC_V
);
564 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_ADDB
, 1);
565 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
566 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
568 tcg_gen_andc_i32(QREG_CC_V
, t1
, QREG_CC_V
);
575 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
576 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
577 /* Compute signed overflow for subtraction. */
580 tcg_gen_add_i32(t0
, QREG_CC_N
, QREG_CC_V
);
581 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_SUBB
, 1);
582 tcg_gen_xor_i32(t1
, QREG_CC_N
, t0
);
583 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
585 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t1
);
592 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_C
, QREG_CC_N
, QREG_CC_V
);
593 tcg_gen_sub_i32(QREG_CC_Z
, QREG_CC_N
, QREG_CC_V
);
594 gen_ext(QREG_CC_Z
, QREG_CC_Z
, s
->cc_op
- CC_OP_CMPB
, 1);
595 /* Compute signed overflow for subtraction. */
597 tcg_gen_xor_i32(t0
, QREG_CC_Z
, QREG_CC_N
);
598 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, QREG_CC_N
);
599 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t0
);
601 tcg_gen_mov_i32(QREG_CC_N
, QREG_CC_Z
);
605 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
606 tcg_gen_movi_i32(QREG_CC_C
, 0);
607 tcg_gen_movi_i32(QREG_CC_V
, 0);
611 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
616 t0
= tcg_const_i32(s
->cc_op
);
617 gen_helper_flush_flags(cpu_env
, t0
);
623 /* Note that flush_flags also assigned to env->cc_op. */
624 s
->cc_op
= CC_OP_FLAGS
;
627 static inline TCGv
gen_extend(TCGv val
, int opsize
, int sign
)
631 if (opsize
== OS_LONG
) {
634 tmp
= tcg_temp_new();
635 gen_ext(tmp
, val
, opsize
, sign
);
641 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
643 gen_ext(QREG_CC_N
, val
, opsize
, 1);
644 set_cc_op(s
, CC_OP_LOGIC
);
647 static void gen_update_cc_cmp(DisasContext
*s
, TCGv dest
, TCGv src
, int opsize
)
649 tcg_gen_mov_i32(QREG_CC_N
, dest
);
650 tcg_gen_mov_i32(QREG_CC_V
, src
);
651 set_cc_op(s
, CC_OP_CMPB
+ opsize
);
654 static void gen_update_cc_add(TCGv dest
, TCGv src
, int opsize
)
656 gen_ext(QREG_CC_N
, dest
, opsize
, 1);
657 tcg_gen_mov_i32(QREG_CC_V
, src
);
660 static inline int opsize_bytes(int opsize
)
663 case OS_BYTE
: return 1;
664 case OS_WORD
: return 2;
665 case OS_LONG
: return 4;
666 case OS_SINGLE
: return 4;
667 case OS_DOUBLE
: return 8;
668 case OS_EXTENDED
: return 12;
669 case OS_PACKED
: return 12;
671 g_assert_not_reached();
675 static inline int insn_opsize(int insn
)
677 switch ((insn
>> 6) & 3) {
678 case 0: return OS_BYTE
;
679 case 1: return OS_WORD
;
680 case 2: return OS_LONG
;
682 g_assert_not_reached();
686 static inline int ext_opsize(int ext
, int pos
)
688 switch ((ext
>> pos
) & 7) {
689 case 0: return OS_LONG
;
690 case 1: return OS_SINGLE
;
691 case 2: return OS_EXTENDED
;
692 case 3: return OS_PACKED
;
693 case 4: return OS_WORD
;
694 case 5: return OS_DOUBLE
;
695 case 6: return OS_BYTE
;
697 g_assert_not_reached();
701 /* Assign value to a register. If the width is less than the register width
702 only the low part of the register is set. */
703 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
708 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
709 tmp
= tcg_temp_new();
710 tcg_gen_ext8u_i32(tmp
, val
);
711 tcg_gen_or_i32(reg
, reg
, tmp
);
715 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
716 tmp
= tcg_temp_new();
717 tcg_gen_ext16u_i32(tmp
, val
);
718 tcg_gen_or_i32(reg
, reg
, tmp
);
723 tcg_gen_mov_i32(reg
, val
);
726 g_assert_not_reached();
730 /* Generate code for an "effective address". Does not adjust the base
731 register for autoincrement addressing modes. */
732 static TCGv
gen_lea_mode(CPUM68KState
*env
, DisasContext
*s
,
733 int mode
, int reg0
, int opsize
)
741 case 0: /* Data register direct. */
742 case 1: /* Address register direct. */
744 case 3: /* Indirect postincrement. */
745 if (opsize
== OS_UNSIZED
) {
749 case 2: /* Indirect register */
750 return get_areg(s
, reg0
);
751 case 4: /* Indirect predecrememnt. */
752 if (opsize
== OS_UNSIZED
) {
755 reg
= get_areg(s
, reg0
);
756 tmp
= tcg_temp_new();
757 if (reg0
== 7 && opsize
== OS_BYTE
&&
758 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
759 tcg_gen_subi_i32(tmp
, reg
, 2);
761 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
764 case 5: /* Indirect displacement. */
765 reg
= get_areg(s
, reg0
);
766 tmp
= tcg_temp_new();
767 ext
= read_im16(env
, s
);
768 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
770 case 6: /* Indirect index + displacement. */
771 reg
= get_areg(s
, reg0
);
772 return gen_lea_indexed(env
, s
, reg
);
775 case 0: /* Absolute short. */
776 offset
= (int16_t)read_im16(env
, s
);
777 return tcg_const_i32(offset
);
778 case 1: /* Absolute long. */
779 offset
= read_im32(env
, s
);
780 return tcg_const_i32(offset
);
781 case 2: /* pc displacement */
783 offset
+= (int16_t)read_im16(env
, s
);
784 return tcg_const_i32(offset
);
785 case 3: /* pc index+displacement. */
786 return gen_lea_indexed(env
, s
, NULL_QREG
);
787 case 4: /* Immediate. */
792 /* Should never happen. */
796 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
799 int mode
= extract32(insn
, 3, 3);
800 int reg0
= REG(insn
, 0);
801 return gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
804 /* Generate code to load/store a value from/into an EA. If WHAT > 0 this is
805 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
806 ADDRP is non-null for readwrite operands. */
807 static TCGv
gen_ea_mode(CPUM68KState
*env
, DisasContext
*s
, int mode
, int reg0
,
808 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
)
810 TCGv reg
, tmp
, result
;
814 case 0: /* Data register direct. */
815 reg
= cpu_dregs
[reg0
];
816 if (what
== EA_STORE
) {
817 gen_partset_reg(opsize
, reg
, val
);
820 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
822 case 1: /* Address register direct. */
823 reg
= get_areg(s
, reg0
);
824 if (what
== EA_STORE
) {
825 tcg_gen_mov_i32(reg
, val
);
828 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
830 case 2: /* Indirect register */
831 reg
= get_areg(s
, reg0
);
832 return gen_ldst(s
, opsize
, reg
, val
, what
);
833 case 3: /* Indirect postincrement. */
834 reg
= get_areg(s
, reg0
);
835 result
= gen_ldst(s
, opsize
, reg
, val
, what
);
836 if (what
== EA_STORE
|| !addrp
) {
837 TCGv tmp
= tcg_temp_new();
838 if (reg0
== 7 && opsize
== OS_BYTE
&&
839 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
840 tcg_gen_addi_i32(tmp
, reg
, 2);
842 tcg_gen_addi_i32(tmp
, reg
, opsize_bytes(opsize
));
844 delay_set_areg(s
, reg0
, tmp
, true);
847 case 4: /* Indirect predecrememnt. */
848 if (addrp
&& what
== EA_STORE
) {
851 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
852 if (IS_NULL_QREG(tmp
)) {
859 result
= gen_ldst(s
, opsize
, tmp
, val
, what
);
860 if (what
== EA_STORE
|| !addrp
) {
861 delay_set_areg(s
, reg0
, tmp
, false);
864 case 5: /* Indirect displacement. */
865 case 6: /* Indirect index + displacement. */
867 if (addrp
&& what
== EA_STORE
) {
870 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
871 if (IS_NULL_QREG(tmp
)) {
878 return gen_ldst(s
, opsize
, tmp
, val
, what
);
881 case 0: /* Absolute short. */
882 case 1: /* Absolute long. */
883 case 2: /* pc displacement */
884 case 3: /* pc index+displacement. */
886 case 4: /* Immediate. */
887 /* Sign extend values for consistency. */
890 if (what
== EA_LOADS
) {
891 offset
= (int8_t)read_im8(env
, s
);
893 offset
= read_im8(env
, s
);
897 if (what
== EA_LOADS
) {
898 offset
= (int16_t)read_im16(env
, s
);
900 offset
= read_im16(env
, s
);
904 offset
= read_im32(env
, s
);
907 g_assert_not_reached();
909 return tcg_const_i32(offset
);
914 /* Should never happen. */
918 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
919 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
)
921 int mode
= extract32(insn
, 3, 3);
922 int reg0
= REG(insn
, 0);
923 return gen_ea_mode(env
, s
, mode
, reg0
, opsize
, val
, addrp
, what
);
926 static TCGv_ptr
gen_fp_ptr(int freg
)
928 TCGv_ptr fp
= tcg_temp_new_ptr();
929 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fregs
[freg
]));
933 static TCGv_ptr
gen_fp_result_ptr(void)
935 TCGv_ptr fp
= tcg_temp_new_ptr();
936 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fp_result
));
940 static void gen_fp_move(TCGv_ptr dest
, TCGv_ptr src
)
945 t32
= tcg_temp_new();
946 tcg_gen_ld16u_i32(t32
, src
, offsetof(FPReg
, l
.upper
));
947 tcg_gen_st16_i32(t32
, dest
, offsetof(FPReg
, l
.upper
));
950 t64
= tcg_temp_new_i64();
951 tcg_gen_ld_i64(t64
, src
, offsetof(FPReg
, l
.lower
));
952 tcg_gen_st_i64(t64
, dest
, offsetof(FPReg
, l
.lower
));
953 tcg_temp_free_i64(t64
);
956 static void gen_load_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
)
960 int index
= IS_USER(s
);
962 t64
= tcg_temp_new_i64();
963 tmp
= tcg_temp_new();
966 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
967 gen_helper_exts32(cpu_env
, fp
, tmp
);
970 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
971 gen_helper_exts32(cpu_env
, fp
, tmp
);
974 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
975 gen_helper_exts32(cpu_env
, fp
, tmp
);
978 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
979 gen_helper_extf32(cpu_env
, fp
, tmp
);
982 tcg_gen_qemu_ld64(t64
, addr
, index
);
983 gen_helper_extf64(cpu_env
, fp
, t64
);
984 tcg_temp_free_i64(t64
);
987 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
988 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
991 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
992 tcg_gen_shri_i32(tmp
, tmp
, 16);
993 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
994 tcg_gen_addi_i32(tmp
, addr
, 4);
995 tcg_gen_qemu_ld64(t64
, tmp
, index
);
996 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
999 /* unimplemented data type on 68040/ColdFire
1000 * FIXME if needed for another FPU
1002 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1005 g_assert_not_reached();
1008 tcg_temp_free_i64(t64
);
1009 gen_throws_exception
= gen_last_qop
;
1012 static void gen_store_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
)
1016 int index
= IS_USER(s
);
1018 t64
= tcg_temp_new_i64();
1019 tmp
= tcg_temp_new();
1022 gen_helper_reds32(tmp
, cpu_env
, fp
);
1023 tcg_gen_qemu_st8(tmp
, addr
, index
);
1026 gen_helper_reds32(tmp
, cpu_env
, fp
);
1027 tcg_gen_qemu_st16(tmp
, addr
, index
);
1030 gen_helper_reds32(tmp
, cpu_env
, fp
);
1031 tcg_gen_qemu_st32(tmp
, addr
, index
);
1034 gen_helper_redf32(tmp
, cpu_env
, fp
);
1035 tcg_gen_qemu_st32(tmp
, addr
, index
);
1038 gen_helper_redf64(t64
, cpu_env
, fp
);
1039 tcg_gen_qemu_st64(t64
, addr
, index
);
1042 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1043 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1046 tcg_gen_ld16u_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1047 tcg_gen_shli_i32(tmp
, tmp
, 16);
1048 tcg_gen_qemu_st32(tmp
, addr
, index
);
1049 tcg_gen_addi_i32(tmp
, addr
, 4);
1050 tcg_gen_ld_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1051 tcg_gen_qemu_st64(t64
, tmp
, index
);
1054 /* unimplemented data type on 68040/ColdFire
1055 * FIXME if needed for another FPU
1057 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1060 g_assert_not_reached();
1063 tcg_temp_free_i64(t64
);
1064 gen_throws_exception
= gen_last_qop
;
1067 static void gen_ldst_fp(DisasContext
*s
, int opsize
, TCGv addr
,
1068 TCGv_ptr fp
, ea_what what
)
1070 if (what
== EA_STORE
) {
1071 gen_store_fp(s
, opsize
, addr
, fp
);
1073 gen_load_fp(s
, opsize
, addr
, fp
);
1077 static int gen_ea_mode_fp(CPUM68KState
*env
, DisasContext
*s
, int mode
,
1078 int reg0
, int opsize
, TCGv_ptr fp
, ea_what what
)
1080 TCGv reg
, addr
, tmp
;
1084 case 0: /* Data register direct. */
1085 reg
= cpu_dregs
[reg0
];
1086 if (what
== EA_STORE
) {
1091 gen_helper_reds32(reg
, cpu_env
, fp
);
1094 gen_helper_redf32(reg
, cpu_env
, fp
);
1097 g_assert_not_reached();
1100 tmp
= tcg_temp_new();
1103 tcg_gen_ext8s_i32(tmp
, reg
);
1104 gen_helper_exts32(cpu_env
, fp
, tmp
);
1107 tcg_gen_ext16s_i32(tmp
, reg
);
1108 gen_helper_exts32(cpu_env
, fp
, tmp
);
1111 gen_helper_exts32(cpu_env
, fp
, reg
);
1114 gen_helper_extf32(cpu_env
, fp
, reg
);
1117 g_assert_not_reached();
1122 case 1: /* Address register direct. */
1124 case 2: /* Indirect register */
1125 addr
= get_areg(s
, reg0
);
1126 gen_ldst_fp(s
, opsize
, addr
, fp
, what
);
1128 case 3: /* Indirect postincrement. */
1129 addr
= cpu_aregs
[reg0
];
1130 gen_ldst_fp(s
, opsize
, addr
, fp
, what
);
1131 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(opsize
));
1133 case 4: /* Indirect predecrememnt. */
1134 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1135 if (IS_NULL_QREG(addr
)) {
1138 gen_ldst_fp(s
, opsize
, addr
, fp
, what
);
1139 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
1141 case 5: /* Indirect displacement. */
1142 case 6: /* Indirect index + displacement. */
1144 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1145 if (IS_NULL_QREG(addr
)) {
1148 gen_ldst_fp(s
, opsize
, addr
, fp
, what
);
1152 case 0: /* Absolute short. */
1153 case 1: /* Absolute long. */
1154 case 2: /* pc displacement */
1155 case 3: /* pc index+displacement. */
1157 case 4: /* Immediate. */
1158 if (what
== EA_STORE
) {
1163 tmp
= tcg_const_i32((int8_t)read_im8(env
, s
));
1164 gen_helper_exts32(cpu_env
, fp
, tmp
);
1168 tmp
= tcg_const_i32((int16_t)read_im16(env
, s
));
1169 gen_helper_exts32(cpu_env
, fp
, tmp
);
1173 tmp
= tcg_const_i32(read_im32(env
, s
));
1174 gen_helper_exts32(cpu_env
, fp
, tmp
);
1178 tmp
= tcg_const_i32(read_im32(env
, s
));
1179 gen_helper_extf32(cpu_env
, fp
, tmp
);
1183 t64
= tcg_const_i64(read_im64(env
, s
));
1184 gen_helper_extf64(cpu_env
, fp
, t64
);
1185 tcg_temp_free_i64(t64
);
1188 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1189 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1192 tmp
= tcg_const_i32(read_im32(env
, s
) >> 16);
1193 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1195 t64
= tcg_const_i64(read_im64(env
, s
));
1196 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1197 tcg_temp_free_i64(t64
);
1200 /* unimplemented data type on 68040/ColdFire
1201 * FIXME if needed for another FPU
1203 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1206 g_assert_not_reached();
1216 static int gen_ea_fp(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1217 int opsize
, TCGv_ptr fp
, ea_what what
)
1219 int mode
= extract32(insn
, 3, 3);
1220 int reg0
= REG(insn
, 0);
1221 return gen_ea_mode_fp(env
, s
, mode
, reg0
, opsize
, fp
, what
);
1232 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
1238 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1239 if (op
== CC_OP_CMPB
|| op
== CC_OP_CMPW
|| op
== CC_OP_CMPL
) {
1246 tcond
= TCG_COND_LEU
;
1250 tcond
= TCG_COND_LTU
;
1254 tcond
= TCG_COND_EQ
;
1259 c
->v2
= tcg_const_i32(0);
1260 c
->v1
= tmp
= tcg_temp_new();
1261 tcg_gen_sub_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1262 gen_ext(tmp
, tmp
, op
- CC_OP_CMPB
, 1);
1266 tcond
= TCG_COND_LT
;
1270 tcond
= TCG_COND_LE
;
1277 c
->v2
= tcg_const_i32(0);
1283 tcond
= TCG_COND_NEVER
;
1285 case 14: /* GT (!(Z || (N ^ V))) */
1286 case 15: /* LE (Z || (N ^ V)) */
1287 /* Logic operations clear V, which simplifies LE to (Z || N),
1288 and since Z and N are co-located, this becomes a normal
1290 if (op
== CC_OP_LOGIC
) {
1292 tcond
= TCG_COND_LE
;
1296 case 12: /* GE (!(N ^ V)) */
1297 case 13: /* LT (N ^ V) */
1298 /* Logic operations clear V, which simplifies this to N. */
1299 if (op
!= CC_OP_LOGIC
) {
1303 case 10: /* PL (!N) */
1304 case 11: /* MI (N) */
1305 /* Several cases represent N normally. */
1306 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1307 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1308 op
== CC_OP_LOGIC
) {
1310 tcond
= TCG_COND_LT
;
1314 case 6: /* NE (!Z) */
1315 case 7: /* EQ (Z) */
1316 /* Some cases fold Z into N. */
1317 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1318 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1319 op
== CC_OP_LOGIC
) {
1320 tcond
= TCG_COND_EQ
;
1325 case 4: /* CC (!C) */
1326 case 5: /* CS (C) */
1327 /* Some cases fold C into X. */
1328 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1329 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
) {
1330 tcond
= TCG_COND_NE
;
1335 case 8: /* VC (!V) */
1336 case 9: /* VS (V) */
1337 /* Logic operations clear V and C. */
1338 if (op
== CC_OP_LOGIC
) {
1339 tcond
= TCG_COND_NEVER
;
1346 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1353 /* Invalid, or handled above. */
1355 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1356 case 3: /* LS (C || Z) */
1357 c
->v1
= tmp
= tcg_temp_new();
1359 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1360 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
1361 tcond
= TCG_COND_NE
;
1363 case 4: /* CC (!C) */
1364 case 5: /* CS (C) */
1366 tcond
= TCG_COND_NE
;
1368 case 6: /* NE (!Z) */
1369 case 7: /* EQ (Z) */
1371 tcond
= TCG_COND_EQ
;
1373 case 8: /* VC (!V) */
1374 case 9: /* VS (V) */
1376 tcond
= TCG_COND_LT
;
1378 case 10: /* PL (!N) */
1379 case 11: /* MI (N) */
1381 tcond
= TCG_COND_LT
;
1383 case 12: /* GE (!(N ^ V)) */
1384 case 13: /* LT (N ^ V) */
1385 c
->v1
= tmp
= tcg_temp_new();
1387 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1388 tcond
= TCG_COND_LT
;
1390 case 14: /* GT (!(Z || (N ^ V))) */
1391 case 15: /* LE (Z || (N ^ V)) */
1392 c
->v1
= tmp
= tcg_temp_new();
1394 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1395 tcg_gen_neg_i32(tmp
, tmp
);
1396 tmp2
= tcg_temp_new();
1397 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
1398 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1399 tcg_temp_free(tmp2
);
1400 tcond
= TCG_COND_LT
;
1405 if ((cond
& 1) == 0) {
1406 tcond
= tcg_invert_cond(tcond
);
1411 static void free_cond(DisasCompare
*c
)
1414 tcg_temp_free(c
->v1
);
1417 tcg_temp_free(c
->v2
);
1421 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
1425 gen_cc_cond(&c
, s
, cond
);
1427 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
1431 /* Force a TB lookup after an instruction that changes the CPU state. */
1432 static void gen_lookup_tb(DisasContext
*s
)
1435 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
1436 s
->is_jmp
= DISAS_UPDATE
;
1439 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1440 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1441 op_sign ? EA_LOADS : EA_LOADU); \
1442 if (IS_NULL_QREG(result)) { \
1443 gen_addr_fault(s); \
1448 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1449 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
1450 if (IS_NULL_QREG(ea_result)) { \
1451 gen_addr_fault(s); \
1456 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
1458 #ifndef CONFIG_USER_ONLY
1459 return (s
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
1460 (s
->insn_pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
1466 /* Generate a jump to an immediate address. */
1467 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
1469 if (unlikely(s
->singlestep_enabled
)) {
1470 gen_exception(s
, dest
, EXCP_DEBUG
);
1471 } else if (use_goto_tb(s
, dest
)) {
1473 tcg_gen_movi_i32(QREG_PC
, dest
);
1474 tcg_gen_exit_tb((uintptr_t)s
->tb
+ n
);
1476 gen_jmp_im(s
, dest
);
1479 s
->is_jmp
= DISAS_TB_JUMP
;
1488 cond
= (insn
>> 8) & 0xf;
1489 gen_cc_cond(&c
, s
, cond
);
1491 tmp
= tcg_temp_new();
1492 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
1495 tcg_gen_neg_i32(tmp
, tmp
);
1496 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
1508 reg
= DREG(insn
, 0);
1510 offset
= (int16_t)read_im16(env
, s
);
1511 l1
= gen_new_label();
1512 gen_jmpcc(s
, (insn
>> 8) & 0xf, l1
);
1514 tmp
= tcg_temp_new();
1515 tcg_gen_ext16s_i32(tmp
, reg
);
1516 tcg_gen_addi_i32(tmp
, tmp
, -1);
1517 gen_partset_reg(OS_WORD
, reg
, tmp
);
1518 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, -1, l1
);
1519 gen_jmp_tb(s
, 1, base
+ offset
);
1521 gen_jmp_tb(s
, 0, s
->pc
);
1524 DISAS_INSN(undef_mac
)
1526 gen_exception(s
, s
->pc
- 2, EXCP_LINEA
);
1529 DISAS_INSN(undef_fpu
)
1531 gen_exception(s
, s
->pc
- 2, EXCP_LINEF
);
1536 /* ??? This is both instructions that are as yet unimplemented
1537 for the 680x0 series, as well as those that are implemented
1538 but actually illegal for CPU32 or pre-68020. */
1539 qemu_log_mask(LOG_UNIMP
, "Illegal instruction: %04x @ %08x",
1541 gen_exception(s
, s
->pc
- 2, EXCP_UNSUPPORTED
);
1551 sign
= (insn
& 0x100) != 0;
1552 reg
= DREG(insn
, 9);
1553 tmp
= tcg_temp_new();
1555 tcg_gen_ext16s_i32(tmp
, reg
);
1557 tcg_gen_ext16u_i32(tmp
, reg
);
1558 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1559 tcg_gen_mul_i32(tmp
, tmp
, src
);
1560 tcg_gen_mov_i32(reg
, tmp
);
1561 gen_logic_cc(s
, tmp
, OS_LONG
);
1571 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1573 sign
= (insn
& 0x100) != 0;
1575 /* dest.l / src.w */
1577 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1578 destr
= tcg_const_i32(REG(insn
, 9));
1580 gen_helper_divsw(cpu_env
, destr
, src
);
1582 gen_helper_divuw(cpu_env
, destr
, src
);
1584 tcg_temp_free(destr
);
1586 set_cc_op(s
, CC_OP_FLAGS
);
1595 ext
= read_im16(env
, s
);
1597 sign
= (ext
& 0x0800) != 0;
1600 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
1601 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
1605 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1607 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1608 num
= tcg_const_i32(REG(ext
, 12));
1609 reg
= tcg_const_i32(REG(ext
, 0));
1611 gen_helper_divsll(cpu_env
, num
, reg
, den
);
1613 gen_helper_divull(cpu_env
, num
, reg
, den
);
1617 set_cc_op(s
, CC_OP_FLAGS
);
1621 /* divX.l <EA>, Dq 32/32 -> 32q */
1622 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1624 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1625 num
= tcg_const_i32(REG(ext
, 12));
1626 reg
= tcg_const_i32(REG(ext
, 0));
1628 gen_helper_divsl(cpu_env
, num
, reg
, den
);
1630 gen_helper_divul(cpu_env
, num
, reg
, den
);
1635 set_cc_op(s
, CC_OP_FLAGS
);
1638 static void bcd_add(TCGv dest
, TCGv src
)
1642 /* dest10 = dest10 + src10 + X
1646 * t3 = t2 + dest + X
1650 * t7 = (t6 >> 2) | (t6 >> 3)
1654 /* t1 = (src + 0x066) + dest + X
1655 * = result with some possible exceding 0x6
1658 t0
= tcg_const_i32(0x066);
1659 tcg_gen_add_i32(t0
, t0
, src
);
1661 t1
= tcg_temp_new();
1662 tcg_gen_add_i32(t1
, t0
, dest
);
1663 tcg_gen_add_i32(t1
, t1
, QREG_CC_X
);
1665 /* we will remove exceding 0x6 where there is no carry */
1667 /* t0 = (src + 0x0066) ^ dest
1668 * = t1 without carries
1671 tcg_gen_xor_i32(t0
, t0
, dest
);
1673 /* extract the carries
1675 * = only the carries
1678 tcg_gen_xor_i32(t0
, t0
, t1
);
1680 /* generate 0x1 where there is no carry
1681 * and for each 0x10, generate a 0x6
1684 tcg_gen_shri_i32(t0
, t0
, 3);
1685 tcg_gen_not_i32(t0
, t0
);
1686 tcg_gen_andi_i32(t0
, t0
, 0x22);
1687 tcg_gen_add_i32(dest
, t0
, t0
);
1688 tcg_gen_add_i32(dest
, dest
, t0
);
1691 /* remove the exceding 0x6
1692 * for digits that have not generated a carry
1695 tcg_gen_sub_i32(dest
, t1
, dest
);
1699 static void bcd_sub(TCGv dest
, TCGv src
)
1703 /* dest10 = dest10 - src10 - X
1704 * = bcd_add(dest + 1 - X, 0x199 - src)
1707 /* t0 = 0x066 + (0x199 - src) */
1709 t0
= tcg_temp_new();
1710 tcg_gen_subfi_i32(t0
, 0x1ff, src
);
1712 /* t1 = t0 + dest + 1 - X*/
1714 t1
= tcg_temp_new();
1715 tcg_gen_add_i32(t1
, t0
, dest
);
1716 tcg_gen_addi_i32(t1
, t1
, 1);
1717 tcg_gen_sub_i32(t1
, t1
, QREG_CC_X
);
1719 /* t2 = t0 ^ dest */
1721 t2
= tcg_temp_new();
1722 tcg_gen_xor_i32(t2
, t0
, dest
);
1726 tcg_gen_xor_i32(t0
, t1
, t2
);
1729 * t0 = (t2 >> 2) | (t2 >> 3)
1731 * to fit on 8bit operands, changed in:
1733 * t2 = ~(t0 >> 3) & 0x22
1738 tcg_gen_shri_i32(t2
, t0
, 3);
1739 tcg_gen_not_i32(t2
, t2
);
1740 tcg_gen_andi_i32(t2
, t2
, 0x22);
1741 tcg_gen_add_i32(t0
, t2
, t2
);
1742 tcg_gen_add_i32(t0
, t0
, t2
);
1745 /* return t1 - t0 */
1747 tcg_gen_sub_i32(dest
, t1
, t0
);
1752 static void bcd_flags(TCGv val
)
1754 tcg_gen_andi_i32(QREG_CC_C
, val
, 0x0ff);
1755 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_C
);
1757 tcg_gen_extract_i32(QREG_CC_C
, val
, 8, 1);
1759 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
1762 DISAS_INSN(abcd_reg
)
1767 gen_flush_flags(s
); /* !Z is sticky */
1769 src
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
1770 dest
= gen_extend(DREG(insn
, 9), OS_BYTE
, 0);
1772 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1777 DISAS_INSN(abcd_mem
)
1779 TCGv src
, dest
, addr
;
1781 gen_flush_flags(s
); /* !Z is sticky */
1783 /* Indirect pre-decrement load (mode 4) */
1785 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1786 NULL_QREG
, NULL
, EA_LOADU
);
1787 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1788 NULL_QREG
, &addr
, EA_LOADU
);
1792 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
, EA_STORE
);
1797 DISAS_INSN(sbcd_reg
)
1801 gen_flush_flags(s
); /* !Z is sticky */
1803 src
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
1804 dest
= gen_extend(DREG(insn
, 9), OS_BYTE
, 0);
1808 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1813 DISAS_INSN(sbcd_mem
)
1815 TCGv src
, dest
, addr
;
1817 gen_flush_flags(s
); /* !Z is sticky */
1819 /* Indirect pre-decrement load (mode 4) */
1821 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1822 NULL_QREG
, NULL
, EA_LOADU
);
1823 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1824 NULL_QREG
, &addr
, EA_LOADU
);
1828 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
, EA_STORE
);
1838 gen_flush_flags(s
); /* !Z is sticky */
1840 SRC_EA(env
, src
, OS_BYTE
, 0, &addr
);
1842 dest
= tcg_const_i32(0);
1845 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1849 tcg_temp_free(dest
);
1862 add
= (insn
& 0x4000) != 0;
1863 opsize
= insn_opsize(insn
);
1864 reg
= gen_extend(DREG(insn
, 9), opsize
, 1);
1865 dest
= tcg_temp_new();
1867 SRC_EA(env
, tmp
, opsize
, 1, &addr
);
1871 SRC_EA(env
, src
, opsize
, 1, NULL
);
1874 tcg_gen_add_i32(dest
, tmp
, src
);
1875 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1876 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
1878 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1879 tcg_gen_sub_i32(dest
, tmp
, src
);
1880 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
1882 gen_update_cc_add(dest
, src
, opsize
);
1884 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1886 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
1888 tcg_temp_free(dest
);
1891 /* Reverse the order of the bits in REG. */
1895 reg
= DREG(insn
, 0);
1896 gen_helper_bitrev(reg
, reg
);
1899 DISAS_INSN(bitop_reg
)
1909 if ((insn
& 0x38) != 0)
1913 op
= (insn
>> 6) & 3;
1914 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1917 src2
= tcg_temp_new();
1918 if (opsize
== OS_BYTE
)
1919 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 7);
1921 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 31);
1923 tmp
= tcg_const_i32(1);
1924 tcg_gen_shl_i32(tmp
, tmp
, src2
);
1925 tcg_temp_free(src2
);
1927 tcg_gen_and_i32(QREG_CC_Z
, src1
, tmp
);
1929 dest
= tcg_temp_new();
1932 tcg_gen_xor_i32(dest
, src1
, tmp
);
1935 tcg_gen_andc_i32(dest
, src1
, tmp
);
1938 tcg_gen_or_i32(dest
, src1
, tmp
);
1945 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1947 tcg_temp_free(dest
);
1953 reg
= DREG(insn
, 0);
1955 gen_helper_sats(reg
, reg
, QREG_CC_V
);
1956 gen_logic_cc(s
, reg
, OS_LONG
);
1959 static void gen_push(DisasContext
*s
, TCGv val
)
1963 tmp
= tcg_temp_new();
1964 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1965 gen_store(s
, OS_LONG
, tmp
, val
);
1966 tcg_gen_mov_i32(QREG_SP
, tmp
);
1970 static TCGv
mreg(int reg
)
1974 return cpu_dregs
[reg
];
1977 return cpu_aregs
[reg
& 7];
1982 TCGv addr
, incr
, tmp
, r
[16];
1983 int is_load
= (insn
& 0x0400) != 0;
1984 int opsize
= (insn
& 0x40) != 0 ? OS_LONG
: OS_WORD
;
1985 uint16_t mask
= read_im16(env
, s
);
1986 int mode
= extract32(insn
, 3, 3);
1987 int reg0
= REG(insn
, 0);
1990 tmp
= cpu_aregs
[reg0
];
1993 case 0: /* data register direct */
1994 case 1: /* addr register direct */
1999 case 2: /* indirect */
2002 case 3: /* indirect post-increment */
2004 /* post-increment is not allowed */
2009 case 4: /* indirect pre-decrement */
2011 /* pre-decrement is not allowed */
2014 /* We want a bare copy of the address reg, without any pre-decrement
2015 adjustment, as gen_lea would provide. */
2019 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
2020 if (IS_NULL_QREG(tmp
)) {
2026 addr
= tcg_temp_new();
2027 tcg_gen_mov_i32(addr
, tmp
);
2028 incr
= tcg_const_i32(opsize_bytes(opsize
));
2031 /* memory to register */
2032 for (i
= 0; i
< 16; i
++) {
2033 if (mask
& (1 << i
)) {
2034 r
[i
] = gen_load(s
, opsize
, addr
, 1);
2035 tcg_gen_add_i32(addr
, addr
, incr
);
2038 for (i
= 0; i
< 16; i
++) {
2039 if (mask
& (1 << i
)) {
2040 tcg_gen_mov_i32(mreg(i
), r
[i
]);
2041 tcg_temp_free(r
[i
]);
2045 /* post-increment: movem (An)+,X */
2046 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2049 /* register to memory */
2051 /* pre-decrement: movem X,-(An) */
2052 for (i
= 15; i
>= 0; i
--) {
2053 if ((mask
<< i
) & 0x8000) {
2054 tcg_gen_sub_i32(addr
, addr
, incr
);
2055 if (reg0
+ 8 == i
&&
2056 m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
)) {
2057 /* M68020+: if the addressing register is the
2058 * register moved to memory, the value written
2059 * is the initial value decremented by the size of
2060 * the operation, regardless of how many actual
2061 * stores have been performed until this point.
2062 * M68000/M68010: the value is the initial value.
2064 tmp
= tcg_temp_new();
2065 tcg_gen_sub_i32(tmp
, cpu_aregs
[reg0
], incr
);
2066 gen_store(s
, opsize
, addr
, tmp
);
2069 gen_store(s
, opsize
, addr
, mreg(i
));
2073 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2075 for (i
= 0; i
< 16; i
++) {
2076 if (mask
& (1 << i
)) {
2077 gen_store(s
, opsize
, addr
, mreg(i
));
2078 tcg_gen_add_i32(addr
, addr
, incr
);
2084 tcg_temp_free(incr
);
2085 tcg_temp_free(addr
);
2088 DISAS_INSN(bitop_im
)
2098 if ((insn
& 0x38) != 0)
2102 op
= (insn
>> 6) & 3;
2104 bitnum
= read_im16(env
, s
);
2105 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2106 if (bitnum
& 0xfe00) {
2107 disas_undef(env
, s
, insn
);
2111 if (bitnum
& 0xff00) {
2112 disas_undef(env
, s
, insn
);
2117 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
2120 if (opsize
== OS_BYTE
)
2126 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
2129 tmp
= tcg_temp_new();
2132 tcg_gen_xori_i32(tmp
, src1
, mask
);
2135 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
2138 tcg_gen_ori_i32(tmp
, src1
, mask
);
2143 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
2148 DISAS_INSN(arith_im
)
2157 op
= (insn
>> 9) & 7;
2158 opsize
= insn_opsize(insn
);
2161 im
= tcg_const_i32((int8_t)read_im8(env
, s
));
2164 im
= tcg_const_i32((int16_t)read_im16(env
, s
));
2167 im
= tcg_const_i32(read_im32(env
, s
));
2172 SRC_EA(env
, src1
, opsize
, 1, (op
== 6) ? NULL
: &addr
);
2173 dest
= tcg_temp_new();
2176 tcg_gen_or_i32(dest
, src1
, im
);
2177 gen_logic_cc(s
, dest
, opsize
);
2180 tcg_gen_and_i32(dest
, src1
, im
);
2181 gen_logic_cc(s
, dest
, opsize
);
2184 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, src1
, im
);
2185 tcg_gen_sub_i32(dest
, src1
, im
);
2186 gen_update_cc_add(dest
, im
, opsize
);
2187 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2190 tcg_gen_add_i32(dest
, src1
, im
);
2191 gen_update_cc_add(dest
, im
, opsize
);
2192 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
2193 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2196 tcg_gen_xor_i32(dest
, src1
, im
);
2197 gen_logic_cc(s
, dest
, opsize
);
2200 gen_update_cc_cmp(s
, src1
, im
, opsize
);
2207 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2209 tcg_temp_free(dest
);
2221 switch ((insn
>> 9) & 3) {
2235 g_assert_not_reached();
2238 ext
= read_im16(env
, s
);
2240 /* cas Dc,Du,<EA> */
2242 addr
= gen_lea(env
, s
, insn
, opsize
);
2243 if (IS_NULL_QREG(addr
)) {
2248 cmp
= gen_extend(DREG(ext
, 0), opsize
, 1);
2250 /* if <EA> == Dc then
2252 * Dc = <EA> (because <EA> == Dc)
2257 load
= tcg_temp_new();
2258 tcg_gen_atomic_cmpxchg_i32(load
, addr
, cmp
, DREG(ext
, 6),
2260 /* update flags before setting cmp to load */
2261 gen_update_cc_cmp(s
, load
, cmp
, opsize
);
2262 gen_partset_reg(opsize
, DREG(ext
, 0), load
);
2264 tcg_temp_free(load
);
2266 switch (extract32(insn
, 3, 3)) {
2267 case 3: /* Indirect postincrement. */
2268 tcg_gen_addi_i32(AREG(insn
, 0), addr
, opsize_bytes(opsize
));
2270 case 4: /* Indirect predecrememnt. */
2271 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2278 uint16_t ext1
, ext2
;
2282 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2284 ext1
= read_im16(env
, s
);
2286 if (ext1
& 0x8000) {
2287 /* Address Register */
2288 addr1
= AREG(ext1
, 12);
2291 addr1
= DREG(ext1
, 12);
2294 ext2
= read_im16(env
, s
);
2295 if (ext2
& 0x8000) {
2296 /* Address Register */
2297 addr2
= AREG(ext2
, 12);
2300 addr2
= DREG(ext2
, 12);
2303 /* if (R1) == Dc1 && (R2) == Dc2 then
2311 regs
= tcg_const_i32(REG(ext2
, 6) |
2312 (REG(ext1
, 6) << 3) |
2313 (REG(ext2
, 0) << 6) |
2314 (REG(ext1
, 0) << 9));
2315 if (tb_cflags(s
->tb
) & CF_PARALLEL
) {
2316 gen_helper_exit_atomic(cpu_env
);
2318 gen_helper_cas2w(cpu_env
, regs
, addr1
, addr2
);
2320 tcg_temp_free(regs
);
2322 /* Note that cas2w also assigned to env->cc_op. */
2323 s
->cc_op
= CC_OP_CMPW
;
2324 s
->cc_op_synced
= 1;
2329 uint16_t ext1
, ext2
;
2330 TCGv addr1
, addr2
, regs
;
2332 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2334 ext1
= read_im16(env
, s
);
2336 if (ext1
& 0x8000) {
2337 /* Address Register */
2338 addr1
= AREG(ext1
, 12);
2341 addr1
= DREG(ext1
, 12);
2344 ext2
= read_im16(env
, s
);
2345 if (ext2
& 0x8000) {
2346 /* Address Register */
2347 addr2
= AREG(ext2
, 12);
2350 addr2
= DREG(ext2
, 12);
2353 /* if (R1) == Dc1 && (R2) == Dc2 then
2361 regs
= tcg_const_i32(REG(ext2
, 6) |
2362 (REG(ext1
, 6) << 3) |
2363 (REG(ext2
, 0) << 6) |
2364 (REG(ext1
, 0) << 9));
2365 if (tb_cflags(s
->tb
) & CF_PARALLEL
) {
2366 gen_helper_cas2l_parallel(cpu_env
, regs
, addr1
, addr2
);
2368 gen_helper_cas2l(cpu_env
, regs
, addr1
, addr2
);
2370 tcg_temp_free(regs
);
2372 /* Note that cas2l also assigned to env->cc_op. */
2373 s
->cc_op
= CC_OP_CMPL
;
2374 s
->cc_op_synced
= 1;
2381 reg
= DREG(insn
, 0);
2382 tcg_gen_bswap32_i32(reg
, reg
);
2392 switch (insn
>> 12) {
2393 case 1: /* move.b */
2396 case 2: /* move.l */
2399 case 3: /* move.w */
2405 SRC_EA(env
, src
, opsize
, 1, NULL
);
2406 op
= (insn
>> 6) & 7;
2409 /* The value will already have been sign extended. */
2410 dest
= AREG(insn
, 9);
2411 tcg_gen_mov_i32(dest
, src
);
2415 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
2416 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
2417 /* This will be correct because loads sign extend. */
2418 gen_logic_cc(s
, src
, opsize
);
2429 opsize
= insn_opsize(insn
);
2430 SRC_EA(env
, src
, opsize
, 1, &addr
);
2432 gen_flush_flags(s
); /* compute old Z */
2434 /* Perform substract with borrow.
2435 * (X, N) = -(src + X);
2438 z
= tcg_const_i32(0);
2439 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, z
, QREG_CC_X
, z
);
2440 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, z
, z
, QREG_CC_N
, QREG_CC_X
);
2442 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2444 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2446 /* Compute signed-overflow for negation. The normal formula for
2447 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2448 * this simplies to res & src.
2451 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_N
, src
);
2453 /* Copy the rest of the results into place. */
2454 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2455 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2457 set_cc_op(s
, CC_OP_FLAGS
);
2459 /* result is in QREG_CC_N */
2461 DEST_EA(env
, insn
, opsize
, QREG_CC_N
, &addr
);
2469 reg
= AREG(insn
, 9);
2470 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2471 if (IS_NULL_QREG(tmp
)) {
2475 tcg_gen_mov_i32(reg
, tmp
);
2483 zero
= tcg_const_i32(0);
2485 opsize
= insn_opsize(insn
);
2486 DEST_EA(env
, insn
, opsize
, zero
, NULL
);
2487 gen_logic_cc(s
, zero
, opsize
);
2488 tcg_temp_free(zero
);
2491 static TCGv
gen_get_ccr(DisasContext
*s
)
2497 dest
= tcg_temp_new();
2498 gen_helper_get_ccr(dest
, cpu_env
);
2502 DISAS_INSN(move_from_ccr
)
2506 ccr
= gen_get_ccr(s
);
2507 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
2517 opsize
= insn_opsize(insn
);
2518 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2519 dest
= tcg_temp_new();
2520 tcg_gen_neg_i32(dest
, src1
);
2521 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2522 gen_update_cc_add(dest
, src1
, opsize
);
2523 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, dest
, 0);
2524 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2525 tcg_temp_free(dest
);
2528 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
2531 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
2532 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
2533 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
2534 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
2535 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
2537 gen_helper_set_sr(cpu_env
, tcg_const_i32(val
));
2539 set_cc_op(s
, CC_OP_FLAGS
);
2542 static void gen_set_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
2545 if ((insn
& 0x38) == 0) {
2547 gen_helper_set_ccr(cpu_env
, DREG(insn
, 0));
2549 gen_helper_set_sr(cpu_env
, DREG(insn
, 0));
2551 set_cc_op(s
, CC_OP_FLAGS
);
2552 } else if ((insn
& 0x3f) == 0x3c) {
2554 val
= read_im16(env
, s
);
2555 gen_set_sr_im(s
, val
, ccr_only
);
2557 disas_undef(env
, s
, insn
);
2562 DISAS_INSN(move_to_ccr
)
2564 gen_set_sr(env
, s
, insn
, 1);
2574 opsize
= insn_opsize(insn
);
2575 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2576 dest
= tcg_temp_new();
2577 tcg_gen_not_i32(dest
, src1
);
2578 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2579 gen_logic_cc(s
, dest
, opsize
);
2588 src1
= tcg_temp_new();
2589 src2
= tcg_temp_new();
2590 reg
= DREG(insn
, 0);
2591 tcg_gen_shli_i32(src1
, reg
, 16);
2592 tcg_gen_shri_i32(src2
, reg
, 16);
2593 tcg_gen_or_i32(reg
, src1
, src2
);
2594 tcg_temp_free(src2
);
2595 tcg_temp_free(src1
);
2596 gen_logic_cc(s
, reg
, OS_LONG
);
2601 gen_exception(s
, s
->pc
- 2, EXCP_DEBUG
);
2608 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2609 if (IS_NULL_QREG(tmp
)) {
2622 reg
= DREG(insn
, 0);
2623 op
= (insn
>> 6) & 7;
2624 tmp
= tcg_temp_new();
2626 tcg_gen_ext16s_i32(tmp
, reg
);
2628 tcg_gen_ext8s_i32(tmp
, reg
);
2630 gen_partset_reg(OS_WORD
, reg
, tmp
);
2632 tcg_gen_mov_i32(reg
, tmp
);
2633 gen_logic_cc(s
, tmp
, OS_LONG
);
2642 opsize
= insn_opsize(insn
);
2643 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
2644 gen_logic_cc(s
, tmp
, opsize
);
2649 /* Implemented as a NOP. */
2654 gen_exception(s
, s
->pc
- 2, EXCP_ILLEGAL
);
2657 /* ??? This should be atomic. */
2664 dest
= tcg_temp_new();
2665 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
2666 gen_logic_cc(s
, src1
, OS_BYTE
);
2667 tcg_gen_ori_i32(dest
, src1
, 0x80);
2668 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
2669 tcg_temp_free(dest
);
2678 ext
= read_im16(env
, s
);
2683 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
2684 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
2688 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2691 tcg_gen_muls2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2693 tcg_gen_mulu2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2695 /* if Dl == Dh, 68040 returns low word */
2696 tcg_gen_mov_i32(DREG(ext
, 0), QREG_CC_N
);
2697 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_Z
);
2698 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
);
2700 tcg_gen_movi_i32(QREG_CC_V
, 0);
2701 tcg_gen_movi_i32(QREG_CC_C
, 0);
2703 set_cc_op(s
, CC_OP_FLAGS
);
2706 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2707 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2708 tcg_gen_movi_i32(QREG_CC_C
, 0);
2710 tcg_gen_muls2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2711 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2712 tcg_gen_sari_i32(QREG_CC_Z
, QREG_CC_N
, 31);
2713 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_Z
);
2715 tcg_gen_mulu2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2716 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2717 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_C
);
2719 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
2720 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_N
);
2722 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
2724 set_cc_op(s
, CC_OP_FLAGS
);
2726 /* The upper 32 bits of the product are discarded, so
2727 muls.l and mulu.l are functionally equivalent. */
2728 tcg_gen_mul_i32(DREG(ext
, 12), src1
, DREG(ext
, 12));
2729 gen_logic_cc(s
, DREG(ext
, 12), OS_LONG
);
2733 static void gen_link(DisasContext
*s
, uint16_t insn
, int32_t offset
)
2738 reg
= AREG(insn
, 0);
2739 tmp
= tcg_temp_new();
2740 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2741 gen_store(s
, OS_LONG
, tmp
, reg
);
2742 if ((insn
& 7) != 7) {
2743 tcg_gen_mov_i32(reg
, tmp
);
2745 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
2753 offset
= read_im16(env
, s
);
2754 gen_link(s
, insn
, offset
);
2761 offset
= read_im32(env
, s
);
2762 gen_link(s
, insn
, offset
);
2771 src
= tcg_temp_new();
2772 reg
= AREG(insn
, 0);
2773 tcg_gen_mov_i32(src
, reg
);
2774 tmp
= gen_load(s
, OS_LONG
, src
, 0);
2775 tcg_gen_mov_i32(reg
, tmp
);
2776 tcg_gen_addi_i32(QREG_SP
, src
, 4);
2787 int16_t offset
= read_im16(env
, s
);
2789 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
2790 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, offset
+ 4);
2798 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
2799 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
2807 /* Load the target address first to ensure correct exception
2809 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2810 if (IS_NULL_QREG(tmp
)) {
2814 if ((insn
& 0x40) == 0) {
2816 gen_push(s
, tcg_const_i32(s
->pc
));
2830 if ((insn
& 070) == 010) {
2831 /* Operation on address register is always long. */
2834 opsize
= insn_opsize(insn
);
2836 SRC_EA(env
, src
, opsize
, 1, &addr
);
2837 imm
= (insn
>> 9) & 7;
2841 val
= tcg_const_i32(imm
);
2842 dest
= tcg_temp_new();
2843 tcg_gen_mov_i32(dest
, src
);
2844 if ((insn
& 0x38) == 0x08) {
2845 /* Don't update condition codes if the destination is an
2846 address register. */
2847 if (insn
& 0x0100) {
2848 tcg_gen_sub_i32(dest
, dest
, val
);
2850 tcg_gen_add_i32(dest
, dest
, val
);
2853 if (insn
& 0x0100) {
2854 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
2855 tcg_gen_sub_i32(dest
, dest
, val
);
2856 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2858 tcg_gen_add_i32(dest
, dest
, val
);
2859 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
2860 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2862 gen_update_cc_add(dest
, val
, opsize
);
2865 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2866 tcg_temp_free(dest
);
2872 case 2: /* One extension word. */
2875 case 3: /* Two extension words. */
2878 case 4: /* No extension words. */
2881 disas_undef(env
, s
, insn
);
2893 op
= (insn
>> 8) & 0xf;
2894 offset
= (int8_t)insn
;
2896 offset
= (int16_t)read_im16(env
, s
);
2897 } else if (offset
== -1) {
2898 offset
= read_im32(env
, s
);
2902 gen_push(s
, tcg_const_i32(s
->pc
));
2906 l1
= gen_new_label();
2907 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
2908 gen_jmp_tb(s
, 1, base
+ offset
);
2910 gen_jmp_tb(s
, 0, s
->pc
);
2912 /* Unconditional branch. */
2913 gen_jmp_tb(s
, 0, base
+ offset
);
2919 tcg_gen_movi_i32(DREG(insn
, 9), (int8_t)insn
);
2920 gen_logic_cc(s
, DREG(insn
, 9), OS_LONG
);
2933 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
2934 reg
= DREG(insn
, 9);
2935 tcg_gen_mov_i32(reg
, src
);
2936 gen_logic_cc(s
, src
, opsize
);
2947 opsize
= insn_opsize(insn
);
2948 reg
= gen_extend(DREG(insn
, 9), opsize
, 0);
2949 dest
= tcg_temp_new();
2951 SRC_EA(env
, src
, opsize
, 0, &addr
);
2952 tcg_gen_or_i32(dest
, src
, reg
);
2953 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2955 SRC_EA(env
, src
, opsize
, 0, NULL
);
2956 tcg_gen_or_i32(dest
, src
, reg
);
2957 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
2959 gen_logic_cc(s
, dest
, opsize
);
2960 tcg_temp_free(dest
);
2968 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
2969 reg
= AREG(insn
, 9);
2970 tcg_gen_sub_i32(reg
, reg
, src
);
2973 static inline void gen_subx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
2977 gen_flush_flags(s
); /* compute old Z */
2979 /* Perform substract with borrow.
2980 * (X, N) = dest - (src + X);
2983 tmp
= tcg_const_i32(0);
2984 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, tmp
, QREG_CC_X
, tmp
);
2985 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, dest
, tmp
, QREG_CC_N
, QREG_CC_X
);
2986 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2987 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2989 /* Compute signed-overflow for substract. */
2991 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, dest
);
2992 tcg_gen_xor_i32(tmp
, dest
, src
);
2993 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
2996 /* Copy the rest of the results into place. */
2997 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2998 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3000 set_cc_op(s
, CC_OP_FLAGS
);
3002 /* result is in QREG_CC_N */
3005 DISAS_INSN(subx_reg
)
3011 opsize
= insn_opsize(insn
);
3013 src
= gen_extend(DREG(insn
, 0), opsize
, 1);
3014 dest
= gen_extend(DREG(insn
, 9), opsize
, 1);
3016 gen_subx(s
, src
, dest
, opsize
);
3018 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3021 DISAS_INSN(subx_mem
)
3029 opsize
= insn_opsize(insn
);
3031 addr_src
= AREG(insn
, 0);
3032 tcg_gen_subi_i32(addr_src
, addr_src
, opsize
);
3033 src
= gen_load(s
, opsize
, addr_src
, 1);
3035 addr_dest
= AREG(insn
, 9);
3036 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize
);
3037 dest
= gen_load(s
, opsize
, addr_dest
, 1);
3039 gen_subx(s
, src
, dest
, opsize
);
3041 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
);
3049 val
= (insn
>> 9) & 7;
3052 src
= tcg_const_i32(val
);
3053 gen_logic_cc(s
, src
, OS_LONG
);
3054 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
3064 opsize
= insn_opsize(insn
);
3065 SRC_EA(env
, src
, opsize
, 1, NULL
);
3066 reg
= gen_extend(DREG(insn
, 9), opsize
, 1);
3067 gen_update_cc_cmp(s
, reg
, src
, opsize
);
3081 SRC_EA(env
, src
, opsize
, 1, NULL
);
3082 reg
= AREG(insn
, 9);
3083 gen_update_cc_cmp(s
, reg
, src
, OS_LONG
);
3088 int opsize
= insn_opsize(insn
);
3091 /* Post-increment load (mode 3) from Ay. */
3092 src
= gen_ea_mode(env
, s
, 3, REG(insn
, 0), opsize
,
3093 NULL_QREG
, NULL
, EA_LOADS
);
3094 /* Post-increment load (mode 3) from Ax. */
3095 dst
= gen_ea_mode(env
, s
, 3, REG(insn
, 9), opsize
,
3096 NULL_QREG
, NULL
, EA_LOADS
);
3098 gen_update_cc_cmp(s
, dst
, src
, opsize
);
3108 opsize
= insn_opsize(insn
);
3110 SRC_EA(env
, src
, opsize
, 0, &addr
);
3111 dest
= tcg_temp_new();
3112 tcg_gen_xor_i32(dest
, src
, DREG(insn
, 9));
3113 gen_logic_cc(s
, dest
, opsize
);
3114 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3115 tcg_temp_free(dest
);
3118 static void do_exg(TCGv reg1
, TCGv reg2
)
3120 TCGv temp
= tcg_temp_new();
3121 tcg_gen_mov_i32(temp
, reg1
);
3122 tcg_gen_mov_i32(reg1
, reg2
);
3123 tcg_gen_mov_i32(reg2
, temp
);
3124 tcg_temp_free(temp
);
3129 /* exchange Dx and Dy */
3130 do_exg(DREG(insn
, 9), DREG(insn
, 0));
3135 /* exchange Ax and Ay */
3136 do_exg(AREG(insn
, 9), AREG(insn
, 0));
3141 /* exchange Dx and Ay */
3142 do_exg(DREG(insn
, 9), AREG(insn
, 0));
3153 dest
= tcg_temp_new();
3155 opsize
= insn_opsize(insn
);
3156 reg
= DREG(insn
, 9);
3158 SRC_EA(env
, src
, opsize
, 0, &addr
);
3159 tcg_gen_and_i32(dest
, src
, reg
);
3160 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3162 SRC_EA(env
, src
, opsize
, 0, NULL
);
3163 tcg_gen_and_i32(dest
, src
, reg
);
3164 gen_partset_reg(opsize
, reg
, dest
);
3166 gen_logic_cc(s
, dest
, opsize
);
3167 tcg_temp_free(dest
);
3175 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3176 reg
= AREG(insn
, 9);
3177 tcg_gen_add_i32(reg
, reg
, src
);
3180 static inline void gen_addx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3184 gen_flush_flags(s
); /* compute old Z */
3186 /* Perform addition with carry.
3187 * (X, N) = src + dest + X;
3190 tmp
= tcg_const_i32(0);
3191 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_X
, tmp
, dest
, tmp
);
3192 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_N
, QREG_CC_X
, src
, tmp
);
3193 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3195 /* Compute signed-overflow for addition. */
3197 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3198 tcg_gen_xor_i32(tmp
, dest
, src
);
3199 tcg_gen_andc_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3202 /* Copy the rest of the results into place. */
3203 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3204 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3206 set_cc_op(s
, CC_OP_FLAGS
);
3208 /* result is in QREG_CC_N */
3211 DISAS_INSN(addx_reg
)
3217 opsize
= insn_opsize(insn
);
3219 dest
= gen_extend(DREG(insn
, 9), opsize
, 1);
3220 src
= gen_extend(DREG(insn
, 0), opsize
, 1);
3222 gen_addx(s
, src
, dest
, opsize
);
3224 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3227 DISAS_INSN(addx_mem
)
3235 opsize
= insn_opsize(insn
);
3237 addr_src
= AREG(insn
, 0);
3238 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3239 src
= gen_load(s
, opsize
, addr_src
, 1);
3241 addr_dest
= AREG(insn
, 9);
3242 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3243 dest
= gen_load(s
, opsize
, addr_dest
, 1);
3245 gen_addx(s
, src
, dest
, opsize
);
3247 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
);
3250 static inline void shift_im(DisasContext
*s
, uint16_t insn
, int opsize
)
3252 int count
= (insn
>> 9) & 7;
3253 int logical
= insn
& 8;
3254 int left
= insn
& 0x100;
3255 int bits
= opsize_bytes(opsize
) * 8;
3256 TCGv reg
= gen_extend(DREG(insn
, 0), opsize
, !logical
);
3262 tcg_gen_movi_i32(QREG_CC_V
, 0);
3264 tcg_gen_shri_i32(QREG_CC_C
, reg
, bits
- count
);
3265 tcg_gen_shli_i32(QREG_CC_N
, reg
, count
);
3267 /* Note that ColdFire always clears V (done above),
3268 while M68000 sets if the most significant bit is changed at
3269 any time during the shift operation */
3270 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3271 /* if shift count >= bits, V is (reg != 0) */
3272 if (count
>= bits
) {
3273 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, reg
, QREG_CC_V
);
3275 TCGv t0
= tcg_temp_new();
3276 tcg_gen_sari_i32(QREG_CC_V
, reg
, bits
- 1);
3277 tcg_gen_sari_i32(t0
, reg
, bits
- count
- 1);
3278 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, t0
);
3281 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3284 tcg_gen_shri_i32(QREG_CC_C
, reg
, count
- 1);
3286 tcg_gen_shri_i32(QREG_CC_N
, reg
, count
);
3288 tcg_gen_sari_i32(QREG_CC_N
, reg
, count
);
3292 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3293 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3294 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3295 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3297 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3298 set_cc_op(s
, CC_OP_FLAGS
);
3301 static inline void shift_reg(DisasContext
*s
, uint16_t insn
, int opsize
)
3303 int logical
= insn
& 8;
3304 int left
= insn
& 0x100;
3305 int bits
= opsize_bytes(opsize
) * 8;
3306 TCGv reg
= gen_extend(DREG(insn
, 0), opsize
, !logical
);
3310 t64
= tcg_temp_new_i64();
3311 s64
= tcg_temp_new_i64();
3312 s32
= tcg_temp_new();
3314 /* Note that m68k truncates the shift count modulo 64, not 32.
3315 In addition, a 64-bit shift makes it easy to find "the last
3316 bit shifted out", for the carry flag. */
3317 tcg_gen_andi_i32(s32
, DREG(insn
, 9), 63);
3318 tcg_gen_extu_i32_i64(s64
, s32
);
3319 tcg_gen_extu_i32_i64(t64
, reg
);
3321 /* Optimistically set V=0. Also used as a zero source below. */
3322 tcg_gen_movi_i32(QREG_CC_V
, 0);
3324 tcg_gen_shl_i64(t64
, t64
, s64
);
3326 if (opsize
== OS_LONG
) {
3327 tcg_gen_extr_i64_i32(QREG_CC_N
, QREG_CC_C
, t64
);
3328 /* Note that C=0 if shift count is 0, and we get that for free. */
3330 TCGv zero
= tcg_const_i32(0);
3331 tcg_gen_extrl_i64_i32(QREG_CC_N
, t64
);
3332 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_N
, bits
);
3333 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3334 s32
, zero
, zero
, QREG_CC_C
);
3335 tcg_temp_free(zero
);
3337 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3339 /* X = C, but only if the shift count was non-zero. */
3340 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3341 QREG_CC_C
, QREG_CC_X
);
3343 /* M68000 sets V if the most significant bit is changed at
3344 * any time during the shift operation. Do this via creating
3345 * an extension of the sign bit, comparing, and discarding
3346 * the bits below the sign bit. I.e.
3347 * int64_t s = (intN_t)reg;
3348 * int64_t t = (int64_t)(intN_t)reg << count;
3349 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3351 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3352 TCGv_i64 tt
= tcg_const_i64(32);
3353 /* if shift is greater than 32, use 32 */
3354 tcg_gen_movcond_i64(TCG_COND_GT
, s64
, s64
, tt
, tt
, s64
);
3355 tcg_temp_free_i64(tt
);
3356 /* Sign extend the input to 64 bits; re-do the shift. */
3357 tcg_gen_ext_i32_i64(t64
, reg
);
3358 tcg_gen_shl_i64(s64
, t64
, s64
);
3359 /* Clear all bits that are unchanged. */
3360 tcg_gen_xor_i64(t64
, t64
, s64
);
3361 /* Ignore the bits below the sign bit. */
3362 tcg_gen_andi_i64(t64
, t64
, -1ULL << (bits
- 1));
3363 /* If any bits remain set, we have overflow. */
3364 tcg_gen_setcondi_i64(TCG_COND_NE
, t64
, t64
, 0);
3365 tcg_gen_extrl_i64_i32(QREG_CC_V
, t64
);
3366 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3369 tcg_gen_shli_i64(t64
, t64
, 32);
3371 tcg_gen_shr_i64(t64
, t64
, s64
);
3373 tcg_gen_sar_i64(t64
, t64
, s64
);
3375 tcg_gen_extr_i64_i32(QREG_CC_C
, QREG_CC_N
, t64
);
3377 /* Note that C=0 if shift count is 0, and we get that for free. */
3378 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_C
, 31);
3380 /* X = C, but only if the shift count was non-zero. */
3381 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3382 QREG_CC_C
, QREG_CC_X
);
3384 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3385 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3388 tcg_temp_free_i64(s64
);
3389 tcg_temp_free_i64(t64
);
3391 /* Write back the result. */
3392 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3393 set_cc_op(s
, CC_OP_FLAGS
);
3396 DISAS_INSN(shift8_im
)
3398 shift_im(s
, insn
, OS_BYTE
);
3401 DISAS_INSN(shift16_im
)
3403 shift_im(s
, insn
, OS_WORD
);
3406 DISAS_INSN(shift_im
)
3408 shift_im(s
, insn
, OS_LONG
);
3411 DISAS_INSN(shift8_reg
)
3413 shift_reg(s
, insn
, OS_BYTE
);
3416 DISAS_INSN(shift16_reg
)
3418 shift_reg(s
, insn
, OS_WORD
);
3421 DISAS_INSN(shift_reg
)
3423 shift_reg(s
, insn
, OS_LONG
);
3426 DISAS_INSN(shift_mem
)
3428 int logical
= insn
& 8;
3429 int left
= insn
& 0x100;
3433 SRC_EA(env
, src
, OS_WORD
, !logical
, &addr
);
3434 tcg_gen_movi_i32(QREG_CC_V
, 0);
3436 tcg_gen_shri_i32(QREG_CC_C
, src
, 15);
3437 tcg_gen_shli_i32(QREG_CC_N
, src
, 1);
3439 /* Note that ColdFire always clears V,
3440 while M68000 sets if the most significant bit is changed at
3441 any time during the shift operation */
3442 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3443 src
= gen_extend(src
, OS_WORD
, 1);
3444 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3447 tcg_gen_mov_i32(QREG_CC_C
, src
);
3449 tcg_gen_shri_i32(QREG_CC_N
, src
, 1);
3451 tcg_gen_sari_i32(QREG_CC_N
, src
, 1);
3455 gen_ext(QREG_CC_N
, QREG_CC_N
, OS_WORD
, 1);
3456 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3457 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3458 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3460 DEST_EA(env
, insn
, OS_WORD
, QREG_CC_N
, &addr
);
3461 set_cc_op(s
, CC_OP_FLAGS
);
3464 static void rotate(TCGv reg
, TCGv shift
, int left
, int size
)
3468 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3469 tcg_gen_ext8u_i32(reg
, reg
);
3470 tcg_gen_muli_i32(reg
, reg
, 0x01010101);
3473 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3474 tcg_gen_deposit_i32(reg
, reg
, reg
, 16, 16);
3479 tcg_gen_rotl_i32(reg
, reg
, shift
);
3481 tcg_gen_rotr_i32(reg
, reg
, shift
);
3489 tcg_gen_ext8s_i32(reg
, reg
);
3492 tcg_gen_ext16s_i32(reg
, reg
);
3498 /* QREG_CC_X is not affected */
3500 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3501 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3504 tcg_gen_andi_i32(QREG_CC_C
, reg
, 1);
3506 tcg_gen_shri_i32(QREG_CC_C
, reg
, 31);
3509 tcg_gen_movi_i32(QREG_CC_V
, 0); /* always cleared */
3512 static void rotate_x_flags(TCGv reg
, TCGv X
, int size
)
3516 tcg_gen_ext8s_i32(reg
, reg
);
3519 tcg_gen_ext16s_i32(reg
, reg
);
3524 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3525 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3526 tcg_gen_mov_i32(QREG_CC_X
, X
);
3527 tcg_gen_mov_i32(QREG_CC_C
, X
);
3528 tcg_gen_movi_i32(QREG_CC_V
, 0);
3531 /* Result of rotate_x() is valid if 0 <= shift <= size */
3532 static TCGv
rotate_x(TCGv reg
, TCGv shift
, int left
, int size
)
3534 TCGv X
, shl
, shr
, shx
, sz
, zero
;
3536 sz
= tcg_const_i32(size
);
3538 shr
= tcg_temp_new();
3539 shl
= tcg_temp_new();
3540 shx
= tcg_temp_new();
3542 tcg_gen_mov_i32(shl
, shift
); /* shl = shift */
3543 tcg_gen_movi_i32(shr
, size
+ 1);
3544 tcg_gen_sub_i32(shr
, shr
, shift
); /* shr = size + 1 - shift */
3545 tcg_gen_subi_i32(shx
, shift
, 1); /* shx = shift - 1 */
3546 /* shx = shx < 0 ? size : shx; */
3547 zero
= tcg_const_i32(0);
3548 tcg_gen_movcond_i32(TCG_COND_LT
, shx
, shx
, zero
, sz
, shx
);
3549 tcg_temp_free(zero
);
3551 tcg_gen_mov_i32(shr
, shift
); /* shr = shift */
3552 tcg_gen_movi_i32(shl
, size
+ 1);
3553 tcg_gen_sub_i32(shl
, shl
, shift
); /* shl = size + 1 - shift */
3554 tcg_gen_sub_i32(shx
, sz
, shift
); /* shx = size - shift */
3557 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3559 tcg_gen_shl_i32(shl
, reg
, shl
);
3560 tcg_gen_shr_i32(shr
, reg
, shr
);
3561 tcg_gen_or_i32(reg
, shl
, shr
);
3564 tcg_gen_shl_i32(shx
, QREG_CC_X
, shx
);
3565 tcg_gen_or_i32(reg
, reg
, shx
);
3568 /* X = (reg >> size) & 1 */
3571 tcg_gen_shr_i32(X
, reg
, sz
);
3572 tcg_gen_andi_i32(X
, X
, 1);
3578 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3579 static TCGv
rotate32_x(TCGv reg
, TCGv shift
, int left
)
3581 TCGv_i64 t0
, shift64
;
3582 TCGv X
, lo
, hi
, zero
;
3584 shift64
= tcg_temp_new_i64();
3585 tcg_gen_extu_i32_i64(shift64
, shift
);
3587 t0
= tcg_temp_new_i64();
3590 lo
= tcg_temp_new();
3591 hi
= tcg_temp_new();
3594 /* create [reg:X:..] */
3596 tcg_gen_shli_i32(lo
, QREG_CC_X
, 31);
3597 tcg_gen_concat_i32_i64(t0
, lo
, reg
);
3601 tcg_gen_rotl_i64(t0
, t0
, shift64
);
3602 tcg_temp_free_i64(shift64
);
3604 /* result is [reg:..:reg:X] */
3606 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3607 tcg_gen_andi_i32(X
, lo
, 1);
3609 tcg_gen_shri_i32(lo
, lo
, 1);
3611 /* create [..:X:reg] */
3613 tcg_gen_concat_i32_i64(t0
, reg
, QREG_CC_X
);
3615 tcg_gen_rotr_i64(t0
, t0
, shift64
);
3616 tcg_temp_free_i64(shift64
);
3618 /* result is value: [X:reg:..:reg] */
3620 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3624 tcg_gen_shri_i32(X
, hi
, 31);
3626 /* extract result */
3628 tcg_gen_shli_i32(hi
, hi
, 1);
3630 tcg_temp_free_i64(t0
);
3631 tcg_gen_or_i32(lo
, lo
, hi
);
3634 /* if shift == 0, register and X are not affected */
3636 zero
= tcg_const_i32(0);
3637 tcg_gen_movcond_i32(TCG_COND_EQ
, X
, shift
, zero
, QREG_CC_X
, X
);
3638 tcg_gen_movcond_i32(TCG_COND_EQ
, reg
, shift
, zero
, reg
, lo
);
3639 tcg_temp_free(zero
);
3645 DISAS_INSN(rotate_im
)
3649 int left
= (insn
& 0x100);
3651 tmp
= (insn
>> 9) & 7;
3656 shift
= tcg_const_i32(tmp
);
3658 rotate(DREG(insn
, 0), shift
, left
, 32);
3660 TCGv X
= rotate32_x(DREG(insn
, 0), shift
, left
);
3661 rotate_x_flags(DREG(insn
, 0), X
, 32);
3664 tcg_temp_free(shift
);
3666 set_cc_op(s
, CC_OP_FLAGS
);
3669 DISAS_INSN(rotate8_im
)
3671 int left
= (insn
& 0x100);
3676 reg
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
3678 tmp
= (insn
>> 9) & 7;
3683 shift
= tcg_const_i32(tmp
);
3685 rotate(reg
, shift
, left
, 8);
3687 TCGv X
= rotate_x(reg
, shift
, left
, 8);
3688 rotate_x_flags(reg
, X
, 8);
3691 tcg_temp_free(shift
);
3692 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3693 set_cc_op(s
, CC_OP_FLAGS
);
3696 DISAS_INSN(rotate16_im
)
3698 int left
= (insn
& 0x100);
3703 reg
= gen_extend(DREG(insn
, 0), OS_WORD
, 0);
3704 tmp
= (insn
>> 9) & 7;
3709 shift
= tcg_const_i32(tmp
);
3711 rotate(reg
, shift
, left
, 16);
3713 TCGv X
= rotate_x(reg
, shift
, left
, 16);
3714 rotate_x_flags(reg
, X
, 16);
3717 tcg_temp_free(shift
);
3718 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3719 set_cc_op(s
, CC_OP_FLAGS
);
3722 DISAS_INSN(rotate_reg
)
3727 int left
= (insn
& 0x100);
3729 reg
= DREG(insn
, 0);
3730 src
= DREG(insn
, 9);
3731 /* shift in [0..63] */
3732 t0
= tcg_temp_new();
3733 tcg_gen_andi_i32(t0
, src
, 63);
3734 t1
= tcg_temp_new_i32();
3736 tcg_gen_andi_i32(t1
, src
, 31);
3737 rotate(reg
, t1
, left
, 32);
3738 /* if shift == 0, clear C */
3739 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3740 t0
, QREG_CC_V
/* 0 */,
3741 QREG_CC_V
/* 0 */, QREG_CC_C
);
3745 tcg_gen_movi_i32(t1
, 33);
3746 tcg_gen_remu_i32(t1
, t0
, t1
);
3747 X
= rotate32_x(DREG(insn
, 0), t1
, left
);
3748 rotate_x_flags(DREG(insn
, 0), X
, 32);
3753 set_cc_op(s
, CC_OP_FLAGS
);
3756 DISAS_INSN(rotate8_reg
)
3761 int left
= (insn
& 0x100);
3763 reg
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
3764 src
= DREG(insn
, 9);
3765 /* shift in [0..63] */
3766 t0
= tcg_temp_new_i32();
3767 tcg_gen_andi_i32(t0
, src
, 63);
3768 t1
= tcg_temp_new_i32();
3770 tcg_gen_andi_i32(t1
, src
, 7);
3771 rotate(reg
, t1
, left
, 8);
3772 /* if shift == 0, clear C */
3773 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3774 t0
, QREG_CC_V
/* 0 */,
3775 QREG_CC_V
/* 0 */, QREG_CC_C
);
3779 tcg_gen_movi_i32(t1
, 9);
3780 tcg_gen_remu_i32(t1
, t0
, t1
);
3781 X
= rotate_x(reg
, t1
, left
, 8);
3782 rotate_x_flags(reg
, X
, 8);
3787 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3788 set_cc_op(s
, CC_OP_FLAGS
);
3791 DISAS_INSN(rotate16_reg
)
3796 int left
= (insn
& 0x100);
3798 reg
= gen_extend(DREG(insn
, 0), OS_WORD
, 0);
3799 src
= DREG(insn
, 9);
3800 /* shift in [0..63] */
3801 t0
= tcg_temp_new_i32();
3802 tcg_gen_andi_i32(t0
, src
, 63);
3803 t1
= tcg_temp_new_i32();
3805 tcg_gen_andi_i32(t1
, src
, 15);
3806 rotate(reg
, t1
, left
, 16);
3807 /* if shift == 0, clear C */
3808 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3809 t0
, QREG_CC_V
/* 0 */,
3810 QREG_CC_V
/* 0 */, QREG_CC_C
);
3814 tcg_gen_movi_i32(t1
, 17);
3815 tcg_gen_remu_i32(t1
, t0
, t1
);
3816 X
= rotate_x(reg
, t1
, left
, 16);
3817 rotate_x_flags(reg
, X
, 16);
3822 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3823 set_cc_op(s
, CC_OP_FLAGS
);
3826 DISAS_INSN(rotate_mem
)
3831 int left
= (insn
& 0x100);
3833 SRC_EA(env
, src
, OS_WORD
, 0, &addr
);
3835 shift
= tcg_const_i32(1);
3836 if (insn
& 0x0200) {
3837 rotate(src
, shift
, left
, 16);
3839 TCGv X
= rotate_x(src
, shift
, left
, 16);
3840 rotate_x_flags(src
, X
, 16);
3843 tcg_temp_free(shift
);
3844 DEST_EA(env
, insn
, OS_WORD
, src
, &addr
);
3845 set_cc_op(s
, CC_OP_FLAGS
);
3848 DISAS_INSN(bfext_reg
)
3850 int ext
= read_im16(env
, s
);
3851 int is_sign
= insn
& 0x200;
3852 TCGv src
= DREG(insn
, 0);
3853 TCGv dst
= DREG(ext
, 12);
3854 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
3855 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
3856 int pos
= 32 - ofs
- len
; /* little bit-endian */
3857 TCGv tmp
= tcg_temp_new();
3860 /* In general, we're going to rotate the field so that it's at the
3861 top of the word and then right-shift by the compliment of the
3862 width to extend the field. */
3864 /* Variable width. */
3866 /* Variable offset. */
3867 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
3868 tcg_gen_rotl_i32(tmp
, src
, tmp
);
3870 tcg_gen_rotli_i32(tmp
, src
, ofs
);
3873 shift
= tcg_temp_new();
3874 tcg_gen_neg_i32(shift
, DREG(ext
, 0));
3875 tcg_gen_andi_i32(shift
, shift
, 31);
3876 tcg_gen_sar_i32(QREG_CC_N
, tmp
, shift
);
3878 tcg_gen_mov_i32(dst
, QREG_CC_N
);
3880 tcg_gen_shr_i32(dst
, tmp
, shift
);
3882 tcg_temp_free(shift
);
3884 /* Immediate width. */
3886 /* Variable offset */
3887 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
3888 tcg_gen_rotl_i32(tmp
, src
, tmp
);
3892 /* Immediate offset. If the field doesn't wrap around the
3893 end of the word, rely on (s)extract completely. */
3895 tcg_gen_rotli_i32(tmp
, src
, ofs
);
3901 tcg_gen_sextract_i32(QREG_CC_N
, src
, pos
, len
);
3903 tcg_gen_mov_i32(dst
, QREG_CC_N
);
3905 tcg_gen_extract_i32(dst
, src
, pos
, len
);
3910 set_cc_op(s
, CC_OP_LOGIC
);
3913 DISAS_INSN(bfext_mem
)
3915 int ext
= read_im16(env
, s
);
3916 int is_sign
= insn
& 0x200;
3917 TCGv dest
= DREG(ext
, 12);
3918 TCGv addr
, len
, ofs
;
3920 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
3921 if (IS_NULL_QREG(addr
)) {
3929 len
= tcg_const_i32(extract32(ext
, 0, 5));
3934 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
3938 gen_helper_bfexts_mem(dest
, cpu_env
, addr
, ofs
, len
);
3939 tcg_gen_mov_i32(QREG_CC_N
, dest
);
3941 TCGv_i64 tmp
= tcg_temp_new_i64();
3942 gen_helper_bfextu_mem(tmp
, cpu_env
, addr
, ofs
, len
);
3943 tcg_gen_extr_i64_i32(dest
, QREG_CC_N
, tmp
);
3944 tcg_temp_free_i64(tmp
);
3946 set_cc_op(s
, CC_OP_LOGIC
);
3948 if (!(ext
& 0x20)) {
3951 if (!(ext
& 0x800)) {
3956 DISAS_INSN(bfop_reg
)
3958 int ext
= read_im16(env
, s
);
3959 TCGv src
= DREG(insn
, 0);
3960 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
3961 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
3962 TCGv mask
, tofs
, tlen
;
3966 if ((insn
& 0x0f00) == 0x0d00) { /* bfffo */
3967 tofs
= tcg_temp_new();
3968 tlen
= tcg_temp_new();
3971 if ((ext
& 0x820) == 0) {
3972 /* Immediate width and offset. */
3973 uint32_t maski
= 0x7fffffffu
>> (len
- 1);
3974 if (ofs
+ len
<= 32) {
3975 tcg_gen_shli_i32(QREG_CC_N
, src
, ofs
);
3977 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
3979 tcg_gen_andi_i32(QREG_CC_N
, QREG_CC_N
, ~maski
);
3980 mask
= tcg_const_i32(ror32(maski
, ofs
));
3981 if (!TCGV_IS_UNUSED(tofs
)) {
3982 tcg_gen_movi_i32(tofs
, ofs
);
3983 tcg_gen_movi_i32(tlen
, len
);
3986 TCGv tmp
= tcg_temp_new();
3988 /* Variable width */
3989 tcg_gen_subi_i32(tmp
, DREG(ext
, 0), 1);
3990 tcg_gen_andi_i32(tmp
, tmp
, 31);
3991 mask
= tcg_const_i32(0x7fffffffu
);
3992 tcg_gen_shr_i32(mask
, mask
, tmp
);
3993 if (!TCGV_IS_UNUSED(tlen
)) {
3994 tcg_gen_addi_i32(tlen
, tmp
, 1);
3997 /* Immediate width */
3998 mask
= tcg_const_i32(0x7fffffffu
>> (len
- 1));
3999 if (!TCGV_IS_UNUSED(tlen
)) {
4000 tcg_gen_movi_i32(tlen
, len
);
4004 /* Variable offset */
4005 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4006 tcg_gen_rotl_i32(QREG_CC_N
, src
, tmp
);
4007 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4008 tcg_gen_rotr_i32(mask
, mask
, tmp
);
4009 if (!TCGV_IS_UNUSED(tofs
)) {
4010 tcg_gen_mov_i32(tofs
, tmp
);
4013 /* Immediate offset (and variable width) */
4014 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4015 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4016 tcg_gen_rotri_i32(mask
, mask
, ofs
);
4017 if (!TCGV_IS_UNUSED(tofs
)) {
4018 tcg_gen_movi_i32(tofs
, ofs
);
4023 set_cc_op(s
, CC_OP_LOGIC
);
4025 switch (insn
& 0x0f00) {
4026 case 0x0a00: /* bfchg */
4027 tcg_gen_eqv_i32(src
, src
, mask
);
4029 case 0x0c00: /* bfclr */
4030 tcg_gen_and_i32(src
, src
, mask
);
4032 case 0x0d00: /* bfffo */
4033 gen_helper_bfffo_reg(DREG(ext
, 12), QREG_CC_N
, tofs
, tlen
);
4034 tcg_temp_free(tlen
);
4035 tcg_temp_free(tofs
);
4037 case 0x0e00: /* bfset */
4038 tcg_gen_orc_i32(src
, src
, mask
);
4040 case 0x0800: /* bftst */
4041 /* flags already set; no other work to do. */
4044 g_assert_not_reached();
4046 tcg_temp_free(mask
);
4049 DISAS_INSN(bfop_mem
)
4051 int ext
= read_im16(env
, s
);
4052 TCGv addr
, len
, ofs
;
4055 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4056 if (IS_NULL_QREG(addr
)) {
4064 len
= tcg_const_i32(extract32(ext
, 0, 5));
4069 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4072 switch (insn
& 0x0f00) {
4073 case 0x0a00: /* bfchg */
4074 gen_helper_bfchg_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4076 case 0x0c00: /* bfclr */
4077 gen_helper_bfclr_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4079 case 0x0d00: /* bfffo */
4080 t64
= tcg_temp_new_i64();
4081 gen_helper_bfffo_mem(t64
, cpu_env
, addr
, ofs
, len
);
4082 tcg_gen_extr_i64_i32(DREG(ext
, 12), QREG_CC_N
, t64
);
4083 tcg_temp_free_i64(t64
);
4085 case 0x0e00: /* bfset */
4086 gen_helper_bfset_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4088 case 0x0800: /* bftst */
4089 gen_helper_bfexts_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4092 g_assert_not_reached();
4094 set_cc_op(s
, CC_OP_LOGIC
);
4096 if (!(ext
& 0x20)) {
4099 if (!(ext
& 0x800)) {
4104 DISAS_INSN(bfins_reg
)
4106 int ext
= read_im16(env
, s
);
4107 TCGv dst
= DREG(insn
, 0);
4108 TCGv src
= DREG(ext
, 12);
4109 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4110 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4111 int pos
= 32 - ofs
- len
; /* little bit-endian */
4114 tmp
= tcg_temp_new();
4117 /* Variable width */
4118 tcg_gen_neg_i32(tmp
, DREG(ext
, 0));
4119 tcg_gen_andi_i32(tmp
, tmp
, 31);
4120 tcg_gen_shl_i32(QREG_CC_N
, src
, tmp
);
4122 /* Immediate width */
4123 tcg_gen_shli_i32(QREG_CC_N
, src
, 32 - len
);
4125 set_cc_op(s
, CC_OP_LOGIC
);
4127 /* Immediate width and offset */
4128 if ((ext
& 0x820) == 0) {
4129 /* Check for suitability for deposit. */
4131 tcg_gen_deposit_i32(dst
, dst
, src
, pos
, len
);
4133 uint32_t maski
= -2U << (len
- 1);
4134 uint32_t roti
= (ofs
+ len
) & 31;
4135 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4136 tcg_gen_rotri_i32(tmp
, tmp
, roti
);
4137 tcg_gen_andi_i32(dst
, dst
, ror32(maski
, roti
));
4138 tcg_gen_or_i32(dst
, dst
, tmp
);
4141 TCGv mask
= tcg_temp_new();
4142 TCGv rot
= tcg_temp_new();
4145 /* Variable width */
4146 tcg_gen_subi_i32(rot
, DREG(ext
, 0), 1);
4147 tcg_gen_andi_i32(rot
, rot
, 31);
4148 tcg_gen_movi_i32(mask
, -2);
4149 tcg_gen_shl_i32(mask
, mask
, rot
);
4150 tcg_gen_mov_i32(rot
, DREG(ext
, 0));
4151 tcg_gen_andc_i32(tmp
, src
, mask
);
4153 /* Immediate width (variable offset) */
4154 uint32_t maski
= -2U << (len
- 1);
4155 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4156 tcg_gen_movi_i32(mask
, maski
);
4157 tcg_gen_movi_i32(rot
, len
& 31);
4160 /* Variable offset */
4161 tcg_gen_add_i32(rot
, rot
, DREG(ext
, 6));
4163 /* Immediate offset (variable width) */
4164 tcg_gen_addi_i32(rot
, rot
, ofs
);
4166 tcg_gen_andi_i32(rot
, rot
, 31);
4167 tcg_gen_rotr_i32(mask
, mask
, rot
);
4168 tcg_gen_rotr_i32(tmp
, tmp
, rot
);
4169 tcg_gen_and_i32(dst
, dst
, mask
);
4170 tcg_gen_or_i32(dst
, dst
, tmp
);
4173 tcg_temp_free(mask
);
4178 DISAS_INSN(bfins_mem
)
4180 int ext
= read_im16(env
, s
);
4181 TCGv src
= DREG(ext
, 12);
4182 TCGv addr
, len
, ofs
;
4184 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4185 if (IS_NULL_QREG(addr
)) {
4193 len
= tcg_const_i32(extract32(ext
, 0, 5));
4198 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4201 gen_helper_bfins_mem(QREG_CC_N
, cpu_env
, addr
, src
, ofs
, len
);
4202 set_cc_op(s
, CC_OP_LOGIC
);
4204 if (!(ext
& 0x20)) {
4207 if (!(ext
& 0x800)) {
4215 reg
= DREG(insn
, 0);
4216 gen_logic_cc(s
, reg
, OS_LONG
);
4217 gen_helper_ff1(reg
, reg
);
4220 static TCGv
gen_get_sr(DisasContext
*s
)
4225 ccr
= gen_get_ccr(s
);
4226 sr
= tcg_temp_new();
4227 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
4228 tcg_gen_or_i32(sr
, sr
, ccr
);
4238 ext
= read_im16(env
, s
);
4239 if (ext
!= 0x46FC) {
4240 gen_exception(s
, addr
, EXCP_UNSUPPORTED
);
4243 ext
= read_im16(env
, s
);
4244 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
4245 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
4248 gen_push(s
, gen_get_sr(s
));
4249 gen_set_sr_im(s
, ext
, 0);
4252 DISAS_INSN(move_from_sr
)
4256 if (IS_USER(s
) && !m68k_feature(env
, M68K_FEATURE_M68000
)) {
4257 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4261 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
4264 DISAS_INSN(move_to_sr
)
4267 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4270 gen_set_sr(env
, s
, insn
, 0);
4274 DISAS_INSN(move_from_usp
)
4277 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4280 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
4281 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4284 DISAS_INSN(move_to_usp
)
4287 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4290 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
4291 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4296 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
4304 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4308 ext
= read_im16(env
, s
);
4310 gen_set_sr_im(s
, ext
, 0);
4311 tcg_gen_movi_i32(cpu_halted
, 1);
4312 gen_exception(s
, s
->pc
, EXCP_HLT
);
4318 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4321 gen_exception(s
, s
->pc
- 2, EXCP_RTE
);
4330 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4334 ext
= read_im16(env
, s
);
4337 reg
= AREG(ext
, 12);
4339 reg
= DREG(ext
, 12);
4341 gen_helper_movec(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4348 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4351 /* ICache fetch. Implement as no-op. */
4357 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4360 /* Cache push/invalidate. Implement as no-op. */
4365 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4370 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
4373 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
4376 /* TODO: Implement wdebug. */
4377 cpu_abort(CPU(cpu
), "WDEBUG not implemented");
4382 gen_exception(s
, s
->pc
- 2, EXCP_TRAP0
+ (insn
& 0xf));
4385 static void gen_load_fcr(DisasContext
*s
, TCGv res
, int reg
)
4389 tcg_gen_movi_i32(res
, 0);
4392 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4395 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpcr
));
4400 static void gen_store_fcr(DisasContext
*s
, TCGv val
, int reg
)
4406 tcg_gen_st_i32(val
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4409 gen_helper_set_fpcr(cpu_env
, val
);
4414 static void gen_qemu_store_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4416 int index
= IS_USER(s
);
4419 tmp
= tcg_temp_new();
4420 gen_load_fcr(s
, tmp
, reg
);
4421 tcg_gen_qemu_st32(tmp
, addr
, index
);
4425 static void gen_qemu_load_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4427 int index
= IS_USER(s
);
4430 tmp
= tcg_temp_new();
4431 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
4432 gen_store_fcr(s
, tmp
, reg
);
4437 static void gen_op_fmove_fcr(CPUM68KState
*env
, DisasContext
*s
,
4438 uint32_t insn
, uint32_t ext
)
4440 int mask
= (ext
>> 10) & 7;
4441 int is_write
= (ext
>> 13) & 1;
4442 int mode
= extract32(insn
, 3, 3);
4448 if (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&& mask
!= M68K_FPCR
) {
4449 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4453 gen_load_fcr(s
, DREG(insn
, 0), mask
);
4455 gen_store_fcr(s
, DREG(insn
, 0), mask
);
4458 case 1: /* An, only with FPIAR */
4459 if (mask
!= M68K_FPIAR
) {
4460 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4464 gen_load_fcr(s
, AREG(insn
, 0), mask
);
4466 gen_store_fcr(s
, AREG(insn
, 0), mask
);
4473 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
4474 if (IS_NULL_QREG(tmp
)) {
4479 addr
= tcg_temp_new();
4480 tcg_gen_mov_i32(addr
, tmp
);
4484 * 0b100 Floating-Point Control Register
4485 * 0b010 Floating-Point Status Register
4486 * 0b001 Floating-Point Instruction Address Register
4490 if (is_write
&& mode
== 4) {
4491 for (i
= 2; i
>= 0; i
--, mask
>>= 1) {
4493 gen_qemu_store_fcr(s
, addr
, 1 << i
);
4495 tcg_gen_subi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
4499 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4501 for (i
= 0; i
< 3; i
++, mask
>>= 1) {
4504 gen_qemu_store_fcr(s
, addr
, 1 << i
);
4506 gen_qemu_load_fcr(s
, addr
, 1 << i
);
4508 if (mask
!= 1 || mode
== 3) {
4509 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
4514 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4517 tcg_temp_free_i32(addr
);
4520 static void gen_op_fmovem(CPUM68KState
*env
, DisasContext
*s
,
4521 uint32_t insn
, uint32_t ext
)
4525 int mode
= (ext
>> 11) & 0x3;
4526 int is_load
= ((ext
& 0x2000) == 0);
4528 if (m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
4529 opsize
= OS_EXTENDED
;
4531 opsize
= OS_DOUBLE
; /* FIXME */
4534 addr
= gen_lea(env
, s
, insn
, opsize
);
4535 if (IS_NULL_QREG(addr
)) {
4540 tmp
= tcg_temp_new();
4542 /* Dynamic register list */
4543 tcg_gen_ext8u_i32(tmp
, DREG(ext
, 4));
4545 /* Static register list */
4546 tcg_gen_movi_i32(tmp
, ext
& 0xff);
4549 if (!is_load
&& (mode
& 2) == 0) {
4550 /* predecrement addressing mode
4551 * only available to store register to memory
4553 if (opsize
== OS_EXTENDED
) {
4554 gen_helper_fmovemx_st_predec(tmp
, cpu_env
, addr
, tmp
);
4556 gen_helper_fmovemd_st_predec(tmp
, cpu_env
, addr
, tmp
);
4559 /* postincrement addressing mode */
4560 if (opsize
== OS_EXTENDED
) {
4562 gen_helper_fmovemx_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
4564 gen_helper_fmovemx_st_postinc(tmp
, cpu_env
, addr
, tmp
);
4568 gen_helper_fmovemd_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
4570 gen_helper_fmovemd_st_postinc(tmp
, cpu_env
, addr
, tmp
);
4574 if ((insn
& 070) == 030 || (insn
& 070) == 040) {
4575 tcg_gen_mov_i32(AREG(insn
, 0), tmp
);
4580 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
4581 immediately before the next FP instruction is executed. */
4587 TCGv_ptr cpu_src
, cpu_dest
;
4589 ext
= read_im16(env
, s
);
4590 opmode
= ext
& 0x7f;
4591 switch ((ext
>> 13) & 7) {
4597 if (insn
== 0xf200 && (ext
& 0xfc00) == 0x5c00) {
4599 TCGv rom_offset
= tcg_const_i32(opmode
);
4600 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
4601 gen_helper_fconst(cpu_env
, cpu_dest
, rom_offset
);
4602 tcg_temp_free_ptr(cpu_dest
);
4603 tcg_temp_free(rom_offset
);
4607 case 3: /* fmove out */
4608 cpu_src
= gen_fp_ptr(REG(ext
, 7));
4609 opsize
= ext_opsize(ext
, 10);
4610 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
, EA_STORE
) == -1) {
4613 gen_helper_ftst(cpu_env
, cpu_src
);
4614 tcg_temp_free_ptr(cpu_src
);
4616 case 4: /* fmove to control register. */
4617 case 5: /* fmove from control register. */
4618 gen_op_fmove_fcr(env
, s
, insn
, ext
);
4620 case 6: /* fmovem */
4622 if ((ext
& 0x1000) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
4625 gen_op_fmovem(env
, s
, insn
, ext
);
4628 if (ext
& (1 << 14)) {
4629 /* Source effective address. */
4630 opsize
= ext_opsize(ext
, 10);
4631 cpu_src
= gen_fp_result_ptr();
4632 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
, EA_LOADS
) == -1) {
4637 /* Source register. */
4638 opsize
= OS_EXTENDED
;
4639 cpu_src
= gen_fp_ptr(REG(ext
, 10));
4641 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
4644 gen_fp_move(cpu_dest
, cpu_src
);
4646 case 0x40: /* fsmove */
4647 gen_helper_fsround(cpu_env
, cpu_dest
, cpu_src
);
4649 case 0x44: /* fdmove */
4650 gen_helper_fdround(cpu_env
, cpu_dest
, cpu_src
);
4653 gen_helper_firound(cpu_env
, cpu_dest
, cpu_src
);
4655 case 3: /* fintrz */
4656 gen_helper_fitrunc(cpu_env
, cpu_dest
, cpu_src
);
4659 gen_helper_fsqrt(cpu_env
, cpu_dest
, cpu_src
);
4661 case 0x41: /* fssqrt */
4662 gen_helper_fssqrt(cpu_env
, cpu_dest
, cpu_src
);
4664 case 0x45: /* fdsqrt */
4665 gen_helper_fdsqrt(cpu_env
, cpu_dest
, cpu_src
);
4667 case 0x18: /* fabs */
4668 gen_helper_fabs(cpu_env
, cpu_dest
, cpu_src
);
4670 case 0x58: /* fsabs */
4671 gen_helper_fsabs(cpu_env
, cpu_dest
, cpu_src
);
4673 case 0x5c: /* fdabs */
4674 gen_helper_fdabs(cpu_env
, cpu_dest
, cpu_src
);
4676 case 0x1a: /* fneg */
4677 gen_helper_fneg(cpu_env
, cpu_dest
, cpu_src
);
4679 case 0x5a: /* fsneg */
4680 gen_helper_fsneg(cpu_env
, cpu_dest
, cpu_src
);
4682 case 0x5e: /* fdneg */
4683 gen_helper_fdneg(cpu_env
, cpu_dest
, cpu_src
);
4685 case 0x20: /* fdiv */
4686 gen_helper_fdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4688 case 0x60: /* fsdiv */
4689 gen_helper_fsdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4691 case 0x64: /* fddiv */
4692 gen_helper_fddiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4694 case 0x22: /* fadd */
4695 gen_helper_fadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4697 case 0x62: /* fsadd */
4698 gen_helper_fsadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4700 case 0x66: /* fdadd */
4701 gen_helper_fdadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4703 case 0x23: /* fmul */
4704 gen_helper_fmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4706 case 0x63: /* fsmul */
4707 gen_helper_fsmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4709 case 0x67: /* fdmul */
4710 gen_helper_fdmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4712 case 0x24: /* fsgldiv */
4713 gen_helper_fsgldiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4715 case 0x27: /* fsglmul */
4716 gen_helper_fsglmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4718 case 0x28: /* fsub */
4719 gen_helper_fsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4721 case 0x68: /* fssub */
4722 gen_helper_fssub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4724 case 0x6c: /* fdsub */
4725 gen_helper_fdsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4727 case 0x38: /* fcmp */
4728 gen_helper_fcmp(cpu_env
, cpu_src
, cpu_dest
);
4730 case 0x3a: /* ftst */
4731 gen_helper_ftst(cpu_env
, cpu_src
);
4736 tcg_temp_free_ptr(cpu_src
);
4737 gen_helper_ftst(cpu_env
, cpu_dest
);
4738 tcg_temp_free_ptr(cpu_dest
);
4741 /* FIXME: Is this right for offset addressing modes? */
4743 disas_undef_fpu(env
, s
, insn
);
4746 static void gen_fcc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
4751 c
->v2
= tcg_const_i32(0);
4753 /* TODO: Raise BSUN exception. */
4754 fpsr
= tcg_temp_new();
4755 gen_load_fcr(s
, fpsr
, M68K_FPSR
);
4758 case 16: /* Signaling False */
4760 c
->tcond
= TCG_COND_NEVER
;
4762 case 1: /* EQual Z */
4763 case 17: /* Signaling EQual Z */
4764 c
->v1
= tcg_temp_new();
4766 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
4767 c
->tcond
= TCG_COND_NE
;
4769 case 2: /* Ordered Greater Than !(A || Z || N) */
4770 case 18: /* Greater Than !(A || Z || N) */
4771 c
->v1
= tcg_temp_new();
4773 tcg_gen_andi_i32(c
->v1
, fpsr
,
4774 FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
4775 c
->tcond
= TCG_COND_EQ
;
4777 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
4778 case 19: /* Greater than or Equal Z || !(A || N) */
4779 c
->v1
= tcg_temp_new();
4781 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
4782 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
4783 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_Z
| FPSR_CC_N
);
4784 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
4785 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
4786 c
->tcond
= TCG_COND_NE
;
4788 case 4: /* Ordered Less Than !(!N || A || Z); */
4789 case 20: /* Less Than !(!N || A || Z); */
4790 c
->v1
= tcg_temp_new();
4792 tcg_gen_xori_i32(c
->v1
, fpsr
, FPSR_CC_N
);
4793 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_N
| FPSR_CC_A
| FPSR_CC_Z
);
4794 c
->tcond
= TCG_COND_EQ
;
4796 case 5: /* Ordered Less than or Equal Z || (N && !A) */
4797 case 21: /* Less than or Equal Z || (N && !A) */
4798 c
->v1
= tcg_temp_new();
4800 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
4801 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
4802 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
4803 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_Z
| FPSR_CC_N
);
4804 c
->tcond
= TCG_COND_NE
;
4806 case 6: /* Ordered Greater or Less than !(A || Z) */
4807 case 22: /* Greater or Less than !(A || Z) */
4808 c
->v1
= tcg_temp_new();
4810 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
4811 c
->tcond
= TCG_COND_EQ
;
4813 case 7: /* Ordered !A */
4814 case 23: /* Greater, Less or Equal !A */
4815 c
->v1
= tcg_temp_new();
4817 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
4818 c
->tcond
= TCG_COND_EQ
;
4820 case 8: /* Unordered A */
4821 case 24: /* Not Greater, Less or Equal A */
4822 c
->v1
= tcg_temp_new();
4824 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
4825 c
->tcond
= TCG_COND_NE
;
4827 case 9: /* Unordered or Equal A || Z */
4828 case 25: /* Not Greater or Less then A || Z */
4829 c
->v1
= tcg_temp_new();
4831 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
4832 c
->tcond
= TCG_COND_NE
;
4834 case 10: /* Unordered or Greater Than A || !(N || Z)) */
4835 case 26: /* Not Less or Equal A || !(N || Z)) */
4836 c
->v1
= tcg_temp_new();
4838 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
4839 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
4840 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_A
| FPSR_CC_N
);
4841 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
4842 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
4843 c
->tcond
= TCG_COND_NE
;
4845 case 11: /* Unordered or Greater or Equal A || Z || !N */
4846 case 27: /* Not Less Than A || Z || !N */
4847 c
->v1
= tcg_temp_new();
4849 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
4850 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
4851 c
->tcond
= TCG_COND_NE
;
4853 case 12: /* Unordered or Less Than A || (N && !Z) */
4854 case 28: /* Not Greater than or Equal A || (N && !Z) */
4855 c
->v1
= tcg_temp_new();
4857 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
4858 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
4859 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
4860 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_A
| FPSR_CC_N
);
4861 c
->tcond
= TCG_COND_NE
;
4863 case 13: /* Unordered or Less or Equal A || Z || N */
4864 case 29: /* Not Greater Than A || Z || N */
4865 c
->v1
= tcg_temp_new();
4867 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
4868 c
->tcond
= TCG_COND_NE
;
4870 case 14: /* Not Equal !Z */
4871 case 30: /* Signaling Not Equal !Z */
4872 c
->v1
= tcg_temp_new();
4874 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
4875 c
->tcond
= TCG_COND_EQ
;
4878 case 31: /* Signaling True */
4880 c
->tcond
= TCG_COND_ALWAYS
;
4883 tcg_temp_free(fpsr
);
4886 static void gen_fjmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
4890 gen_fcc_cond(&c
, s
, cond
);
4891 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
4902 offset
= (int16_t)read_im16(env
, s
);
4903 if (insn
& (1 << 6)) {
4904 offset
= (offset
<< 16) | read_im16(env
, s
);
4907 l1
= gen_new_label();
4909 gen_fjmpcc(s
, insn
& 0x3f, l1
);
4910 gen_jmp_tb(s
, 0, s
->pc
);
4912 gen_jmp_tb(s
, 1, base
+ offset
);
4922 ext
= read_im16(env
, s
);
4924 gen_fcc_cond(&c
, s
, cond
);
4926 tmp
= tcg_temp_new();
4927 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
4930 tcg_gen_neg_i32(tmp
, tmp
);
4931 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
4935 DISAS_INSN(frestore
)
4937 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
4939 /* TODO: Implement frestore. */
4940 cpu_abort(CPU(cpu
), "FRESTORE not implemented");
4945 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
4947 /* TODO: Implement fsave. */
4948 cpu_abort(CPU(cpu
), "FSAVE not implemented");
4951 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
4953 TCGv tmp
= tcg_temp_new();
4954 if (s
->env
->macsr
& MACSR_FI
) {
4956 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
4958 tcg_gen_shli_i32(tmp
, val
, 16);
4959 } else if (s
->env
->macsr
& MACSR_SU
) {
4961 tcg_gen_sari_i32(tmp
, val
, 16);
4963 tcg_gen_ext16s_i32(tmp
, val
);
4966 tcg_gen_shri_i32(tmp
, val
, 16);
4968 tcg_gen_ext16u_i32(tmp
, val
);
4973 static void gen_mac_clear_flags(void)
4975 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
4976 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
4992 s
->mactmp
= tcg_temp_new_i64();
4996 ext
= read_im16(env
, s
);
4998 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
4999 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
5000 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
5001 disas_undef(env
, s
, insn
);
5005 /* MAC with load. */
5006 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
5007 addr
= tcg_temp_new();
5008 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
5009 /* Load the value now to ensure correct exception behavior.
5010 Perform writeback after reading the MAC inputs. */
5011 loadval
= gen_load(s
, OS_LONG
, addr
, 0);
5014 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
5015 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
5017 loadval
= addr
= NULL_QREG
;
5018 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5019 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5022 gen_mac_clear_flags();
5025 /* Disabled because conditional branches clobber temporary vars. */
5026 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
5027 /* Skip the multiply if we know we will ignore it. */
5028 l1
= gen_new_label();
5029 tmp
= tcg_temp_new();
5030 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
5031 gen_op_jmp_nz32(tmp
, l1
);
5035 if ((ext
& 0x0800) == 0) {
5037 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
5038 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
5040 if (s
->env
->macsr
& MACSR_FI
) {
5041 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
5043 if (s
->env
->macsr
& MACSR_SU
)
5044 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
5046 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
5047 switch ((ext
>> 9) & 3) {
5049 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
5052 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
5058 /* Save the overflow flag from the multiply. */
5059 saved_flags
= tcg_temp_new();
5060 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
5062 saved_flags
= NULL_QREG
;
5066 /* Disabled because conditional branches clobber temporary vars. */
5067 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
5068 /* Skip the accumulate if the value is already saturated. */
5069 l1
= gen_new_label();
5070 tmp
= tcg_temp_new();
5071 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5072 gen_op_jmp_nz32(tmp
, l1
);
5077 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5079 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5081 if (s
->env
->macsr
& MACSR_FI
)
5082 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5083 else if (s
->env
->macsr
& MACSR_SU
)
5084 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5086 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5089 /* Disabled because conditional branches clobber temporary vars. */
5095 /* Dual accumulate variant. */
5096 acc
= (ext
>> 2) & 3;
5097 /* Restore the overflow flag from the multiplier. */
5098 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
5100 /* Disabled because conditional branches clobber temporary vars. */
5101 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
5102 /* Skip the accumulate if the value is already saturated. */
5103 l1
= gen_new_label();
5104 tmp
= tcg_temp_new();
5105 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5106 gen_op_jmp_nz32(tmp
, l1
);
5110 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5112 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5113 if (s
->env
->macsr
& MACSR_FI
)
5114 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5115 else if (s
->env
->macsr
& MACSR_SU
)
5116 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5118 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5120 /* Disabled because conditional branches clobber temporary vars. */
5125 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
5129 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5130 tcg_gen_mov_i32(rw
, loadval
);
5131 /* FIXME: Should address writeback happen with the masked or
5133 switch ((insn
>> 3) & 7) {
5134 case 3: /* Post-increment. */
5135 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
5137 case 4: /* Pre-decrement. */
5138 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5143 DISAS_INSN(from_mac
)
5149 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5150 accnum
= (insn
>> 9) & 3;
5151 acc
= MACREG(accnum
);
5152 if (s
->env
->macsr
& MACSR_FI
) {
5153 gen_helper_get_macf(rx
, cpu_env
, acc
);
5154 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
5155 tcg_gen_extrl_i64_i32(rx
, acc
);
5156 } else if (s
->env
->macsr
& MACSR_SU
) {
5157 gen_helper_get_macs(rx
, acc
);
5159 gen_helper_get_macu(rx
, acc
);
5162 tcg_gen_movi_i64(acc
, 0);
5163 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5167 DISAS_INSN(move_mac
)
5169 /* FIXME: This can be done without a helper. */
5173 dest
= tcg_const_i32((insn
>> 9) & 3);
5174 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
5175 gen_mac_clear_flags();
5176 gen_helper_mac_set_flags(cpu_env
, dest
);
5179 DISAS_INSN(from_macsr
)
5183 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5184 tcg_gen_mov_i32(reg
, QREG_MACSR
);
5187 DISAS_INSN(from_mask
)
5190 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5191 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
5194 DISAS_INSN(from_mext
)
5198 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5199 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5200 if (s
->env
->macsr
& MACSR_FI
)
5201 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
5203 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
5206 DISAS_INSN(macsr_to_ccr
)
5208 TCGv tmp
= tcg_temp_new();
5209 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 0xf);
5210 gen_helper_set_sr(cpu_env
, tmp
);
5212 set_cc_op(s
, CC_OP_FLAGS
);
5220 accnum
= (insn
>> 9) & 3;
5221 acc
= MACREG(accnum
);
5222 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5223 if (s
->env
->macsr
& MACSR_FI
) {
5224 tcg_gen_ext_i32_i64(acc
, val
);
5225 tcg_gen_shli_i64(acc
, acc
, 8);
5226 } else if (s
->env
->macsr
& MACSR_SU
) {
5227 tcg_gen_ext_i32_i64(acc
, val
);
5229 tcg_gen_extu_i32_i64(acc
, val
);
5231 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5232 gen_mac_clear_flags();
5233 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
5236 DISAS_INSN(to_macsr
)
5239 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5240 gen_helper_set_macsr(cpu_env
, val
);
5247 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5248 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
5255 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5256 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5257 if (s
->env
->macsr
& MACSR_FI
)
5258 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
5259 else if (s
->env
->macsr
& MACSR_SU
)
5260 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
5262 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
5265 static disas_proc opcode_table
[65536];
5268 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
5274 /* Sanity check. All set bits must be included in the mask. */
5275 if (opcode
& ~mask
) {
5277 "qemu internal error: bogus opcode definition %04x/%04x\n",
5281 /* This could probably be cleverer. For now just optimize the case where
5282 the top bits are known. */
5283 /* Find the first zero bit in the mask. */
5285 while ((i
& mask
) != 0)
5287 /* Iterate over all combinations of this and lower bits. */
5292 from
= opcode
& ~(i
- 1);
5294 for (i
= from
; i
< to
; i
++) {
5295 if ((i
& mask
) == opcode
)
5296 opcode_table
[i
] = proc
;
5300 /* Register m68k opcode handlers. Order is important.
5301 Later insn override earlier ones. */
5302 void register_m68k_insns (CPUM68KState
*env
)
5304 /* Build the opcode table only once to avoid
5305 multithreading issues. */
5306 if (opcode_table
[0] != NULL
) {
5310 /* use BASE() for instruction available
5311 * for CF_ISA_A and M68000.
5313 #define BASE(name, opcode, mask) \
5314 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5315 #define INSN(name, opcode, mask, feature) do { \
5316 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5317 BASE(name, opcode, mask); \
5319 BASE(undef
, 0000, 0000);
5320 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
5321 INSN(arith_im
, 0000, ff00
, M68000
);
5322 INSN(undef
, 00c0
, ffc0
, M68000
);
5323 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
5324 BASE(bitop_reg
, 0100, f1c0
);
5325 BASE(bitop_reg
, 0140, f1c0
);
5326 BASE(bitop_reg
, 0180, f1c0
);
5327 BASE(bitop_reg
, 01c0
, f1c0
);
5328 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
5329 INSN(arith_im
, 0200, ff00
, M68000
);
5330 INSN(undef
, 02c0
, ffc0
, M68000
);
5331 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
5332 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
5333 INSN(arith_im
, 0400, ff00
, M68000
);
5334 INSN(undef
, 04c0
, ffc0
, M68000
);
5335 INSN(arith_im
, 0600, ff00
, M68000
);
5336 INSN(undef
, 06c0
, ffc0
, M68000
);
5337 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
5338 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
5339 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
5340 INSN(arith_im
, 0c00
, ff00
, M68000
);
5341 BASE(bitop_im
, 0800, ffc0
);
5342 BASE(bitop_im
, 0840, ffc0
);
5343 BASE(bitop_im
, 0880, ffc0
);
5344 BASE(bitop_im
, 08c0
, ffc0
);
5345 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
5346 INSN(arith_im
, 0a00
, ff00
, M68000
);
5347 INSN(cas
, 0ac0
, ffc0
, CAS
);
5348 INSN(cas
, 0cc0
, ffc0
, CAS
);
5349 INSN(cas
, 0ec0
, ffc0
, CAS
);
5350 INSN(cas2w
, 0cfc
, ffff
, CAS
);
5351 INSN(cas2l
, 0efc
, ffff
, CAS
);
5352 BASE(move
, 1000, f000
);
5353 BASE(move
, 2000, f000
);
5354 BASE(move
, 3000, f000
);
5355 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
5356 INSN(negx
, 4080, fff8
, CF_ISA_A
);
5357 INSN(negx
, 4000, ff00
, M68000
);
5358 INSN(undef
, 40c0
, ffc0
, M68000
);
5359 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
5360 INSN(move_from_sr
, 40c0
, ffc0
, M68000
);
5361 BASE(lea
, 41c0
, f1c0
);
5362 BASE(clr
, 4200, ff00
);
5363 BASE(undef
, 42c0
, ffc0
);
5364 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
5365 INSN(move_from_ccr
, 42c0
, ffc0
, M68000
);
5366 INSN(neg
, 4480, fff8
, CF_ISA_A
);
5367 INSN(neg
, 4400, ff00
, M68000
);
5368 INSN(undef
, 44c0
, ffc0
, M68000
);
5369 BASE(move_to_ccr
, 44c0
, ffc0
);
5370 INSN(not, 4680, fff8
, CF_ISA_A
);
5371 INSN(not, 4600, ff00
, M68000
);
5372 INSN(undef
, 46c0
, ffc0
, M68000
);
5373 INSN(move_to_sr
, 46c0
, ffc0
, CF_ISA_A
);
5374 INSN(nbcd
, 4800, ffc0
, M68000
);
5375 INSN(linkl
, 4808, fff8
, M68000
);
5376 BASE(pea
, 4840, ffc0
);
5377 BASE(swap
, 4840, fff8
);
5378 INSN(bkpt
, 4848, fff8
, BKPT
);
5379 INSN(movem
, 48d0
, fbf8
, CF_ISA_A
);
5380 INSN(movem
, 48e8
, fbf8
, CF_ISA_A
);
5381 INSN(movem
, 4880, fb80
, M68000
);
5382 BASE(ext
, 4880, fff8
);
5383 BASE(ext
, 48c0
, fff8
);
5384 BASE(ext
, 49c0
, fff8
);
5385 BASE(tst
, 4a00
, ff00
);
5386 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
5387 INSN(tas
, 4ac0
, ffc0
, M68000
);
5388 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
5389 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
5390 BASE(illegal
, 4afc
, ffff
);
5391 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
5392 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
5393 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
5394 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
5395 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
5396 BASE(trap
, 4e40
, fff0
);
5397 BASE(link
, 4e50
, fff8
);
5398 BASE(unlk
, 4e58
, fff8
);
5399 INSN(move_to_usp
, 4e60
, fff8
, USP
);
5400 INSN(move_from_usp
, 4e68
, fff8
, USP
);
5401 BASE(nop
, 4e71
, ffff
);
5402 BASE(stop
, 4e72
, ffff
);
5403 BASE(rte
, 4e73
, ffff
);
5404 INSN(rtd
, 4e74
, ffff
, RTD
);
5405 BASE(rts
, 4e75
, ffff
);
5406 INSN(movec
, 4e7b
, ffff
, CF_ISA_A
);
5407 BASE(jump
, 4e80
, ffc0
);
5408 BASE(jump
, 4ec0
, ffc0
);
5409 INSN(addsubq
, 5000, f080
, M68000
);
5410 BASE(addsubq
, 5080, f0c0
);
5411 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
); /* Scc.B Dx */
5412 INSN(scc
, 50c0
, f0c0
, M68000
); /* Scc.B <EA> */
5413 INSN(dbcc
, 50c8
, f0f8
, M68000
);
5414 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
5416 /* Branch instructions. */
5417 BASE(branch
, 6000, f000
);
5418 /* Disable long branch instructions, then add back the ones we want. */
5419 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
5420 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
5421 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
5422 INSN(branch
, 60ff
, ffff
, BRAL
);
5423 INSN(branch
, 60ff
, f0ff
, BCCL
);
5425 BASE(moveq
, 7000, f100
);
5426 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
5427 BASE(or, 8000, f000
);
5428 BASE(divw
, 80c0
, f0c0
);
5429 INSN(sbcd_reg
, 8100, f1f8
, M68000
);
5430 INSN(sbcd_mem
, 8108, f1f8
, M68000
);
5431 BASE(addsub
, 9000, f000
);
5432 INSN(undef
, 90c0
, f0c0
, CF_ISA_A
);
5433 INSN(subx_reg
, 9180, f1f8
, CF_ISA_A
);
5434 INSN(subx_reg
, 9100, f138
, M68000
);
5435 INSN(subx_mem
, 9108, f138
, M68000
);
5436 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
5437 INSN(suba
, 90c0
, f0c0
, M68000
);
5439 BASE(undef_mac
, a000
, f000
);
5440 INSN(mac
, a000
, f100
, CF_EMAC
);
5441 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
5442 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
5443 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
5444 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
5445 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
5446 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
5447 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
5448 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
5449 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
5450 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
5452 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
5453 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
5454 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
5455 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
5456 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
5457 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
5458 INSN(cmp
, b000
, f100
, M68000
);
5459 INSN(eor
, b100
, f100
, M68000
);
5460 INSN(cmpm
, b108
, f138
, M68000
);
5461 INSN(cmpa
, b0c0
, f0c0
, M68000
);
5462 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
5463 BASE(and, c000
, f000
);
5464 INSN(exg_dd
, c140
, f1f8
, M68000
);
5465 INSN(exg_aa
, c148
, f1f8
, M68000
);
5466 INSN(exg_da
, c188
, f1f8
, M68000
);
5467 BASE(mulw
, c0c0
, f0c0
);
5468 INSN(abcd_reg
, c100
, f1f8
, M68000
);
5469 INSN(abcd_mem
, c108
, f1f8
, M68000
);
5470 BASE(addsub
, d000
, f000
);
5471 INSN(undef
, d0c0
, f0c0
, CF_ISA_A
);
5472 INSN(addx_reg
, d180
, f1f8
, CF_ISA_A
);
5473 INSN(addx_reg
, d100
, f138
, M68000
);
5474 INSN(addx_mem
, d108
, f138
, M68000
);
5475 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
5476 INSN(adda
, d0c0
, f0c0
, M68000
);
5477 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
5478 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
5479 INSN(shift8_im
, e000
, f0f0
, M68000
);
5480 INSN(shift16_im
, e040
, f0f0
, M68000
);
5481 INSN(shift_im
, e080
, f0f0
, M68000
);
5482 INSN(shift8_reg
, e020
, f0f0
, M68000
);
5483 INSN(shift16_reg
, e060
, f0f0
, M68000
);
5484 INSN(shift_reg
, e0a0
, f0f0
, M68000
);
5485 INSN(shift_mem
, e0c0
, fcc0
, M68000
);
5486 INSN(rotate_im
, e090
, f0f0
, M68000
);
5487 INSN(rotate8_im
, e010
, f0f0
, M68000
);
5488 INSN(rotate16_im
, e050
, f0f0
, M68000
);
5489 INSN(rotate_reg
, e0b0
, f0f0
, M68000
);
5490 INSN(rotate8_reg
, e030
, f0f0
, M68000
);
5491 INSN(rotate16_reg
, e070
, f0f0
, M68000
);
5492 INSN(rotate_mem
, e4c0
, fcc0
, M68000
);
5493 INSN(bfext_mem
, e9c0
, fdc0
, BITFIELD
); /* bfextu & bfexts */
5494 INSN(bfext_reg
, e9c0
, fdf8
, BITFIELD
);
5495 INSN(bfins_mem
, efc0
, ffc0
, BITFIELD
);
5496 INSN(bfins_reg
, efc0
, fff8
, BITFIELD
);
5497 INSN(bfop_mem
, eac0
, ffc0
, BITFIELD
); /* bfchg */
5498 INSN(bfop_reg
, eac0
, fff8
, BITFIELD
); /* bfchg */
5499 INSN(bfop_mem
, ecc0
, ffc0
, BITFIELD
); /* bfclr */
5500 INSN(bfop_reg
, ecc0
, fff8
, BITFIELD
); /* bfclr */
5501 INSN(bfop_mem
, edc0
, ffc0
, BITFIELD
); /* bfffo */
5502 INSN(bfop_reg
, edc0
, fff8
, BITFIELD
); /* bfffo */
5503 INSN(bfop_mem
, eec0
, ffc0
, BITFIELD
); /* bfset */
5504 INSN(bfop_reg
, eec0
, fff8
, BITFIELD
); /* bfset */
5505 INSN(bfop_mem
, e8c0
, ffc0
, BITFIELD
); /* bftst */
5506 INSN(bfop_reg
, e8c0
, fff8
, BITFIELD
); /* bftst */
5507 BASE(undef_fpu
, f000
, f000
);
5508 INSN(fpu
, f200
, ffc0
, CF_FPU
);
5509 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
5510 INSN(frestore
, f340
, ffc0
, CF_FPU
);
5511 INSN(fsave
, f300
, ffc0
, CF_FPU
);
5512 INSN(fpu
, f200
, ffc0
, FPU
);
5513 INSN(fscc
, f240
, ffc0
, FPU
);
5514 INSN(fbcc
, f280
, ff80
, FPU
);
5515 INSN(frestore
, f340
, ffc0
, FPU
);
5516 INSN(fsave
, f300
, ffc0
, FPU
);
5517 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
5518 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
5519 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
5520 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
5524 /* ??? Some of this implementation is not exception safe. We should always
5525 write back the result to memory before setting the condition codes. */
5526 static void disas_m68k_insn(CPUM68KState
* env
, DisasContext
*s
)
5528 uint16_t insn
= read_im16(env
, s
);
5529 opcode_table
[insn
](env
, s
, insn
);
5533 /* generate intermediate code for basic block 'tb'. */
5534 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
)
5536 CPUM68KState
*env
= cs
->env_ptr
;
5537 DisasContext dc1
, *dc
= &dc1
;
5538 target_ulong pc_start
;
5543 /* generate intermediate code */
5549 dc
->is_jmp
= DISAS_NEXT
;
5551 dc
->cc_op
= CC_OP_DYNAMIC
;
5552 dc
->cc_op_synced
= 1;
5553 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
5554 dc
->user
= (env
->sr
& SR_S
) == 0;
5556 dc
->writeback_mask
= 0;
5558 max_insns
= tb_cflags(tb
) & CF_COUNT_MASK
;
5559 if (max_insns
== 0) {
5560 max_insns
= CF_COUNT_MASK
;
5562 if (max_insns
> TCG_MAX_INSNS
) {
5563 max_insns
= TCG_MAX_INSNS
;
5568 pc_offset
= dc
->pc
- pc_start
;
5569 gen_throws_exception
= NULL
;
5570 tcg_gen_insn_start(dc
->pc
, dc
->cc_op
);
5573 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
5574 gen_exception(dc
, dc
->pc
, EXCP_DEBUG
);
5575 dc
->is_jmp
= DISAS_JUMP
;
5576 /* The address covered by the breakpoint must be included in
5577 [tb->pc, tb->pc + tb->size) in order to for it to be
5578 properly cleared -- thus we increment the PC here so that
5579 the logic setting tb->size below does the right thing. */
5584 if (num_insns
== max_insns
&& (tb_cflags(tb
) & CF_LAST_IO
)) {
5588 dc
->insn_pc
= dc
->pc
;
5589 disas_m68k_insn(env
, dc
);
5590 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
5591 !cs
->singlestep_enabled
&&
5593 (pc_offset
) < (TARGET_PAGE_SIZE
- 32) &&
5594 num_insns
< max_insns
);
5596 if (tb_cflags(tb
) & CF_LAST_IO
)
5598 if (unlikely(cs
->singlestep_enabled
)) {
5599 /* Make sure the pc is updated, and raise a debug exception. */
5602 tcg_gen_movi_i32(QREG_PC
, dc
->pc
);
5604 gen_helper_raise_exception(cpu_env
, tcg_const_i32(EXCP_DEBUG
));
5606 switch(dc
->is_jmp
) {
5609 gen_jmp_tb(dc
, 0, dc
->pc
);
5615 /* indicate that the hash table must be used to find the next TB */
5619 /* nothing more to generate */
5623 gen_tb_end(tb
, num_insns
);
5626 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
5627 && qemu_log_in_addr_range(pc_start
)) {
5629 qemu_log("----------------\n");
5630 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
5631 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
, 0);
5636 tb
->size
= dc
->pc
- pc_start
;
5637 tb
->icount
= num_insns
;
5640 static double floatx80_to_double(CPUM68KState
*env
, uint16_t high
, uint64_t low
)
5642 floatx80 a
= { .high
= high
, .low
= low
};
5648 u
.f64
= floatx80_to_float64(a
, &env
->fp_status
);
5652 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
5655 M68kCPU
*cpu
= M68K_CPU(cs
);
5656 CPUM68KState
*env
= &cpu
->env
;
5659 for (i
= 0; i
< 8; i
++) {
5660 cpu_fprintf(f
, "D%d = %08x A%d = %08x "
5661 "F%d = %04x %016"PRIx64
" (%12g)\n",
5662 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
5663 i
, env
->fregs
[i
].l
.upper
, env
->fregs
[i
].l
.lower
,
5664 floatx80_to_double(env
, env
->fregs
[i
].l
.upper
,
5665 env
->fregs
[i
].l
.lower
));
5667 cpu_fprintf (f
, "PC = %08x ", env
->pc
);
5668 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
5669 cpu_fprintf(f
, "SR = %04x %c%c%c%c%c ", sr
, (sr
& CCF_X
) ? 'X' : '-',
5670 (sr
& CCF_N
) ? 'N' : '-', (sr
& CCF_Z
) ? 'Z' : '-',
5671 (sr
& CCF_V
) ? 'V' : '-', (sr
& CCF_C
) ? 'C' : '-');
5672 cpu_fprintf(f
, "FPSR = %08x %c%c%c%c ", env
->fpsr
,
5673 (env
->fpsr
& FPSR_CC_A
) ? 'A' : '-',
5674 (env
->fpsr
& FPSR_CC_I
) ? 'I' : '-',
5675 (env
->fpsr
& FPSR_CC_Z
) ? 'Z' : '-',
5676 (env
->fpsr
& FPSR_CC_N
) ? 'N' : '-');
5677 cpu_fprintf(f
, "\n "
5678 "FPCR = %04x ", env
->fpcr
);
5679 switch (env
->fpcr
& FPCR_PREC_MASK
) {
5681 cpu_fprintf(f
, "X ");
5684 cpu_fprintf(f
, "S ");
5687 cpu_fprintf(f
, "D ");
5690 switch (env
->fpcr
& FPCR_RND_MASK
) {
5692 cpu_fprintf(f
, "RN ");
5695 cpu_fprintf(f
, "RZ ");
5698 cpu_fprintf(f
, "RM ");
5701 cpu_fprintf(f
, "RP ");
5706 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,
5709 int cc_op
= data
[1];
5711 if (cc_op
!= CC_OP_DYNAMIC
) {