4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
27 #include "qemu/qemu-print.h"
28 #include "exec/cpu_ldst.h"
29 #include "exec/translator.h"
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
35 #include "fpu/softfloat.h"
38 //#define DEBUG_DISPATCH 1
40 #define DEFO32(name, offset) static TCGv QREG_##name;
41 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
46 static TCGv_i32 cpu_halted
;
47 static TCGv_i32 cpu_exception_index
;
49 static char cpu_reg_names
[2 * 8 * 3 + 5 * 4];
50 static TCGv cpu_dregs
[8];
51 static TCGv cpu_aregs
[8];
52 static TCGv_i64 cpu_macc
[4];
54 #define REG(insn, pos) (((insn) >> (pos)) & 7)
55 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
56 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
57 #define MACREG(acc) cpu_macc[acc]
58 #define QREG_SP get_areg(s, 7)
60 static TCGv NULL_QREG
;
61 #define IS_NULL_QREG(t) (t == NULL_QREG)
62 /* Used to distinguish stores from bad addressing modes. */
63 static TCGv store_dummy
;
65 #include "exec/gen-icount.h"
67 void m68k_tcg_init(void)
72 #define DEFO32(name, offset) \
73 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
74 offsetof(CPUM68KState, offset), #name);
75 #define DEFO64(name, offset) \
76 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
77 offsetof(CPUM68KState, offset), #name);
82 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
83 -offsetof(M68kCPU
, env
) +
84 offsetof(CPUState
, halted
), "HALTED");
85 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
86 -offsetof(M68kCPU
, env
) +
87 offsetof(CPUState
, exception_index
),
91 for (i
= 0; i
< 8; i
++) {
93 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
94 offsetof(CPUM68KState
, dregs
[i
]), p
);
97 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
98 offsetof(CPUM68KState
, aregs
[i
]), p
);
101 for (i
= 0; i
< 4; i
++) {
102 sprintf(p
, "ACC%d", i
);
103 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
104 offsetof(CPUM68KState
, macc
[i
]), p
);
108 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
109 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
112 /* internal defines */
113 typedef struct DisasContext
{
114 DisasContextBase base
;
117 target_ulong pc_prev
;
118 CCOp cc_op
; /* Current CC operation */
124 #define MAX_TO_RELEASE 8
126 TCGv release
[MAX_TO_RELEASE
];
130 static void init_release_array(DisasContext
*s
)
132 #ifdef CONFIG_DEBUG_TCG
133 memset(s
->release
, 0, sizeof(s
->release
));
135 s
->release_count
= 0;
138 static void do_release(DisasContext
*s
)
141 for (i
= 0; i
< s
->release_count
; i
++) {
142 tcg_temp_free(s
->release
[i
]);
144 init_release_array(s
);
147 static TCGv
mark_to_release(DisasContext
*s
, TCGv tmp
)
149 g_assert(s
->release_count
< MAX_TO_RELEASE
);
150 return s
->release
[s
->release_count
++] = tmp
;
153 static TCGv
get_areg(DisasContext
*s
, unsigned regno
)
155 if (s
->writeback_mask
& (1 << regno
)) {
156 return s
->writeback
[regno
];
158 return cpu_aregs
[regno
];
162 static void delay_set_areg(DisasContext
*s
, unsigned regno
,
163 TCGv val
, bool give_temp
)
165 if (s
->writeback_mask
& (1 << regno
)) {
167 tcg_temp_free(s
->writeback
[regno
]);
168 s
->writeback
[regno
] = val
;
170 tcg_gen_mov_i32(s
->writeback
[regno
], val
);
173 s
->writeback_mask
|= 1 << regno
;
175 s
->writeback
[regno
] = val
;
177 TCGv tmp
= tcg_temp_new();
178 s
->writeback
[regno
] = tmp
;
179 tcg_gen_mov_i32(tmp
, val
);
184 static void do_writebacks(DisasContext
*s
)
186 unsigned mask
= s
->writeback_mask
;
188 s
->writeback_mask
= 0;
190 unsigned regno
= ctz32(mask
);
191 tcg_gen_mov_i32(cpu_aregs
[regno
], s
->writeback
[regno
]);
192 tcg_temp_free(s
->writeback
[regno
]);
198 /* is_jmp field values */
199 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
200 #define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
202 #if defined(CONFIG_USER_ONLY)
205 #define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S))
206 #define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \
207 MMU_KERNEL_IDX : MMU_USER_IDX)
208 #define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \
209 MMU_KERNEL_IDX : MMU_USER_IDX)
212 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
214 #ifdef DEBUG_DISPATCH
215 #define DISAS_INSN(name) \
216 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
218 static void disas_##name(CPUM68KState *env, DisasContext *s, \
221 qemu_log("Dispatch " #name "\n"); \
222 real_disas_##name(env, s, insn); \
224 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
227 #define DISAS_INSN(name) \
228 static void disas_##name(CPUM68KState *env, DisasContext *s, \
232 static const uint8_t cc_op_live
[CC_OP_NB
] = {
233 [CC_OP_DYNAMIC
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
234 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
235 [CC_OP_ADDB
... CC_OP_ADDL
] = CCF_X
| CCF_N
| CCF_V
,
236 [CC_OP_SUBB
... CC_OP_SUBL
] = CCF_X
| CCF_N
| CCF_V
,
237 [CC_OP_CMPB
... CC_OP_CMPL
] = CCF_X
| CCF_N
| CCF_V
,
238 [CC_OP_LOGIC
] = CCF_X
| CCF_N
241 static void set_cc_op(DisasContext
*s
, CCOp op
)
243 CCOp old_op
= s
->cc_op
;
253 * Discard CC computation that will no longer be used.
254 * Note that X and N are never dead.
256 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
258 tcg_gen_discard_i32(QREG_CC_C
);
261 tcg_gen_discard_i32(QREG_CC_Z
);
264 tcg_gen_discard_i32(QREG_CC_V
);
268 /* Update the CPU env CC_OP state. */
269 static void update_cc_op(DisasContext
*s
)
271 if (!s
->cc_op_synced
) {
273 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
277 /* Generate a jump to an immediate address. */
278 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
281 tcg_gen_movi_i32(QREG_PC
, dest
);
282 s
->base
.is_jmp
= DISAS_JUMP
;
285 /* Generate a jump to the address in qreg DEST. */
286 static void gen_jmp(DisasContext
*s
, TCGv dest
)
289 tcg_gen_mov_i32(QREG_PC
, dest
);
290 s
->base
.is_jmp
= DISAS_JUMP
;
293 static void gen_raise_exception(int nr
)
297 tmp
= tcg_const_i32(nr
);
298 gen_helper_raise_exception(cpu_env
, tmp
);
299 tcg_temp_free_i32(tmp
);
302 static void gen_raise_exception_format2(DisasContext
*s
, int nr
,
303 target_ulong this_pc
)
306 * Pass the address of the insn to the exception handler,
307 * for recording in the Format $2 (6-word) stack frame.
308 * Re-use mmu.ar for the purpose, since that's only valid
311 tcg_gen_st_i32(tcg_constant_i32(this_pc
), cpu_env
,
312 offsetof(CPUM68KState
, mmu
.ar
));
313 gen_raise_exception(nr
);
314 s
->base
.is_jmp
= DISAS_NORETURN
;
317 static void gen_exception(DisasContext
*s
, uint32_t dest
, int nr
)
320 tcg_gen_movi_i32(QREG_PC
, dest
);
322 gen_raise_exception(nr
);
324 s
->base
.is_jmp
= DISAS_NORETURN
;
327 static inline void gen_addr_fault(DisasContext
*s
)
329 gen_exception(s
, s
->base
.pc_next
, EXCP_ADDRESS
);
333 * Generate a load from the specified address. Narrow values are
334 * sign extended to full register width.
336 static inline TCGv
gen_load(DisasContext
*s
, int opsize
, TCGv addr
,
340 tmp
= tcg_temp_new_i32();
344 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
346 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
350 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
352 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
355 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
358 g_assert_not_reached();
363 /* Generate a store. */
364 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
369 tcg_gen_qemu_st8(val
, addr
, index
);
372 tcg_gen_qemu_st16(val
, addr
, index
);
375 tcg_gen_qemu_st32(val
, addr
, index
);
378 g_assert_not_reached();
389 * Generate an unsigned load if VAL is 0 a signed load if val is -1,
390 * otherwise generate a store.
392 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
393 ea_what what
, int index
)
395 if (what
== EA_STORE
) {
396 gen_store(s
, opsize
, addr
, val
, index
);
399 return mark_to_release(s
, gen_load(s
, opsize
, addr
,
400 what
== EA_LOADS
, index
));
404 /* Read a 16-bit immediate constant */
405 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
408 im
= translator_lduw(env
, &s
->base
, s
->pc
);
413 /* Read an 8-bit immediate constant */
414 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
416 return read_im16(env
, s
);
419 /* Read a 32-bit immediate constant. */
420 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
423 im
= read_im16(env
, s
) << 16;
424 im
|= 0xffff & read_im16(env
, s
);
428 /* Read a 64-bit immediate constant. */
429 static inline uint64_t read_im64(CPUM68KState
*env
, DisasContext
*s
)
432 im
= (uint64_t)read_im32(env
, s
) << 32;
433 im
|= (uint64_t)read_im32(env
, s
);
437 /* Calculate and address index. */
438 static TCGv
gen_addr_index(DisasContext
*s
, uint16_t ext
, TCGv tmp
)
443 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
444 if ((ext
& 0x800) == 0) {
445 tcg_gen_ext16s_i32(tmp
, add
);
448 scale
= (ext
>> 9) & 3;
450 tcg_gen_shli_i32(tmp
, add
, scale
);
457 * Handle a base + index + displacement effective address.
458 * A NULL_QREG base means pc-relative.
460 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
469 ext
= read_im16(env
, s
);
471 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
474 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
) &&
475 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
480 /* full extension word format */
481 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
484 if ((ext
& 0x30) > 0x10) {
485 /* base displacement */
486 if ((ext
& 0x30) == 0x20) {
487 bd
= (int16_t)read_im16(env
, s
);
489 bd
= read_im32(env
, s
);
494 tmp
= mark_to_release(s
, tcg_temp_new());
495 if ((ext
& 0x44) == 0) {
497 add
= gen_addr_index(s
, ext
, tmp
);
501 if ((ext
& 0x80) == 0) {
502 /* base not suppressed */
503 if (IS_NULL_QREG(base
)) {
504 base
= mark_to_release(s
, tcg_const_i32(offset
+ bd
));
507 if (!IS_NULL_QREG(add
)) {
508 tcg_gen_add_i32(tmp
, add
, base
);
514 if (!IS_NULL_QREG(add
)) {
516 tcg_gen_addi_i32(tmp
, add
, bd
);
520 add
= mark_to_release(s
, tcg_const_i32(bd
));
522 if ((ext
& 3) != 0) {
523 /* memory indirect */
524 base
= mark_to_release(s
, gen_load(s
, OS_LONG
, add
, 0, IS_USER(s
)));
525 if ((ext
& 0x44) == 4) {
526 add
= gen_addr_index(s
, ext
, tmp
);
527 tcg_gen_add_i32(tmp
, add
, base
);
533 /* outer displacement */
534 if ((ext
& 3) == 2) {
535 od
= (int16_t)read_im16(env
, s
);
537 od
= read_im32(env
, s
);
543 tcg_gen_addi_i32(tmp
, add
, od
);
548 /* brief extension word format */
549 tmp
= mark_to_release(s
, tcg_temp_new());
550 add
= gen_addr_index(s
, ext
, tmp
);
551 if (!IS_NULL_QREG(base
)) {
552 tcg_gen_add_i32(tmp
, add
, base
);
554 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
556 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
563 /* Sign or zero extend a value. */
565 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
570 tcg_gen_ext8s_i32(res
, val
);
572 tcg_gen_ext8u_i32(res
, val
);
577 tcg_gen_ext16s_i32(res
, val
);
579 tcg_gen_ext16u_i32(res
, val
);
583 tcg_gen_mov_i32(res
, val
);
586 g_assert_not_reached();
590 /* Evaluate all the CC flags. */
592 static void gen_flush_flags(DisasContext
*s
)
603 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
604 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
605 /* Compute signed overflow for addition. */
608 tcg_gen_sub_i32(t0
, QREG_CC_N
, QREG_CC_V
);
609 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_ADDB
, 1);
610 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
611 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
613 tcg_gen_andc_i32(QREG_CC_V
, t1
, QREG_CC_V
);
620 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
621 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
622 /* Compute signed overflow for subtraction. */
625 tcg_gen_add_i32(t0
, QREG_CC_N
, QREG_CC_V
);
626 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_SUBB
, 1);
627 tcg_gen_xor_i32(t1
, QREG_CC_N
, t0
);
628 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
630 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t1
);
637 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_C
, QREG_CC_N
, QREG_CC_V
);
638 tcg_gen_sub_i32(QREG_CC_Z
, QREG_CC_N
, QREG_CC_V
);
639 gen_ext(QREG_CC_Z
, QREG_CC_Z
, s
->cc_op
- CC_OP_CMPB
, 1);
640 /* Compute signed overflow for subtraction. */
642 tcg_gen_xor_i32(t0
, QREG_CC_Z
, QREG_CC_N
);
643 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, QREG_CC_N
);
644 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t0
);
646 tcg_gen_mov_i32(QREG_CC_N
, QREG_CC_Z
);
650 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
651 tcg_gen_movi_i32(QREG_CC_C
, 0);
652 tcg_gen_movi_i32(QREG_CC_V
, 0);
656 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
661 t0
= tcg_const_i32(s
->cc_op
);
662 gen_helper_flush_flags(cpu_env
, t0
);
668 /* Note that flush_flags also assigned to env->cc_op. */
669 s
->cc_op
= CC_OP_FLAGS
;
672 static inline TCGv
gen_extend(DisasContext
*s
, TCGv val
, int opsize
, int sign
)
676 if (opsize
== OS_LONG
) {
679 tmp
= mark_to_release(s
, tcg_temp_new());
680 gen_ext(tmp
, val
, opsize
, sign
);
686 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
688 gen_ext(QREG_CC_N
, val
, opsize
, 1);
689 set_cc_op(s
, CC_OP_LOGIC
);
692 static void gen_update_cc_cmp(DisasContext
*s
, TCGv dest
, TCGv src
, int opsize
)
694 tcg_gen_mov_i32(QREG_CC_N
, dest
);
695 tcg_gen_mov_i32(QREG_CC_V
, src
);
696 set_cc_op(s
, CC_OP_CMPB
+ opsize
);
699 static void gen_update_cc_add(TCGv dest
, TCGv src
, int opsize
)
701 gen_ext(QREG_CC_N
, dest
, opsize
, 1);
702 tcg_gen_mov_i32(QREG_CC_V
, src
);
705 static inline int opsize_bytes(int opsize
)
708 case OS_BYTE
: return 1;
709 case OS_WORD
: return 2;
710 case OS_LONG
: return 4;
711 case OS_SINGLE
: return 4;
712 case OS_DOUBLE
: return 8;
713 case OS_EXTENDED
: return 12;
714 case OS_PACKED
: return 12;
716 g_assert_not_reached();
720 static inline int insn_opsize(int insn
)
722 switch ((insn
>> 6) & 3) {
723 case 0: return OS_BYTE
;
724 case 1: return OS_WORD
;
725 case 2: return OS_LONG
;
727 g_assert_not_reached();
731 static inline int ext_opsize(int ext
, int pos
)
733 switch ((ext
>> pos
) & 7) {
734 case 0: return OS_LONG
;
735 case 1: return OS_SINGLE
;
736 case 2: return OS_EXTENDED
;
737 case 3: return OS_PACKED
;
738 case 4: return OS_WORD
;
739 case 5: return OS_DOUBLE
;
740 case 6: return OS_BYTE
;
742 g_assert_not_reached();
747 * Assign value to a register. If the width is less than the register width
748 * only the low part of the register is set.
750 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
755 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
756 tmp
= tcg_temp_new();
757 tcg_gen_ext8u_i32(tmp
, val
);
758 tcg_gen_or_i32(reg
, reg
, tmp
);
762 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
763 tmp
= tcg_temp_new();
764 tcg_gen_ext16u_i32(tmp
, val
);
765 tcg_gen_or_i32(reg
, reg
, tmp
);
770 tcg_gen_mov_i32(reg
, val
);
773 g_assert_not_reached();
778 * Generate code for an "effective address". Does not adjust the base
779 * register for autoincrement addressing modes.
781 static TCGv
gen_lea_mode(CPUM68KState
*env
, DisasContext
*s
,
782 int mode
, int reg0
, int opsize
)
790 case 0: /* Data register direct. */
791 case 1: /* Address register direct. */
793 case 3: /* Indirect postincrement. */
794 if (opsize
== OS_UNSIZED
) {
798 case 2: /* Indirect register */
799 return get_areg(s
, reg0
);
800 case 4: /* Indirect predecrememnt. */
801 if (opsize
== OS_UNSIZED
) {
804 reg
= get_areg(s
, reg0
);
805 tmp
= mark_to_release(s
, tcg_temp_new());
806 if (reg0
== 7 && opsize
== OS_BYTE
&&
807 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
808 tcg_gen_subi_i32(tmp
, reg
, 2);
810 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
813 case 5: /* Indirect displacement. */
814 reg
= get_areg(s
, reg0
);
815 tmp
= mark_to_release(s
, tcg_temp_new());
816 ext
= read_im16(env
, s
);
817 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
819 case 6: /* Indirect index + displacement. */
820 reg
= get_areg(s
, reg0
);
821 return gen_lea_indexed(env
, s
, reg
);
824 case 0: /* Absolute short. */
825 offset
= (int16_t)read_im16(env
, s
);
826 return mark_to_release(s
, tcg_const_i32(offset
));
827 case 1: /* Absolute long. */
828 offset
= read_im32(env
, s
);
829 return mark_to_release(s
, tcg_const_i32(offset
));
830 case 2: /* pc displacement */
832 offset
+= (int16_t)read_im16(env
, s
);
833 return mark_to_release(s
, tcg_const_i32(offset
));
834 case 3: /* pc index+displacement. */
835 return gen_lea_indexed(env
, s
, NULL_QREG
);
836 case 4: /* Immediate. */
841 /* Should never happen. */
845 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
848 int mode
= extract32(insn
, 3, 3);
849 int reg0
= REG(insn
, 0);
850 return gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
854 * Generate code to load/store a value from/into an EA. If WHAT > 0 this is
855 * a write otherwise it is a read (0 == sign extend, -1 == zero extend).
856 * ADDRP is non-null for readwrite operands.
858 static TCGv
gen_ea_mode(CPUM68KState
*env
, DisasContext
*s
, int mode
, int reg0
,
859 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
,
862 TCGv reg
, tmp
, result
;
866 case 0: /* Data register direct. */
867 reg
= cpu_dregs
[reg0
];
868 if (what
== EA_STORE
) {
869 gen_partset_reg(opsize
, reg
, val
);
872 return gen_extend(s
, reg
, opsize
, what
== EA_LOADS
);
874 case 1: /* Address register direct. */
875 reg
= get_areg(s
, reg0
);
876 if (what
== EA_STORE
) {
877 tcg_gen_mov_i32(reg
, val
);
880 return gen_extend(s
, reg
, opsize
, what
== EA_LOADS
);
882 case 2: /* Indirect register */
883 reg
= get_areg(s
, reg0
);
884 return gen_ldst(s
, opsize
, reg
, val
, what
, index
);
885 case 3: /* Indirect postincrement. */
886 reg
= get_areg(s
, reg0
);
887 result
= gen_ldst(s
, opsize
, reg
, val
, what
, index
);
888 if (what
== EA_STORE
|| !addrp
) {
889 TCGv tmp
= tcg_temp_new();
890 if (reg0
== 7 && opsize
== OS_BYTE
&&
891 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
892 tcg_gen_addi_i32(tmp
, reg
, 2);
894 tcg_gen_addi_i32(tmp
, reg
, opsize_bytes(opsize
));
896 delay_set_areg(s
, reg0
, tmp
, true);
899 case 4: /* Indirect predecrememnt. */
900 if (addrp
&& what
== EA_STORE
) {
903 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
904 if (IS_NULL_QREG(tmp
)) {
911 result
= gen_ldst(s
, opsize
, tmp
, val
, what
, index
);
912 if (what
== EA_STORE
|| !addrp
) {
913 delay_set_areg(s
, reg0
, tmp
, false);
916 case 5: /* Indirect displacement. */
917 case 6: /* Indirect index + displacement. */
919 if (addrp
&& what
== EA_STORE
) {
922 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
923 if (IS_NULL_QREG(tmp
)) {
930 return gen_ldst(s
, opsize
, tmp
, val
, what
, index
);
933 case 0: /* Absolute short. */
934 case 1: /* Absolute long. */
935 case 2: /* pc displacement */
936 case 3: /* pc index+displacement. */
938 case 4: /* Immediate. */
939 /* Sign extend values for consistency. */
942 if (what
== EA_LOADS
) {
943 offset
= (int8_t)read_im8(env
, s
);
945 offset
= read_im8(env
, s
);
949 if (what
== EA_LOADS
) {
950 offset
= (int16_t)read_im16(env
, s
);
952 offset
= read_im16(env
, s
);
956 offset
= read_im32(env
, s
);
959 g_assert_not_reached();
961 return mark_to_release(s
, tcg_const_i32(offset
));
966 /* Should never happen. */
970 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
971 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
, int index
)
973 int mode
= extract32(insn
, 3, 3);
974 int reg0
= REG(insn
, 0);
975 return gen_ea_mode(env
, s
, mode
, reg0
, opsize
, val
, addrp
, what
, index
);
978 static TCGv_ptr
gen_fp_ptr(int freg
)
980 TCGv_ptr fp
= tcg_temp_new_ptr();
981 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fregs
[freg
]));
985 static TCGv_ptr
gen_fp_result_ptr(void)
987 TCGv_ptr fp
= tcg_temp_new_ptr();
988 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fp_result
));
992 static void gen_fp_move(TCGv_ptr dest
, TCGv_ptr src
)
997 t32
= tcg_temp_new();
998 tcg_gen_ld16u_i32(t32
, src
, offsetof(FPReg
, l
.upper
));
999 tcg_gen_st16_i32(t32
, dest
, offsetof(FPReg
, l
.upper
));
1002 t64
= tcg_temp_new_i64();
1003 tcg_gen_ld_i64(t64
, src
, offsetof(FPReg
, l
.lower
));
1004 tcg_gen_st_i64(t64
, dest
, offsetof(FPReg
, l
.lower
));
1005 tcg_temp_free_i64(t64
);
1008 static void gen_load_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
,
1014 t64
= tcg_temp_new_i64();
1015 tmp
= tcg_temp_new();
1018 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
1019 gen_helper_exts32(cpu_env
, fp
, tmp
);
1022 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
1023 gen_helper_exts32(cpu_env
, fp
, tmp
);
1026 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1027 gen_helper_exts32(cpu_env
, fp
, tmp
);
1030 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1031 gen_helper_extf32(cpu_env
, fp
, tmp
);
1034 tcg_gen_qemu_ld64(t64
, addr
, index
);
1035 gen_helper_extf64(cpu_env
, fp
, t64
);
1038 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1039 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1042 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1043 tcg_gen_shri_i32(tmp
, tmp
, 16);
1044 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1045 tcg_gen_addi_i32(tmp
, addr
, 4);
1046 tcg_gen_qemu_ld64(t64
, tmp
, index
);
1047 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1051 * unimplemented data type on 68040/ColdFire
1052 * FIXME if needed for another FPU
1054 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1057 g_assert_not_reached();
1060 tcg_temp_free_i64(t64
);
1063 static void gen_store_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
,
1069 t64
= tcg_temp_new_i64();
1070 tmp
= tcg_temp_new();
1073 gen_helper_reds32(tmp
, cpu_env
, fp
);
1074 tcg_gen_qemu_st8(tmp
, addr
, index
);
1077 gen_helper_reds32(tmp
, cpu_env
, fp
);
1078 tcg_gen_qemu_st16(tmp
, addr
, index
);
1081 gen_helper_reds32(tmp
, cpu_env
, fp
);
1082 tcg_gen_qemu_st32(tmp
, addr
, index
);
1085 gen_helper_redf32(tmp
, cpu_env
, fp
);
1086 tcg_gen_qemu_st32(tmp
, addr
, index
);
1089 gen_helper_redf64(t64
, cpu_env
, fp
);
1090 tcg_gen_qemu_st64(t64
, addr
, index
);
1093 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1094 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1097 tcg_gen_ld16u_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1098 tcg_gen_shli_i32(tmp
, tmp
, 16);
1099 tcg_gen_qemu_st32(tmp
, addr
, index
);
1100 tcg_gen_addi_i32(tmp
, addr
, 4);
1101 tcg_gen_ld_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1102 tcg_gen_qemu_st64(t64
, tmp
, index
);
1106 * unimplemented data type on 68040/ColdFire
1107 * FIXME if needed for another FPU
1109 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1112 g_assert_not_reached();
1115 tcg_temp_free_i64(t64
);
1118 static void gen_ldst_fp(DisasContext
*s
, int opsize
, TCGv addr
,
1119 TCGv_ptr fp
, ea_what what
, int index
)
1121 if (what
== EA_STORE
) {
1122 gen_store_fp(s
, opsize
, addr
, fp
, index
);
1124 gen_load_fp(s
, opsize
, addr
, fp
, index
);
1128 static int gen_ea_mode_fp(CPUM68KState
*env
, DisasContext
*s
, int mode
,
1129 int reg0
, int opsize
, TCGv_ptr fp
, ea_what what
,
1132 TCGv reg
, addr
, tmp
;
1136 case 0: /* Data register direct. */
1137 reg
= cpu_dregs
[reg0
];
1138 if (what
== EA_STORE
) {
1143 gen_helper_reds32(reg
, cpu_env
, fp
);
1146 gen_helper_redf32(reg
, cpu_env
, fp
);
1149 g_assert_not_reached();
1152 tmp
= tcg_temp_new();
1155 tcg_gen_ext8s_i32(tmp
, reg
);
1156 gen_helper_exts32(cpu_env
, fp
, tmp
);
1159 tcg_gen_ext16s_i32(tmp
, reg
);
1160 gen_helper_exts32(cpu_env
, fp
, tmp
);
1163 gen_helper_exts32(cpu_env
, fp
, reg
);
1166 gen_helper_extf32(cpu_env
, fp
, reg
);
1169 g_assert_not_reached();
1174 case 1: /* Address register direct. */
1176 case 2: /* Indirect register */
1177 addr
= get_areg(s
, reg0
);
1178 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1180 case 3: /* Indirect postincrement. */
1181 addr
= cpu_aregs
[reg0
];
1182 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1183 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(opsize
));
1185 case 4: /* Indirect predecrememnt. */
1186 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1187 if (IS_NULL_QREG(addr
)) {
1190 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1191 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
1193 case 5: /* Indirect displacement. */
1194 case 6: /* Indirect index + displacement. */
1196 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1197 if (IS_NULL_QREG(addr
)) {
1200 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1204 case 0: /* Absolute short. */
1205 case 1: /* Absolute long. */
1206 case 2: /* pc displacement */
1207 case 3: /* pc index+displacement. */
1209 case 4: /* Immediate. */
1210 if (what
== EA_STORE
) {
1215 tmp
= tcg_const_i32((int8_t)read_im8(env
, s
));
1216 gen_helper_exts32(cpu_env
, fp
, tmp
);
1220 tmp
= tcg_const_i32((int16_t)read_im16(env
, s
));
1221 gen_helper_exts32(cpu_env
, fp
, tmp
);
1225 tmp
= tcg_const_i32(read_im32(env
, s
));
1226 gen_helper_exts32(cpu_env
, fp
, tmp
);
1230 tmp
= tcg_const_i32(read_im32(env
, s
));
1231 gen_helper_extf32(cpu_env
, fp
, tmp
);
1235 t64
= tcg_const_i64(read_im64(env
, s
));
1236 gen_helper_extf64(cpu_env
, fp
, t64
);
1237 tcg_temp_free_i64(t64
);
1240 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1241 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1244 tmp
= tcg_const_i32(read_im32(env
, s
) >> 16);
1245 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1247 t64
= tcg_const_i64(read_im64(env
, s
));
1248 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1249 tcg_temp_free_i64(t64
);
1253 * unimplemented data type on 68040/ColdFire
1254 * FIXME if needed for another FPU
1256 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1259 g_assert_not_reached();
1269 static int gen_ea_fp(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1270 int opsize
, TCGv_ptr fp
, ea_what what
, int index
)
1272 int mode
= extract32(insn
, 3, 3);
1273 int reg0
= REG(insn
, 0);
1274 return gen_ea_mode_fp(env
, s
, mode
, reg0
, opsize
, fp
, what
, index
);
1285 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
1291 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1292 if (op
== CC_OP_CMPB
|| op
== CC_OP_CMPW
|| op
== CC_OP_CMPL
) {
1299 tcond
= TCG_COND_LEU
;
1303 tcond
= TCG_COND_LTU
;
1307 tcond
= TCG_COND_EQ
;
1312 c
->v2
= tcg_const_i32(0);
1313 c
->v1
= tmp
= tcg_temp_new();
1314 tcg_gen_sub_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1315 gen_ext(tmp
, tmp
, op
- CC_OP_CMPB
, 1);
1319 tcond
= TCG_COND_LT
;
1323 tcond
= TCG_COND_LE
;
1330 c
->v2
= tcg_const_i32(0);
1336 tcond
= TCG_COND_NEVER
;
1338 case 14: /* GT (!(Z || (N ^ V))) */
1339 case 15: /* LE (Z || (N ^ V)) */
1341 * Logic operations clear V, which simplifies LE to (Z || N),
1342 * and since Z and N are co-located, this becomes a normal
1345 if (op
== CC_OP_LOGIC
) {
1347 tcond
= TCG_COND_LE
;
1351 case 12: /* GE (!(N ^ V)) */
1352 case 13: /* LT (N ^ V) */
1353 /* Logic operations clear V, which simplifies this to N. */
1354 if (op
!= CC_OP_LOGIC
) {
1358 case 10: /* PL (!N) */
1359 case 11: /* MI (N) */
1360 /* Several cases represent N normally. */
1361 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1362 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1363 op
== CC_OP_LOGIC
) {
1365 tcond
= TCG_COND_LT
;
1369 case 6: /* NE (!Z) */
1370 case 7: /* EQ (Z) */
1371 /* Some cases fold Z into N. */
1372 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1373 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1374 op
== CC_OP_LOGIC
) {
1375 tcond
= TCG_COND_EQ
;
1380 case 4: /* CC (!C) */
1381 case 5: /* CS (C) */
1382 /* Some cases fold C into X. */
1383 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1384 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
) {
1385 tcond
= TCG_COND_NE
;
1390 case 8: /* VC (!V) */
1391 case 9: /* VS (V) */
1392 /* Logic operations clear V and C. */
1393 if (op
== CC_OP_LOGIC
) {
1394 tcond
= TCG_COND_NEVER
;
1401 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1408 /* Invalid, or handled above. */
1410 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1411 case 3: /* LS (C || Z) */
1412 c
->v1
= tmp
= tcg_temp_new();
1414 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1415 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
1416 tcond
= TCG_COND_NE
;
1418 case 4: /* CC (!C) */
1419 case 5: /* CS (C) */
1421 tcond
= TCG_COND_NE
;
1423 case 6: /* NE (!Z) */
1424 case 7: /* EQ (Z) */
1426 tcond
= TCG_COND_EQ
;
1428 case 8: /* VC (!V) */
1429 case 9: /* VS (V) */
1431 tcond
= TCG_COND_LT
;
1433 case 10: /* PL (!N) */
1434 case 11: /* MI (N) */
1436 tcond
= TCG_COND_LT
;
1438 case 12: /* GE (!(N ^ V)) */
1439 case 13: /* LT (N ^ V) */
1440 c
->v1
= tmp
= tcg_temp_new();
1442 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1443 tcond
= TCG_COND_LT
;
1445 case 14: /* GT (!(Z || (N ^ V))) */
1446 case 15: /* LE (Z || (N ^ V)) */
1447 c
->v1
= tmp
= tcg_temp_new();
1449 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1450 tcg_gen_neg_i32(tmp
, tmp
);
1451 tmp2
= tcg_temp_new();
1452 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
1453 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1454 tcg_temp_free(tmp2
);
1455 tcond
= TCG_COND_LT
;
1460 if ((cond
& 1) == 0) {
1461 tcond
= tcg_invert_cond(tcond
);
1466 static void free_cond(DisasCompare
*c
)
1469 tcg_temp_free(c
->v1
);
1472 tcg_temp_free(c
->v2
);
1476 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
1480 gen_cc_cond(&c
, s
, cond
);
1482 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
1486 /* Force a TB lookup after an instruction that changes the CPU state. */
1487 static void gen_exit_tb(DisasContext
*s
)
1490 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
1491 s
->base
.is_jmp
= DISAS_EXIT
;
1494 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1495 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1496 op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \
1497 if (IS_NULL_QREG(result)) { \
1498 gen_addr_fault(s); \
1503 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1504 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, \
1505 EA_STORE, IS_USER(s)); \
1506 if (IS_NULL_QREG(ea_result)) { \
1507 gen_addr_fault(s); \
1512 /* Generate a jump to an immediate address. */
1513 static void gen_jmp_tb(DisasContext
*s
, int n
, target_ulong dest
,
1516 if (unlikely(s
->ss_active
)) {
1518 tcg_gen_movi_i32(QREG_PC
, dest
);
1519 gen_raise_exception_format2(s
, EXCP_TRACE
, src
);
1520 } else if (translator_use_goto_tb(&s
->base
, dest
)) {
1522 tcg_gen_movi_i32(QREG_PC
, dest
);
1523 tcg_gen_exit_tb(s
->base
.tb
, n
);
1525 gen_jmp_im(s
, dest
);
1526 tcg_gen_exit_tb(NULL
, 0);
1528 s
->base
.is_jmp
= DISAS_NORETURN
;
1537 cond
= (insn
>> 8) & 0xf;
1538 gen_cc_cond(&c
, s
, cond
);
1540 tmp
= tcg_temp_new();
1541 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
1544 tcg_gen_neg_i32(tmp
, tmp
);
1545 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
1557 reg
= DREG(insn
, 0);
1559 offset
= (int16_t)read_im16(env
, s
);
1560 l1
= gen_new_label();
1561 gen_jmpcc(s
, (insn
>> 8) & 0xf, l1
);
1563 tmp
= tcg_temp_new();
1564 tcg_gen_ext16s_i32(tmp
, reg
);
1565 tcg_gen_addi_i32(tmp
, tmp
, -1);
1566 gen_partset_reg(OS_WORD
, reg
, tmp
);
1567 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, -1, l1
);
1568 gen_jmp_tb(s
, 1, base
+ offset
, s
->base
.pc_next
);
1570 gen_jmp_tb(s
, 0, s
->pc
, s
->base
.pc_next
);
1573 DISAS_INSN(undef_mac
)
1575 gen_exception(s
, s
->base
.pc_next
, EXCP_LINEA
);
1578 DISAS_INSN(undef_fpu
)
1580 gen_exception(s
, s
->base
.pc_next
, EXCP_LINEF
);
1586 * ??? This is both instructions that are as yet unimplemented
1587 * for the 680x0 series, as well as those that are implemented
1588 * but actually illegal for CPU32 or pre-68020.
1590 qemu_log_mask(LOG_UNIMP
, "Illegal instruction: %04x @ %08x\n",
1591 insn
, s
->base
.pc_next
);
1592 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
1602 sign
= (insn
& 0x100) != 0;
1603 reg
= DREG(insn
, 9);
1604 tmp
= tcg_temp_new();
1606 tcg_gen_ext16s_i32(tmp
, reg
);
1608 tcg_gen_ext16u_i32(tmp
, reg
);
1609 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1610 tcg_gen_mul_i32(tmp
, tmp
, src
);
1611 tcg_gen_mov_i32(reg
, tmp
);
1612 gen_logic_cc(s
, tmp
, OS_LONG
);
1623 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1625 sign
= (insn
& 0x100) != 0;
1627 /* dest.l / src.w */
1629 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1630 destr
= tcg_constant_i32(REG(insn
, 9));
1631 ilen
= tcg_constant_i32(s
->pc
- s
->base
.pc_next
);
1633 gen_helper_divsw(cpu_env
, destr
, src
, ilen
);
1635 gen_helper_divuw(cpu_env
, destr
, src
, ilen
);
1638 set_cc_op(s
, CC_OP_FLAGS
);
1643 TCGv num
, reg
, den
, ilen
;
1647 ext
= read_im16(env
, s
);
1649 sign
= (ext
& 0x0800) != 0;
1652 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
1653 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
1657 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1659 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1660 num
= tcg_constant_i32(REG(ext
, 12));
1661 reg
= tcg_constant_i32(REG(ext
, 0));
1662 ilen
= tcg_constant_i32(s
->pc
- s
->base
.pc_next
);
1664 gen_helper_divsll(cpu_env
, num
, reg
, den
, ilen
);
1666 gen_helper_divull(cpu_env
, num
, reg
, den
, ilen
);
1668 set_cc_op(s
, CC_OP_FLAGS
);
1672 /* divX.l <EA>, Dq 32/32 -> 32q */
1673 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1675 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1676 num
= tcg_constant_i32(REG(ext
, 12));
1677 reg
= tcg_constant_i32(REG(ext
, 0));
1678 ilen
= tcg_constant_i32(s
->pc
- s
->base
.pc_next
);
1680 gen_helper_divsl(cpu_env
, num
, reg
, den
, ilen
);
1682 gen_helper_divul(cpu_env
, num
, reg
, den
, ilen
);
1685 set_cc_op(s
, CC_OP_FLAGS
);
1688 static void bcd_add(TCGv dest
, TCGv src
)
1693 * dest10 = dest10 + src10 + X
1697 * t3 = t2 + dest + X
1701 * t7 = (t6 >> 2) | (t6 >> 3)
1706 * t1 = (src + 0x066) + dest + X
1707 * = result with some possible exceeding 0x6
1710 t0
= tcg_const_i32(0x066);
1711 tcg_gen_add_i32(t0
, t0
, src
);
1713 t1
= tcg_temp_new();
1714 tcg_gen_add_i32(t1
, t0
, dest
);
1715 tcg_gen_add_i32(t1
, t1
, QREG_CC_X
);
1717 /* we will remove exceeding 0x6 where there is no carry */
1720 * t0 = (src + 0x0066) ^ dest
1721 * = t1 without carries
1724 tcg_gen_xor_i32(t0
, t0
, dest
);
1727 * extract the carries
1729 * = only the carries
1732 tcg_gen_xor_i32(t0
, t0
, t1
);
1735 * generate 0x1 where there is no carry
1736 * and for each 0x10, generate a 0x6
1739 tcg_gen_shri_i32(t0
, t0
, 3);
1740 tcg_gen_not_i32(t0
, t0
);
1741 tcg_gen_andi_i32(t0
, t0
, 0x22);
1742 tcg_gen_add_i32(dest
, t0
, t0
);
1743 tcg_gen_add_i32(dest
, dest
, t0
);
1747 * remove the exceeding 0x6
1748 * for digits that have not generated a carry
1751 tcg_gen_sub_i32(dest
, t1
, dest
);
1755 static void bcd_sub(TCGv dest
, TCGv src
)
1760 * dest10 = dest10 - src10 - X
1761 * = bcd_add(dest + 1 - X, 0x199 - src)
1764 /* t0 = 0x066 + (0x199 - src) */
1766 t0
= tcg_temp_new();
1767 tcg_gen_subfi_i32(t0
, 0x1ff, src
);
1769 /* t1 = t0 + dest + 1 - X*/
1771 t1
= tcg_temp_new();
1772 tcg_gen_add_i32(t1
, t0
, dest
);
1773 tcg_gen_addi_i32(t1
, t1
, 1);
1774 tcg_gen_sub_i32(t1
, t1
, QREG_CC_X
);
1776 /* t2 = t0 ^ dest */
1778 t2
= tcg_temp_new();
1779 tcg_gen_xor_i32(t2
, t0
, dest
);
1783 tcg_gen_xor_i32(t0
, t1
, t2
);
1787 * t0 = (t2 >> 2) | (t2 >> 3)
1789 * to fit on 8bit operands, changed in:
1791 * t2 = ~(t0 >> 3) & 0x22
1796 tcg_gen_shri_i32(t2
, t0
, 3);
1797 tcg_gen_not_i32(t2
, t2
);
1798 tcg_gen_andi_i32(t2
, t2
, 0x22);
1799 tcg_gen_add_i32(t0
, t2
, t2
);
1800 tcg_gen_add_i32(t0
, t0
, t2
);
1803 /* return t1 - t0 */
1805 tcg_gen_sub_i32(dest
, t1
, t0
);
1810 static void bcd_flags(TCGv val
)
1812 tcg_gen_andi_i32(QREG_CC_C
, val
, 0x0ff);
1813 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_C
);
1815 tcg_gen_extract_i32(QREG_CC_C
, val
, 8, 1);
1817 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
1820 DISAS_INSN(abcd_reg
)
1825 gen_flush_flags(s
); /* !Z is sticky */
1827 src
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
1828 dest
= gen_extend(s
, DREG(insn
, 9), OS_BYTE
, 0);
1830 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1835 DISAS_INSN(abcd_mem
)
1837 TCGv src
, dest
, addr
;
1839 gen_flush_flags(s
); /* !Z is sticky */
1841 /* Indirect pre-decrement load (mode 4) */
1843 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1844 NULL_QREG
, NULL
, EA_LOADU
, IS_USER(s
));
1845 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1846 NULL_QREG
, &addr
, EA_LOADU
, IS_USER(s
));
1850 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
,
1851 EA_STORE
, IS_USER(s
));
1856 DISAS_INSN(sbcd_reg
)
1860 gen_flush_flags(s
); /* !Z is sticky */
1862 src
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
1863 dest
= gen_extend(s
, DREG(insn
, 9), OS_BYTE
, 0);
1867 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1872 DISAS_INSN(sbcd_mem
)
1874 TCGv src
, dest
, addr
;
1876 gen_flush_flags(s
); /* !Z is sticky */
1878 /* Indirect pre-decrement load (mode 4) */
1880 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1881 NULL_QREG
, NULL
, EA_LOADU
, IS_USER(s
));
1882 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1883 NULL_QREG
, &addr
, EA_LOADU
, IS_USER(s
));
1887 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
,
1888 EA_STORE
, IS_USER(s
));
1898 gen_flush_flags(s
); /* !Z is sticky */
1900 SRC_EA(env
, src
, OS_BYTE
, 0, &addr
);
1902 dest
= tcg_const_i32(0);
1905 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1909 tcg_temp_free(dest
);
1922 add
= (insn
& 0x4000) != 0;
1923 opsize
= insn_opsize(insn
);
1924 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
1925 dest
= tcg_temp_new();
1927 SRC_EA(env
, tmp
, opsize
, 1, &addr
);
1931 SRC_EA(env
, src
, opsize
, 1, NULL
);
1934 tcg_gen_add_i32(dest
, tmp
, src
);
1935 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1936 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
1938 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1939 tcg_gen_sub_i32(dest
, tmp
, src
);
1940 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
1942 gen_update_cc_add(dest
, src
, opsize
);
1944 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1946 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
1948 tcg_temp_free(dest
);
1951 /* Reverse the order of the bits in REG. */
1955 reg
= DREG(insn
, 0);
1956 gen_helper_bitrev(reg
, reg
);
1959 DISAS_INSN(bitop_reg
)
1969 if ((insn
& 0x38) != 0)
1973 op
= (insn
>> 6) & 3;
1974 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1977 src2
= tcg_temp_new();
1978 if (opsize
== OS_BYTE
)
1979 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 7);
1981 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 31);
1983 tmp
= tcg_const_i32(1);
1984 tcg_gen_shl_i32(tmp
, tmp
, src2
);
1985 tcg_temp_free(src2
);
1987 tcg_gen_and_i32(QREG_CC_Z
, src1
, tmp
);
1989 dest
= tcg_temp_new();
1992 tcg_gen_xor_i32(dest
, src1
, tmp
);
1995 tcg_gen_andc_i32(dest
, src1
, tmp
);
1998 tcg_gen_or_i32(dest
, src1
, tmp
);
2005 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2007 tcg_temp_free(dest
);
2013 reg
= DREG(insn
, 0);
2015 gen_helper_sats(reg
, reg
, QREG_CC_V
);
2016 gen_logic_cc(s
, reg
, OS_LONG
);
2019 static void gen_push(DisasContext
*s
, TCGv val
)
2023 tmp
= tcg_temp_new();
2024 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2025 gen_store(s
, OS_LONG
, tmp
, val
, IS_USER(s
));
2026 tcg_gen_mov_i32(QREG_SP
, tmp
);
2030 static TCGv
mreg(int reg
)
2034 return cpu_dregs
[reg
];
2037 return cpu_aregs
[reg
& 7];
2042 TCGv addr
, incr
, tmp
, r
[16];
2043 int is_load
= (insn
& 0x0400) != 0;
2044 int opsize
= (insn
& 0x40) != 0 ? OS_LONG
: OS_WORD
;
2045 uint16_t mask
= read_im16(env
, s
);
2046 int mode
= extract32(insn
, 3, 3);
2047 int reg0
= REG(insn
, 0);
2050 tmp
= cpu_aregs
[reg0
];
2053 case 0: /* data register direct */
2054 case 1: /* addr register direct */
2059 case 2: /* indirect */
2062 case 3: /* indirect post-increment */
2064 /* post-increment is not allowed */
2069 case 4: /* indirect pre-decrement */
2071 /* pre-decrement is not allowed */
2075 * We want a bare copy of the address reg, without any pre-decrement
2076 * adjustment, as gen_lea would provide.
2081 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
2082 if (IS_NULL_QREG(tmp
)) {
2088 addr
= tcg_temp_new();
2089 tcg_gen_mov_i32(addr
, tmp
);
2090 incr
= tcg_const_i32(opsize_bytes(opsize
));
2093 /* memory to register */
2094 for (i
= 0; i
< 16; i
++) {
2095 if (mask
& (1 << i
)) {
2096 r
[i
] = gen_load(s
, opsize
, addr
, 1, IS_USER(s
));
2097 tcg_gen_add_i32(addr
, addr
, incr
);
2100 for (i
= 0; i
< 16; i
++) {
2101 if (mask
& (1 << i
)) {
2102 tcg_gen_mov_i32(mreg(i
), r
[i
]);
2103 tcg_temp_free(r
[i
]);
2107 /* post-increment: movem (An)+,X */
2108 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2111 /* register to memory */
2113 /* pre-decrement: movem X,-(An) */
2114 for (i
= 15; i
>= 0; i
--) {
2115 if ((mask
<< i
) & 0x8000) {
2116 tcg_gen_sub_i32(addr
, addr
, incr
);
2117 if (reg0
+ 8 == i
&&
2118 m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
)) {
2120 * M68020+: if the addressing register is the
2121 * register moved to memory, the value written
2122 * is the initial value decremented by the size of
2123 * the operation, regardless of how many actual
2124 * stores have been performed until this point.
2125 * M68000/M68010: the value is the initial value.
2127 tmp
= tcg_temp_new();
2128 tcg_gen_sub_i32(tmp
, cpu_aregs
[reg0
], incr
);
2129 gen_store(s
, opsize
, addr
, tmp
, IS_USER(s
));
2132 gen_store(s
, opsize
, addr
, mreg(i
), IS_USER(s
));
2136 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2138 for (i
= 0; i
< 16; i
++) {
2139 if (mask
& (1 << i
)) {
2140 gen_store(s
, opsize
, addr
, mreg(i
), IS_USER(s
));
2141 tcg_gen_add_i32(addr
, addr
, incr
);
2147 tcg_temp_free(incr
);
2148 tcg_temp_free(addr
);
2160 displ
= read_im16(env
, s
);
2162 addr
= AREG(insn
, 0);
2163 reg
= DREG(insn
, 9);
2165 abuf
= tcg_temp_new();
2166 tcg_gen_addi_i32(abuf
, addr
, displ
);
2167 dbuf
= tcg_temp_new();
2176 for ( ; i
> 0 ; i
--) {
2177 tcg_gen_shri_i32(dbuf
, reg
, (i
- 1) * 8);
2178 tcg_gen_qemu_st8(dbuf
, abuf
, IS_USER(s
));
2180 tcg_gen_addi_i32(abuf
, abuf
, 2);
2184 for ( ; i
> 0 ; i
--) {
2185 tcg_gen_qemu_ld8u(dbuf
, abuf
, IS_USER(s
));
2186 tcg_gen_deposit_i32(reg
, reg
, dbuf
, (i
- 1) * 8, 8);
2188 tcg_gen_addi_i32(abuf
, abuf
, 2);
2192 tcg_temp_free(abuf
);
2193 tcg_temp_free(dbuf
);
2196 DISAS_INSN(bitop_im
)
2206 if ((insn
& 0x38) != 0)
2210 op
= (insn
>> 6) & 3;
2212 bitnum
= read_im16(env
, s
);
2213 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2214 if (bitnum
& 0xfe00) {
2215 disas_undef(env
, s
, insn
);
2219 if (bitnum
& 0xff00) {
2220 disas_undef(env
, s
, insn
);
2225 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
2228 if (opsize
== OS_BYTE
)
2234 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
2237 tmp
= tcg_temp_new();
2240 tcg_gen_xori_i32(tmp
, src1
, mask
);
2243 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
2246 tcg_gen_ori_i32(tmp
, src1
, mask
);
2251 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
2256 static TCGv
gen_get_ccr(DisasContext
*s
)
2261 dest
= tcg_temp_new();
2262 gen_helper_get_ccr(dest
, cpu_env
);
2266 static TCGv
gen_get_sr(DisasContext
*s
)
2271 ccr
= gen_get_ccr(s
);
2272 sr
= tcg_temp_new();
2273 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
2274 tcg_gen_or_i32(sr
, sr
, ccr
);
2279 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
2282 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
2283 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
2284 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
2285 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
2286 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
2288 TCGv sr
= tcg_const_i32(val
);
2289 gen_helper_set_sr(cpu_env
, sr
);
2292 set_cc_op(s
, CC_OP_FLAGS
);
2295 static void gen_set_sr(DisasContext
*s
, TCGv val
, int ccr_only
)
2298 gen_helper_set_ccr(cpu_env
, val
);
2300 gen_helper_set_sr(cpu_env
, val
);
2302 set_cc_op(s
, CC_OP_FLAGS
);
2305 static void gen_move_to_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
2308 if ((insn
& 0x3f) == 0x3c) {
2310 val
= read_im16(env
, s
);
2311 gen_set_sr_im(s
, val
, ccr_only
);
2314 SRC_EA(env
, src
, OS_WORD
, 0, NULL
);
2315 gen_set_sr(s
, src
, ccr_only
);
2319 DISAS_INSN(arith_im
)
2327 bool with_SR
= ((insn
& 0x3f) == 0x3c);
2329 op
= (insn
>> 9) & 7;
2330 opsize
= insn_opsize(insn
);
2333 im
= tcg_const_i32((int8_t)read_im8(env
, s
));
2336 im
= tcg_const_i32((int16_t)read_im16(env
, s
));
2339 im
= tcg_const_i32(read_im32(env
, s
));
2342 g_assert_not_reached();
2346 /* SR/CCR can only be used with andi/eori/ori */
2347 if (op
== 2 || op
== 3 || op
== 6) {
2348 disas_undef(env
, s
, insn
);
2353 src1
= gen_get_ccr(s
);
2357 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
2360 src1
= gen_get_sr(s
);
2363 /* OS_LONG; others already g_assert_not_reached. */
2364 disas_undef(env
, s
, insn
);
2368 SRC_EA(env
, src1
, opsize
, 1, (op
== 6) ? NULL
: &addr
);
2370 dest
= tcg_temp_new();
2373 tcg_gen_or_i32(dest
, src1
, im
);
2375 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2377 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2378 gen_logic_cc(s
, dest
, opsize
);
2382 tcg_gen_and_i32(dest
, src1
, im
);
2384 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2386 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2387 gen_logic_cc(s
, dest
, opsize
);
2391 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, src1
, im
);
2392 tcg_gen_sub_i32(dest
, src1
, im
);
2393 gen_update_cc_add(dest
, im
, opsize
);
2394 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2395 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2398 tcg_gen_add_i32(dest
, src1
, im
);
2399 gen_update_cc_add(dest
, im
, opsize
);
2400 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
2401 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2402 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2405 tcg_gen_xor_i32(dest
, src1
, im
);
2407 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2409 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2410 gen_logic_cc(s
, dest
, opsize
);
2414 gen_update_cc_cmp(s
, src1
, im
, opsize
);
2420 tcg_temp_free(dest
);
2432 switch ((insn
>> 9) & 3) {
2446 g_assert_not_reached();
2449 ext
= read_im16(env
, s
);
2451 /* cas Dc,Du,<EA> */
2453 addr
= gen_lea(env
, s
, insn
, opsize
);
2454 if (IS_NULL_QREG(addr
)) {
2459 cmp
= gen_extend(s
, DREG(ext
, 0), opsize
, 1);
2462 * if <EA> == Dc then
2464 * Dc = <EA> (because <EA> == Dc)
2469 load
= tcg_temp_new();
2470 tcg_gen_atomic_cmpxchg_i32(load
, addr
, cmp
, DREG(ext
, 6),
2472 /* update flags before setting cmp to load */
2473 gen_update_cc_cmp(s
, load
, cmp
, opsize
);
2474 gen_partset_reg(opsize
, DREG(ext
, 0), load
);
2476 tcg_temp_free(load
);
2478 switch (extract32(insn
, 3, 3)) {
2479 case 3: /* Indirect postincrement. */
2480 tcg_gen_addi_i32(AREG(insn
, 0), addr
, opsize_bytes(opsize
));
2482 case 4: /* Indirect predecrememnt. */
2483 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2490 uint16_t ext1
, ext2
;
2494 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2496 ext1
= read_im16(env
, s
);
2498 if (ext1
& 0x8000) {
2499 /* Address Register */
2500 addr1
= AREG(ext1
, 12);
2503 addr1
= DREG(ext1
, 12);
2506 ext2
= read_im16(env
, s
);
2507 if (ext2
& 0x8000) {
2508 /* Address Register */
2509 addr2
= AREG(ext2
, 12);
2512 addr2
= DREG(ext2
, 12);
2516 * if (R1) == Dc1 && (R2) == Dc2 then
2524 regs
= tcg_const_i32(REG(ext2
, 6) |
2525 (REG(ext1
, 6) << 3) |
2526 (REG(ext2
, 0) << 6) |
2527 (REG(ext1
, 0) << 9));
2528 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2529 gen_helper_exit_atomic(cpu_env
);
2531 gen_helper_cas2w(cpu_env
, regs
, addr1
, addr2
);
2533 tcg_temp_free(regs
);
2535 /* Note that cas2w also assigned to env->cc_op. */
2536 s
->cc_op
= CC_OP_CMPW
;
2537 s
->cc_op_synced
= 1;
2542 uint16_t ext1
, ext2
;
2543 TCGv addr1
, addr2
, regs
;
2545 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2547 ext1
= read_im16(env
, s
);
2549 if (ext1
& 0x8000) {
2550 /* Address Register */
2551 addr1
= AREG(ext1
, 12);
2554 addr1
= DREG(ext1
, 12);
2557 ext2
= read_im16(env
, s
);
2558 if (ext2
& 0x8000) {
2559 /* Address Register */
2560 addr2
= AREG(ext2
, 12);
2563 addr2
= DREG(ext2
, 12);
2567 * if (R1) == Dc1 && (R2) == Dc2 then
2575 regs
= tcg_const_i32(REG(ext2
, 6) |
2576 (REG(ext1
, 6) << 3) |
2577 (REG(ext2
, 0) << 6) |
2578 (REG(ext1
, 0) << 9));
2579 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2580 gen_helper_cas2l_parallel(cpu_env
, regs
, addr1
, addr2
);
2582 gen_helper_cas2l(cpu_env
, regs
, addr1
, addr2
);
2584 tcg_temp_free(regs
);
2586 /* Note that cas2l also assigned to env->cc_op. */
2587 s
->cc_op
= CC_OP_CMPL
;
2588 s
->cc_op_synced
= 1;
2595 reg
= DREG(insn
, 0);
2596 tcg_gen_bswap32_i32(reg
, reg
);
2606 switch (insn
>> 12) {
2607 case 1: /* move.b */
2610 case 2: /* move.l */
2613 case 3: /* move.w */
2619 SRC_EA(env
, src
, opsize
, 1, NULL
);
2620 op
= (insn
>> 6) & 7;
2623 /* The value will already have been sign extended. */
2624 dest
= AREG(insn
, 9);
2625 tcg_gen_mov_i32(dest
, src
);
2629 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
2630 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
2631 /* This will be correct because loads sign extend. */
2632 gen_logic_cc(s
, src
, opsize
);
2643 opsize
= insn_opsize(insn
);
2644 SRC_EA(env
, src
, opsize
, 1, &addr
);
2646 gen_flush_flags(s
); /* compute old Z */
2649 * Perform subtract with borrow.
2650 * (X, N) = -(src + X);
2653 z
= tcg_const_i32(0);
2654 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, z
, QREG_CC_X
, z
);
2655 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, z
, z
, QREG_CC_N
, QREG_CC_X
);
2657 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2659 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2662 * Compute signed-overflow for negation. The normal formula for
2663 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2664 * this simplifies to res & src.
2667 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_N
, src
);
2669 /* Copy the rest of the results into place. */
2670 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2671 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2673 set_cc_op(s
, CC_OP_FLAGS
);
2675 /* result is in QREG_CC_N */
2677 DEST_EA(env
, insn
, opsize
, QREG_CC_N
, &addr
);
2685 reg
= AREG(insn
, 9);
2686 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2687 if (IS_NULL_QREG(tmp
)) {
2691 tcg_gen_mov_i32(reg
, tmp
);
2699 zero
= tcg_const_i32(0);
2701 opsize
= insn_opsize(insn
);
2702 DEST_EA(env
, insn
, opsize
, zero
, NULL
);
2703 gen_logic_cc(s
, zero
, opsize
);
2704 tcg_temp_free(zero
);
2707 DISAS_INSN(move_from_ccr
)
2711 ccr
= gen_get_ccr(s
);
2712 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
2722 opsize
= insn_opsize(insn
);
2723 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2724 dest
= tcg_temp_new();
2725 tcg_gen_neg_i32(dest
, src1
);
2726 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2727 gen_update_cc_add(dest
, src1
, opsize
);
2728 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, dest
, 0);
2729 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2730 tcg_temp_free(dest
);
2733 DISAS_INSN(move_to_ccr
)
2735 gen_move_to_sr(env
, s
, insn
, true);
2745 opsize
= insn_opsize(insn
);
2746 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2747 dest
= tcg_temp_new();
2748 tcg_gen_not_i32(dest
, src1
);
2749 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2750 gen_logic_cc(s
, dest
, opsize
);
2759 src1
= tcg_temp_new();
2760 src2
= tcg_temp_new();
2761 reg
= DREG(insn
, 0);
2762 tcg_gen_shli_i32(src1
, reg
, 16);
2763 tcg_gen_shri_i32(src2
, reg
, 16);
2764 tcg_gen_or_i32(reg
, src1
, src2
);
2765 tcg_temp_free(src2
);
2766 tcg_temp_free(src1
);
2767 gen_logic_cc(s
, reg
, OS_LONG
);
2772 gen_exception(s
, s
->base
.pc_next
, EXCP_DEBUG
);
2779 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2780 if (IS_NULL_QREG(tmp
)) {
2793 reg
= DREG(insn
, 0);
2794 op
= (insn
>> 6) & 7;
2795 tmp
= tcg_temp_new();
2797 tcg_gen_ext16s_i32(tmp
, reg
);
2799 tcg_gen_ext8s_i32(tmp
, reg
);
2801 gen_partset_reg(OS_WORD
, reg
, tmp
);
2803 tcg_gen_mov_i32(reg
, tmp
);
2804 gen_logic_cc(s
, tmp
, OS_LONG
);
2813 opsize
= insn_opsize(insn
);
2814 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
2815 gen_logic_cc(s
, tmp
, opsize
);
2820 /* Implemented as a NOP. */
2825 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
2828 /* ??? This should be atomic. */
2835 dest
= tcg_temp_new();
2836 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
2837 gen_logic_cc(s
, src1
, OS_BYTE
);
2838 tcg_gen_ori_i32(dest
, src1
, 0x80);
2839 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
2840 tcg_temp_free(dest
);
2849 ext
= read_im16(env
, s
);
2854 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
2855 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
2859 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2862 tcg_gen_muls2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2864 tcg_gen_mulu2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2866 /* if Dl == Dh, 68040 returns low word */
2867 tcg_gen_mov_i32(DREG(ext
, 0), QREG_CC_N
);
2868 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_Z
);
2869 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
);
2871 tcg_gen_movi_i32(QREG_CC_V
, 0);
2872 tcg_gen_movi_i32(QREG_CC_C
, 0);
2874 set_cc_op(s
, CC_OP_FLAGS
);
2877 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2878 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2879 tcg_gen_movi_i32(QREG_CC_C
, 0);
2881 tcg_gen_muls2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2882 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2883 tcg_gen_sari_i32(QREG_CC_Z
, QREG_CC_N
, 31);
2884 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_Z
);
2886 tcg_gen_mulu2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2887 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2888 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_C
);
2890 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
2891 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_N
);
2893 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
2895 set_cc_op(s
, CC_OP_FLAGS
);
2898 * The upper 32 bits of the product are discarded, so
2899 * muls.l and mulu.l are functionally equivalent.
2901 tcg_gen_mul_i32(DREG(ext
, 12), src1
, DREG(ext
, 12));
2902 gen_logic_cc(s
, DREG(ext
, 12), OS_LONG
);
2906 static void gen_link(DisasContext
*s
, uint16_t insn
, int32_t offset
)
2911 reg
= AREG(insn
, 0);
2912 tmp
= tcg_temp_new();
2913 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2914 gen_store(s
, OS_LONG
, tmp
, reg
, IS_USER(s
));
2915 if ((insn
& 7) != 7) {
2916 tcg_gen_mov_i32(reg
, tmp
);
2918 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
2926 offset
= read_im16(env
, s
);
2927 gen_link(s
, insn
, offset
);
2934 offset
= read_im32(env
, s
);
2935 gen_link(s
, insn
, offset
);
2944 src
= tcg_temp_new();
2945 reg
= AREG(insn
, 0);
2946 tcg_gen_mov_i32(src
, reg
);
2947 tmp
= gen_load(s
, OS_LONG
, src
, 0, IS_USER(s
));
2948 tcg_gen_mov_i32(reg
, tmp
);
2949 tcg_gen_addi_i32(QREG_SP
, src
, 4);
2954 #if defined(CONFIG_SOFTMMU)
2958 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
2962 gen_helper_reset(cpu_env
);
2973 int16_t offset
= read_im16(env
, s
);
2975 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0, IS_USER(s
));
2976 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, offset
+ 4);
2986 sp
= tcg_temp_new();
2987 ccr
= gen_load(s
, OS_WORD
, QREG_SP
, 0, IS_USER(s
));
2988 tcg_gen_addi_i32(sp
, QREG_SP
, 2);
2989 tmp
= gen_load(s
, OS_LONG
, sp
, 0, IS_USER(s
));
2990 tcg_gen_addi_i32(QREG_SP
, sp
, 4);
2993 gen_set_sr(s
, ccr
, true);
3003 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0, IS_USER(s
));
3004 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
3013 * Load the target address first to ensure correct exception
3016 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
3017 if (IS_NULL_QREG(tmp
)) {
3021 if ((insn
& 0x40) == 0) {
3023 gen_push(s
, tcg_const_i32(s
->pc
));
3037 if ((insn
& 070) == 010) {
3038 /* Operation on address register is always long. */
3041 opsize
= insn_opsize(insn
);
3043 SRC_EA(env
, src
, opsize
, 1, &addr
);
3044 imm
= (insn
>> 9) & 7;
3048 val
= tcg_const_i32(imm
);
3049 dest
= tcg_temp_new();
3050 tcg_gen_mov_i32(dest
, src
);
3051 if ((insn
& 0x38) == 0x08) {
3053 * Don't update condition codes if the destination is an
3056 if (insn
& 0x0100) {
3057 tcg_gen_sub_i32(dest
, dest
, val
);
3059 tcg_gen_add_i32(dest
, dest
, val
);
3062 if (insn
& 0x0100) {
3063 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
3064 tcg_gen_sub_i32(dest
, dest
, val
);
3065 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
3067 tcg_gen_add_i32(dest
, dest
, val
);
3068 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
3069 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
3071 gen_update_cc_add(dest
, val
, opsize
);
3074 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3075 tcg_temp_free(dest
);
3081 case 2: /* One extension word. */
3084 case 3: /* Two extension words. */
3087 case 4: /* No extension words. */
3090 disas_undef(env
, s
, insn
);
3101 op
= (insn
>> 8) & 0xf;
3102 offset
= (int8_t)insn
;
3104 offset
= (int16_t)read_im16(env
, s
);
3105 } else if (offset
== -1) {
3106 offset
= read_im32(env
, s
);
3110 gen_push(s
, tcg_const_i32(s
->pc
));
3114 TCGLabel
*l1
= gen_new_label();
3115 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
3116 gen_jmp_tb(s
, 1, base
+ offset
, s
->base
.pc_next
);
3118 gen_jmp_tb(s
, 0, s
->pc
, s
->base
.pc_next
);
3120 /* Unconditional branch. */
3122 gen_jmp_tb(s
, 0, base
+ offset
, s
->base
.pc_next
);
3128 tcg_gen_movi_i32(DREG(insn
, 9), (int8_t)insn
);
3129 gen_logic_cc(s
, DREG(insn
, 9), OS_LONG
);
3142 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
3143 reg
= DREG(insn
, 9);
3144 tcg_gen_mov_i32(reg
, src
);
3145 gen_logic_cc(s
, src
, opsize
);
3156 opsize
= insn_opsize(insn
);
3157 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 0);
3158 dest
= tcg_temp_new();
3160 SRC_EA(env
, src
, opsize
, 0, &addr
);
3161 tcg_gen_or_i32(dest
, src
, reg
);
3162 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3164 SRC_EA(env
, src
, opsize
, 0, NULL
);
3165 tcg_gen_or_i32(dest
, src
, reg
);
3166 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
3168 gen_logic_cc(s
, dest
, opsize
);
3169 tcg_temp_free(dest
);
3177 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3178 reg
= AREG(insn
, 9);
3179 tcg_gen_sub_i32(reg
, reg
, src
);
3182 static inline void gen_subx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3186 gen_flush_flags(s
); /* compute old Z */
3189 * Perform subtract with borrow.
3190 * (X, N) = dest - (src + X);
3193 tmp
= tcg_const_i32(0);
3194 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, tmp
, QREG_CC_X
, tmp
);
3195 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, dest
, tmp
, QREG_CC_N
, QREG_CC_X
);
3196 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3197 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
3199 /* Compute signed-overflow for subtract. */
3201 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, dest
);
3202 tcg_gen_xor_i32(tmp
, dest
, src
);
3203 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3206 /* Copy the rest of the results into place. */
3207 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3208 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3210 set_cc_op(s
, CC_OP_FLAGS
);
3212 /* result is in QREG_CC_N */
3215 DISAS_INSN(subx_reg
)
3221 opsize
= insn_opsize(insn
);
3223 src
= gen_extend(s
, DREG(insn
, 0), opsize
, 1);
3224 dest
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3226 gen_subx(s
, src
, dest
, opsize
);
3228 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3231 DISAS_INSN(subx_mem
)
3239 opsize
= insn_opsize(insn
);
3241 addr_src
= AREG(insn
, 0);
3242 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3243 src
= gen_load(s
, opsize
, addr_src
, 1, IS_USER(s
));
3245 addr_dest
= AREG(insn
, 9);
3246 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3247 dest
= gen_load(s
, opsize
, addr_dest
, 1, IS_USER(s
));
3249 gen_subx(s
, src
, dest
, opsize
);
3251 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
, IS_USER(s
));
3253 tcg_temp_free(dest
);
3262 val
= (insn
>> 9) & 7;
3265 src
= tcg_const_i32(val
);
3266 gen_logic_cc(s
, src
, OS_LONG
);
3267 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
3277 opsize
= insn_opsize(insn
);
3278 SRC_EA(env
, src
, opsize
, 1, NULL
);
3279 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3280 gen_update_cc_cmp(s
, reg
, src
, opsize
);
3294 SRC_EA(env
, src
, opsize
, 1, NULL
);
3295 reg
= AREG(insn
, 9);
3296 gen_update_cc_cmp(s
, reg
, src
, OS_LONG
);
3301 int opsize
= insn_opsize(insn
);
3304 /* Post-increment load (mode 3) from Ay. */
3305 src
= gen_ea_mode(env
, s
, 3, REG(insn
, 0), opsize
,
3306 NULL_QREG
, NULL
, EA_LOADS
, IS_USER(s
));
3307 /* Post-increment load (mode 3) from Ax. */
3308 dst
= gen_ea_mode(env
, s
, 3, REG(insn
, 9), opsize
,
3309 NULL_QREG
, NULL
, EA_LOADS
, IS_USER(s
));
3311 gen_update_cc_cmp(s
, dst
, src
, opsize
);
3321 opsize
= insn_opsize(insn
);
3323 SRC_EA(env
, src
, opsize
, 0, &addr
);
3324 dest
= tcg_temp_new();
3325 tcg_gen_xor_i32(dest
, src
, DREG(insn
, 9));
3326 gen_logic_cc(s
, dest
, opsize
);
3327 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3328 tcg_temp_free(dest
);
3331 static void do_exg(TCGv reg1
, TCGv reg2
)
3333 TCGv temp
= tcg_temp_new();
3334 tcg_gen_mov_i32(temp
, reg1
);
3335 tcg_gen_mov_i32(reg1
, reg2
);
3336 tcg_gen_mov_i32(reg2
, temp
);
3337 tcg_temp_free(temp
);
3342 /* exchange Dx and Dy */
3343 do_exg(DREG(insn
, 9), DREG(insn
, 0));
3348 /* exchange Ax and Ay */
3349 do_exg(AREG(insn
, 9), AREG(insn
, 0));
3354 /* exchange Dx and Ay */
3355 do_exg(DREG(insn
, 9), AREG(insn
, 0));
3366 dest
= tcg_temp_new();
3368 opsize
= insn_opsize(insn
);
3369 reg
= DREG(insn
, 9);
3371 SRC_EA(env
, src
, opsize
, 0, &addr
);
3372 tcg_gen_and_i32(dest
, src
, reg
);
3373 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3375 SRC_EA(env
, src
, opsize
, 0, NULL
);
3376 tcg_gen_and_i32(dest
, src
, reg
);
3377 gen_partset_reg(opsize
, reg
, dest
);
3379 gen_logic_cc(s
, dest
, opsize
);
3380 tcg_temp_free(dest
);
3388 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3389 reg
= AREG(insn
, 9);
3390 tcg_gen_add_i32(reg
, reg
, src
);
3393 static inline void gen_addx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3397 gen_flush_flags(s
); /* compute old Z */
3400 * Perform addition with carry.
3401 * (X, N) = src + dest + X;
3404 tmp
= tcg_const_i32(0);
3405 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_X
, tmp
, dest
, tmp
);
3406 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_N
, QREG_CC_X
, src
, tmp
);
3407 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3409 /* Compute signed-overflow for addition. */
3411 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3412 tcg_gen_xor_i32(tmp
, dest
, src
);
3413 tcg_gen_andc_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3416 /* Copy the rest of the results into place. */
3417 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3418 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3420 set_cc_op(s
, CC_OP_FLAGS
);
3422 /* result is in QREG_CC_N */
3425 DISAS_INSN(addx_reg
)
3431 opsize
= insn_opsize(insn
);
3433 dest
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3434 src
= gen_extend(s
, DREG(insn
, 0), opsize
, 1);
3436 gen_addx(s
, src
, dest
, opsize
);
3438 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3441 DISAS_INSN(addx_mem
)
3449 opsize
= insn_opsize(insn
);
3451 addr_src
= AREG(insn
, 0);
3452 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3453 src
= gen_load(s
, opsize
, addr_src
, 1, IS_USER(s
));
3455 addr_dest
= AREG(insn
, 9);
3456 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3457 dest
= gen_load(s
, opsize
, addr_dest
, 1, IS_USER(s
));
3459 gen_addx(s
, src
, dest
, opsize
);
3461 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
, IS_USER(s
));
3463 tcg_temp_free(dest
);
3467 static inline void shift_im(DisasContext
*s
, uint16_t insn
, int opsize
)
3469 int count
= (insn
>> 9) & 7;
3470 int logical
= insn
& 8;
3471 int left
= insn
& 0x100;
3472 int bits
= opsize_bytes(opsize
) * 8;
3473 TCGv reg
= gen_extend(s
, DREG(insn
, 0), opsize
, !logical
);
3479 tcg_gen_movi_i32(QREG_CC_V
, 0);
3481 tcg_gen_shri_i32(QREG_CC_C
, reg
, bits
- count
);
3482 tcg_gen_shli_i32(QREG_CC_N
, reg
, count
);
3485 * Note that ColdFire always clears V (done above),
3486 * while M68000 sets if the most significant bit is changed at
3487 * any time during the shift operation.
3489 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3490 /* if shift count >= bits, V is (reg != 0) */
3491 if (count
>= bits
) {
3492 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, reg
, QREG_CC_V
);
3494 TCGv t0
= tcg_temp_new();
3495 tcg_gen_sari_i32(QREG_CC_V
, reg
, bits
- 1);
3496 tcg_gen_sari_i32(t0
, reg
, bits
- count
- 1);
3497 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, t0
);
3500 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3503 tcg_gen_shri_i32(QREG_CC_C
, reg
, count
- 1);
3505 tcg_gen_shri_i32(QREG_CC_N
, reg
, count
);
3507 tcg_gen_sari_i32(QREG_CC_N
, reg
, count
);
3511 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3512 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3513 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3514 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3516 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3517 set_cc_op(s
, CC_OP_FLAGS
);
3520 static inline void shift_reg(DisasContext
*s
, uint16_t insn
, int opsize
)
3522 int logical
= insn
& 8;
3523 int left
= insn
& 0x100;
3524 int bits
= opsize_bytes(opsize
) * 8;
3525 TCGv reg
= gen_extend(s
, DREG(insn
, 0), opsize
, !logical
);
3529 t64
= tcg_temp_new_i64();
3530 s64
= tcg_temp_new_i64();
3531 s32
= tcg_temp_new();
3534 * Note that m68k truncates the shift count modulo 64, not 32.
3535 * In addition, a 64-bit shift makes it easy to find "the last
3536 * bit shifted out", for the carry flag.
3538 tcg_gen_andi_i32(s32
, DREG(insn
, 9), 63);
3539 tcg_gen_extu_i32_i64(s64
, s32
);
3540 tcg_gen_extu_i32_i64(t64
, reg
);
3542 /* Optimistically set V=0. Also used as a zero source below. */
3543 tcg_gen_movi_i32(QREG_CC_V
, 0);
3545 tcg_gen_shl_i64(t64
, t64
, s64
);
3547 if (opsize
== OS_LONG
) {
3548 tcg_gen_extr_i64_i32(QREG_CC_N
, QREG_CC_C
, t64
);
3549 /* Note that C=0 if shift count is 0, and we get that for free. */
3551 TCGv zero
= tcg_const_i32(0);
3552 tcg_gen_extrl_i64_i32(QREG_CC_N
, t64
);
3553 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_N
, bits
);
3554 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3555 s32
, zero
, zero
, QREG_CC_C
);
3556 tcg_temp_free(zero
);
3558 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3560 /* X = C, but only if the shift count was non-zero. */
3561 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3562 QREG_CC_C
, QREG_CC_X
);
3565 * M68000 sets V if the most significant bit is changed at
3566 * any time during the shift operation. Do this via creating
3567 * an extension of the sign bit, comparing, and discarding
3568 * the bits below the sign bit. I.e.
3569 * int64_t s = (intN_t)reg;
3570 * int64_t t = (int64_t)(intN_t)reg << count;
3571 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3573 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3574 TCGv_i64 tt
= tcg_const_i64(32);
3575 /* if shift is greater than 32, use 32 */
3576 tcg_gen_movcond_i64(TCG_COND_GT
, s64
, s64
, tt
, tt
, s64
);
3577 tcg_temp_free_i64(tt
);
3578 /* Sign extend the input to 64 bits; re-do the shift. */
3579 tcg_gen_ext_i32_i64(t64
, reg
);
3580 tcg_gen_shl_i64(s64
, t64
, s64
);
3581 /* Clear all bits that are unchanged. */
3582 tcg_gen_xor_i64(t64
, t64
, s64
);
3583 /* Ignore the bits below the sign bit. */
3584 tcg_gen_andi_i64(t64
, t64
, -1ULL << (bits
- 1));
3585 /* If any bits remain set, we have overflow. */
3586 tcg_gen_setcondi_i64(TCG_COND_NE
, t64
, t64
, 0);
3587 tcg_gen_extrl_i64_i32(QREG_CC_V
, t64
);
3588 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3591 tcg_gen_shli_i64(t64
, t64
, 32);
3593 tcg_gen_shr_i64(t64
, t64
, s64
);
3595 tcg_gen_sar_i64(t64
, t64
, s64
);
3597 tcg_gen_extr_i64_i32(QREG_CC_C
, QREG_CC_N
, t64
);
3599 /* Note that C=0 if shift count is 0, and we get that for free. */
3600 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_C
, 31);
3602 /* X = C, but only if the shift count was non-zero. */
3603 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3604 QREG_CC_C
, QREG_CC_X
);
3606 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3607 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3610 tcg_temp_free_i64(s64
);
3611 tcg_temp_free_i64(t64
);
3613 /* Write back the result. */
3614 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3615 set_cc_op(s
, CC_OP_FLAGS
);
3618 DISAS_INSN(shift8_im
)
3620 shift_im(s
, insn
, OS_BYTE
);
3623 DISAS_INSN(shift16_im
)
3625 shift_im(s
, insn
, OS_WORD
);
3628 DISAS_INSN(shift_im
)
3630 shift_im(s
, insn
, OS_LONG
);
3633 DISAS_INSN(shift8_reg
)
3635 shift_reg(s
, insn
, OS_BYTE
);
3638 DISAS_INSN(shift16_reg
)
3640 shift_reg(s
, insn
, OS_WORD
);
3643 DISAS_INSN(shift_reg
)
3645 shift_reg(s
, insn
, OS_LONG
);
3648 DISAS_INSN(shift_mem
)
3650 int logical
= insn
& 8;
3651 int left
= insn
& 0x100;
3655 SRC_EA(env
, src
, OS_WORD
, !logical
, &addr
);
3656 tcg_gen_movi_i32(QREG_CC_V
, 0);
3658 tcg_gen_shri_i32(QREG_CC_C
, src
, 15);
3659 tcg_gen_shli_i32(QREG_CC_N
, src
, 1);
3662 * Note that ColdFire always clears V,
3663 * while M68000 sets if the most significant bit is changed at
3664 * any time during the shift operation
3666 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3667 src
= gen_extend(s
, src
, OS_WORD
, 1);
3668 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3671 tcg_gen_mov_i32(QREG_CC_C
, src
);
3673 tcg_gen_shri_i32(QREG_CC_N
, src
, 1);
3675 tcg_gen_sari_i32(QREG_CC_N
, src
, 1);
3679 gen_ext(QREG_CC_N
, QREG_CC_N
, OS_WORD
, 1);
3680 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3681 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3682 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3684 DEST_EA(env
, insn
, OS_WORD
, QREG_CC_N
, &addr
);
3685 set_cc_op(s
, CC_OP_FLAGS
);
3688 static void rotate(TCGv reg
, TCGv shift
, int left
, int size
)
3692 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3693 tcg_gen_ext8u_i32(reg
, reg
);
3694 tcg_gen_muli_i32(reg
, reg
, 0x01010101);
3697 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3698 tcg_gen_deposit_i32(reg
, reg
, reg
, 16, 16);
3703 tcg_gen_rotl_i32(reg
, reg
, shift
);
3705 tcg_gen_rotr_i32(reg
, reg
, shift
);
3713 tcg_gen_ext8s_i32(reg
, reg
);
3716 tcg_gen_ext16s_i32(reg
, reg
);
3722 /* QREG_CC_X is not affected */
3724 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3725 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3728 tcg_gen_andi_i32(QREG_CC_C
, reg
, 1);
3730 tcg_gen_shri_i32(QREG_CC_C
, reg
, 31);
3733 tcg_gen_movi_i32(QREG_CC_V
, 0); /* always cleared */
3736 static void rotate_x_flags(TCGv reg
, TCGv X
, int size
)
3740 tcg_gen_ext8s_i32(reg
, reg
);
3743 tcg_gen_ext16s_i32(reg
, reg
);
3748 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3749 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3750 tcg_gen_mov_i32(QREG_CC_X
, X
);
3751 tcg_gen_mov_i32(QREG_CC_C
, X
);
3752 tcg_gen_movi_i32(QREG_CC_V
, 0);
3755 /* Result of rotate_x() is valid if 0 <= shift <= size */
3756 static TCGv
rotate_x(TCGv reg
, TCGv shift
, int left
, int size
)
3758 TCGv X
, shl
, shr
, shx
, sz
, zero
;
3760 sz
= tcg_const_i32(size
);
3762 shr
= tcg_temp_new();
3763 shl
= tcg_temp_new();
3764 shx
= tcg_temp_new();
3766 tcg_gen_mov_i32(shl
, shift
); /* shl = shift */
3767 tcg_gen_movi_i32(shr
, size
+ 1);
3768 tcg_gen_sub_i32(shr
, shr
, shift
); /* shr = size + 1 - shift */
3769 tcg_gen_subi_i32(shx
, shift
, 1); /* shx = shift - 1 */
3770 /* shx = shx < 0 ? size : shx; */
3771 zero
= tcg_const_i32(0);
3772 tcg_gen_movcond_i32(TCG_COND_LT
, shx
, shx
, zero
, sz
, shx
);
3773 tcg_temp_free(zero
);
3775 tcg_gen_mov_i32(shr
, shift
); /* shr = shift */
3776 tcg_gen_movi_i32(shl
, size
+ 1);
3777 tcg_gen_sub_i32(shl
, shl
, shift
); /* shl = size + 1 - shift */
3778 tcg_gen_sub_i32(shx
, sz
, shift
); /* shx = size - shift */
3780 tcg_temp_free_i32(sz
);
3782 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3784 tcg_gen_shl_i32(shl
, reg
, shl
);
3785 tcg_gen_shr_i32(shr
, reg
, shr
);
3786 tcg_gen_or_i32(reg
, shl
, shr
);
3789 tcg_gen_shl_i32(shx
, QREG_CC_X
, shx
);
3790 tcg_gen_or_i32(reg
, reg
, shx
);
3793 /* X = (reg >> size) & 1 */
3796 tcg_gen_extract_i32(X
, reg
, size
, 1);
3801 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3802 static TCGv
rotate32_x(TCGv reg
, TCGv shift
, int left
)
3804 TCGv_i64 t0
, shift64
;
3805 TCGv X
, lo
, hi
, zero
;
3807 shift64
= tcg_temp_new_i64();
3808 tcg_gen_extu_i32_i64(shift64
, shift
);
3810 t0
= tcg_temp_new_i64();
3813 lo
= tcg_temp_new();
3814 hi
= tcg_temp_new();
3817 /* create [reg:X:..] */
3819 tcg_gen_shli_i32(lo
, QREG_CC_X
, 31);
3820 tcg_gen_concat_i32_i64(t0
, lo
, reg
);
3824 tcg_gen_rotl_i64(t0
, t0
, shift64
);
3825 tcg_temp_free_i64(shift64
);
3827 /* result is [reg:..:reg:X] */
3829 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3830 tcg_gen_andi_i32(X
, lo
, 1);
3832 tcg_gen_shri_i32(lo
, lo
, 1);
3834 /* create [..:X:reg] */
3836 tcg_gen_concat_i32_i64(t0
, reg
, QREG_CC_X
);
3838 tcg_gen_rotr_i64(t0
, t0
, shift64
);
3839 tcg_temp_free_i64(shift64
);
3841 /* result is value: [X:reg:..:reg] */
3843 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3847 tcg_gen_shri_i32(X
, hi
, 31);
3849 /* extract result */
3851 tcg_gen_shli_i32(hi
, hi
, 1);
3853 tcg_temp_free_i64(t0
);
3854 tcg_gen_or_i32(lo
, lo
, hi
);
3857 /* if shift == 0, register and X are not affected */
3859 zero
= tcg_const_i32(0);
3860 tcg_gen_movcond_i32(TCG_COND_EQ
, X
, shift
, zero
, QREG_CC_X
, X
);
3861 tcg_gen_movcond_i32(TCG_COND_EQ
, reg
, shift
, zero
, reg
, lo
);
3862 tcg_temp_free(zero
);
3868 DISAS_INSN(rotate_im
)
3872 int left
= (insn
& 0x100);
3874 tmp
= (insn
>> 9) & 7;
3879 shift
= tcg_const_i32(tmp
);
3881 rotate(DREG(insn
, 0), shift
, left
, 32);
3883 TCGv X
= rotate32_x(DREG(insn
, 0), shift
, left
);
3884 rotate_x_flags(DREG(insn
, 0), X
, 32);
3887 tcg_temp_free(shift
);
3889 set_cc_op(s
, CC_OP_FLAGS
);
3892 DISAS_INSN(rotate8_im
)
3894 int left
= (insn
& 0x100);
3899 reg
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
3901 tmp
= (insn
>> 9) & 7;
3906 shift
= tcg_const_i32(tmp
);
3908 rotate(reg
, shift
, left
, 8);
3910 TCGv X
= rotate_x(reg
, shift
, left
, 8);
3911 rotate_x_flags(reg
, X
, 8);
3914 tcg_temp_free(shift
);
3915 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3916 set_cc_op(s
, CC_OP_FLAGS
);
3919 DISAS_INSN(rotate16_im
)
3921 int left
= (insn
& 0x100);
3926 reg
= gen_extend(s
, DREG(insn
, 0), OS_WORD
, 0);
3927 tmp
= (insn
>> 9) & 7;
3932 shift
= tcg_const_i32(tmp
);
3934 rotate(reg
, shift
, left
, 16);
3936 TCGv X
= rotate_x(reg
, shift
, left
, 16);
3937 rotate_x_flags(reg
, X
, 16);
3940 tcg_temp_free(shift
);
3941 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3942 set_cc_op(s
, CC_OP_FLAGS
);
3945 DISAS_INSN(rotate_reg
)
3950 int left
= (insn
& 0x100);
3952 reg
= DREG(insn
, 0);
3953 src
= DREG(insn
, 9);
3954 /* shift in [0..63] */
3955 t0
= tcg_temp_new();
3956 tcg_gen_andi_i32(t0
, src
, 63);
3957 t1
= tcg_temp_new_i32();
3959 tcg_gen_andi_i32(t1
, src
, 31);
3960 rotate(reg
, t1
, left
, 32);
3961 /* if shift == 0, clear C */
3962 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3963 t0
, QREG_CC_V
/* 0 */,
3964 QREG_CC_V
/* 0 */, QREG_CC_C
);
3968 tcg_gen_movi_i32(t1
, 33);
3969 tcg_gen_remu_i32(t1
, t0
, t1
);
3970 X
= rotate32_x(DREG(insn
, 0), t1
, left
);
3971 rotate_x_flags(DREG(insn
, 0), X
, 32);
3976 set_cc_op(s
, CC_OP_FLAGS
);
3979 DISAS_INSN(rotate8_reg
)
3984 int left
= (insn
& 0x100);
3986 reg
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
3987 src
= DREG(insn
, 9);
3988 /* shift in [0..63] */
3989 t0
= tcg_temp_new_i32();
3990 tcg_gen_andi_i32(t0
, src
, 63);
3991 t1
= tcg_temp_new_i32();
3993 tcg_gen_andi_i32(t1
, src
, 7);
3994 rotate(reg
, t1
, left
, 8);
3995 /* if shift == 0, clear C */
3996 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3997 t0
, QREG_CC_V
/* 0 */,
3998 QREG_CC_V
/* 0 */, QREG_CC_C
);
4002 tcg_gen_movi_i32(t1
, 9);
4003 tcg_gen_remu_i32(t1
, t0
, t1
);
4004 X
= rotate_x(reg
, t1
, left
, 8);
4005 rotate_x_flags(reg
, X
, 8);
4010 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
4011 set_cc_op(s
, CC_OP_FLAGS
);
4014 DISAS_INSN(rotate16_reg
)
4019 int left
= (insn
& 0x100);
4021 reg
= gen_extend(s
, DREG(insn
, 0), OS_WORD
, 0);
4022 src
= DREG(insn
, 9);
4023 /* shift in [0..63] */
4024 t0
= tcg_temp_new_i32();
4025 tcg_gen_andi_i32(t0
, src
, 63);
4026 t1
= tcg_temp_new_i32();
4028 tcg_gen_andi_i32(t1
, src
, 15);
4029 rotate(reg
, t1
, left
, 16);
4030 /* if shift == 0, clear C */
4031 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
4032 t0
, QREG_CC_V
/* 0 */,
4033 QREG_CC_V
/* 0 */, QREG_CC_C
);
4037 tcg_gen_movi_i32(t1
, 17);
4038 tcg_gen_remu_i32(t1
, t0
, t1
);
4039 X
= rotate_x(reg
, t1
, left
, 16);
4040 rotate_x_flags(reg
, X
, 16);
4045 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
4046 set_cc_op(s
, CC_OP_FLAGS
);
4049 DISAS_INSN(rotate_mem
)
4054 int left
= (insn
& 0x100);
4056 SRC_EA(env
, src
, OS_WORD
, 0, &addr
);
4058 shift
= tcg_const_i32(1);
4059 if (insn
& 0x0200) {
4060 rotate(src
, shift
, left
, 16);
4062 TCGv X
= rotate_x(src
, shift
, left
, 16);
4063 rotate_x_flags(src
, X
, 16);
4066 tcg_temp_free(shift
);
4067 DEST_EA(env
, insn
, OS_WORD
, src
, &addr
);
4068 set_cc_op(s
, CC_OP_FLAGS
);
4071 DISAS_INSN(bfext_reg
)
4073 int ext
= read_im16(env
, s
);
4074 int is_sign
= insn
& 0x200;
4075 TCGv src
= DREG(insn
, 0);
4076 TCGv dst
= DREG(ext
, 12);
4077 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4078 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4079 int pos
= 32 - ofs
- len
; /* little bit-endian */
4080 TCGv tmp
= tcg_temp_new();
4084 * In general, we're going to rotate the field so that it's at the
4085 * top of the word and then right-shift by the complement of the
4086 * width to extend the field.
4089 /* Variable width. */
4091 /* Variable offset. */
4092 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4093 tcg_gen_rotl_i32(tmp
, src
, tmp
);
4095 tcg_gen_rotli_i32(tmp
, src
, ofs
);
4098 shift
= tcg_temp_new();
4099 tcg_gen_neg_i32(shift
, DREG(ext
, 0));
4100 tcg_gen_andi_i32(shift
, shift
, 31);
4101 tcg_gen_sar_i32(QREG_CC_N
, tmp
, shift
);
4103 tcg_gen_mov_i32(dst
, QREG_CC_N
);
4105 tcg_gen_shr_i32(dst
, tmp
, shift
);
4107 tcg_temp_free(shift
);
4109 /* Immediate width. */
4111 /* Variable offset */
4112 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4113 tcg_gen_rotl_i32(tmp
, src
, tmp
);
4118 * Immediate offset. If the field doesn't wrap around the
4119 * end of the word, rely on (s)extract completely.
4122 tcg_gen_rotli_i32(tmp
, src
, ofs
);
4128 tcg_gen_sextract_i32(QREG_CC_N
, src
, pos
, len
);
4130 tcg_gen_mov_i32(dst
, QREG_CC_N
);
4132 tcg_gen_extract_i32(dst
, src
, pos
, len
);
4137 set_cc_op(s
, CC_OP_LOGIC
);
4140 DISAS_INSN(bfext_mem
)
4142 int ext
= read_im16(env
, s
);
4143 int is_sign
= insn
& 0x200;
4144 TCGv dest
= DREG(ext
, 12);
4145 TCGv addr
, len
, ofs
;
4147 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4148 if (IS_NULL_QREG(addr
)) {
4156 len
= tcg_const_i32(extract32(ext
, 0, 5));
4161 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4165 gen_helper_bfexts_mem(dest
, cpu_env
, addr
, ofs
, len
);
4166 tcg_gen_mov_i32(QREG_CC_N
, dest
);
4168 TCGv_i64 tmp
= tcg_temp_new_i64();
4169 gen_helper_bfextu_mem(tmp
, cpu_env
, addr
, ofs
, len
);
4170 tcg_gen_extr_i64_i32(dest
, QREG_CC_N
, tmp
);
4171 tcg_temp_free_i64(tmp
);
4173 set_cc_op(s
, CC_OP_LOGIC
);
4175 if (!(ext
& 0x20)) {
4178 if (!(ext
& 0x800)) {
4183 DISAS_INSN(bfop_reg
)
4185 int ext
= read_im16(env
, s
);
4186 TCGv src
= DREG(insn
, 0);
4187 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4188 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4189 TCGv mask
, tofs
, tlen
;
4193 if ((insn
& 0x0f00) == 0x0d00) { /* bfffo */
4194 tofs
= tcg_temp_new();
4195 tlen
= tcg_temp_new();
4198 if ((ext
& 0x820) == 0) {
4199 /* Immediate width and offset. */
4200 uint32_t maski
= 0x7fffffffu
>> (len
- 1);
4201 if (ofs
+ len
<= 32) {
4202 tcg_gen_shli_i32(QREG_CC_N
, src
, ofs
);
4204 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4206 tcg_gen_andi_i32(QREG_CC_N
, QREG_CC_N
, ~maski
);
4207 mask
= tcg_const_i32(ror32(maski
, ofs
));
4209 tcg_gen_movi_i32(tofs
, ofs
);
4210 tcg_gen_movi_i32(tlen
, len
);
4213 TCGv tmp
= tcg_temp_new();
4215 /* Variable width */
4216 tcg_gen_subi_i32(tmp
, DREG(ext
, 0), 1);
4217 tcg_gen_andi_i32(tmp
, tmp
, 31);
4218 mask
= tcg_const_i32(0x7fffffffu
);
4219 tcg_gen_shr_i32(mask
, mask
, tmp
);
4221 tcg_gen_addi_i32(tlen
, tmp
, 1);
4224 /* Immediate width */
4225 mask
= tcg_const_i32(0x7fffffffu
>> (len
- 1));
4227 tcg_gen_movi_i32(tlen
, len
);
4231 /* Variable offset */
4232 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4233 tcg_gen_rotl_i32(QREG_CC_N
, src
, tmp
);
4234 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4235 tcg_gen_rotr_i32(mask
, mask
, tmp
);
4237 tcg_gen_mov_i32(tofs
, tmp
);
4240 /* Immediate offset (and variable width) */
4241 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4242 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4243 tcg_gen_rotri_i32(mask
, mask
, ofs
);
4245 tcg_gen_movi_i32(tofs
, ofs
);
4250 set_cc_op(s
, CC_OP_LOGIC
);
4252 switch (insn
& 0x0f00) {
4253 case 0x0a00: /* bfchg */
4254 tcg_gen_eqv_i32(src
, src
, mask
);
4256 case 0x0c00: /* bfclr */
4257 tcg_gen_and_i32(src
, src
, mask
);
4259 case 0x0d00: /* bfffo */
4260 gen_helper_bfffo_reg(DREG(ext
, 12), QREG_CC_N
, tofs
, tlen
);
4261 tcg_temp_free(tlen
);
4262 tcg_temp_free(tofs
);
4264 case 0x0e00: /* bfset */
4265 tcg_gen_orc_i32(src
, src
, mask
);
4267 case 0x0800: /* bftst */
4268 /* flags already set; no other work to do. */
4271 g_assert_not_reached();
4273 tcg_temp_free(mask
);
4276 DISAS_INSN(bfop_mem
)
4278 int ext
= read_im16(env
, s
);
4279 TCGv addr
, len
, ofs
;
4282 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4283 if (IS_NULL_QREG(addr
)) {
4291 len
= tcg_const_i32(extract32(ext
, 0, 5));
4296 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4299 switch (insn
& 0x0f00) {
4300 case 0x0a00: /* bfchg */
4301 gen_helper_bfchg_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4303 case 0x0c00: /* bfclr */
4304 gen_helper_bfclr_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4306 case 0x0d00: /* bfffo */
4307 t64
= tcg_temp_new_i64();
4308 gen_helper_bfffo_mem(t64
, cpu_env
, addr
, ofs
, len
);
4309 tcg_gen_extr_i64_i32(DREG(ext
, 12), QREG_CC_N
, t64
);
4310 tcg_temp_free_i64(t64
);
4312 case 0x0e00: /* bfset */
4313 gen_helper_bfset_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4315 case 0x0800: /* bftst */
4316 gen_helper_bfexts_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4319 g_assert_not_reached();
4321 set_cc_op(s
, CC_OP_LOGIC
);
4323 if (!(ext
& 0x20)) {
4326 if (!(ext
& 0x800)) {
4331 DISAS_INSN(bfins_reg
)
4333 int ext
= read_im16(env
, s
);
4334 TCGv dst
= DREG(insn
, 0);
4335 TCGv src
= DREG(ext
, 12);
4336 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4337 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4338 int pos
= 32 - ofs
- len
; /* little bit-endian */
4341 tmp
= tcg_temp_new();
4344 /* Variable width */
4345 tcg_gen_neg_i32(tmp
, DREG(ext
, 0));
4346 tcg_gen_andi_i32(tmp
, tmp
, 31);
4347 tcg_gen_shl_i32(QREG_CC_N
, src
, tmp
);
4349 /* Immediate width */
4350 tcg_gen_shli_i32(QREG_CC_N
, src
, 32 - len
);
4352 set_cc_op(s
, CC_OP_LOGIC
);
4354 /* Immediate width and offset */
4355 if ((ext
& 0x820) == 0) {
4356 /* Check for suitability for deposit. */
4358 tcg_gen_deposit_i32(dst
, dst
, src
, pos
, len
);
4360 uint32_t maski
= -2U << (len
- 1);
4361 uint32_t roti
= (ofs
+ len
) & 31;
4362 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4363 tcg_gen_rotri_i32(tmp
, tmp
, roti
);
4364 tcg_gen_andi_i32(dst
, dst
, ror32(maski
, roti
));
4365 tcg_gen_or_i32(dst
, dst
, tmp
);
4368 TCGv mask
= tcg_temp_new();
4369 TCGv rot
= tcg_temp_new();
4372 /* Variable width */
4373 tcg_gen_subi_i32(rot
, DREG(ext
, 0), 1);
4374 tcg_gen_andi_i32(rot
, rot
, 31);
4375 tcg_gen_movi_i32(mask
, -2);
4376 tcg_gen_shl_i32(mask
, mask
, rot
);
4377 tcg_gen_mov_i32(rot
, DREG(ext
, 0));
4378 tcg_gen_andc_i32(tmp
, src
, mask
);
4380 /* Immediate width (variable offset) */
4381 uint32_t maski
= -2U << (len
- 1);
4382 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4383 tcg_gen_movi_i32(mask
, maski
);
4384 tcg_gen_movi_i32(rot
, len
& 31);
4387 /* Variable offset */
4388 tcg_gen_add_i32(rot
, rot
, DREG(ext
, 6));
4390 /* Immediate offset (variable width) */
4391 tcg_gen_addi_i32(rot
, rot
, ofs
);
4393 tcg_gen_andi_i32(rot
, rot
, 31);
4394 tcg_gen_rotr_i32(mask
, mask
, rot
);
4395 tcg_gen_rotr_i32(tmp
, tmp
, rot
);
4396 tcg_gen_and_i32(dst
, dst
, mask
);
4397 tcg_gen_or_i32(dst
, dst
, tmp
);
4400 tcg_temp_free(mask
);
4405 DISAS_INSN(bfins_mem
)
4407 int ext
= read_im16(env
, s
);
4408 TCGv src
= DREG(ext
, 12);
4409 TCGv addr
, len
, ofs
;
4411 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4412 if (IS_NULL_QREG(addr
)) {
4420 len
= tcg_const_i32(extract32(ext
, 0, 5));
4425 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4428 gen_helper_bfins_mem(QREG_CC_N
, cpu_env
, addr
, src
, ofs
, len
);
4429 set_cc_op(s
, CC_OP_LOGIC
);
4431 if (!(ext
& 0x20)) {
4434 if (!(ext
& 0x800)) {
4442 reg
= DREG(insn
, 0);
4443 gen_logic_cc(s
, reg
, OS_LONG
);
4444 gen_helper_ff1(reg
, reg
);
4452 switch ((insn
>> 7) & 3) {
4457 if (m68k_feature(env
, M68K_FEATURE_CHK2
)) {
4463 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4466 SRC_EA(env
, src
, opsize
, 1, NULL
);
4467 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
4470 gen_helper_chk(cpu_env
, reg
, src
);
4476 TCGv addr1
, addr2
, bound1
, bound2
, reg
;
4479 switch ((insn
>> 9) & 3) {
4490 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4494 ext
= read_im16(env
, s
);
4495 if ((ext
& 0x0800) == 0) {
4496 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4500 addr1
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4501 addr2
= tcg_temp_new();
4502 tcg_gen_addi_i32(addr2
, addr1
, opsize_bytes(opsize
));
4504 bound1
= gen_load(s
, opsize
, addr1
, 1, IS_USER(s
));
4505 tcg_temp_free(addr1
);
4506 bound2
= gen_load(s
, opsize
, addr2
, 1, IS_USER(s
));
4507 tcg_temp_free(addr2
);
4509 reg
= tcg_temp_new();
4511 tcg_gen_mov_i32(reg
, AREG(ext
, 12));
4513 gen_ext(reg
, DREG(ext
, 12), opsize
, 1);
4517 gen_helper_chk2(cpu_env
, reg
, bound1
, bound2
);
4519 tcg_temp_free(bound1
);
4520 tcg_temp_free(bound2
);
4523 static void m68k_copy_line(TCGv dst
, TCGv src
, int index
)
4528 addr
= tcg_temp_new();
4530 t0
= tcg_temp_new_i64();
4531 t1
= tcg_temp_new_i64();
4533 tcg_gen_andi_i32(addr
, src
, ~15);
4534 tcg_gen_qemu_ld64(t0
, addr
, index
);
4535 tcg_gen_addi_i32(addr
, addr
, 8);
4536 tcg_gen_qemu_ld64(t1
, addr
, index
);
4538 tcg_gen_andi_i32(addr
, dst
, ~15);
4539 tcg_gen_qemu_st64(t0
, addr
, index
);
4540 tcg_gen_addi_i32(addr
, addr
, 8);
4541 tcg_gen_qemu_st64(t1
, addr
, index
);
4543 tcg_temp_free_i64(t0
);
4544 tcg_temp_free_i64(t1
);
4545 tcg_temp_free(addr
);
4548 DISAS_INSN(move16_reg
)
4550 int index
= IS_USER(s
);
4554 ext
= read_im16(env
, s
);
4555 if ((ext
& (1 << 15)) == 0) {
4556 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4559 m68k_copy_line(AREG(ext
, 12), AREG(insn
, 0), index
);
4561 /* Ax can be Ay, so save Ay before incrementing Ax */
4562 tmp
= tcg_temp_new();
4563 tcg_gen_mov_i32(tmp
, AREG(ext
, 12));
4564 tcg_gen_addi_i32(AREG(insn
, 0), AREG(insn
, 0), 16);
4565 tcg_gen_addi_i32(AREG(ext
, 12), tmp
, 16);
4569 DISAS_INSN(move16_mem
)
4571 int index
= IS_USER(s
);
4574 reg
= AREG(insn
, 0);
4575 addr
= tcg_const_i32(read_im32(env
, s
));
4577 if ((insn
>> 3) & 1) {
4578 /* MOVE16 (xxx).L, (Ay) */
4579 m68k_copy_line(reg
, addr
, index
);
4581 /* MOVE16 (Ay), (xxx).L */
4582 m68k_copy_line(addr
, reg
, index
);
4585 tcg_temp_free(addr
);
4587 if (((insn
>> 3) & 2) == 0) {
4589 tcg_gen_addi_i32(reg
, reg
, 16);
4599 ext
= read_im16(env
, s
);
4600 if (ext
!= 0x46FC) {
4601 gen_exception(s
, addr
, EXCP_ILLEGAL
);
4604 ext
= read_im16(env
, s
);
4605 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
4606 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
4609 gen_push(s
, gen_get_sr(s
));
4610 gen_set_sr_im(s
, ext
, 0);
4613 DISAS_INSN(move_from_sr
)
4617 if (IS_USER(s
) && !m68k_feature(env
, M68K_FEATURE_M68000
)) {
4618 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4622 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
4625 #if defined(CONFIG_SOFTMMU)
4635 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4639 ext
= read_im16(env
, s
);
4641 opsize
= insn_opsize(insn
);
4644 /* address register */
4645 reg
= AREG(ext
, 12);
4649 reg
= DREG(ext
, 12);
4653 addr
= gen_lea(env
, s
, insn
, opsize
);
4654 if (IS_NULL_QREG(addr
)) {
4660 /* from reg to ea */
4661 gen_store(s
, opsize
, addr
, reg
, DFC_INDEX(s
));
4663 /* from ea to reg */
4664 TCGv tmp
= gen_load(s
, opsize
, addr
, 0, SFC_INDEX(s
));
4666 gen_ext(reg
, tmp
, opsize
, 1);
4668 gen_partset_reg(opsize
, reg
, tmp
);
4672 switch (extract32(insn
, 3, 3)) {
4673 case 3: /* Indirect postincrement. */
4674 tcg_gen_addi_i32(AREG(insn
, 0), addr
,
4675 REG(insn
, 0) == 7 && opsize
== OS_BYTE
4677 : opsize_bytes(opsize
));
4679 case 4: /* Indirect predecrememnt. */
4680 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4685 DISAS_INSN(move_to_sr
)
4688 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4691 gen_move_to_sr(env
, s
, insn
, false);
4695 DISAS_INSN(move_from_usp
)
4698 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4701 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
4702 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4705 DISAS_INSN(move_to_usp
)
4708 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4711 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
4712 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4718 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4722 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
4730 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4734 ext
= read_im16(env
, s
);
4736 gen_set_sr_im(s
, ext
, 0);
4737 tcg_gen_movi_i32(cpu_halted
, 1);
4738 gen_exception(s
, s
->pc
, EXCP_HLT
);
4744 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4747 gen_exception(s
, s
->base
.pc_next
, EXCP_RTE
);
4750 DISAS_INSN(cf_movec
)
4756 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4760 ext
= read_im16(env
, s
);
4763 reg
= AREG(ext
, 12);
4765 reg
= DREG(ext
, 12);
4767 gen_helper_cf_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4771 DISAS_INSN(m68k_movec
)
4777 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4781 ext
= read_im16(env
, s
);
4784 reg
= AREG(ext
, 12);
4786 reg
= DREG(ext
, 12);
4789 gen_helper_m68k_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4791 gen_helper_m68k_movec_from(reg
, cpu_env
, tcg_const_i32(ext
& 0xfff));
4799 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4802 /* ICache fetch. Implement as no-op. */
4808 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4811 /* Cache push/invalidate. Implement as no-op. */
4817 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4820 /* Cache push/invalidate. Implement as no-op. */
4826 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4829 /* Invalidate cache line. Implement as no-op. */
4832 #if defined(CONFIG_SOFTMMU)
4838 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4842 opmode
= tcg_const_i32((insn
>> 3) & 3);
4843 gen_helper_pflush(cpu_env
, AREG(insn
, 0), opmode
);
4844 tcg_temp_free(opmode
);
4852 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4855 is_read
= tcg_const_i32((insn
>> 5) & 1);
4856 gen_helper_ptest(cpu_env
, AREG(insn
, 0), is_read
);
4857 tcg_temp_free(is_read
);
4863 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4869 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4872 /* TODO: Implement wdebug. */
4873 cpu_abort(env_cpu(env
), "WDEBUG not implemented");
4879 gen_exception(s
, s
->pc
, EXCP_TRAP0
+ (insn
& 0xf));
4882 static void gen_load_fcr(DisasContext
*s
, TCGv res
, int reg
)
4886 tcg_gen_movi_i32(res
, 0);
4889 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4892 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpcr
));
4897 static void gen_store_fcr(DisasContext
*s
, TCGv val
, int reg
)
4903 tcg_gen_st_i32(val
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4906 gen_helper_set_fpcr(cpu_env
, val
);
4911 static void gen_qemu_store_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4913 int index
= IS_USER(s
);
4916 tmp
= tcg_temp_new();
4917 gen_load_fcr(s
, tmp
, reg
);
4918 tcg_gen_qemu_st32(tmp
, addr
, index
);
4922 static void gen_qemu_load_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4924 int index
= IS_USER(s
);
4927 tmp
= tcg_temp_new();
4928 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
4929 gen_store_fcr(s
, tmp
, reg
);
4934 static void gen_op_fmove_fcr(CPUM68KState
*env
, DisasContext
*s
,
4935 uint32_t insn
, uint32_t ext
)
4937 int mask
= (ext
>> 10) & 7;
4938 int is_write
= (ext
>> 13) & 1;
4939 int mode
= extract32(insn
, 3, 3);
4945 if (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&& mask
!= M68K_FPCR
) {
4946 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4950 gen_load_fcr(s
, DREG(insn
, 0), mask
);
4952 gen_store_fcr(s
, DREG(insn
, 0), mask
);
4955 case 1: /* An, only with FPIAR */
4956 if (mask
!= M68K_FPIAR
) {
4957 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4961 gen_load_fcr(s
, AREG(insn
, 0), mask
);
4963 gen_store_fcr(s
, AREG(insn
, 0), mask
);
4966 case 7: /* Immediate */
4967 if (REG(insn
, 0) == 4) {
4969 (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&&
4970 mask
!= M68K_FPCR
)) {
4971 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4974 tmp
= tcg_const_i32(read_im32(env
, s
));
4975 gen_store_fcr(s
, tmp
, mask
);
4984 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
4985 if (IS_NULL_QREG(tmp
)) {
4990 addr
= tcg_temp_new();
4991 tcg_gen_mov_i32(addr
, tmp
);
4996 * 0b100 Floating-Point Control Register
4997 * 0b010 Floating-Point Status Register
4998 * 0b001 Floating-Point Instruction Address Register
5002 if (is_write
&& mode
== 4) {
5003 for (i
= 2; i
>= 0; i
--, mask
>>= 1) {
5005 gen_qemu_store_fcr(s
, addr
, 1 << i
);
5007 tcg_gen_subi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
5011 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5013 for (i
= 0; i
< 3; i
++, mask
>>= 1) {
5016 gen_qemu_store_fcr(s
, addr
, 1 << i
);
5018 gen_qemu_load_fcr(s
, addr
, 1 << i
);
5020 if (mask
!= 1 || mode
== 3) {
5021 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
5026 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5029 tcg_temp_free_i32(addr
);
5032 static void gen_op_fmovem(CPUM68KState
*env
, DisasContext
*s
,
5033 uint32_t insn
, uint32_t ext
)
5037 int mode
= (ext
>> 11) & 0x3;
5038 int is_load
= ((ext
& 0x2000) == 0);
5040 if (m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
5041 opsize
= OS_EXTENDED
;
5043 opsize
= OS_DOUBLE
; /* FIXME */
5046 addr
= gen_lea(env
, s
, insn
, opsize
);
5047 if (IS_NULL_QREG(addr
)) {
5052 tmp
= tcg_temp_new();
5054 /* Dynamic register list */
5055 tcg_gen_ext8u_i32(tmp
, DREG(ext
, 4));
5057 /* Static register list */
5058 tcg_gen_movi_i32(tmp
, ext
& 0xff);
5061 if (!is_load
&& (mode
& 2) == 0) {
5063 * predecrement addressing mode
5064 * only available to store register to memory
5066 if (opsize
== OS_EXTENDED
) {
5067 gen_helper_fmovemx_st_predec(tmp
, cpu_env
, addr
, tmp
);
5069 gen_helper_fmovemd_st_predec(tmp
, cpu_env
, addr
, tmp
);
5072 /* postincrement addressing mode */
5073 if (opsize
== OS_EXTENDED
) {
5075 gen_helper_fmovemx_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
5077 gen_helper_fmovemx_st_postinc(tmp
, cpu_env
, addr
, tmp
);
5081 gen_helper_fmovemd_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
5083 gen_helper_fmovemd_st_postinc(tmp
, cpu_env
, addr
, tmp
);
5087 if ((insn
& 070) == 030 || (insn
& 070) == 040) {
5088 tcg_gen_mov_i32(AREG(insn
, 0), tmp
);
5094 * ??? FP exceptions are not implemented. Most exceptions are deferred until
5095 * immediately before the next FP instruction is executed.
5102 TCGv_ptr cpu_src
, cpu_dest
;
5104 ext
= read_im16(env
, s
);
5105 opmode
= ext
& 0x7f;
5106 switch ((ext
>> 13) & 7) {
5112 if (insn
== 0xf200 && (ext
& 0xfc00) == 0x5c00) {
5114 TCGv rom_offset
= tcg_const_i32(opmode
);
5115 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
5116 gen_helper_fconst(cpu_env
, cpu_dest
, rom_offset
);
5117 tcg_temp_free_ptr(cpu_dest
);
5118 tcg_temp_free(rom_offset
);
5122 case 3: /* fmove out */
5123 cpu_src
= gen_fp_ptr(REG(ext
, 7));
5124 opsize
= ext_opsize(ext
, 10);
5125 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
,
5126 EA_STORE
, IS_USER(s
)) == -1) {
5129 gen_helper_ftst(cpu_env
, cpu_src
);
5130 tcg_temp_free_ptr(cpu_src
);
5132 case 4: /* fmove to control register. */
5133 case 5: /* fmove from control register. */
5134 gen_op_fmove_fcr(env
, s
, insn
, ext
);
5136 case 6: /* fmovem */
5138 if ((ext
& 0x1000) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
5141 gen_op_fmovem(env
, s
, insn
, ext
);
5144 if (ext
& (1 << 14)) {
5145 /* Source effective address. */
5146 opsize
= ext_opsize(ext
, 10);
5147 cpu_src
= gen_fp_result_ptr();
5148 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
,
5149 EA_LOADS
, IS_USER(s
)) == -1) {
5154 /* Source register. */
5155 opsize
= OS_EXTENDED
;
5156 cpu_src
= gen_fp_ptr(REG(ext
, 10));
5158 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
5161 gen_fp_move(cpu_dest
, cpu_src
);
5163 case 0x40: /* fsmove */
5164 gen_helper_fsround(cpu_env
, cpu_dest
, cpu_src
);
5166 case 0x44: /* fdmove */
5167 gen_helper_fdround(cpu_env
, cpu_dest
, cpu_src
);
5170 gen_helper_firound(cpu_env
, cpu_dest
, cpu_src
);
5173 gen_helper_fsinh(cpu_env
, cpu_dest
, cpu_src
);
5175 case 3: /* fintrz */
5176 gen_helper_fitrunc(cpu_env
, cpu_dest
, cpu_src
);
5179 gen_helper_fsqrt(cpu_env
, cpu_dest
, cpu_src
);
5181 case 0x41: /* fssqrt */
5182 gen_helper_fssqrt(cpu_env
, cpu_dest
, cpu_src
);
5184 case 0x45: /* fdsqrt */
5185 gen_helper_fdsqrt(cpu_env
, cpu_dest
, cpu_src
);
5187 case 0x06: /* flognp1 */
5188 gen_helper_flognp1(cpu_env
, cpu_dest
, cpu_src
);
5190 case 0x08: /* fetoxm1 */
5191 gen_helper_fetoxm1(cpu_env
, cpu_dest
, cpu_src
);
5193 case 0x09: /* ftanh */
5194 gen_helper_ftanh(cpu_env
, cpu_dest
, cpu_src
);
5196 case 0x0a: /* fatan */
5197 gen_helper_fatan(cpu_env
, cpu_dest
, cpu_src
);
5199 case 0x0c: /* fasin */
5200 gen_helper_fasin(cpu_env
, cpu_dest
, cpu_src
);
5202 case 0x0d: /* fatanh */
5203 gen_helper_fatanh(cpu_env
, cpu_dest
, cpu_src
);
5205 case 0x0e: /* fsin */
5206 gen_helper_fsin(cpu_env
, cpu_dest
, cpu_src
);
5208 case 0x0f: /* ftan */
5209 gen_helper_ftan(cpu_env
, cpu_dest
, cpu_src
);
5211 case 0x10: /* fetox */
5212 gen_helper_fetox(cpu_env
, cpu_dest
, cpu_src
);
5214 case 0x11: /* ftwotox */
5215 gen_helper_ftwotox(cpu_env
, cpu_dest
, cpu_src
);
5217 case 0x12: /* ftentox */
5218 gen_helper_ftentox(cpu_env
, cpu_dest
, cpu_src
);
5220 case 0x14: /* flogn */
5221 gen_helper_flogn(cpu_env
, cpu_dest
, cpu_src
);
5223 case 0x15: /* flog10 */
5224 gen_helper_flog10(cpu_env
, cpu_dest
, cpu_src
);
5226 case 0x16: /* flog2 */
5227 gen_helper_flog2(cpu_env
, cpu_dest
, cpu_src
);
5229 case 0x18: /* fabs */
5230 gen_helper_fabs(cpu_env
, cpu_dest
, cpu_src
);
5232 case 0x58: /* fsabs */
5233 gen_helper_fsabs(cpu_env
, cpu_dest
, cpu_src
);
5235 case 0x5c: /* fdabs */
5236 gen_helper_fdabs(cpu_env
, cpu_dest
, cpu_src
);
5238 case 0x19: /* fcosh */
5239 gen_helper_fcosh(cpu_env
, cpu_dest
, cpu_src
);
5241 case 0x1a: /* fneg */
5242 gen_helper_fneg(cpu_env
, cpu_dest
, cpu_src
);
5244 case 0x5a: /* fsneg */
5245 gen_helper_fsneg(cpu_env
, cpu_dest
, cpu_src
);
5247 case 0x5e: /* fdneg */
5248 gen_helper_fdneg(cpu_env
, cpu_dest
, cpu_src
);
5250 case 0x1c: /* facos */
5251 gen_helper_facos(cpu_env
, cpu_dest
, cpu_src
);
5253 case 0x1d: /* fcos */
5254 gen_helper_fcos(cpu_env
, cpu_dest
, cpu_src
);
5256 case 0x1e: /* fgetexp */
5257 gen_helper_fgetexp(cpu_env
, cpu_dest
, cpu_src
);
5259 case 0x1f: /* fgetman */
5260 gen_helper_fgetman(cpu_env
, cpu_dest
, cpu_src
);
5262 case 0x20: /* fdiv */
5263 gen_helper_fdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5265 case 0x60: /* fsdiv */
5266 gen_helper_fsdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5268 case 0x64: /* fddiv */
5269 gen_helper_fddiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5271 case 0x21: /* fmod */
5272 gen_helper_fmod(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5274 case 0x22: /* fadd */
5275 gen_helper_fadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5277 case 0x62: /* fsadd */
5278 gen_helper_fsadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5280 case 0x66: /* fdadd */
5281 gen_helper_fdadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5283 case 0x23: /* fmul */
5284 gen_helper_fmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5286 case 0x63: /* fsmul */
5287 gen_helper_fsmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5289 case 0x67: /* fdmul */
5290 gen_helper_fdmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5292 case 0x24: /* fsgldiv */
5293 gen_helper_fsgldiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5295 case 0x25: /* frem */
5296 gen_helper_frem(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5298 case 0x26: /* fscale */
5299 gen_helper_fscale(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5301 case 0x27: /* fsglmul */
5302 gen_helper_fsglmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5304 case 0x28: /* fsub */
5305 gen_helper_fsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5307 case 0x68: /* fssub */
5308 gen_helper_fssub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5310 case 0x6c: /* fdsub */
5311 gen_helper_fdsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5313 case 0x30: case 0x31: case 0x32:
5314 case 0x33: case 0x34: case 0x35:
5315 case 0x36: case 0x37: {
5316 TCGv_ptr cpu_dest2
= gen_fp_ptr(REG(ext
, 0));
5317 gen_helper_fsincos(cpu_env
, cpu_dest
, cpu_dest2
, cpu_src
);
5318 tcg_temp_free_ptr(cpu_dest2
);
5321 case 0x38: /* fcmp */
5322 gen_helper_fcmp(cpu_env
, cpu_src
, cpu_dest
);
5324 case 0x3a: /* ftst */
5325 gen_helper_ftst(cpu_env
, cpu_src
);
5330 tcg_temp_free_ptr(cpu_src
);
5331 gen_helper_ftst(cpu_env
, cpu_dest
);
5332 tcg_temp_free_ptr(cpu_dest
);
5335 /* FIXME: Is this right for offset addressing modes? */
5337 disas_undef_fpu(env
, s
, insn
);
5340 static void gen_fcc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
5345 c
->v2
= tcg_const_i32(0);
5347 /* TODO: Raise BSUN exception. */
5348 fpsr
= tcg_temp_new();
5349 gen_load_fcr(s
, fpsr
, M68K_FPSR
);
5352 case 16: /* Signaling False */
5354 c
->tcond
= TCG_COND_NEVER
;
5356 case 1: /* EQual Z */
5357 case 17: /* Signaling EQual Z */
5358 c
->v1
= tcg_temp_new();
5360 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5361 c
->tcond
= TCG_COND_NE
;
5363 case 2: /* Ordered Greater Than !(A || Z || N) */
5364 case 18: /* Greater Than !(A || Z || N) */
5365 c
->v1
= tcg_temp_new();
5367 tcg_gen_andi_i32(c
->v1
, fpsr
,
5368 FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5369 c
->tcond
= TCG_COND_EQ
;
5371 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
5372 case 19: /* Greater than or Equal Z || !(A || N) */
5373 c
->v1
= tcg_temp_new();
5375 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5376 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5377 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_Z
| FPSR_CC_N
);
5378 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5379 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5380 c
->tcond
= TCG_COND_NE
;
5382 case 4: /* Ordered Less Than !(!N || A || Z); */
5383 case 20: /* Less Than !(!N || A || Z); */
5384 c
->v1
= tcg_temp_new();
5386 tcg_gen_xori_i32(c
->v1
, fpsr
, FPSR_CC_N
);
5387 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_N
| FPSR_CC_A
| FPSR_CC_Z
);
5388 c
->tcond
= TCG_COND_EQ
;
5390 case 5: /* Ordered Less than or Equal Z || (N && !A) */
5391 case 21: /* Less than or Equal Z || (N && !A) */
5392 c
->v1
= tcg_temp_new();
5394 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5395 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5396 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5397 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_Z
| FPSR_CC_N
);
5398 c
->tcond
= TCG_COND_NE
;
5400 case 6: /* Ordered Greater or Less than !(A || Z) */
5401 case 22: /* Greater or Less than !(A || Z) */
5402 c
->v1
= tcg_temp_new();
5404 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5405 c
->tcond
= TCG_COND_EQ
;
5407 case 7: /* Ordered !A */
5408 case 23: /* Greater, Less or Equal !A */
5409 c
->v1
= tcg_temp_new();
5411 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5412 c
->tcond
= TCG_COND_EQ
;
5414 case 8: /* Unordered A */
5415 case 24: /* Not Greater, Less or Equal A */
5416 c
->v1
= tcg_temp_new();
5418 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5419 c
->tcond
= TCG_COND_NE
;
5421 case 9: /* Unordered or Equal A || Z */
5422 case 25: /* Not Greater or Less then A || Z */
5423 c
->v1
= tcg_temp_new();
5425 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5426 c
->tcond
= TCG_COND_NE
;
5428 case 10: /* Unordered or Greater Than A || !(N || Z)) */
5429 case 26: /* Not Less or Equal A || !(N || Z)) */
5430 c
->v1
= tcg_temp_new();
5432 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5433 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5434 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_A
| FPSR_CC_N
);
5435 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5436 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5437 c
->tcond
= TCG_COND_NE
;
5439 case 11: /* Unordered or Greater or Equal A || Z || !N */
5440 case 27: /* Not Less Than A || Z || !N */
5441 c
->v1
= tcg_temp_new();
5443 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5444 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5445 c
->tcond
= TCG_COND_NE
;
5447 case 12: /* Unordered or Less Than A || (N && !Z) */
5448 case 28: /* Not Greater than or Equal A || (N && !Z) */
5449 c
->v1
= tcg_temp_new();
5451 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5452 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5453 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5454 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_A
| FPSR_CC_N
);
5455 c
->tcond
= TCG_COND_NE
;
5457 case 13: /* Unordered or Less or Equal A || Z || N */
5458 case 29: /* Not Greater Than A || Z || N */
5459 c
->v1
= tcg_temp_new();
5461 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5462 c
->tcond
= TCG_COND_NE
;
5464 case 14: /* Not Equal !Z */
5465 case 30: /* Signaling Not Equal !Z */
5466 c
->v1
= tcg_temp_new();
5468 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5469 c
->tcond
= TCG_COND_EQ
;
5472 case 31: /* Signaling True */
5474 c
->tcond
= TCG_COND_ALWAYS
;
5477 tcg_temp_free(fpsr
);
5480 static void gen_fjmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
5484 gen_fcc_cond(&c
, s
, cond
);
5486 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
5497 offset
= (int16_t)read_im16(env
, s
);
5498 if (insn
& (1 << 6)) {
5499 offset
= (offset
<< 16) | read_im16(env
, s
);
5502 l1
= gen_new_label();
5504 gen_fjmpcc(s
, insn
& 0x3f, l1
);
5505 gen_jmp_tb(s
, 0, s
->pc
, s
->base
.pc_next
);
5507 gen_jmp_tb(s
, 1, base
+ offset
, s
->base
.pc_next
);
5517 ext
= read_im16(env
, s
);
5519 gen_fcc_cond(&c
, s
, cond
);
5521 tmp
= tcg_temp_new();
5522 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
5525 tcg_gen_neg_i32(tmp
, tmp
);
5526 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
5530 #if defined(CONFIG_SOFTMMU)
5531 DISAS_INSN(frestore
)
5536 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
5539 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5540 SRC_EA(env
, addr
, OS_LONG
, 0, NULL
);
5541 /* FIXME: check the state frame */
5543 disas_undef(env
, s
, insn
);
5550 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
5554 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5555 /* always write IDLE */
5556 TCGv idle
= tcg_const_i32(0x41000000);
5557 DEST_EA(env
, insn
, OS_LONG
, idle
, NULL
);
5558 tcg_temp_free(idle
);
5560 disas_undef(env
, s
, insn
);
5565 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
5567 TCGv tmp
= tcg_temp_new();
5568 if (s
->env
->macsr
& MACSR_FI
) {
5570 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
5572 tcg_gen_shli_i32(tmp
, val
, 16);
5573 } else if (s
->env
->macsr
& MACSR_SU
) {
5575 tcg_gen_sari_i32(tmp
, val
, 16);
5577 tcg_gen_ext16s_i32(tmp
, val
);
5580 tcg_gen_shri_i32(tmp
, val
, 16);
5582 tcg_gen_ext16u_i32(tmp
, val
);
5587 static void gen_mac_clear_flags(void)
5589 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
5590 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
5606 s
->mactmp
= tcg_temp_new_i64();
5610 ext
= read_im16(env
, s
);
5612 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
5613 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
5614 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
5615 disas_undef(env
, s
, insn
);
5619 /* MAC with load. */
5620 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
5621 addr
= tcg_temp_new();
5622 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
5624 * Load the value now to ensure correct exception behavior.
5625 * Perform writeback after reading the MAC inputs.
5627 loadval
= gen_load(s
, OS_LONG
, addr
, 0, IS_USER(s
));
5630 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
5631 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
5633 loadval
= addr
= NULL_QREG
;
5634 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5635 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5638 gen_mac_clear_flags();
5641 /* Disabled because conditional branches clobber temporary vars. */
5642 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
5643 /* Skip the multiply if we know we will ignore it. */
5644 l1
= gen_new_label();
5645 tmp
= tcg_temp_new();
5646 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
5647 gen_op_jmp_nz32(tmp
, l1
);
5651 if ((ext
& 0x0800) == 0) {
5653 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
5654 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
5656 if (s
->env
->macsr
& MACSR_FI
) {
5657 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
5659 if (s
->env
->macsr
& MACSR_SU
)
5660 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
5662 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
5663 switch ((ext
>> 9) & 3) {
5665 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
5668 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
5674 /* Save the overflow flag from the multiply. */
5675 saved_flags
= tcg_temp_new();
5676 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
5678 saved_flags
= NULL_QREG
;
5682 /* Disabled because conditional branches clobber temporary vars. */
5683 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
5684 /* Skip the accumulate if the value is already saturated. */
5685 l1
= gen_new_label();
5686 tmp
= tcg_temp_new();
5687 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5688 gen_op_jmp_nz32(tmp
, l1
);
5693 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5695 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5697 if (s
->env
->macsr
& MACSR_FI
)
5698 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5699 else if (s
->env
->macsr
& MACSR_SU
)
5700 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5702 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5705 /* Disabled because conditional branches clobber temporary vars. */
5711 /* Dual accumulate variant. */
5712 acc
= (ext
>> 2) & 3;
5713 /* Restore the overflow flag from the multiplier. */
5714 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
5716 /* Disabled because conditional branches clobber temporary vars. */
5717 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
5718 /* Skip the accumulate if the value is already saturated. */
5719 l1
= gen_new_label();
5720 tmp
= tcg_temp_new();
5721 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5722 gen_op_jmp_nz32(tmp
, l1
);
5726 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5728 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5729 if (s
->env
->macsr
& MACSR_FI
)
5730 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5731 else if (s
->env
->macsr
& MACSR_SU
)
5732 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5734 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5736 /* Disabled because conditional branches clobber temporary vars. */
5741 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
5745 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5746 tcg_gen_mov_i32(rw
, loadval
);
5748 * FIXME: Should address writeback happen with the masked or
5751 switch ((insn
>> 3) & 7) {
5752 case 3: /* Post-increment. */
5753 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
5755 case 4: /* Pre-decrement. */
5756 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5758 tcg_temp_free(loadval
);
5762 DISAS_INSN(from_mac
)
5768 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5769 accnum
= (insn
>> 9) & 3;
5770 acc
= MACREG(accnum
);
5771 if (s
->env
->macsr
& MACSR_FI
) {
5772 gen_helper_get_macf(rx
, cpu_env
, acc
);
5773 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
5774 tcg_gen_extrl_i64_i32(rx
, acc
);
5775 } else if (s
->env
->macsr
& MACSR_SU
) {
5776 gen_helper_get_macs(rx
, acc
);
5778 gen_helper_get_macu(rx
, acc
);
5781 tcg_gen_movi_i64(acc
, 0);
5782 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5786 DISAS_INSN(move_mac
)
5788 /* FIXME: This can be done without a helper. */
5792 dest
= tcg_const_i32((insn
>> 9) & 3);
5793 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
5794 gen_mac_clear_flags();
5795 gen_helper_mac_set_flags(cpu_env
, dest
);
5798 DISAS_INSN(from_macsr
)
5802 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5803 tcg_gen_mov_i32(reg
, QREG_MACSR
);
5806 DISAS_INSN(from_mask
)
5809 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5810 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
5813 DISAS_INSN(from_mext
)
5817 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5818 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5819 if (s
->env
->macsr
& MACSR_FI
)
5820 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
5822 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
5825 DISAS_INSN(macsr_to_ccr
)
5827 TCGv tmp
= tcg_temp_new();
5828 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 0xf);
5829 gen_helper_set_sr(cpu_env
, tmp
);
5831 set_cc_op(s
, CC_OP_FLAGS
);
5839 accnum
= (insn
>> 9) & 3;
5840 acc
= MACREG(accnum
);
5841 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5842 if (s
->env
->macsr
& MACSR_FI
) {
5843 tcg_gen_ext_i32_i64(acc
, val
);
5844 tcg_gen_shli_i64(acc
, acc
, 8);
5845 } else if (s
->env
->macsr
& MACSR_SU
) {
5846 tcg_gen_ext_i32_i64(acc
, val
);
5848 tcg_gen_extu_i32_i64(acc
, val
);
5850 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5851 gen_mac_clear_flags();
5852 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
5855 DISAS_INSN(to_macsr
)
5858 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5859 gen_helper_set_macsr(cpu_env
, val
);
5866 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5867 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
5874 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5875 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5876 if (s
->env
->macsr
& MACSR_FI
)
5877 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
5878 else if (s
->env
->macsr
& MACSR_SU
)
5879 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
5881 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
5884 static disas_proc opcode_table
[65536];
5887 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
5893 /* Sanity check. All set bits must be included in the mask. */
5894 if (opcode
& ~mask
) {
5896 "qemu internal error: bogus opcode definition %04x/%04x\n",
5901 * This could probably be cleverer. For now just optimize the case where
5902 * the top bits are known.
5904 /* Find the first zero bit in the mask. */
5906 while ((i
& mask
) != 0)
5908 /* Iterate over all combinations of this and lower bits. */
5913 from
= opcode
& ~(i
- 1);
5915 for (i
= from
; i
< to
; i
++) {
5916 if ((i
& mask
) == opcode
)
5917 opcode_table
[i
] = proc
;
5922 * Register m68k opcode handlers. Order is important.
5923 * Later insn override earlier ones.
5925 void register_m68k_insns (CPUM68KState
*env
)
5928 * Build the opcode table only once to avoid
5929 * multithreading issues.
5931 if (opcode_table
[0] != NULL
) {
5936 * use BASE() for instruction available
5937 * for CF_ISA_A and M68000.
5939 #define BASE(name, opcode, mask) \
5940 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5941 #define INSN(name, opcode, mask, feature) do { \
5942 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5943 BASE(name, opcode, mask); \
5945 BASE(undef
, 0000, 0000);
5946 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
5947 INSN(arith_im
, 0000, ff00
, M68000
);
5948 INSN(chk2
, 00c0
, f9c0
, CHK2
);
5949 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
5950 BASE(bitop_reg
, 0100, f1c0
);
5951 BASE(bitop_reg
, 0140, f1c0
);
5952 BASE(bitop_reg
, 0180, f1c0
);
5953 BASE(bitop_reg
, 01c0
, f1c0
);
5954 INSN(movep
, 0108, f138
, MOVEP
);
5955 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
5956 INSN(arith_im
, 0200, ff00
, M68000
);
5957 INSN(undef
, 02c0
, ffc0
, M68000
);
5958 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
5959 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
5960 INSN(arith_im
, 0400, ff00
, M68000
);
5961 INSN(undef
, 04c0
, ffc0
, M68000
);
5962 INSN(arith_im
, 0600, ff00
, M68000
);
5963 INSN(undef
, 06c0
, ffc0
, M68000
);
5964 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
5965 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
5966 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
5967 INSN(arith_im
, 0c00
, ff00
, M68000
);
5968 BASE(bitop_im
, 0800, ffc0
);
5969 BASE(bitop_im
, 0840, ffc0
);
5970 BASE(bitop_im
, 0880, ffc0
);
5971 BASE(bitop_im
, 08c0
, ffc0
);
5972 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
5973 INSN(arith_im
, 0a00
, ff00
, M68000
);
5974 #if defined(CONFIG_SOFTMMU)
5975 INSN(moves
, 0e00
, ff00
, M68000
);
5977 INSN(cas
, 0ac0
, ffc0
, CAS
);
5978 INSN(cas
, 0cc0
, ffc0
, CAS
);
5979 INSN(cas
, 0ec0
, ffc0
, CAS
);
5980 INSN(cas2w
, 0cfc
, ffff
, CAS
);
5981 INSN(cas2l
, 0efc
, ffff
, CAS
);
5982 BASE(move
, 1000, f000
);
5983 BASE(move
, 2000, f000
);
5984 BASE(move
, 3000, f000
);
5985 INSN(chk
, 4000, f040
, M68000
);
5986 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
5987 INSN(negx
, 4080, fff8
, CF_ISA_A
);
5988 INSN(negx
, 4000, ff00
, M68000
);
5989 INSN(undef
, 40c0
, ffc0
, M68000
);
5990 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
5991 INSN(move_from_sr
, 40c0
, ffc0
, M68000
);
5992 BASE(lea
, 41c0
, f1c0
);
5993 BASE(clr
, 4200, ff00
);
5994 BASE(undef
, 42c0
, ffc0
);
5995 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
5996 INSN(move_from_ccr
, 42c0
, ffc0
, M68000
);
5997 INSN(neg
, 4480, fff8
, CF_ISA_A
);
5998 INSN(neg
, 4400, ff00
, M68000
);
5999 INSN(undef
, 44c0
, ffc0
, M68000
);
6000 BASE(move_to_ccr
, 44c0
, ffc0
);
6001 INSN(not, 4680, fff8
, CF_ISA_A
);
6002 INSN(not, 4600, ff00
, M68000
);
6003 #if defined(CONFIG_SOFTMMU)
6004 BASE(move_to_sr
, 46c0
, ffc0
);
6006 INSN(nbcd
, 4800, ffc0
, M68000
);
6007 INSN(linkl
, 4808, fff8
, M68000
);
6008 BASE(pea
, 4840, ffc0
);
6009 BASE(swap
, 4840, fff8
);
6010 INSN(bkpt
, 4848, fff8
, BKPT
);
6011 INSN(movem
, 48d0
, fbf8
, CF_ISA_A
);
6012 INSN(movem
, 48e8
, fbf8
, CF_ISA_A
);
6013 INSN(movem
, 4880, fb80
, M68000
);
6014 BASE(ext
, 4880, fff8
);
6015 BASE(ext
, 48c0
, fff8
);
6016 BASE(ext
, 49c0
, fff8
);
6017 BASE(tst
, 4a00
, ff00
);
6018 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
6019 INSN(tas
, 4ac0
, ffc0
, M68000
);
6020 #if defined(CONFIG_SOFTMMU)
6021 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
6022 INSN(halt
, 4ac8
, ffff
, M68060
);
6024 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
6025 BASE(illegal
, 4afc
, ffff
);
6026 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
6027 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
6028 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
6029 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
6030 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
6031 BASE(trap
, 4e40
, fff0
);
6032 BASE(link
, 4e50
, fff8
);
6033 BASE(unlk
, 4e58
, fff8
);
6034 #if defined(CONFIG_SOFTMMU)
6035 INSN(move_to_usp
, 4e60
, fff8
, USP
);
6036 INSN(move_from_usp
, 4e68
, fff8
, USP
);
6037 INSN(reset
, 4e70
, ffff
, M68000
);
6038 BASE(stop
, 4e72
, ffff
);
6039 BASE(rte
, 4e73
, ffff
);
6040 INSN(cf_movec
, 4e7b
, ffff
, CF_ISA_A
);
6041 INSN(m68k_movec
, 4e7a
, fffe
, MOVEC
);
6043 BASE(nop
, 4e71
, ffff
);
6044 INSN(rtd
, 4e74
, ffff
, RTD
);
6045 BASE(rts
, 4e75
, ffff
);
6046 INSN(rtr
, 4e77
, ffff
, M68000
);
6047 BASE(jump
, 4e80
, ffc0
);
6048 BASE(jump
, 4ec0
, ffc0
);
6049 INSN(addsubq
, 5000, f080
, M68000
);
6050 BASE(addsubq
, 5080, f0c0
);
6051 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
); /* Scc.B Dx */
6052 INSN(scc
, 50c0
, f0c0
, M68000
); /* Scc.B <EA> */
6053 INSN(dbcc
, 50c8
, f0f8
, M68000
);
6054 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
6056 /* Branch instructions. */
6057 BASE(branch
, 6000, f000
);
6058 /* Disable long branch instructions, then add back the ones we want. */
6059 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
6060 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
6061 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
6062 INSN(branch
, 60ff
, ffff
, BRAL
);
6063 INSN(branch
, 60ff
, f0ff
, BCCL
);
6065 BASE(moveq
, 7000, f100
);
6066 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
6067 BASE(or, 8000, f000
);
6068 BASE(divw
, 80c0
, f0c0
);
6069 INSN(sbcd_reg
, 8100, f1f8
, M68000
);
6070 INSN(sbcd_mem
, 8108, f1f8
, M68000
);
6071 BASE(addsub
, 9000, f000
);
6072 INSN(undef
, 90c0
, f0c0
, CF_ISA_A
);
6073 INSN(subx_reg
, 9180, f1f8
, CF_ISA_A
);
6074 INSN(subx_reg
, 9100, f138
, M68000
);
6075 INSN(subx_mem
, 9108, f138
, M68000
);
6076 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
6077 INSN(suba
, 90c0
, f0c0
, M68000
);
6079 BASE(undef_mac
, a000
, f000
);
6080 INSN(mac
, a000
, f100
, CF_EMAC
);
6081 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
6082 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
6083 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
6084 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
6085 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
6086 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
6087 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
6088 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
6089 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
6090 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
6092 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
6093 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
6094 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
6095 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
6096 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
6097 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
6098 INSN(cmp
, b000
, f100
, M68000
);
6099 INSN(eor
, b100
, f100
, M68000
);
6100 INSN(cmpm
, b108
, f138
, M68000
);
6101 INSN(cmpa
, b0c0
, f0c0
, M68000
);
6102 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
6103 BASE(and, c000
, f000
);
6104 INSN(exg_dd
, c140
, f1f8
, M68000
);
6105 INSN(exg_aa
, c148
, f1f8
, M68000
);
6106 INSN(exg_da
, c188
, f1f8
, M68000
);
6107 BASE(mulw
, c0c0
, f0c0
);
6108 INSN(abcd_reg
, c100
, f1f8
, M68000
);
6109 INSN(abcd_mem
, c108
, f1f8
, M68000
);
6110 BASE(addsub
, d000
, f000
);
6111 INSN(undef
, d0c0
, f0c0
, CF_ISA_A
);
6112 INSN(addx_reg
, d180
, f1f8
, CF_ISA_A
);
6113 INSN(addx_reg
, d100
, f138
, M68000
);
6114 INSN(addx_mem
, d108
, f138
, M68000
);
6115 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
6116 INSN(adda
, d0c0
, f0c0
, M68000
);
6117 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
6118 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
6119 INSN(shift8_im
, e000
, f0f0
, M68000
);
6120 INSN(shift16_im
, e040
, f0f0
, M68000
);
6121 INSN(shift_im
, e080
, f0f0
, M68000
);
6122 INSN(shift8_reg
, e020
, f0f0
, M68000
);
6123 INSN(shift16_reg
, e060
, f0f0
, M68000
);
6124 INSN(shift_reg
, e0a0
, f0f0
, M68000
);
6125 INSN(shift_mem
, e0c0
, fcc0
, M68000
);
6126 INSN(rotate_im
, e090
, f0f0
, M68000
);
6127 INSN(rotate8_im
, e010
, f0f0
, M68000
);
6128 INSN(rotate16_im
, e050
, f0f0
, M68000
);
6129 INSN(rotate_reg
, e0b0
, f0f0
, M68000
);
6130 INSN(rotate8_reg
, e030
, f0f0
, M68000
);
6131 INSN(rotate16_reg
, e070
, f0f0
, M68000
);
6132 INSN(rotate_mem
, e4c0
, fcc0
, M68000
);
6133 INSN(bfext_mem
, e9c0
, fdc0
, BITFIELD
); /* bfextu & bfexts */
6134 INSN(bfext_reg
, e9c0
, fdf8
, BITFIELD
);
6135 INSN(bfins_mem
, efc0
, ffc0
, BITFIELD
);
6136 INSN(bfins_reg
, efc0
, fff8
, BITFIELD
);
6137 INSN(bfop_mem
, eac0
, ffc0
, BITFIELD
); /* bfchg */
6138 INSN(bfop_reg
, eac0
, fff8
, BITFIELD
); /* bfchg */
6139 INSN(bfop_mem
, ecc0
, ffc0
, BITFIELD
); /* bfclr */
6140 INSN(bfop_reg
, ecc0
, fff8
, BITFIELD
); /* bfclr */
6141 INSN(bfop_mem
, edc0
, ffc0
, BITFIELD
); /* bfffo */
6142 INSN(bfop_reg
, edc0
, fff8
, BITFIELD
); /* bfffo */
6143 INSN(bfop_mem
, eec0
, ffc0
, BITFIELD
); /* bfset */
6144 INSN(bfop_reg
, eec0
, fff8
, BITFIELD
); /* bfset */
6145 INSN(bfop_mem
, e8c0
, ffc0
, BITFIELD
); /* bftst */
6146 INSN(bfop_reg
, e8c0
, fff8
, BITFIELD
); /* bftst */
6147 BASE(undef_fpu
, f000
, f000
);
6148 INSN(fpu
, f200
, ffc0
, CF_FPU
);
6149 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
6150 INSN(fpu
, f200
, ffc0
, FPU
);
6151 INSN(fscc
, f240
, ffc0
, FPU
);
6152 INSN(fbcc
, f280
, ff80
, FPU
);
6153 #if defined(CONFIG_SOFTMMU)
6154 INSN(frestore
, f340
, ffc0
, CF_FPU
);
6155 INSN(fsave
, f300
, ffc0
, CF_FPU
);
6156 INSN(frestore
, f340
, ffc0
, FPU
);
6157 INSN(fsave
, f300
, ffc0
, FPU
);
6158 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
6159 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
6160 INSN(cpush
, f420
, ff20
, M68040
);
6161 INSN(cinv
, f400
, ff20
, M68040
);
6162 INSN(pflush
, f500
, ffe0
, M68040
);
6163 INSN(ptest
, f548
, ffd8
, M68040
);
6164 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
6165 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
6167 INSN(move16_mem
, f600
, ffe0
, M68040
);
6168 INSN(move16_reg
, f620
, fff8
, M68040
);
6172 static void m68k_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cpu
)
6174 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6175 CPUM68KState
*env
= cpu
->env_ptr
;
6178 dc
->pc
= dc
->base
.pc_first
;
6179 /* This value will always be filled in properly before m68k_tr_tb_stop. */
6180 dc
->pc_prev
= 0xdeadbeef;
6181 dc
->cc_op
= CC_OP_DYNAMIC
;
6182 dc
->cc_op_synced
= 1;
6184 dc
->writeback_mask
= 0;
6185 init_release_array(dc
);
6187 dc
->ss_active
= (M68K_SR_TRACE(env
->sr
) == M68K_SR_TRACE_ANY_INS
);
6188 /* If architectural single step active, limit to 1 */
6189 if (dc
->ss_active
) {
6190 dc
->base
.max_insns
= 1;
6194 static void m68k_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
6198 static void m68k_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
6200 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6201 tcg_gen_insn_start(dc
->base
.pc_next
, dc
->cc_op
);
6204 static void m68k_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
6206 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6207 CPUM68KState
*env
= cpu
->env_ptr
;
6208 uint16_t insn
= read_im16(env
, dc
);
6210 opcode_table
[insn
](env
, dc
, insn
);
6214 dc
->pc_prev
= dc
->base
.pc_next
;
6215 dc
->base
.pc_next
= dc
->pc
;
6217 if (dc
->base
.is_jmp
== DISAS_NEXT
) {
6219 * Stop translation when the next insn might touch a new page.
6220 * This ensures that prefetch aborts at the right place.
6222 * We cannot determine the size of the next insn without
6223 * completely decoding it. However, the maximum insn size
6224 * is 32 bytes, so end if we do not have that much remaining.
6225 * This may produce several small TBs at the end of each page,
6226 * but they will all be linked with goto_tb.
6228 * ??? ColdFire maximum is 4 bytes; MC68000's maximum is also
6229 * smaller than MC68020's.
6231 target_ulong start_page_offset
6232 = dc
->pc
- (dc
->base
.pc_first
& TARGET_PAGE_MASK
);
6234 if (start_page_offset
>= TARGET_PAGE_SIZE
- 32) {
6235 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
6240 static void m68k_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
6242 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6244 switch (dc
->base
.is_jmp
) {
6245 case DISAS_NORETURN
:
6247 case DISAS_TOO_MANY
:
6249 gen_jmp_tb(dc
, 0, dc
->pc
, dc
->pc_prev
);
6252 /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
6253 if (dc
->ss_active
) {
6254 gen_raise_exception_format2(dc
, EXCP_TRACE
, dc
->pc_prev
);
6256 tcg_gen_lookup_and_goto_ptr();
6261 * We updated CC_OP and PC in gen_exit_tb, but also modified
6262 * other state that may require returning to the main loop.
6264 if (dc
->ss_active
) {
6265 gen_raise_exception_format2(dc
, EXCP_TRACE
, dc
->pc_prev
);
6267 tcg_gen_exit_tb(NULL
, 0);
6271 g_assert_not_reached();
6275 static void m68k_tr_disas_log(const DisasContextBase
*dcbase
,
6276 CPUState
*cpu
, FILE *logfile
)
6278 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
6279 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
6282 static const TranslatorOps m68k_tr_ops
= {
6283 .init_disas_context
= m68k_tr_init_disas_context
,
6284 .tb_start
= m68k_tr_tb_start
,
6285 .insn_start
= m68k_tr_insn_start
,
6286 .translate_insn
= m68k_tr_translate_insn
,
6287 .tb_stop
= m68k_tr_tb_stop
,
6288 .disas_log
= m68k_tr_disas_log
,
6291 void gen_intermediate_code(CPUState
*cpu
, TranslationBlock
*tb
, int max_insns
)
6294 translator_loop(&m68k_tr_ops
, &dc
.base
, cpu
, tb
, max_insns
);
6297 static double floatx80_to_double(CPUM68KState
*env
, uint16_t high
, uint64_t low
)
6299 floatx80 a
= { .high
= high
, .low
= low
};
6305 u
.f64
= floatx80_to_float64(a
, &env
->fp_status
);
6309 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
6311 M68kCPU
*cpu
= M68K_CPU(cs
);
6312 CPUM68KState
*env
= &cpu
->env
;
6315 for (i
= 0; i
< 8; i
++) {
6316 qemu_fprintf(f
, "D%d = %08x A%d = %08x "
6317 "F%d = %04x %016"PRIx64
" (%12g)\n",
6318 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
6319 i
, env
->fregs
[i
].l
.upper
, env
->fregs
[i
].l
.lower
,
6320 floatx80_to_double(env
, env
->fregs
[i
].l
.upper
,
6321 env
->fregs
[i
].l
.lower
));
6323 qemu_fprintf(f
, "PC = %08x ", env
->pc
);
6324 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
6325 qemu_fprintf(f
, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",
6326 sr
, (sr
& SR_T
) >> SR_T_SHIFT
, (sr
& SR_I
) >> SR_I_SHIFT
,
6327 (sr
& SR_S
) ? 'S' : 'U', (sr
& SR_M
) ? '%' : 'I',
6328 (sr
& CCF_X
) ? 'X' : '-', (sr
& CCF_N
) ? 'N' : '-',
6329 (sr
& CCF_Z
) ? 'Z' : '-', (sr
& CCF_V
) ? 'V' : '-',
6330 (sr
& CCF_C
) ? 'C' : '-');
6331 qemu_fprintf(f
, "FPSR = %08x %c%c%c%c ", env
->fpsr
,
6332 (env
->fpsr
& FPSR_CC_A
) ? 'A' : '-',
6333 (env
->fpsr
& FPSR_CC_I
) ? 'I' : '-',
6334 (env
->fpsr
& FPSR_CC_Z
) ? 'Z' : '-',
6335 (env
->fpsr
& FPSR_CC_N
) ? 'N' : '-');
6336 qemu_fprintf(f
, "\n "
6337 "FPCR = %04x ", env
->fpcr
);
6338 switch (env
->fpcr
& FPCR_PREC_MASK
) {
6340 qemu_fprintf(f
, "X ");
6343 qemu_fprintf(f
, "S ");
6346 qemu_fprintf(f
, "D ");
6349 switch (env
->fpcr
& FPCR_RND_MASK
) {
6351 qemu_fprintf(f
, "RN ");
6354 qemu_fprintf(f
, "RZ ");
6357 qemu_fprintf(f
, "RM ");
6360 qemu_fprintf(f
, "RP ");
6363 qemu_fprintf(f
, "\n");
6364 #ifdef CONFIG_SOFTMMU
6365 qemu_fprintf(f
, "%sA7(MSP) = %08x %sA7(USP) = %08x %sA7(ISP) = %08x\n",
6366 env
->current_sp
== M68K_SSP
? "->" : " ", env
->sp
[M68K_SSP
],
6367 env
->current_sp
== M68K_USP
? "->" : " ", env
->sp
[M68K_USP
],
6368 env
->current_sp
== M68K_ISP
? "->" : " ", env
->sp
[M68K_ISP
]);
6369 qemu_fprintf(f
, "VBR = 0x%08x\n", env
->vbr
);
6370 qemu_fprintf(f
, "SFC = %x DFC %x\n", env
->sfc
, env
->dfc
);
6371 qemu_fprintf(f
, "SSW %08x TCR %08x URP %08x SRP %08x\n",
6372 env
->mmu
.ssw
, env
->mmu
.tcr
, env
->mmu
.urp
, env
->mmu
.srp
);
6373 qemu_fprintf(f
, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n",
6374 env
->mmu
.ttr
[M68K_DTTR0
], env
->mmu
.ttr
[M68K_DTTR1
],
6375 env
->mmu
.ttr
[M68K_ITTR0
], env
->mmu
.ttr
[M68K_ITTR1
]);
6376 qemu_fprintf(f
, "MMUSR %08x, fault at %08x\n",
6377 env
->mmu
.mmusr
, env
->mmu
.ar
);
6381 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,
6384 int cc_op
= data
[1];
6386 if (cc_op
!= CC_OP_DYNAMIC
) {