4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
27 #include "qemu/qemu-print.h"
28 #include "exec/cpu_ldst.h"
29 #include "exec/translator.h"
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
35 #include "fpu/softfloat.h"
38 //#define DEBUG_DISPATCH 1
40 #define DEFO32(name, offset) static TCGv QREG_##name;
41 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
42 #include "qregs.h.inc"
46 static TCGv_i32 cpu_halted
;
47 static TCGv_i32 cpu_exception_index
;
49 static char cpu_reg_names
[2 * 8 * 3 + 5 * 4];
50 static TCGv cpu_dregs
[8];
51 static TCGv cpu_aregs
[8];
52 static TCGv_i64 cpu_macc
[4];
54 #define REG(insn, pos) (((insn) >> (pos)) & 7)
55 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
56 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
57 #define MACREG(acc) cpu_macc[acc]
58 #define QREG_SP get_areg(s, 7)
60 static TCGv NULL_QREG
;
61 #define IS_NULL_QREG(t) (t == NULL_QREG)
62 /* Used to distinguish stores from bad addressing modes. */
63 static TCGv store_dummy
;
65 #include "exec/gen-icount.h"
67 void m68k_tcg_init(void)
72 #define DEFO32(name, offset) \
73 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
74 offsetof(CPUM68KState, offset), #name);
75 #define DEFO64(name, offset) \
76 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
77 offsetof(CPUM68KState, offset), #name);
78 #include "qregs.h.inc"
82 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
83 -offsetof(M68kCPU
, env
) +
84 offsetof(CPUState
, halted
), "HALTED");
85 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
86 -offsetof(M68kCPU
, env
) +
87 offsetof(CPUState
, exception_index
),
91 for (i
= 0; i
< 8; i
++) {
93 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
94 offsetof(CPUM68KState
, dregs
[i
]), p
);
97 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
98 offsetof(CPUM68KState
, aregs
[i
]), p
);
101 for (i
= 0; i
< 4; i
++) {
102 sprintf(p
, "ACC%d", i
);
103 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
104 offsetof(CPUM68KState
, macc
[i
]), p
);
108 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
109 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
112 /* internal defines */
113 typedef struct DisasContext
{
114 DisasContextBase base
;
117 target_ulong pc_prev
;
118 CCOp cc_op
; /* Current CC operation */
127 static TCGv
get_areg(DisasContext
*s
, unsigned regno
)
129 if (s
->writeback_mask
& (1 << regno
)) {
130 return s
->writeback
[regno
];
132 return cpu_aregs
[regno
];
136 static void delay_set_areg(DisasContext
*s
, unsigned regno
,
137 TCGv val
, bool give_temp
)
139 if (s
->writeback_mask
& (1 << regno
)) {
141 tcg_temp_free(s
->writeback
[regno
]);
142 s
->writeback
[regno
] = val
;
144 tcg_gen_mov_i32(s
->writeback
[regno
], val
);
147 s
->writeback_mask
|= 1 << regno
;
149 s
->writeback
[regno
] = val
;
151 TCGv tmp
= tcg_temp_new();
152 s
->writeback
[regno
] = tmp
;
153 tcg_gen_mov_i32(tmp
, val
);
158 static void do_writebacks(DisasContext
*s
)
160 unsigned mask
= s
->writeback_mask
;
162 s
->writeback_mask
= 0;
164 unsigned regno
= ctz32(mask
);
165 tcg_gen_mov_i32(cpu_aregs
[regno
], s
->writeback
[regno
]);
166 tcg_temp_free(s
->writeback
[regno
]);
172 /* is_jmp field values */
173 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
174 #define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
176 #if defined(CONFIG_USER_ONLY)
179 #define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S))
180 #define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \
181 MMU_KERNEL_IDX : MMU_USER_IDX)
182 #define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \
183 MMU_KERNEL_IDX : MMU_USER_IDX)
186 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
188 #ifdef DEBUG_DISPATCH
189 #define DISAS_INSN(name) \
190 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
192 static void disas_##name(CPUM68KState *env, DisasContext *s, \
195 qemu_log("Dispatch " #name "\n"); \
196 real_disas_##name(env, s, insn); \
198 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
201 #define DISAS_INSN(name) \
202 static void disas_##name(CPUM68KState *env, DisasContext *s, \
206 static const uint8_t cc_op_live
[CC_OP_NB
] = {
207 [CC_OP_DYNAMIC
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
208 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
209 [CC_OP_ADDB
... CC_OP_ADDL
] = CCF_X
| CCF_N
| CCF_V
,
210 [CC_OP_SUBB
... CC_OP_SUBL
] = CCF_X
| CCF_N
| CCF_V
,
211 [CC_OP_CMPB
... CC_OP_CMPL
] = CCF_X
| CCF_N
| CCF_V
,
212 [CC_OP_LOGIC
] = CCF_X
| CCF_N
215 static void set_cc_op(DisasContext
*s
, CCOp op
)
217 CCOp old_op
= s
->cc_op
;
227 * Discard CC computation that will no longer be used.
228 * Note that X and N are never dead.
230 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
232 tcg_gen_discard_i32(QREG_CC_C
);
235 tcg_gen_discard_i32(QREG_CC_Z
);
238 tcg_gen_discard_i32(QREG_CC_V
);
242 /* Update the CPU env CC_OP state. */
243 static void update_cc_op(DisasContext
*s
)
245 if (!s
->cc_op_synced
) {
247 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
251 /* Generate a jump to an immediate address. */
252 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
255 tcg_gen_movi_i32(QREG_PC
, dest
);
256 s
->base
.is_jmp
= DISAS_JUMP
;
259 /* Generate a jump to the address in qreg DEST. */
260 static void gen_jmp(DisasContext
*s
, TCGv dest
)
263 tcg_gen_mov_i32(QREG_PC
, dest
);
264 s
->base
.is_jmp
= DISAS_JUMP
;
267 static void gen_raise_exception(int nr
)
271 tmp
= tcg_const_i32(nr
);
272 gen_helper_raise_exception(cpu_env
, tmp
);
273 tcg_temp_free_i32(tmp
);
276 static void gen_raise_exception_format2(DisasContext
*s
, int nr
,
277 target_ulong this_pc
)
280 * Pass the address of the insn to the exception handler,
281 * for recording in the Format $2 (6-word) stack frame.
282 * Re-use mmu.ar for the purpose, since that's only valid
285 tcg_gen_st_i32(tcg_constant_i32(this_pc
), cpu_env
,
286 offsetof(CPUM68KState
, mmu
.ar
));
287 gen_raise_exception(nr
);
288 s
->base
.is_jmp
= DISAS_NORETURN
;
291 static void gen_exception(DisasContext
*s
, uint32_t dest
, int nr
)
294 tcg_gen_movi_i32(QREG_PC
, dest
);
296 gen_raise_exception(nr
);
298 s
->base
.is_jmp
= DISAS_NORETURN
;
301 static inline void gen_addr_fault(DisasContext
*s
)
303 gen_exception(s
, s
->base
.pc_next
, EXCP_ADDRESS
);
307 * Generate a load from the specified address. Narrow values are
308 * sign extended to full register width.
310 static inline TCGv
gen_load(DisasContext
*s
, int opsize
, TCGv addr
,
314 tmp
= tcg_temp_new_i32();
318 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
320 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
324 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
326 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
329 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
332 g_assert_not_reached();
337 /* Generate a store. */
338 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
343 tcg_gen_qemu_st8(val
, addr
, index
);
346 tcg_gen_qemu_st16(val
, addr
, index
);
349 tcg_gen_qemu_st32(val
, addr
, index
);
352 g_assert_not_reached();
363 * Generate an unsigned load if VAL is 0 a signed load if val is -1,
364 * otherwise generate a store.
366 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
367 ea_what what
, int index
)
369 if (what
== EA_STORE
) {
370 gen_store(s
, opsize
, addr
, val
, index
);
373 return gen_load(s
, opsize
, addr
, what
== EA_LOADS
, index
);
377 /* Read a 16-bit immediate constant */
378 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
381 im
= translator_lduw(env
, &s
->base
, s
->pc
);
386 /* Read an 8-bit immediate constant */
387 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
389 return read_im16(env
, s
);
392 /* Read a 32-bit immediate constant. */
393 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
396 im
= read_im16(env
, s
) << 16;
397 im
|= 0xffff & read_im16(env
, s
);
401 /* Read a 64-bit immediate constant. */
402 static inline uint64_t read_im64(CPUM68KState
*env
, DisasContext
*s
)
405 im
= (uint64_t)read_im32(env
, s
) << 32;
406 im
|= (uint64_t)read_im32(env
, s
);
410 /* Calculate and address index. */
411 static TCGv
gen_addr_index(DisasContext
*s
, uint16_t ext
, TCGv tmp
)
416 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
417 if ((ext
& 0x800) == 0) {
418 tcg_gen_ext16s_i32(tmp
, add
);
421 scale
= (ext
>> 9) & 3;
423 tcg_gen_shli_i32(tmp
, add
, scale
);
430 * Handle a base + index + displacement effective address.
431 * A NULL_QREG base means pc-relative.
433 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
442 ext
= read_im16(env
, s
);
444 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
447 if (m68k_feature(s
->env
, M68K_FEATURE_M68K
) &&
448 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
453 /* full extension word format */
454 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
457 if ((ext
& 0x30) > 0x10) {
458 /* base displacement */
459 if ((ext
& 0x30) == 0x20) {
460 bd
= (int16_t)read_im16(env
, s
);
462 bd
= read_im32(env
, s
);
467 tmp
= tcg_temp_new();
468 if ((ext
& 0x44) == 0) {
470 add
= gen_addr_index(s
, ext
, tmp
);
474 if ((ext
& 0x80) == 0) {
475 /* base not suppressed */
476 if (IS_NULL_QREG(base
)) {
477 base
= tcg_const_i32(offset
+ bd
);
480 if (!IS_NULL_QREG(add
)) {
481 tcg_gen_add_i32(tmp
, add
, base
);
487 if (!IS_NULL_QREG(add
)) {
489 tcg_gen_addi_i32(tmp
, add
, bd
);
493 add
= tcg_const_i32(bd
);
495 if ((ext
& 3) != 0) {
496 /* memory indirect */
497 base
= gen_load(s
, OS_LONG
, add
, 0, IS_USER(s
));
498 if ((ext
& 0x44) == 4) {
499 add
= gen_addr_index(s
, ext
, tmp
);
500 tcg_gen_add_i32(tmp
, add
, base
);
506 /* outer displacement */
507 if ((ext
& 3) == 2) {
508 od
= (int16_t)read_im16(env
, s
);
510 od
= read_im32(env
, s
);
516 tcg_gen_addi_i32(tmp
, add
, od
);
521 /* brief extension word format */
522 tmp
= tcg_temp_new();
523 add
= gen_addr_index(s
, ext
, tmp
);
524 if (!IS_NULL_QREG(base
)) {
525 tcg_gen_add_i32(tmp
, add
, base
);
527 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
529 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
536 /* Sign or zero extend a value. */
538 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
543 tcg_gen_ext8s_i32(res
, val
);
545 tcg_gen_ext8u_i32(res
, val
);
550 tcg_gen_ext16s_i32(res
, val
);
552 tcg_gen_ext16u_i32(res
, val
);
556 tcg_gen_mov_i32(res
, val
);
559 g_assert_not_reached();
563 /* Evaluate all the CC flags. */
565 static void gen_flush_flags(DisasContext
*s
)
576 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
577 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
578 /* Compute signed overflow for addition. */
581 tcg_gen_sub_i32(t0
, QREG_CC_N
, QREG_CC_V
);
582 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_ADDB
, 1);
583 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
584 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
586 tcg_gen_andc_i32(QREG_CC_V
, t1
, QREG_CC_V
);
593 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
594 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
595 /* Compute signed overflow for subtraction. */
598 tcg_gen_add_i32(t0
, QREG_CC_N
, QREG_CC_V
);
599 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_SUBB
, 1);
600 tcg_gen_xor_i32(t1
, QREG_CC_N
, t0
);
601 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
603 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t1
);
610 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_C
, QREG_CC_N
, QREG_CC_V
);
611 tcg_gen_sub_i32(QREG_CC_Z
, QREG_CC_N
, QREG_CC_V
);
612 gen_ext(QREG_CC_Z
, QREG_CC_Z
, s
->cc_op
- CC_OP_CMPB
, 1);
613 /* Compute signed overflow for subtraction. */
615 tcg_gen_xor_i32(t0
, QREG_CC_Z
, QREG_CC_N
);
616 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, QREG_CC_N
);
617 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t0
);
619 tcg_gen_mov_i32(QREG_CC_N
, QREG_CC_Z
);
623 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
624 tcg_gen_movi_i32(QREG_CC_C
, 0);
625 tcg_gen_movi_i32(QREG_CC_V
, 0);
629 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
634 t0
= tcg_const_i32(s
->cc_op
);
635 gen_helper_flush_flags(cpu_env
, t0
);
641 /* Note that flush_flags also assigned to env->cc_op. */
642 s
->cc_op
= CC_OP_FLAGS
;
645 static inline TCGv
gen_extend(DisasContext
*s
, TCGv val
, int opsize
, int sign
)
649 if (opsize
== OS_LONG
) {
652 tmp
= tcg_temp_new();
653 gen_ext(tmp
, val
, opsize
, sign
);
659 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
661 gen_ext(QREG_CC_N
, val
, opsize
, 1);
662 set_cc_op(s
, CC_OP_LOGIC
);
665 static void gen_update_cc_cmp(DisasContext
*s
, TCGv dest
, TCGv src
, int opsize
)
667 tcg_gen_mov_i32(QREG_CC_N
, dest
);
668 tcg_gen_mov_i32(QREG_CC_V
, src
);
669 set_cc_op(s
, CC_OP_CMPB
+ opsize
);
672 static void gen_update_cc_add(TCGv dest
, TCGv src
, int opsize
)
674 gen_ext(QREG_CC_N
, dest
, opsize
, 1);
675 tcg_gen_mov_i32(QREG_CC_V
, src
);
678 static inline int opsize_bytes(int opsize
)
681 case OS_BYTE
: return 1;
682 case OS_WORD
: return 2;
683 case OS_LONG
: return 4;
684 case OS_SINGLE
: return 4;
685 case OS_DOUBLE
: return 8;
686 case OS_EXTENDED
: return 12;
687 case OS_PACKED
: return 12;
689 g_assert_not_reached();
693 static inline int insn_opsize(int insn
)
695 switch ((insn
>> 6) & 3) {
696 case 0: return OS_BYTE
;
697 case 1: return OS_WORD
;
698 case 2: return OS_LONG
;
700 g_assert_not_reached();
704 static inline int ext_opsize(int ext
, int pos
)
706 switch ((ext
>> pos
) & 7) {
707 case 0: return OS_LONG
;
708 case 1: return OS_SINGLE
;
709 case 2: return OS_EXTENDED
;
710 case 3: return OS_PACKED
;
711 case 4: return OS_WORD
;
712 case 5: return OS_DOUBLE
;
713 case 6: return OS_BYTE
;
715 g_assert_not_reached();
720 * Assign value to a register. If the width is less than the register width
721 * only the low part of the register is set.
723 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
728 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
729 tmp
= tcg_temp_new();
730 tcg_gen_ext8u_i32(tmp
, val
);
731 tcg_gen_or_i32(reg
, reg
, tmp
);
735 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
736 tmp
= tcg_temp_new();
737 tcg_gen_ext16u_i32(tmp
, val
);
738 tcg_gen_or_i32(reg
, reg
, tmp
);
743 tcg_gen_mov_i32(reg
, val
);
746 g_assert_not_reached();
751 * Generate code for an "effective address". Does not adjust the base
752 * register for autoincrement addressing modes.
754 static TCGv
gen_lea_mode(CPUM68KState
*env
, DisasContext
*s
,
755 int mode
, int reg0
, int opsize
)
763 case 0: /* Data register direct. */
764 case 1: /* Address register direct. */
766 case 3: /* Indirect postincrement. */
767 if (opsize
== OS_UNSIZED
) {
771 case 2: /* Indirect register */
772 return get_areg(s
, reg0
);
773 case 4: /* Indirect predecrememnt. */
774 if (opsize
== OS_UNSIZED
) {
777 reg
= get_areg(s
, reg0
);
778 tmp
= tcg_temp_new();
779 if (reg0
== 7 && opsize
== OS_BYTE
&&
780 m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
781 tcg_gen_subi_i32(tmp
, reg
, 2);
783 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
786 case 5: /* Indirect displacement. */
787 reg
= get_areg(s
, reg0
);
788 tmp
= tcg_temp_new();
789 ext
= read_im16(env
, s
);
790 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
792 case 6: /* Indirect index + displacement. */
793 reg
= get_areg(s
, reg0
);
794 return gen_lea_indexed(env
, s
, reg
);
797 case 0: /* Absolute short. */
798 offset
= (int16_t)read_im16(env
, s
);
799 return tcg_const_i32(offset
);
800 case 1: /* Absolute long. */
801 offset
= read_im32(env
, s
);
802 return tcg_const_i32(offset
);
803 case 2: /* pc displacement */
805 offset
+= (int16_t)read_im16(env
, s
);
806 return tcg_const_i32(offset
);
807 case 3: /* pc index+displacement. */
808 return gen_lea_indexed(env
, s
, NULL_QREG
);
809 case 4: /* Immediate. */
814 /* Should never happen. */
818 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
821 int mode
= extract32(insn
, 3, 3);
822 int reg0
= REG(insn
, 0);
823 return gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
827 * Generate code to load/store a value from/into an EA. If WHAT > 0 this is
828 * a write otherwise it is a read (0 == sign extend, -1 == zero extend).
829 * ADDRP is non-null for readwrite operands.
831 static TCGv
gen_ea_mode(CPUM68KState
*env
, DisasContext
*s
, int mode
, int reg0
,
832 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
,
835 TCGv reg
, tmp
, result
;
839 case 0: /* Data register direct. */
840 reg
= cpu_dregs
[reg0
];
841 if (what
== EA_STORE
) {
842 gen_partset_reg(opsize
, reg
, val
);
845 return gen_extend(s
, reg
, opsize
, what
== EA_LOADS
);
847 case 1: /* Address register direct. */
848 reg
= get_areg(s
, reg0
);
849 if (what
== EA_STORE
) {
850 tcg_gen_mov_i32(reg
, val
);
853 return gen_extend(s
, reg
, opsize
, what
== EA_LOADS
);
855 case 2: /* Indirect register */
856 reg
= get_areg(s
, reg0
);
857 return gen_ldst(s
, opsize
, reg
, val
, what
, index
);
858 case 3: /* Indirect postincrement. */
859 reg
= get_areg(s
, reg0
);
860 result
= gen_ldst(s
, opsize
, reg
, val
, what
, index
);
861 if (what
== EA_STORE
|| !addrp
) {
862 TCGv tmp
= tcg_temp_new();
863 if (reg0
== 7 && opsize
== OS_BYTE
&&
864 m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
865 tcg_gen_addi_i32(tmp
, reg
, 2);
867 tcg_gen_addi_i32(tmp
, reg
, opsize_bytes(opsize
));
869 delay_set_areg(s
, reg0
, tmp
, true);
872 case 4: /* Indirect predecrememnt. */
873 if (addrp
&& what
== EA_STORE
) {
876 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
877 if (IS_NULL_QREG(tmp
)) {
884 result
= gen_ldst(s
, opsize
, tmp
, val
, what
, index
);
885 if (what
== EA_STORE
|| !addrp
) {
886 delay_set_areg(s
, reg0
, tmp
, false);
889 case 5: /* Indirect displacement. */
890 case 6: /* Indirect index + displacement. */
892 if (addrp
&& what
== EA_STORE
) {
895 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
896 if (IS_NULL_QREG(tmp
)) {
903 return gen_ldst(s
, opsize
, tmp
, val
, what
, index
);
906 case 0: /* Absolute short. */
907 case 1: /* Absolute long. */
908 case 2: /* pc displacement */
909 case 3: /* pc index+displacement. */
911 case 4: /* Immediate. */
912 /* Sign extend values for consistency. */
915 if (what
== EA_LOADS
) {
916 offset
= (int8_t)read_im8(env
, s
);
918 offset
= read_im8(env
, s
);
922 if (what
== EA_LOADS
) {
923 offset
= (int16_t)read_im16(env
, s
);
925 offset
= read_im16(env
, s
);
929 offset
= read_im32(env
, s
);
932 g_assert_not_reached();
934 return tcg_const_i32(offset
);
939 /* Should never happen. */
943 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
944 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
, int index
)
946 int mode
= extract32(insn
, 3, 3);
947 int reg0
= REG(insn
, 0);
948 return gen_ea_mode(env
, s
, mode
, reg0
, opsize
, val
, addrp
, what
, index
);
951 static TCGv_ptr
gen_fp_ptr(int freg
)
953 TCGv_ptr fp
= tcg_temp_new_ptr();
954 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fregs
[freg
]));
958 static TCGv_ptr
gen_fp_result_ptr(void)
960 TCGv_ptr fp
= tcg_temp_new_ptr();
961 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fp_result
));
965 static void gen_fp_move(TCGv_ptr dest
, TCGv_ptr src
)
970 t32
= tcg_temp_new();
971 tcg_gen_ld16u_i32(t32
, src
, offsetof(FPReg
, l
.upper
));
972 tcg_gen_st16_i32(t32
, dest
, offsetof(FPReg
, l
.upper
));
975 t64
= tcg_temp_new_i64();
976 tcg_gen_ld_i64(t64
, src
, offsetof(FPReg
, l
.lower
));
977 tcg_gen_st_i64(t64
, dest
, offsetof(FPReg
, l
.lower
));
978 tcg_temp_free_i64(t64
);
981 static void gen_load_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
,
987 t64
= tcg_temp_new_i64();
988 tmp
= tcg_temp_new();
991 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
992 gen_helper_exts32(cpu_env
, fp
, tmp
);
995 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
996 gen_helper_exts32(cpu_env
, fp
, tmp
);
999 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1000 gen_helper_exts32(cpu_env
, fp
, tmp
);
1003 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1004 gen_helper_extf32(cpu_env
, fp
, tmp
);
1007 tcg_gen_qemu_ld64(t64
, addr
, index
);
1008 gen_helper_extf64(cpu_env
, fp
, t64
);
1011 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1012 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1015 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1016 tcg_gen_shri_i32(tmp
, tmp
, 16);
1017 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1018 tcg_gen_addi_i32(tmp
, addr
, 4);
1019 tcg_gen_qemu_ld64(t64
, tmp
, index
);
1020 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1024 * unimplemented data type on 68040/ColdFire
1025 * FIXME if needed for another FPU
1027 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1030 g_assert_not_reached();
1033 tcg_temp_free_i64(t64
);
1036 static void gen_store_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
,
1042 t64
= tcg_temp_new_i64();
1043 tmp
= tcg_temp_new();
1046 gen_helper_reds32(tmp
, cpu_env
, fp
);
1047 tcg_gen_qemu_st8(tmp
, addr
, index
);
1050 gen_helper_reds32(tmp
, cpu_env
, fp
);
1051 tcg_gen_qemu_st16(tmp
, addr
, index
);
1054 gen_helper_reds32(tmp
, cpu_env
, fp
);
1055 tcg_gen_qemu_st32(tmp
, addr
, index
);
1058 gen_helper_redf32(tmp
, cpu_env
, fp
);
1059 tcg_gen_qemu_st32(tmp
, addr
, index
);
1062 gen_helper_redf64(t64
, cpu_env
, fp
);
1063 tcg_gen_qemu_st64(t64
, addr
, index
);
1066 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1067 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1070 tcg_gen_ld16u_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1071 tcg_gen_shli_i32(tmp
, tmp
, 16);
1072 tcg_gen_qemu_st32(tmp
, addr
, index
);
1073 tcg_gen_addi_i32(tmp
, addr
, 4);
1074 tcg_gen_ld_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1075 tcg_gen_qemu_st64(t64
, tmp
, index
);
1079 * unimplemented data type on 68040/ColdFire
1080 * FIXME if needed for another FPU
1082 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1085 g_assert_not_reached();
1088 tcg_temp_free_i64(t64
);
1091 static void gen_ldst_fp(DisasContext
*s
, int opsize
, TCGv addr
,
1092 TCGv_ptr fp
, ea_what what
, int index
)
1094 if (what
== EA_STORE
) {
1095 gen_store_fp(s
, opsize
, addr
, fp
, index
);
1097 gen_load_fp(s
, opsize
, addr
, fp
, index
);
1101 static int gen_ea_mode_fp(CPUM68KState
*env
, DisasContext
*s
, int mode
,
1102 int reg0
, int opsize
, TCGv_ptr fp
, ea_what what
,
1105 TCGv reg
, addr
, tmp
;
1109 case 0: /* Data register direct. */
1110 reg
= cpu_dregs
[reg0
];
1111 if (what
== EA_STORE
) {
1116 gen_helper_reds32(reg
, cpu_env
, fp
);
1119 gen_helper_redf32(reg
, cpu_env
, fp
);
1122 g_assert_not_reached();
1125 tmp
= tcg_temp_new();
1128 tcg_gen_ext8s_i32(tmp
, reg
);
1129 gen_helper_exts32(cpu_env
, fp
, tmp
);
1132 tcg_gen_ext16s_i32(tmp
, reg
);
1133 gen_helper_exts32(cpu_env
, fp
, tmp
);
1136 gen_helper_exts32(cpu_env
, fp
, reg
);
1139 gen_helper_extf32(cpu_env
, fp
, reg
);
1142 g_assert_not_reached();
1147 case 1: /* Address register direct. */
1149 case 2: /* Indirect register */
1150 addr
= get_areg(s
, reg0
);
1151 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1153 case 3: /* Indirect postincrement. */
1154 addr
= cpu_aregs
[reg0
];
1155 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1156 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(opsize
));
1158 case 4: /* Indirect predecrememnt. */
1159 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1160 if (IS_NULL_QREG(addr
)) {
1163 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1164 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
1166 case 5: /* Indirect displacement. */
1167 case 6: /* Indirect index + displacement. */
1169 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1170 if (IS_NULL_QREG(addr
)) {
1173 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1177 case 0: /* Absolute short. */
1178 case 1: /* Absolute long. */
1179 case 2: /* pc displacement */
1180 case 3: /* pc index+displacement. */
1182 case 4: /* Immediate. */
1183 if (what
== EA_STORE
) {
1188 tmp
= tcg_const_i32((int8_t)read_im8(env
, s
));
1189 gen_helper_exts32(cpu_env
, fp
, tmp
);
1193 tmp
= tcg_const_i32((int16_t)read_im16(env
, s
));
1194 gen_helper_exts32(cpu_env
, fp
, tmp
);
1198 tmp
= tcg_const_i32(read_im32(env
, s
));
1199 gen_helper_exts32(cpu_env
, fp
, tmp
);
1203 tmp
= tcg_const_i32(read_im32(env
, s
));
1204 gen_helper_extf32(cpu_env
, fp
, tmp
);
1208 t64
= tcg_const_i64(read_im64(env
, s
));
1209 gen_helper_extf64(cpu_env
, fp
, t64
);
1210 tcg_temp_free_i64(t64
);
1213 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1214 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1217 tmp
= tcg_const_i32(read_im32(env
, s
) >> 16);
1218 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1220 t64
= tcg_const_i64(read_im64(env
, s
));
1221 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1222 tcg_temp_free_i64(t64
);
1226 * unimplemented data type on 68040/ColdFire
1227 * FIXME if needed for another FPU
1229 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1232 g_assert_not_reached();
1242 static int gen_ea_fp(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1243 int opsize
, TCGv_ptr fp
, ea_what what
, int index
)
1245 int mode
= extract32(insn
, 3, 3);
1246 int reg0
= REG(insn
, 0);
1247 return gen_ea_mode_fp(env
, s
, mode
, reg0
, opsize
, fp
, what
, index
);
1256 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
1262 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1263 if (op
== CC_OP_CMPB
|| op
== CC_OP_CMPW
|| op
== CC_OP_CMPL
) {
1269 tcond
= TCG_COND_LEU
;
1273 tcond
= TCG_COND_LTU
;
1277 tcond
= TCG_COND_EQ
;
1281 c
->v2
= tcg_const_i32(0);
1282 c
->v1
= tmp
= tcg_temp_new();
1283 tcg_gen_sub_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1284 gen_ext(tmp
, tmp
, op
- CC_OP_CMPB
, 1);
1288 tcond
= TCG_COND_LT
;
1292 tcond
= TCG_COND_LE
;
1297 c
->v2
= tcg_const_i32(0);
1303 tcond
= TCG_COND_NEVER
;
1305 case 14: /* GT (!(Z || (N ^ V))) */
1306 case 15: /* LE (Z || (N ^ V)) */
1308 * Logic operations clear V, which simplifies LE to (Z || N),
1309 * and since Z and N are co-located, this becomes a normal
1312 if (op
== CC_OP_LOGIC
) {
1314 tcond
= TCG_COND_LE
;
1318 case 12: /* GE (!(N ^ V)) */
1319 case 13: /* LT (N ^ V) */
1320 /* Logic operations clear V, which simplifies this to N. */
1321 if (op
!= CC_OP_LOGIC
) {
1325 case 10: /* PL (!N) */
1326 case 11: /* MI (N) */
1327 /* Several cases represent N normally. */
1328 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1329 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1330 op
== CC_OP_LOGIC
) {
1332 tcond
= TCG_COND_LT
;
1336 case 6: /* NE (!Z) */
1337 case 7: /* EQ (Z) */
1338 /* Some cases fold Z into N. */
1339 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1340 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1341 op
== CC_OP_LOGIC
) {
1342 tcond
= TCG_COND_EQ
;
1347 case 4: /* CC (!C) */
1348 case 5: /* CS (C) */
1349 /* Some cases fold C into X. */
1350 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1351 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
) {
1352 tcond
= TCG_COND_NE
;
1357 case 8: /* VC (!V) */
1358 case 9: /* VS (V) */
1359 /* Logic operations clear V and C. */
1360 if (op
== CC_OP_LOGIC
) {
1361 tcond
= TCG_COND_NEVER
;
1368 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1375 /* Invalid, or handled above. */
1377 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1378 case 3: /* LS (C || Z) */
1379 c
->v1
= tmp
= tcg_temp_new();
1380 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1381 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
1382 tcond
= TCG_COND_NE
;
1384 case 4: /* CC (!C) */
1385 case 5: /* CS (C) */
1387 tcond
= TCG_COND_NE
;
1389 case 6: /* NE (!Z) */
1390 case 7: /* EQ (Z) */
1392 tcond
= TCG_COND_EQ
;
1394 case 8: /* VC (!V) */
1395 case 9: /* VS (V) */
1397 tcond
= TCG_COND_LT
;
1399 case 10: /* PL (!N) */
1400 case 11: /* MI (N) */
1402 tcond
= TCG_COND_LT
;
1404 case 12: /* GE (!(N ^ V)) */
1405 case 13: /* LT (N ^ V) */
1406 c
->v1
= tmp
= tcg_temp_new();
1407 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1408 tcond
= TCG_COND_LT
;
1410 case 14: /* GT (!(Z || (N ^ V))) */
1411 case 15: /* LE (Z || (N ^ V)) */
1412 c
->v1
= tmp
= tcg_temp_new();
1413 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1414 tcg_gen_neg_i32(tmp
, tmp
);
1415 tmp2
= tcg_temp_new();
1416 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
1417 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1418 tcg_temp_free(tmp2
);
1419 tcond
= TCG_COND_LT
;
1424 if ((cond
& 1) == 0) {
1425 tcond
= tcg_invert_cond(tcond
);
1430 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
1434 gen_cc_cond(&c
, s
, cond
);
1436 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
1439 /* Force a TB lookup after an instruction that changes the CPU state. */
1440 static void gen_exit_tb(DisasContext
*s
)
1443 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
1444 s
->base
.is_jmp
= DISAS_EXIT
;
1447 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1448 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1449 op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \
1450 if (IS_NULL_QREG(result)) { \
1451 gen_addr_fault(s); \
1456 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1457 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, \
1458 EA_STORE, IS_USER(s)); \
1459 if (IS_NULL_QREG(ea_result)) { \
1460 gen_addr_fault(s); \
1465 /* Generate a jump to an immediate address. */
1466 static void gen_jmp_tb(DisasContext
*s
, int n
, target_ulong dest
,
1469 if (unlikely(s
->ss_active
)) {
1471 tcg_gen_movi_i32(QREG_PC
, dest
);
1472 gen_raise_exception_format2(s
, EXCP_TRACE
, src
);
1473 } else if (translator_use_goto_tb(&s
->base
, dest
)) {
1475 tcg_gen_movi_i32(QREG_PC
, dest
);
1476 tcg_gen_exit_tb(s
->base
.tb
, n
);
1478 gen_jmp_im(s
, dest
);
1479 tcg_gen_exit_tb(NULL
, 0);
1481 s
->base
.is_jmp
= DISAS_NORETURN
;
1490 cond
= (insn
>> 8) & 0xf;
1491 gen_cc_cond(&c
, s
, cond
);
1493 tmp
= tcg_temp_new();
1494 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
1496 tcg_gen_neg_i32(tmp
, tmp
);
1497 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
1509 reg
= DREG(insn
, 0);
1511 offset
= (int16_t)read_im16(env
, s
);
1512 l1
= gen_new_label();
1513 gen_jmpcc(s
, (insn
>> 8) & 0xf, l1
);
1515 tmp
= tcg_temp_new();
1516 tcg_gen_ext16s_i32(tmp
, reg
);
1517 tcg_gen_addi_i32(tmp
, tmp
, -1);
1518 gen_partset_reg(OS_WORD
, reg
, tmp
);
1519 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, -1, l1
);
1520 gen_jmp_tb(s
, 1, base
+ offset
, s
->base
.pc_next
);
1522 gen_jmp_tb(s
, 0, s
->pc
, s
->base
.pc_next
);
1525 DISAS_INSN(undef_mac
)
1527 gen_exception(s
, s
->base
.pc_next
, EXCP_LINEA
);
1530 DISAS_INSN(undef_fpu
)
1532 gen_exception(s
, s
->base
.pc_next
, EXCP_LINEF
);
1538 * ??? This is both instructions that are as yet unimplemented
1539 * for the 680x0 series, as well as those that are implemented
1540 * but actually illegal for CPU32 or pre-68020.
1542 qemu_log_mask(LOG_UNIMP
, "Illegal instruction: %04x @ %08x\n",
1543 insn
, s
->base
.pc_next
);
1544 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
1554 sign
= (insn
& 0x100) != 0;
1555 reg
= DREG(insn
, 9);
1556 tmp
= tcg_temp_new();
1558 tcg_gen_ext16s_i32(tmp
, reg
);
1560 tcg_gen_ext16u_i32(tmp
, reg
);
1561 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1562 tcg_gen_mul_i32(tmp
, tmp
, src
);
1563 tcg_gen_mov_i32(reg
, tmp
);
1564 gen_logic_cc(s
, tmp
, OS_LONG
);
1575 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1577 sign
= (insn
& 0x100) != 0;
1579 /* dest.l / src.w */
1581 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1582 destr
= tcg_constant_i32(REG(insn
, 9));
1583 ilen
= tcg_constant_i32(s
->pc
- s
->base
.pc_next
);
1585 gen_helper_divsw(cpu_env
, destr
, src
, ilen
);
1587 gen_helper_divuw(cpu_env
, destr
, src
, ilen
);
1590 set_cc_op(s
, CC_OP_FLAGS
);
1595 TCGv num
, reg
, den
, ilen
;
1599 ext
= read_im16(env
, s
);
1601 sign
= (ext
& 0x0800) != 0;
1604 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
1605 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
1609 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1611 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1612 num
= tcg_constant_i32(REG(ext
, 12));
1613 reg
= tcg_constant_i32(REG(ext
, 0));
1614 ilen
= tcg_constant_i32(s
->pc
- s
->base
.pc_next
);
1616 gen_helper_divsll(cpu_env
, num
, reg
, den
, ilen
);
1618 gen_helper_divull(cpu_env
, num
, reg
, den
, ilen
);
1620 set_cc_op(s
, CC_OP_FLAGS
);
1624 /* divX.l <EA>, Dq 32/32 -> 32q */
1625 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1627 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1628 num
= tcg_constant_i32(REG(ext
, 12));
1629 reg
= tcg_constant_i32(REG(ext
, 0));
1630 ilen
= tcg_constant_i32(s
->pc
- s
->base
.pc_next
);
1632 gen_helper_divsl(cpu_env
, num
, reg
, den
, ilen
);
1634 gen_helper_divul(cpu_env
, num
, reg
, den
, ilen
);
1637 set_cc_op(s
, CC_OP_FLAGS
);
1640 static void bcd_add(TCGv dest
, TCGv src
)
1645 * dest10 = dest10 + src10 + X
1649 * t3 = t2 + dest + X
1653 * t7 = (t6 >> 2) | (t6 >> 3)
1658 * t1 = (src + 0x066) + dest + X
1659 * = result with some possible exceeding 0x6
1662 t0
= tcg_const_i32(0x066);
1663 tcg_gen_add_i32(t0
, t0
, src
);
1665 t1
= tcg_temp_new();
1666 tcg_gen_add_i32(t1
, t0
, dest
);
1667 tcg_gen_add_i32(t1
, t1
, QREG_CC_X
);
1669 /* we will remove exceeding 0x6 where there is no carry */
1672 * t0 = (src + 0x0066) ^ dest
1673 * = t1 without carries
1676 tcg_gen_xor_i32(t0
, t0
, dest
);
1679 * extract the carries
1681 * = only the carries
1684 tcg_gen_xor_i32(t0
, t0
, t1
);
1687 * generate 0x1 where there is no carry
1688 * and for each 0x10, generate a 0x6
1691 tcg_gen_shri_i32(t0
, t0
, 3);
1692 tcg_gen_not_i32(t0
, t0
);
1693 tcg_gen_andi_i32(t0
, t0
, 0x22);
1694 tcg_gen_add_i32(dest
, t0
, t0
);
1695 tcg_gen_add_i32(dest
, dest
, t0
);
1699 * remove the exceeding 0x6
1700 * for digits that have not generated a carry
1703 tcg_gen_sub_i32(dest
, t1
, dest
);
1707 static void bcd_sub(TCGv dest
, TCGv src
)
1712 * dest10 = dest10 - src10 - X
1713 * = bcd_add(dest + 1 - X, 0x199 - src)
1716 /* t0 = 0x066 + (0x199 - src) */
1718 t0
= tcg_temp_new();
1719 tcg_gen_subfi_i32(t0
, 0x1ff, src
);
1721 /* t1 = t0 + dest + 1 - X*/
1723 t1
= tcg_temp_new();
1724 tcg_gen_add_i32(t1
, t0
, dest
);
1725 tcg_gen_addi_i32(t1
, t1
, 1);
1726 tcg_gen_sub_i32(t1
, t1
, QREG_CC_X
);
1728 /* t2 = t0 ^ dest */
1730 t2
= tcg_temp_new();
1731 tcg_gen_xor_i32(t2
, t0
, dest
);
1735 tcg_gen_xor_i32(t0
, t1
, t2
);
1739 * t0 = (t2 >> 2) | (t2 >> 3)
1741 * to fit on 8bit operands, changed in:
1743 * t2 = ~(t0 >> 3) & 0x22
1748 tcg_gen_shri_i32(t2
, t0
, 3);
1749 tcg_gen_not_i32(t2
, t2
);
1750 tcg_gen_andi_i32(t2
, t2
, 0x22);
1751 tcg_gen_add_i32(t0
, t2
, t2
);
1752 tcg_gen_add_i32(t0
, t0
, t2
);
1755 /* return t1 - t0 */
1757 tcg_gen_sub_i32(dest
, t1
, t0
);
1762 static void bcd_flags(TCGv val
)
1764 tcg_gen_andi_i32(QREG_CC_C
, val
, 0x0ff);
1765 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_C
);
1767 tcg_gen_extract_i32(QREG_CC_C
, val
, 8, 1);
1769 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
1772 DISAS_INSN(abcd_reg
)
1777 gen_flush_flags(s
); /* !Z is sticky */
1779 src
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
1780 dest
= gen_extend(s
, DREG(insn
, 9), OS_BYTE
, 0);
1782 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1787 DISAS_INSN(abcd_mem
)
1789 TCGv src
, dest
, addr
;
1791 gen_flush_flags(s
); /* !Z is sticky */
1793 /* Indirect pre-decrement load (mode 4) */
1795 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1796 NULL_QREG
, NULL
, EA_LOADU
, IS_USER(s
));
1797 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1798 NULL_QREG
, &addr
, EA_LOADU
, IS_USER(s
));
1802 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
,
1803 EA_STORE
, IS_USER(s
));
1808 DISAS_INSN(sbcd_reg
)
1812 gen_flush_flags(s
); /* !Z is sticky */
1814 src
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
1815 dest
= gen_extend(s
, DREG(insn
, 9), OS_BYTE
, 0);
1819 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1824 DISAS_INSN(sbcd_mem
)
1826 TCGv src
, dest
, addr
;
1828 gen_flush_flags(s
); /* !Z is sticky */
1830 /* Indirect pre-decrement load (mode 4) */
1832 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1833 NULL_QREG
, NULL
, EA_LOADU
, IS_USER(s
));
1834 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1835 NULL_QREG
, &addr
, EA_LOADU
, IS_USER(s
));
1839 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
,
1840 EA_STORE
, IS_USER(s
));
1850 gen_flush_flags(s
); /* !Z is sticky */
1852 SRC_EA(env
, src
, OS_BYTE
, 0, &addr
);
1854 dest
= tcg_const_i32(0);
1857 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1861 tcg_temp_free(dest
);
1874 add
= (insn
& 0x4000) != 0;
1875 opsize
= insn_opsize(insn
);
1876 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
1877 dest
= tcg_temp_new();
1879 SRC_EA(env
, tmp
, opsize
, 1, &addr
);
1883 SRC_EA(env
, src
, opsize
, 1, NULL
);
1886 tcg_gen_add_i32(dest
, tmp
, src
);
1887 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1888 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
1890 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1891 tcg_gen_sub_i32(dest
, tmp
, src
);
1892 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
1894 gen_update_cc_add(dest
, src
, opsize
);
1896 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1898 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
1900 tcg_temp_free(dest
);
1903 /* Reverse the order of the bits in REG. */
1907 reg
= DREG(insn
, 0);
1908 gen_helper_bitrev(reg
, reg
);
1911 DISAS_INSN(bitop_reg
)
1921 if ((insn
& 0x38) != 0)
1925 op
= (insn
>> 6) & 3;
1926 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1929 src2
= tcg_temp_new();
1930 if (opsize
== OS_BYTE
)
1931 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 7);
1933 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 31);
1935 tmp
= tcg_const_i32(1);
1936 tcg_gen_shl_i32(tmp
, tmp
, src2
);
1937 tcg_temp_free(src2
);
1939 tcg_gen_and_i32(QREG_CC_Z
, src1
, tmp
);
1941 dest
= tcg_temp_new();
1944 tcg_gen_xor_i32(dest
, src1
, tmp
);
1947 tcg_gen_andc_i32(dest
, src1
, tmp
);
1950 tcg_gen_or_i32(dest
, src1
, tmp
);
1957 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1959 tcg_temp_free(dest
);
1965 reg
= DREG(insn
, 0);
1967 gen_helper_sats(reg
, reg
, QREG_CC_V
);
1968 gen_logic_cc(s
, reg
, OS_LONG
);
1971 static void gen_push(DisasContext
*s
, TCGv val
)
1975 tmp
= tcg_temp_new();
1976 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1977 gen_store(s
, OS_LONG
, tmp
, val
, IS_USER(s
));
1978 tcg_gen_mov_i32(QREG_SP
, tmp
);
1982 static TCGv
mreg(int reg
)
1986 return cpu_dregs
[reg
];
1989 return cpu_aregs
[reg
& 7];
1994 TCGv addr
, incr
, tmp
, r
[16];
1995 int is_load
= (insn
& 0x0400) != 0;
1996 int opsize
= (insn
& 0x40) != 0 ? OS_LONG
: OS_WORD
;
1997 uint16_t mask
= read_im16(env
, s
);
1998 int mode
= extract32(insn
, 3, 3);
1999 int reg0
= REG(insn
, 0);
2002 tmp
= cpu_aregs
[reg0
];
2005 case 0: /* data register direct */
2006 case 1: /* addr register direct */
2011 case 2: /* indirect */
2014 case 3: /* indirect post-increment */
2016 /* post-increment is not allowed */
2021 case 4: /* indirect pre-decrement */
2023 /* pre-decrement is not allowed */
2027 * We want a bare copy of the address reg, without any pre-decrement
2028 * adjustment, as gen_lea would provide.
2033 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
2034 if (IS_NULL_QREG(tmp
)) {
2040 addr
= tcg_temp_new();
2041 tcg_gen_mov_i32(addr
, tmp
);
2042 incr
= tcg_const_i32(opsize_bytes(opsize
));
2045 /* memory to register */
2046 for (i
= 0; i
< 16; i
++) {
2047 if (mask
& (1 << i
)) {
2048 r
[i
] = gen_load(s
, opsize
, addr
, 1, IS_USER(s
));
2049 tcg_gen_add_i32(addr
, addr
, incr
);
2052 for (i
= 0; i
< 16; i
++) {
2053 if (mask
& (1 << i
)) {
2054 tcg_gen_mov_i32(mreg(i
), r
[i
]);
2055 tcg_temp_free(r
[i
]);
2059 /* post-increment: movem (An)+,X */
2060 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2063 /* register to memory */
2065 /* pre-decrement: movem X,-(An) */
2066 for (i
= 15; i
>= 0; i
--) {
2067 if ((mask
<< i
) & 0x8000) {
2068 tcg_gen_sub_i32(addr
, addr
, incr
);
2069 if (reg0
+ 8 == i
&&
2070 m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
)) {
2072 * M68020+: if the addressing register is the
2073 * register moved to memory, the value written
2074 * is the initial value decremented by the size of
2075 * the operation, regardless of how many actual
2076 * stores have been performed until this point.
2077 * M68000/M68010: the value is the initial value.
2079 tmp
= tcg_temp_new();
2080 tcg_gen_sub_i32(tmp
, cpu_aregs
[reg0
], incr
);
2081 gen_store(s
, opsize
, addr
, tmp
, IS_USER(s
));
2084 gen_store(s
, opsize
, addr
, mreg(i
), IS_USER(s
));
2088 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2090 for (i
= 0; i
< 16; i
++) {
2091 if (mask
& (1 << i
)) {
2092 gen_store(s
, opsize
, addr
, mreg(i
), IS_USER(s
));
2093 tcg_gen_add_i32(addr
, addr
, incr
);
2099 tcg_temp_free(incr
);
2100 tcg_temp_free(addr
);
2112 displ
= read_im16(env
, s
);
2114 addr
= AREG(insn
, 0);
2115 reg
= DREG(insn
, 9);
2117 abuf
= tcg_temp_new();
2118 tcg_gen_addi_i32(abuf
, addr
, displ
);
2119 dbuf
= tcg_temp_new();
2128 for ( ; i
> 0 ; i
--) {
2129 tcg_gen_shri_i32(dbuf
, reg
, (i
- 1) * 8);
2130 tcg_gen_qemu_st8(dbuf
, abuf
, IS_USER(s
));
2132 tcg_gen_addi_i32(abuf
, abuf
, 2);
2136 for ( ; i
> 0 ; i
--) {
2137 tcg_gen_qemu_ld8u(dbuf
, abuf
, IS_USER(s
));
2138 tcg_gen_deposit_i32(reg
, reg
, dbuf
, (i
- 1) * 8, 8);
2140 tcg_gen_addi_i32(abuf
, abuf
, 2);
2144 tcg_temp_free(abuf
);
2145 tcg_temp_free(dbuf
);
2148 DISAS_INSN(bitop_im
)
2158 if ((insn
& 0x38) != 0)
2162 op
= (insn
>> 6) & 3;
2164 bitnum
= read_im16(env
, s
);
2165 if (m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
2166 if (bitnum
& 0xfe00) {
2167 disas_undef(env
, s
, insn
);
2171 if (bitnum
& 0xff00) {
2172 disas_undef(env
, s
, insn
);
2177 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
2180 if (opsize
== OS_BYTE
)
2186 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
2189 tmp
= tcg_temp_new();
2192 tcg_gen_xori_i32(tmp
, src1
, mask
);
2195 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
2198 tcg_gen_ori_i32(tmp
, src1
, mask
);
2203 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
2208 static TCGv
gen_get_ccr(DisasContext
*s
)
2213 dest
= tcg_temp_new();
2214 gen_helper_get_ccr(dest
, cpu_env
);
2218 static TCGv
gen_get_sr(DisasContext
*s
)
2223 ccr
= gen_get_ccr(s
);
2224 sr
= tcg_temp_new();
2225 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
2226 tcg_gen_or_i32(sr
, sr
, ccr
);
2231 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
2234 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
2235 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
2236 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
2237 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
2238 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
2240 /* Must writeback before changing security state. */
2242 gen_helper_set_sr(cpu_env
, tcg_constant_i32(val
));
2244 set_cc_op(s
, CC_OP_FLAGS
);
2247 static void gen_set_sr(DisasContext
*s
, TCGv val
, int ccr_only
)
2250 gen_helper_set_ccr(cpu_env
, val
);
2252 /* Must writeback before changing security state. */
2254 gen_helper_set_sr(cpu_env
, val
);
2256 set_cc_op(s
, CC_OP_FLAGS
);
2259 static void gen_move_to_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
2262 if ((insn
& 0x3f) == 0x3c) {
2264 val
= read_im16(env
, s
);
2265 gen_set_sr_im(s
, val
, ccr_only
);
2268 SRC_EA(env
, src
, OS_WORD
, 0, NULL
);
2269 gen_set_sr(s
, src
, ccr_only
);
2273 DISAS_INSN(arith_im
)
2281 bool with_SR
= ((insn
& 0x3f) == 0x3c);
2283 op
= (insn
>> 9) & 7;
2284 opsize
= insn_opsize(insn
);
2287 im
= tcg_const_i32((int8_t)read_im8(env
, s
));
2290 im
= tcg_const_i32((int16_t)read_im16(env
, s
));
2293 im
= tcg_const_i32(read_im32(env
, s
));
2296 g_assert_not_reached();
2300 /* SR/CCR can only be used with andi/eori/ori */
2301 if (op
== 2 || op
== 3 || op
== 6) {
2302 disas_undef(env
, s
, insn
);
2307 src1
= gen_get_ccr(s
);
2311 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
2314 src1
= gen_get_sr(s
);
2317 /* OS_LONG; others already g_assert_not_reached. */
2318 disas_undef(env
, s
, insn
);
2322 SRC_EA(env
, src1
, opsize
, 1, (op
== 6) ? NULL
: &addr
);
2324 dest
= tcg_temp_new();
2327 tcg_gen_or_i32(dest
, src1
, im
);
2329 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2332 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2333 gen_logic_cc(s
, dest
, opsize
);
2337 tcg_gen_and_i32(dest
, src1
, im
);
2339 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2342 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2343 gen_logic_cc(s
, dest
, opsize
);
2347 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, src1
, im
);
2348 tcg_gen_sub_i32(dest
, src1
, im
);
2349 gen_update_cc_add(dest
, im
, opsize
);
2350 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2351 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2354 tcg_gen_add_i32(dest
, src1
, im
);
2355 gen_update_cc_add(dest
, im
, opsize
);
2356 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
2357 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2358 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2361 tcg_gen_xor_i32(dest
, src1
, im
);
2363 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2366 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2367 gen_logic_cc(s
, dest
, opsize
);
2371 gen_update_cc_cmp(s
, src1
, im
, opsize
);
2377 tcg_temp_free(dest
);
2389 switch ((insn
>> 9) & 3) {
2403 g_assert_not_reached();
2406 ext
= read_im16(env
, s
);
2408 /* cas Dc,Du,<EA> */
2410 addr
= gen_lea(env
, s
, insn
, opsize
);
2411 if (IS_NULL_QREG(addr
)) {
2416 cmp
= gen_extend(s
, DREG(ext
, 0), opsize
, 1);
2419 * if <EA> == Dc then
2421 * Dc = <EA> (because <EA> == Dc)
2426 load
= tcg_temp_new();
2427 tcg_gen_atomic_cmpxchg_i32(load
, addr
, cmp
, DREG(ext
, 6),
2429 /* update flags before setting cmp to load */
2430 gen_update_cc_cmp(s
, load
, cmp
, opsize
);
2431 gen_partset_reg(opsize
, DREG(ext
, 0), load
);
2433 tcg_temp_free(load
);
2435 switch (extract32(insn
, 3, 3)) {
2436 case 3: /* Indirect postincrement. */
2437 tcg_gen_addi_i32(AREG(insn
, 0), addr
, opsize_bytes(opsize
));
2439 case 4: /* Indirect predecrememnt. */
2440 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2447 uint16_t ext1
, ext2
;
2451 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2453 ext1
= read_im16(env
, s
);
2455 if (ext1
& 0x8000) {
2456 /* Address Register */
2457 addr1
= AREG(ext1
, 12);
2460 addr1
= DREG(ext1
, 12);
2463 ext2
= read_im16(env
, s
);
2464 if (ext2
& 0x8000) {
2465 /* Address Register */
2466 addr2
= AREG(ext2
, 12);
2469 addr2
= DREG(ext2
, 12);
2473 * if (R1) == Dc1 && (R2) == Dc2 then
2481 regs
= tcg_const_i32(REG(ext2
, 6) |
2482 (REG(ext1
, 6) << 3) |
2483 (REG(ext2
, 0) << 6) |
2484 (REG(ext1
, 0) << 9));
2485 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2486 gen_helper_exit_atomic(cpu_env
);
2488 gen_helper_cas2w(cpu_env
, regs
, addr1
, addr2
);
2490 tcg_temp_free(regs
);
2492 /* Note that cas2w also assigned to env->cc_op. */
2493 s
->cc_op
= CC_OP_CMPW
;
2494 s
->cc_op_synced
= 1;
2499 uint16_t ext1
, ext2
;
2500 TCGv addr1
, addr2
, regs
;
2502 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2504 ext1
= read_im16(env
, s
);
2506 if (ext1
& 0x8000) {
2507 /* Address Register */
2508 addr1
= AREG(ext1
, 12);
2511 addr1
= DREG(ext1
, 12);
2514 ext2
= read_im16(env
, s
);
2515 if (ext2
& 0x8000) {
2516 /* Address Register */
2517 addr2
= AREG(ext2
, 12);
2520 addr2
= DREG(ext2
, 12);
2524 * if (R1) == Dc1 && (R2) == Dc2 then
2532 regs
= tcg_const_i32(REG(ext2
, 6) |
2533 (REG(ext1
, 6) << 3) |
2534 (REG(ext2
, 0) << 6) |
2535 (REG(ext1
, 0) << 9));
2536 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2537 gen_helper_cas2l_parallel(cpu_env
, regs
, addr1
, addr2
);
2539 gen_helper_cas2l(cpu_env
, regs
, addr1
, addr2
);
2541 tcg_temp_free(regs
);
2543 /* Note that cas2l also assigned to env->cc_op. */
2544 s
->cc_op
= CC_OP_CMPL
;
2545 s
->cc_op_synced
= 1;
2552 reg
= DREG(insn
, 0);
2553 tcg_gen_bswap32_i32(reg
, reg
);
2563 switch (insn
>> 12) {
2564 case 1: /* move.b */
2567 case 2: /* move.l */
2570 case 3: /* move.w */
2576 SRC_EA(env
, src
, opsize
, 1, NULL
);
2577 op
= (insn
>> 6) & 7;
2580 /* The value will already have been sign extended. */
2581 dest
= AREG(insn
, 9);
2582 tcg_gen_mov_i32(dest
, src
);
2586 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
2587 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
2588 /* This will be correct because loads sign extend. */
2589 gen_logic_cc(s
, src
, opsize
);
2600 opsize
= insn_opsize(insn
);
2601 SRC_EA(env
, src
, opsize
, 1, &addr
);
2603 gen_flush_flags(s
); /* compute old Z */
2606 * Perform subtract with borrow.
2607 * (X, N) = -(src + X);
2610 z
= tcg_const_i32(0);
2611 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, z
, QREG_CC_X
, z
);
2612 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, z
, z
, QREG_CC_N
, QREG_CC_X
);
2614 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2616 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2619 * Compute signed-overflow for negation. The normal formula for
2620 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2621 * this simplifies to res & src.
2624 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_N
, src
);
2626 /* Copy the rest of the results into place. */
2627 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2628 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2630 set_cc_op(s
, CC_OP_FLAGS
);
2632 /* result is in QREG_CC_N */
2634 DEST_EA(env
, insn
, opsize
, QREG_CC_N
, &addr
);
2642 reg
= AREG(insn
, 9);
2643 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2644 if (IS_NULL_QREG(tmp
)) {
2648 tcg_gen_mov_i32(reg
, tmp
);
2656 zero
= tcg_const_i32(0);
2658 opsize
= insn_opsize(insn
);
2659 DEST_EA(env
, insn
, opsize
, zero
, NULL
);
2660 gen_logic_cc(s
, zero
, opsize
);
2661 tcg_temp_free(zero
);
2664 DISAS_INSN(move_from_ccr
)
2668 ccr
= gen_get_ccr(s
);
2669 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
2679 opsize
= insn_opsize(insn
);
2680 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2681 dest
= tcg_temp_new();
2682 tcg_gen_neg_i32(dest
, src1
);
2683 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2684 gen_update_cc_add(dest
, src1
, opsize
);
2685 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, dest
, 0);
2686 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2687 tcg_temp_free(dest
);
2690 DISAS_INSN(move_to_ccr
)
2692 gen_move_to_sr(env
, s
, insn
, true);
2702 opsize
= insn_opsize(insn
);
2703 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2704 dest
= tcg_temp_new();
2705 tcg_gen_not_i32(dest
, src1
);
2706 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2707 gen_logic_cc(s
, dest
, opsize
);
2716 src1
= tcg_temp_new();
2717 src2
= tcg_temp_new();
2718 reg
= DREG(insn
, 0);
2719 tcg_gen_shli_i32(src1
, reg
, 16);
2720 tcg_gen_shri_i32(src2
, reg
, 16);
2721 tcg_gen_or_i32(reg
, src1
, src2
);
2722 tcg_temp_free(src2
);
2723 tcg_temp_free(src1
);
2724 gen_logic_cc(s
, reg
, OS_LONG
);
2729 #if defined(CONFIG_SOFTMMU)
2730 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
2732 gen_exception(s
, s
->base
.pc_next
, EXCP_DEBUG
);
2740 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2741 if (IS_NULL_QREG(tmp
)) {
2754 reg
= DREG(insn
, 0);
2755 op
= (insn
>> 6) & 7;
2756 tmp
= tcg_temp_new();
2758 tcg_gen_ext16s_i32(tmp
, reg
);
2760 tcg_gen_ext8s_i32(tmp
, reg
);
2762 gen_partset_reg(OS_WORD
, reg
, tmp
);
2764 tcg_gen_mov_i32(reg
, tmp
);
2765 gen_logic_cc(s
, tmp
, OS_LONG
);
2774 opsize
= insn_opsize(insn
);
2775 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
2776 gen_logic_cc(s
, tmp
, opsize
);
2781 /* Implemented as a NOP. */
2786 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
2791 int mode
= extract32(insn
, 3, 3);
2792 int reg0
= REG(insn
, 0);
2795 /* data register direct */
2796 TCGv dest
= cpu_dregs
[reg0
];
2797 gen_logic_cc(s
, dest
, OS_BYTE
);
2798 tcg_gen_ori_tl(dest
, dest
, 0x80);
2802 addr
= gen_lea_mode(env
, s
, mode
, reg0
, OS_BYTE
);
2803 if (IS_NULL_QREG(addr
)) {
2807 src1
= tcg_temp_new();
2808 tcg_gen_atomic_fetch_or_tl(src1
, addr
, tcg_constant_tl(0x80),
2810 gen_logic_cc(s
, src1
, OS_BYTE
);
2811 tcg_temp_free(src1
);
2814 case 3: /* Indirect postincrement. */
2815 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 1);
2817 case 4: /* Indirect predecrememnt. */
2818 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2830 ext
= read_im16(env
, s
);
2835 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
2836 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
2840 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2843 tcg_gen_muls2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2845 tcg_gen_mulu2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2847 /* if Dl == Dh, 68040 returns low word */
2848 tcg_gen_mov_i32(DREG(ext
, 0), QREG_CC_N
);
2849 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_Z
);
2850 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
);
2852 tcg_gen_movi_i32(QREG_CC_V
, 0);
2853 tcg_gen_movi_i32(QREG_CC_C
, 0);
2855 set_cc_op(s
, CC_OP_FLAGS
);
2858 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2859 if (m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
2860 tcg_gen_movi_i32(QREG_CC_C
, 0);
2862 tcg_gen_muls2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2863 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2864 tcg_gen_sari_i32(QREG_CC_Z
, QREG_CC_N
, 31);
2865 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_Z
);
2867 tcg_gen_mulu2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2868 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2869 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_C
);
2871 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
2872 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_N
);
2874 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
2876 set_cc_op(s
, CC_OP_FLAGS
);
2879 * The upper 32 bits of the product are discarded, so
2880 * muls.l and mulu.l are functionally equivalent.
2882 tcg_gen_mul_i32(DREG(ext
, 12), src1
, DREG(ext
, 12));
2883 gen_logic_cc(s
, DREG(ext
, 12), OS_LONG
);
2887 static void gen_link(DisasContext
*s
, uint16_t insn
, int32_t offset
)
2892 reg
= AREG(insn
, 0);
2893 tmp
= tcg_temp_new();
2894 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2895 gen_store(s
, OS_LONG
, tmp
, reg
, IS_USER(s
));
2896 if ((insn
& 7) != 7) {
2897 tcg_gen_mov_i32(reg
, tmp
);
2899 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
2907 offset
= read_im16(env
, s
);
2908 gen_link(s
, insn
, offset
);
2915 offset
= read_im32(env
, s
);
2916 gen_link(s
, insn
, offset
);
2925 src
= tcg_temp_new();
2926 reg
= AREG(insn
, 0);
2927 tcg_gen_mov_i32(src
, reg
);
2928 tmp
= gen_load(s
, OS_LONG
, src
, 0, IS_USER(s
));
2929 tcg_gen_mov_i32(reg
, tmp
);
2930 tcg_gen_addi_i32(QREG_SP
, src
, 4);
2935 #if defined(CONFIG_SOFTMMU)
2939 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
2943 gen_helper_reset(cpu_env
);
2954 int16_t offset
= read_im16(env
, s
);
2956 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0, IS_USER(s
));
2957 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, offset
+ 4);
2967 sp
= tcg_temp_new();
2968 ccr
= gen_load(s
, OS_WORD
, QREG_SP
, 0, IS_USER(s
));
2969 tcg_gen_addi_i32(sp
, QREG_SP
, 2);
2970 tmp
= gen_load(s
, OS_LONG
, sp
, 0, IS_USER(s
));
2971 tcg_gen_addi_i32(QREG_SP
, sp
, 4);
2974 gen_set_sr(s
, ccr
, true);
2984 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0, IS_USER(s
));
2985 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
2994 * Load the target address first to ensure correct exception
2997 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2998 if (IS_NULL_QREG(tmp
)) {
3002 if ((insn
& 0x40) == 0) {
3004 gen_push(s
, tcg_const_i32(s
->pc
));
3018 if ((insn
& 070) == 010) {
3019 /* Operation on address register is always long. */
3022 opsize
= insn_opsize(insn
);
3024 SRC_EA(env
, src
, opsize
, 1, &addr
);
3025 imm
= (insn
>> 9) & 7;
3029 val
= tcg_const_i32(imm
);
3030 dest
= tcg_temp_new();
3031 tcg_gen_mov_i32(dest
, src
);
3032 if ((insn
& 0x38) == 0x08) {
3034 * Don't update condition codes if the destination is an
3037 if (insn
& 0x0100) {
3038 tcg_gen_sub_i32(dest
, dest
, val
);
3040 tcg_gen_add_i32(dest
, dest
, val
);
3043 if (insn
& 0x0100) {
3044 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
3045 tcg_gen_sub_i32(dest
, dest
, val
);
3046 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
3048 tcg_gen_add_i32(dest
, dest
, val
);
3049 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
3050 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
3052 gen_update_cc_add(dest
, val
, opsize
);
3055 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3056 tcg_temp_free(dest
);
3066 op
= (insn
>> 8) & 0xf;
3067 offset
= (int8_t)insn
;
3069 offset
= (int16_t)read_im16(env
, s
);
3070 } else if (offset
== -1) {
3071 offset
= read_im32(env
, s
);
3075 gen_push(s
, tcg_const_i32(s
->pc
));
3079 TCGLabel
*l1
= gen_new_label();
3080 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
3081 gen_jmp_tb(s
, 1, base
+ offset
, s
->base
.pc_next
);
3083 gen_jmp_tb(s
, 0, s
->pc
, s
->base
.pc_next
);
3085 /* Unconditional branch. */
3087 gen_jmp_tb(s
, 0, base
+ offset
, s
->base
.pc_next
);
3093 tcg_gen_movi_i32(DREG(insn
, 9), (int8_t)insn
);
3094 gen_logic_cc(s
, DREG(insn
, 9), OS_LONG
);
3107 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
3108 reg
= DREG(insn
, 9);
3109 tcg_gen_mov_i32(reg
, src
);
3110 gen_logic_cc(s
, src
, opsize
);
3121 opsize
= insn_opsize(insn
);
3122 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 0);
3123 dest
= tcg_temp_new();
3125 SRC_EA(env
, src
, opsize
, 0, &addr
);
3126 tcg_gen_or_i32(dest
, src
, reg
);
3127 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3129 SRC_EA(env
, src
, opsize
, 0, NULL
);
3130 tcg_gen_or_i32(dest
, src
, reg
);
3131 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
3133 gen_logic_cc(s
, dest
, opsize
);
3134 tcg_temp_free(dest
);
3142 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3143 reg
= AREG(insn
, 9);
3144 tcg_gen_sub_i32(reg
, reg
, src
);
3147 static inline void gen_subx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3151 gen_flush_flags(s
); /* compute old Z */
3154 * Perform subtract with borrow.
3155 * (X, N) = dest - (src + X);
3158 tmp
= tcg_const_i32(0);
3159 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, tmp
, QREG_CC_X
, tmp
);
3160 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, dest
, tmp
, QREG_CC_N
, QREG_CC_X
);
3161 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3162 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
3164 /* Compute signed-overflow for subtract. */
3166 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, dest
);
3167 tcg_gen_xor_i32(tmp
, dest
, src
);
3168 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3171 /* Copy the rest of the results into place. */
3172 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3173 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3175 set_cc_op(s
, CC_OP_FLAGS
);
3177 /* result is in QREG_CC_N */
3180 DISAS_INSN(subx_reg
)
3186 opsize
= insn_opsize(insn
);
3188 src
= gen_extend(s
, DREG(insn
, 0), opsize
, 1);
3189 dest
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3191 gen_subx(s
, src
, dest
, opsize
);
3193 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3196 DISAS_INSN(subx_mem
)
3204 opsize
= insn_opsize(insn
);
3206 addr_src
= AREG(insn
, 0);
3207 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3208 src
= gen_load(s
, opsize
, addr_src
, 1, IS_USER(s
));
3210 addr_dest
= AREG(insn
, 9);
3211 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3212 dest
= gen_load(s
, opsize
, addr_dest
, 1, IS_USER(s
));
3214 gen_subx(s
, src
, dest
, opsize
);
3216 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
, IS_USER(s
));
3218 tcg_temp_free(dest
);
3227 val
= (insn
>> 9) & 7;
3230 src
= tcg_const_i32(val
);
3231 gen_logic_cc(s
, src
, OS_LONG
);
3232 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
3242 opsize
= insn_opsize(insn
);
3243 SRC_EA(env
, src
, opsize
, 1, NULL
);
3244 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3245 gen_update_cc_cmp(s
, reg
, src
, opsize
);
3259 SRC_EA(env
, src
, opsize
, 1, NULL
);
3260 reg
= AREG(insn
, 9);
3261 gen_update_cc_cmp(s
, reg
, src
, OS_LONG
);
3266 int opsize
= insn_opsize(insn
);
3269 /* Post-increment load (mode 3) from Ay. */
3270 src
= gen_ea_mode(env
, s
, 3, REG(insn
, 0), opsize
,
3271 NULL_QREG
, NULL
, EA_LOADS
, IS_USER(s
));
3272 /* Post-increment load (mode 3) from Ax. */
3273 dst
= gen_ea_mode(env
, s
, 3, REG(insn
, 9), opsize
,
3274 NULL_QREG
, NULL
, EA_LOADS
, IS_USER(s
));
3276 gen_update_cc_cmp(s
, dst
, src
, opsize
);
3286 opsize
= insn_opsize(insn
);
3288 SRC_EA(env
, src
, opsize
, 0, &addr
);
3289 dest
= tcg_temp_new();
3290 tcg_gen_xor_i32(dest
, src
, DREG(insn
, 9));
3291 gen_logic_cc(s
, dest
, opsize
);
3292 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3293 tcg_temp_free(dest
);
3296 static void do_exg(TCGv reg1
, TCGv reg2
)
3298 TCGv temp
= tcg_temp_new();
3299 tcg_gen_mov_i32(temp
, reg1
);
3300 tcg_gen_mov_i32(reg1
, reg2
);
3301 tcg_gen_mov_i32(reg2
, temp
);
3302 tcg_temp_free(temp
);
3307 /* exchange Dx and Dy */
3308 do_exg(DREG(insn
, 9), DREG(insn
, 0));
3313 /* exchange Ax and Ay */
3314 do_exg(AREG(insn
, 9), AREG(insn
, 0));
3319 /* exchange Dx and Ay */
3320 do_exg(DREG(insn
, 9), AREG(insn
, 0));
3331 dest
= tcg_temp_new();
3333 opsize
= insn_opsize(insn
);
3334 reg
= DREG(insn
, 9);
3336 SRC_EA(env
, src
, opsize
, 0, &addr
);
3337 tcg_gen_and_i32(dest
, src
, reg
);
3338 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3340 SRC_EA(env
, src
, opsize
, 0, NULL
);
3341 tcg_gen_and_i32(dest
, src
, reg
);
3342 gen_partset_reg(opsize
, reg
, dest
);
3344 gen_logic_cc(s
, dest
, opsize
);
3345 tcg_temp_free(dest
);
3353 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3354 reg
= AREG(insn
, 9);
3355 tcg_gen_add_i32(reg
, reg
, src
);
3358 static inline void gen_addx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3362 gen_flush_flags(s
); /* compute old Z */
3365 * Perform addition with carry.
3366 * (X, N) = src + dest + X;
3369 tmp
= tcg_const_i32(0);
3370 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_X
, tmp
, dest
, tmp
);
3371 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_N
, QREG_CC_X
, src
, tmp
);
3372 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3374 /* Compute signed-overflow for addition. */
3376 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3377 tcg_gen_xor_i32(tmp
, dest
, src
);
3378 tcg_gen_andc_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3381 /* Copy the rest of the results into place. */
3382 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3383 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3385 set_cc_op(s
, CC_OP_FLAGS
);
3387 /* result is in QREG_CC_N */
3390 DISAS_INSN(addx_reg
)
3396 opsize
= insn_opsize(insn
);
3398 dest
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3399 src
= gen_extend(s
, DREG(insn
, 0), opsize
, 1);
3401 gen_addx(s
, src
, dest
, opsize
);
3403 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3406 DISAS_INSN(addx_mem
)
3414 opsize
= insn_opsize(insn
);
3416 addr_src
= AREG(insn
, 0);
3417 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3418 src
= gen_load(s
, opsize
, addr_src
, 1, IS_USER(s
));
3420 addr_dest
= AREG(insn
, 9);
3421 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3422 dest
= gen_load(s
, opsize
, addr_dest
, 1, IS_USER(s
));
3424 gen_addx(s
, src
, dest
, opsize
);
3426 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
, IS_USER(s
));
3428 tcg_temp_free(dest
);
3432 static inline void shift_im(DisasContext
*s
, uint16_t insn
, int opsize
)
3434 int count
= (insn
>> 9) & 7;
3435 int logical
= insn
& 8;
3436 int left
= insn
& 0x100;
3437 int bits
= opsize_bytes(opsize
) * 8;
3438 TCGv reg
= gen_extend(s
, DREG(insn
, 0), opsize
, !logical
);
3444 tcg_gen_movi_i32(QREG_CC_V
, 0);
3446 tcg_gen_shri_i32(QREG_CC_C
, reg
, bits
- count
);
3447 tcg_gen_shli_i32(QREG_CC_N
, reg
, count
);
3450 * Note that ColdFire always clears V (done above),
3451 * while M68000 sets if the most significant bit is changed at
3452 * any time during the shift operation.
3454 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
3455 /* if shift count >= bits, V is (reg != 0) */
3456 if (count
>= bits
) {
3457 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, reg
, QREG_CC_V
);
3459 TCGv t0
= tcg_temp_new();
3460 tcg_gen_sari_i32(QREG_CC_V
, reg
, bits
- 1);
3461 tcg_gen_sari_i32(t0
, reg
, bits
- count
- 1);
3462 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, t0
);
3465 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3468 tcg_gen_shri_i32(QREG_CC_C
, reg
, count
- 1);
3470 tcg_gen_shri_i32(QREG_CC_N
, reg
, count
);
3472 tcg_gen_sari_i32(QREG_CC_N
, reg
, count
);
3476 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3477 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3478 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3479 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3481 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3482 set_cc_op(s
, CC_OP_FLAGS
);
3485 static inline void shift_reg(DisasContext
*s
, uint16_t insn
, int opsize
)
3487 int logical
= insn
& 8;
3488 int left
= insn
& 0x100;
3489 int bits
= opsize_bytes(opsize
) * 8;
3490 TCGv reg
= gen_extend(s
, DREG(insn
, 0), opsize
, !logical
);
3494 t64
= tcg_temp_new_i64();
3495 s64
= tcg_temp_new_i64();
3496 s32
= tcg_temp_new();
3499 * Note that m68k truncates the shift count modulo 64, not 32.
3500 * In addition, a 64-bit shift makes it easy to find "the last
3501 * bit shifted out", for the carry flag.
3503 tcg_gen_andi_i32(s32
, DREG(insn
, 9), 63);
3504 tcg_gen_extu_i32_i64(s64
, s32
);
3505 tcg_gen_extu_i32_i64(t64
, reg
);
3507 /* Optimistically set V=0. Also used as a zero source below. */
3508 tcg_gen_movi_i32(QREG_CC_V
, 0);
3510 tcg_gen_shl_i64(t64
, t64
, s64
);
3512 if (opsize
== OS_LONG
) {
3513 tcg_gen_extr_i64_i32(QREG_CC_N
, QREG_CC_C
, t64
);
3514 /* Note that C=0 if shift count is 0, and we get that for free. */
3516 TCGv zero
= tcg_const_i32(0);
3517 tcg_gen_extrl_i64_i32(QREG_CC_N
, t64
);
3518 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_N
, bits
);
3519 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3520 s32
, zero
, zero
, QREG_CC_C
);
3521 tcg_temp_free(zero
);
3523 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3525 /* X = C, but only if the shift count was non-zero. */
3526 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3527 QREG_CC_C
, QREG_CC_X
);
3530 * M68000 sets V if the most significant bit is changed at
3531 * any time during the shift operation. Do this via creating
3532 * an extension of the sign bit, comparing, and discarding
3533 * the bits below the sign bit. I.e.
3534 * int64_t s = (intN_t)reg;
3535 * int64_t t = (int64_t)(intN_t)reg << count;
3536 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3538 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
3539 TCGv_i64 tt
= tcg_const_i64(32);
3540 /* if shift is greater than 32, use 32 */
3541 tcg_gen_movcond_i64(TCG_COND_GT
, s64
, s64
, tt
, tt
, s64
);
3542 tcg_temp_free_i64(tt
);
3543 /* Sign extend the input to 64 bits; re-do the shift. */
3544 tcg_gen_ext_i32_i64(t64
, reg
);
3545 tcg_gen_shl_i64(s64
, t64
, s64
);
3546 /* Clear all bits that are unchanged. */
3547 tcg_gen_xor_i64(t64
, t64
, s64
);
3548 /* Ignore the bits below the sign bit. */
3549 tcg_gen_andi_i64(t64
, t64
, -1ULL << (bits
- 1));
3550 /* If any bits remain set, we have overflow. */
3551 tcg_gen_setcondi_i64(TCG_COND_NE
, t64
, t64
, 0);
3552 tcg_gen_extrl_i64_i32(QREG_CC_V
, t64
);
3553 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3556 tcg_gen_shli_i64(t64
, t64
, 32);
3558 tcg_gen_shr_i64(t64
, t64
, s64
);
3560 tcg_gen_sar_i64(t64
, t64
, s64
);
3562 tcg_gen_extr_i64_i32(QREG_CC_C
, QREG_CC_N
, t64
);
3564 /* Note that C=0 if shift count is 0, and we get that for free. */
3565 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_C
, 31);
3567 /* X = C, but only if the shift count was non-zero. */
3568 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3569 QREG_CC_C
, QREG_CC_X
);
3571 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3572 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3575 tcg_temp_free_i64(s64
);
3576 tcg_temp_free_i64(t64
);
3578 /* Write back the result. */
3579 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3580 set_cc_op(s
, CC_OP_FLAGS
);
3583 DISAS_INSN(shift8_im
)
3585 shift_im(s
, insn
, OS_BYTE
);
3588 DISAS_INSN(shift16_im
)
3590 shift_im(s
, insn
, OS_WORD
);
3593 DISAS_INSN(shift_im
)
3595 shift_im(s
, insn
, OS_LONG
);
3598 DISAS_INSN(shift8_reg
)
3600 shift_reg(s
, insn
, OS_BYTE
);
3603 DISAS_INSN(shift16_reg
)
3605 shift_reg(s
, insn
, OS_WORD
);
3608 DISAS_INSN(shift_reg
)
3610 shift_reg(s
, insn
, OS_LONG
);
3613 DISAS_INSN(shift_mem
)
3615 int logical
= insn
& 8;
3616 int left
= insn
& 0x100;
3620 SRC_EA(env
, src
, OS_WORD
, !logical
, &addr
);
3621 tcg_gen_movi_i32(QREG_CC_V
, 0);
3623 tcg_gen_shri_i32(QREG_CC_C
, src
, 15);
3624 tcg_gen_shli_i32(QREG_CC_N
, src
, 1);
3627 * Note that ColdFire always clears V,
3628 * while M68000 sets if the most significant bit is changed at
3629 * any time during the shift operation
3631 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68K
)) {
3632 src
= gen_extend(s
, src
, OS_WORD
, 1);
3633 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3636 tcg_gen_mov_i32(QREG_CC_C
, src
);
3638 tcg_gen_shri_i32(QREG_CC_N
, src
, 1);
3640 tcg_gen_sari_i32(QREG_CC_N
, src
, 1);
3644 gen_ext(QREG_CC_N
, QREG_CC_N
, OS_WORD
, 1);
3645 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3646 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3647 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3649 DEST_EA(env
, insn
, OS_WORD
, QREG_CC_N
, &addr
);
3650 set_cc_op(s
, CC_OP_FLAGS
);
3653 static void rotate(TCGv reg
, TCGv shift
, int left
, int size
)
3657 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3658 tcg_gen_ext8u_i32(reg
, reg
);
3659 tcg_gen_muli_i32(reg
, reg
, 0x01010101);
3662 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3663 tcg_gen_deposit_i32(reg
, reg
, reg
, 16, 16);
3668 tcg_gen_rotl_i32(reg
, reg
, shift
);
3670 tcg_gen_rotr_i32(reg
, reg
, shift
);
3678 tcg_gen_ext8s_i32(reg
, reg
);
3681 tcg_gen_ext16s_i32(reg
, reg
);
3687 /* QREG_CC_X is not affected */
3689 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3690 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3693 tcg_gen_andi_i32(QREG_CC_C
, reg
, 1);
3695 tcg_gen_shri_i32(QREG_CC_C
, reg
, 31);
3698 tcg_gen_movi_i32(QREG_CC_V
, 0); /* always cleared */
3701 static void rotate_x_flags(TCGv reg
, TCGv X
, int size
)
3705 tcg_gen_ext8s_i32(reg
, reg
);
3708 tcg_gen_ext16s_i32(reg
, reg
);
3713 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3714 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3715 tcg_gen_mov_i32(QREG_CC_X
, X
);
3716 tcg_gen_mov_i32(QREG_CC_C
, X
);
3717 tcg_gen_movi_i32(QREG_CC_V
, 0);
3720 /* Result of rotate_x() is valid if 0 <= shift <= size */
3721 static TCGv
rotate_x(TCGv reg
, TCGv shift
, int left
, int size
)
3723 TCGv X
, shl
, shr
, shx
, sz
, zero
;
3725 sz
= tcg_const_i32(size
);
3727 shr
= tcg_temp_new();
3728 shl
= tcg_temp_new();
3729 shx
= tcg_temp_new();
3731 tcg_gen_mov_i32(shl
, shift
); /* shl = shift */
3732 tcg_gen_movi_i32(shr
, size
+ 1);
3733 tcg_gen_sub_i32(shr
, shr
, shift
); /* shr = size + 1 - shift */
3734 tcg_gen_subi_i32(shx
, shift
, 1); /* shx = shift - 1 */
3735 /* shx = shx < 0 ? size : shx; */
3736 zero
= tcg_const_i32(0);
3737 tcg_gen_movcond_i32(TCG_COND_LT
, shx
, shx
, zero
, sz
, shx
);
3738 tcg_temp_free(zero
);
3740 tcg_gen_mov_i32(shr
, shift
); /* shr = shift */
3741 tcg_gen_movi_i32(shl
, size
+ 1);
3742 tcg_gen_sub_i32(shl
, shl
, shift
); /* shl = size + 1 - shift */
3743 tcg_gen_sub_i32(shx
, sz
, shift
); /* shx = size - shift */
3745 tcg_temp_free_i32(sz
);
3747 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3749 tcg_gen_shl_i32(shl
, reg
, shl
);
3750 tcg_gen_shr_i32(shr
, reg
, shr
);
3751 tcg_gen_or_i32(reg
, shl
, shr
);
3754 tcg_gen_shl_i32(shx
, QREG_CC_X
, shx
);
3755 tcg_gen_or_i32(reg
, reg
, shx
);
3758 /* X = (reg >> size) & 1 */
3761 tcg_gen_extract_i32(X
, reg
, size
, 1);
3766 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3767 static TCGv
rotate32_x(TCGv reg
, TCGv shift
, int left
)
3769 TCGv_i64 t0
, shift64
;
3770 TCGv X
, lo
, hi
, zero
;
3772 shift64
= tcg_temp_new_i64();
3773 tcg_gen_extu_i32_i64(shift64
, shift
);
3775 t0
= tcg_temp_new_i64();
3778 lo
= tcg_temp_new();
3779 hi
= tcg_temp_new();
3782 /* create [reg:X:..] */
3784 tcg_gen_shli_i32(lo
, QREG_CC_X
, 31);
3785 tcg_gen_concat_i32_i64(t0
, lo
, reg
);
3789 tcg_gen_rotl_i64(t0
, t0
, shift64
);
3790 tcg_temp_free_i64(shift64
);
3792 /* result is [reg:..:reg:X] */
3794 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3795 tcg_gen_andi_i32(X
, lo
, 1);
3797 tcg_gen_shri_i32(lo
, lo
, 1);
3799 /* create [..:X:reg] */
3801 tcg_gen_concat_i32_i64(t0
, reg
, QREG_CC_X
);
3803 tcg_gen_rotr_i64(t0
, t0
, shift64
);
3804 tcg_temp_free_i64(shift64
);
3806 /* result is value: [X:reg:..:reg] */
3808 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3812 tcg_gen_shri_i32(X
, hi
, 31);
3814 /* extract result */
3816 tcg_gen_shli_i32(hi
, hi
, 1);
3818 tcg_temp_free_i64(t0
);
3819 tcg_gen_or_i32(lo
, lo
, hi
);
3822 /* if shift == 0, register and X are not affected */
3824 zero
= tcg_const_i32(0);
3825 tcg_gen_movcond_i32(TCG_COND_EQ
, X
, shift
, zero
, QREG_CC_X
, X
);
3826 tcg_gen_movcond_i32(TCG_COND_EQ
, reg
, shift
, zero
, reg
, lo
);
3827 tcg_temp_free(zero
);
3833 DISAS_INSN(rotate_im
)
3837 int left
= (insn
& 0x100);
3839 tmp
= (insn
>> 9) & 7;
3844 shift
= tcg_const_i32(tmp
);
3846 rotate(DREG(insn
, 0), shift
, left
, 32);
3848 TCGv X
= rotate32_x(DREG(insn
, 0), shift
, left
);
3849 rotate_x_flags(DREG(insn
, 0), X
, 32);
3852 tcg_temp_free(shift
);
3854 set_cc_op(s
, CC_OP_FLAGS
);
3857 DISAS_INSN(rotate8_im
)
3859 int left
= (insn
& 0x100);
3864 reg
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
3866 tmp
= (insn
>> 9) & 7;
3871 shift
= tcg_const_i32(tmp
);
3873 rotate(reg
, shift
, left
, 8);
3875 TCGv X
= rotate_x(reg
, shift
, left
, 8);
3876 rotate_x_flags(reg
, X
, 8);
3879 tcg_temp_free(shift
);
3880 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3881 set_cc_op(s
, CC_OP_FLAGS
);
3884 DISAS_INSN(rotate16_im
)
3886 int left
= (insn
& 0x100);
3891 reg
= gen_extend(s
, DREG(insn
, 0), OS_WORD
, 0);
3892 tmp
= (insn
>> 9) & 7;
3897 shift
= tcg_const_i32(tmp
);
3899 rotate(reg
, shift
, left
, 16);
3901 TCGv X
= rotate_x(reg
, shift
, left
, 16);
3902 rotate_x_flags(reg
, X
, 16);
3905 tcg_temp_free(shift
);
3906 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3907 set_cc_op(s
, CC_OP_FLAGS
);
3910 DISAS_INSN(rotate_reg
)
3915 int left
= (insn
& 0x100);
3917 reg
= DREG(insn
, 0);
3918 src
= DREG(insn
, 9);
3919 /* shift in [0..63] */
3920 t0
= tcg_temp_new();
3921 tcg_gen_andi_i32(t0
, src
, 63);
3922 t1
= tcg_temp_new_i32();
3924 tcg_gen_andi_i32(t1
, src
, 31);
3925 rotate(reg
, t1
, left
, 32);
3926 /* if shift == 0, clear C */
3927 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3928 t0
, QREG_CC_V
/* 0 */,
3929 QREG_CC_V
/* 0 */, QREG_CC_C
);
3933 tcg_gen_movi_i32(t1
, 33);
3934 tcg_gen_remu_i32(t1
, t0
, t1
);
3935 X
= rotate32_x(DREG(insn
, 0), t1
, left
);
3936 rotate_x_flags(DREG(insn
, 0), X
, 32);
3941 set_cc_op(s
, CC_OP_FLAGS
);
3944 DISAS_INSN(rotate8_reg
)
3949 int left
= (insn
& 0x100);
3951 reg
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
3952 src
= DREG(insn
, 9);
3953 /* shift in [0..63] */
3954 t0
= tcg_temp_new_i32();
3955 tcg_gen_andi_i32(t0
, src
, 63);
3956 t1
= tcg_temp_new_i32();
3958 tcg_gen_andi_i32(t1
, src
, 7);
3959 rotate(reg
, t1
, left
, 8);
3960 /* if shift == 0, clear C */
3961 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3962 t0
, QREG_CC_V
/* 0 */,
3963 QREG_CC_V
/* 0 */, QREG_CC_C
);
3967 tcg_gen_movi_i32(t1
, 9);
3968 tcg_gen_remu_i32(t1
, t0
, t1
);
3969 X
= rotate_x(reg
, t1
, left
, 8);
3970 rotate_x_flags(reg
, X
, 8);
3975 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3976 set_cc_op(s
, CC_OP_FLAGS
);
3979 DISAS_INSN(rotate16_reg
)
3984 int left
= (insn
& 0x100);
3986 reg
= gen_extend(s
, DREG(insn
, 0), OS_WORD
, 0);
3987 src
= DREG(insn
, 9);
3988 /* shift in [0..63] */
3989 t0
= tcg_temp_new_i32();
3990 tcg_gen_andi_i32(t0
, src
, 63);
3991 t1
= tcg_temp_new_i32();
3993 tcg_gen_andi_i32(t1
, src
, 15);
3994 rotate(reg
, t1
, left
, 16);
3995 /* if shift == 0, clear C */
3996 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3997 t0
, QREG_CC_V
/* 0 */,
3998 QREG_CC_V
/* 0 */, QREG_CC_C
);
4002 tcg_gen_movi_i32(t1
, 17);
4003 tcg_gen_remu_i32(t1
, t0
, t1
);
4004 X
= rotate_x(reg
, t1
, left
, 16);
4005 rotate_x_flags(reg
, X
, 16);
4010 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
4011 set_cc_op(s
, CC_OP_FLAGS
);
4014 DISAS_INSN(rotate_mem
)
4019 int left
= (insn
& 0x100);
4021 SRC_EA(env
, src
, OS_WORD
, 0, &addr
);
4023 shift
= tcg_const_i32(1);
4024 if (insn
& 0x0200) {
4025 rotate(src
, shift
, left
, 16);
4027 TCGv X
= rotate_x(src
, shift
, left
, 16);
4028 rotate_x_flags(src
, X
, 16);
4031 tcg_temp_free(shift
);
4032 DEST_EA(env
, insn
, OS_WORD
, src
, &addr
);
4033 set_cc_op(s
, CC_OP_FLAGS
);
4036 DISAS_INSN(bfext_reg
)
4038 int ext
= read_im16(env
, s
);
4039 int is_sign
= insn
& 0x200;
4040 TCGv src
= DREG(insn
, 0);
4041 TCGv dst
= DREG(ext
, 12);
4042 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4043 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4044 int pos
= 32 - ofs
- len
; /* little bit-endian */
4045 TCGv tmp
= tcg_temp_new();
4049 * In general, we're going to rotate the field so that it's at the
4050 * top of the word and then right-shift by the complement of the
4051 * width to extend the field.
4054 /* Variable width. */
4056 /* Variable offset. */
4057 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4058 tcg_gen_rotl_i32(tmp
, src
, tmp
);
4060 tcg_gen_rotli_i32(tmp
, src
, ofs
);
4063 shift
= tcg_temp_new();
4064 tcg_gen_neg_i32(shift
, DREG(ext
, 0));
4065 tcg_gen_andi_i32(shift
, shift
, 31);
4066 tcg_gen_sar_i32(QREG_CC_N
, tmp
, shift
);
4068 tcg_gen_mov_i32(dst
, QREG_CC_N
);
4070 tcg_gen_shr_i32(dst
, tmp
, shift
);
4072 tcg_temp_free(shift
);
4074 /* Immediate width. */
4076 /* Variable offset */
4077 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4078 tcg_gen_rotl_i32(tmp
, src
, tmp
);
4083 * Immediate offset. If the field doesn't wrap around the
4084 * end of the word, rely on (s)extract completely.
4087 tcg_gen_rotli_i32(tmp
, src
, ofs
);
4093 tcg_gen_sextract_i32(QREG_CC_N
, src
, pos
, len
);
4095 tcg_gen_mov_i32(dst
, QREG_CC_N
);
4097 tcg_gen_extract_i32(dst
, src
, pos
, len
);
4102 set_cc_op(s
, CC_OP_LOGIC
);
4105 DISAS_INSN(bfext_mem
)
4107 int ext
= read_im16(env
, s
);
4108 int is_sign
= insn
& 0x200;
4109 TCGv dest
= DREG(ext
, 12);
4110 TCGv addr
, len
, ofs
;
4112 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4113 if (IS_NULL_QREG(addr
)) {
4121 len
= tcg_const_i32(extract32(ext
, 0, 5));
4126 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4130 gen_helper_bfexts_mem(dest
, cpu_env
, addr
, ofs
, len
);
4131 tcg_gen_mov_i32(QREG_CC_N
, dest
);
4133 TCGv_i64 tmp
= tcg_temp_new_i64();
4134 gen_helper_bfextu_mem(tmp
, cpu_env
, addr
, ofs
, len
);
4135 tcg_gen_extr_i64_i32(dest
, QREG_CC_N
, tmp
);
4136 tcg_temp_free_i64(tmp
);
4138 set_cc_op(s
, CC_OP_LOGIC
);
4140 if (!(ext
& 0x20)) {
4143 if (!(ext
& 0x800)) {
4148 DISAS_INSN(bfop_reg
)
4150 int ext
= read_im16(env
, s
);
4151 TCGv src
= DREG(insn
, 0);
4152 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4153 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4154 TCGv mask
, tofs
, tlen
;
4158 if ((insn
& 0x0f00) == 0x0d00) { /* bfffo */
4159 tofs
= tcg_temp_new();
4160 tlen
= tcg_temp_new();
4163 if ((ext
& 0x820) == 0) {
4164 /* Immediate width and offset. */
4165 uint32_t maski
= 0x7fffffffu
>> (len
- 1);
4166 if (ofs
+ len
<= 32) {
4167 tcg_gen_shli_i32(QREG_CC_N
, src
, ofs
);
4169 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4171 tcg_gen_andi_i32(QREG_CC_N
, QREG_CC_N
, ~maski
);
4172 mask
= tcg_const_i32(ror32(maski
, ofs
));
4174 tcg_gen_movi_i32(tofs
, ofs
);
4175 tcg_gen_movi_i32(tlen
, len
);
4178 TCGv tmp
= tcg_temp_new();
4180 /* Variable width */
4181 tcg_gen_subi_i32(tmp
, DREG(ext
, 0), 1);
4182 tcg_gen_andi_i32(tmp
, tmp
, 31);
4183 mask
= tcg_const_i32(0x7fffffffu
);
4184 tcg_gen_shr_i32(mask
, mask
, tmp
);
4186 tcg_gen_addi_i32(tlen
, tmp
, 1);
4189 /* Immediate width */
4190 mask
= tcg_const_i32(0x7fffffffu
>> (len
- 1));
4192 tcg_gen_movi_i32(tlen
, len
);
4196 /* Variable offset */
4197 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4198 tcg_gen_rotl_i32(QREG_CC_N
, src
, tmp
);
4199 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4200 tcg_gen_rotr_i32(mask
, mask
, tmp
);
4202 tcg_gen_mov_i32(tofs
, tmp
);
4205 /* Immediate offset (and variable width) */
4206 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4207 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4208 tcg_gen_rotri_i32(mask
, mask
, ofs
);
4210 tcg_gen_movi_i32(tofs
, ofs
);
4215 set_cc_op(s
, CC_OP_LOGIC
);
4217 switch (insn
& 0x0f00) {
4218 case 0x0a00: /* bfchg */
4219 tcg_gen_eqv_i32(src
, src
, mask
);
4221 case 0x0c00: /* bfclr */
4222 tcg_gen_and_i32(src
, src
, mask
);
4224 case 0x0d00: /* bfffo */
4225 gen_helper_bfffo_reg(DREG(ext
, 12), QREG_CC_N
, tofs
, tlen
);
4226 tcg_temp_free(tlen
);
4227 tcg_temp_free(tofs
);
4229 case 0x0e00: /* bfset */
4230 tcg_gen_orc_i32(src
, src
, mask
);
4232 case 0x0800: /* bftst */
4233 /* flags already set; no other work to do. */
4236 g_assert_not_reached();
4238 tcg_temp_free(mask
);
4241 DISAS_INSN(bfop_mem
)
4243 int ext
= read_im16(env
, s
);
4244 TCGv addr
, len
, ofs
;
4247 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4248 if (IS_NULL_QREG(addr
)) {
4256 len
= tcg_const_i32(extract32(ext
, 0, 5));
4261 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4264 switch (insn
& 0x0f00) {
4265 case 0x0a00: /* bfchg */
4266 gen_helper_bfchg_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4268 case 0x0c00: /* bfclr */
4269 gen_helper_bfclr_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4271 case 0x0d00: /* bfffo */
4272 t64
= tcg_temp_new_i64();
4273 gen_helper_bfffo_mem(t64
, cpu_env
, addr
, ofs
, len
);
4274 tcg_gen_extr_i64_i32(DREG(ext
, 12), QREG_CC_N
, t64
);
4275 tcg_temp_free_i64(t64
);
4277 case 0x0e00: /* bfset */
4278 gen_helper_bfset_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4280 case 0x0800: /* bftst */
4281 gen_helper_bfexts_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4284 g_assert_not_reached();
4286 set_cc_op(s
, CC_OP_LOGIC
);
4288 if (!(ext
& 0x20)) {
4291 if (!(ext
& 0x800)) {
4296 DISAS_INSN(bfins_reg
)
4298 int ext
= read_im16(env
, s
);
4299 TCGv dst
= DREG(insn
, 0);
4300 TCGv src
= DREG(ext
, 12);
4301 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4302 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4303 int pos
= 32 - ofs
- len
; /* little bit-endian */
4306 tmp
= tcg_temp_new();
4309 /* Variable width */
4310 tcg_gen_neg_i32(tmp
, DREG(ext
, 0));
4311 tcg_gen_andi_i32(tmp
, tmp
, 31);
4312 tcg_gen_shl_i32(QREG_CC_N
, src
, tmp
);
4314 /* Immediate width */
4315 tcg_gen_shli_i32(QREG_CC_N
, src
, 32 - len
);
4317 set_cc_op(s
, CC_OP_LOGIC
);
4319 /* Immediate width and offset */
4320 if ((ext
& 0x820) == 0) {
4321 /* Check for suitability for deposit. */
4323 tcg_gen_deposit_i32(dst
, dst
, src
, pos
, len
);
4325 uint32_t maski
= -2U << (len
- 1);
4326 uint32_t roti
= (ofs
+ len
) & 31;
4327 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4328 tcg_gen_rotri_i32(tmp
, tmp
, roti
);
4329 tcg_gen_andi_i32(dst
, dst
, ror32(maski
, roti
));
4330 tcg_gen_or_i32(dst
, dst
, tmp
);
4333 TCGv mask
= tcg_temp_new();
4334 TCGv rot
= tcg_temp_new();
4337 /* Variable width */
4338 tcg_gen_subi_i32(rot
, DREG(ext
, 0), 1);
4339 tcg_gen_andi_i32(rot
, rot
, 31);
4340 tcg_gen_movi_i32(mask
, -2);
4341 tcg_gen_shl_i32(mask
, mask
, rot
);
4342 tcg_gen_mov_i32(rot
, DREG(ext
, 0));
4343 tcg_gen_andc_i32(tmp
, src
, mask
);
4345 /* Immediate width (variable offset) */
4346 uint32_t maski
= -2U << (len
- 1);
4347 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4348 tcg_gen_movi_i32(mask
, maski
);
4349 tcg_gen_movi_i32(rot
, len
& 31);
4352 /* Variable offset */
4353 tcg_gen_add_i32(rot
, rot
, DREG(ext
, 6));
4355 /* Immediate offset (variable width) */
4356 tcg_gen_addi_i32(rot
, rot
, ofs
);
4358 tcg_gen_andi_i32(rot
, rot
, 31);
4359 tcg_gen_rotr_i32(mask
, mask
, rot
);
4360 tcg_gen_rotr_i32(tmp
, tmp
, rot
);
4361 tcg_gen_and_i32(dst
, dst
, mask
);
4362 tcg_gen_or_i32(dst
, dst
, tmp
);
4365 tcg_temp_free(mask
);
4370 DISAS_INSN(bfins_mem
)
4372 int ext
= read_im16(env
, s
);
4373 TCGv src
= DREG(ext
, 12);
4374 TCGv addr
, len
, ofs
;
4376 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4377 if (IS_NULL_QREG(addr
)) {
4385 len
= tcg_const_i32(extract32(ext
, 0, 5));
4390 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4393 gen_helper_bfins_mem(QREG_CC_N
, cpu_env
, addr
, src
, ofs
, len
);
4394 set_cc_op(s
, CC_OP_LOGIC
);
4396 if (!(ext
& 0x20)) {
4399 if (!(ext
& 0x800)) {
4407 reg
= DREG(insn
, 0);
4408 gen_logic_cc(s
, reg
, OS_LONG
);
4409 gen_helper_ff1(reg
, reg
);
4417 switch ((insn
>> 7) & 3) {
4422 if (m68k_feature(env
, M68K_FEATURE_CHK2
)) {
4428 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4431 SRC_EA(env
, src
, opsize
, 1, NULL
);
4432 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
4435 gen_helper_chk(cpu_env
, reg
, src
);
4441 TCGv addr1
, addr2
, bound1
, bound2
, reg
;
4444 switch ((insn
>> 9) & 3) {
4455 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4459 ext
= read_im16(env
, s
);
4460 if ((ext
& 0x0800) == 0) {
4461 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4465 addr1
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4466 addr2
= tcg_temp_new();
4467 tcg_gen_addi_i32(addr2
, addr1
, opsize_bytes(opsize
));
4469 bound1
= gen_load(s
, opsize
, addr1
, 1, IS_USER(s
));
4470 tcg_temp_free(addr1
);
4471 bound2
= gen_load(s
, opsize
, addr2
, 1, IS_USER(s
));
4472 tcg_temp_free(addr2
);
4474 reg
= tcg_temp_new();
4476 tcg_gen_mov_i32(reg
, AREG(ext
, 12));
4478 gen_ext(reg
, DREG(ext
, 12), opsize
, 1);
4482 gen_helper_chk2(cpu_env
, reg
, bound1
, bound2
);
4484 tcg_temp_free(bound1
);
4485 tcg_temp_free(bound2
);
4488 static void m68k_copy_line(TCGv dst
, TCGv src
, int index
)
4493 addr
= tcg_temp_new();
4495 t0
= tcg_temp_new_i64();
4496 t1
= tcg_temp_new_i64();
4498 tcg_gen_andi_i32(addr
, src
, ~15);
4499 tcg_gen_qemu_ld64(t0
, addr
, index
);
4500 tcg_gen_addi_i32(addr
, addr
, 8);
4501 tcg_gen_qemu_ld64(t1
, addr
, index
);
4503 tcg_gen_andi_i32(addr
, dst
, ~15);
4504 tcg_gen_qemu_st64(t0
, addr
, index
);
4505 tcg_gen_addi_i32(addr
, addr
, 8);
4506 tcg_gen_qemu_st64(t1
, addr
, index
);
4508 tcg_temp_free_i64(t0
);
4509 tcg_temp_free_i64(t1
);
4510 tcg_temp_free(addr
);
4513 DISAS_INSN(move16_reg
)
4515 int index
= IS_USER(s
);
4519 ext
= read_im16(env
, s
);
4520 if ((ext
& (1 << 15)) == 0) {
4521 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4524 m68k_copy_line(AREG(ext
, 12), AREG(insn
, 0), index
);
4526 /* Ax can be Ay, so save Ay before incrementing Ax */
4527 tmp
= tcg_temp_new();
4528 tcg_gen_mov_i32(tmp
, AREG(ext
, 12));
4529 tcg_gen_addi_i32(AREG(insn
, 0), AREG(insn
, 0), 16);
4530 tcg_gen_addi_i32(AREG(ext
, 12), tmp
, 16);
4534 DISAS_INSN(move16_mem
)
4536 int index
= IS_USER(s
);
4539 reg
= AREG(insn
, 0);
4540 addr
= tcg_const_i32(read_im32(env
, s
));
4542 if ((insn
>> 3) & 1) {
4543 /* MOVE16 (xxx).L, (Ay) */
4544 m68k_copy_line(reg
, addr
, index
);
4546 /* MOVE16 (Ay), (xxx).L */
4547 m68k_copy_line(addr
, reg
, index
);
4550 tcg_temp_free(addr
);
4552 if (((insn
>> 3) & 2) == 0) {
4554 tcg_gen_addi_i32(reg
, reg
, 16);
4564 ext
= read_im16(env
, s
);
4565 if (ext
!= 0x46FC) {
4566 gen_exception(s
, addr
, EXCP_ILLEGAL
);
4569 ext
= read_im16(env
, s
);
4570 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
4571 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
4574 gen_push(s
, gen_get_sr(s
));
4575 gen_set_sr_im(s
, ext
, 0);
4579 DISAS_INSN(move_from_sr
)
4583 if (IS_USER(s
) && m68k_feature(env
, M68K_FEATURE_MOVEFROMSR_PRIV
)) {
4584 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4588 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
4591 #if defined(CONFIG_SOFTMMU)
4601 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4605 ext
= read_im16(env
, s
);
4607 opsize
= insn_opsize(insn
);
4610 /* address register */
4611 reg
= AREG(ext
, 12);
4615 reg
= DREG(ext
, 12);
4619 addr
= gen_lea(env
, s
, insn
, opsize
);
4620 if (IS_NULL_QREG(addr
)) {
4626 /* from reg to ea */
4627 gen_store(s
, opsize
, addr
, reg
, DFC_INDEX(s
));
4629 /* from ea to reg */
4630 TCGv tmp
= gen_load(s
, opsize
, addr
, 0, SFC_INDEX(s
));
4632 gen_ext(reg
, tmp
, opsize
, 1);
4634 gen_partset_reg(opsize
, reg
, tmp
);
4638 switch (extract32(insn
, 3, 3)) {
4639 case 3: /* Indirect postincrement. */
4640 tcg_gen_addi_i32(AREG(insn
, 0), addr
,
4641 REG(insn
, 0) == 7 && opsize
== OS_BYTE
4643 : opsize_bytes(opsize
));
4645 case 4: /* Indirect predecrememnt. */
4646 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4651 DISAS_INSN(move_to_sr
)
4654 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4657 gen_move_to_sr(env
, s
, insn
, false);
4661 DISAS_INSN(move_from_usp
)
4664 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4667 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
4668 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4671 DISAS_INSN(move_to_usp
)
4674 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4677 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
4678 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4684 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4688 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
4696 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4700 ext
= read_im16(env
, s
);
4702 gen_set_sr_im(s
, ext
, 0);
4703 tcg_gen_movi_i32(cpu_halted
, 1);
4704 gen_exception(s
, s
->pc
, EXCP_HLT
);
4710 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4713 gen_exception(s
, s
->base
.pc_next
, EXCP_RTE
);
4716 DISAS_INSN(cf_movec
)
4722 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4726 ext
= read_im16(env
, s
);
4729 reg
= AREG(ext
, 12);
4731 reg
= DREG(ext
, 12);
4733 gen_helper_cf_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4737 DISAS_INSN(m68k_movec
)
4743 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4747 ext
= read_im16(env
, s
);
4750 reg
= AREG(ext
, 12);
4752 reg
= DREG(ext
, 12);
4755 gen_helper_m68k_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4757 gen_helper_m68k_movec_from(reg
, cpu_env
, tcg_const_i32(ext
& 0xfff));
4765 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4768 /* ICache fetch. Implement as no-op. */
4774 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4777 /* Cache push/invalidate. Implement as no-op. */
4783 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4786 /* Cache push/invalidate. Implement as no-op. */
4792 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4795 /* Invalidate cache line. Implement as no-op. */
4798 #if defined(CONFIG_SOFTMMU)
4804 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4808 opmode
= tcg_const_i32((insn
>> 3) & 3);
4809 gen_helper_pflush(cpu_env
, AREG(insn
, 0), opmode
);
4810 tcg_temp_free(opmode
);
4818 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4821 is_read
= tcg_const_i32((insn
>> 5) & 1);
4822 gen_helper_ptest(cpu_env
, AREG(insn
, 0), is_read
);
4823 tcg_temp_free(is_read
);
4829 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4835 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4838 /* TODO: Implement wdebug. */
4839 cpu_abort(env_cpu(env
), "WDEBUG not implemented");
4845 gen_exception(s
, s
->pc
, EXCP_TRAP0
+ (insn
& 0xf));
4848 static void do_trapcc(DisasContext
*s
, DisasCompare
*c
)
4850 if (c
->tcond
!= TCG_COND_NEVER
) {
4851 TCGLabel
*over
= NULL
;
4855 if (c
->tcond
!= TCG_COND_ALWAYS
) {
4856 /* Jump over if !c. */
4857 over
= gen_new_label();
4858 tcg_gen_brcond_i32(tcg_invert_cond(c
->tcond
), c
->v1
, c
->v2
, over
);
4861 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
4862 gen_raise_exception_format2(s
, EXCP_TRAPCC
, s
->base
.pc_next
);
4865 gen_set_label(over
);
4866 s
->base
.is_jmp
= DISAS_NEXT
;
4875 /* Consume and discard the immediate operand. */
4876 switch (extract32(insn
, 0, 3)) {
4877 case 2: /* trapcc.w */
4878 (void)read_im16(env
, s
);
4880 case 3: /* trapcc.l */
4881 (void)read_im32(env
, s
);
4883 case 4: /* trapcc (no operand) */
4886 /* trapcc registered with only valid opmodes */
4887 g_assert_not_reached();
4890 gen_cc_cond(&c
, s
, extract32(insn
, 8, 4));
4898 gen_cc_cond(&c
, s
, 9); /* V set */
4902 static void gen_load_fcr(DisasContext
*s
, TCGv res
, int reg
)
4906 tcg_gen_movi_i32(res
, 0);
4909 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4912 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpcr
));
4917 static void gen_store_fcr(DisasContext
*s
, TCGv val
, int reg
)
4923 tcg_gen_st_i32(val
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4926 gen_helper_set_fpcr(cpu_env
, val
);
4931 static void gen_qemu_store_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4933 int index
= IS_USER(s
);
4936 tmp
= tcg_temp_new();
4937 gen_load_fcr(s
, tmp
, reg
);
4938 tcg_gen_qemu_st32(tmp
, addr
, index
);
4942 static void gen_qemu_load_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4944 int index
= IS_USER(s
);
4947 tmp
= tcg_temp_new();
4948 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
4949 gen_store_fcr(s
, tmp
, reg
);
4954 static void gen_op_fmove_fcr(CPUM68KState
*env
, DisasContext
*s
,
4955 uint32_t insn
, uint32_t ext
)
4957 int mask
= (ext
>> 10) & 7;
4958 int is_write
= (ext
>> 13) & 1;
4959 int mode
= extract32(insn
, 3, 3);
4965 if (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&& mask
!= M68K_FPCR
) {
4966 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4970 gen_load_fcr(s
, DREG(insn
, 0), mask
);
4972 gen_store_fcr(s
, DREG(insn
, 0), mask
);
4975 case 1: /* An, only with FPIAR */
4976 if (mask
!= M68K_FPIAR
) {
4977 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4981 gen_load_fcr(s
, AREG(insn
, 0), mask
);
4983 gen_store_fcr(s
, AREG(insn
, 0), mask
);
4986 case 7: /* Immediate */
4987 if (REG(insn
, 0) == 4) {
4989 (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&&
4990 mask
!= M68K_FPCR
)) {
4991 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4994 tmp
= tcg_const_i32(read_im32(env
, s
));
4995 gen_store_fcr(s
, tmp
, mask
);
5004 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
5005 if (IS_NULL_QREG(tmp
)) {
5010 addr
= tcg_temp_new();
5011 tcg_gen_mov_i32(addr
, tmp
);
5016 * 0b100 Floating-Point Control Register
5017 * 0b010 Floating-Point Status Register
5018 * 0b001 Floating-Point Instruction Address Register
5022 if (is_write
&& mode
== 4) {
5023 for (i
= 2; i
>= 0; i
--, mask
>>= 1) {
5025 gen_qemu_store_fcr(s
, addr
, 1 << i
);
5027 tcg_gen_subi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
5031 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5033 for (i
= 0; i
< 3; i
++, mask
>>= 1) {
5036 gen_qemu_store_fcr(s
, addr
, 1 << i
);
5038 gen_qemu_load_fcr(s
, addr
, 1 << i
);
5040 if (mask
!= 1 || mode
== 3) {
5041 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
5046 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5049 tcg_temp_free_i32(addr
);
5052 static void gen_op_fmovem(CPUM68KState
*env
, DisasContext
*s
,
5053 uint32_t insn
, uint32_t ext
)
5057 int mode
= (ext
>> 11) & 0x3;
5058 int is_load
= ((ext
& 0x2000) == 0);
5060 if (m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
5061 opsize
= OS_EXTENDED
;
5063 opsize
= OS_DOUBLE
; /* FIXME */
5066 addr
= gen_lea(env
, s
, insn
, opsize
);
5067 if (IS_NULL_QREG(addr
)) {
5072 tmp
= tcg_temp_new();
5074 /* Dynamic register list */
5075 tcg_gen_ext8u_i32(tmp
, DREG(ext
, 4));
5077 /* Static register list */
5078 tcg_gen_movi_i32(tmp
, ext
& 0xff);
5081 if (!is_load
&& (mode
& 2) == 0) {
5083 * predecrement addressing mode
5084 * only available to store register to memory
5086 if (opsize
== OS_EXTENDED
) {
5087 gen_helper_fmovemx_st_predec(tmp
, cpu_env
, addr
, tmp
);
5089 gen_helper_fmovemd_st_predec(tmp
, cpu_env
, addr
, tmp
);
5092 /* postincrement addressing mode */
5093 if (opsize
== OS_EXTENDED
) {
5095 gen_helper_fmovemx_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
5097 gen_helper_fmovemx_st_postinc(tmp
, cpu_env
, addr
, tmp
);
5101 gen_helper_fmovemd_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
5103 gen_helper_fmovemd_st_postinc(tmp
, cpu_env
, addr
, tmp
);
5107 if ((insn
& 070) == 030 || (insn
& 070) == 040) {
5108 tcg_gen_mov_i32(AREG(insn
, 0), tmp
);
5114 * ??? FP exceptions are not implemented. Most exceptions are deferred until
5115 * immediately before the next FP instruction is executed.
5122 TCGv_ptr cpu_src
, cpu_dest
;
5124 ext
= read_im16(env
, s
);
5125 opmode
= ext
& 0x7f;
5126 switch ((ext
>> 13) & 7) {
5132 if (insn
== 0xf200 && (ext
& 0xfc00) == 0x5c00) {
5134 TCGv rom_offset
= tcg_const_i32(opmode
);
5135 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
5136 gen_helper_fconst(cpu_env
, cpu_dest
, rom_offset
);
5137 tcg_temp_free_ptr(cpu_dest
);
5138 tcg_temp_free(rom_offset
);
5142 case 3: /* fmove out */
5143 cpu_src
= gen_fp_ptr(REG(ext
, 7));
5144 opsize
= ext_opsize(ext
, 10);
5145 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
,
5146 EA_STORE
, IS_USER(s
)) == -1) {
5149 gen_helper_ftst(cpu_env
, cpu_src
);
5150 tcg_temp_free_ptr(cpu_src
);
5152 case 4: /* fmove to control register. */
5153 case 5: /* fmove from control register. */
5154 gen_op_fmove_fcr(env
, s
, insn
, ext
);
5156 case 6: /* fmovem */
5158 if ((ext
& 0x1000) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
5161 gen_op_fmovem(env
, s
, insn
, ext
);
5164 if (ext
& (1 << 14)) {
5165 /* Source effective address. */
5166 opsize
= ext_opsize(ext
, 10);
5167 cpu_src
= gen_fp_result_ptr();
5168 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
,
5169 EA_LOADS
, IS_USER(s
)) == -1) {
5174 /* Source register. */
5175 opsize
= OS_EXTENDED
;
5176 cpu_src
= gen_fp_ptr(REG(ext
, 10));
5178 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
5181 gen_fp_move(cpu_dest
, cpu_src
);
5183 case 0x40: /* fsmove */
5184 gen_helper_fsround(cpu_env
, cpu_dest
, cpu_src
);
5186 case 0x44: /* fdmove */
5187 gen_helper_fdround(cpu_env
, cpu_dest
, cpu_src
);
5190 gen_helper_firound(cpu_env
, cpu_dest
, cpu_src
);
5193 gen_helper_fsinh(cpu_env
, cpu_dest
, cpu_src
);
5195 case 3: /* fintrz */
5196 gen_helper_fitrunc(cpu_env
, cpu_dest
, cpu_src
);
5199 gen_helper_fsqrt(cpu_env
, cpu_dest
, cpu_src
);
5201 case 0x41: /* fssqrt */
5202 gen_helper_fssqrt(cpu_env
, cpu_dest
, cpu_src
);
5204 case 0x45: /* fdsqrt */
5205 gen_helper_fdsqrt(cpu_env
, cpu_dest
, cpu_src
);
5207 case 0x06: /* flognp1 */
5208 gen_helper_flognp1(cpu_env
, cpu_dest
, cpu_src
);
5210 case 0x08: /* fetoxm1 */
5211 gen_helper_fetoxm1(cpu_env
, cpu_dest
, cpu_src
);
5213 case 0x09: /* ftanh */
5214 gen_helper_ftanh(cpu_env
, cpu_dest
, cpu_src
);
5216 case 0x0a: /* fatan */
5217 gen_helper_fatan(cpu_env
, cpu_dest
, cpu_src
);
5219 case 0x0c: /* fasin */
5220 gen_helper_fasin(cpu_env
, cpu_dest
, cpu_src
);
5222 case 0x0d: /* fatanh */
5223 gen_helper_fatanh(cpu_env
, cpu_dest
, cpu_src
);
5225 case 0x0e: /* fsin */
5226 gen_helper_fsin(cpu_env
, cpu_dest
, cpu_src
);
5228 case 0x0f: /* ftan */
5229 gen_helper_ftan(cpu_env
, cpu_dest
, cpu_src
);
5231 case 0x10: /* fetox */
5232 gen_helper_fetox(cpu_env
, cpu_dest
, cpu_src
);
5234 case 0x11: /* ftwotox */
5235 gen_helper_ftwotox(cpu_env
, cpu_dest
, cpu_src
);
5237 case 0x12: /* ftentox */
5238 gen_helper_ftentox(cpu_env
, cpu_dest
, cpu_src
);
5240 case 0x14: /* flogn */
5241 gen_helper_flogn(cpu_env
, cpu_dest
, cpu_src
);
5243 case 0x15: /* flog10 */
5244 gen_helper_flog10(cpu_env
, cpu_dest
, cpu_src
);
5246 case 0x16: /* flog2 */
5247 gen_helper_flog2(cpu_env
, cpu_dest
, cpu_src
);
5249 case 0x18: /* fabs */
5250 gen_helper_fabs(cpu_env
, cpu_dest
, cpu_src
);
5252 case 0x58: /* fsabs */
5253 gen_helper_fsabs(cpu_env
, cpu_dest
, cpu_src
);
5255 case 0x5c: /* fdabs */
5256 gen_helper_fdabs(cpu_env
, cpu_dest
, cpu_src
);
5258 case 0x19: /* fcosh */
5259 gen_helper_fcosh(cpu_env
, cpu_dest
, cpu_src
);
5261 case 0x1a: /* fneg */
5262 gen_helper_fneg(cpu_env
, cpu_dest
, cpu_src
);
5264 case 0x5a: /* fsneg */
5265 gen_helper_fsneg(cpu_env
, cpu_dest
, cpu_src
);
5267 case 0x5e: /* fdneg */
5268 gen_helper_fdneg(cpu_env
, cpu_dest
, cpu_src
);
5270 case 0x1c: /* facos */
5271 gen_helper_facos(cpu_env
, cpu_dest
, cpu_src
);
5273 case 0x1d: /* fcos */
5274 gen_helper_fcos(cpu_env
, cpu_dest
, cpu_src
);
5276 case 0x1e: /* fgetexp */
5277 gen_helper_fgetexp(cpu_env
, cpu_dest
, cpu_src
);
5279 case 0x1f: /* fgetman */
5280 gen_helper_fgetman(cpu_env
, cpu_dest
, cpu_src
);
5282 case 0x20: /* fdiv */
5283 gen_helper_fdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5285 case 0x60: /* fsdiv */
5286 gen_helper_fsdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5288 case 0x64: /* fddiv */
5289 gen_helper_fddiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5291 case 0x21: /* fmod */
5292 gen_helper_fmod(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5294 case 0x22: /* fadd */
5295 gen_helper_fadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5297 case 0x62: /* fsadd */
5298 gen_helper_fsadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5300 case 0x66: /* fdadd */
5301 gen_helper_fdadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5303 case 0x23: /* fmul */
5304 gen_helper_fmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5306 case 0x63: /* fsmul */
5307 gen_helper_fsmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5309 case 0x67: /* fdmul */
5310 gen_helper_fdmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5312 case 0x24: /* fsgldiv */
5313 gen_helper_fsgldiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5315 case 0x25: /* frem */
5316 gen_helper_frem(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5318 case 0x26: /* fscale */
5319 gen_helper_fscale(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5321 case 0x27: /* fsglmul */
5322 gen_helper_fsglmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5324 case 0x28: /* fsub */
5325 gen_helper_fsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5327 case 0x68: /* fssub */
5328 gen_helper_fssub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5330 case 0x6c: /* fdsub */
5331 gen_helper_fdsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5333 case 0x30: case 0x31: case 0x32:
5334 case 0x33: case 0x34: case 0x35:
5335 case 0x36: case 0x37: {
5336 TCGv_ptr cpu_dest2
= gen_fp_ptr(REG(ext
, 0));
5337 gen_helper_fsincos(cpu_env
, cpu_dest
, cpu_dest2
, cpu_src
);
5338 tcg_temp_free_ptr(cpu_dest2
);
5341 case 0x38: /* fcmp */
5342 gen_helper_fcmp(cpu_env
, cpu_src
, cpu_dest
);
5344 case 0x3a: /* ftst */
5345 gen_helper_ftst(cpu_env
, cpu_src
);
5350 tcg_temp_free_ptr(cpu_src
);
5351 gen_helper_ftst(cpu_env
, cpu_dest
);
5352 tcg_temp_free_ptr(cpu_dest
);
5355 /* FIXME: Is this right for offset addressing modes? */
5357 disas_undef_fpu(env
, s
, insn
);
5360 static void gen_fcc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
5364 c
->v2
= tcg_const_i32(0);
5365 /* TODO: Raise BSUN exception. */
5366 fpsr
= tcg_temp_new();
5367 gen_load_fcr(s
, fpsr
, M68K_FPSR
);
5370 case 16: /* Signaling False */
5372 c
->tcond
= TCG_COND_NEVER
;
5374 case 1: /* EQual Z */
5375 case 17: /* Signaling EQual Z */
5376 c
->v1
= tcg_temp_new();
5377 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5378 c
->tcond
= TCG_COND_NE
;
5380 case 2: /* Ordered Greater Than !(A || Z || N) */
5381 case 18: /* Greater Than !(A || Z || N) */
5382 c
->v1
= tcg_temp_new();
5383 tcg_gen_andi_i32(c
->v1
, fpsr
,
5384 FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5385 c
->tcond
= TCG_COND_EQ
;
5387 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
5388 case 19: /* Greater than or Equal Z || !(A || N) */
5389 c
->v1
= tcg_temp_new();
5390 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5391 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5392 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_Z
| FPSR_CC_N
);
5393 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5394 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5395 c
->tcond
= TCG_COND_NE
;
5397 case 4: /* Ordered Less Than !(!N || A || Z); */
5398 case 20: /* Less Than !(!N || A || Z); */
5399 c
->v1
= tcg_temp_new();
5400 tcg_gen_xori_i32(c
->v1
, fpsr
, FPSR_CC_N
);
5401 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_N
| FPSR_CC_A
| FPSR_CC_Z
);
5402 c
->tcond
= TCG_COND_EQ
;
5404 case 5: /* Ordered Less than or Equal Z || (N && !A) */
5405 case 21: /* Less than or Equal Z || (N && !A) */
5406 c
->v1
= tcg_temp_new();
5407 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5408 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5409 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5410 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_Z
| FPSR_CC_N
);
5411 c
->tcond
= TCG_COND_NE
;
5413 case 6: /* Ordered Greater or Less than !(A || Z) */
5414 case 22: /* Greater or Less than !(A || Z) */
5415 c
->v1
= tcg_temp_new();
5416 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5417 c
->tcond
= TCG_COND_EQ
;
5419 case 7: /* Ordered !A */
5420 case 23: /* Greater, Less or Equal !A */
5421 c
->v1
= tcg_temp_new();
5422 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5423 c
->tcond
= TCG_COND_EQ
;
5425 case 8: /* Unordered A */
5426 case 24: /* Not Greater, Less or Equal A */
5427 c
->v1
= tcg_temp_new();
5428 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5429 c
->tcond
= TCG_COND_NE
;
5431 case 9: /* Unordered or Equal A || Z */
5432 case 25: /* Not Greater or Less then A || Z */
5433 c
->v1
= tcg_temp_new();
5434 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5435 c
->tcond
= TCG_COND_NE
;
5437 case 10: /* Unordered or Greater Than A || !(N || Z)) */
5438 case 26: /* Not Less or Equal A || !(N || Z)) */
5439 c
->v1
= tcg_temp_new();
5440 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5441 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5442 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_A
| FPSR_CC_N
);
5443 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5444 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5445 c
->tcond
= TCG_COND_NE
;
5447 case 11: /* Unordered or Greater or Equal A || Z || !N */
5448 case 27: /* Not Less Than A || Z || !N */
5449 c
->v1
= tcg_temp_new();
5450 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5451 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5452 c
->tcond
= TCG_COND_NE
;
5454 case 12: /* Unordered or Less Than A || (N && !Z) */
5455 case 28: /* Not Greater than or Equal A || (N && !Z) */
5456 c
->v1
= tcg_temp_new();
5457 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5458 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5459 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5460 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_A
| FPSR_CC_N
);
5461 c
->tcond
= TCG_COND_NE
;
5463 case 13: /* Unordered or Less or Equal A || Z || N */
5464 case 29: /* Not Greater Than A || Z || N */
5465 c
->v1
= tcg_temp_new();
5466 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5467 c
->tcond
= TCG_COND_NE
;
5469 case 14: /* Not Equal !Z */
5470 case 30: /* Signaling Not Equal !Z */
5471 c
->v1
= tcg_temp_new();
5472 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5473 c
->tcond
= TCG_COND_EQ
;
5476 case 31: /* Signaling True */
5478 c
->tcond
= TCG_COND_ALWAYS
;
5481 tcg_temp_free(fpsr
);
5484 static void gen_fjmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
5488 gen_fcc_cond(&c
, s
, cond
);
5490 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
5500 offset
= (int16_t)read_im16(env
, s
);
5501 if (insn
& (1 << 6)) {
5502 offset
= (offset
<< 16) | read_im16(env
, s
);
5505 l1
= gen_new_label();
5507 gen_fjmpcc(s
, insn
& 0x3f, l1
);
5508 gen_jmp_tb(s
, 0, s
->pc
, s
->base
.pc_next
);
5510 gen_jmp_tb(s
, 1, base
+ offset
, s
->base
.pc_next
);
5520 ext
= read_im16(env
, s
);
5522 gen_fcc_cond(&c
, s
, cond
);
5524 tmp
= tcg_temp_new();
5525 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
5527 tcg_gen_neg_i32(tmp
, tmp
);
5528 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
5538 ext
= read_im16(env
, s
);
5541 /* Consume and discard the immediate operand. */
5542 switch (extract32(insn
, 0, 3)) {
5543 case 2: /* ftrapcc.w */
5544 (void)read_im16(env
, s
);
5546 case 3: /* ftrapcc.l */
5547 (void)read_im32(env
, s
);
5549 case 4: /* ftrapcc (no operand) */
5552 /* ftrapcc registered with only valid opmodes */
5553 g_assert_not_reached();
5556 gen_fcc_cond(&c
, s
, cond
);
5560 #if defined(CONFIG_SOFTMMU)
5561 DISAS_INSN(frestore
)
5566 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
5569 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5570 SRC_EA(env
, addr
, OS_LONG
, 0, NULL
);
5571 /* FIXME: check the state frame */
5573 disas_undef(env
, s
, insn
);
5580 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
5584 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5585 /* always write IDLE */
5586 TCGv idle
= tcg_const_i32(0x41000000);
5587 DEST_EA(env
, insn
, OS_LONG
, idle
, NULL
);
5588 tcg_temp_free(idle
);
5590 disas_undef(env
, s
, insn
);
5595 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
5597 TCGv tmp
= tcg_temp_new();
5598 if (s
->env
->macsr
& MACSR_FI
) {
5600 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
5602 tcg_gen_shli_i32(tmp
, val
, 16);
5603 } else if (s
->env
->macsr
& MACSR_SU
) {
5605 tcg_gen_sari_i32(tmp
, val
, 16);
5607 tcg_gen_ext16s_i32(tmp
, val
);
5610 tcg_gen_shri_i32(tmp
, val
, 16);
5612 tcg_gen_ext16u_i32(tmp
, val
);
5617 static void gen_mac_clear_flags(void)
5619 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
5620 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
5636 s
->mactmp
= tcg_temp_new_i64();
5640 ext
= read_im16(env
, s
);
5642 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
5643 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
5644 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
5645 disas_undef(env
, s
, insn
);
5649 /* MAC with load. */
5650 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
5651 addr
= tcg_temp_new();
5652 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
5654 * Load the value now to ensure correct exception behavior.
5655 * Perform writeback after reading the MAC inputs.
5657 loadval
= gen_load(s
, OS_LONG
, addr
, 0, IS_USER(s
));
5660 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
5661 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
5663 loadval
= addr
= NULL_QREG
;
5664 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5665 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5668 gen_mac_clear_flags();
5671 /* Disabled because conditional branches clobber temporary vars. */
5672 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
5673 /* Skip the multiply if we know we will ignore it. */
5674 l1
= gen_new_label();
5675 tmp
= tcg_temp_new();
5676 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
5677 gen_op_jmp_nz32(tmp
, l1
);
5681 if ((ext
& 0x0800) == 0) {
5683 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
5684 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
5686 if (s
->env
->macsr
& MACSR_FI
) {
5687 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
5689 if (s
->env
->macsr
& MACSR_SU
)
5690 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
5692 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
5693 switch ((ext
>> 9) & 3) {
5695 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
5698 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
5704 /* Save the overflow flag from the multiply. */
5705 saved_flags
= tcg_temp_new();
5706 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
5708 saved_flags
= NULL_QREG
;
5712 /* Disabled because conditional branches clobber temporary vars. */
5713 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
5714 /* Skip the accumulate if the value is already saturated. */
5715 l1
= gen_new_label();
5716 tmp
= tcg_temp_new();
5717 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5718 gen_op_jmp_nz32(tmp
, l1
);
5723 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5725 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5727 if (s
->env
->macsr
& MACSR_FI
)
5728 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5729 else if (s
->env
->macsr
& MACSR_SU
)
5730 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5732 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5735 /* Disabled because conditional branches clobber temporary vars. */
5741 /* Dual accumulate variant. */
5742 acc
= (ext
>> 2) & 3;
5743 /* Restore the overflow flag from the multiplier. */
5744 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
5746 /* Disabled because conditional branches clobber temporary vars. */
5747 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
5748 /* Skip the accumulate if the value is already saturated. */
5749 l1
= gen_new_label();
5750 tmp
= tcg_temp_new();
5751 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5752 gen_op_jmp_nz32(tmp
, l1
);
5756 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5758 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5759 if (s
->env
->macsr
& MACSR_FI
)
5760 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5761 else if (s
->env
->macsr
& MACSR_SU
)
5762 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5764 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5766 /* Disabled because conditional branches clobber temporary vars. */
5771 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
5775 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5776 tcg_gen_mov_i32(rw
, loadval
);
5778 * FIXME: Should address writeback happen with the masked or
5781 switch ((insn
>> 3) & 7) {
5782 case 3: /* Post-increment. */
5783 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
5785 case 4: /* Pre-decrement. */
5786 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5788 tcg_temp_free(loadval
);
5792 DISAS_INSN(from_mac
)
5798 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5799 accnum
= (insn
>> 9) & 3;
5800 acc
= MACREG(accnum
);
5801 if (s
->env
->macsr
& MACSR_FI
) {
5802 gen_helper_get_macf(rx
, cpu_env
, acc
);
5803 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
5804 tcg_gen_extrl_i64_i32(rx
, acc
);
5805 } else if (s
->env
->macsr
& MACSR_SU
) {
5806 gen_helper_get_macs(rx
, acc
);
5808 gen_helper_get_macu(rx
, acc
);
5811 tcg_gen_movi_i64(acc
, 0);
5812 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5816 DISAS_INSN(move_mac
)
5818 /* FIXME: This can be done without a helper. */
5822 dest
= tcg_const_i32((insn
>> 9) & 3);
5823 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
5824 gen_mac_clear_flags();
5825 gen_helper_mac_set_flags(cpu_env
, dest
);
5828 DISAS_INSN(from_macsr
)
5832 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5833 tcg_gen_mov_i32(reg
, QREG_MACSR
);
5836 DISAS_INSN(from_mask
)
5839 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5840 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
5843 DISAS_INSN(from_mext
)
5847 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5848 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5849 if (s
->env
->macsr
& MACSR_FI
)
5850 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
5852 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
5855 DISAS_INSN(macsr_to_ccr
)
5857 TCGv tmp
= tcg_temp_new();
5859 /* Note that X and C are always cleared. */
5860 tcg_gen_andi_i32(tmp
, QREG_MACSR
, CCF_N
| CCF_Z
| CCF_V
);
5861 gen_helper_set_ccr(cpu_env
, tmp
);
5863 set_cc_op(s
, CC_OP_FLAGS
);
5871 accnum
= (insn
>> 9) & 3;
5872 acc
= MACREG(accnum
);
5873 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5874 if (s
->env
->macsr
& MACSR_FI
) {
5875 tcg_gen_ext_i32_i64(acc
, val
);
5876 tcg_gen_shli_i64(acc
, acc
, 8);
5877 } else if (s
->env
->macsr
& MACSR_SU
) {
5878 tcg_gen_ext_i32_i64(acc
, val
);
5880 tcg_gen_extu_i32_i64(acc
, val
);
5882 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5883 gen_mac_clear_flags();
5884 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
5887 DISAS_INSN(to_macsr
)
5890 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5891 gen_helper_set_macsr(cpu_env
, val
);
5898 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5899 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
5906 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5907 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5908 if (s
->env
->macsr
& MACSR_FI
)
5909 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
5910 else if (s
->env
->macsr
& MACSR_SU
)
5911 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
5913 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
5916 static disas_proc opcode_table
[65536];
5919 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
5925 /* Sanity check. All set bits must be included in the mask. */
5926 if (opcode
& ~mask
) {
5928 "qemu internal error: bogus opcode definition %04x/%04x\n",
5933 * This could probably be cleverer. For now just optimize the case where
5934 * the top bits are known.
5936 /* Find the first zero bit in the mask. */
5938 while ((i
& mask
) != 0)
5940 /* Iterate over all combinations of this and lower bits. */
5945 from
= opcode
& ~(i
- 1);
5947 for (i
= from
; i
< to
; i
++) {
5948 if ((i
& mask
) == opcode
)
5949 opcode_table
[i
] = proc
;
5954 * Register m68k opcode handlers. Order is important.
5955 * Later insn override earlier ones.
5957 void register_m68k_insns (CPUM68KState
*env
)
5960 * Build the opcode table only once to avoid
5961 * multithreading issues.
5963 if (opcode_table
[0] != NULL
) {
5968 * use BASE() for instruction available
5969 * for CF_ISA_A and M68000.
5971 #define BASE(name, opcode, mask) \
5972 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5973 #define INSN(name, opcode, mask, feature) do { \
5974 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5975 BASE(name, opcode, mask); \
5977 BASE(undef
, 0000, 0000);
5978 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
5979 INSN(arith_im
, 0000, ff00
, M68K
);
5980 INSN(chk2
, 00c0
, f9c0
, CHK2
);
5981 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
5982 BASE(bitop_reg
, 0100, f1c0
);
5983 BASE(bitop_reg
, 0140, f1c0
);
5984 BASE(bitop_reg
, 0180, f1c0
);
5985 BASE(bitop_reg
, 01c0
, f1c0
);
5986 INSN(movep
, 0108, f138
, MOVEP
);
5987 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
5988 INSN(arith_im
, 0200, ff00
, M68K
);
5989 INSN(undef
, 02c0
, ffc0
, M68K
);
5990 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
5991 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
5992 INSN(arith_im
, 0400, ff00
, M68K
);
5993 INSN(undef
, 04c0
, ffc0
, M68K
);
5994 INSN(arith_im
, 0600, ff00
, M68K
);
5995 INSN(undef
, 06c0
, ffc0
, M68K
);
5996 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
5997 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
5998 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
5999 INSN(arith_im
, 0c00
, ff00
, M68K
);
6000 BASE(bitop_im
, 0800, ffc0
);
6001 BASE(bitop_im
, 0840, ffc0
);
6002 BASE(bitop_im
, 0880, ffc0
);
6003 BASE(bitop_im
, 08c0
, ffc0
);
6004 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
6005 INSN(arith_im
, 0a00
, ff00
, M68K
);
6006 #if defined(CONFIG_SOFTMMU)
6007 INSN(moves
, 0e00
, ff00
, M68K
);
6009 INSN(cas
, 0ac0
, ffc0
, CAS
);
6010 INSN(cas
, 0cc0
, ffc0
, CAS
);
6011 INSN(cas
, 0ec0
, ffc0
, CAS
);
6012 INSN(cas2w
, 0cfc
, ffff
, CAS
);
6013 INSN(cas2l
, 0efc
, ffff
, CAS
);
6014 BASE(move
, 1000, f000
);
6015 BASE(move
, 2000, f000
);
6016 BASE(move
, 3000, f000
);
6017 INSN(chk
, 4000, f040
, M68K
);
6018 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
6019 INSN(negx
, 4080, fff8
, CF_ISA_A
);
6020 INSN(negx
, 4000, ff00
, M68K
);
6021 INSN(undef
, 40c0
, ffc0
, M68K
);
6022 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
6023 INSN(move_from_sr
, 40c0
, ffc0
, M68K
);
6024 BASE(lea
, 41c0
, f1c0
);
6025 BASE(clr
, 4200, ff00
);
6026 BASE(undef
, 42c0
, ffc0
);
6027 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
6028 INSN(move_from_ccr
, 42c0
, ffc0
, M68K
);
6029 INSN(neg
, 4480, fff8
, CF_ISA_A
);
6030 INSN(neg
, 4400, ff00
, M68K
);
6031 INSN(undef
, 44c0
, ffc0
, M68K
);
6032 BASE(move_to_ccr
, 44c0
, ffc0
);
6033 INSN(not, 4680, fff8
, CF_ISA_A
);
6034 INSN(not, 4600, ff00
, M68K
);
6035 #if defined(CONFIG_SOFTMMU)
6036 BASE(move_to_sr
, 46c0
, ffc0
);
6038 INSN(nbcd
, 4800, ffc0
, M68K
);
6039 INSN(linkl
, 4808, fff8
, M68K
);
6040 BASE(pea
, 4840, ffc0
);
6041 BASE(swap
, 4840, fff8
);
6042 INSN(bkpt
, 4848, fff8
, BKPT
);
6043 INSN(movem
, 48d0
, fbf8
, CF_ISA_A
);
6044 INSN(movem
, 48e8
, fbf8
, CF_ISA_A
);
6045 INSN(movem
, 4880, fb80
, M68K
);
6046 BASE(ext
, 4880, fff8
);
6047 BASE(ext
, 48c0
, fff8
);
6048 BASE(ext
, 49c0
, fff8
);
6049 BASE(tst
, 4a00
, ff00
);
6050 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
6051 INSN(tas
, 4ac0
, ffc0
, M68K
);
6052 #if defined(CONFIG_SOFTMMU)
6053 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
6054 INSN(halt
, 4ac8
, ffff
, M68K
);
6056 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
6057 BASE(illegal
, 4afc
, ffff
);
6058 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
6059 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
6060 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
6061 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
6062 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
6063 BASE(trap
, 4e40
, fff0
);
6064 BASE(link
, 4e50
, fff8
);
6065 BASE(unlk
, 4e58
, fff8
);
6066 #if defined(CONFIG_SOFTMMU)
6067 INSN(move_to_usp
, 4e60
, fff8
, USP
);
6068 INSN(move_from_usp
, 4e68
, fff8
, USP
);
6069 INSN(reset
, 4e70
, ffff
, M68K
);
6070 BASE(stop
, 4e72
, ffff
);
6071 BASE(rte
, 4e73
, ffff
);
6072 INSN(cf_movec
, 4e7b
, ffff
, CF_ISA_A
);
6073 INSN(m68k_movec
, 4e7a
, fffe
, MOVEC
);
6075 BASE(nop
, 4e71
, ffff
);
6076 INSN(rtd
, 4e74
, ffff
, RTD
);
6077 BASE(rts
, 4e75
, ffff
);
6078 INSN(trapv
, 4e76
, ffff
, M68K
);
6079 INSN(rtr
, 4e77
, ffff
, M68K
);
6080 BASE(jump
, 4e80
, ffc0
);
6081 BASE(jump
, 4ec0
, ffc0
);
6082 INSN(addsubq
, 5000, f080
, M68K
);
6083 BASE(addsubq
, 5080, f0c0
);
6084 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
); /* Scc.B Dx */
6085 INSN(scc
, 50c0
, f0c0
, M68K
); /* Scc.B <EA> */
6086 INSN(dbcc
, 50c8
, f0f8
, M68K
);
6087 INSN(trapcc
, 50fa
, f0fe
, TRAPCC
); /* opmode 010, 011 */
6088 INSN(trapcc
, 50fc
, f0ff
, TRAPCC
); /* opmode 100 */
6089 INSN(trapcc
, 51fa
, fffe
, CF_ISA_A
); /* TPF (trapf) opmode 010, 011 */
6090 INSN(trapcc
, 51fc
, ffff
, CF_ISA_A
); /* TPF (trapf) opmode 100 */
6092 /* Branch instructions. */
6093 BASE(branch
, 6000, f000
);
6094 /* Disable long branch instructions, then add back the ones we want. */
6095 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
6096 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
6097 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
6098 INSN(branch
, 60ff
, ffff
, BRAL
);
6099 INSN(branch
, 60ff
, f0ff
, BCCL
);
6101 BASE(moveq
, 7000, f100
);
6102 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
6103 BASE(or, 8000, f000
);
6104 BASE(divw
, 80c0
, f0c0
);
6105 INSN(sbcd_reg
, 8100, f1f8
, M68K
);
6106 INSN(sbcd_mem
, 8108, f1f8
, M68K
);
6107 BASE(addsub
, 9000, f000
);
6108 INSN(undef
, 90c0
, f0c0
, CF_ISA_A
);
6109 INSN(subx_reg
, 9180, f1f8
, CF_ISA_A
);
6110 INSN(subx_reg
, 9100, f138
, M68K
);
6111 INSN(subx_mem
, 9108, f138
, M68K
);
6112 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
6113 INSN(suba
, 90c0
, f0c0
, M68K
);
6115 BASE(undef_mac
, a000
, f000
);
6116 INSN(mac
, a000
, f100
, CF_EMAC
);
6117 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
6118 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
6119 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
6120 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
6121 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
6122 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
6123 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
6124 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
6125 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
6126 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
6128 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
6129 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
6130 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
6131 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
6132 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
6133 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
6134 INSN(cmp
, b000
, f100
, M68K
);
6135 INSN(eor
, b100
, f100
, M68K
);
6136 INSN(cmpm
, b108
, f138
, M68K
);
6137 INSN(cmpa
, b0c0
, f0c0
, M68K
);
6138 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
6139 BASE(and, c000
, f000
);
6140 INSN(exg_dd
, c140
, f1f8
, M68K
);
6141 INSN(exg_aa
, c148
, f1f8
, M68K
);
6142 INSN(exg_da
, c188
, f1f8
, M68K
);
6143 BASE(mulw
, c0c0
, f0c0
);
6144 INSN(abcd_reg
, c100
, f1f8
, M68K
);
6145 INSN(abcd_mem
, c108
, f1f8
, M68K
);
6146 BASE(addsub
, d000
, f000
);
6147 INSN(undef
, d0c0
, f0c0
, CF_ISA_A
);
6148 INSN(addx_reg
, d180
, f1f8
, CF_ISA_A
);
6149 INSN(addx_reg
, d100
, f138
, M68K
);
6150 INSN(addx_mem
, d108
, f138
, M68K
);
6151 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
6152 INSN(adda
, d0c0
, f0c0
, M68K
);
6153 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
6154 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
6155 INSN(shift8_im
, e000
, f0f0
, M68K
);
6156 INSN(shift16_im
, e040
, f0f0
, M68K
);
6157 INSN(shift_im
, e080
, f0f0
, M68K
);
6158 INSN(shift8_reg
, e020
, f0f0
, M68K
);
6159 INSN(shift16_reg
, e060
, f0f0
, M68K
);
6160 INSN(shift_reg
, e0a0
, f0f0
, M68K
);
6161 INSN(shift_mem
, e0c0
, fcc0
, M68K
);
6162 INSN(rotate_im
, e090
, f0f0
, M68K
);
6163 INSN(rotate8_im
, e010
, f0f0
, M68K
);
6164 INSN(rotate16_im
, e050
, f0f0
, M68K
);
6165 INSN(rotate_reg
, e0b0
, f0f0
, M68K
);
6166 INSN(rotate8_reg
, e030
, f0f0
, M68K
);
6167 INSN(rotate16_reg
, e070
, f0f0
, M68K
);
6168 INSN(rotate_mem
, e4c0
, fcc0
, M68K
);
6169 INSN(bfext_mem
, e9c0
, fdc0
, BITFIELD
); /* bfextu & bfexts */
6170 INSN(bfext_reg
, e9c0
, fdf8
, BITFIELD
);
6171 INSN(bfins_mem
, efc0
, ffc0
, BITFIELD
);
6172 INSN(bfins_reg
, efc0
, fff8
, BITFIELD
);
6173 INSN(bfop_mem
, eac0
, ffc0
, BITFIELD
); /* bfchg */
6174 INSN(bfop_reg
, eac0
, fff8
, BITFIELD
); /* bfchg */
6175 INSN(bfop_mem
, ecc0
, ffc0
, BITFIELD
); /* bfclr */
6176 INSN(bfop_reg
, ecc0
, fff8
, BITFIELD
); /* bfclr */
6177 INSN(bfop_mem
, edc0
, ffc0
, BITFIELD
); /* bfffo */
6178 INSN(bfop_reg
, edc0
, fff8
, BITFIELD
); /* bfffo */
6179 INSN(bfop_mem
, eec0
, ffc0
, BITFIELD
); /* bfset */
6180 INSN(bfop_reg
, eec0
, fff8
, BITFIELD
); /* bfset */
6181 INSN(bfop_mem
, e8c0
, ffc0
, BITFIELD
); /* bftst */
6182 INSN(bfop_reg
, e8c0
, fff8
, BITFIELD
); /* bftst */
6183 BASE(undef_fpu
, f000
, f000
);
6184 INSN(fpu
, f200
, ffc0
, CF_FPU
);
6185 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
6186 INSN(fpu
, f200
, ffc0
, FPU
);
6187 INSN(fscc
, f240
, ffc0
, FPU
);
6188 INSN(ftrapcc
, f27a
, fffe
, FPU
); /* opmode 010, 011 */
6189 INSN(ftrapcc
, f27c
, ffff
, FPU
); /* opmode 100 */
6190 INSN(fbcc
, f280
, ff80
, FPU
);
6191 #if defined(CONFIG_SOFTMMU)
6192 INSN(frestore
, f340
, ffc0
, CF_FPU
);
6193 INSN(fsave
, f300
, ffc0
, CF_FPU
);
6194 INSN(frestore
, f340
, ffc0
, FPU
);
6195 INSN(fsave
, f300
, ffc0
, FPU
);
6196 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
6197 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
6198 INSN(cpush
, f420
, ff20
, M68040
);
6199 INSN(cinv
, f400
, ff20
, M68040
);
6200 INSN(pflush
, f500
, ffe0
, M68040
);
6201 INSN(ptest
, f548
, ffd8
, M68040
);
6202 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
6203 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
6205 INSN(move16_mem
, f600
, ffe0
, M68040
);
6206 INSN(move16_reg
, f620
, fff8
, M68040
);
6210 static void m68k_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cpu
)
6212 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6213 CPUM68KState
*env
= cpu
->env_ptr
;
6216 dc
->pc
= dc
->base
.pc_first
;
6217 /* This value will always be filled in properly before m68k_tr_tb_stop. */
6218 dc
->pc_prev
= 0xdeadbeef;
6219 dc
->cc_op
= CC_OP_DYNAMIC
;
6220 dc
->cc_op_synced
= 1;
6222 dc
->writeback_mask
= 0;
6224 dc
->ss_active
= (M68K_SR_TRACE(env
->sr
) == M68K_SR_TRACE_ANY_INS
);
6225 /* If architectural single step active, limit to 1 */
6226 if (dc
->ss_active
) {
6227 dc
->base
.max_insns
= 1;
6231 static void m68k_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
6235 static void m68k_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
6237 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6238 tcg_gen_insn_start(dc
->base
.pc_next
, dc
->cc_op
);
6241 static void m68k_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
6243 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6244 CPUM68KState
*env
= cpu
->env_ptr
;
6245 uint16_t insn
= read_im16(env
, dc
);
6247 opcode_table
[insn
](env
, dc
, insn
);
6250 dc
->pc_prev
= dc
->base
.pc_next
;
6251 dc
->base
.pc_next
= dc
->pc
;
6253 if (dc
->base
.is_jmp
== DISAS_NEXT
) {
6255 * Stop translation when the next insn might touch a new page.
6256 * This ensures that prefetch aborts at the right place.
6258 * We cannot determine the size of the next insn without
6259 * completely decoding it. However, the maximum insn size
6260 * is 32 bytes, so end if we do not have that much remaining.
6261 * This may produce several small TBs at the end of each page,
6262 * but they will all be linked with goto_tb.
6264 * ??? ColdFire maximum is 4 bytes; MC68000's maximum is also
6265 * smaller than MC68020's.
6267 target_ulong start_page_offset
6268 = dc
->pc
- (dc
->base
.pc_first
& TARGET_PAGE_MASK
);
6270 if (start_page_offset
>= TARGET_PAGE_SIZE
- 32) {
6271 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
6276 static void m68k_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
6278 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6280 switch (dc
->base
.is_jmp
) {
6281 case DISAS_NORETURN
:
6283 case DISAS_TOO_MANY
:
6285 gen_jmp_tb(dc
, 0, dc
->pc
, dc
->pc_prev
);
6288 /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
6289 if (dc
->ss_active
) {
6290 gen_raise_exception_format2(dc
, EXCP_TRACE
, dc
->pc_prev
);
6292 tcg_gen_lookup_and_goto_ptr();
6297 * We updated CC_OP and PC in gen_exit_tb, but also modified
6298 * other state that may require returning to the main loop.
6300 if (dc
->ss_active
) {
6301 gen_raise_exception_format2(dc
, EXCP_TRACE
, dc
->pc_prev
);
6303 tcg_gen_exit_tb(NULL
, 0);
6307 g_assert_not_reached();
6311 static void m68k_tr_disas_log(const DisasContextBase
*dcbase
,
6312 CPUState
*cpu
, FILE *logfile
)
6314 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
6315 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
6318 static const TranslatorOps m68k_tr_ops
= {
6319 .init_disas_context
= m68k_tr_init_disas_context
,
6320 .tb_start
= m68k_tr_tb_start
,
6321 .insn_start
= m68k_tr_insn_start
,
6322 .translate_insn
= m68k_tr_translate_insn
,
6323 .tb_stop
= m68k_tr_tb_stop
,
6324 .disas_log
= m68k_tr_disas_log
,
6327 void gen_intermediate_code(CPUState
*cpu
, TranslationBlock
*tb
, int *max_insns
,
6328 target_ulong pc
, void *host_pc
)
6331 translator_loop(cpu
, tb
, max_insns
, pc
, host_pc
, &m68k_tr_ops
, &dc
.base
);
6334 static double floatx80_to_double(CPUM68KState
*env
, uint16_t high
, uint64_t low
)
6336 floatx80 a
= { .high
= high
, .low
= low
};
6342 u
.f64
= floatx80_to_float64(a
, &env
->fp_status
);
6346 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
6348 M68kCPU
*cpu
= M68K_CPU(cs
);
6349 CPUM68KState
*env
= &cpu
->env
;
6352 for (i
= 0; i
< 8; i
++) {
6353 qemu_fprintf(f
, "D%d = %08x A%d = %08x "
6354 "F%d = %04x %016"PRIx64
" (%12g)\n",
6355 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
6356 i
, env
->fregs
[i
].l
.upper
, env
->fregs
[i
].l
.lower
,
6357 floatx80_to_double(env
, env
->fregs
[i
].l
.upper
,
6358 env
->fregs
[i
].l
.lower
));
6360 qemu_fprintf(f
, "PC = %08x ", env
->pc
);
6361 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
6362 qemu_fprintf(f
, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",
6363 sr
, (sr
& SR_T
) >> SR_T_SHIFT
, (sr
& SR_I
) >> SR_I_SHIFT
,
6364 (sr
& SR_S
) ? 'S' : 'U', (sr
& SR_M
) ? '%' : 'I',
6365 (sr
& CCF_X
) ? 'X' : '-', (sr
& CCF_N
) ? 'N' : '-',
6366 (sr
& CCF_Z
) ? 'Z' : '-', (sr
& CCF_V
) ? 'V' : '-',
6367 (sr
& CCF_C
) ? 'C' : '-');
6368 qemu_fprintf(f
, "FPSR = %08x %c%c%c%c ", env
->fpsr
,
6369 (env
->fpsr
& FPSR_CC_A
) ? 'A' : '-',
6370 (env
->fpsr
& FPSR_CC_I
) ? 'I' : '-',
6371 (env
->fpsr
& FPSR_CC_Z
) ? 'Z' : '-',
6372 (env
->fpsr
& FPSR_CC_N
) ? 'N' : '-');
6373 qemu_fprintf(f
, "\n "
6374 "FPCR = %04x ", env
->fpcr
);
6375 switch (env
->fpcr
& FPCR_PREC_MASK
) {
6377 qemu_fprintf(f
, "X ");
6380 qemu_fprintf(f
, "S ");
6383 qemu_fprintf(f
, "D ");
6386 switch (env
->fpcr
& FPCR_RND_MASK
) {
6388 qemu_fprintf(f
, "RN ");
6391 qemu_fprintf(f
, "RZ ");
6394 qemu_fprintf(f
, "RM ");
6397 qemu_fprintf(f
, "RP ");
6400 qemu_fprintf(f
, "\n");
6401 #ifdef CONFIG_SOFTMMU
6402 qemu_fprintf(f
, "%sA7(MSP) = %08x %sA7(USP) = %08x %sA7(ISP) = %08x\n",
6403 env
->current_sp
== M68K_SSP
? "->" : " ", env
->sp
[M68K_SSP
],
6404 env
->current_sp
== M68K_USP
? "->" : " ", env
->sp
[M68K_USP
],
6405 env
->current_sp
== M68K_ISP
? "->" : " ", env
->sp
[M68K_ISP
]);
6406 qemu_fprintf(f
, "VBR = 0x%08x\n", env
->vbr
);
6407 qemu_fprintf(f
, "SFC = %x DFC %x\n", env
->sfc
, env
->dfc
);
6408 qemu_fprintf(f
, "SSW %08x TCR %08x URP %08x SRP %08x\n",
6409 env
->mmu
.ssw
, env
->mmu
.tcr
, env
->mmu
.urp
, env
->mmu
.srp
);
6410 qemu_fprintf(f
, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n",
6411 env
->mmu
.ttr
[M68K_DTTR0
], env
->mmu
.ttr
[M68K_DTTR1
],
6412 env
->mmu
.ttr
[M68K_ITTR0
], env
->mmu
.ttr
[M68K_ITTR1
]);
6413 qemu_fprintf(f
, "MMUSR %08x, fault at %08x\n",
6414 env
->mmu
.mmusr
, env
->mmu
.ar
);