target/microblaze/cpu.h

   1 /*
   2  *  MicroBlaze virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef MICROBLAZE_CPU_H
  21 #define MICROBLAZE_CPU_H
  22
  23 #include "cpu-qom.h"
  24 #include "exec/cpu-defs.h"
  25 #include "fpu/softfloat-types.h"
  26
  27 typedef struct CPUMBState CPUMBState;
  28 #if !defined(CONFIG_USER_ONLY)
  29 #include "mmu.h"
  30 #endif
  31
  32 #define EXCP_MMU        1
  33 #define EXCP_IRQ        2
  34 #define EXCP_SYSCALL    3  /* user-only */
  35 #define EXCP_HW_BREAK   4
  36 #define EXCP_HW_EXCP    5
  37
  38 /* MicroBlaze-specific interrupt pending bits.  */
  39 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
  40
  41 /* Meanings of the MBCPU object's two inbound GPIO lines */
  42 #define MB_CPU_IRQ 0
  43 #define MB_CPU_FIR 1
  44
  45 /* Register aliases. R0 - R15 */
  46 #define R_SP     1
  47 #define SR_PC    0
  48 #define SR_MSR   1
  49 #define SR_EAR   3
  50 #define SR_ESR   5
  51 #define SR_FSR   7
  52 #define SR_BTR   0xb
  53 #define SR_EDR   0xd
  54
  55 /* MSR flags.  */
  56 #define MSR_BE  (1<<0) /* 0x001 */
  57 #define MSR_IE  (1<<1) /* 0x002 */
  58 #define MSR_C   (1<<2) /* 0x004 */
  59 #define MSR_BIP (1<<3) /* 0x008 */
  60 #define MSR_FSL (1<<4) /* 0x010 */
  61 #define MSR_ICE (1<<5) /* 0x020 */
  62 #define MSR_DZ  (1<<6) /* 0x040 */
  63 #define MSR_DCE (1<<7) /* 0x080 */
  64 #define MSR_EE  (1<<8) /* 0x100 */
  65 #define MSR_EIP (1<<9) /* 0x200 */
  66 #define MSR_PVR (1<<10) /* 0x400 */
  67 #define MSR_CC  (1<<31)
  68
  69 /* Machine State Register (MSR) Fields */
  70 #define MSR_UM (1<<11) /* User Mode */
  71 #define MSR_UMS        (1<<12) /* User Mode Save */
  72 #define MSR_VM (1<<13) /* Virtual Mode */
  73 #define MSR_VMS        (1<<14) /* Virtual Mode Save */
  74
  75 #define MSR_KERNEL      MSR_EE|MSR_VM
  76 //#define MSR_USER     MSR_KERNEL|MSR_UM|MSR_IE
  77 #define MSR_KERNEL_VMS  MSR_EE|MSR_VMS
  78 //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
  79
  80 /* Exception State Register (ESR) Fields */
  81 #define          ESR_DIZ       (1<<11) /* Zone Protection */
  82 #define          ESR_W         (1<<11) /* Unaligned word access */
  83 #define          ESR_S         (1<<10) /* Store instruction */
  84
  85 #define          ESR_ESS_FSL_OFFSET     5
  86
  87 #define          ESR_ESS_MASK  (0x7f << 5)
  88
  89 #define          ESR_EC_FSL             0
  90 #define          ESR_EC_UNALIGNED_DATA  1
  91 #define          ESR_EC_ILLEGAL_OP      2
  92 #define          ESR_EC_INSN_BUS        3
  93 #define          ESR_EC_DATA_BUS        4
  94 #define          ESR_EC_DIVZERO         5
  95 #define          ESR_EC_FPU             6
  96 #define          ESR_EC_PRIVINSN        7
  97 #define          ESR_EC_STACKPROT       7  /* Same as PRIVINSN.  */
  98 #define          ESR_EC_DATA_STORAGE    8
  99 #define          ESR_EC_INSN_STORAGE    9
 100 #define          ESR_EC_DATA_TLB        10
 101 #define          ESR_EC_INSN_TLB        11
 102 #define          ESR_EC_MASK            31
 103
 104 /* Floating Point Status Register (FSR) Bits */
 105 #define FSR_IO          (1<<4) /* Invalid operation */
 106 #define FSR_DZ          (1<<3) /* Divide-by-zero */
 107 #define FSR_OF          (1<<2) /* Overflow */
 108 #define FSR_UF          (1<<1) /* Underflow */
 109 #define FSR_DO          (1<<0) /* Denormalized operand error */
 110
 111 /* Version reg.  */
 112 /* Basic PVR mask */
 113 #define PVR0_PVR_FULL_MASK              0x80000000
 114 #define PVR0_USE_BARREL_MASK            0x40000000
 115 #define PVR0_USE_DIV_MASK               0x20000000
 116 #define PVR0_USE_HW_MUL_MASK            0x10000000
 117 #define PVR0_USE_FPU_MASK               0x08000000
 118 #define PVR0_USE_EXC_MASK               0x04000000
 119 #define PVR0_USE_ICACHE_MASK            0x02000000
 120 #define PVR0_USE_DCACHE_MASK            0x01000000
 121 #define PVR0_USE_MMU_MASK               0x00800000
 122 #define PVR0_USE_BTC                    0x00400000
 123 #define PVR0_ENDI_MASK                  0x00200000
 124 #define PVR0_FAULT                      0x00100000
 125 #define PVR0_VERSION_MASK               0x0000FF00
 126 #define PVR0_USER1_MASK                 0x000000FF
 127 #define PVR0_SPROT_MASK                 0x00000001
 128
 129 #define PVR0_VERSION_SHIFT              8
 130
 131 /* User 2 PVR mask */
 132 #define PVR1_USER2_MASK                 0xFFFFFFFF
 133
 134 /* Configuration PVR masks */
 135 #define PVR2_D_OPB_MASK                 0x80000000
 136 #define PVR2_D_LMB_MASK                 0x40000000
 137 #define PVR2_I_OPB_MASK                 0x20000000
 138 #define PVR2_I_LMB_MASK                 0x10000000
 139 #define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
 140 #define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
 141 #define PVR2_D_PLB_MASK                 0x02000000      /* new */
 142 #define PVR2_I_PLB_MASK                 0x01000000      /* new */
 143 #define PVR2_INTERCONNECT               0x00800000      /* new */
 144 #define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
 145 #define PVR2_USE_FSL_EXC                0x00040000      /* new */
 146 #define PVR2_USE_MSR_INSTR              0x00020000
 147 #define PVR2_USE_PCMP_INSTR             0x00010000
 148 #define PVR2_AREA_OPTIMISED             0x00008000
 149 #define PVR2_USE_BARREL_MASK            0x00004000
 150 #define PVR2_USE_DIV_MASK               0x00002000
 151 #define PVR2_USE_HW_MUL_MASK            0x00001000
 152 #define PVR2_USE_FPU_MASK               0x00000800
 153 #define PVR2_USE_MUL64_MASK             0x00000400
 154 #define PVR2_USE_FPU2_MASK              0x00000200      /* new */
 155 #define PVR2_USE_IPLBEXC                0x00000100
 156 #define PVR2_USE_DPLBEXC                0x00000080
 157 #define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
 158 #define PVR2_UNALIGNED_EXC_MASK         0x00000020
 159 #define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
 160 #define PVR2_IOPB_BUS_EXC_MASK          0x00000008
 161 #define PVR2_DOPB_BUS_EXC_MASK          0x00000004
 162 #define PVR2_DIV_ZERO_EXC_MASK          0x00000002
 163 #define PVR2_FPU_EXC_MASK               0x00000001
 164
 165 /* Debug and exception PVR masks */
 166 #define PVR3_DEBUG_ENABLED_MASK         0x80000000
 167 #define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
 168 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
 169 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
 170 #define PVR3_FSL_LINKS_MASK             0x00000380
 171
 172 /* ICache config PVR masks */
 173 #define PVR4_USE_ICACHE_MASK            0x80000000
 174 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
 175 #define PVR4_ICACHE_USE_FSL_MASK        0x02000000
 176 #define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
 177 #define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
 178 #define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000
 179
 180 /* DCache config PVR masks */
 181 #define PVR5_USE_DCACHE_MASK            0x80000000
 182 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
 183 #define PVR5_DCACHE_USE_FSL_MASK        0x02000000
 184 #define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
 185 #define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
 186 #define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
 187 #define PVR5_DCACHE_WRITEBACK_MASK      0x00004000
 188
 189 /* ICache base address PVR mask */
 190 #define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF
 191
 192 /* ICache high address PVR mask */
 193 #define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF
 194
 195 /* DCache base address PVR mask */
 196 #define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF
 197
 198 /* DCache high address PVR mask */
 199 #define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF
 200
 201 /* Target family PVR mask */
 202 #define PVR10_TARGET_FAMILY_MASK        0xFF000000
 203 #define PVR10_ASIZE_SHIFT               18
 204
 205 /* MMU descrtiption */
 206 #define PVR11_USE_MMU                   0xC0000000
 207 #define PVR11_MMU_ITLB_SIZE             0x38000000
 208 #define PVR11_MMU_DTLB_SIZE             0x07000000
 209 #define PVR11_MMU_TLB_ACCESS            0x00C00000
 210 #define PVR11_MMU_ZONES                 0x003E0000
 211 /* MSR Reset value PVR mask */
 212 #define PVR11_MSR_RESET_VALUE_MASK      0x000007FF
 213
 214 #define C_PVR_NONE                      0
 215 #define C_PVR_BASIC                     1
 216 #define C_PVR_FULL                      2
 217
 218 /* CPU flags.  */
 219
 220 /* Condition codes.  */
 221 #define CC_GE  5
 222 #define CC_GT  4
 223 #define CC_LE  3
 224 #define CC_LT  2
 225 #define CC_NE  1
 226 #define CC_EQ  0
 227
 228 #define STREAM_EXCEPTION (1 << 0)
 229 #define STREAM_ATOMIC    (1 << 1)
 230 #define STREAM_TEST      (1 << 2)
 231 #define STREAM_CONTROL   (1 << 3)
 232 #define STREAM_NONBLOCK  (1 << 4)
 233
 234 #define TARGET_INSN_START_EXTRA_WORDS 1
 235
 236 struct CPUMBState {
 237     uint32_t bvalue;   /* TCG temporary, only valid during a TB */
 238     uint32_t btarget;  /* Full resolved branch destination */
 239
 240     uint32_t imm;
 241     uint32_t regs[32];
 242     uint32_t pc;
 243     uint32_t msr;    /* All bits of MSR except MSR[C] and MSR[CC] */
 244     uint32_t msr_c;  /* MSR[C], in low bit; other bits must be 0 */
 245     target_ulong ear;
 246     uint32_t esr;
 247     uint32_t fsr;
 248     uint32_t btr;
 249     uint32_t edr;
 250     float_status fp_status;
 251     /* Stack protectors. Yes, it's a hw feature.  */
 252     uint32_t slr, shr;
 253
 254     /* lwx/swx reserved address */
 255 #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
 256     target_ulong res_addr;
 257     uint32_t res_val;
 258
 259     /* Internal flags.  */
 260 #define IMM_FLAG        (1 << 0)
 261 #define BIMM_FLAG       (1 << 1)
 262 #define ESR_ESS_FLAG    (1 << 2)  /* indicates ESR_ESS_MASK is present */
 263 /* MSR_EE               (1 << 8)  -- these 3 are not in iflags but tb_flags */
 264 /* MSR_UM               (1 << 11) */
 265 /* MSR_VM               (1 << 13) */
 266 /* ESR_ESS_MASK         [11:5]    -- unwind into iflags for unaligned excp */
 267 #define DRTI_FLAG       (1 << 16)
 268 #define DRTE_FLAG       (1 << 17)
 269 #define DRTB_FLAG       (1 << 18)
 270 #define D_FLAG          (1 << 19)  /* Bit in ESR.  */
 271
 272 /* TB dependent CPUMBState.  */
 273 #define IFLAGS_TB_MASK  (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
 274 #define MSR_TB_MASK     (MSR_UM | MSR_VM | MSR_EE)
 275
 276     uint32_t iflags;
 277
 278 #if !defined(CONFIG_USER_ONLY)
 279     /* Unified MMU.  */
 280     struct microblaze_mmu mmu;
 281 #endif
 282
 283     /* Fields up to this point are cleared by a CPU reset */
 284     struct {} end_reset_fields;
 285
 286     /* These fields are preserved on reset.  */
 287
 288     struct {
 289         uint32_t regs[13];
 290     } pvr;
 291 };
 292
 293 /**
 294  * MicroBlazeCPU:
 295  * @env: #CPUMBState
 296  *
 297  * A MicroBlaze CPU.
 298  */
 299 struct MicroBlazeCPU {
 300     /*< private >*/
 301     CPUState parent_obj;
 302
 303     /*< public >*/
 304
 305     CPUNegativeOffsetState neg;
 306     CPUMBState env;
 307
 308     /* Microblaze Configuration Settings */
 309     struct {
 310         bool stackprot;
 311         uint32_t base_vectors;
 312         uint8_t addr_size;
 313         uint8_t use_fpu;
 314         uint8_t use_hw_mul;
 315         bool use_barrel;
 316         bool use_div;
 317         bool use_msr_instr;
 318         bool use_pcmp_instr;
 319         bool use_mmu;
 320         bool dcache_writeback;
 321         bool endi;
 322         bool dopb_bus_exception;
 323         bool iopb_bus_exception;
 324         bool illegal_opcode_exception;
 325         bool opcode_0_illegal;
 326         bool div_zero_exception;
 327         bool unaligned_exceptions;
 328         uint8_t pvr_user1;
 329         uint32_t pvr_user2;
 330         char *version;
 331         uint8_t pvr;
 332     } cfg;
 333 };
 334
 335
 336 void mb_cpu_do_interrupt(CPUState *cs);
 337 bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
 338 void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
 339                                 MMUAccessType access_type,
 340                                 int mmu_idx, uintptr_t retaddr);
 341 void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 342 hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 343 int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 344 int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 345
 346 static inline uint32_t mb_cpu_read_msr(const CPUMBState *env)
 347 {
 348     /* Replicate MSR[C] to MSR[CC]. */
 349     return env->msr | (env->msr_c * (MSR_C | MSR_CC));
 350 }
 351
 352 static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val)
 353 {
 354     env->msr_c = (val >> 2) & 1;
 355     /*
 356      * Clear both MSR[C] and MSR[CC] from the saved copy.
 357      * MSR_PVR is not writable and is always clear.
 358      */
 359     env->msr = val & ~(MSR_C | MSR_CC | MSR_PVR);
 360 }
 361
 362 void mb_tcg_init(void);
 363 /* you can call this signal handler from your SIGBUS and SIGSEGV
 364    signal handlers to inform the virtual CPU of exceptions. non zero
 365    is returned if the signal was handled by the virtual CPU.  */
 366 int cpu_mb_signal_handler(int host_signum, void *pinfo,
 367                           void *puc);
 368
 369 #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU
 370
 371 #define cpu_signal_handler cpu_mb_signal_handler
 372
 373 /* MMU modes definitions */
 374 #define MMU_NOMMU_IDX   0
 375 #define MMU_KERNEL_IDX  1
 376 #define MMU_USER_IDX    2
 377 /* See NB_MMU_MODES further up the file.  */
 378
 379 bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 380                      MMUAccessType access_type, int mmu_idx,
 381                      bool probe, uintptr_t retaddr);
 382
 383 typedef CPUMBState CPUArchState;
 384 typedef MicroBlazeCPU ArchCPU;
 385
 386 #include "exec/cpu-all.h"
 387
 388 /* Ensure there is no overlap between the two masks. */
 389 QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
 390
 391 static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
 392                                         target_ulong *cs_base, uint32_t *flags)
 393 {
 394     *pc = env->pc;
 395     *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK);
 396     *cs_base = (*flags & IMM_FLAG ? env->imm : 0);
 397 }
 398
 399 #if !defined(CONFIG_USER_ONLY)
 400 void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
 401                                unsigned size, MMUAccessType access_type,
 402                                int mmu_idx, MemTxAttrs attrs,
 403                                MemTxResult response, uintptr_t retaddr);
 404 #endif
 405
 406 static inline int cpu_mmu_index(CPUMBState *env, bool ifetch)
 407 {
 408     MicroBlazeCPU *cpu = env_archcpu(env);
 409
 410     /* Are we in nommu mode?.  */
 411     if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
 412         return MMU_NOMMU_IDX;
 413     }
 414
 415     if (env->msr & MSR_UM) {
 416         return MMU_USER_IDX;
 417     }
 418     return MMU_KERNEL_IDX;
 419 }
 420
 421 #endif