target/microblaze/mmu.c

   1 /*
   2  *  Microblaze MMU emulation for qemu.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias
   5  *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "exec/exec-all.h"
  24
  25 static unsigned int tlb_decode_size(unsigned int f)
  26 {
  27     static const unsigned int sizes[] = {
  28         1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024,
  29         1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024
  30     };
  31     assert(f < ARRAY_SIZE(sizes));
  32     return sizes[f];
  33 }
  34
  35 static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
  36 {
  37     CPUState *cs = env_cpu(env);
  38     MicroBlazeMMU *mmu = &env->mmu;
  39     unsigned int tlb_size;
  40     uint32_t tlb_tag, end, t;
  41
  42     t = mmu->rams[RAM_TAG][idx];
  43     if (!(t & TLB_VALID))
  44         return;
  45
  46     tlb_tag = t & TLB_EPN_MASK;
  47     tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
  48     end = tlb_tag + tlb_size;
  49
  50     while (tlb_tag < end) {
  51         tlb_flush_page(cs, tlb_tag);
  52         tlb_tag += TARGET_PAGE_SIZE;
  53     }
  54 }
  55
  56 static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
  57 {
  58     MicroBlazeMMU *mmu = &env->mmu;
  59     unsigned int i;
  60     uint32_t t;
  61
  62     if (newpid & ~0xff)
  63         qemu_log_mask(LOG_GUEST_ERROR, "Illegal rpid=%x\n", newpid);
  64
  65     for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
  66         /* Lookup and decode.  */
  67         t = mmu->rams[RAM_TAG][i];
  68         if (t & TLB_VALID) {
  69             if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))
  70                 mmu_flush_idx(env, i);
  71         }
  72     }
  73 }
  74
  75 /* rw - 0 = read, 1 = write, 2 = fetch.  */
  76 unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu,
  77                            target_ulong vaddr, int rw, int mmu_idx)
  78 {
  79     unsigned int i, hit = 0;
  80     unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
  81     uint64_t tlb_tag, tlb_rpn, mask;
  82     uint32_t tlb_size, t0;
  83
  84     lu->err = ERR_MISS;
  85     for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
  86         uint64_t t, d;
  87
  88         /* Lookup and decode.  */
  89         t = mmu->rams[RAM_TAG][i];
  90         if (t & TLB_VALID) {
  91             tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
  92             if (tlb_size < TARGET_PAGE_SIZE) {
  93                 qemu_log_mask(LOG_UNIMP, "%d pages not supported\n", tlb_size);
  94                 abort();
  95             }
  96
  97             mask = ~((uint64_t)tlb_size - 1);
  98             tlb_tag = t & TLB_EPN_MASK;
  99             if ((vaddr & mask) != (tlb_tag & mask)) {
 100                 continue;
 101             }
 102             if (mmu->tids[i]
 103                 && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
 104                 continue;
 105             }
 106
 107             /* Bring in the data part.  */
 108             d = mmu->rams[RAM_DATA][i];
 109             tlb_ex = d & TLB_EX;
 110             tlb_wr = d & TLB_WR;
 111
 112             /* Now let's see if there is a zone that overrides the protbits.  */
 113             tlb_zsel = (d >> 4) & 0xf;
 114             t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
 115             t0 &= 0x3;
 116
 117             if (tlb_zsel > mmu->c_mmu_zones) {
 118                 qemu_log_mask(LOG_GUEST_ERROR,
 119                               "tlb zone select out of range! %d\n", tlb_zsel);
 120                 t0 = 1; /* Ignore.  */
 121             }
 122
 123             if (mmu->c_mmu == 1) {
 124                 t0 = 1; /* Zones are disabled.  */
 125             }
 126
 127             switch (t0) {
 128                 case 0:
 129                     if (mmu_idx == MMU_USER_IDX)
 130                         continue;
 131                     break;
 132                 case 2:
 133                     if (mmu_idx != MMU_USER_IDX) {
 134                         tlb_ex = 1;
 135                         tlb_wr = 1;
 136                     }
 137                     break;
 138                 case 3:
 139                     tlb_ex = 1;
 140                     tlb_wr = 1;
 141                     break;
 142                 default: break;
 143             }
 144
 145             lu->err = ERR_PROT;
 146             lu->prot = PAGE_READ;
 147             if (tlb_wr)
 148                 lu->prot |= PAGE_WRITE;
 149             else if (rw == 1)
 150                 goto done;
 151             if (tlb_ex)
 152                 lu->prot |=PAGE_EXEC;
 153             else if (rw == 2) {
 154                 goto done;
 155             }
 156
 157             tlb_rpn = d & TLB_RPN_MASK;
 158
 159             lu->vaddr = tlb_tag;
 160             lu->paddr = tlb_rpn & mmu->c_addr_mask;
 161             lu->size = tlb_size;
 162             lu->err = ERR_HIT;
 163             lu->idx = i;
 164             hit = 1;
 165             goto done;
 166         }
 167     }
 168 done:
 169     qemu_log_mask(CPU_LOG_MMU,
 170                   "MMU vaddr=%" PRIx64 " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
 171                   vaddr, rw, tlb_wr, tlb_ex, hit);
 172     return hit;
 173 }
 174
 175 /* Writes/reads to the MMU's special regs end up here.  */
 176 uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
 177 {
 178     unsigned int i;
 179     uint32_t r = 0;
 180
 181     if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
 182         qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
 183         return 0;
 184     }
 185     if (ext && rn != MMU_R_TLBLO) {
 186         qemu_log_mask(LOG_GUEST_ERROR, "Extended access only to TLBLO.\n");
 187         return 0;
 188     }
 189
 190     switch (rn) {
 191         /* Reads to HI/LO trig reads from the mmu rams.  */
 192         case MMU_R_TLBLO:
 193         case MMU_R_TLBHI:
 194             if (!(env->mmu.c_mmu_tlb_access & 1)) {
 195                 qemu_log_mask(LOG_GUEST_ERROR,
 196                               "Invalid access to MMU reg %d\n", rn);
 197                 return 0;
 198             }
 199
 200             i = env->mmu.regs[MMU_R_TLBX] & 0xff;
 201             r = extract64(env->mmu.rams[rn & 1][i], ext * 32, 32);
 202             if (rn == MMU_R_TLBHI)
 203                 env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];
 204             break;
 205         case MMU_R_PID:
 206         case MMU_R_ZPR:
 207             if (!(env->mmu.c_mmu_tlb_access & 1)) {
 208                 qemu_log_mask(LOG_GUEST_ERROR,
 209                               "Invalid access to MMU reg %d\n", rn);
 210                 return 0;
 211             }
 212             r = env->mmu.regs[rn];
 213             break;
 214         case MMU_R_TLBX:
 215             r = env->mmu.regs[rn];
 216             break;
 217         case MMU_R_TLBSX:
 218             qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n");
 219             break;
 220         default:
 221             qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn);
 222             break;
 223     }
 224     qemu_log_mask(CPU_LOG_MMU, "%s rn=%d=%x\n", __func__, rn, r);
 225     return r;
 226 }
 227
 228 void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
 229 {
 230     uint64_t tmp64;
 231     unsigned int i;
 232     qemu_log_mask(CPU_LOG_MMU,
 233                   "%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]);
 234
 235     if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
 236         qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
 237         return;
 238     }
 239     if (ext && rn != MMU_R_TLBLO) {
 240         qemu_log_mask(LOG_GUEST_ERROR, "Extended access only to TLBLO.\n");
 241         return;
 242     }
 243
 244     switch (rn) {
 245         /* Writes to HI/LO trig writes to the mmu rams.  */
 246         case MMU_R_TLBLO:
 247         case MMU_R_TLBHI:
 248             i = env->mmu.regs[MMU_R_TLBX] & 0xff;
 249             if (rn == MMU_R_TLBHI) {
 250                 if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
 251                     qemu_log_mask(LOG_GUEST_ERROR,
 252                                   "invalidating index %x at pc=%x\n",
 253                                   i, env->pc);
 254                 env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
 255                 mmu_flush_idx(env, i);
 256             }
 257             tmp64 = env->mmu.rams[rn & 1][i];
 258             env->mmu.rams[rn & 1][i] = deposit64(tmp64, ext * 32, 32, v);
 259             break;
 260         case MMU_R_ZPR:
 261             if (env->mmu.c_mmu_tlb_access <= 1) {
 262                 qemu_log_mask(LOG_GUEST_ERROR,
 263                               "Invalid access to MMU reg %d\n", rn);
 264                 return;
 265             }
 266
 267             /* Changes to the zone protection reg flush the QEMU TLB.
 268                Fortunately, these are very uncommon.  */
 269             if (v != env->mmu.regs[rn]) {
 270                 tlb_flush(env_cpu(env));
 271             }
 272             env->mmu.regs[rn] = v;
 273             break;
 274         case MMU_R_PID:
 275             if (env->mmu.c_mmu_tlb_access <= 1) {
 276                 qemu_log_mask(LOG_GUEST_ERROR,
 277                               "Invalid access to MMU reg %d\n", rn);
 278                 return;
 279             }
 280
 281             if (v != env->mmu.regs[rn]) {
 282                 mmu_change_pid(env, v);
 283                 env->mmu.regs[rn] = v;
 284             }
 285             break;
 286         case MMU_R_TLBX:
 287             /* Bit 31 is read-only.  */
 288             env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v);
 289             break;
 290         case MMU_R_TLBSX:
 291         {
 292             MicroBlazeMMULookup lu;
 293             int hit;
 294
 295             if (env->mmu.c_mmu_tlb_access <= 1) {
 296                 qemu_log_mask(LOG_GUEST_ERROR,
 297                               "Invalid access to MMU reg %d\n", rn);
 298                 return;
 299             }
 300
 301             hit = mmu_translate(&env->mmu, &lu,
 302                                 v & TLB_EPN_MASK, 0, cpu_mmu_index(env, false));
 303             if (hit) {
 304                 env->mmu.regs[MMU_R_TLBX] = lu.idx;
 305             } else {
 306                 env->mmu.regs[MMU_R_TLBX] |= R_TBLX_MISS_MASK;
 307             }
 308             break;
 309         }
 310         default:
 311             qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn);
 312             break;
 313    }
 314 }
 315
 316 void mmu_init(MicroBlazeMMU *mmu)
 317 {
 318     int i;
 319     for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
 320         mmu->regs[i] = 0;
 321     }
 322 }