target/mips/cpu-defs.c.inc

   1 /*
   2  *  MIPS emulation for qemu: CPU initialisation routines.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *  Copyright (c) 2007 Herve Poussineau
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 /* CPU / CPU family specific config register values. */
  22
  23 /* Have config1, uncached coherency */
  24 #define MIPS_CONFIG0                                              \
  25   ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
  26
  27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
  28    no performance counters, watch registers present,
  29    no code compression, EJTAG present, no FPU */
  30 #define MIPS_CONFIG1                                              \
  31 ((1U << CP0C1_M) |                                                \
  32  (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
  33  (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |            \
  34  (0 << CP0C1_FP))
  35
  36 /* Have config3, no tertiary/secondary caches implemented */
  37 #define MIPS_CONFIG2                                              \
  38 ((1U << CP0C2_M))
  39
  40 /* No config4, no DSP ASE, no large physaddr (PABITS),
  41    no external interrupt controller, no vectored interrupts,
  42    no 1kb pages, no SmartMIPS ASE, no trace logic */
  43 #define MIPS_CONFIG3                                              \
  44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
  45  (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
  46  (0 << CP0C3_SM) | (0 << CP0C3_TL))
  47
  48 #define MIPS_CONFIG4                                              \
  49 ((0 << CP0C4_M))
  50
  51 #define MIPS_CONFIG5                                              \
  52 ((0 << CP0C5_M))
  53
  54 /*****************************************************************************/
  55 /* MIPS CPU definitions */
  56 const mips_def_t mips_defs[] =
  57 {
  58     {
  59         .name = "4Kc",
  60         .CP0_PRid = 0x00018000,
  61         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
  62         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
  63                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  64                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
  65                        (0 << CP0C1_CA),
  66         .CP0_Config2 = MIPS_CONFIG2,
  67         .CP0_Config3 = MIPS_CONFIG3,
  68         .CP0_LLAddr_rw_bitmask = 0,
  69         .CP0_LLAddr_shift = 4,
  70         .SYNCI_Step = 32,
  71         .CCRes = 2,
  72         .CP0_Status_rw_bitmask = 0x1278FF17,
  73         .SEGBITS = 32,
  74         .PABITS = 32,
  75         .insn_flags = CPU_MIPS32R1,
  76         .mmu_type = MMU_TYPE_R4000,
  77     },
  78     {
  79         .name = "4Km",
  80         .CP0_PRid = 0x00018300,
  81         /* Config1 implemented, fixed mapping MMU,
  82            no virtual icache, uncached coherency. */
  83         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
  84         .CP0_Config1 = MIPS_CONFIG1 |
  85                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  86                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
  87                        (1 << CP0C1_CA),
  88         .CP0_Config2 = MIPS_CONFIG2,
  89         .CP0_Config3 = MIPS_CONFIG3,
  90         .CP0_LLAddr_rw_bitmask = 0,
  91         .CP0_LLAddr_shift = 4,
  92         .SYNCI_Step = 32,
  93         .CCRes = 2,
  94         .CP0_Status_rw_bitmask = 0x1258FF17,
  95         .SEGBITS = 32,
  96         .PABITS = 32,
  97         .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
  98         .mmu_type = MMU_TYPE_FMT,
  99     },
 100     {
 101         .name = "4KEcR1",
 102         .CP0_PRid = 0x00018400,
 103         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
 104         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 105                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 106                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 107                        (0 << CP0C1_CA),
 108         .CP0_Config2 = MIPS_CONFIG2,
 109         .CP0_Config3 = MIPS_CONFIG3,
 110         .CP0_LLAddr_rw_bitmask = 0,
 111         .CP0_LLAddr_shift = 4,
 112         .SYNCI_Step = 32,
 113         .CCRes = 2,
 114         .CP0_Status_rw_bitmask = 0x1278FF17,
 115         .SEGBITS = 32,
 116         .PABITS = 32,
 117         .insn_flags = CPU_MIPS32R1,
 118         .mmu_type = MMU_TYPE_R4000,
 119     },
 120     {
 121         .name = "XBurstR1",
 122         .CP0_PRid = 0x1ed0024f,
 123         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
 124         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 125                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 126                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 127                        (0 << CP0C1_CA),
 128         .CP0_Config2 = MIPS_CONFIG2,
 129         .CP0_Config3 = MIPS_CONFIG3,
 130         .CP0_LLAddr_rw_bitmask = 0,
 131         .CP0_LLAddr_shift = 4,
 132         .SYNCI_Step = 32,
 133         .CCRes = 2,
 134         .CP0_Status_rw_bitmask = 0x1278FF17,
 135         .SEGBITS = 32,
 136         .PABITS = 32,
 137         .insn_flags = CPU_MIPS32R1 | ASE_MXU,
 138         .mmu_type = MMU_TYPE_R4000,
 139     },
 140     {
 141         .name = "4KEmR1",
 142         .CP0_PRid = 0x00018500,
 143         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
 144         .CP0_Config1 = MIPS_CONFIG1 |
 145                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 146                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 147                        (1 << CP0C1_CA),
 148         .CP0_Config2 = MIPS_CONFIG2,
 149         .CP0_Config3 = MIPS_CONFIG3,
 150         .CP0_LLAddr_rw_bitmask = 0,
 151         .CP0_LLAddr_shift = 4,
 152         .SYNCI_Step = 32,
 153         .CCRes = 2,
 154         .CP0_Status_rw_bitmask = 0x1258FF17,
 155         .SEGBITS = 32,
 156         .PABITS = 32,
 157         .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
 158         .mmu_type = MMU_TYPE_FMT,
 159     },
 160     {
 161         .name = "4KEc",
 162         .CP0_PRid = 0x00019000,
 163         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 164                     (MMU_TYPE_R4000 << CP0C0_MT),
 165         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 166                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 167                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 168                        (0 << CP0C1_CA),
 169         .CP0_Config2 = MIPS_CONFIG2,
 170         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 171         .CP0_LLAddr_rw_bitmask = 0,
 172         .CP0_LLAddr_shift = 4,
 173         .SYNCI_Step = 32,
 174         .CCRes = 2,
 175         .CP0_Status_rw_bitmask = 0x1278FF17,
 176         .SEGBITS = 32,
 177         .PABITS = 32,
 178         .insn_flags = CPU_MIPS32R2,
 179         .mmu_type = MMU_TYPE_R4000,
 180     },
 181     {
 182         .name = "4KEm",
 183         .CP0_PRid = 0x00019100,
 184         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 185                        (MMU_TYPE_FMT << CP0C0_MT),
 186         .CP0_Config1 = MIPS_CONFIG1 |
 187                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 188                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 189                        (1 << CP0C1_CA),
 190         .CP0_Config2 = MIPS_CONFIG2,
 191         .CP0_Config3 = MIPS_CONFIG3,
 192         .CP0_LLAddr_rw_bitmask = 0,
 193         .CP0_LLAddr_shift = 4,
 194         .SYNCI_Step = 32,
 195         .CCRes = 2,
 196         .CP0_Status_rw_bitmask = 0x1258FF17,
 197         .SEGBITS = 32,
 198         .PABITS = 32,
 199         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 200         .mmu_type = MMU_TYPE_FMT,
 201     },
 202     {
 203         .name = "24Kc",
 204         .CP0_PRid = 0x00019300,
 205         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 206                        (MMU_TYPE_R4000 << CP0C0_MT),
 207         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 208                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 209                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 210                        (1 << CP0C1_CA),
 211         .CP0_Config2 = MIPS_CONFIG2,
 212         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 213         .CP0_LLAddr_rw_bitmask = 0,
 214         .CP0_LLAddr_shift = 4,
 215         .SYNCI_Step = 32,
 216         .CCRes = 2,
 217         /* No DSP implemented. */
 218         .CP0_Status_rw_bitmask = 0x1278FF1F,
 219         .SEGBITS = 32,
 220         .PABITS = 32,
 221         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 222         .mmu_type = MMU_TYPE_R4000,
 223     },
 224     {
 225         .name = "24KEc",
 226         .CP0_PRid = 0x00019600,
 227         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 228                        (MMU_TYPE_R4000 << CP0C0_MT),
 229         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 230                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 231                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 232                        (1 << CP0C1_CA),
 233         .CP0_Config2 = MIPS_CONFIG2,
 234         .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
 235         .CP0_LLAddr_rw_bitmask = 0,
 236         .CP0_LLAddr_shift = 4,
 237         .SYNCI_Step = 32,
 238         .CCRes = 2,
 239         /* we have a DSP, but no FPU */
 240         .CP0_Status_rw_bitmask = 0x1378FF1F,
 241         .SEGBITS = 32,
 242         .PABITS = 32,
 243         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
 244         .mmu_type = MMU_TYPE_R4000,
 245     },
 246     {
 247         .name = "24Kf",
 248         .CP0_PRid = 0x00019300,
 249         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 250                     (MMU_TYPE_R4000 << CP0C0_MT),
 251         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 252                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 253                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 254                        (1 << CP0C1_CA),
 255         .CP0_Config2 = MIPS_CONFIG2,
 256         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 257         .CP0_LLAddr_rw_bitmask = 0,
 258         .CP0_LLAddr_shift = 4,
 259         .SYNCI_Step = 32,
 260         .CCRes = 2,
 261         /* No DSP implemented. */
 262         .CP0_Status_rw_bitmask = 0x3678FF1F,
 263         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 264                     (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
 265         .CP1_fcr31 = 0,
 266         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 267         .SEGBITS = 32,
 268         .PABITS = 32,
 269         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 270         .mmu_type = MMU_TYPE_R4000,
 271     },
 272     {
 273         .name = "34Kf",
 274         .CP0_PRid = 0x00019500,
 275         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 276                        (MMU_TYPE_R4000 << CP0C0_MT),
 277         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
 278                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 279                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 280                        (1 << CP0C1_CA),
 281         .CP0_Config2 = MIPS_CONFIG2,
 282         .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
 283                        (1 << CP0C3_DSPP),
 284         .CP0_LLAddr_rw_bitmask = 0,
 285         .CP0_LLAddr_shift = 0,
 286         .SYNCI_Step = 32,
 287         .CCRes = 2,
 288         .CP0_Status_rw_bitmask = 0x3778FF1F,
 289         .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
 290                     (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
 291                     (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
 292                     (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
 293                     (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
 294                     (0xff << CP0TCSt_TASID),
 295         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 296                     (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
 297         .CP1_fcr31 = 0,
 298         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 299         .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
 300         .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
 301         .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
 302                     (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
 303         .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
 304         .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
 305                     (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
 306         .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
 307         .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
 308                     (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
 309         .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
 310         .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
 311                     (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
 312         .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
 313         .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
 314                     (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
 315         .SEGBITS = 32,
 316         .PABITS = 32,
 317         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
 318         .mmu_type = MMU_TYPE_R4000,
 319     },
 320     {
 321         .name = "74Kf",
 322         .CP0_PRid = 0x00019700,
 323         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 324                     (MMU_TYPE_R4000 << CP0C0_MT),
 325         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 326                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 327                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 328                        (1 << CP0C1_CA),
 329         .CP0_Config2 = MIPS_CONFIG2,
 330         .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
 331                        (1 << CP0C3_VInt),
 332         .CP0_LLAddr_rw_bitmask = 0,
 333         .CP0_LLAddr_shift = 4,
 334         .SYNCI_Step = 32,
 335         .CCRes = 2,
 336         .CP0_Status_rw_bitmask = 0x3778FF1F,
 337         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 338                     (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
 339         .CP1_fcr31 = 0,
 340         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 341         .SEGBITS = 32,
 342         .PABITS = 32,
 343         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
 344         .mmu_type = MMU_TYPE_R4000,
 345     },
 346     {
 347         .name = "XBurstR2",
 348         .CP0_PRid = 0x2ed1024f,
 349         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 350                     (MMU_TYPE_R4000 << CP0C0_MT),
 351         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 352                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 353                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 354                        (1 << CP0C1_CA),
 355         .CP0_Config2 = MIPS_CONFIG2,
 356         .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
 357                        (1 << CP0C3_VInt),
 358         .CP0_LLAddr_rw_bitmask = 0,
 359         .CP0_LLAddr_shift = 4,
 360         .SYNCI_Step = 32,
 361         .CCRes = 2,
 362         .CP0_Status_rw_bitmask = 0x3778FF1F,
 363         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 364                     (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
 365         .CP1_fcr31 = 0,
 366         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 367         .SEGBITS = 32,
 368         .PABITS = 32,
 369         .insn_flags = CPU_MIPS32R2 | ASE_MXU,
 370         .mmu_type = MMU_TYPE_R4000,
 371     },
 372     {
 373         .name = "M14K",
 374         .CP0_PRid = 0x00019b00,
 375         /* Config1 implemented, fixed mapping MMU,
 376            no virtual icache, uncached coherency. */
 377         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
 378                        (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
 379         .CP0_Config1 = MIPS_CONFIG1,
 380         .CP0_Config2 = MIPS_CONFIG2,
 381         .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt) |
 382                        (1 << CP0C3_M),
 383         .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
 384         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),
 385         .CP0_Config7 = 1 << CP0C7_WII,
 386         .CP0_LLAddr_rw_bitmask = 0,
 387         .CP0_LLAddr_shift = 4,
 388         .SYNCI_Step = 32,
 389         .CCRes = 2,
 390         .CP0_Status_rw_bitmask = 0x1258FF17,
 391         .SEGBITS = 32,
 392         .PABITS = 32,
 393         .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
 394         .mmu_type = MMU_TYPE_FMT,
 395     },
 396     {
 397         .name = "M14Kc",
 398         /* This is the TLB-based MMU core.  */
 399         .CP0_PRid = 0x00019c00,
 400         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 401                        (MMU_TYPE_R4000 << CP0C0_MT),
 402         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 403                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 404                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 405         .CP0_Config2 = MIPS_CONFIG2,
 406         .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt) |
 407                        (1 << CP0C3_M),
 408         .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
 409         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),
 410         .CP0_Config7 = 1 << CP0C7_WII,
 411         .CP0_LLAddr_rw_bitmask = 0,
 412         .CP0_LLAddr_shift = 4,
 413         .SYNCI_Step = 32,
 414         .CCRes = 2,
 415         .CP0_Status_rw_bitmask = 0x1278FF17,
 416         .SEGBITS = 32,
 417         .PABITS = 32,
 418         .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
 419         .mmu_type = MMU_TYPE_R4000,
 420     },
 421     {
 422         /* FIXME:
 423          * Config3: VZ, CTXTC, CDMM, TL
 424          * Config4: MMUExtDef
 425          * Config5: MRP
 426          * */
 427         .name = "P5600",
 428         .CP0_PRid = 0x0001A800,
 429         .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
 430                     (MMU_TYPE_R4000 << CP0C0_MT),
 431         .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
 432                        (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 433                        (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 434                        (1 << CP0C1_PC) | (1 << CP0C1_FP),
 435         .CP0_Config2 = MIPS_CONFIG2,
 436         .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
 437                        (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
 438                        (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
 439                        (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
 440                        (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
 441         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
 442                        (0x1c << CP0C4_KScrExist),
 443         .CP0_Config4_rw_bitmask = 0,
 444         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
 445                        (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
 446         .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
 447                                   (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
 448                                   (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
 449         .CP0_Config7 = 1 << CP0C7_WII,
 450         .CP0_LLAddr_rw_bitmask = 0,
 451         .CP0_LLAddr_shift = 0,
 452         .SYNCI_Step = 32,
 453         .CCRes = 2,
 454         .CP0_Status_rw_bitmask = 0x3C68FF1F,
 455         .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
 456                     (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
 457         .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
 458         .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
 459                     (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 460                     (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
 461         .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
 462         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 463         .SEGBITS = 32,
 464         .PABITS = 40,
 465         .insn_flags = CPU_MIPS32R5,
 466         .mmu_type = MMU_TYPE_R4000,
 467     },
 468     {
 469         /* A generic CPU supporting MIPS32 Release 6 ISA.
 470            FIXME: Support IEEE 754-2008 FP.
 471                   Eventually this should be replaced by a real CPU model. */
 472         .name = "mips32r6-generic",
 473         .CP0_PRid = 0x00010000,
 474         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
 475                        (MMU_TYPE_R4000 << CP0C0_MT),
 476         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
 477                        (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 478                        (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 479                        (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 480         .CP0_Config2 = MIPS_CONFIG2,
 481         .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
 482                        (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
 483                        (1 << CP0C3_RXI) | (1U << CP0C3_M),
 484         .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
 485                        (3 << CP0C4_IE) | (1U << CP0C4_M),
 486         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
 487         .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
 488                                   (1 << CP0C5_UFE),
 489         .CP0_LLAddr_rw_bitmask = 0,
 490         .CP0_LLAddr_shift = 0,
 491         .SYNCI_Step = 32,
 492         .CCRes = 2,
 493         .CP0_Status_rw_bitmask = 0x3058FF1F,
 494         .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
 495                          (1U << CP0PG_RIE),
 496         .CP0_PageGrain_rw_bitmask = 0,
 497         .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
 498                     (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 499                     (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
 500         .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
 501         .CP1_fcr31_rw_bitmask = 0x0103FFFF,
 502         .SEGBITS = 32,
 503         .PABITS = 32,
 504         .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
 505         .mmu_type = MMU_TYPE_R4000,
 506     },
 507     {
 508         .name = "I7200",
 509         .CP0_PRid = 0x00010000,
 510         .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
 511                         (MMU_TYPE_R4000 << CP0C0_MT),
 512         .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |
 513                        (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |
 514                        (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |
 515                        (1 << CP0C1_EP),
 516         .CP0_Config2 = MIPS_CONFIG2,
 517         .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |
 518                        (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) |
 519                        (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |
 520                        (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
 521                        (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
 522                        (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) |
 523                        (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL),
 524         .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
 525                        (2 << CP0C4_IE) | (1U << CP0C4_M),
 526         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
 527         .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
 528                                   (1 << CP0C5_UFE),
 529         .CP0_LLAddr_rw_bitmask = 0,
 530         .CP0_LLAddr_shift = 0,
 531         .SYNCI_Step = 32,
 532         .CCRes = 2,
 533         .CP0_Status_rw_bitmask = 0x3158FF1F,
 534         .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
 535                          (1U << CP0PG_RIE),
 536         .CP0_PageGrain_rw_bitmask = 0,
 537         .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
 538                     (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 539                     (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
 540         .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
 541         .SEGBITS = 32,
 542         .PABITS = 32,
 543         .insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 |
 544                       ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT,
 545         .mmu_type = MMU_TYPE_R4000,
 546     },
 547 #if defined(TARGET_MIPS64)
 548     {
 549         .name = "R4000",
 550         .CP0_PRid = 0x00000400,
 551         /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
 552         .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) |
 553                        (2 << CP0C0_K0),
 554         /* Note: Config1 is only used internally, the R4000 has only Config0. */
 555         .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
 556         .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
 557         .CP0_LLAddr_shift = 4,
 558         .SYNCI_Step = 16,
 559         .CCRes = 2,
 560         .CP0_Status_rw_bitmask = 0x3678FFFF,
 561         /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
 562         .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
 563         .CP1_fcr31 = 0,
 564         .CP1_fcr31_rw_bitmask = 0x0183FFFF,
 565         .SEGBITS = 40,
 566         .PABITS = 36,
 567         .insn_flags = CPU_MIPS3,
 568         .mmu_type = MMU_TYPE_R4000,
 569     },
 570     {
 571         .name = "VR5432",
 572         .CP0_PRid = 0x00005400,
 573         /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
 574         .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) |
 575                        (2 << CP0C0_K0),
 576         .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
 577         .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
 578         .CP0_LLAddr_shift = 4,
 579         .SYNCI_Step = 16,
 580         .CCRes = 2,
 581         .CP0_Status_rw_bitmask = 0x3678FFFF,
 582         /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
 583         .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
 584         .CP1_fcr31 = 0,
 585         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 586         .SEGBITS = 40,
 587         .PABITS = 32,
 588         .insn_flags = CPU_MIPS4 | INSN_VR54XX,
 589         .mmu_type = MMU_TYPE_R4000,
 590     },
 591     {
 592         .name = "5Kc",
 593         .CP0_PRid = 0x00018100,
 594         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
 595                        (MMU_TYPE_R4000 << CP0C0_MT),
 596         .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
 597                        (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 598                        (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 599                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 600         .CP0_Config2 = MIPS_CONFIG2,
 601         .CP0_Config3 = MIPS_CONFIG3,
 602         .CP0_LLAddr_rw_bitmask = 0,
 603         .CP0_LLAddr_shift = 4,
 604         .SYNCI_Step = 32,
 605         .CCRes = 2,
 606         .CP0_Status_rw_bitmask = 0x12F8FFFF,
 607         .SEGBITS = 42,
 608         .PABITS = 36,
 609         .insn_flags = CPU_MIPS64R1,
 610         .mmu_type = MMU_TYPE_R4000,
 611     },
 612     {
 613         .name = "5Kf",
 614         .CP0_PRid = 0x00018100,
 615         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
 616                        (MMU_TYPE_R4000 << CP0C0_MT),
 617         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
 618                        (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 619                        (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 620                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 621         .CP0_Config2 = MIPS_CONFIG2,
 622         .CP0_Config3 = MIPS_CONFIG3,
 623         .CP0_LLAddr_rw_bitmask = 0,
 624         .CP0_LLAddr_shift = 4,
 625         .SYNCI_Step = 32,
 626         .CCRes = 2,
 627         .CP0_Status_rw_bitmask = 0x36F8FFFF,
 628         /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
 629         .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
 630                     (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
 631         .CP1_fcr31 = 0,
 632         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 633         .SEGBITS = 42,
 634         .PABITS = 36,
 635         .insn_flags = CPU_MIPS64R1,
 636         .mmu_type = MMU_TYPE_R4000,
 637     },
 638     {
 639         .name = "20Kc",
 640         /* We emulate a later version of the 20Kc, earlier ones had a broken
 641            WAIT instruction. */
 642         .CP0_PRid = 0x000182a0,
 643         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
 644                     (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
 645         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
 646                        (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 647                        (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 648                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 649         .CP0_Config2 = MIPS_CONFIG2,
 650         .CP0_Config3 = MIPS_CONFIG3,
 651         .CP0_LLAddr_rw_bitmask = 0,
 652         .CP0_LLAddr_shift = 0,
 653         .SYNCI_Step = 32,
 654         .CCRes = 1,
 655         .CP0_Status_rw_bitmask = 0x36FBFFFF,
 656         /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
 657         .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
 658                     (1 << FCR0_D) | (1 << FCR0_S) |
 659                     (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
 660         .CP1_fcr31 = 0,
 661         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 662         .SEGBITS = 40,
 663         .PABITS = 36,
 664         .insn_flags = CPU_MIPS64R1 | ASE_MIPS3D,
 665         .mmu_type = MMU_TYPE_R4000,
 666     },
 667     {
 668         /* A generic CPU providing MIPS64 Release 2 features.
 669            FIXME: Eventually this should be replaced by a real CPU model. */
 670         .name = "MIPS64R2-generic",
 671         .CP0_PRid = 0x00010000,
 672         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 673                        (MMU_TYPE_R4000 << CP0C0_MT),
 674         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
 675                        (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 676                        (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 677                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 678         .CP0_Config2 = MIPS_CONFIG2,
 679         .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
 680         .CP0_LLAddr_rw_bitmask = 0,
 681         .CP0_LLAddr_shift = 0,
 682         .SYNCI_Step = 32,
 683         .CCRes = 2,
 684         .CP0_Status_rw_bitmask = 0x36FBFFFF,
 685         .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
 686         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
 687                     (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 688                     (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
 689         .CP1_fcr31 = 0,
 690         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 691         .SEGBITS = 42,
 692         .PABITS = 36,
 693         .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
 694         .mmu_type = MMU_TYPE_R4000,
 695     },
 696     {
 697         .name = "5KEc",
 698         .CP0_PRid = 0x00018900,
 699         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 700                        (MMU_TYPE_R4000 << CP0C0_MT),
 701         .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
 702                        (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 703                        (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 704                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 705         .CP0_Config2 = MIPS_CONFIG2,
 706         .CP0_Config3 = MIPS_CONFIG3,
 707         .CP0_LLAddr_rw_bitmask = 0,
 708         .CP0_LLAddr_shift = 4,
 709         .SYNCI_Step = 32,
 710         .CCRes = 2,
 711         .CP0_Status_rw_bitmask = 0x12F8FFFF,
 712         .SEGBITS = 42,
 713         .PABITS = 36,
 714         .insn_flags = CPU_MIPS64R2,
 715         .mmu_type = MMU_TYPE_R4000,
 716     },
 717     {
 718         .name = "5KEf",
 719         .CP0_PRid = 0x00018900,
 720         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 721                        (MMU_TYPE_R4000 << CP0C0_MT),
 722         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
 723                        (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 724                        (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 725                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 726         .CP0_Config2 = MIPS_CONFIG2,
 727         .CP0_Config3 = MIPS_CONFIG3,
 728         .CP0_LLAddr_rw_bitmask = 0,
 729         .CP0_LLAddr_shift = 4,
 730         .SYNCI_Step = 32,
 731         .CCRes = 2,
 732         .CP0_Status_rw_bitmask = 0x36F8FFFF,
 733         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 734                     (1 << FCR0_D) | (1 << FCR0_S) |
 735                     (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
 736         .SEGBITS = 42,
 737         .PABITS = 36,
 738         .insn_flags = CPU_MIPS64R2,
 739         .mmu_type = MMU_TYPE_R4000,
 740     },
 741     {
 742         .name = "I6400",
 743         .CP0_PRid = 0x1A900,
 744         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 745                        (MMU_TYPE_R4000 << CP0C0_MT),
 746         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 747                        (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
 748                        (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
 749                        (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 750         .CP0_Config2 = MIPS_CONFIG2,
 751         .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
 752                        (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
 753                        (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
 754                        (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
 755         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
 756                        (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
 757         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
 758                        (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
 759         .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
 760                                   (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
 761         .CP0_LLAddr_rw_bitmask = 0,
 762         .CP0_LLAddr_shift = 0,
 763         .SYNCI_Step = 32,
 764         .CCRes = 2,
 765         .CP0_Status_rw_bitmask = 0x30D8FFFF,
 766         .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
 767                          (1U << CP0PG_RIE),
 768         .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
 769         .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
 770         .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
 771                     (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 772                     (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
 773         .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
 774         .CP1_fcr31_rw_bitmask = 0x0103FFFF,
 775         .MSAIR = 0x03 << MSAIR_ProcID,
 776         .SEGBITS = 48,
 777         .PABITS = 48,
 778         .insn_flags = CPU_MIPS64R6,
 779         .mmu_type = MMU_TYPE_R4000,
 780     },
 781     {
 782         .name = "I6500",
 783         .CP0_PRid = 0x1B000,
 784         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 785                        (MMU_TYPE_R4000 << CP0C0_MT),
 786         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 787                        (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
 788                        (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
 789                        (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 790         .CP0_Config2 = MIPS_CONFIG2,
 791         .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
 792                        (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
 793                        (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
 794                        (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
 795         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
 796                        (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
 797         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
 798                        (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
 799         .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
 800                                   (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
 801         .CP0_LLAddr_rw_bitmask = 0,
 802         .CP0_LLAddr_shift = 0,
 803         .SYNCI_Step = 64,
 804         .CCRes = 2,
 805         .CP0_Status_rw_bitmask = 0x30D8FFFF,
 806         .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
 807                          (1U << CP0PG_RIE),
 808         .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
 809         .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
 810         .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
 811                     (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 812                     (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
 813         .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
 814         .CP1_fcr31_rw_bitmask = 0x0103FFFF,
 815         .MSAIR = 0x03 << MSAIR_ProcID,
 816         .SEGBITS = 48,
 817         .PABITS = 48,
 818         .insn_flags = CPU_MIPS64R6,
 819         .mmu_type = MMU_TYPE_R4000,
 820     },
 821     {
 822         .name = "Loongson-2E",
 823         .CP0_PRid = 0x6302,
 824         /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
 825         .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) |
 826                        (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0),
 827         /* Note: Config1 is only used internally,
 828            Loongson-2E has only Config0.  */
 829         .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
 830         .SYNCI_Step = 16,
 831         .CCRes = 2,
 832         .CP0_Status_rw_bitmask = 0x35D0FFFF,
 833         .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
 834         .CP1_fcr31 = 0,
 835         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 836         .SEGBITS = 40,
 837         .PABITS = 40,
 838         .insn_flags = CPU_MIPS3 | INSN_LOONGSON2E,
 839         .mmu_type = MMU_TYPE_R4000,
 840     },
 841     {
 842         .name = "Loongson-2F",
 843         .CP0_PRid = 0x6303,
 844         /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
 845         .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) |
 846                        (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0),
 847         /* Note: Config1 is only used internally,
 848            Loongson-2F has only Config0.  */
 849         .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
 850         .SYNCI_Step = 16,
 851         .CCRes = 2,
 852         .CP0_Status_rw_bitmask = 0xF5D0FF1F,   /* Bits 7:5 not writable.  */
 853         .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
 854         .CP1_fcr31 = 0,
 855         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 856         .SEGBITS = 40,
 857         .PABITS = 40,
 858         .insn_flags = CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI,
 859         .mmu_type = MMU_TYPE_R4000,
 860     },
 861     {
 862         .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */
 863         .CP0_PRid = 0x6305,
 864         /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
 865         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 866                        (MMU_TYPE_R4000 << CP0C0_MT),
 867         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
 868                        (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 869                        (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 870                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 871         .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) |
 872                        (3 << CP0C2_SA),
 873         .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
 874         .CP0_LLAddr_rw_bitmask = 0,
 875         .SYNCI_Step = 32,
 876         .CCRes = 2,
 877         .CP0_Status_rw_bitmask = 0x74D8FFFF,
 878         .CP0_PageGrain = (1 << CP0PG_ELPA),
 879         .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
 880         .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
 881                     (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
 882                     (0x1 << FCR0_D) | (0x1 << FCR0_S),
 883         .CP1_fcr31 = 0,
 884         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 885         .SEGBITS = 48,
 886         .PABITS = 48,
 887         .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
 888                       ASE_LMMI | ASE_LEXT,
 889         .mmu_type = MMU_TYPE_R4000,
 890     },
 891     {
 892         .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */
 893         .CP0_PRid = 0x14C000,
 894         /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
 895         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 896                        (MMU_TYPE_R4000 << CP0C0_MT),
 897         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
 898                        (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
 899                        (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
 900                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 901         .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
 902                        (15 << CP0C2_SA),
 903         .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
 904                        (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
 905                        (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
 906         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
 907                        (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist),
 908         .CP0_Config4_rw_bitmask = 0,
 909         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
 910         .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
 911                                   (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
 912                                   (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
 913         .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) |
 914                        (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) |
 915                        (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF),
 916         .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) |
 917                        (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) |
 918                        (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) |
 919                        (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) |
 920                        (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) |
 921                        (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) |
 922                        (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) |
 923                        (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) |
 924                        (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) |
 925                        (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) |
 926                        (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) |
 927                        (1 << CP0C6_DATAPREF),
 928         .CP0_Config7 = 0,
 929         .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) |
 930                                   (1 << CP0C7_VFPUCGEN),
 931         .CP0_LLAddr_rw_bitmask = 1,
 932         .SYNCI_Step = 16,
 933         .CCRes = 2,
 934         .CP0_Status_rw_bitmask = 0x7DDBFFFF,
 935         .CP0_PageGrain = (1 << CP0PG_ELPA),
 936         .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
 937                     (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
 938         .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
 939                     (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
 940                     (0x1 << FCR0_D) | (0x1 << FCR0_S),
 941         .CP1_fcr31 = 0,
 942         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 943         .MSAIR = (0x01 << MSAIR_ProcID) | (0x40 << MSAIR_Rev),
 944         .lcsr_cpucfg1 = (1 << CPUCFG1_FP) | (2 << CPUCFG1_FPREV) |
 945                     (1 << CPUCFG1_MSA1) | (1 << CPUCFG1_LSLDR0) |
 946                     (1 << CPUCFG1_LSPERF) | (1 << CPUCFG1_LSPERFX) |
 947                     (1 << CPUCFG1_LSSYNCI) | (1 << CPUCFG1_LLEXC) |
 948                     (1 << CPUCFG1_SCRAND) | (1 << CPUCFG1_MUALP) |
 949                     (1 << CPUCFG1_KMUALEN) | (1 << CPUCFG1_ITLBT) |
 950                     (1 << CPUCFG1_SFBP) | (1 << CPUCFG1_CDMAP),
 951         .lcsr_cpucfg2 = (1 << CPUCFG2_LEXT1) | (1 << CPUCFG2_LCSRP) |
 952                     (1 << CPUCFG2_LDISBLIKELY),
 953         .SEGBITS = 48,
 954         .PABITS = 48,
 955         .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
 956                       ASE_LMMI | ASE_LEXT,
 957         .mmu_type = MMU_TYPE_R4000,
 958     },
 959     {
 960         /* A generic CPU providing MIPS64 DSP R2 ASE features.
 961            FIXME: Eventually this should be replaced by a real CPU model. */
 962         .name = "mips64dspr2",
 963         .CP0_PRid = 0x00010000,
 964         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 965                        (MMU_TYPE_R4000 << CP0C0_MT),
 966         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
 967                        (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 968                        (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 969                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 970         .CP0_Config2 = MIPS_CONFIG2,
 971         .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
 972                        (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
 973         .CP0_LLAddr_rw_bitmask = 0,
 974         .CP0_LLAddr_shift = 0,
 975         .SYNCI_Step = 32,
 976         .CCRes = 2,
 977         .CP0_Status_rw_bitmask = 0x37FBFFFF,
 978         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
 979                     (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 980                     (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
 981         .CP1_fcr31 = 0,
 982         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 983         .SEGBITS = 42,
 984         .PABITS = 36,
 985         .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
 986         .mmu_type = MMU_TYPE_R4000,
 987     },
 988     {
 989         /*
 990          * Octeon 68xx with MIPS64 Cavium Octeon features.
 991          */
 992         .name = "Octeon68XX",
 993         .CP0_PRid = 0x000D9100,
 994         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 995                        (MMU_TYPE_R4000 << CP0C0_MT),
 996         .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
 997                        (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 998                        (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 999                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
1000         .CP0_Config2 = MIPS_CONFIG2,
1001         .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
1002         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
1003                        (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
1004                        (3U << CP0C4_MMUSizeExt),
1005         .CP0_LLAddr_rw_bitmask = 0,
1006         .CP0_LLAddr_shift = 4,
1007         .CP0_PageGrain = (1 << CP0PG_ELPA),
1008         .SYNCI_Step = 32,
1009         .CCRes = 2,
1010         .CP0_Status_rw_bitmask = 0x12F8FFFF,
1011         .SEGBITS = 42,
1012         .PABITS = 49,
1013         .insn_flags = CPU_MIPS64R2 | INSN_OCTEON,
1014         .mmu_type = MMU_TYPE_R4000,
1015     },
1016
1017 #endif
1018 };
1019 const int mips_defs_number = ARRAY_SIZE(mips_defs);
1020
1021 void mips_cpu_list(void)
1022 {
1023     int i;
1024
1025     for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
1026         qemu_printf("MIPS '%s'\n", mips_defs[i].name);
1027     }
1028 }
1029
1030 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
1031 {
1032     int i;
1033
1034     for (i = 0; i < MIPS_FPU_MAX; i++)
1035         env->fpus[i].fcr0 = def->CP1_fcr0;
1036
1037     memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
1038 }
1039
1040 static void mvp_init(CPUMIPSState *env)
1041 {
1042     env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
1043
1044     if (!ase_mt_available(env)) {
1045         return;
1046     }
1047
1048     /* MVPConf1 implemented, TLB sharable, no gating storage support,
1049        programmable cache partitioning implemented, number of allocatable
1050        and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
1051        implemented, 5 TCs implemented. */
1052     env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
1053                              (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
1054 // TODO: actually do 2 VPEs.
1055 //                             (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
1056 //                             (0x04 << CP0MVPC0_PTC);
1057                              (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
1058                              (0x00 << CP0MVPC0_PTC);
1059 #if !defined(CONFIG_USER_ONLY)
1060     /* Usermode has no TLB support */
1061     env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
1062 #endif
1063
1064     /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
1065        no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
1066     env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
1067                              (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
1068                              (0x1 << CP0MVPC1_PCP1);
1069 }