4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
26 #include "qemu/module.h"
27 #include "sysemu/kvm.h"
28 #include "exec/exec-all.h"
31 static void mips_cpu_set_pc(CPUState
*cs
, vaddr value
)
33 MIPSCPU
*cpu
= MIPS_CPU(cs
);
34 CPUMIPSState
*env
= &cpu
->env
;
36 env
->active_tc
.PC
= value
& ~(target_ulong
)1;
38 env
->hflags
|= MIPS_HFLAG_M16
;
40 env
->hflags
&= ~(MIPS_HFLAG_M16
);
44 static void mips_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
46 MIPSCPU
*cpu
= MIPS_CPU(cs
);
47 CPUMIPSState
*env
= &cpu
->env
;
49 env
->active_tc
.PC
= tb
->pc
;
50 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
51 env
->hflags
|= tb
->flags
& MIPS_HFLAG_BMASK
;
54 static bool mips_cpu_has_work(CPUState
*cs
)
56 MIPSCPU
*cpu
= MIPS_CPU(cs
);
57 CPUMIPSState
*env
= &cpu
->env
;
58 bool has_work
= false;
60 /* Prior to MIPS Release 6 it is implementation dependent if non-enabled
61 interrupts wake-up the CPU, however most of the implementations only
62 check for interrupts that can be taken. */
63 if ((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
64 cpu_mips_hw_interrupts_pending(env
)) {
65 if (cpu_mips_hw_interrupts_enabled(env
) ||
66 (env
->insn_flags
& ISA_MIPS32R6
)) {
71 /* MIPS-MT has the ability to halt the CPU. */
72 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
73 /* The QEMU model will issue an _WAKE request whenever the CPUs
74 should be woken up. */
75 if (cs
->interrupt_request
& CPU_INTERRUPT_WAKE
) {
79 if (!mips_vpe_active(env
)) {
83 /* MIPS Release 6 has the ability to halt the CPU. */
84 if (env
->CP0_Config5
& (1 << CP0C5_VP
)) {
85 if (cs
->interrupt_request
& CPU_INTERRUPT_WAKE
) {
88 if (!mips_vp_active(env
)) {
95 /* CPUClass::reset() */
96 static void mips_cpu_reset(CPUState
*s
)
98 MIPSCPU
*cpu
= MIPS_CPU(s
);
99 MIPSCPUClass
*mcc
= MIPS_CPU_GET_CLASS(cpu
);
100 CPUMIPSState
*env
= &cpu
->env
;
102 mcc
->parent_reset(s
);
104 memset(env
, 0, offsetof(CPUMIPSState
, end_reset_fields
));
106 cpu_state_reset(env
);
108 #ifndef CONFIG_USER_ONLY
110 kvm_mips_reset_vcpu(cpu
);
115 static void mips_cpu_disas_set_info(CPUState
*s
, disassemble_info
*info
) {
116 MIPSCPU
*cpu
= MIPS_CPU(s
);
117 CPUMIPSState
*env
= &cpu
->env
;
119 if (!(env
->insn_flags
& ISA_NANOMIPS32
)) {
120 #ifdef TARGET_WORDS_BIGENDIAN
121 info
->print_insn
= print_insn_big_mips
;
123 info
->print_insn
= print_insn_little_mips
;
126 #if defined(CONFIG_NANOMIPS_DIS)
127 info
->print_insn
= print_insn_nanomips
;
132 static void mips_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
134 CPUState
*cs
= CPU(dev
);
135 MIPSCPU
*cpu
= MIPS_CPU(dev
);
136 MIPSCPUClass
*mcc
= MIPS_CPU_GET_CLASS(dev
);
137 Error
*local_err
= NULL
;
139 cpu_exec_realizefn(cs
, &local_err
);
140 if (local_err
!= NULL
) {
141 error_propagate(errp
, local_err
);
145 cpu_mips_realize_env(&cpu
->env
);
150 mcc
->parent_realize(dev
, errp
);
153 static void mips_cpu_initfn(Object
*obj
)
155 MIPSCPU
*cpu
= MIPS_CPU(obj
);
156 CPUMIPSState
*env
= &cpu
->env
;
157 MIPSCPUClass
*mcc
= MIPS_CPU_GET_CLASS(obj
);
159 cpu_set_cpustate_pointers(cpu
);
160 env
->cpu_model
= mcc
->cpu_def
;
163 static char *mips_cpu_type_name(const char *cpu_model
)
165 return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model
);
168 static ObjectClass
*mips_cpu_class_by_name(const char *cpu_model
)
173 typename
= mips_cpu_type_name(cpu_model
);
174 oc
= object_class_by_name(typename
);
179 static void mips_cpu_class_init(ObjectClass
*c
, void *data
)
181 MIPSCPUClass
*mcc
= MIPS_CPU_CLASS(c
);
182 CPUClass
*cc
= CPU_CLASS(c
);
183 DeviceClass
*dc
= DEVICE_CLASS(c
);
185 device_class_set_parent_realize(dc
, mips_cpu_realizefn
,
186 &mcc
->parent_realize
);
187 mcc
->parent_reset
= cc
->reset
;
188 cc
->reset
= mips_cpu_reset
;
190 cc
->class_by_name
= mips_cpu_class_by_name
;
191 cc
->has_work
= mips_cpu_has_work
;
192 cc
->do_interrupt
= mips_cpu_do_interrupt
;
193 cc
->cpu_exec_interrupt
= mips_cpu_exec_interrupt
;
194 cc
->dump_state
= mips_cpu_dump_state
;
195 cc
->set_pc
= mips_cpu_set_pc
;
196 cc
->synchronize_from_tb
= mips_cpu_synchronize_from_tb
;
197 cc
->gdb_read_register
= mips_cpu_gdb_read_register
;
198 cc
->gdb_write_register
= mips_cpu_gdb_write_register
;
199 #ifndef CONFIG_USER_ONLY
200 cc
->do_unassigned_access
= mips_cpu_unassigned_access
;
201 cc
->do_unaligned_access
= mips_cpu_do_unaligned_access
;
202 cc
->get_phys_page_debug
= mips_cpu_get_phys_page_debug
;
203 cc
->vmsd
= &vmstate_mips_cpu
;
205 cc
->disas_set_info
= mips_cpu_disas_set_info
;
207 cc
->tcg_initialize
= mips_tcg_init
;
208 cc
->tlb_fill
= mips_cpu_tlb_fill
;
211 cc
->gdb_num_core_regs
= 73;
212 cc
->gdb_stop_before_watchpoint
= true;
215 static const TypeInfo mips_cpu_type_info
= {
216 .name
= TYPE_MIPS_CPU
,
218 .instance_size
= sizeof(MIPSCPU
),
219 .instance_init
= mips_cpu_initfn
,
221 .class_size
= sizeof(MIPSCPUClass
),
222 .class_init
= mips_cpu_class_init
,
225 static void mips_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
227 MIPSCPUClass
*mcc
= MIPS_CPU_CLASS(oc
);
231 static void mips_register_cpudef_type(const struct mips_def_t
*def
)
233 char *typename
= mips_cpu_type_name(def
->name
);
236 .parent
= TYPE_MIPS_CPU
,
237 .class_init
= mips_cpu_cpudef_class_init
,
238 .class_data
= (void *)def
,
245 static void mips_cpu_register_types(void)
249 type_register_static(&mips_cpu_type_info
);
250 for (i
= 0; i
< mips_defs_number
; i
++) {
251 mips_register_cpudef_type(&mips_defs
[i
]);
255 type_init(mips_cpu_register_types
)