target/mips/cpu.c

   1 /*
   2  * QEMU MIPS CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/cutils.h"
  23 #include "qemu/qemu-print.h"
  24 #include "qapi/error.h"
  25 #include "cpu.h"
  26 #include "internal.h"
  27 #include "kvm_mips.h"
  28 #include "qemu/module.h"
  29 #include "sysemu/kvm.h"
  30 #include "sysemu/qtest.h"
  31 #include "exec/exec-all.h"
  32 #include "hw/qdev-properties.h"
  33 #include "hw/qdev-clock.h"
  34 #include "semihosting/semihost.h"
  35 #include "qapi/qapi-commands-machine-target.h"
  36 #include "fpu_helper.h"
  37
  38 const char regnames[32][4] = {
  39     "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
  40     "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
  41     "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
  42     "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
  43 };
  44
  45 #if !defined(CONFIG_USER_ONLY)
  46
  47 /* Called for updates to CP0_Status.  */
  48 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
  49 {
  50     int32_t tcstatus, *tcst;
  51     uint32_t v = cpu->CP0_Status;
  52     uint32_t cu, mx, asid, ksu;
  53     uint32_t mask = ((1 << CP0TCSt_TCU3)
  54                        | (1 << CP0TCSt_TCU2)
  55                        | (1 << CP0TCSt_TCU1)
  56                        | (1 << CP0TCSt_TCU0)
  57                        | (1 << CP0TCSt_TMX)
  58                        | (3 << CP0TCSt_TKSU)
  59                        | (0xff << CP0TCSt_TASID));
  60
  61     cu = (v >> CP0St_CU0) & 0xf;
  62     mx = (v >> CP0St_MX) & 0x1;
  63     ksu = (v >> CP0St_KSU) & 0x3;
  64     asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
  65
  66     tcstatus = cu << CP0TCSt_TCU0;
  67     tcstatus |= mx << CP0TCSt_TMX;
  68     tcstatus |= ksu << CP0TCSt_TKSU;
  69     tcstatus |= asid;
  70
  71     if (tc == cpu->current_tc) {
  72         tcst = &cpu->active_tc.CP0_TCStatus;
  73     } else {
  74         tcst = &cpu->tcs[tc].CP0_TCStatus;
  75     }
  76
  77     *tcst &= ~mask;
  78     *tcst |= tcstatus;
  79     compute_hflags(cpu);
  80 }
  81
  82 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
  83 {
  84     uint32_t mask = env->CP0_Status_rw_bitmask;
  85     target_ulong old = env->CP0_Status;
  86
  87     if (env->insn_flags & ISA_MIPS_R6) {
  88         bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
  89 #if defined(TARGET_MIPS64)
  90         uint32_t ksux = (1 << CP0St_KX) & val;
  91         ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
  92         ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
  93         val = (val & ~(7 << CP0St_UX)) | ksux;
  94 #endif
  95         if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
  96             mask &= ~(3 << CP0St_KSU);
  97         }
  98         mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
  99     }
 100
 101     env->CP0_Status = (old & ~mask) | (val & mask);
 102 #if defined(TARGET_MIPS64)
 103     if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
 104         /* Access to at least one of the 64-bit segments has been disabled */
 105         tlb_flush(env_cpu(env));
 106     }
 107 #endif
 108     if (ase_mt_available(env)) {
 109         sync_c0_status(env, env, env->current_tc);
 110     } else {
 111         compute_hflags(env);
 112     }
 113 }
 114
 115 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
 116 {
 117     uint32_t mask = 0x00C00300;
 118     uint32_t old = env->CP0_Cause;
 119     int i;
 120
 121     if (env->insn_flags & ISA_MIPS_R2) {
 122         mask |= 1 << CP0Ca_DC;
 123     }
 124     if (env->insn_flags & ISA_MIPS_R6) {
 125         mask &= ~((1 << CP0Ca_WP) & val);
 126     }
 127
 128     env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
 129
 130     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
 131         if (env->CP0_Cause & (1 << CP0Ca_DC)) {
 132             cpu_mips_stop_count(env);
 133         } else {
 134             cpu_mips_start_count(env);
 135         }
 136     }
 137
 138     /* Set/reset software interrupts */
 139     for (i = 0 ; i < 2 ; i++) {
 140         if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
 141             cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
 142         }
 143     }
 144 }
 145
 146 #endif /* !CONFIG_USER_ONLY */
 147
 148 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
 149 {
 150     int i;
 151     int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
 152
 153 #define printfpr(fp)                                                    \
 154     do {                                                                \
 155         if (is_fpu64)                                                   \
 156             qemu_fprintf(f, "w:%08x d:%016" PRIx64                      \
 157                          " fd:%13g fs:%13g psu: %13g\n",                \
 158                          (fp)->w[FP_ENDIAN_IDX], (fp)->d,               \
 159                          (double)(fp)->fd,                              \
 160                          (double)(fp)->fs[FP_ENDIAN_IDX],               \
 161                          (double)(fp)->fs[!FP_ENDIAN_IDX]);             \
 162         else {                                                          \
 163             fpr_t tmp;                                                  \
 164             tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX];              \
 165             tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX];       \
 166             qemu_fprintf(f, "w:%08x d:%016" PRIx64                      \
 167                          " fd:%13g fs:%13g psu:%13g\n",                 \
 168                          tmp.w[FP_ENDIAN_IDX], tmp.d,                   \
 169                          (double)tmp.fd,                                \
 170                          (double)tmp.fs[FP_ENDIAN_IDX],                 \
 171                          (double)tmp.fs[!FP_ENDIAN_IDX]);               \
 172         }                                                               \
 173     } while (0)
 174
 175
 176     qemu_fprintf(f,
 177                  "CP1 FCR0 0x%08x  FCR31 0x%08x  SR.FR %d  fp_status 0x%02x\n",
 178                  env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
 179                  get_float_exception_flags(&env->active_fpu.fp_status));
 180     for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
 181         qemu_fprintf(f, "%3s: ", fregnames[i]);
 182         printfpr(&env->active_fpu.fpr[i]);
 183     }
 184
 185 #undef printfpr
 186 }
 187
 188 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 189 {
 190     MIPSCPU *cpu = MIPS_CPU(cs);
 191     CPUMIPSState *env = &cpu->env;
 192     int i;
 193
 194     qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
 195                  " LO=0x" TARGET_FMT_lx " ds %04x "
 196                  TARGET_FMT_lx " " TARGET_FMT_ld "\n",
 197                  env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
 198                  env->hflags, env->btarget, env->bcond);
 199     for (i = 0; i < 32; i++) {
 200         if ((i & 3) == 0) {
 201             qemu_fprintf(f, "GPR%02d:", i);
 202         }
 203         qemu_fprintf(f, " %s " TARGET_FMT_lx,
 204                      regnames[i], env->active_tc.gpr[i]);
 205         if ((i & 3) == 3) {
 206             qemu_fprintf(f, "\n");
 207         }
 208     }
 209
 210     qemu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x"
 211                  TARGET_FMT_lx "\n",
 212                  env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
 213     qemu_fprintf(f, "    Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
 214                  PRIx64 "\n",
 215                  env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
 216     qemu_fprintf(f, "    Config2 0x%08x Config3 0x%08x\n",
 217                  env->CP0_Config2, env->CP0_Config3);
 218     qemu_fprintf(f, "    Config4 0x%08x Config5 0x%08x\n",
 219                  env->CP0_Config4, env->CP0_Config5);
 220     if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
 221         fpu_dump_state(env, f, flags);
 222     }
 223 }
 224
 225 static const char * const excp_names[EXCP_LAST + 1] = {
 226     [EXCP_RESET] = "reset",
 227     [EXCP_SRESET] = "soft reset",
 228     [EXCP_DSS] = "debug single step",
 229     [EXCP_DINT] = "debug interrupt",
 230     [EXCP_NMI] = "non-maskable interrupt",
 231     [EXCP_MCHECK] = "machine check",
 232     [EXCP_EXT_INTERRUPT] = "interrupt",
 233     [EXCP_DFWATCH] = "deferred watchpoint",
 234     [EXCP_DIB] = "debug instruction breakpoint",
 235     [EXCP_IWATCH] = "instruction fetch watchpoint",
 236     [EXCP_AdEL] = "address error load",
 237     [EXCP_AdES] = "address error store",
 238     [EXCP_TLBF] = "TLB refill",
 239     [EXCP_IBE] = "instruction bus error",
 240     [EXCP_DBp] = "debug breakpoint",
 241     [EXCP_SYSCALL] = "syscall",
 242     [EXCP_BREAK] = "break",
 243     [EXCP_CpU] = "coprocessor unusable",
 244     [EXCP_RI] = "reserved instruction",
 245     [EXCP_OVERFLOW] = "arithmetic overflow",
 246     [EXCP_TRAP] = "trap",
 247     [EXCP_FPE] = "floating point",
 248     [EXCP_DDBS] = "debug data break store",
 249     [EXCP_DWATCH] = "data watchpoint",
 250     [EXCP_LTLBL] = "TLB modify",
 251     [EXCP_TLBL] = "TLB load",
 252     [EXCP_TLBS] = "TLB store",
 253     [EXCP_DBE] = "data bus error",
 254     [EXCP_DDBL] = "debug data break load",
 255     [EXCP_THREAD] = "thread",
 256     [EXCP_MDMX] = "MDMX",
 257     [EXCP_C2E] = "precise coprocessor 2",
 258     [EXCP_CACHE] = "cache error",
 259     [EXCP_TLBXI] = "TLB execute-inhibit",
 260     [EXCP_TLBRI] = "TLB read-inhibit",
 261     [EXCP_MSADIS] = "MSA disabled",
 262     [EXCP_MSAFPE] = "MSA floating point",
 263 };
 264
 265 const char *mips_exception_name(int32_t exception)
 266 {
 267     if (exception < 0 || exception > EXCP_LAST) {
 268         return "unknown";
 269     }
 270     return excp_names[exception];
 271 }
 272
 273 void cpu_set_exception_base(int vp_index, target_ulong address)
 274 {
 275     MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
 276     vp->env.exception_base = address;
 277 }
 278
 279 target_ulong exception_resume_pc(CPUMIPSState *env)
 280 {
 281     target_ulong bad_pc;
 282     target_ulong isa_mode;
 283
 284     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 285     bad_pc = env->active_tc.PC | isa_mode;
 286     if (env->hflags & MIPS_HFLAG_BMASK) {
 287         /*
 288          * If the exception was raised from a delay slot, come back to
 289          * the jump.
 290          */
 291         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 292     }
 293
 294     return bad_pc;
 295 }
 296
 297 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 298 {
 299     if (interrupt_request & CPU_INTERRUPT_HARD) {
 300         MIPSCPU *cpu = MIPS_CPU(cs);
 301         CPUMIPSState *env = &cpu->env;
 302
 303         if (cpu_mips_hw_interrupts_enabled(env) &&
 304             cpu_mips_hw_interrupts_pending(env)) {
 305             /* Raise it */
 306             cs->exception_index = EXCP_EXT_INTERRUPT;
 307             env->error_code = 0;
 308             mips_cpu_do_interrupt(cs);
 309             return true;
 310         }
 311     }
 312     return false;
 313 }
 314
 315 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
 316                                           uint32_t exception,
 317                                           int error_code,
 318                                           uintptr_t pc)
 319 {
 320     CPUState *cs = env_cpu(env);
 321
 322     qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
 323                   __func__, exception, mips_exception_name(exception),
 324                   error_code);
 325     cs->exception_index = exception;
 326     env->error_code = error_code;
 327
 328     cpu_loop_exit_restore(cs, pc);
 329 }
 330
 331 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
 332 {
 333     MIPSCPU *cpu = MIPS_CPU(cs);
 334     CPUMIPSState *env = &cpu->env;
 335
 336     env->active_tc.PC = value & ~(target_ulong)1;
 337     if (value & 1) {
 338         env->hflags |= MIPS_HFLAG_M16;
 339     } else {
 340         env->hflags &= ~(MIPS_HFLAG_M16);
 341     }
 342 }
 343
 344 #ifdef CONFIG_TCG
 345 static void mips_cpu_synchronize_from_tb(CPUState *cs,
 346                                          const TranslationBlock *tb)
 347 {
 348     MIPSCPU *cpu = MIPS_CPU(cs);
 349     CPUMIPSState *env = &cpu->env;
 350
 351     env->active_tc.PC = tb->pc;
 352     env->hflags &= ~MIPS_HFLAG_BMASK;
 353     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
 354 }
 355
 356 # ifndef CONFIG_USER_ONLY
 357 static bool mips_io_recompile_replay_branch(CPUState *cs,
 358                                             const TranslationBlock *tb)
 359 {
 360     MIPSCPU *cpu = MIPS_CPU(cs);
 361     CPUMIPSState *env = &cpu->env;
 362
 363     if ((env->hflags & MIPS_HFLAG_BMASK) != 0
 364         && env->active_tc.PC != tb->pc) {
 365         env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 366         env->hflags &= ~MIPS_HFLAG_BMASK;
 367         return true;
 368     }
 369     return false;
 370 }
 371 # endif /* !CONFIG_USER_ONLY */
 372 #endif /* CONFIG_TCG */
 373
 374 static bool mips_cpu_has_work(CPUState *cs)
 375 {
 376     MIPSCPU *cpu = MIPS_CPU(cs);
 377     CPUMIPSState *env = &cpu->env;
 378     bool has_work = false;
 379
 380     /*
 381      * Prior to MIPS Release 6 it is implementation dependent if non-enabled
 382      * interrupts wake-up the CPU, however most of the implementations only
 383      * check for interrupts that can be taken.
 384      */
 385     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
 386         cpu_mips_hw_interrupts_pending(env)) {
 387         if (cpu_mips_hw_interrupts_enabled(env) ||
 388             (env->insn_flags & ISA_MIPS_R6)) {
 389             has_work = true;
 390         }
 391     }
 392
 393     /* MIPS-MT has the ability to halt the CPU.  */
 394     if (ase_mt_available(env)) {
 395         /*
 396          * The QEMU model will issue an _WAKE request whenever the CPUs
 397          * should be woken up.
 398          */
 399         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
 400             has_work = true;
 401         }
 402
 403         if (!mips_vpe_active(env)) {
 404             has_work = false;
 405         }
 406     }
 407     /* MIPS Release 6 has the ability to halt the CPU.  */
 408     if (env->CP0_Config5 & (1 << CP0C5_VP)) {
 409         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
 410             has_work = true;
 411         }
 412         if (!mips_vp_active(env)) {
 413             has_work = false;
 414         }
 415     }
 416     return has_work;
 417 }
 418
 419 #include "cpu-defs.c.inc"
 420
 421 static void mips_cpu_reset(DeviceState *dev)
 422 {
 423     CPUState *cs = CPU(dev);
 424     MIPSCPU *cpu = MIPS_CPU(cs);
 425     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
 426     CPUMIPSState *env = &cpu->env;
 427
 428     mcc->parent_reset(dev);
 429
 430     memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
 431
 432     /* Reset registers to their default values */
 433     env->CP0_PRid = env->cpu_model->CP0_PRid;
 434     env->CP0_Config0 = env->cpu_model->CP0_Config0;
 435 #ifdef TARGET_WORDS_BIGENDIAN
 436     env->CP0_Config0 |= (1 << CP0C0_BE);
 437 #endif
 438     env->CP0_Config1 = env->cpu_model->CP0_Config1;
 439     env->CP0_Config2 = env->cpu_model->CP0_Config2;
 440     env->CP0_Config3 = env->cpu_model->CP0_Config3;
 441     env->CP0_Config4 = env->cpu_model->CP0_Config4;
 442     env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
 443     env->CP0_Config5 = env->cpu_model->CP0_Config5;
 444     env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
 445     env->CP0_Config6 = env->cpu_model->CP0_Config6;
 446     env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
 447     env->CP0_Config7 = env->cpu_model->CP0_Config7;
 448     env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
 449     env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
 450                                  << env->cpu_model->CP0_LLAddr_shift;
 451     env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
 452     env->SYNCI_Step = env->cpu_model->SYNCI_Step;
 453     env->CCRes = env->cpu_model->CCRes;
 454     env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
 455     env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
 456     env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
 457     env->current_tc = 0;
 458     env->SEGBITS = env->cpu_model->SEGBITS;
 459     env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
 460 #if defined(TARGET_MIPS64)
 461     if (env->cpu_model->insn_flags & ISA_MIPS3) {
 462         env->SEGMask |= 3ULL << 62;
 463     }
 464 #endif
 465     env->PABITS = env->cpu_model->PABITS;
 466     env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
 467     env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
 468     env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
 469     env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
 470     env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
 471     env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
 472     env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
 473     env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
 474     env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
 475     env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
 476     env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
 477     env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
 478     env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask;
 479     env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
 480     env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
 481     env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
 482     env->msair = env->cpu_model->MSAIR;
 483     env->insn_flags = env->cpu_model->insn_flags;
 484
 485 #if defined(CONFIG_USER_ONLY)
 486     env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
 487 # ifdef TARGET_MIPS64
 488     /* Enable 64-bit register mode.  */
 489     env->CP0_Status |= (1 << CP0St_PX);
 490 # endif
 491 # ifdef TARGET_ABI_MIPSN64
 492     /* Enable 64-bit address mode.  */
 493     env->CP0_Status |= (1 << CP0St_UX);
 494 # endif
 495     /*
 496      * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
 497      * hardware registers.
 498      */
 499     env->CP0_HWREna |= 0x0000000F;
 500     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
 501         env->CP0_Status |= (1 << CP0St_CU1);
 502     }
 503     if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
 504         env->CP0_Status |= (1 << CP0St_MX);
 505     }
 506 # if defined(TARGET_MIPS64)
 507     /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
 508     if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
 509         (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
 510         env->CP0_Status |= (1 << CP0St_FR);
 511     }
 512 # endif
 513 #else /* !CONFIG_USER_ONLY */
 514     if (env->hflags & MIPS_HFLAG_BMASK) {
 515         /*
 516          * If the exception was raised from a delay slot,
 517          * come back to the jump.
 518          */
 519         env->CP0_ErrorEPC = (env->active_tc.PC
 520                              - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
 521     } else {
 522         env->CP0_ErrorEPC = env->active_tc.PC;
 523     }
 524     env->active_tc.PC = env->exception_base;
 525     env->CP0_Random = env->tlb->nb_tlb - 1;
 526     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 527     env->CP0_Wired = 0;
 528     env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
 529     env->CP0_EBase = (cs->cpu_index & 0x3FF);
 530     if (mips_um_ksegs_enabled()) {
 531         env->CP0_EBase |= 0x40000000;
 532     } else {
 533         env->CP0_EBase |= (int32_t)0x80000000;
 534     }
 535     if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
 536         env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
 537     }
 538     env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
 539             0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
 540     env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
 541     /*
 542      * Vectored interrupts not implemented, timer on int 7,
 543      * no performance counters.
 544      */
 545     env->CP0_IntCtl = 0xe0000000;
 546     {
 547         int i;
 548
 549         for (i = 0; i < 7; i++) {
 550             env->CP0_WatchLo[i] = 0;
 551             env->CP0_WatchHi[i] = 0x80000000;
 552         }
 553         env->CP0_WatchLo[7] = 0;
 554         env->CP0_WatchHi[7] = 0;
 555     }
 556     /* Count register increments in debug mode, EJTAG version 1 */
 557     env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
 558
 559     cpu_mips_store_count(env, 1);
 560
 561     if (ase_mt_available(env)) {
 562         int i;
 563
 564         /* Only TC0 on VPE 0 starts as active.  */
 565         for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
 566             env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
 567             env->tcs[i].CP0_TCHalt = 1;
 568         }
 569         env->active_tc.CP0_TCHalt = 1;
 570         cs->halted = 1;
 571
 572         if (cs->cpu_index == 0) {
 573             /* VPE0 starts up enabled.  */
 574             env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
 575             env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
 576
 577             /* TC0 starts up unhalted.  */
 578             cs->halted = 0;
 579             env->active_tc.CP0_TCHalt = 0;
 580             env->tcs[0].CP0_TCHalt = 0;
 581             /* With thread 0 active.  */
 582             env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
 583             env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
 584         }
 585     }
 586
 587     /*
 588      * Configure default legacy segmentation control. We use this regardless of
 589      * whether segmentation control is presented to the guest.
 590      */
 591     /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
 592     env->CP0_SegCtl0 =   (CP0SC_AM_MK << CP0SC_AM);
 593     /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
 594     env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16;
 595     /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
 596     env->CP0_SegCtl1 =   (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
 597                          (2 << CP0SC_C);
 598     /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
 599     env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
 600                          (3 << CP0SC_C)) << 16;
 601     /* USeg (seg4 0x40000000..0x7FFFFFFF) */
 602     env->CP0_SegCtl2 =   (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
 603                          (1 << CP0SC_EU) | (2 << CP0SC_C);
 604     /* USeg (seg5 0x00000000..0x3FFFFFFF) */
 605     env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
 606                          (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16;
 607     /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
 608     env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
 609 #endif /* !CONFIG_USER_ONLY */
 610     if ((env->insn_flags & ISA_MIPS_R6) &&
 611         (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
 612         /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
 613         env->CP0_Status |= (1 << CP0St_FR);
 614     }
 615
 616     if (env->insn_flags & ISA_MIPS_R6) {
 617         /* PTW  =  1 */
 618         env->CP0_PWSize = 0x40;
 619         /* GDI  = 12 */
 620         /* UDI  = 12 */
 621         /* MDI  = 12 */
 622         /* PRI  = 12 */
 623         /* PTEI =  2 */
 624         env->CP0_PWField = 0x0C30C302;
 625     } else {
 626         /* GDI  =  0 */
 627         /* UDI  =  0 */
 628         /* MDI  =  0 */
 629         /* PRI  =  0 */
 630         /* PTEI =  2 */
 631         env->CP0_PWField = 0x02;
 632     }
 633
 634     if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
 635         /*  microMIPS on reset when Config3.ISA is 3 */
 636         env->hflags |= MIPS_HFLAG_M16;
 637     }
 638
 639     msa_reset(env);
 640
 641     compute_hflags(env);
 642     restore_fp_status(env);
 643     restore_pamask(env);
 644     cs->exception_index = EXCP_NONE;
 645
 646     if (semihosting_get_argc()) {
 647         /* UHI interface can be used to obtain argc and argv */
 648         env->active_tc.gpr[4] = -1;
 649     }
 650
 651 #ifndef CONFIG_USER_ONLY
 652     if (kvm_enabled()) {
 653         kvm_mips_reset_vcpu(cpu);
 654     }
 655 #endif
 656 }
 657
 658 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 659 {
 660     MIPSCPU *cpu = MIPS_CPU(s);
 661     CPUMIPSState *env = &cpu->env;
 662
 663     if (!(env->insn_flags & ISA_NANOMIPS32)) {
 664 #ifdef TARGET_WORDS_BIGENDIAN
 665         info->print_insn = print_insn_big_mips;
 666 #else
 667         info->print_insn = print_insn_little_mips;
 668 #endif
 669     } else {
 670 #if defined(CONFIG_NANOMIPS_DIS)
 671         info->print_insn = print_insn_nanomips;
 672 #endif
 673     }
 674 }
 675
 676 /*
 677  * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
 678  */
 679 #define CPU_FREQ_HZ_DEFAULT     200000000
 680 #define CP0_COUNT_RATE_DEFAULT  2
 681
 682 static void mips_cp0_period_set(MIPSCPU *cpu)
 683 {
 684     CPUMIPSState *env = &cpu->env;
 685
 686     env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
 687                                           cpu->cp0_count_rate);
 688     assert(env->cp0_count_ns);
 689 }
 690
 691 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
 692 {
 693     CPUState *cs = CPU(dev);
 694     MIPSCPU *cpu = MIPS_CPU(dev);
 695     CPUMIPSState *env = &cpu->env;
 696     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
 697     Error *local_err = NULL;
 698
 699     if (!clock_get(cpu->clock)) {
 700 #ifndef CONFIG_USER_ONLY
 701         if (!qtest_enabled()) {
 702             g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT);
 703
 704             warn_report("CPU input clock is not connected to any output clock, "
 705                         "using default frequency of %s.", cpu_freq_str);
 706         }
 707 #endif
 708         /* Initialize the frequency in case the clock remains unconnected. */
 709         clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT);
 710     }
 711     mips_cp0_period_set(cpu);
 712
 713     cpu_exec_realizefn(cs, &local_err);
 714     if (local_err != NULL) {
 715         error_propagate(errp, local_err);
 716         return;
 717     }
 718
 719     env->exception_base = (int32_t)0xBFC00000;
 720
 721 #ifndef CONFIG_USER_ONLY
 722     mmu_init(env, env->cpu_model);
 723 #endif
 724     fpu_init(env, env->cpu_model);
 725     mvp_init(env);
 726
 727     cpu_reset(cs);
 728     qemu_init_vcpu(cs);
 729
 730     mcc->parent_realize(dev, errp);
 731 }
 732
 733 static void mips_cpu_initfn(Object *obj)
 734 {
 735     MIPSCPU *cpu = MIPS_CPU(obj);
 736     CPUMIPSState *env = &cpu->env;
 737     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
 738
 739     cpu_set_cpustate_pointers(cpu);
 740     cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
 741     env->cpu_model = mcc->cpu_def;
 742 }
 743
 744 static char *mips_cpu_type_name(const char *cpu_model)
 745 {
 746     return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
 747 }
 748
 749 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
 750 {
 751     ObjectClass *oc;
 752     char *typename;
 753
 754     typename = mips_cpu_type_name(cpu_model);
 755     oc = object_class_by_name(typename);
 756     g_free(typename);
 757     return oc;
 758 }
 759
 760 static Property mips_cpu_properties[] = {
 761     /* CP0 timer running at half the clock of the CPU */
 762     DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate,
 763                        CP0_COUNT_RATE_DEFAULT),
 764     DEFINE_PROP_END_OF_LIST()
 765 };
 766
 767 #ifdef CONFIG_TCG
 768 #include "hw/core/tcg-cpu-ops.h"
 769 /*
 770  * NB: cannot be const, as some elements are changed for specific
 771  * mips hardware (see hw/mips/jazz.c).
 772  */
 773 static struct TCGCPUOps mips_tcg_ops = {
 774     .initialize = mips_tcg_init,
 775     .synchronize_from_tb = mips_cpu_synchronize_from_tb,
 776     .cpu_exec_interrupt = mips_cpu_exec_interrupt,
 777     .tlb_fill = mips_cpu_tlb_fill,
 778
 779 #if !defined(CONFIG_USER_ONLY)
 780     .do_interrupt = mips_cpu_do_interrupt,
 781     .do_transaction_failed = mips_cpu_do_transaction_failed,
 782     .do_unaligned_access = mips_cpu_do_unaligned_access,
 783     .io_recompile_replay_branch = mips_io_recompile_replay_branch,
 784 #endif /* !CONFIG_USER_ONLY */
 785 };
 786 #endif /* CONFIG_TCG */
 787
 788 static void mips_cpu_class_init(ObjectClass *c, void *data)
 789 {
 790     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
 791     CPUClass *cc = CPU_CLASS(c);
 792     DeviceClass *dc = DEVICE_CLASS(c);
 793
 794     device_class_set_parent_realize(dc, mips_cpu_realizefn,
 795                                     &mcc->parent_realize);
 796     device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
 797     device_class_set_props(dc, mips_cpu_properties);
 798
 799     cc->class_by_name = mips_cpu_class_by_name;
 800     cc->has_work = mips_cpu_has_work;
 801     cc->dump_state = mips_cpu_dump_state;
 802     cc->set_pc = mips_cpu_set_pc;
 803     cc->gdb_read_register = mips_cpu_gdb_read_register;
 804     cc->gdb_write_register = mips_cpu_gdb_write_register;
 805 #ifndef CONFIG_USER_ONLY
 806     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 807     cc->vmsd = &vmstate_mips_cpu;
 808 #endif
 809     cc->disas_set_info = mips_cpu_disas_set_info;
 810     cc->gdb_num_core_regs = 73;
 811     cc->gdb_stop_before_watchpoint = true;
 812 #ifdef CONFIG_TCG
 813     cc->tcg_ops = &mips_tcg_ops;
 814 #endif /* CONFIG_TCG */
 815 }
 816
 817 static const TypeInfo mips_cpu_type_info = {
 818     .name = TYPE_MIPS_CPU,
 819     .parent = TYPE_CPU,
 820     .instance_size = sizeof(MIPSCPU),
 821     .instance_init = mips_cpu_initfn,
 822     .abstract = true,
 823     .class_size = sizeof(MIPSCPUClass),
 824     .class_init = mips_cpu_class_init,
 825 };
 826
 827 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
 828 {
 829     MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
 830     mcc->cpu_def = data;
 831 }
 832
 833 static void mips_register_cpudef_type(const struct mips_def_t *def)
 834 {
 835     char *typename = mips_cpu_type_name(def->name);
 836     TypeInfo ti = {
 837         .name = typename,
 838         .parent = TYPE_MIPS_CPU,
 839         .class_init = mips_cpu_cpudef_class_init,
 840         .class_data = (void *)def,
 841     };
 842
 843     type_register(&ti);
 844     g_free(typename);
 845 }
 846
 847 static void mips_cpu_register_types(void)
 848 {
 849     int i;
 850
 851     type_register_static(&mips_cpu_type_info);
 852     for (i = 0; i < mips_defs_number; i++) {
 853         mips_register_cpudef_type(&mips_defs[i]);
 854     }
 855 }
 856
 857 type_init(mips_cpu_register_types)
 858
 859 static void mips_cpu_add_definition(gpointer data, gpointer user_data)
 860 {
 861     ObjectClass *oc = data;
 862     CpuDefinitionInfoList **cpu_list = user_data;
 863     CpuDefinitionInfo *info;
 864     const char *typename;
 865
 866     typename = object_class_get_name(oc);
 867     info = g_malloc0(sizeof(*info));
 868     info->name = g_strndup(typename,
 869                            strlen(typename) - strlen("-" TYPE_MIPS_CPU));
 870     info->q_typename = g_strdup(typename);
 871
 872     QAPI_LIST_PREPEND(*cpu_list, info);
 873 }
 874
 875 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 876 {
 877     CpuDefinitionInfoList *cpu_list = NULL;
 878     GSList *list;
 879
 880     list = object_class_get_list(TYPE_MIPS_CPU, false);
 881     g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
 882     g_slist_free(list);
 883
 884     return cpu_list;
 885 }
 886
 887 /* Could be used by generic CPU object */
 888 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
 889 {
 890     DeviceState *cpu;
 891
 892     cpu = DEVICE(object_new(cpu_type));
 893     qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
 894     qdev_realize(cpu, NULL, &error_abort);
 895
 896     return MIPS_CPU(cpu);
 897 }
 898
 899 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
 900 {
 901     return (env->cpu_model->insn_flags & isa_mask) != 0;
 902 }
 903
 904 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa)
 905 {
 906     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
 907     return (mcc->cpu_def->insn_flags & isa) != 0;
 908 }
 909
 910 bool cpu_type_supports_cps_smp(const char *cpu_type)
 911 {
 912     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
 913     return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
 914 }