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target/mips: fpu: Demacro MADD.<D|S|PS>
[mirror_qemu.git] / target / mips / fpu_helper.c
1 /*
2 * Helpers for emulation of FPU-related MIPS instructions.
3 *
4 * Copyright (C) 2004-2005 Jocelyn Mayer
5 * Copyright (C) 2020 Wave Computing, Inc.
6 * Copyright (C) 2020 Aleksandar Markovic <amarkovic@wavecomp.com>
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22
23 #include "qemu/osdep.h"
24 #include "qemu/main-loop.h"
25 #include "cpu.h"
26 #include "internal.h"
27 #include "qemu/host-utils.h"
28 #include "exec/helper-proto.h"
29 #include "exec/exec-all.h"
30 #include "exec/cpu_ldst.h"
31 #include "exec/memop.h"
32 #include "sysemu/kvm.h"
33 #include "fpu/softfloat.h"
34
35
36 /* Complex FPU operations which may need stack space. */
37
38 #define FLOAT_TWO32 make_float32(1 << 30)
39 #define FLOAT_TWO64 make_float64(1ULL << 62)
40
41 #define FP_TO_INT32_OVERFLOW 0x7fffffff
42 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
43
44 /* convert MIPS rounding mode in FCR31 to IEEE library */
45 unsigned int ieee_rm[] = {
46 float_round_nearest_even,
47 float_round_to_zero,
48 float_round_up,
49 float_round_down
50 };
51
52 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
53 {
54 target_ulong arg1 = 0;
55
56 switch (reg) {
57 case 0:
58 arg1 = (int32_t)env->active_fpu.fcr0;
59 break;
60 case 1:
61 /* UFR Support - Read Status FR */
62 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
63 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
64 arg1 = (int32_t)
65 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
66 } else {
67 do_raise_exception(env, EXCP_RI, GETPC());
68 }
69 }
70 break;
71 case 5:
72 /* FRE Support - read Config5.FRE bit */
73 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
74 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
75 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
76 } else {
77 helper_raise_exception(env, EXCP_RI);
78 }
79 }
80 break;
81 case 25:
82 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) |
83 ((env->active_fpu.fcr31 >> 23) & 0x1);
84 break;
85 case 26:
86 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
87 break;
88 case 28:
89 arg1 = (env->active_fpu.fcr31 & 0x00000f83) |
90 ((env->active_fpu.fcr31 >> 22) & 0x4);
91 break;
92 default:
93 arg1 = (int32_t)env->active_fpu.fcr31;
94 break;
95 }
96
97 return arg1;
98 }
99
100 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
101 {
102 switch (fs) {
103 case 1:
104 /* UFR Alias - Reset Status FR */
105 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
106 return;
107 }
108 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
109 env->CP0_Status &= ~(1 << CP0St_FR);
110 compute_hflags(env);
111 } else {
112 do_raise_exception(env, EXCP_RI, GETPC());
113 }
114 break;
115 case 4:
116 /* UNFR Alias - Set Status FR */
117 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
118 return;
119 }
120 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
121 env->CP0_Status |= (1 << CP0St_FR);
122 compute_hflags(env);
123 } else {
124 do_raise_exception(env, EXCP_RI, GETPC());
125 }
126 break;
127 case 5:
128 /* FRE Support - clear Config5.FRE bit */
129 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
130 return;
131 }
132 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
133 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
134 compute_hflags(env);
135 } else {
136 helper_raise_exception(env, EXCP_RI);
137 }
138 break;
139 case 6:
140 /* FRE Support - set Config5.FRE bit */
141 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
142 return;
143 }
144 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
145 env->CP0_Config5 |= (1 << CP0C5_FRE);
146 compute_hflags(env);
147 } else {
148 helper_raise_exception(env, EXCP_RI);
149 }
150 break;
151 case 25:
152 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
153 return;
154 }
155 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) |
156 ((arg1 & 0xfe) << 24) |
157 ((arg1 & 0x1) << 23);
158 break;
159 case 26:
160 if (arg1 & 0x007c0000) {
161 return;
162 }
163 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) |
164 (arg1 & 0x0003f07c);
165 break;
166 case 28:
167 if (arg1 & 0x007c0000) {
168 return;
169 }
170 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) |
171 (arg1 & 0x00000f83) |
172 ((arg1 & 0x4) << 22);
173 break;
174 case 31:
175 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
176 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
177 break;
178 default:
179 if (env->insn_flags & ISA_MIPS32R6) {
180 do_raise_exception(env, EXCP_RI, GETPC());
181 }
182 return;
183 }
184 restore_fp_status(env);
185 set_float_exception_flags(0, &env->active_fpu.fp_status);
186 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) &
187 GET_FP_CAUSE(env->active_fpu.fcr31)) {
188 do_raise_exception(env, EXCP_FPE, GETPC());
189 }
190 }
191
192 int ieee_ex_to_mips(int xcpt)
193 {
194 int ret = 0;
195 if (xcpt) {
196 if (xcpt & float_flag_invalid) {
197 ret |= FP_INVALID;
198 }
199 if (xcpt & float_flag_overflow) {
200 ret |= FP_OVERFLOW;
201 }
202 if (xcpt & float_flag_underflow) {
203 ret |= FP_UNDERFLOW;
204 }
205 if (xcpt & float_flag_divbyzero) {
206 ret |= FP_DIV0;
207 }
208 if (xcpt & float_flag_inexact) {
209 ret |= FP_INEXACT;
210 }
211 }
212 return ret;
213 }
214
215 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
216 {
217 int tmp = ieee_ex_to_mips(get_float_exception_flags(
218 &env->active_fpu.fp_status));
219
220 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
221
222 if (tmp) {
223 set_float_exception_flags(0, &env->active_fpu.fp_status);
224
225 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
226 do_raise_exception(env, EXCP_FPE, pc);
227 } else {
228 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
229 }
230 }
231 }
232
233 /*
234 * Float support.
235 * Single precition routines have a "s" suffix, double precision a
236 * "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
237 * paired single lower "pl", paired single upper "pu".
238 */
239
240 /* unary operations, modifying fp status */
241 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
242 {
243 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
244 update_fcr31(env, GETPC());
245 return fdt0;
246 }
247
248 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
249 {
250 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
251 update_fcr31(env, GETPC());
252 return fst0;
253 }
254
255 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
256 {
257 uint64_t fdt2;
258
259 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
260 update_fcr31(env, GETPC());
261 return fdt2;
262 }
263
264 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
265 {
266 uint64_t fdt2;
267
268 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
269 update_fcr31(env, GETPC());
270 return fdt2;
271 }
272
273 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
274 {
275 uint64_t fdt2;
276
277 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
278 update_fcr31(env, GETPC());
279 return fdt2;
280 }
281
282 uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
283 {
284 uint64_t dt2;
285
286 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
287 if (get_float_exception_flags(&env->active_fpu.fp_status)
288 & (float_flag_invalid | float_flag_overflow)) {
289 dt2 = FP_TO_INT64_OVERFLOW;
290 }
291 update_fcr31(env, GETPC());
292 return dt2;
293 }
294
295 uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
296 {
297 uint64_t dt2;
298
299 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
300 if (get_float_exception_flags(&env->active_fpu.fp_status)
301 & (float_flag_invalid | float_flag_overflow)) {
302 dt2 = FP_TO_INT64_OVERFLOW;
303 }
304 update_fcr31(env, GETPC());
305 return dt2;
306 }
307
308 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
309 {
310 uint32_t fst2;
311 uint32_t fsth2;
312
313 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
314 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
315 update_fcr31(env, GETPC());
316 return ((uint64_t)fsth2 << 32) | fst2;
317 }
318
319 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
320 {
321 uint32_t wt2;
322 uint32_t wth2;
323 int excp, excph;
324
325 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
326 excp = get_float_exception_flags(&env->active_fpu.fp_status);
327 if (excp & (float_flag_overflow | float_flag_invalid)) {
328 wt2 = FP_TO_INT32_OVERFLOW;
329 }
330
331 set_float_exception_flags(0, &env->active_fpu.fp_status);
332 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
333 excph = get_float_exception_flags(&env->active_fpu.fp_status);
334 if (excph & (float_flag_overflow | float_flag_invalid)) {
335 wth2 = FP_TO_INT32_OVERFLOW;
336 }
337
338 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
339 update_fcr31(env, GETPC());
340
341 return ((uint64_t)wth2 << 32) | wt2;
342 }
343
344 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
345 {
346 uint32_t fst2;
347
348 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
349 update_fcr31(env, GETPC());
350 return fst2;
351 }
352
353 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
354 {
355 uint32_t fst2;
356
357 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
358 update_fcr31(env, GETPC());
359 return fst2;
360 }
361
362 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
363 {
364 uint32_t fst2;
365
366 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
367 update_fcr31(env, GETPC());
368 return fst2;
369 }
370
371 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
372 {
373 uint32_t wt2;
374
375 wt2 = wt0;
376 update_fcr31(env, GETPC());
377 return wt2;
378 }
379
380 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
381 {
382 uint32_t wt2;
383
384 wt2 = wth0;
385 update_fcr31(env, GETPC());
386 return wt2;
387 }
388
389 uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
390 {
391 uint32_t wt2;
392
393 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
394 if (get_float_exception_flags(&env->active_fpu.fp_status)
395 & (float_flag_invalid | float_flag_overflow)) {
396 wt2 = FP_TO_INT32_OVERFLOW;
397 }
398 update_fcr31(env, GETPC());
399 return wt2;
400 }
401
402 uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
403 {
404 uint32_t wt2;
405
406 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
407 if (get_float_exception_flags(&env->active_fpu.fp_status)
408 & (float_flag_invalid | float_flag_overflow)) {
409 wt2 = FP_TO_INT32_OVERFLOW;
410 }
411 update_fcr31(env, GETPC());
412 return wt2;
413 }
414
415 uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
416 {
417 uint64_t dt2;
418
419 set_float_rounding_mode(float_round_nearest_even,
420 &env->active_fpu.fp_status);
421 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
422 restore_rounding_mode(env);
423 if (get_float_exception_flags(&env->active_fpu.fp_status)
424 & (float_flag_invalid | float_flag_overflow)) {
425 dt2 = FP_TO_INT64_OVERFLOW;
426 }
427 update_fcr31(env, GETPC());
428 return dt2;
429 }
430
431 uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
432 {
433 uint64_t dt2;
434
435 set_float_rounding_mode(float_round_nearest_even,
436 &env->active_fpu.fp_status);
437 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
438 restore_rounding_mode(env);
439 if (get_float_exception_flags(&env->active_fpu.fp_status)
440 & (float_flag_invalid | float_flag_overflow)) {
441 dt2 = FP_TO_INT64_OVERFLOW;
442 }
443 update_fcr31(env, GETPC());
444 return dt2;
445 }
446
447 uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
448 {
449 uint32_t wt2;
450
451 set_float_rounding_mode(float_round_nearest_even,
452 &env->active_fpu.fp_status);
453 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
454 restore_rounding_mode(env);
455 if (get_float_exception_flags(&env->active_fpu.fp_status)
456 & (float_flag_invalid | float_flag_overflow)) {
457 wt2 = FP_TO_INT32_OVERFLOW;
458 }
459 update_fcr31(env, GETPC());
460 return wt2;
461 }
462
463 uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
464 {
465 uint32_t wt2;
466
467 set_float_rounding_mode(float_round_nearest_even,
468 &env->active_fpu.fp_status);
469 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
470 restore_rounding_mode(env);
471 if (get_float_exception_flags(&env->active_fpu.fp_status)
472 & (float_flag_invalid | float_flag_overflow)) {
473 wt2 = FP_TO_INT32_OVERFLOW;
474 }
475 update_fcr31(env, GETPC());
476 return wt2;
477 }
478
479 uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
480 {
481 uint64_t dt2;
482
483 dt2 = float64_to_int64_round_to_zero(fdt0,
484 &env->active_fpu.fp_status);
485 if (get_float_exception_flags(&env->active_fpu.fp_status)
486 & (float_flag_invalid | float_flag_overflow)) {
487 dt2 = FP_TO_INT64_OVERFLOW;
488 }
489 update_fcr31(env, GETPC());
490 return dt2;
491 }
492
493 uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
494 {
495 uint64_t dt2;
496
497 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
498 if (get_float_exception_flags(&env->active_fpu.fp_status)
499 & (float_flag_invalid | float_flag_overflow)) {
500 dt2 = FP_TO_INT64_OVERFLOW;
501 }
502 update_fcr31(env, GETPC());
503 return dt2;
504 }
505
506 uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
507 {
508 uint32_t wt2;
509
510 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
511 if (get_float_exception_flags(&env->active_fpu.fp_status)
512 & (float_flag_invalid | float_flag_overflow)) {
513 wt2 = FP_TO_INT32_OVERFLOW;
514 }
515 update_fcr31(env, GETPC());
516 return wt2;
517 }
518
519 uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
520 {
521 uint32_t wt2;
522
523 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
524 if (get_float_exception_flags(&env->active_fpu.fp_status)
525 & (float_flag_invalid | float_flag_overflow)) {
526 wt2 = FP_TO_INT32_OVERFLOW;
527 }
528 update_fcr31(env, GETPC());
529 return wt2;
530 }
531
532 uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
533 {
534 uint64_t dt2;
535
536 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
537 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
538 restore_rounding_mode(env);
539 if (get_float_exception_flags(&env->active_fpu.fp_status)
540 & (float_flag_invalid | float_flag_overflow)) {
541 dt2 = FP_TO_INT64_OVERFLOW;
542 }
543 update_fcr31(env, GETPC());
544 return dt2;
545 }
546
547 uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
548 {
549 uint64_t dt2;
550
551 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
552 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
553 restore_rounding_mode(env);
554 if (get_float_exception_flags(&env->active_fpu.fp_status)
555 & (float_flag_invalid | float_flag_overflow)) {
556 dt2 = FP_TO_INT64_OVERFLOW;
557 }
558 update_fcr31(env, GETPC());
559 return dt2;
560 }
561
562 uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
563 {
564 uint32_t wt2;
565
566 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
567 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
568 restore_rounding_mode(env);
569 if (get_float_exception_flags(&env->active_fpu.fp_status)
570 & (float_flag_invalid | float_flag_overflow)) {
571 wt2 = FP_TO_INT32_OVERFLOW;
572 }
573 update_fcr31(env, GETPC());
574 return wt2;
575 }
576
577 uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
578 {
579 uint32_t wt2;
580
581 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
582 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
583 restore_rounding_mode(env);
584 if (get_float_exception_flags(&env->active_fpu.fp_status)
585 & (float_flag_invalid | float_flag_overflow)) {
586 wt2 = FP_TO_INT32_OVERFLOW;
587 }
588 update_fcr31(env, GETPC());
589 return wt2;
590 }
591
592 uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
593 {
594 uint64_t dt2;
595
596 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
597 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
598 restore_rounding_mode(env);
599 if (get_float_exception_flags(&env->active_fpu.fp_status)
600 & (float_flag_invalid | float_flag_overflow)) {
601 dt2 = FP_TO_INT64_OVERFLOW;
602 }
603 update_fcr31(env, GETPC());
604 return dt2;
605 }
606
607 uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
608 {
609 uint64_t dt2;
610
611 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
612 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
613 restore_rounding_mode(env);
614 if (get_float_exception_flags(&env->active_fpu.fp_status)
615 & (float_flag_invalid | float_flag_overflow)) {
616 dt2 = FP_TO_INT64_OVERFLOW;
617 }
618 update_fcr31(env, GETPC());
619 return dt2;
620 }
621
622 uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
623 {
624 uint32_t wt2;
625
626 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
627 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
628 restore_rounding_mode(env);
629 if (get_float_exception_flags(&env->active_fpu.fp_status)
630 & (float_flag_invalid | float_flag_overflow)) {
631 wt2 = FP_TO_INT32_OVERFLOW;
632 }
633 update_fcr31(env, GETPC());
634 return wt2;
635 }
636
637 uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
638 {
639 uint32_t wt2;
640
641 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
642 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
643 restore_rounding_mode(env);
644 if (get_float_exception_flags(&env->active_fpu.fp_status)
645 & (float_flag_invalid | float_flag_overflow)) {
646 wt2 = FP_TO_INT32_OVERFLOW;
647 }
648 update_fcr31(env, GETPC());
649 return wt2;
650 }
651
652 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
653 {
654 uint64_t dt2;
655
656 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
657 if (get_float_exception_flags(&env->active_fpu.fp_status)
658 & float_flag_invalid) {
659 if (float64_is_any_nan(fdt0)) {
660 dt2 = 0;
661 }
662 }
663 update_fcr31(env, GETPC());
664 return dt2;
665 }
666
667 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
668 {
669 uint64_t dt2;
670
671 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
672 if (get_float_exception_flags(&env->active_fpu.fp_status)
673 & float_flag_invalid) {
674 if (float32_is_any_nan(fst0)) {
675 dt2 = 0;
676 }
677 }
678 update_fcr31(env, GETPC());
679 return dt2;
680 }
681
682 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
683 {
684 uint32_t wt2;
685
686 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
687 if (get_float_exception_flags(&env->active_fpu.fp_status)
688 & float_flag_invalid) {
689 if (float64_is_any_nan(fdt0)) {
690 wt2 = 0;
691 }
692 }
693 update_fcr31(env, GETPC());
694 return wt2;
695 }
696
697 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
698 {
699 uint32_t wt2;
700
701 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
702 if (get_float_exception_flags(&env->active_fpu.fp_status)
703 & float_flag_invalid) {
704 if (float32_is_any_nan(fst0)) {
705 wt2 = 0;
706 }
707 }
708 update_fcr31(env, GETPC());
709 return wt2;
710 }
711
712 uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
713 {
714 uint64_t dt2;
715
716 set_float_rounding_mode(float_round_nearest_even,
717 &env->active_fpu.fp_status);
718 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
719 restore_rounding_mode(env);
720 if (get_float_exception_flags(&env->active_fpu.fp_status)
721 & float_flag_invalid) {
722 if (float64_is_any_nan(fdt0)) {
723 dt2 = 0;
724 }
725 }
726 update_fcr31(env, GETPC());
727 return dt2;
728 }
729
730 uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
731 {
732 uint64_t dt2;
733
734 set_float_rounding_mode(float_round_nearest_even,
735 &env->active_fpu.fp_status);
736 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
737 restore_rounding_mode(env);
738 if (get_float_exception_flags(&env->active_fpu.fp_status)
739 & float_flag_invalid) {
740 if (float32_is_any_nan(fst0)) {
741 dt2 = 0;
742 }
743 }
744 update_fcr31(env, GETPC());
745 return dt2;
746 }
747
748 uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
749 {
750 uint32_t wt2;
751
752 set_float_rounding_mode(float_round_nearest_even,
753 &env->active_fpu.fp_status);
754 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
755 restore_rounding_mode(env);
756 if (get_float_exception_flags(&env->active_fpu.fp_status)
757 & float_flag_invalid) {
758 if (float64_is_any_nan(fdt0)) {
759 wt2 = 0;
760 }
761 }
762 update_fcr31(env, GETPC());
763 return wt2;
764 }
765
766 uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
767 {
768 uint32_t wt2;
769
770 set_float_rounding_mode(float_round_nearest_even,
771 &env->active_fpu.fp_status);
772 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
773 restore_rounding_mode(env);
774 if (get_float_exception_flags(&env->active_fpu.fp_status)
775 & float_flag_invalid) {
776 if (float32_is_any_nan(fst0)) {
777 wt2 = 0;
778 }
779 }
780 update_fcr31(env, GETPC());
781 return wt2;
782 }
783
784 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
785 {
786 uint64_t dt2;
787
788 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
789 if (get_float_exception_flags(&env->active_fpu.fp_status)
790 & float_flag_invalid) {
791 if (float64_is_any_nan(fdt0)) {
792 dt2 = 0;
793 }
794 }
795 update_fcr31(env, GETPC());
796 return dt2;
797 }
798
799 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
800 {
801 uint64_t dt2;
802
803 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
804 if (get_float_exception_flags(&env->active_fpu.fp_status)
805 & float_flag_invalid) {
806 if (float32_is_any_nan(fst0)) {
807 dt2 = 0;
808 }
809 }
810 update_fcr31(env, GETPC());
811 return dt2;
812 }
813
814 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
815 {
816 uint32_t wt2;
817
818 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
819 if (get_float_exception_flags(&env->active_fpu.fp_status)
820 & float_flag_invalid) {
821 if (float64_is_any_nan(fdt0)) {
822 wt2 = 0;
823 }
824 }
825 update_fcr31(env, GETPC());
826 return wt2;
827 }
828
829 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
830 {
831 uint32_t wt2;
832
833 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
834 if (get_float_exception_flags(&env->active_fpu.fp_status)
835 & float_flag_invalid) {
836 if (float32_is_any_nan(fst0)) {
837 wt2 = 0;
838 }
839 }
840 update_fcr31(env, GETPC());
841 return wt2;
842 }
843
844 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
845 {
846 uint64_t dt2;
847
848 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
849 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
850 restore_rounding_mode(env);
851 if (get_float_exception_flags(&env->active_fpu.fp_status)
852 & float_flag_invalid) {
853 if (float64_is_any_nan(fdt0)) {
854 dt2 = 0;
855 }
856 }
857 update_fcr31(env, GETPC());
858 return dt2;
859 }
860
861 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
862 {
863 uint64_t dt2;
864
865 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
866 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
867 restore_rounding_mode(env);
868 if (get_float_exception_flags(&env->active_fpu.fp_status)
869 & float_flag_invalid) {
870 if (float32_is_any_nan(fst0)) {
871 dt2 = 0;
872 }
873 }
874 update_fcr31(env, GETPC());
875 return dt2;
876 }
877
878 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
879 {
880 uint32_t wt2;
881
882 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
883 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
884 restore_rounding_mode(env);
885 if (get_float_exception_flags(&env->active_fpu.fp_status)
886 & float_flag_invalid) {
887 if (float64_is_any_nan(fdt0)) {
888 wt2 = 0;
889 }
890 }
891 update_fcr31(env, GETPC());
892 return wt2;
893 }
894
895 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
896 {
897 uint32_t wt2;
898
899 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
900 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
901 restore_rounding_mode(env);
902 if (get_float_exception_flags(&env->active_fpu.fp_status)
903 & float_flag_invalid) {
904 if (float32_is_any_nan(fst0)) {
905 wt2 = 0;
906 }
907 }
908 update_fcr31(env, GETPC());
909 return wt2;
910 }
911
912 uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
913 {
914 uint64_t dt2;
915
916 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
917 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
918 restore_rounding_mode(env);
919 if (get_float_exception_flags(&env->active_fpu.fp_status)
920 & float_flag_invalid) {
921 if (float64_is_any_nan(fdt0)) {
922 dt2 = 0;
923 }
924 }
925 update_fcr31(env, GETPC());
926 return dt2;
927 }
928
929 uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
930 {
931 uint64_t dt2;
932
933 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
934 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
935 restore_rounding_mode(env);
936 if (get_float_exception_flags(&env->active_fpu.fp_status)
937 & float_flag_invalid) {
938 if (float32_is_any_nan(fst0)) {
939 dt2 = 0;
940 }
941 }
942 update_fcr31(env, GETPC());
943 return dt2;
944 }
945
946 uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
947 {
948 uint32_t wt2;
949
950 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
951 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
952 restore_rounding_mode(env);
953 if (get_float_exception_flags(&env->active_fpu.fp_status)
954 & float_flag_invalid) {
955 if (float64_is_any_nan(fdt0)) {
956 wt2 = 0;
957 }
958 }
959 update_fcr31(env, GETPC());
960 return wt2;
961 }
962
963 uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
964 {
965 uint32_t wt2;
966
967 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
968 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
969 restore_rounding_mode(env);
970 if (get_float_exception_flags(&env->active_fpu.fp_status)
971 & float_flag_invalid) {
972 if (float32_is_any_nan(fst0)) {
973 wt2 = 0;
974 }
975 }
976 update_fcr31(env, GETPC());
977 return wt2;
978 }
979
980 /* unary operations, not modifying fp status */
981 #define FLOAT_UNOP(name) \
982 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
983 { \
984 return float64_ ## name(fdt0); \
985 } \
986 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
987 { \
988 return float32_ ## name(fst0); \
989 } \
990 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
991 { \
992 uint32_t wt0; \
993 uint32_t wth0; \
994 \
995 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
996 wth0 = float32_ ## name(fdt0 >> 32); \
997 return ((uint64_t)wth0 << 32) | wt0; \
998 }
999 FLOAT_UNOP(abs)
1000 FLOAT_UNOP(chs)
1001 #undef FLOAT_UNOP
1002
1003 /* MIPS specific unary operations */
1004 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
1005 {
1006 uint64_t fdt2;
1007
1008 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
1009 update_fcr31(env, GETPC());
1010 return fdt2;
1011 }
1012
1013 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
1014 {
1015 uint32_t fst2;
1016
1017 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
1018 update_fcr31(env, GETPC());
1019 return fst2;
1020 }
1021
1022 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
1023 {
1024 uint64_t fdt2;
1025
1026 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
1027 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
1028 update_fcr31(env, GETPC());
1029 return fdt2;
1030 }
1031
1032 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
1033 {
1034 uint32_t fst2;
1035
1036 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
1037 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
1038 update_fcr31(env, GETPC());
1039 return fst2;
1040 }
1041
1042 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
1043 {
1044 uint64_t fdt2;
1045
1046 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
1047 update_fcr31(env, GETPC());
1048 return fdt2;
1049 }
1050
1051 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
1052 {
1053 uint32_t fst2;
1054
1055 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
1056 update_fcr31(env, GETPC());
1057 return fst2;
1058 }
1059
1060 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
1061 {
1062 uint32_t fst2;
1063 uint32_t fsth2;
1064
1065 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF,
1066 &env->active_fpu.fp_status);
1067 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
1068 update_fcr31(env, GETPC());
1069 return ((uint64_t)fsth2 << 32) | fst2;
1070 }
1071
1072 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
1073 {
1074 uint64_t fdt2;
1075
1076 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
1077 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
1078 update_fcr31(env, GETPC());
1079 return fdt2;
1080 }
1081
1082 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
1083 {
1084 uint32_t fst2;
1085
1086 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
1087 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
1088 update_fcr31(env, GETPC());
1089 return fst2;
1090 }
1091
1092 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
1093 {
1094 uint32_t fst2;
1095 uint32_t fsth2;
1096
1097 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
1098 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
1099 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
1100 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
1101 update_fcr31(env, GETPC());
1102 return ((uint64_t)fsth2 << 32) | fst2;
1103 }
1104
1105 #define FLOAT_RINT(name, bits) \
1106 uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
1107 uint ## bits ## _t fs) \
1108 { \
1109 uint ## bits ## _t fdret; \
1110 \
1111 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
1112 update_fcr31(env, GETPC()); \
1113 return fdret; \
1114 }
1115
1116 FLOAT_RINT(rint_s, 32)
1117 FLOAT_RINT(rint_d, 64)
1118 #undef FLOAT_RINT
1119
1120 #define FLOAT_CLASS_SIGNALING_NAN 0x001
1121 #define FLOAT_CLASS_QUIET_NAN 0x002
1122 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
1123 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
1124 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
1125 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
1126 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
1127 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
1128 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
1129 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
1130
1131 #define FLOAT_CLASS(name, bits) \
1132 uint ## bits ## _t float_ ## name(uint ## bits ## _t arg, \
1133 float_status *status) \
1134 { \
1135 if (float ## bits ## _is_signaling_nan(arg, status)) { \
1136 return FLOAT_CLASS_SIGNALING_NAN; \
1137 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
1138 return FLOAT_CLASS_QUIET_NAN; \
1139 } else if (float ## bits ## _is_neg(arg)) { \
1140 if (float ## bits ## _is_infinity(arg)) { \
1141 return FLOAT_CLASS_NEGATIVE_INFINITY; \
1142 } else if (float ## bits ## _is_zero(arg)) { \
1143 return FLOAT_CLASS_NEGATIVE_ZERO; \
1144 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
1145 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
1146 } else { \
1147 return FLOAT_CLASS_NEGATIVE_NORMAL; \
1148 } \
1149 } else { \
1150 if (float ## bits ## _is_infinity(arg)) { \
1151 return FLOAT_CLASS_POSITIVE_INFINITY; \
1152 } else if (float ## bits ## _is_zero(arg)) { \
1153 return FLOAT_CLASS_POSITIVE_ZERO; \
1154 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
1155 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
1156 } else { \
1157 return FLOAT_CLASS_POSITIVE_NORMAL; \
1158 } \
1159 } \
1160 } \
1161 \
1162 uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
1163 uint ## bits ## _t arg) \
1164 { \
1165 return float_ ## name(arg, &env->active_fpu.fp_status); \
1166 }
1167
1168 FLOAT_CLASS(class_s, 32)
1169 FLOAT_CLASS(class_d, 64)
1170 #undef FLOAT_CLASS
1171
1172 /* binary operations */
1173
1174 uint64_t helper_float_add_d(CPUMIPSState *env,
1175 uint64_t fdt0, uint64_t fdt1)
1176 {
1177 uint64_t dt2;
1178
1179 dt2 = float64_add(fdt0, fdt1, &env->active_fpu.fp_status);
1180 update_fcr31(env, GETPC());
1181 return dt2;
1182 }
1183
1184 uint32_t helper_float_add_s(CPUMIPSState *env,
1185 uint32_t fst0, uint32_t fst1)
1186 {
1187 uint32_t wt2;
1188
1189 wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status);
1190 update_fcr31(env, GETPC());
1191 return wt2;
1192 }
1193
1194 uint64_t helper_float_add_ps(CPUMIPSState *env,
1195 uint64_t fdt0, uint64_t fdt1)
1196 {
1197 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1198 uint32_t fsth0 = fdt0 >> 32;
1199 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1200 uint32_t fsth1 = fdt1 >> 32;
1201 uint32_t wtl2;
1202 uint32_t wth2;
1203
1204 wtl2 = float32_add(fstl0, fstl1, &env->active_fpu.fp_status);
1205 wth2 = float32_add(fsth0, fsth1, &env->active_fpu.fp_status);
1206 update_fcr31(env, GETPC());
1207 return ((uint64_t)wth2 << 32) | wtl2;
1208 }
1209
1210 uint64_t helper_float_sub_d(CPUMIPSState *env,
1211 uint64_t fdt0, uint64_t fdt1)
1212 {
1213 uint64_t dt2;
1214
1215 dt2 = float64_sub(fdt0, fdt1, &env->active_fpu.fp_status);
1216 update_fcr31(env, GETPC());
1217 return dt2;
1218 }
1219
1220 uint32_t helper_float_sub_s(CPUMIPSState *env,
1221 uint32_t fst0, uint32_t fst1)
1222 {
1223 uint32_t wt2;
1224
1225 wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status);
1226 update_fcr31(env, GETPC());
1227 return wt2;
1228 }
1229
1230 uint64_t helper_float_sub_ps(CPUMIPSState *env,
1231 uint64_t fdt0, uint64_t fdt1)
1232 {
1233 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1234 uint32_t fsth0 = fdt0 >> 32;
1235 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1236 uint32_t fsth1 = fdt1 >> 32;
1237 uint32_t wtl2;
1238 uint32_t wth2;
1239
1240 wtl2 = float32_sub(fstl0, fstl1, &env->active_fpu.fp_status);
1241 wth2 = float32_sub(fsth0, fsth1, &env->active_fpu.fp_status);
1242 update_fcr31(env, GETPC());
1243 return ((uint64_t)wth2 << 32) | wtl2;
1244 }
1245
1246 uint64_t helper_float_mul_d(CPUMIPSState *env,
1247 uint64_t fdt0, uint64_t fdt1)
1248 {
1249 uint64_t dt2;
1250
1251 dt2 = float64_mul(fdt0, fdt1, &env->active_fpu.fp_status);
1252 update_fcr31(env, GETPC());
1253 return dt2;
1254 }
1255
1256 uint32_t helper_float_mul_s(CPUMIPSState *env,
1257 uint32_t fst0, uint32_t fst1)
1258 {
1259 uint32_t wt2;
1260
1261 wt2 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
1262 update_fcr31(env, GETPC());
1263 return wt2;
1264 }
1265
1266 uint64_t helper_float_mul_ps(CPUMIPSState *env,
1267 uint64_t fdt0, uint64_t fdt1)
1268 {
1269 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1270 uint32_t fsth0 = fdt0 >> 32;
1271 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1272 uint32_t fsth1 = fdt1 >> 32;
1273 uint32_t wtl2;
1274 uint32_t wth2;
1275
1276 wtl2 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
1277 wth2 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
1278 update_fcr31(env, GETPC());
1279 return ((uint64_t)wth2 << 32) | wtl2;
1280 }
1281
1282 uint64_t helper_float_div_d(CPUMIPSState *env,
1283 uint64_t fdt0, uint64_t fdt1)
1284 {
1285 uint64_t dt2;
1286
1287 dt2 = float64_div(fdt0, fdt1, &env->active_fpu.fp_status);
1288 update_fcr31(env, GETPC());
1289 return dt2;
1290 }
1291
1292 uint32_t helper_float_div_s(CPUMIPSState *env,
1293 uint32_t fst0, uint32_t fst1)
1294 {
1295 uint32_t wt2;
1296
1297 wt2 = float32_div(fst0, fst1, &env->active_fpu.fp_status);
1298 update_fcr31(env, GETPC());
1299 return wt2;
1300 }
1301
1302 uint64_t helper_float_div_ps(CPUMIPSState *env,
1303 uint64_t fdt0, uint64_t fdt1)
1304 {
1305 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1306 uint32_t fsth0 = fdt0 >> 32;
1307 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1308 uint32_t fsth1 = fdt1 >> 32;
1309 uint32_t wtl2;
1310 uint32_t wth2;
1311
1312 wtl2 = float32_div(fstl0, fstl1, &env->active_fpu.fp_status);
1313 wth2 = float32_div(fsth0, fsth1, &env->active_fpu.fp_status);
1314 update_fcr31(env, GETPC());
1315 return ((uint64_t)wth2 << 32) | wtl2;
1316 }
1317
1318
1319 /* MIPS specific binary operations */
1320 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
1321 {
1322 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
1323 fdt2 = float64_chs(float64_sub(fdt2, float64_one,
1324 &env->active_fpu.fp_status));
1325 update_fcr31(env, GETPC());
1326 return fdt2;
1327 }
1328
1329 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
1330 {
1331 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
1332 fst2 = float32_chs(float32_sub(fst2, float32_one,
1333 &env->active_fpu.fp_status));
1334 update_fcr31(env, GETPC());
1335 return fst2;
1336 }
1337
1338 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
1339 {
1340 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
1341 uint32_t fsth0 = fdt0 >> 32;
1342 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
1343 uint32_t fsth2 = fdt2 >> 32;
1344
1345 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
1346 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
1347 fst2 = float32_chs(float32_sub(fst2, float32_one,
1348 &env->active_fpu.fp_status));
1349 fsth2 = float32_chs(float32_sub(fsth2, float32_one,
1350 &env->active_fpu.fp_status));
1351 update_fcr31(env, GETPC());
1352 return ((uint64_t)fsth2 << 32) | fst2;
1353 }
1354
1355 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
1356 {
1357 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
1358 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
1359 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64,
1360 &env->active_fpu.fp_status));
1361 update_fcr31(env, GETPC());
1362 return fdt2;
1363 }
1364
1365 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
1366 {
1367 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
1368 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
1369 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
1370 &env->active_fpu.fp_status));
1371 update_fcr31(env, GETPC());
1372 return fst2;
1373 }
1374
1375 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
1376 {
1377 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
1378 uint32_t fsth0 = fdt0 >> 32;
1379 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
1380 uint32_t fsth2 = fdt2 >> 32;
1381
1382 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
1383 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
1384 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
1385 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
1386 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
1387 &env->active_fpu.fp_status));
1388 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32,
1389 &env->active_fpu.fp_status));
1390 update_fcr31(env, GETPC());
1391 return ((uint64_t)fsth2 << 32) | fst2;
1392 }
1393
1394 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
1395 {
1396 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
1397 uint32_t fsth0 = fdt0 >> 32;
1398 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
1399 uint32_t fsth1 = fdt1 >> 32;
1400 uint32_t fst2;
1401 uint32_t fsth2;
1402
1403 fst2 = float32_add(fst0, fsth0, &env->active_fpu.fp_status);
1404 fsth2 = float32_add(fst1, fsth1, &env->active_fpu.fp_status);
1405 update_fcr31(env, GETPC());
1406 return ((uint64_t)fsth2 << 32) | fst2;
1407 }
1408
1409 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
1410 {
1411 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
1412 uint32_t fsth0 = fdt0 >> 32;
1413 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
1414 uint32_t fsth1 = fdt1 >> 32;
1415 uint32_t fst2;
1416 uint32_t fsth2;
1417
1418 fst2 = float32_mul(fst0, fsth0, &env->active_fpu.fp_status);
1419 fsth2 = float32_mul(fst1, fsth1, &env->active_fpu.fp_status);
1420 update_fcr31(env, GETPC());
1421 return ((uint64_t)fsth2 << 32) | fst2;
1422 }
1423
1424 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
1425 uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
1426 uint ## bits ## _t fs, \
1427 uint ## bits ## _t ft) \
1428 { \
1429 uint ## bits ## _t fdret; \
1430 \
1431 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
1432 &env->active_fpu.fp_status); \
1433 update_fcr31(env, GETPC()); \
1434 return fdret; \
1435 }
1436
1437 FLOAT_MINMAX(max_s, 32, maxnum)
1438 FLOAT_MINMAX(max_d, 64, maxnum)
1439 FLOAT_MINMAX(maxa_s, 32, maxnummag)
1440 FLOAT_MINMAX(maxa_d, 64, maxnummag)
1441
1442 FLOAT_MINMAX(min_s, 32, minnum)
1443 FLOAT_MINMAX(min_d, 64, minnum)
1444 FLOAT_MINMAX(mina_s, 32, minnummag)
1445 FLOAT_MINMAX(mina_d, 64, minnummag)
1446 #undef FLOAT_MINMAX
1447
1448 /* ternary operations */
1449 #define UNFUSED_FMA(prefix, a, b, c, flags) \
1450 { \
1451 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
1452 if ((flags) & float_muladd_negate_c) { \
1453 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
1454 } else { \
1455 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
1456 } \
1457 if ((flags) & float_muladd_negate_result) { \
1458 a = prefix##_chs(a); \
1459 } \
1460 }
1461
1462 /* FMA based operations */
1463 #define FLOAT_FMA(name, type) \
1464 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
1465 uint64_t fdt0, uint64_t fdt1, \
1466 uint64_t fdt2) \
1467 { \
1468 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
1469 update_fcr31(env, GETPC()); \
1470 return fdt0; \
1471 } \
1472 \
1473 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
1474 uint32_t fst0, uint32_t fst1, \
1475 uint32_t fst2) \
1476 { \
1477 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
1478 update_fcr31(env, GETPC()); \
1479 return fst0; \
1480 } \
1481 \
1482 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
1483 uint64_t fdt0, uint64_t fdt1, \
1484 uint64_t fdt2) \
1485 { \
1486 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
1487 uint32_t fsth0 = fdt0 >> 32; \
1488 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
1489 uint32_t fsth1 = fdt1 >> 32; \
1490 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
1491 uint32_t fsth2 = fdt2 >> 32; \
1492 \
1493 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
1494 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
1495 update_fcr31(env, GETPC()); \
1496 return ((uint64_t)fsth0 << 32) | fst0; \
1497 }
1498 FLOAT_FMA(msub, float_muladd_negate_c)
1499 FLOAT_FMA(nmadd, float_muladd_negate_result)
1500 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
1501 #undef FLOAT_FMA
1502
1503 uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0,
1504 uint64_t fst1, uint64_t fst2)
1505 {
1506 fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
1507 fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status);
1508
1509 update_fcr31(env, GETPC());
1510 return fst0;
1511 }
1512
1513 uint32_t helper_float_madd_s(CPUMIPSState *env, uint32_t fst0,
1514 uint32_t fst1, uint32_t fst2)
1515 {
1516 fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
1517 fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status);
1518
1519 update_fcr31(env, GETPC());
1520 return fst0;
1521 }
1522
1523 uint64_t helper_float_madd_ps(CPUMIPSState *env, uint64_t fdt0,
1524 uint64_t fdt1, uint64_t fdt2)
1525 {
1526 uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
1527 uint32_t fsth0 = fdt0 >> 32;
1528 uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
1529 uint32_t fsth1 = fdt1 >> 32;
1530 uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
1531 uint32_t fsth2 = fdt2 >> 32;
1532
1533 fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
1534 fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status);
1535 fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
1536 fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status);
1537
1538 update_fcr31(env, GETPC());
1539 return ((uint64_t)fsth0 << 32) | fstl0;
1540 }
1541
1542
1543 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
1544 uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
1545 uint ## bits ## _t fs, \
1546 uint ## bits ## _t ft, \
1547 uint ## bits ## _t fd) \
1548 { \
1549 uint ## bits ## _t fdret; \
1550 \
1551 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
1552 &env->active_fpu.fp_status); \
1553 update_fcr31(env, GETPC()); \
1554 return fdret; \
1555 }
1556
1557 FLOAT_FMADDSUB(maddf_s, 32, 0)
1558 FLOAT_FMADDSUB(maddf_d, 64, 0)
1559 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
1560 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
1561 #undef FLOAT_FMADDSUB
1562
1563 /* compare operations */
1564 #define FOP_COND_D(op, cond) \
1565 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1566 uint64_t fdt1, int cc) \
1567 { \
1568 int c; \
1569 c = cond; \
1570 update_fcr31(env, GETPC()); \
1571 if (c) \
1572 SET_FP_COND(cc, env->active_fpu); \
1573 else \
1574 CLEAR_FP_COND(cc, env->active_fpu); \
1575 } \
1576 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1577 uint64_t fdt1, int cc) \
1578 { \
1579 int c; \
1580 fdt0 = float64_abs(fdt0); \
1581 fdt1 = float64_abs(fdt1); \
1582 c = cond; \
1583 update_fcr31(env, GETPC()); \
1584 if (c) \
1585 SET_FP_COND(cc, env->active_fpu); \
1586 else \
1587 CLEAR_FP_COND(cc, env->active_fpu); \
1588 }
1589
1590 /*
1591 * NOTE: the comma operator will make "cond" to eval to false,
1592 * but float64_unordered_quiet() is still called.
1593 */
1594 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0,
1595 &env->active_fpu.fp_status), 0))
1596 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0,
1597 &env->active_fpu.fp_status))
1598 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1,
1599 &env->active_fpu.fp_status))
1600 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0,
1601 &env->active_fpu.fp_status)
1602 || float64_eq_quiet(fdt0, fdt1,
1603 &env->active_fpu.fp_status))
1604 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1,
1605 &env->active_fpu.fp_status))
1606 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0,
1607 &env->active_fpu.fp_status)
1608 || float64_lt_quiet(fdt0, fdt1,
1609 &env->active_fpu.fp_status))
1610 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1,
1611 &env->active_fpu.fp_status))
1612 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0,
1613 &env->active_fpu.fp_status)
1614 || float64_le_quiet(fdt0, fdt1,
1615 &env->active_fpu.fp_status))
1616 /*
1617 * NOTE: the comma operator will make "cond" to eval to false,
1618 * but float64_unordered() is still called.
1619 */
1620 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0,
1621 &env->active_fpu.fp_status), 0))
1622 FOP_COND_D(ngle, float64_unordered(fdt1, fdt0,
1623 &env->active_fpu.fp_status))
1624 FOP_COND_D(seq, float64_eq(fdt0, fdt1,
1625 &env->active_fpu.fp_status))
1626 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0,
1627 &env->active_fpu.fp_status)
1628 || float64_eq(fdt0, fdt1,
1629 &env->active_fpu.fp_status))
1630 FOP_COND_D(lt, float64_lt(fdt0, fdt1,
1631 &env->active_fpu.fp_status))
1632 FOP_COND_D(nge, float64_unordered(fdt1, fdt0,
1633 &env->active_fpu.fp_status)
1634 || float64_lt(fdt0, fdt1,
1635 &env->active_fpu.fp_status))
1636 FOP_COND_D(le, float64_le(fdt0, fdt1,
1637 &env->active_fpu.fp_status))
1638 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0,
1639 &env->active_fpu.fp_status)
1640 || float64_le(fdt0, fdt1,
1641 &env->active_fpu.fp_status))
1642
1643 #define FOP_COND_S(op, cond) \
1644 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
1645 uint32_t fst1, int cc) \
1646 { \
1647 int c; \
1648 c = cond; \
1649 update_fcr31(env, GETPC()); \
1650 if (c) \
1651 SET_FP_COND(cc, env->active_fpu); \
1652 else \
1653 CLEAR_FP_COND(cc, env->active_fpu); \
1654 } \
1655 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
1656 uint32_t fst1, int cc) \
1657 { \
1658 int c; \
1659 fst0 = float32_abs(fst0); \
1660 fst1 = float32_abs(fst1); \
1661 c = cond; \
1662 update_fcr31(env, GETPC()); \
1663 if (c) \
1664 SET_FP_COND(cc, env->active_fpu); \
1665 else \
1666 CLEAR_FP_COND(cc, env->active_fpu); \
1667 }
1668
1669 /*
1670 * NOTE: the comma operator will make "cond" to eval to false,
1671 * but float32_unordered_quiet() is still called.
1672 */
1673 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0,
1674 &env->active_fpu.fp_status), 0))
1675 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0,
1676 &env->active_fpu.fp_status))
1677 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1,
1678 &env->active_fpu.fp_status))
1679 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0,
1680 &env->active_fpu.fp_status)
1681 || float32_eq_quiet(fst0, fst1,
1682 &env->active_fpu.fp_status))
1683 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1,
1684 &env->active_fpu.fp_status))
1685 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0,
1686 &env->active_fpu.fp_status)
1687 || float32_lt_quiet(fst0, fst1,
1688 &env->active_fpu.fp_status))
1689 FOP_COND_S(ole, float32_le_quiet(fst0, fst1,
1690 &env->active_fpu.fp_status))
1691 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0,
1692 &env->active_fpu.fp_status)
1693 || float32_le_quiet(fst0, fst1,
1694 &env->active_fpu.fp_status))
1695 /*
1696 * NOTE: the comma operator will make "cond" to eval to false,
1697 * but float32_unordered() is still called.
1698 */
1699 FOP_COND_S(sf, (float32_unordered(fst1, fst0,
1700 &env->active_fpu.fp_status), 0))
1701 FOP_COND_S(ngle, float32_unordered(fst1, fst0,
1702 &env->active_fpu.fp_status))
1703 FOP_COND_S(seq, float32_eq(fst0, fst1,
1704 &env->active_fpu.fp_status))
1705 FOP_COND_S(ngl, float32_unordered(fst1, fst0,
1706 &env->active_fpu.fp_status)
1707 || float32_eq(fst0, fst1,
1708 &env->active_fpu.fp_status))
1709 FOP_COND_S(lt, float32_lt(fst0, fst1,
1710 &env->active_fpu.fp_status))
1711 FOP_COND_S(nge, float32_unordered(fst1, fst0,
1712 &env->active_fpu.fp_status)
1713 || float32_lt(fst0, fst1,
1714 &env->active_fpu.fp_status))
1715 FOP_COND_S(le, float32_le(fst0, fst1,
1716 &env->active_fpu.fp_status))
1717 FOP_COND_S(ngt, float32_unordered(fst1, fst0,
1718 &env->active_fpu.fp_status)
1719 || float32_le(fst0, fst1,
1720 &env->active_fpu.fp_status))
1721
1722 #define FOP_COND_PS(op, condl, condh) \
1723 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1724 uint64_t fdt1, int cc) \
1725 { \
1726 uint32_t fst0, fsth0, fst1, fsth1; \
1727 int ch, cl; \
1728 fst0 = fdt0 & 0XFFFFFFFF; \
1729 fsth0 = fdt0 >> 32; \
1730 fst1 = fdt1 & 0XFFFFFFFF; \
1731 fsth1 = fdt1 >> 32; \
1732 cl = condl; \
1733 ch = condh; \
1734 update_fcr31(env, GETPC()); \
1735 if (cl) \
1736 SET_FP_COND(cc, env->active_fpu); \
1737 else \
1738 CLEAR_FP_COND(cc, env->active_fpu); \
1739 if (ch) \
1740 SET_FP_COND(cc + 1, env->active_fpu); \
1741 else \
1742 CLEAR_FP_COND(cc + 1, env->active_fpu); \
1743 } \
1744 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1745 uint64_t fdt1, int cc) \
1746 { \
1747 uint32_t fst0, fsth0, fst1, fsth1; \
1748 int ch, cl; \
1749 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
1750 fsth0 = float32_abs(fdt0 >> 32); \
1751 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
1752 fsth1 = float32_abs(fdt1 >> 32); \
1753 cl = condl; \
1754 ch = condh; \
1755 update_fcr31(env, GETPC()); \
1756 if (cl) \
1757 SET_FP_COND(cc, env->active_fpu); \
1758 else \
1759 CLEAR_FP_COND(cc, env->active_fpu); \
1760 if (ch) \
1761 SET_FP_COND(cc + 1, env->active_fpu); \
1762 else \
1763 CLEAR_FP_COND(cc + 1, env->active_fpu); \
1764 }
1765
1766 /*
1767 * NOTE: the comma operator will make "cond" to eval to false,
1768 * but float32_unordered_quiet() is still called.
1769 */
1770 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0,
1771 &env->active_fpu.fp_status), 0),
1772 (float32_unordered_quiet(fsth1, fsth0,
1773 &env->active_fpu.fp_status), 0))
1774 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0,
1775 &env->active_fpu.fp_status),
1776 float32_unordered_quiet(fsth1, fsth0,
1777 &env->active_fpu.fp_status))
1778 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1,
1779 &env->active_fpu.fp_status),
1780 float32_eq_quiet(fsth0, fsth1,
1781 &env->active_fpu.fp_status))
1782 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0,
1783 &env->active_fpu.fp_status)
1784 || float32_eq_quiet(fst0, fst1,
1785 &env->active_fpu.fp_status),
1786 float32_unordered_quiet(fsth1, fsth0,
1787 &env->active_fpu.fp_status)
1788 || float32_eq_quiet(fsth0, fsth1,
1789 &env->active_fpu.fp_status))
1790 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1,
1791 &env->active_fpu.fp_status),
1792 float32_lt_quiet(fsth0, fsth1,
1793 &env->active_fpu.fp_status))
1794 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0,
1795 &env->active_fpu.fp_status)
1796 || float32_lt_quiet(fst0, fst1,
1797 &env->active_fpu.fp_status),
1798 float32_unordered_quiet(fsth1, fsth0,
1799 &env->active_fpu.fp_status)
1800 || float32_lt_quiet(fsth0, fsth1,
1801 &env->active_fpu.fp_status))
1802 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1,
1803 &env->active_fpu.fp_status),
1804 float32_le_quiet(fsth0, fsth1,
1805 &env->active_fpu.fp_status))
1806 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0,
1807 &env->active_fpu.fp_status)
1808 || float32_le_quiet(fst0, fst1,
1809 &env->active_fpu.fp_status),
1810 float32_unordered_quiet(fsth1, fsth0,
1811 &env->active_fpu.fp_status)
1812 || float32_le_quiet(fsth0, fsth1,
1813 &env->active_fpu.fp_status))
1814 /*
1815 * NOTE: the comma operator will make "cond" to eval to false,
1816 * but float32_unordered() is still called.
1817 */
1818 FOP_COND_PS(sf, (float32_unordered(fst1, fst0,
1819 &env->active_fpu.fp_status), 0),
1820 (float32_unordered(fsth1, fsth0,
1821 &env->active_fpu.fp_status), 0))
1822 FOP_COND_PS(ngle, float32_unordered(fst1, fst0,
1823 &env->active_fpu.fp_status),
1824 float32_unordered(fsth1, fsth0,
1825 &env->active_fpu.fp_status))
1826 FOP_COND_PS(seq, float32_eq(fst0, fst1,
1827 &env->active_fpu.fp_status),
1828 float32_eq(fsth0, fsth1,
1829 &env->active_fpu.fp_status))
1830 FOP_COND_PS(ngl, float32_unordered(fst1, fst0,
1831 &env->active_fpu.fp_status)
1832 || float32_eq(fst0, fst1,
1833 &env->active_fpu.fp_status),
1834 float32_unordered(fsth1, fsth0,
1835 &env->active_fpu.fp_status)
1836 || float32_eq(fsth0, fsth1,
1837 &env->active_fpu.fp_status))
1838 FOP_COND_PS(lt, float32_lt(fst0, fst1,
1839 &env->active_fpu.fp_status),
1840 float32_lt(fsth0, fsth1,
1841 &env->active_fpu.fp_status))
1842 FOP_COND_PS(nge, float32_unordered(fst1, fst0,
1843 &env->active_fpu.fp_status)
1844 || float32_lt(fst0, fst1,
1845 &env->active_fpu.fp_status),
1846 float32_unordered(fsth1, fsth0,
1847 &env->active_fpu.fp_status)
1848 || float32_lt(fsth0, fsth1,
1849 &env->active_fpu.fp_status))
1850 FOP_COND_PS(le, float32_le(fst0, fst1,
1851 &env->active_fpu.fp_status),
1852 float32_le(fsth0, fsth1,
1853 &env->active_fpu.fp_status))
1854 FOP_COND_PS(ngt, float32_unordered(fst1, fst0,
1855 &env->active_fpu.fp_status)
1856 || float32_le(fst0, fst1,
1857 &env->active_fpu.fp_status),
1858 float32_unordered(fsth1, fsth0,
1859 &env->active_fpu.fp_status)
1860 || float32_le(fsth0, fsth1,
1861 &env->active_fpu.fp_status))
1862
1863 /* R6 compare operations */
1864 #define FOP_CONDN_D(op, cond) \
1865 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
1866 uint64_t fdt1) \
1867 { \
1868 uint64_t c; \
1869 c = cond; \
1870 update_fcr31(env, GETPC()); \
1871 if (c) { \
1872 return -1; \
1873 } else { \
1874 return 0; \
1875 } \
1876 }
1877
1878 /*
1879 * NOTE: the comma operator will make "cond" to eval to false,
1880 * but float64_unordered_quiet() is still called.
1881 */
1882 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0,
1883 &env->active_fpu.fp_status), 0))
1884 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0,
1885 &env->active_fpu.fp_status)))
1886 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1,
1887 &env->active_fpu.fp_status)))
1888 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0,
1889 &env->active_fpu.fp_status)
1890 || float64_eq_quiet(fdt0, fdt1,
1891 &env->active_fpu.fp_status)))
1892 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1,
1893 &env->active_fpu.fp_status)))
1894 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0,
1895 &env->active_fpu.fp_status)
1896 || float64_lt_quiet(fdt0, fdt1,
1897 &env->active_fpu.fp_status)))
1898 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1,
1899 &env->active_fpu.fp_status)))
1900 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0,
1901 &env->active_fpu.fp_status)
1902 || float64_le_quiet(fdt0, fdt1,
1903 &env->active_fpu.fp_status)))
1904 /*
1905 * NOTE: the comma operator will make "cond" to eval to false,
1906 * but float64_unordered() is still called.\
1907 */
1908 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0,
1909 &env->active_fpu.fp_status), 0))
1910 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0,
1911 &env->active_fpu.fp_status)))
1912 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1,
1913 &env->active_fpu.fp_status)))
1914 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0,
1915 &env->active_fpu.fp_status)
1916 || float64_eq(fdt0, fdt1,
1917 &env->active_fpu.fp_status)))
1918 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1,
1919 &env->active_fpu.fp_status)))
1920 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0,
1921 &env->active_fpu.fp_status)
1922 || float64_lt(fdt0, fdt1,
1923 &env->active_fpu.fp_status)))
1924 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1,
1925 &env->active_fpu.fp_status)))
1926 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0,
1927 &env->active_fpu.fp_status)
1928 || float64_le(fdt0, fdt1,
1929 &env->active_fpu.fp_status)))
1930 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0,
1931 &env->active_fpu.fp_status)
1932 || float64_le_quiet(fdt0, fdt1,
1933 &env->active_fpu.fp_status)))
1934 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0,
1935 &env->active_fpu.fp_status)
1936 || float64_lt_quiet(fdt1, fdt0,
1937 &env->active_fpu.fp_status)
1938 || float64_lt_quiet(fdt0, fdt1,
1939 &env->active_fpu.fp_status)))
1940 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0,
1941 &env->active_fpu.fp_status)
1942 || float64_lt_quiet(fdt0, fdt1,
1943 &env->active_fpu.fp_status)))
1944 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0,
1945 &env->active_fpu.fp_status)
1946 || float64_le(fdt0, fdt1,
1947 &env->active_fpu.fp_status)))
1948 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0,
1949 &env->active_fpu.fp_status)
1950 || float64_lt(fdt1, fdt0,
1951 &env->active_fpu.fp_status)
1952 || float64_lt(fdt0, fdt1,
1953 &env->active_fpu.fp_status)))
1954 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0,
1955 &env->active_fpu.fp_status)
1956 || float64_lt(fdt0, fdt1,
1957 &env->active_fpu.fp_status)))
1958
1959 #define FOP_CONDN_S(op, cond) \
1960 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
1961 uint32_t fst1) \
1962 { \
1963 uint64_t c; \
1964 c = cond; \
1965 update_fcr31(env, GETPC()); \
1966 if (c) { \
1967 return -1; \
1968 } else { \
1969 return 0; \
1970 } \
1971 }
1972
1973 /*
1974 * NOTE: the comma operator will make "cond" to eval to false,
1975 * but float32_unordered_quiet() is still called.
1976 */
1977 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0,
1978 &env->active_fpu.fp_status), 0))
1979 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0,
1980 &env->active_fpu.fp_status)))
1981 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1,
1982 &env->active_fpu.fp_status)))
1983 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0,
1984 &env->active_fpu.fp_status)
1985 || float32_eq_quiet(fst0, fst1,
1986 &env->active_fpu.fp_status)))
1987 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1,
1988 &env->active_fpu.fp_status)))
1989 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0,
1990 &env->active_fpu.fp_status)
1991 || float32_lt_quiet(fst0, fst1,
1992 &env->active_fpu.fp_status)))
1993 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1,
1994 &env->active_fpu.fp_status)))
1995 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0,
1996 &env->active_fpu.fp_status)
1997 || float32_le_quiet(fst0, fst1,
1998 &env->active_fpu.fp_status)))
1999 /*
2000 * NOTE: the comma operator will make "cond" to eval to false,
2001 * but float32_unordered() is still called.
2002 */
2003 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0,
2004 &env->active_fpu.fp_status), 0))
2005 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0,
2006 &env->active_fpu.fp_status)))
2007 FOP_CONDN_S(seq, (float32_eq(fst0, fst1,
2008 &env->active_fpu.fp_status)))
2009 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0,
2010 &env->active_fpu.fp_status)
2011 || float32_eq(fst0, fst1,
2012 &env->active_fpu.fp_status)))
2013 FOP_CONDN_S(slt, (float32_lt(fst0, fst1,
2014 &env->active_fpu.fp_status)))
2015 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0,
2016 &env->active_fpu.fp_status)
2017 || float32_lt(fst0, fst1,
2018 &env->active_fpu.fp_status)))
2019 FOP_CONDN_S(sle, (float32_le(fst0, fst1,
2020 &env->active_fpu.fp_status)))
2021 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0,
2022 &env->active_fpu.fp_status)
2023 || float32_le(fst0, fst1,
2024 &env->active_fpu.fp_status)))
2025 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0,
2026 &env->active_fpu.fp_status)
2027 || float32_le_quiet(fst0, fst1,
2028 &env->active_fpu.fp_status)))
2029 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0,
2030 &env->active_fpu.fp_status)
2031 || float32_lt_quiet(fst1, fst0,
2032 &env->active_fpu.fp_status)
2033 || float32_lt_quiet(fst0, fst1,
2034 &env->active_fpu.fp_status)))
2035 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0,
2036 &env->active_fpu.fp_status)
2037 || float32_lt_quiet(fst0, fst1,
2038 &env->active_fpu.fp_status)))
2039 FOP_CONDN_S(sor, (float32_le(fst1, fst0,
2040 &env->active_fpu.fp_status)
2041 || float32_le(fst0, fst1,
2042 &env->active_fpu.fp_status)))
2043 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0,
2044 &env->active_fpu.fp_status)
2045 || float32_lt(fst1, fst0,
2046 &env->active_fpu.fp_status)
2047 || float32_lt(fst0, fst1,
2048 &env->active_fpu.fp_status)))
2049 FOP_CONDN_S(sne, (float32_lt(fst1, fst0,
2050 &env->active_fpu.fp_status)
2051 || float32_lt(fst0, fst1,
2052 &env->active_fpu.fp_status)))
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