2 * MIPS internal definitions and helpers
4 * This work is licensed under the terms of the GNU GPL, version 2 or later.
5 * See the COPYING file in the top-level directory.
8 #ifndef MIPS_INTERNAL_H
9 #define MIPS_INTERNAL_H
11 #include "exec/memattrs.h"
12 #include "fpu/softfloat-helpers.h"
15 * MMU types, the first four entries have the same layout as the
20 MMU_TYPE_R4000
= 1, /* Standard TLB */
21 MMU_TYPE_BAT
= 2, /* Block Address Translation */
22 MMU_TYPE_FMT
= 3, /* Fixed Mapping */
23 MMU_TYPE_DVF
= 4, /* Dual VTLB and FTLB */
37 int32_t CP0_Config4_rw_bitmask
;
39 int32_t CP0_Config5_rw_bitmask
;
41 int32_t CP0_Config6_rw_bitmask
;
43 int32_t CP0_Config7_rw_bitmask
;
44 target_ulong CP0_LLAddr_rw_bitmask
;
48 int32_t CP0_Status_rw_bitmask
;
49 int32_t CP0_TCStatus_rw_bitmask
;
52 int32_t CP1_fcr31_rw_bitmask
;
57 int32_t CP0_SRSConf0_rw_bitmask
;
59 int32_t CP0_SRSConf1_rw_bitmask
;
61 int32_t CP0_SRSConf2_rw_bitmask
;
63 int32_t CP0_SRSConf3_rw_bitmask
;
65 int32_t CP0_SRSConf4_rw_bitmask
;
67 int32_t CP0_PageGrain_rw_bitmask
;
68 int32_t CP0_PageGrain
;
69 target_ulong CP0_EBaseWG_rw_bitmask
;
71 enum mips_mmu_types mmu_type
;
75 extern const struct mips_def_t mips_defs
[];
76 extern const int mips_defs_number
;
78 enum CPUMIPSMSADataFormat
{
85 void mips_cpu_do_interrupt(CPUState
*cpu
);
86 bool mips_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
87 void mips_cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
88 hwaddr
mips_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
89 int mips_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
90 int mips_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
91 void mips_cpu_do_unaligned_access(CPUState
*cpu
, vaddr addr
,
92 MMUAccessType access_type
,
93 int mmu_idx
, uintptr_t retaddr
);
95 #if !defined(CONFIG_USER_ONLY)
97 typedef struct r4k_tlb_t r4k_tlb_t
;
114 unsigned int EHINV
:1;
118 struct CPUMIPSTLBContext
{
121 int (*map_address
)(struct CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
122 target_ulong address
, int rw
, int access_type
);
123 void (*helper_tlbwi
)(struct CPUMIPSState
*env
);
124 void (*helper_tlbwr
)(struct CPUMIPSState
*env
);
125 void (*helper_tlbp
)(struct CPUMIPSState
*env
);
126 void (*helper_tlbr
)(struct CPUMIPSState
*env
);
127 void (*helper_tlbinv
)(struct CPUMIPSState
*env
);
128 void (*helper_tlbinvf
)(struct CPUMIPSState
*env
);
131 r4k_tlb_t tlb
[MIPS_TLB_MAX
];
136 int no_mmu_map_address(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
137 target_ulong address
, int rw
, int access_type
);
138 int fixed_mmu_map_address(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
139 target_ulong address
, int rw
, int access_type
);
140 int r4k_map_address(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
141 target_ulong address
, int rw
, int access_type
);
142 void r4k_helper_tlbwi(CPUMIPSState
*env
);
143 void r4k_helper_tlbwr(CPUMIPSState
*env
);
144 void r4k_helper_tlbp(CPUMIPSState
*env
);
145 void r4k_helper_tlbr(CPUMIPSState
*env
);
146 void r4k_helper_tlbinv(CPUMIPSState
*env
);
147 void r4k_helper_tlbinvf(CPUMIPSState
*env
);
148 void r4k_invalidate_tlb(CPUMIPSState
*env
, int idx
, int use_extra
);
149 uint32_t cpu_mips_get_random(CPUMIPSState
*env
);
151 void mips_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
152 vaddr addr
, unsigned size
,
153 MMUAccessType access_type
,
154 int mmu_idx
, MemTxAttrs attrs
,
155 MemTxResult response
, uintptr_t retaddr
);
156 hwaddr
cpu_mips_translate_address(CPUMIPSState
*env
, target_ulong address
,
160 #define cpu_signal_handler cpu_mips_signal_handler
162 #ifndef CONFIG_USER_ONLY
163 extern const VMStateDescription vmstate_mips_cpu
;
166 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState
*env
)
168 return (env
->CP0_Status
& (1 << CP0St_IE
)) &&
169 !(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
170 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
171 !(env
->hflags
& MIPS_HFLAG_DM
) &&
173 * Note that the TCStatus IXMT field is initialized to zero,
174 * and only MT capable cores can set it to one. So we don't
175 * need to check for MT capabilities here.
177 !(env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_IXMT
));
180 /* Check if there is pending and not masked out interrupt */
181 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState
*env
)
187 pending
= env
->CP0_Cause
& CP0Ca_IP_mask
;
188 status
= env
->CP0_Status
& CP0Ca_IP_mask
;
190 if (env
->CP0_Config3
& (1 << CP0C3_VEIC
)) {
192 * A MIPS configured with a vectorizing external interrupt controller
193 * will feed a vector into the Cause pending lines. The core treats
194 * the status lines as a vector level, not as individual masks.
196 r
= pending
> status
;
199 * A MIPS configured with compatibility or VInt (Vectored Interrupts)
200 * treats the pending lines as individual interrupt lines, the status
201 * lines are individual masks.
203 r
= (pending
& status
) != 0;
208 void mips_tcg_init(void);
211 uint32_t cpu_mips_get_count(CPUMIPSState
*env
);
212 void cpu_mips_store_count(CPUMIPSState
*env
, uint32_t value
);
213 void cpu_mips_store_compare(CPUMIPSState
*env
, uint32_t value
);
214 void cpu_mips_start_count(CPUMIPSState
*env
);
215 void cpu_mips_stop_count(CPUMIPSState
*env
);
218 bool mips_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
219 MMUAccessType access_type
, int mmu_idx
,
220 bool probe
, uintptr_t retaddr
);
223 uint32_t float_class_s(uint32_t arg
, float_status
*fst
);
224 uint64_t float_class_d(uint64_t arg
, float_status
*fst
);
226 extern const FloatRoundMode ieee_rm
[4];
228 void update_pagemask(CPUMIPSState
*env
, target_ulong arg1
, int32_t *pagemask
);
230 static inline void restore_rounding_mode(CPUMIPSState
*env
)
232 set_float_rounding_mode(ieee_rm
[env
->active_fpu
.fcr31
& 3],
233 &env
->active_fpu
.fp_status
);
236 static inline void restore_flush_mode(CPUMIPSState
*env
)
238 set_flush_to_zero((env
->active_fpu
.fcr31
& (1 << FCR31_FS
)) != 0,
239 &env
->active_fpu
.fp_status
);
242 static inline void restore_snan_bit_mode(CPUMIPSState
*env
)
244 set_snan_bit_is_one((env
->active_fpu
.fcr31
& (1 << FCR31_NAN2008
)) == 0,
245 &env
->active_fpu
.fp_status
);
248 static inline void restore_fp_status(CPUMIPSState
*env
)
250 restore_rounding_mode(env
);
251 restore_flush_mode(env
);
252 restore_snan_bit_mode(env
);
255 static inline void restore_msa_fp_status(CPUMIPSState
*env
)
257 float_status
*status
= &env
->active_tc
.msa_fp_status
;
258 int rounding_mode
= (env
->active_tc
.msacsr
& MSACSR_RM_MASK
) >> MSACSR_RM
;
259 bool flush_to_zero
= (env
->active_tc
.msacsr
& MSACSR_FS_MASK
) != 0;
261 set_float_rounding_mode(ieee_rm
[rounding_mode
], status
);
262 set_flush_to_zero(flush_to_zero
, status
);
263 set_flush_inputs_to_zero(flush_to_zero
, status
);
266 static inline void restore_pamask(CPUMIPSState
*env
)
268 if (env
->hflags
& MIPS_HFLAG_ELPA
) {
269 env
->PAMask
= (1ULL << env
->PABITS
) - 1;
271 env
->PAMask
= PAMASK_BASE
;
275 static inline int mips_vpe_active(CPUMIPSState
*env
)
279 /* Check that the VPE is enabled. */
280 if (!(env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_EVP
))) {
283 /* Check that the VPE is activated. */
284 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))) {
289 * Now verify that there are active thread contexts in the VPE.
291 * This assumes the CPU model will internally reschedule threads
292 * if the active one goes to sleep. If there are no threads available
293 * the active one will be in a sleeping state, and we can turn off
296 if (!(env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_A
))) {
297 /* TC is not activated. */
300 if (env
->active_tc
.CP0_TCHalt
& 1) {
301 /* TC is in halt state. */
308 static inline int mips_vp_active(CPUMIPSState
*env
)
310 CPUState
*other_cs
= first_cpu
;
312 /* Check if the VP disabled other VPs (which means the VP is enabled) */
313 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
317 /* Check if the virtual processor is disabled due to a DVP */
318 CPU_FOREACH(other_cs
) {
319 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
320 if ((&other_cpu
->env
!= env
) &&
321 ((other_cpu
->env
.CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
328 static inline void compute_hflags(CPUMIPSState
*env
)
330 env
->hflags
&= ~(MIPS_HFLAG_COP1X
| MIPS_HFLAG_64
| MIPS_HFLAG_CP0
|
331 MIPS_HFLAG_F64
| MIPS_HFLAG_FPU
| MIPS_HFLAG_KSU
|
332 MIPS_HFLAG_AWRAP
| MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
|
333 MIPS_HFLAG_DSP_R3
| MIPS_HFLAG_SBRI
| MIPS_HFLAG_MSA
|
334 MIPS_HFLAG_FRE
| MIPS_HFLAG_ELPA
| MIPS_HFLAG_ERL
);
335 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
336 env
->hflags
|= MIPS_HFLAG_ERL
;
338 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
339 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
340 !(env
->hflags
& MIPS_HFLAG_DM
)) {
341 env
->hflags
|= (env
->CP0_Status
>> CP0St_KSU
) &
344 #if defined(TARGET_MIPS64)
345 if ((env
->insn_flags
& ISA_MIPS3
) &&
346 (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_UM
) ||
347 (env
->CP0_Status
& (1 << CP0St_PX
)) ||
348 (env
->CP0_Status
& (1 << CP0St_UX
)))) {
349 env
->hflags
|= MIPS_HFLAG_64
;
352 if (!(env
->insn_flags
& ISA_MIPS3
)) {
353 env
->hflags
|= MIPS_HFLAG_AWRAP
;
354 } else if (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
355 !(env
->CP0_Status
& (1 << CP0St_UX
))) {
356 env
->hflags
|= MIPS_HFLAG_AWRAP
;
357 } else if (env
->insn_flags
& ISA_MIPS64R6
) {
358 /* Address wrapping for Supervisor and Kernel is specified in R6 */
359 if ((((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_SM
) &&
360 !(env
->CP0_Status
& (1 << CP0St_SX
))) ||
361 (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_KM
) &&
362 !(env
->CP0_Status
& (1 << CP0St_KX
)))) {
363 env
->hflags
|= MIPS_HFLAG_AWRAP
;
367 if (((env
->CP0_Status
& (1 << CP0St_CU0
)) &&
368 !(env
->insn_flags
& ISA_MIPS32R6
)) ||
369 !(env
->hflags
& MIPS_HFLAG_KSU
)) {
370 env
->hflags
|= MIPS_HFLAG_CP0
;
372 if (env
->CP0_Status
& (1 << CP0St_CU1
)) {
373 env
->hflags
|= MIPS_HFLAG_FPU
;
375 if (env
->CP0_Status
& (1 << CP0St_FR
)) {
376 env
->hflags
|= MIPS_HFLAG_F64
;
378 if (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_KM
) &&
379 (env
->CP0_Config5
& (1 << CP0C5_SBRI
))) {
380 env
->hflags
|= MIPS_HFLAG_SBRI
;
382 if (env
->insn_flags
& ASE_DSP_R3
) {
384 * Our cpu supports DSP R3 ASE, so enable
385 * access to DSP R3 resources.
387 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
388 env
->hflags
|= MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
|
391 } else if (env
->insn_flags
& ASE_DSP_R2
) {
393 * Our cpu supports DSP R2 ASE, so enable
394 * access to DSP R2 resources.
396 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
397 env
->hflags
|= MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
;
400 } else if (env
->insn_flags
& ASE_DSP
) {
402 * Our cpu supports DSP ASE, so enable
403 * access to DSP resources.
405 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
406 env
->hflags
|= MIPS_HFLAG_DSP
;
410 if (env
->insn_flags
& ISA_MIPS32R2
) {
411 if (env
->active_fpu
.fcr0
& (1 << FCR0_F64
)) {
412 env
->hflags
|= MIPS_HFLAG_COP1X
;
414 } else if (env
->insn_flags
& ISA_MIPS32
) {
415 if (env
->hflags
& MIPS_HFLAG_64
) {
416 env
->hflags
|= MIPS_HFLAG_COP1X
;
418 } else if (env
->insn_flags
& ISA_MIPS4
) {
420 * All supported MIPS IV CPUs use the XX (CU3) to enable
421 * and disable the MIPS IV extensions to the MIPS III ISA.
422 * Some other MIPS IV CPUs ignore the bit, so the check here
423 * would be too restrictive for them.
425 if (env
->CP0_Status
& (1U << CP0St_CU3
)) {
426 env
->hflags
|= MIPS_HFLAG_COP1X
;
429 if (env
->insn_flags
& ASE_MSA
) {
430 if (env
->CP0_Config5
& (1 << CP0C5_MSAEn
)) {
431 env
->hflags
|= MIPS_HFLAG_MSA
;
434 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
435 if (env
->CP0_Config5
& (1 << CP0C5_FRE
)) {
436 env
->hflags
|= MIPS_HFLAG_FRE
;
439 if (env
->CP0_Config3
& (1 << CP0C3_LPA
)) {
440 if (env
->CP0_PageGrain
& (1 << CP0PG_ELPA
)) {
441 env
->hflags
|= MIPS_HFLAG_ELPA
;
446 void cpu_mips_tlb_flush(CPUMIPSState
*env
);
447 void sync_c0_status(CPUMIPSState
*env
, CPUMIPSState
*cpu
, int tc
);
448 void cpu_mips_store_status(CPUMIPSState
*env
, target_ulong val
);
449 void cpu_mips_store_cause(CPUMIPSState
*env
, target_ulong val
);
451 void QEMU_NORETURN
do_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
452 int error_code
, uintptr_t pc
);
454 static inline void QEMU_NORETURN
do_raise_exception(CPUMIPSState
*env
,
458 do_raise_exception_err(env
, exception
, 0, pc
);