target/mips/internal.h

   1 /*
   2  * MIPS internal definitions and helpers
   3  *
   4  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   5  * See the COPYING file in the top-level directory.
   6  */
   7
   8 #ifndef MIPS_INTERNAL_H
   9 #define MIPS_INTERNAL_H
  10
  11 #include "exec/memattrs.h"
  12
  13 /*
  14  * MMU types, the first four entries have the same layout as the
  15  * CP0C0_MT field.
  16  */
  17 enum mips_mmu_types {
  18     MMU_TYPE_NONE       = 0,
  19     MMU_TYPE_R4000      = 1,    /* Standard TLB */
  20     MMU_TYPE_BAT        = 2,    /* Block Address Translation */
  21     MMU_TYPE_FMT        = 3,    /* Fixed Mapping */
  22     MMU_TYPE_DVF        = 4,    /* Dual VTLB and FTLB */
  23     MMU_TYPE_R3000,
  24     MMU_TYPE_R6000,
  25     MMU_TYPE_R8000
  26 };
  27
  28 struct mips_def_t {
  29     const char *name;
  30     int32_t CP0_PRid;
  31     int32_t CP0_Config0;
  32     int32_t CP0_Config1;
  33     int32_t CP0_Config2;
  34     int32_t CP0_Config3;
  35     int32_t CP0_Config4;
  36     int32_t CP0_Config4_rw_bitmask;
  37     int32_t CP0_Config5;
  38     int32_t CP0_Config5_rw_bitmask;
  39     int32_t CP0_Config6;
  40     int32_t CP0_Config6_rw_bitmask;
  41     int32_t CP0_Config7;
  42     int32_t CP0_Config7_rw_bitmask;
  43     target_ulong CP0_LLAddr_rw_bitmask;
  44     int CP0_LLAddr_shift;
  45     int32_t SYNCI_Step;
  46     int32_t CCRes;
  47     int32_t CP0_Status_rw_bitmask;
  48     int32_t CP0_TCStatus_rw_bitmask;
  49     int32_t CP0_SRSCtl;
  50     int32_t CP1_fcr0;
  51     int32_t CP1_fcr31_rw_bitmask;
  52     int32_t CP1_fcr31;
  53     int32_t MSAIR;
  54     int32_t SEGBITS;
  55     int32_t PABITS;
  56     int32_t CP0_SRSConf0_rw_bitmask;
  57     int32_t CP0_SRSConf0;
  58     int32_t CP0_SRSConf1_rw_bitmask;
  59     int32_t CP0_SRSConf1;
  60     int32_t CP0_SRSConf2_rw_bitmask;
  61     int32_t CP0_SRSConf2;
  62     int32_t CP0_SRSConf3_rw_bitmask;
  63     int32_t CP0_SRSConf3;
  64     int32_t CP0_SRSConf4_rw_bitmask;
  65     int32_t CP0_SRSConf4;
  66     int32_t CP0_PageGrain_rw_bitmask;
  67     int32_t CP0_PageGrain;
  68     target_ulong CP0_EBaseWG_rw_bitmask;
  69     uint64_t insn_flags;
  70     enum mips_mmu_types mmu_type;
  71     int32_t SAARP;
  72 };
  73
  74 extern const char regnames[32][4];
  75 extern const char fregnames[32][4];
  76
  77 extern const struct mips_def_t mips_defs[];
  78 extern const int mips_defs_number;
  79
  80 void mips_cpu_do_interrupt(CPUState *cpu);
  81 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
  82 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
  83 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
  84 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  85 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
  86                                   MMUAccessType access_type,
  87                                   int mmu_idx, uintptr_t retaddr);
  88
  89 #if !defined(CONFIG_USER_ONLY)
  90
  91 typedef struct r4k_tlb_t r4k_tlb_t;
  92 struct r4k_tlb_t {
  93     target_ulong VPN;
  94     uint32_t PageMask;
  95     uint16_t ASID;
  96     uint32_t MMID;
  97     unsigned int G:1;
  98     unsigned int C0:3;
  99     unsigned int C1:3;
 100     unsigned int V0:1;
 101     unsigned int V1:1;
 102     unsigned int D0:1;
 103     unsigned int D1:1;
 104     unsigned int XI0:1;
 105     unsigned int XI1:1;
 106     unsigned int RI0:1;
 107     unsigned int RI1:1;
 108     unsigned int EHINV:1;
 109     uint64_t PFN[2];
 110 };
 111
 112 struct CPUMIPSTLBContext {
 113     uint32_t nb_tlb;
 114     uint32_t tlb_in_use;
 115     int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
 116                        target_ulong address, MMUAccessType access_type);
 117     void (*helper_tlbwi)(struct CPUMIPSState *env);
 118     void (*helper_tlbwr)(struct CPUMIPSState *env);
 119     void (*helper_tlbp)(struct CPUMIPSState *env);
 120     void (*helper_tlbr)(struct CPUMIPSState *env);
 121     void (*helper_tlbinv)(struct CPUMIPSState *env);
 122     void (*helper_tlbinvf)(struct CPUMIPSState *env);
 123     union {
 124         struct {
 125             r4k_tlb_t tlb[MIPS_TLB_MAX];
 126         } r4k;
 127     } mmu;
 128 };
 129
 130 int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
 131                        target_ulong address, MMUAccessType access_type);
 132 int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
 133                           target_ulong address, MMUAccessType access_type);
 134 int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
 135                     target_ulong address, MMUAccessType access_type);
 136 void r4k_helper_tlbwi(CPUMIPSState *env);
 137 void r4k_helper_tlbwr(CPUMIPSState *env);
 138 void r4k_helper_tlbp(CPUMIPSState *env);
 139 void r4k_helper_tlbr(CPUMIPSState *env);
 140 void r4k_helper_tlbinv(CPUMIPSState *env);
 141 void r4k_helper_tlbinvf(CPUMIPSState *env);
 142 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
 143 uint32_t cpu_mips_get_random(CPUMIPSState *env);
 144
 145 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 146                                     vaddr addr, unsigned size,
 147                                     MMUAccessType access_type,
 148                                     int mmu_idx, MemTxAttrs attrs,
 149                                     MemTxResult response, uintptr_t retaddr);
 150 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
 151                                   MMUAccessType access_type);
 152 #endif
 153
 154 #define cpu_signal_handler cpu_mips_signal_handler
 155
 156 #ifndef CONFIG_USER_ONLY
 157 extern const VMStateDescription vmstate_mips_cpu;
 158 #endif
 159
 160 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 161 {
 162     return (env->CP0_Status & (1 << CP0St_IE)) &&
 163         !(env->CP0_Status & (1 << CP0St_EXL)) &&
 164         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 165         !(env->hflags & MIPS_HFLAG_DM) &&
 166         /*
 167          * Note that the TCStatus IXMT field is initialized to zero,
 168          * and only MT capable cores can set it to one. So we don't
 169          * need to check for MT capabilities here.
 170          */
 171         !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
 172 }
 173
 174 /* Check if there is pending and not masked out interrupt */
 175 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 176 {
 177     int32_t pending;
 178     int32_t status;
 179     bool r;
 180
 181     pending = env->CP0_Cause & CP0Ca_IP_mask;
 182     status = env->CP0_Status & CP0Ca_IP_mask;
 183
 184     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 185         /*
 186          * A MIPS configured with a vectorizing external interrupt controller
 187          * will feed a vector into the Cause pending lines. The core treats
 188          * the status lines as a vector level, not as individual masks.
 189          */
 190         r = pending > status;
 191     } else {
 192         /*
 193          * A MIPS configured with compatibility or VInt (Vectored Interrupts)
 194          * treats the pending lines as individual interrupt lines, the status
 195          * lines are individual masks.
 196          */
 197         r = (pending & status) != 0;
 198     }
 199     return r;
 200 }
 201
 202 void mips_tcg_init(void);
 203
 204 void msa_reset(CPUMIPSState *env);
 205
 206 /* cp0_timer.c */
 207 uint32_t cpu_mips_get_count(CPUMIPSState *env);
 208 void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
 209 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
 210 void cpu_mips_start_count(CPUMIPSState *env);
 211 void cpu_mips_stop_count(CPUMIPSState *env);
 212
 213 /* helper.c */
 214 void mmu_init(CPUMIPSState *env, const mips_def_t *def);
 215 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 216                        MMUAccessType access_type, int mmu_idx,
 217                        bool probe, uintptr_t retaddr);
 218
 219 /* op_helper.c */
 220 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
 221
 222 static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
 223 {
 224     env->active_tc.PC = value & ~(target_ulong)1;
 225     if (value & 1) {
 226         env->hflags |= MIPS_HFLAG_M16;
 227     } else {
 228         env->hflags &= ~(MIPS_HFLAG_M16);
 229     }
 230 }
 231
 232 static inline void restore_pamask(CPUMIPSState *env)
 233 {
 234     if (env->hflags & MIPS_HFLAG_ELPA) {
 235         env->PAMask = (1ULL << env->PABITS) - 1;
 236     } else {
 237         env->PAMask = PAMASK_BASE;
 238     }
 239 }
 240
 241 static inline int mips_vpe_active(CPUMIPSState *env)
 242 {
 243     int active = 1;
 244
 245     /* Check that the VPE is enabled.  */
 246     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 247         active = 0;
 248     }
 249     /* Check that the VPE is activated.  */
 250     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 251         active = 0;
 252     }
 253
 254     /*
 255      * Now verify that there are active thread contexts in the VPE.
 256      *
 257      * This assumes the CPU model will internally reschedule threads
 258      * if the active one goes to sleep. If there are no threads available
 259      * the active one will be in a sleeping state, and we can turn off
 260      * the entire VPE.
 261      */
 262     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 263         /* TC is not activated.  */
 264         active = 0;
 265     }
 266     if (env->active_tc.CP0_TCHalt & 1) {
 267         /* TC is in halt state.  */
 268         active = 0;
 269     }
 270
 271     return active;
 272 }
 273
 274 static inline int mips_vp_active(CPUMIPSState *env)
 275 {
 276     CPUState *other_cs = first_cpu;
 277
 278     /* Check if the VP disabled other VPs (which means the VP is enabled) */
 279     if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
 280         return 1;
 281     }
 282
 283     /* Check if the virtual processor is disabled due to a DVP */
 284     CPU_FOREACH(other_cs) {
 285         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
 286         if ((&other_cpu->env != env) &&
 287             ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
 288             return 0;
 289         }
 290     }
 291     return 1;
 292 }
 293
 294 static inline void compute_hflags(CPUMIPSState *env)
 295 {
 296     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 297                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 298                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
 299                      MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
 300                      MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
 301     if (env->CP0_Status & (1 << CP0St_ERL)) {
 302         env->hflags |= MIPS_HFLAG_ERL;
 303     }
 304     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 305         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 306         !(env->hflags & MIPS_HFLAG_DM)) {
 307         env->hflags |= (env->CP0_Status >> CP0St_KSU) &
 308                        MIPS_HFLAG_KSU;
 309     }
 310 #if defined(TARGET_MIPS64)
 311     if ((env->insn_flags & ISA_MIPS3) &&
 312         (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 313          (env->CP0_Status & (1 << CP0St_PX)) ||
 314          (env->CP0_Status & (1 << CP0St_UX)))) {
 315         env->hflags |= MIPS_HFLAG_64;
 316     }
 317
 318     if (!(env->insn_flags & ISA_MIPS3)) {
 319         env->hflags |= MIPS_HFLAG_AWRAP;
 320     } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 321                !(env->CP0_Status & (1 << CP0St_UX))) {
 322         env->hflags |= MIPS_HFLAG_AWRAP;
 323     } else if (env->insn_flags & ISA_MIPS_R6) {
 324         /* Address wrapping for Supervisor and Kernel is specified in R6 */
 325         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 326              !(env->CP0_Status & (1 << CP0St_SX))) ||
 327             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 328              !(env->CP0_Status & (1 << CP0St_KX)))) {
 329             env->hflags |= MIPS_HFLAG_AWRAP;
 330         }
 331     }
 332 #endif
 333     if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 334          !(env->insn_flags & ISA_MIPS_R6)) ||
 335         !(env->hflags & MIPS_HFLAG_KSU)) {
 336         env->hflags |= MIPS_HFLAG_CP0;
 337     }
 338     if (env->CP0_Status & (1 << CP0St_CU1)) {
 339         env->hflags |= MIPS_HFLAG_FPU;
 340     }
 341     if (env->CP0_Status & (1 << CP0St_FR)) {
 342         env->hflags |= MIPS_HFLAG_F64;
 343     }
 344     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 345         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 346         env->hflags |= MIPS_HFLAG_SBRI;
 347     }
 348     if (env->insn_flags & ASE_DSP_R3) {
 349         /*
 350          * Our cpu supports DSP R3 ASE, so enable
 351          * access to DSP R3 resources.
 352          */
 353         if (env->CP0_Status & (1 << CP0St_MX)) {
 354             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
 355                            MIPS_HFLAG_DSP_R3;
 356         }
 357     } else if (env->insn_flags & ASE_DSP_R2) {
 358         /*
 359          * Our cpu supports DSP R2 ASE, so enable
 360          * access to DSP R2 resources.
 361          */
 362         if (env->CP0_Status & (1 << CP0St_MX)) {
 363             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
 364         }
 365
 366     } else if (env->insn_flags & ASE_DSP) {
 367         /*
 368          * Our cpu supports DSP ASE, so enable
 369          * access to DSP resources.
 370          */
 371         if (env->CP0_Status & (1 << CP0St_MX)) {
 372             env->hflags |= MIPS_HFLAG_DSP;
 373         }
 374
 375     }
 376     if (env->insn_flags & ISA_MIPS_R2) {
 377         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 378             env->hflags |= MIPS_HFLAG_COP1X;
 379         }
 380     } else if (env->insn_flags & ISA_MIPS_R1) {
 381         if (env->hflags & MIPS_HFLAG_64) {
 382             env->hflags |= MIPS_HFLAG_COP1X;
 383         }
 384     } else if (env->insn_flags & ISA_MIPS4) {
 385         /*
 386          * All supported MIPS IV CPUs use the XX (CU3) to enable
 387          * and disable the MIPS IV extensions to the MIPS III ISA.
 388          * Some other MIPS IV CPUs ignore the bit, so the check here
 389          * would be too restrictive for them.
 390          */
 391         if (env->CP0_Status & (1U << CP0St_CU3)) {
 392             env->hflags |= MIPS_HFLAG_COP1X;
 393         }
 394     }
 395     if (ase_msa_available(env)) {
 396         if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
 397             env->hflags |= MIPS_HFLAG_MSA;
 398         }
 399     }
 400     if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
 401         if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
 402             env->hflags |= MIPS_HFLAG_FRE;
 403         }
 404     }
 405     if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
 406         if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
 407             env->hflags |= MIPS_HFLAG_ELPA;
 408         }
 409     }
 410 }
 411
 412 void cpu_mips_tlb_flush(CPUMIPSState *env);
 413 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 414 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 415 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
 416
 417 const char *mips_exception_name(int32_t exception);
 418
 419 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
 420                                           int error_code, uintptr_t pc);
 421
 422 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
 423                                                     uint32_t exception,
 424                                                     uintptr_t pc)
 425 {
 426     do_raise_exception_err(env, exception, 0, pc);
 427 }
 428
 429 #endif