target/mips/internal.h

   1 /*
   2  * MIPS internal definitions and helpers
   3  *
   4  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   5  * See the COPYING file in the top-level directory.
   6  */
   7
   8 #ifndef MIPS_INTERNAL_H
   9 #define MIPS_INTERNAL_H
  10
  11 #include "exec/memattrs.h"
  12 #ifdef CONFIG_TCG
  13 #include "tcg/tcg-internal.h"
  14 #endif
  15
  16 /*
  17  * MMU types, the first four entries have the same layout as the
  18  * CP0C0_MT field.
  19  */
  20 enum mips_mmu_types {
  21     MMU_TYPE_NONE       = 0,
  22     MMU_TYPE_R4000      = 1,    /* Standard TLB */
  23     MMU_TYPE_BAT        = 2,    /* Block Address Translation */
  24     MMU_TYPE_FMT        = 3,    /* Fixed Mapping */
  25     MMU_TYPE_DVF        = 4,    /* Dual VTLB and FTLB */
  26     MMU_TYPE_R3000,
  27     MMU_TYPE_R6000,
  28     MMU_TYPE_R8000
  29 };
  30
  31 struct mips_def_t {
  32     const char *name;
  33     int32_t CP0_PRid;
  34     int32_t CP0_Config0;
  35     int32_t CP0_Config1;
  36     int32_t CP0_Config2;
  37     int32_t CP0_Config3;
  38     int32_t CP0_Config4;
  39     int32_t CP0_Config4_rw_bitmask;
  40     int32_t CP0_Config5;
  41     int32_t CP0_Config5_rw_bitmask;
  42     int32_t CP0_Config6;
  43     int32_t CP0_Config6_rw_bitmask;
  44     int32_t CP0_Config7;
  45     int32_t CP0_Config7_rw_bitmask;
  46     target_ulong CP0_LLAddr_rw_bitmask;
  47     int CP0_LLAddr_shift;
  48     int32_t SYNCI_Step;
  49     int32_t CCRes;
  50     int32_t CP0_Status_rw_bitmask;
  51     int32_t CP0_TCStatus_rw_bitmask;
  52     int32_t CP0_SRSCtl;
  53     int32_t CP1_fcr0;
  54     int32_t CP1_fcr31_rw_bitmask;
  55     int32_t CP1_fcr31;
  56     int32_t MSAIR;
  57     int32_t SEGBITS;
  58     int32_t PABITS;
  59     int32_t CP0_SRSConf0_rw_bitmask;
  60     int32_t CP0_SRSConf0;
  61     int32_t CP0_SRSConf1_rw_bitmask;
  62     int32_t CP0_SRSConf1;
  63     int32_t CP0_SRSConf2_rw_bitmask;
  64     int32_t CP0_SRSConf2;
  65     int32_t CP0_SRSConf3_rw_bitmask;
  66     int32_t CP0_SRSConf3;
  67     int32_t CP0_SRSConf4_rw_bitmask;
  68     int32_t CP0_SRSConf4;
  69     int32_t CP0_PageGrain_rw_bitmask;
  70     int32_t CP0_PageGrain;
  71     target_ulong CP0_EBaseWG_rw_bitmask;
  72     uint64_t insn_flags;
  73     enum mips_mmu_types mmu_type;
  74     int32_t SAARP;
  75 };
  76
  77 extern const char regnames[32][4];
  78 extern const char fregnames[32][4];
  79
  80 extern const struct mips_def_t mips_defs[];
  81 extern const int mips_defs_number;
  82
  83 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
  84 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  85 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
  86                                   MMUAccessType access_type,
  87                                   int mmu_idx, uintptr_t retaddr);
  88
  89 #define USEG_LIMIT      ((target_ulong)(int32_t)0x7FFFFFFFUL)
  90 #define KSEG0_BASE      ((target_ulong)(int32_t)0x80000000UL)
  91 #define KSEG1_BASE      ((target_ulong)(int32_t)0xA0000000UL)
  92 #define KSEG2_BASE      ((target_ulong)(int32_t)0xC0000000UL)
  93 #define KSEG3_BASE      ((target_ulong)(int32_t)0xE0000000UL)
  94
  95 #define KVM_KSEG0_BASE  ((target_ulong)(int32_t)0x40000000UL)
  96 #define KVM_KSEG2_BASE  ((target_ulong)(int32_t)0x60000000UL)
  97
  98 #if !defined(CONFIG_USER_ONLY)
  99
 100 enum {
 101     TLBRET_XI = -6,
 102     TLBRET_RI = -5,
 103     TLBRET_DIRTY = -4,
 104     TLBRET_INVALID = -3,
 105     TLBRET_NOMATCH = -2,
 106     TLBRET_BADADDR = -1,
 107     TLBRET_MATCH = 0
 108 };
 109
 110 int get_physical_address(CPUMIPSState *env, hwaddr *physical,
 111                          int *prot, target_ulong real_address,
 112                          MMUAccessType access_type, int mmu_idx);
 113 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 114
 115 typedef struct r4k_tlb_t r4k_tlb_t;
 116 struct r4k_tlb_t {
 117     target_ulong VPN;
 118     uint32_t PageMask;
 119     uint16_t ASID;
 120     uint32_t MMID;
 121     unsigned int G:1;
 122     unsigned int C0:3;
 123     unsigned int C1:3;
 124     unsigned int V0:1;
 125     unsigned int V1:1;
 126     unsigned int D0:1;
 127     unsigned int D1:1;
 128     unsigned int XI0:1;
 129     unsigned int XI1:1;
 130     unsigned int RI0:1;
 131     unsigned int RI1:1;
 132     unsigned int EHINV:1;
 133     uint64_t PFN[2];
 134 };
 135
 136 struct CPUMIPSTLBContext {
 137     uint32_t nb_tlb;
 138     uint32_t tlb_in_use;
 139     int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
 140                        target_ulong address, MMUAccessType access_type);
 141     void (*helper_tlbwi)(struct CPUMIPSState *env);
 142     void (*helper_tlbwr)(struct CPUMIPSState *env);
 143     void (*helper_tlbp)(struct CPUMIPSState *env);
 144     void (*helper_tlbr)(struct CPUMIPSState *env);
 145     void (*helper_tlbinv)(struct CPUMIPSState *env);
 146     void (*helper_tlbinvf)(struct CPUMIPSState *env);
 147     union {
 148         struct {
 149             r4k_tlb_t tlb[MIPS_TLB_MAX];
 150         } r4k;
 151     } mmu;
 152 };
 153
 154 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 155                                     vaddr addr, unsigned size,
 156                                     MMUAccessType access_type,
 157                                     int mmu_idx, MemTxAttrs attrs,
 158                                     MemTxResult response, uintptr_t retaddr);
 159
 160 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 161 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 162 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
 163
 164 extern const VMStateDescription vmstate_mips_cpu;
 165
 166 #endif /* !CONFIG_USER_ONLY */
 167
 168 #define cpu_signal_handler cpu_mips_signal_handler
 169
 170 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 171 {
 172     return (env->CP0_Status & (1 << CP0St_IE)) &&
 173         !(env->CP0_Status & (1 << CP0St_EXL)) &&
 174         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 175         !(env->hflags & MIPS_HFLAG_DM) &&
 176         /*
 177          * Note that the TCStatus IXMT field is initialized to zero,
 178          * and only MT capable cores can set it to one. So we don't
 179          * need to check for MT capabilities here.
 180          */
 181         !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
 182 }
 183
 184 /* Check if there is pending and not masked out interrupt */
 185 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 186 {
 187     int32_t pending;
 188     int32_t status;
 189     bool r;
 190
 191     pending = env->CP0_Cause & CP0Ca_IP_mask;
 192     status = env->CP0_Status & CP0Ca_IP_mask;
 193
 194     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 195         /*
 196          * A MIPS configured with a vectorizing external interrupt controller
 197          * will feed a vector into the Cause pending lines. The core treats
 198          * the status lines as a vector level, not as individual masks.
 199          */
 200         r = pending > status;
 201     } else {
 202         /*
 203          * A MIPS configured with compatibility or VInt (Vectored Interrupts)
 204          * treats the pending lines as individual interrupt lines, the status
 205          * lines are individual masks.
 206          */
 207         r = (pending & status) != 0;
 208     }
 209     return r;
 210 }
 211
 212 void mips_tcg_init(void);
 213
 214 void msa_reset(CPUMIPSState *env);
 215
 216 /* cp0_timer.c */
 217 uint32_t cpu_mips_get_count(CPUMIPSState *env);
 218 void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
 219 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
 220 void cpu_mips_start_count(CPUMIPSState *env);
 221 void cpu_mips_stop_count(CPUMIPSState *env);
 222
 223 static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
 224 {
 225     env->active_tc.PC = value & ~(target_ulong)1;
 226     if (value & 1) {
 227         env->hflags |= MIPS_HFLAG_M16;
 228     } else {
 229         env->hflags &= ~(MIPS_HFLAG_M16);
 230     }
 231 }
 232
 233 static inline void restore_pamask(CPUMIPSState *env)
 234 {
 235     if (env->hflags & MIPS_HFLAG_ELPA) {
 236         env->PAMask = (1ULL << env->PABITS) - 1;
 237     } else {
 238         env->PAMask = PAMASK_BASE;
 239     }
 240 }
 241
 242 static inline int mips_vpe_active(CPUMIPSState *env)
 243 {
 244     int active = 1;
 245
 246     /* Check that the VPE is enabled.  */
 247     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 248         active = 0;
 249     }
 250     /* Check that the VPE is activated.  */
 251     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 252         active = 0;
 253     }
 254
 255     /*
 256      * Now verify that there are active thread contexts in the VPE.
 257      *
 258      * This assumes the CPU model will internally reschedule threads
 259      * if the active one goes to sleep. If there are no threads available
 260      * the active one will be in a sleeping state, and we can turn off
 261      * the entire VPE.
 262      */
 263     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 264         /* TC is not activated.  */
 265         active = 0;
 266     }
 267     if (env->active_tc.CP0_TCHalt & 1) {
 268         /* TC is in halt state.  */
 269         active = 0;
 270     }
 271
 272     return active;
 273 }
 274
 275 static inline int mips_vp_active(CPUMIPSState *env)
 276 {
 277     CPUState *other_cs = first_cpu;
 278
 279     /* Check if the VP disabled other VPs (which means the VP is enabled) */
 280     if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
 281         return 1;
 282     }
 283
 284     /* Check if the virtual processor is disabled due to a DVP */
 285     CPU_FOREACH(other_cs) {
 286         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
 287         if ((&other_cpu->env != env) &&
 288             ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
 289             return 0;
 290         }
 291     }
 292     return 1;
 293 }
 294
 295 static inline void compute_hflags(CPUMIPSState *env)
 296 {
 297     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 298                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 299                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
 300                      MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
 301                      MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
 302     if (env->CP0_Status & (1 << CP0St_ERL)) {
 303         env->hflags |= MIPS_HFLAG_ERL;
 304     }
 305     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 306         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 307         !(env->hflags & MIPS_HFLAG_DM)) {
 308         env->hflags |= (env->CP0_Status >> CP0St_KSU) &
 309                        MIPS_HFLAG_KSU;
 310     }
 311 #if defined(TARGET_MIPS64)
 312     if ((env->insn_flags & ISA_MIPS3) &&
 313         (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 314          (env->CP0_Status & (1 << CP0St_PX)) ||
 315          (env->CP0_Status & (1 << CP0St_UX)))) {
 316         env->hflags |= MIPS_HFLAG_64;
 317     }
 318
 319     if (!(env->insn_flags & ISA_MIPS3)) {
 320         env->hflags |= MIPS_HFLAG_AWRAP;
 321     } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 322                !(env->CP0_Status & (1 << CP0St_UX))) {
 323         env->hflags |= MIPS_HFLAG_AWRAP;
 324     } else if (env->insn_flags & ISA_MIPS_R6) {
 325         /* Address wrapping for Supervisor and Kernel is specified in R6 */
 326         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 327              !(env->CP0_Status & (1 << CP0St_SX))) ||
 328             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 329              !(env->CP0_Status & (1 << CP0St_KX)))) {
 330             env->hflags |= MIPS_HFLAG_AWRAP;
 331         }
 332     }
 333 #endif
 334     if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 335          !(env->insn_flags & ISA_MIPS_R6)) ||
 336         !(env->hflags & MIPS_HFLAG_KSU)) {
 337         env->hflags |= MIPS_HFLAG_CP0;
 338     }
 339     if (env->CP0_Status & (1 << CP0St_CU1)) {
 340         env->hflags |= MIPS_HFLAG_FPU;
 341     }
 342     if (env->CP0_Status & (1 << CP0St_FR)) {
 343         env->hflags |= MIPS_HFLAG_F64;
 344     }
 345     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 346         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 347         env->hflags |= MIPS_HFLAG_SBRI;
 348     }
 349     if (env->insn_flags & ASE_DSP_R3) {
 350         /*
 351          * Our cpu supports DSP R3 ASE, so enable
 352          * access to DSP R3 resources.
 353          */
 354         if (env->CP0_Status & (1 << CP0St_MX)) {
 355             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
 356                            MIPS_HFLAG_DSP_R3;
 357         }
 358     } else if (env->insn_flags & ASE_DSP_R2) {
 359         /*
 360          * Our cpu supports DSP R2 ASE, so enable
 361          * access to DSP R2 resources.
 362          */
 363         if (env->CP0_Status & (1 << CP0St_MX)) {
 364             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
 365         }
 366
 367     } else if (env->insn_flags & ASE_DSP) {
 368         /*
 369          * Our cpu supports DSP ASE, so enable
 370          * access to DSP resources.
 371          */
 372         if (env->CP0_Status & (1 << CP0St_MX)) {
 373             env->hflags |= MIPS_HFLAG_DSP;
 374         }
 375
 376     }
 377     if (env->insn_flags & ISA_MIPS_R2) {
 378         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 379             env->hflags |= MIPS_HFLAG_COP1X;
 380         }
 381     } else if (env->insn_flags & ISA_MIPS_R1) {
 382         if (env->hflags & MIPS_HFLAG_64) {
 383             env->hflags |= MIPS_HFLAG_COP1X;
 384         }
 385     } else if (env->insn_flags & ISA_MIPS4) {
 386         /*
 387          * All supported MIPS IV CPUs use the XX (CU3) to enable
 388          * and disable the MIPS IV extensions to the MIPS III ISA.
 389          * Some other MIPS IV CPUs ignore the bit, so the check here
 390          * would be too restrictive for them.
 391          */
 392         if (env->CP0_Status & (1U << CP0St_CU3)) {
 393             env->hflags |= MIPS_HFLAG_COP1X;
 394         }
 395     }
 396     if (ase_msa_available(env)) {
 397         if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
 398             env->hflags |= MIPS_HFLAG_MSA;
 399         }
 400     }
 401     if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
 402         if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
 403             env->hflags |= MIPS_HFLAG_FRE;
 404         }
 405     }
 406     if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
 407         if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
 408             env->hflags |= MIPS_HFLAG_ELPA;
 409         }
 410     }
 411 }
 412
 413 #endif