2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
23 #include "qemu/host-utils.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "sysemu/kvm.h"
29 /*****************************************************************************/
30 /* Exceptions processing helpers */
32 void helper_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
35 do_raise_exception_err(env
, exception
, error_code
, 0);
38 void helper_raise_exception(CPUMIPSState
*env
, uint32_t exception
)
40 do_raise_exception(env
, exception
, GETPC());
43 void helper_raise_exception_debug(CPUMIPSState
*env
)
45 do_raise_exception(env
, EXCP_DEBUG
, 0);
48 static void raise_exception(CPUMIPSState
*env
, uint32_t exception
)
50 do_raise_exception(env
, exception
, 0);
53 #if defined(CONFIG_USER_ONLY)
54 #define HELPER_LD(name, insn, type) \
55 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
56 int mem_idx, uintptr_t retaddr) \
58 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
61 #define HELPER_LD(name, insn, type) \
62 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
63 int mem_idx, uintptr_t retaddr) \
67 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
68 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
70 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
71 case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \
75 HELPER_LD(lw
, ldl
, int32_t)
76 #if defined(TARGET_MIPS64)
77 HELPER_LD(ld
, ldq
, int64_t)
81 #if defined(CONFIG_USER_ONLY)
82 #define HELPER_ST(name, insn, type) \
83 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
84 type val, int mem_idx, uintptr_t retaddr) \
86 cpu_##insn##_data_ra(env, addr, val, retaddr); \
89 #define HELPER_ST(name, insn, type) \
90 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
91 type val, int mem_idx, uintptr_t retaddr) \
95 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
96 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
98 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
100 cpu_##insn##_error_ra(env, addr, val, retaddr); \
105 HELPER_ST(sb
, stb
, uint8_t)
106 HELPER_ST(sw
, stl
, uint32_t)
107 #if defined(TARGET_MIPS64)
108 HELPER_ST(sd
, stq
, uint64_t)
112 /* 64 bits arithmetic for 32 bits hosts */
113 static inline uint64_t get_HILO(CPUMIPSState
*env
)
115 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) | (uint32_t)env
->active_tc
.LO
[0];
118 static inline target_ulong
set_HIT0_LO(CPUMIPSState
*env
, uint64_t HILO
)
120 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
121 return env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
124 static inline target_ulong
set_HI_LOT0(CPUMIPSState
*env
, uint64_t HILO
)
126 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
127 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
131 /* Multiplication variants of the vr54xx. */
132 target_ulong
helper_muls(CPUMIPSState
*env
, target_ulong arg1
,
135 return set_HI_LOT0(env
, 0 - ((int64_t)(int32_t)arg1
*
136 (int64_t)(int32_t)arg2
));
139 target_ulong
helper_mulsu(CPUMIPSState
*env
, target_ulong arg1
,
142 return set_HI_LOT0(env
, 0 - (uint64_t)(uint32_t)arg1
*
143 (uint64_t)(uint32_t)arg2
);
146 target_ulong
helper_macc(CPUMIPSState
*env
, target_ulong arg1
,
149 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
150 (int64_t)(int32_t)arg2
);
153 target_ulong
helper_macchi(CPUMIPSState
*env
, target_ulong arg1
,
156 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
157 (int64_t)(int32_t)arg2
);
160 target_ulong
helper_maccu(CPUMIPSState
*env
, target_ulong arg1
,
163 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) +
164 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
167 target_ulong
helper_macchiu(CPUMIPSState
*env
, target_ulong arg1
,
170 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) +
171 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
174 target_ulong
helper_msac(CPUMIPSState
*env
, target_ulong arg1
,
177 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
178 (int64_t)(int32_t)arg2
);
181 target_ulong
helper_msachi(CPUMIPSState
*env
, target_ulong arg1
,
184 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
185 (int64_t)(int32_t)arg2
);
188 target_ulong
helper_msacu(CPUMIPSState
*env
, target_ulong arg1
,
191 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) -
192 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
195 target_ulong
helper_msachiu(CPUMIPSState
*env
, target_ulong arg1
,
198 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) -
199 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
202 target_ulong
helper_mulhi(CPUMIPSState
*env
, target_ulong arg1
,
205 return set_HIT0_LO(env
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
208 target_ulong
helper_mulhiu(CPUMIPSState
*env
, target_ulong arg1
,
211 return set_HIT0_LO(env
, (uint64_t)(uint32_t)arg1
*
212 (uint64_t)(uint32_t)arg2
);
215 target_ulong
helper_mulshi(CPUMIPSState
*env
, target_ulong arg1
,
218 return set_HIT0_LO(env
, 0 - (int64_t)(int32_t)arg1
*
219 (int64_t)(int32_t)arg2
);
222 target_ulong
helper_mulshiu(CPUMIPSState
*env
, target_ulong arg1
,
225 return set_HIT0_LO(env
, 0 - (uint64_t)(uint32_t)arg1
*
226 (uint64_t)(uint32_t)arg2
);
229 static inline target_ulong
bitswap(target_ulong v
)
231 v
= ((v
>> 1) & (target_ulong
)0x5555555555555555ULL
) |
232 ((v
& (target_ulong
)0x5555555555555555ULL
) << 1);
233 v
= ((v
>> 2) & (target_ulong
)0x3333333333333333ULL
) |
234 ((v
& (target_ulong
)0x3333333333333333ULL
) << 2);
235 v
= ((v
>> 4) & (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) |
236 ((v
& (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) << 4);
241 target_ulong
helper_dbitswap(target_ulong rt
)
247 target_ulong
helper_bitswap(target_ulong rt
)
249 return (int32_t)bitswap(rt
);
252 target_ulong
helper_rotx(target_ulong rs
, uint32_t shift
, uint32_t shiftx
,
256 uint64_t tmp0
= ((uint64_t)rs
) << 32 | ((uint64_t)rs
& 0xffffffff);
257 uint64_t tmp1
= tmp0
;
258 for (i
= 0; i
<= 46; i
++) {
266 if (stripe
!= 0 && !(i
& 0x4)) {
270 if (tmp0
& (1LL << (i
+ 16))) {
278 uint64_t tmp2
= tmp1
;
279 for (i
= 0; i
<= 38; i
++) {
288 if (tmp1
& (1LL << (i
+ 8))) {
296 uint64_t tmp3
= tmp2
;
297 for (i
= 0; i
<= 34; i
++) {
305 if (tmp2
& (1LL << (i
+ 4))) {
313 uint64_t tmp4
= tmp3
;
314 for (i
= 0; i
<= 32; i
++) {
322 if (tmp3
& (1LL << (i
+ 2))) {
330 uint64_t tmp5
= tmp4
;
331 for (i
= 0; i
<= 31; i
++) {
335 if (tmp4
& (1LL << (i
+ 1))) {
343 return (int64_t)(int32_t)(uint32_t)tmp5
;
346 #ifndef CONFIG_USER_ONLY
348 static inline hwaddr
do_translate_address(CPUMIPSState
*env
,
349 target_ulong address
,
350 int rw
, uintptr_t retaddr
)
353 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
355 paddr
= cpu_mips_translate_address(env
, address
, rw
);
358 cpu_loop_exit_restore(cs
, retaddr
);
364 #define HELPER_LD_ATOMIC(name, insn, almask) \
365 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
367 if (arg & almask) { \
368 if (!(env->hflags & MIPS_HFLAG_DM)) { \
369 env->CP0_BadVAddr = arg; \
371 do_raise_exception(env, EXCP_AdEL, GETPC()); \
373 env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC()); \
375 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
378 HELPER_LD_ATOMIC(ll
, lw
, 0x3)
380 HELPER_LD_ATOMIC(lld
, ld
, 0x7)
382 #undef HELPER_LD_ATOMIC
385 #ifdef TARGET_WORDS_BIGENDIAN
386 #define GET_LMASK(v) ((v) & 3)
387 #define GET_OFFSET(addr, offset) (addr + (offset))
389 #define GET_LMASK(v) (((v) & 3) ^ 3)
390 #define GET_OFFSET(addr, offset) (addr - (offset))
393 void helper_swl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
396 do_sb(env
, arg2
, (uint8_t)(arg1
>> 24), mem_idx
, GETPC());
398 if (GET_LMASK(arg2
) <= 2) {
399 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16), mem_idx
,
403 if (GET_LMASK(arg2
) <= 1) {
404 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8), mem_idx
,
408 if (GET_LMASK(arg2
) == 0) {
409 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)arg1
, mem_idx
,
414 void helper_swr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
417 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
419 if (GET_LMASK(arg2
) >= 1) {
420 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
424 if (GET_LMASK(arg2
) >= 2) {
425 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
429 if (GET_LMASK(arg2
) == 3) {
430 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
435 #if defined(TARGET_MIPS64)
436 /* "half" load and stores. We must do the memory access inline,
437 or fault handling won't work. */
439 #ifdef TARGET_WORDS_BIGENDIAN
440 #define GET_LMASK64(v) ((v) & 7)
442 #define GET_LMASK64(v) (((v) & 7) ^ 7)
445 void helper_sdl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
448 do_sb(env
, arg2
, (uint8_t)(arg1
>> 56), mem_idx
, GETPC());
450 if (GET_LMASK64(arg2
) <= 6) {
451 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48), mem_idx
,
455 if (GET_LMASK64(arg2
) <= 5) {
456 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40), mem_idx
,
460 if (GET_LMASK64(arg2
) <= 4) {
461 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32), mem_idx
,
465 if (GET_LMASK64(arg2
) <= 3) {
466 do_sb(env
, GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24), mem_idx
,
470 if (GET_LMASK64(arg2
) <= 2) {
471 do_sb(env
, GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16), mem_idx
,
475 if (GET_LMASK64(arg2
) <= 1) {
476 do_sb(env
, GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8), mem_idx
,
480 if (GET_LMASK64(arg2
) <= 0) {
481 do_sb(env
, GET_OFFSET(arg2
, 7), (uint8_t)arg1
, mem_idx
,
486 void helper_sdr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
489 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
491 if (GET_LMASK64(arg2
) >= 1) {
492 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
496 if (GET_LMASK64(arg2
) >= 2) {
497 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
501 if (GET_LMASK64(arg2
) >= 3) {
502 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
506 if (GET_LMASK64(arg2
) >= 4) {
507 do_sb(env
, GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32), mem_idx
,
511 if (GET_LMASK64(arg2
) >= 5) {
512 do_sb(env
, GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40), mem_idx
,
516 if (GET_LMASK64(arg2
) >= 6) {
517 do_sb(env
, GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48), mem_idx
,
521 if (GET_LMASK64(arg2
) == 7) {
522 do_sb(env
, GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56), mem_idx
,
526 #endif /* TARGET_MIPS64 */
528 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
530 void helper_lwm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
533 target_ulong base_reglist
= reglist
& 0xf;
534 target_ulong do_r31
= reglist
& 0x10;
536 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
539 for (i
= 0; i
< base_reglist
; i
++) {
540 env
->active_tc
.gpr
[multiple_regs
[i
]] =
541 (target_long
)do_lw(env
, addr
, mem_idx
, GETPC());
547 env
->active_tc
.gpr
[31] = (target_long
)do_lw(env
, addr
, mem_idx
,
552 void helper_swm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
555 target_ulong base_reglist
= reglist
& 0xf;
556 target_ulong do_r31
= reglist
& 0x10;
558 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
561 for (i
= 0; i
< base_reglist
; i
++) {
562 do_sw(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
569 do_sw(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
573 #if defined(TARGET_MIPS64)
574 void helper_ldm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
577 target_ulong base_reglist
= reglist
& 0xf;
578 target_ulong do_r31
= reglist
& 0x10;
580 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
583 for (i
= 0; i
< base_reglist
; i
++) {
584 env
->active_tc
.gpr
[multiple_regs
[i
]] = do_ld(env
, addr
, mem_idx
,
591 env
->active_tc
.gpr
[31] = do_ld(env
, addr
, mem_idx
, GETPC());
595 void helper_sdm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
598 target_ulong base_reglist
= reglist
& 0xf;
599 target_ulong do_r31
= reglist
& 0x10;
601 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
604 for (i
= 0; i
< base_reglist
; i
++) {
605 do_sd(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
612 do_sd(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
617 #ifndef CONFIG_USER_ONLY
619 static bool mips_vpe_is_wfi(MIPSCPU
*c
)
621 CPUState
*cpu
= CPU(c
);
622 CPUMIPSState
*env
= &c
->env
;
624 /* If the VPE is halted but otherwise active, it means it's waiting for
626 return cpu
->halted
&& mips_vpe_active(env
);
629 static bool mips_vp_is_wfi(MIPSCPU
*c
)
631 CPUState
*cpu
= CPU(c
);
632 CPUMIPSState
*env
= &c
->env
;
634 return cpu
->halted
&& mips_vp_active(env
);
637 static inline void mips_vpe_wake(MIPSCPU
*c
)
639 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
640 because there might be other conditions that state that c should
642 qemu_mutex_lock_iothread();
643 cpu_interrupt(CPU(c
), CPU_INTERRUPT_WAKE
);
644 qemu_mutex_unlock_iothread();
647 static inline void mips_vpe_sleep(MIPSCPU
*cpu
)
649 CPUState
*cs
= CPU(cpu
);
651 /* The VPE was shut off, really go to bed.
652 Reset any old _WAKE requests. */
654 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
657 static inline void mips_tc_wake(MIPSCPU
*cpu
, int tc
)
659 CPUMIPSState
*c
= &cpu
->env
;
661 /* FIXME: TC reschedule. */
662 if (mips_vpe_active(c
) && !mips_vpe_is_wfi(cpu
)) {
667 static inline void mips_tc_sleep(MIPSCPU
*cpu
, int tc
)
669 CPUMIPSState
*c
= &cpu
->env
;
671 /* FIXME: TC reschedule. */
672 if (!mips_vpe_active(c
)) {
679 * @env: CPU from which mapping is performed.
680 * @tc: Should point to an int with the value of the global TC index.
682 * This function will transform @tc into a local index within the
683 * returned #CPUMIPSState.
685 /* FIXME: This code assumes that all VPEs have the same number of TCs,
686 which depends on runtime setup. Can probably be fixed by
687 walking the list of CPUMIPSStates. */
688 static CPUMIPSState
*mips_cpu_map_tc(CPUMIPSState
*env
, int *tc
)
696 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))) {
697 /* Not allowed to address other CPUs. */
698 *tc
= env
->current_tc
;
702 cs
= CPU(mips_env_get_cpu(env
));
703 vpe_idx
= tc_idx
/ cs
->nr_threads
;
704 *tc
= tc_idx
% cs
->nr_threads
;
705 other_cs
= qemu_get_cpu(vpe_idx
);
706 if (other_cs
== NULL
) {
709 cpu
= MIPS_CPU(other_cs
);
713 /* The per VPE CP0_Status register shares some fields with the per TC
714 CP0_TCStatus registers. These fields are wired to the same registers,
715 so changes to either of them should be reflected on both registers.
717 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
719 These helper call synchronizes the regs for a given cpu. */
721 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
722 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
725 /* Called for updates to CP0_TCStatus. */
726 static void sync_c0_tcstatus(CPUMIPSState
*cpu
, int tc
,
730 uint32_t tcu
, tmx
, tasid
, tksu
;
731 uint32_t mask
= ((1U << CP0St_CU3
)
738 tcu
= (v
>> CP0TCSt_TCU0
) & 0xf;
739 tmx
= (v
>> CP0TCSt_TMX
) & 0x1;
740 tasid
= v
& cpu
->CP0_EntryHi_ASID_mask
;
741 tksu
= (v
>> CP0TCSt_TKSU
) & 0x3;
743 status
= tcu
<< CP0St_CU0
;
744 status
|= tmx
<< CP0St_MX
;
745 status
|= tksu
<< CP0St_KSU
;
747 cpu
->CP0_Status
&= ~mask
;
748 cpu
->CP0_Status
|= status
;
750 /* Sync the TASID with EntryHi. */
751 cpu
->CP0_EntryHi
&= ~cpu
->CP0_EntryHi_ASID_mask
;
752 cpu
->CP0_EntryHi
|= tasid
;
757 /* Called for updates to CP0_EntryHi. */
758 static void sync_c0_entryhi(CPUMIPSState
*cpu
, int tc
)
761 uint32_t asid
, v
= cpu
->CP0_EntryHi
;
763 asid
= v
& cpu
->CP0_EntryHi_ASID_mask
;
765 if (tc
== cpu
->current_tc
) {
766 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
768 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
771 *tcst
&= ~cpu
->CP0_EntryHi_ASID_mask
;
776 target_ulong
helper_mfc0_mvpcontrol(CPUMIPSState
*env
)
778 return env
->mvp
->CP0_MVPControl
;
781 target_ulong
helper_mfc0_mvpconf0(CPUMIPSState
*env
)
783 return env
->mvp
->CP0_MVPConf0
;
786 target_ulong
helper_mfc0_mvpconf1(CPUMIPSState
*env
)
788 return env
->mvp
->CP0_MVPConf1
;
791 target_ulong
helper_mfc0_random(CPUMIPSState
*env
)
793 return (int32_t)cpu_mips_get_random(env
);
796 target_ulong
helper_mfc0_tcstatus(CPUMIPSState
*env
)
798 return env
->active_tc
.CP0_TCStatus
;
801 target_ulong
helper_mftc0_tcstatus(CPUMIPSState
*env
)
803 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
804 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
806 if (other_tc
== other
->current_tc
)
807 return other
->active_tc
.CP0_TCStatus
;
809 return other
->tcs
[other_tc
].CP0_TCStatus
;
812 target_ulong
helper_mfc0_tcbind(CPUMIPSState
*env
)
814 return env
->active_tc
.CP0_TCBind
;
817 target_ulong
helper_mftc0_tcbind(CPUMIPSState
*env
)
819 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
820 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
822 if (other_tc
== other
->current_tc
)
823 return other
->active_tc
.CP0_TCBind
;
825 return other
->tcs
[other_tc
].CP0_TCBind
;
828 target_ulong
helper_mfc0_tcrestart(CPUMIPSState
*env
)
830 return env
->active_tc
.PC
;
833 target_ulong
helper_mftc0_tcrestart(CPUMIPSState
*env
)
835 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
836 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
838 if (other_tc
== other
->current_tc
)
839 return other
->active_tc
.PC
;
841 return other
->tcs
[other_tc
].PC
;
844 target_ulong
helper_mfc0_tchalt(CPUMIPSState
*env
)
846 return env
->active_tc
.CP0_TCHalt
;
849 target_ulong
helper_mftc0_tchalt(CPUMIPSState
*env
)
851 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
852 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
854 if (other_tc
== other
->current_tc
)
855 return other
->active_tc
.CP0_TCHalt
;
857 return other
->tcs
[other_tc
].CP0_TCHalt
;
860 target_ulong
helper_mfc0_tccontext(CPUMIPSState
*env
)
862 return env
->active_tc
.CP0_TCContext
;
865 target_ulong
helper_mftc0_tccontext(CPUMIPSState
*env
)
867 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
868 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
870 if (other_tc
== other
->current_tc
)
871 return other
->active_tc
.CP0_TCContext
;
873 return other
->tcs
[other_tc
].CP0_TCContext
;
876 target_ulong
helper_mfc0_tcschedule(CPUMIPSState
*env
)
878 return env
->active_tc
.CP0_TCSchedule
;
881 target_ulong
helper_mftc0_tcschedule(CPUMIPSState
*env
)
883 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
884 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
886 if (other_tc
== other
->current_tc
)
887 return other
->active_tc
.CP0_TCSchedule
;
889 return other
->tcs
[other_tc
].CP0_TCSchedule
;
892 target_ulong
helper_mfc0_tcschefback(CPUMIPSState
*env
)
894 return env
->active_tc
.CP0_TCScheFBack
;
897 target_ulong
helper_mftc0_tcschefback(CPUMIPSState
*env
)
899 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
900 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
902 if (other_tc
== other
->current_tc
)
903 return other
->active_tc
.CP0_TCScheFBack
;
905 return other
->tcs
[other_tc
].CP0_TCScheFBack
;
908 target_ulong
helper_mfc0_count(CPUMIPSState
*env
)
910 return (int32_t)cpu_mips_get_count(env
);
913 target_ulong
helper_mfc0_saar(CPUMIPSState
*env
)
915 if ((env
->CP0_SAARI
& 0x3f) < 2) {
916 return (int32_t) env
->CP0_SAAR
[env
->CP0_SAARI
& 0x3f];
921 target_ulong
helper_mfhc0_saar(CPUMIPSState
*env
)
923 if ((env
->CP0_SAARI
& 0x3f) < 2) {
924 return env
->CP0_SAAR
[env
->CP0_SAARI
& 0x3f] >> 32;
929 target_ulong
helper_mftc0_entryhi(CPUMIPSState
*env
)
931 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
932 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
934 return other
->CP0_EntryHi
;
937 target_ulong
helper_mftc0_cause(CPUMIPSState
*env
)
939 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
941 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
943 if (other_tc
== other
->current_tc
) {
944 tccause
= other
->CP0_Cause
;
946 tccause
= other
->CP0_Cause
;
952 target_ulong
helper_mftc0_status(CPUMIPSState
*env
)
954 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
955 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
957 return other
->CP0_Status
;
960 target_ulong
helper_mfc0_lladdr(CPUMIPSState
*env
)
962 return (int32_t)(env
->CP0_LLAddr
>> env
->CP0_LLAddr_shift
);
965 target_ulong
helper_mfc0_maar(CPUMIPSState
*env
)
967 return (int32_t) env
->CP0_MAAR
[env
->CP0_MAARI
];
970 target_ulong
helper_mfhc0_maar(CPUMIPSState
*env
)
972 return env
->CP0_MAAR
[env
->CP0_MAARI
] >> 32;
975 target_ulong
helper_mfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
977 return (int32_t)env
->CP0_WatchLo
[sel
];
980 target_ulong
helper_mfc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
982 return env
->CP0_WatchHi
[sel
];
985 target_ulong
helper_mfc0_debug(CPUMIPSState
*env
)
987 target_ulong t0
= env
->CP0_Debug
;
988 if (env
->hflags
& MIPS_HFLAG_DM
)
994 target_ulong
helper_mftc0_debug(CPUMIPSState
*env
)
996 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
998 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1000 if (other_tc
== other
->current_tc
)
1001 tcstatus
= other
->active_tc
.CP0_Debug_tcstatus
;
1003 tcstatus
= other
->tcs
[other_tc
].CP0_Debug_tcstatus
;
1005 /* XXX: Might be wrong, check with EJTAG spec. */
1006 return (other
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1007 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1010 #if defined(TARGET_MIPS64)
1011 target_ulong
helper_dmfc0_tcrestart(CPUMIPSState
*env
)
1013 return env
->active_tc
.PC
;
1016 target_ulong
helper_dmfc0_tchalt(CPUMIPSState
*env
)
1018 return env
->active_tc
.CP0_TCHalt
;
1021 target_ulong
helper_dmfc0_tccontext(CPUMIPSState
*env
)
1023 return env
->active_tc
.CP0_TCContext
;
1026 target_ulong
helper_dmfc0_tcschedule(CPUMIPSState
*env
)
1028 return env
->active_tc
.CP0_TCSchedule
;
1031 target_ulong
helper_dmfc0_tcschefback(CPUMIPSState
*env
)
1033 return env
->active_tc
.CP0_TCScheFBack
;
1036 target_ulong
helper_dmfc0_lladdr(CPUMIPSState
*env
)
1038 return env
->CP0_LLAddr
>> env
->CP0_LLAddr_shift
;
1041 target_ulong
helper_dmfc0_maar(CPUMIPSState
*env
)
1043 return env
->CP0_MAAR
[env
->CP0_MAARI
];
1046 target_ulong
helper_dmfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
1048 return env
->CP0_WatchLo
[sel
];
1051 target_ulong
helper_dmfc0_saar(CPUMIPSState
*env
)
1053 if ((env
->CP0_SAARI
& 0x3f) < 2) {
1054 return env
->CP0_SAAR
[env
->CP0_SAARI
& 0x3f];
1058 #endif /* TARGET_MIPS64 */
1060 void helper_mtc0_index(CPUMIPSState
*env
, target_ulong arg1
)
1062 uint32_t index_p
= env
->CP0_Index
& 0x80000000;
1063 uint32_t tlb_index
= arg1
& 0x7fffffff;
1064 if (tlb_index
< env
->tlb
->nb_tlb
) {
1065 if (env
->insn_flags
& ISA_MIPS32R6
) {
1066 index_p
|= arg1
& 0x80000000;
1068 env
->CP0_Index
= index_p
| tlb_index
;
1072 void helper_mtc0_mvpcontrol(CPUMIPSState
*env
, target_ulong arg1
)
1077 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
1078 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
1079 (1 << CP0MVPCo_EVP
);
1080 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1081 mask
|= (1 << CP0MVPCo_STLB
);
1082 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
1084 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1086 env
->mvp
->CP0_MVPControl
= newval
;
1089 void helper_mtc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1094 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1095 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1096 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1098 /* Yield scheduler intercept not implemented. */
1099 /* Gating storage scheduler intercept not implemented. */
1101 // TODO: Enable/disable TCs.
1103 env
->CP0_VPEControl
= newval
;
1106 void helper_mttc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1108 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1109 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1113 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1114 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1115 newval
= (other
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1117 /* TODO: Enable/disable TCs. */
1119 other
->CP0_VPEControl
= newval
;
1122 target_ulong
helper_mftc0_vpecontrol(CPUMIPSState
*env
)
1124 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1125 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1126 /* FIXME: Mask away return zero on read bits. */
1127 return other
->CP0_VPEControl
;
1130 target_ulong
helper_mftc0_vpeconf0(CPUMIPSState
*env
)
1132 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1133 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1135 return other
->CP0_VPEConf0
;
1138 void helper_mtc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1143 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
1144 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
1145 mask
|= (0xff << CP0VPEC0_XTC
);
1146 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1148 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1150 // TODO: TC exclusive handling due to ERL/EXL.
1152 env
->CP0_VPEConf0
= newval
;
1155 void helper_mttc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1157 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1158 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1162 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1163 newval
= (other
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1165 /* TODO: TC exclusive handling due to ERL/EXL. */
1166 other
->CP0_VPEConf0
= newval
;
1169 void helper_mtc0_vpeconf1(CPUMIPSState
*env
, target_ulong arg1
)
1174 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1175 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
1176 (0xff << CP0VPEC1_NCP1
);
1177 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
1179 /* UDI not implemented. */
1180 /* CP2 not implemented. */
1182 // TODO: Handle FPU (CP1) binding.
1184 env
->CP0_VPEConf1
= newval
;
1187 void helper_mtc0_yqmask(CPUMIPSState
*env
, target_ulong arg1
)
1189 /* Yield qualifier inputs not implemented. */
1190 env
->CP0_YQMask
= 0x00000000;
1193 void helper_mtc0_vpeopt(CPUMIPSState
*env
, target_ulong arg1
)
1195 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
1198 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1200 void helper_mtc0_entrylo0(CPUMIPSState
*env
, target_ulong arg1
)
1202 /* 1k pages not implemented */
1203 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1204 env
->CP0_EntryLo0
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1205 | (rxi
<< (CP0EnLo_XI
- 30));
1208 #if defined(TARGET_MIPS64)
1209 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1211 void helper_dmtc0_entrylo0(CPUMIPSState
*env
, uint64_t arg1
)
1213 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1214 env
->CP0_EntryLo0
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1218 void helper_mtc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1220 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
1223 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
1225 env
->active_tc
.CP0_TCStatus
= newval
;
1226 sync_c0_tcstatus(env
, env
->current_tc
, newval
);
1229 void helper_mttc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1231 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1232 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1234 if (other_tc
== other
->current_tc
)
1235 other
->active_tc
.CP0_TCStatus
= arg1
;
1237 other
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
1238 sync_c0_tcstatus(other
, other_tc
, arg1
);
1241 void helper_mtc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1243 uint32_t mask
= (1 << CP0TCBd_TBE
);
1246 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1247 mask
|= (1 << CP0TCBd_CurVPE
);
1248 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1249 env
->active_tc
.CP0_TCBind
= newval
;
1252 void helper_mttc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1254 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1255 uint32_t mask
= (1 << CP0TCBd_TBE
);
1257 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1259 if (other
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1260 mask
|= (1 << CP0TCBd_CurVPE
);
1261 if (other_tc
== other
->current_tc
) {
1262 newval
= (other
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1263 other
->active_tc
.CP0_TCBind
= newval
;
1265 newval
= (other
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
1266 other
->tcs
[other_tc
].CP0_TCBind
= newval
;
1270 void helper_mtc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1272 env
->active_tc
.PC
= arg1
;
1273 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1274 env
->CP0_LLAddr
= 0;
1276 /* MIPS16 not implemented. */
1279 void helper_mttc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1281 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1282 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1284 if (other_tc
== other
->current_tc
) {
1285 other
->active_tc
.PC
= arg1
;
1286 other
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1287 other
->CP0_LLAddr
= 0;
1289 /* MIPS16 not implemented. */
1291 other
->tcs
[other_tc
].PC
= arg1
;
1292 other
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1293 other
->CP0_LLAddr
= 0;
1295 /* MIPS16 not implemented. */
1299 void helper_mtc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1301 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1303 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
1305 // TODO: Halt TC / Restart (if allocated+active) TC.
1306 if (env
->active_tc
.CP0_TCHalt
& 1) {
1307 mips_tc_sleep(cpu
, env
->current_tc
);
1309 mips_tc_wake(cpu
, env
->current_tc
);
1313 void helper_mttc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1315 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1316 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1317 MIPSCPU
*other_cpu
= mips_env_get_cpu(other
);
1319 // TODO: Halt TC / Restart (if allocated+active) TC.
1321 if (other_tc
== other
->current_tc
)
1322 other
->active_tc
.CP0_TCHalt
= arg1
;
1324 other
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
1327 mips_tc_sleep(other_cpu
, other_tc
);
1329 mips_tc_wake(other_cpu
, other_tc
);
1333 void helper_mtc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1335 env
->active_tc
.CP0_TCContext
= arg1
;
1338 void helper_mttc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1340 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1341 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1343 if (other_tc
== other
->current_tc
)
1344 other
->active_tc
.CP0_TCContext
= arg1
;
1346 other
->tcs
[other_tc
].CP0_TCContext
= arg1
;
1349 void helper_mtc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1351 env
->active_tc
.CP0_TCSchedule
= arg1
;
1354 void helper_mttc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1356 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1357 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1359 if (other_tc
== other
->current_tc
)
1360 other
->active_tc
.CP0_TCSchedule
= arg1
;
1362 other
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
1365 void helper_mtc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1367 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1370 void helper_mttc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1372 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1373 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1375 if (other_tc
== other
->current_tc
)
1376 other
->active_tc
.CP0_TCScheFBack
= arg1
;
1378 other
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
1381 void helper_mtc0_entrylo1(CPUMIPSState
*env
, target_ulong arg1
)
1383 /* 1k pages not implemented */
1384 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1385 env
->CP0_EntryLo1
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1386 | (rxi
<< (CP0EnLo_XI
- 30));
1389 #if defined(TARGET_MIPS64)
1390 void helper_dmtc0_entrylo1(CPUMIPSState
*env
, uint64_t arg1
)
1392 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1393 env
->CP0_EntryLo1
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1397 void helper_mtc0_context(CPUMIPSState
*env
, target_ulong arg1
)
1399 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
1402 void update_pagemask(CPUMIPSState
*env
, target_ulong arg1
, int32_t *pagemask
)
1404 uint64_t mask
= arg1
>> (TARGET_PAGE_BITS
+ 1);
1405 if (!(env
->insn_flags
& ISA_MIPS32R6
) || (arg1
== ~0) ||
1406 (mask
== 0x0000 || mask
== 0x0003 || mask
== 0x000F ||
1407 mask
== 0x003F || mask
== 0x00FF || mask
== 0x03FF ||
1408 mask
== 0x0FFF || mask
== 0x3FFF || mask
== 0xFFFF)) {
1409 env
->CP0_PageMask
= arg1
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1413 void helper_mtc0_pagemask(CPUMIPSState
*env
, target_ulong arg1
)
1415 update_pagemask(env
, arg1
, &env
->CP0_PageMask
);
1418 void helper_mtc0_pagegrain(CPUMIPSState
*env
, target_ulong arg1
)
1420 /* SmartMIPS not implemented */
1421 /* 1k pages not implemented */
1422 env
->CP0_PageGrain
= (arg1
& env
->CP0_PageGrain_rw_bitmask
) |
1423 (env
->CP0_PageGrain
& ~env
->CP0_PageGrain_rw_bitmask
);
1424 compute_hflags(env
);
1425 restore_pamask(env
);
1428 void helper_mtc0_segctl0(CPUMIPSState
*env
, target_ulong arg1
)
1430 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1432 env
->CP0_SegCtl0
= arg1
& CP0SC0_MASK
;
1436 void helper_mtc0_segctl1(CPUMIPSState
*env
, target_ulong arg1
)
1438 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1440 env
->CP0_SegCtl1
= arg1
& CP0SC1_MASK
;
1444 void helper_mtc0_segctl2(CPUMIPSState
*env
, target_ulong arg1
)
1446 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1448 env
->CP0_SegCtl2
= arg1
& CP0SC2_MASK
;
1452 void helper_mtc0_pwfield(CPUMIPSState
*env
, target_ulong arg1
)
1454 #if defined(TARGET_MIPS64)
1455 uint64_t mask
= 0x3F3FFFFFFFULL
;
1456 uint32_t old_ptei
= (env
->CP0_PWField
>> CP0PF_PTEI
) & 0x3FULL
;
1457 uint32_t new_ptei
= (arg1
>> CP0PF_PTEI
) & 0x3FULL
;
1459 if ((env
->insn_flags
& ISA_MIPS32R6
)) {
1460 if (((arg1
>> CP0PF_BDI
) & 0x3FULL
) < 12) {
1461 mask
&= ~(0x3FULL
<< CP0PF_BDI
);
1463 if (((arg1
>> CP0PF_GDI
) & 0x3FULL
) < 12) {
1464 mask
&= ~(0x3FULL
<< CP0PF_GDI
);
1466 if (((arg1
>> CP0PF_UDI
) & 0x3FULL
) < 12) {
1467 mask
&= ~(0x3FULL
<< CP0PF_UDI
);
1469 if (((arg1
>> CP0PF_MDI
) & 0x3FULL
) < 12) {
1470 mask
&= ~(0x3FULL
<< CP0PF_MDI
);
1472 if (((arg1
>> CP0PF_PTI
) & 0x3FULL
) < 12) {
1473 mask
&= ~(0x3FULL
<< CP0PF_PTI
);
1476 env
->CP0_PWField
= arg1
& mask
;
1478 if ((new_ptei
>= 32) ||
1479 ((env
->insn_flags
& ISA_MIPS32R6
) &&
1480 (new_ptei
== 0 || new_ptei
== 1))) {
1481 env
->CP0_PWField
= (env
->CP0_PWField
& ~0x3FULL
) |
1482 (old_ptei
<< CP0PF_PTEI
);
1485 uint32_t mask
= 0x3FFFFFFF;
1486 uint32_t old_ptew
= (env
->CP0_PWField
>> CP0PF_PTEW
) & 0x3F;
1487 uint32_t new_ptew
= (arg1
>> CP0PF_PTEW
) & 0x3F;
1489 if ((env
->insn_flags
& ISA_MIPS32R6
)) {
1490 if (((arg1
>> CP0PF_GDW
) & 0x3F) < 12) {
1491 mask
&= ~(0x3F << CP0PF_GDW
);
1493 if (((arg1
>> CP0PF_UDW
) & 0x3F) < 12) {
1494 mask
&= ~(0x3F << CP0PF_UDW
);
1496 if (((arg1
>> CP0PF_MDW
) & 0x3F) < 12) {
1497 mask
&= ~(0x3F << CP0PF_MDW
);
1499 if (((arg1
>> CP0PF_PTW
) & 0x3F) < 12) {
1500 mask
&= ~(0x3F << CP0PF_PTW
);
1503 env
->CP0_PWField
= arg1
& mask
;
1505 if ((new_ptew
>= 32) ||
1506 ((env
->insn_flags
& ISA_MIPS32R6
) &&
1507 (new_ptew
== 0 || new_ptew
== 1))) {
1508 env
->CP0_PWField
= (env
->CP0_PWField
& ~0x3F) |
1509 (old_ptew
<< CP0PF_PTEW
);
1514 void helper_mtc0_pwsize(CPUMIPSState
*env
, target_ulong arg1
)
1516 #if defined(TARGET_MIPS64)
1517 env
->CP0_PWSize
= arg1
& 0x3F7FFFFFFFULL
;
1519 env
->CP0_PWSize
= arg1
& 0x3FFFFFFF;
1523 void helper_mtc0_wired(CPUMIPSState
*env
, target_ulong arg1
)
1525 if (env
->insn_flags
& ISA_MIPS32R6
) {
1526 if (arg1
< env
->tlb
->nb_tlb
) {
1527 env
->CP0_Wired
= arg1
;
1530 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1534 void helper_mtc0_pwctl(CPUMIPSState
*env
, target_ulong arg1
)
1536 #if defined(TARGET_MIPS64)
1537 /* PWEn = 0. Hardware page table walking is not implemented. */
1538 env
->CP0_PWCtl
= (env
->CP0_PWCtl
& 0x000000C0) | (arg1
& 0x5C00003F);
1540 env
->CP0_PWCtl
= (arg1
& 0x800000FF);
1544 void helper_mtc0_srsconf0(CPUMIPSState
*env
, target_ulong arg1
)
1546 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1549 void helper_mtc0_srsconf1(CPUMIPSState
*env
, target_ulong arg1
)
1551 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1554 void helper_mtc0_srsconf2(CPUMIPSState
*env
, target_ulong arg1
)
1556 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1559 void helper_mtc0_srsconf3(CPUMIPSState
*env
, target_ulong arg1
)
1561 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1564 void helper_mtc0_srsconf4(CPUMIPSState
*env
, target_ulong arg1
)
1566 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1569 void helper_mtc0_hwrena(CPUMIPSState
*env
, target_ulong arg1
)
1571 uint32_t mask
= 0x0000000F;
1573 if ((env
->CP0_Config1
& (1 << CP0C1_PC
)) &&
1574 (env
->insn_flags
& ISA_MIPS32R6
)) {
1577 if (env
->insn_flags
& ISA_MIPS32R6
) {
1580 if (env
->CP0_Config3
& (1 << CP0C3_ULRI
)) {
1583 if (arg1
& (1 << 29)) {
1584 env
->hflags
|= MIPS_HFLAG_HWRENA_ULR
;
1586 env
->hflags
&= ~MIPS_HFLAG_HWRENA_ULR
;
1590 env
->CP0_HWREna
= arg1
& mask
;
1593 void helper_mtc0_count(CPUMIPSState
*env
, target_ulong arg1
)
1595 cpu_mips_store_count(env
, arg1
);
1598 void helper_mtc0_saari(CPUMIPSState
*env
, target_ulong arg1
)
1600 uint32_t target
= arg1
& 0x3f;
1602 env
->CP0_SAARI
= target
;
1606 void helper_mtc0_saar(CPUMIPSState
*env
, target_ulong arg1
)
1608 uint32_t target
= env
->CP0_SAARI
& 0x3f;
1610 env
->CP0_SAAR
[target
] = arg1
& 0x00000ffffffff03fULL
;
1614 itc_reconfigure(env
->itu
);
1621 void helper_mthc0_saar(CPUMIPSState
*env
, target_ulong arg1
)
1623 uint32_t target
= env
->CP0_SAARI
& 0x3f;
1625 env
->CP0_SAAR
[target
] =
1626 (((uint64_t) arg1
<< 32) & 0x00000fff00000000ULL
) |
1627 (env
->CP0_SAAR
[target
] & 0x00000000ffffffffULL
);
1631 itc_reconfigure(env
->itu
);
1638 void helper_mtc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1640 target_ulong old
, val
, mask
;
1641 mask
= (TARGET_PAGE_MASK
<< 1) | env
->CP0_EntryHi_ASID_mask
;
1642 if (((env
->CP0_Config4
>> CP0C4_IE
) & 0x3) >= 2) {
1643 mask
|= 1 << CP0EnHi_EHINV
;
1646 /* 1k pages not implemented */
1647 #if defined(TARGET_MIPS64)
1648 if (env
->insn_flags
& ISA_MIPS32R6
) {
1649 int entryhi_r
= extract64(arg1
, 62, 2);
1650 int config0_at
= extract32(env
->CP0_Config0
, 13, 2);
1651 bool no_supervisor
= (env
->CP0_Status_rw_bitmask
& 0x8) == 0;
1652 if ((entryhi_r
== 2) ||
1653 (entryhi_r
== 1 && (no_supervisor
|| config0_at
== 1))) {
1654 /* skip EntryHi.R field if new value is reserved */
1655 mask
&= ~(0x3ull
<< 62);
1658 mask
&= env
->SEGMask
;
1660 old
= env
->CP0_EntryHi
;
1661 val
= (arg1
& mask
) | (old
& ~mask
);
1662 env
->CP0_EntryHi
= val
;
1663 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1664 sync_c0_entryhi(env
, env
->current_tc
);
1666 /* If the ASID changes, flush qemu's TLB. */
1667 if ((old
& env
->CP0_EntryHi_ASID_mask
) !=
1668 (val
& env
->CP0_EntryHi_ASID_mask
)) {
1669 tlb_flush(CPU(mips_env_get_cpu(env
)));
1673 void helper_mttc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1675 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1676 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1678 other
->CP0_EntryHi
= arg1
;
1679 sync_c0_entryhi(other
, other_tc
);
1682 void helper_mtc0_compare(CPUMIPSState
*env
, target_ulong arg1
)
1684 cpu_mips_store_compare(env
, arg1
);
1687 void helper_mtc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1689 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1692 old
= env
->CP0_Status
;
1693 cpu_mips_store_status(env
, arg1
);
1694 val
= env
->CP0_Status
;
1696 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1697 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1698 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1699 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1701 switch (cpu_mmu_index(env
, false)) {
1703 qemu_log(", ERL\n");
1705 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1706 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1707 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1709 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
1715 void helper_mttc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1717 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1718 uint32_t mask
= env
->CP0_Status_rw_bitmask
& ~0xf1000018;
1719 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1721 other
->CP0_Status
= (other
->CP0_Status
& ~mask
) | (arg1
& mask
);
1722 sync_c0_status(env
, other
, other_tc
);
1725 void helper_mtc0_intctl(CPUMIPSState
*env
, target_ulong arg1
)
1727 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000003e0) | (arg1
& 0x000003e0);
1730 void helper_mtc0_srsctl(CPUMIPSState
*env
, target_ulong arg1
)
1732 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1733 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1736 void helper_mtc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1738 cpu_mips_store_cause(env
, arg1
);
1741 void helper_mttc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1743 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1744 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1746 cpu_mips_store_cause(other
, arg1
);
1749 target_ulong
helper_mftc0_epc(CPUMIPSState
*env
)
1751 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1752 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1754 return other
->CP0_EPC
;
1757 target_ulong
helper_mftc0_ebase(CPUMIPSState
*env
)
1759 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1760 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1762 return other
->CP0_EBase
;
1765 void helper_mtc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1767 target_ulong mask
= 0x3FFFF000 | env
->CP0_EBaseWG_rw_bitmask
;
1768 if (arg1
& env
->CP0_EBaseWG_rw_bitmask
) {
1769 mask
|= ~0x3FFFFFFF;
1771 env
->CP0_EBase
= (env
->CP0_EBase
& ~mask
) | (arg1
& mask
);
1774 void helper_mttc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1776 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1777 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1778 target_ulong mask
= 0x3FFFF000 | env
->CP0_EBaseWG_rw_bitmask
;
1779 if (arg1
& env
->CP0_EBaseWG_rw_bitmask
) {
1780 mask
|= ~0x3FFFFFFF;
1782 other
->CP0_EBase
= (other
->CP0_EBase
& ~mask
) | (arg1
& mask
);
1785 target_ulong
helper_mftc0_configx(CPUMIPSState
*env
, target_ulong idx
)
1787 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1788 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1791 case 0: return other
->CP0_Config0
;
1792 case 1: return other
->CP0_Config1
;
1793 case 2: return other
->CP0_Config2
;
1794 case 3: return other
->CP0_Config3
;
1795 /* 4 and 5 are reserved. */
1796 case 6: return other
->CP0_Config6
;
1797 case 7: return other
->CP0_Config7
;
1804 void helper_mtc0_config0(CPUMIPSState
*env
, target_ulong arg1
)
1806 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1809 void helper_mtc0_config2(CPUMIPSState
*env
, target_ulong arg1
)
1811 /* tertiary/secondary caches not implemented */
1812 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1815 void helper_mtc0_config3(CPUMIPSState
*env
, target_ulong arg1
)
1817 if (env
->insn_flags
& ASE_MICROMIPS
) {
1818 env
->CP0_Config3
= (env
->CP0_Config3
& ~(1 << CP0C3_ISA_ON_EXC
)) |
1819 (arg1
& (1 << CP0C3_ISA_ON_EXC
));
1823 void helper_mtc0_config4(CPUMIPSState
*env
, target_ulong arg1
)
1825 env
->CP0_Config4
= (env
->CP0_Config4
& (~env
->CP0_Config4_rw_bitmask
)) |
1826 (arg1
& env
->CP0_Config4_rw_bitmask
);
1829 void helper_mtc0_config5(CPUMIPSState
*env
, target_ulong arg1
)
1831 env
->CP0_Config5
= (env
->CP0_Config5
& (~env
->CP0_Config5_rw_bitmask
)) |
1832 (arg1
& env
->CP0_Config5_rw_bitmask
);
1833 compute_hflags(env
);
1836 void helper_mtc0_lladdr(CPUMIPSState
*env
, target_ulong arg1
)
1838 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1839 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1840 env
->CP0_LLAddr
= (env
->CP0_LLAddr
& ~mask
) | (arg1
& mask
);
1843 #define MTC0_MAAR_MASK(env) \
1844 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1846 void helper_mtc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1848 env
->CP0_MAAR
[env
->CP0_MAARI
] = arg1
& MTC0_MAAR_MASK(env
);
1851 void helper_mthc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1853 env
->CP0_MAAR
[env
->CP0_MAARI
] =
1854 (((uint64_t) arg1
<< 32) & MTC0_MAAR_MASK(env
)) |
1855 (env
->CP0_MAAR
[env
->CP0_MAARI
] & 0x00000000ffffffffULL
);
1858 void helper_mtc0_maari(CPUMIPSState
*env
, target_ulong arg1
)
1860 int index
= arg1
& 0x3f;
1861 if (index
== 0x3f) {
1862 /* Software may write all ones to INDEX to determine the
1863 maximum value supported. */
1864 env
->CP0_MAARI
= MIPS_MAAR_MAX
- 1;
1865 } else if (index
< MIPS_MAAR_MAX
) {
1866 env
->CP0_MAARI
= index
;
1868 /* Other than the all ones, if the
1869 value written is not supported, then INDEX is unchanged
1870 from its previous value. */
1873 void helper_mtc0_watchlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1875 /* Watch exceptions for instructions, data loads, data stores
1877 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1880 void helper_mtc0_watchhi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1882 int mask
= 0x40000FF8 | (env
->CP0_EntryHi_ASID_mask
<< CP0WH_ASID
);
1883 env
->CP0_WatchHi
[sel
] = arg1
& mask
;
1884 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1887 void helper_mtc0_xcontext(CPUMIPSState
*env
, target_ulong arg1
)
1889 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1890 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1893 void helper_mtc0_framemask(CPUMIPSState
*env
, target_ulong arg1
)
1895 env
->CP0_Framemask
= arg1
; /* XXX */
1898 void helper_mtc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1900 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1901 if (arg1
& (1 << CP0DB_DM
))
1902 env
->hflags
|= MIPS_HFLAG_DM
;
1904 env
->hflags
&= ~MIPS_HFLAG_DM
;
1907 void helper_mttc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1909 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1910 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1911 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1913 /* XXX: Might be wrong, check with EJTAG spec. */
1914 if (other_tc
== other
->current_tc
)
1915 other
->active_tc
.CP0_Debug_tcstatus
= val
;
1917 other
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1918 other
->CP0_Debug
= (other
->CP0_Debug
&
1919 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1920 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1923 void helper_mtc0_performance0(CPUMIPSState
*env
, target_ulong arg1
)
1925 env
->CP0_Performance0
= arg1
& 0x000007ff;
1928 void helper_mtc0_errctl(CPUMIPSState
*env
, target_ulong arg1
)
1930 int32_t wst
= arg1
& (1 << CP0EC_WST
);
1931 int32_t spr
= arg1
& (1 << CP0EC_SPR
);
1932 int32_t itc
= env
->itc_tag
? (arg1
& (1 << CP0EC_ITC
)) : 0;
1934 env
->CP0_ErrCtl
= wst
| spr
| itc
;
1936 if (itc
&& !wst
&& !spr
) {
1937 env
->hflags
|= MIPS_HFLAG_ITC_CACHE
;
1939 env
->hflags
&= ~MIPS_HFLAG_ITC_CACHE
;
1943 void helper_mtc0_taglo(CPUMIPSState
*env
, target_ulong arg1
)
1945 if (env
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
1946 /* If CACHE instruction is configured for ITC tags then make all
1947 CP0.TagLo bits writable. The actual write to ITC Configuration
1948 Tag will take care of the read-only bits. */
1949 env
->CP0_TagLo
= arg1
;
1951 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1955 void helper_mtc0_datalo(CPUMIPSState
*env
, target_ulong arg1
)
1957 env
->CP0_DataLo
= arg1
; /* XXX */
1960 void helper_mtc0_taghi(CPUMIPSState
*env
, target_ulong arg1
)
1962 env
->CP0_TagHi
= arg1
; /* XXX */
1965 void helper_mtc0_datahi(CPUMIPSState
*env
, target_ulong arg1
)
1967 env
->CP0_DataHi
= arg1
; /* XXX */
1970 /* MIPS MT functions */
1971 target_ulong
helper_mftgpr(CPUMIPSState
*env
, uint32_t sel
)
1973 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1974 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1976 if (other_tc
== other
->current_tc
)
1977 return other
->active_tc
.gpr
[sel
];
1979 return other
->tcs
[other_tc
].gpr
[sel
];
1982 target_ulong
helper_mftlo(CPUMIPSState
*env
, uint32_t sel
)
1984 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1985 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1987 if (other_tc
== other
->current_tc
)
1988 return other
->active_tc
.LO
[sel
];
1990 return other
->tcs
[other_tc
].LO
[sel
];
1993 target_ulong
helper_mfthi(CPUMIPSState
*env
, uint32_t sel
)
1995 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1996 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1998 if (other_tc
== other
->current_tc
)
1999 return other
->active_tc
.HI
[sel
];
2001 return other
->tcs
[other_tc
].HI
[sel
];
2004 target_ulong
helper_mftacx(CPUMIPSState
*env
, uint32_t sel
)
2006 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2007 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2009 if (other_tc
== other
->current_tc
)
2010 return other
->active_tc
.ACX
[sel
];
2012 return other
->tcs
[other_tc
].ACX
[sel
];
2015 target_ulong
helper_mftdsp(CPUMIPSState
*env
)
2017 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2018 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2020 if (other_tc
== other
->current_tc
)
2021 return other
->active_tc
.DSPControl
;
2023 return other
->tcs
[other_tc
].DSPControl
;
2026 void helper_mttgpr(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
2028 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2029 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2031 if (other_tc
== other
->current_tc
)
2032 other
->active_tc
.gpr
[sel
] = arg1
;
2034 other
->tcs
[other_tc
].gpr
[sel
] = arg1
;
2037 void helper_mttlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
2039 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2040 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2042 if (other_tc
== other
->current_tc
)
2043 other
->active_tc
.LO
[sel
] = arg1
;
2045 other
->tcs
[other_tc
].LO
[sel
] = arg1
;
2048 void helper_mtthi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
2050 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2051 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2053 if (other_tc
== other
->current_tc
)
2054 other
->active_tc
.HI
[sel
] = arg1
;
2056 other
->tcs
[other_tc
].HI
[sel
] = arg1
;
2059 void helper_mttacx(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
2061 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2062 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2064 if (other_tc
== other
->current_tc
)
2065 other
->active_tc
.ACX
[sel
] = arg1
;
2067 other
->tcs
[other_tc
].ACX
[sel
] = arg1
;
2070 void helper_mttdsp(CPUMIPSState
*env
, target_ulong arg1
)
2072 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2073 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2075 if (other_tc
== other
->current_tc
)
2076 other
->active_tc
.DSPControl
= arg1
;
2078 other
->tcs
[other_tc
].DSPControl
= arg1
;
2081 /* MIPS MT functions */
2082 target_ulong
helper_dmt(void)
2088 target_ulong
helper_emt(void)
2094 target_ulong
helper_dvpe(CPUMIPSState
*env
)
2096 CPUState
*other_cs
= first_cpu
;
2097 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
2099 CPU_FOREACH(other_cs
) {
2100 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
2101 /* Turn off all VPEs except the one executing the dvpe. */
2102 if (&other_cpu
->env
!= env
) {
2103 other_cpu
->env
.mvp
->CP0_MVPControl
&= ~(1 << CP0MVPCo_EVP
);
2104 mips_vpe_sleep(other_cpu
);
2110 target_ulong
helper_evpe(CPUMIPSState
*env
)
2112 CPUState
*other_cs
= first_cpu
;
2113 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
2115 CPU_FOREACH(other_cs
) {
2116 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
2118 if (&other_cpu
->env
!= env
2119 /* If the VPE is WFI, don't disturb its sleep. */
2120 && !mips_vpe_is_wfi(other_cpu
)) {
2121 /* Enable the VPE. */
2122 other_cpu
->env
.mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
2123 mips_vpe_wake(other_cpu
); /* And wake it up. */
2128 #endif /* !CONFIG_USER_ONLY */
2130 void helper_fork(target_ulong arg1
, target_ulong arg2
)
2132 // arg1 = rt, arg2 = rs
2133 // TODO: store to TC register
2136 target_ulong
helper_yield(CPUMIPSState
*env
, target_ulong arg
)
2138 target_long arg1
= arg
;
2141 /* No scheduling policy implemented. */
2143 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
2144 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
2145 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
2146 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
2147 do_raise_exception(env
, EXCP_THREAD
, GETPC());
2150 } else if (arg1
== 0) {
2151 if (0 /* TODO: TC underflow */) {
2152 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
2153 do_raise_exception(env
, EXCP_THREAD
, GETPC());
2155 // TODO: Deallocate TC
2157 } else if (arg1
> 0) {
2158 /* Yield qualifier inputs not implemented. */
2159 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
2160 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
2161 do_raise_exception(env
, EXCP_THREAD
, GETPC());
2163 return env
->CP0_YQMask
;
2166 /* R6 Multi-threading */
2167 #ifndef CONFIG_USER_ONLY
2168 target_ulong
helper_dvp(CPUMIPSState
*env
)
2170 CPUState
*other_cs
= first_cpu
;
2171 target_ulong prev
= env
->CP0_VPControl
;
2173 if (!((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
2174 CPU_FOREACH(other_cs
) {
2175 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
2176 /* Turn off all VPs except the one executing the dvp. */
2177 if (&other_cpu
->env
!= env
) {
2178 mips_vpe_sleep(other_cpu
);
2181 env
->CP0_VPControl
|= (1 << CP0VPCtl_DIS
);
2186 target_ulong
helper_evp(CPUMIPSState
*env
)
2188 CPUState
*other_cs
= first_cpu
;
2189 target_ulong prev
= env
->CP0_VPControl
;
2191 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
2192 CPU_FOREACH(other_cs
) {
2193 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
2194 if ((&other_cpu
->env
!= env
) && !mips_vp_is_wfi(other_cpu
)) {
2195 /* If the VP is WFI, don't disturb its sleep.
2196 * Otherwise, wake it up. */
2197 mips_vpe_wake(other_cpu
);
2200 env
->CP0_VPControl
&= ~(1 << CP0VPCtl_DIS
);
2204 #endif /* !CONFIG_USER_ONLY */
2206 #ifndef CONFIG_USER_ONLY
2207 /* TLB management */
2208 static void r4k_mips_tlb_flush_extra (CPUMIPSState
*env
, int first
)
2210 /* Discard entries from env->tlb[first] onwards. */
2211 while (env
->tlb
->tlb_in_use
> first
) {
2212 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
2216 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo
)
2218 #if defined(TARGET_MIPS64)
2219 return extract64(entrylo
, 6, 54);
2221 return extract64(entrylo
, 6, 24) | /* PFN */
2222 (extract64(entrylo
, 32, 32) << 24); /* PFNX */
2226 static void r4k_fill_tlb(CPUMIPSState
*env
, int idx
)
2229 uint64_t mask
= env
->CP0_PageMask
>> (TARGET_PAGE_BITS
+ 1);
2231 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
2232 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2233 if (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) {
2238 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
2239 #if defined(TARGET_MIPS64)
2240 tlb
->VPN
&= env
->SEGMask
;
2242 tlb
->ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2243 tlb
->PageMask
= env
->CP0_PageMask
;
2244 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
2245 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
2246 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
2247 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
2248 tlb
->XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) & 1;
2249 tlb
->RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) & 1;
2250 tlb
->PFN
[0] = (get_tlb_pfn_from_entrylo(env
->CP0_EntryLo0
) & ~mask
) << 12;
2251 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
2252 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
2253 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
2254 tlb
->XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) & 1;
2255 tlb
->RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) & 1;
2256 tlb
->PFN
[1] = (get_tlb_pfn_from_entrylo(env
->CP0_EntryLo1
) & ~mask
) << 12;
2259 void r4k_helper_tlbinv(CPUMIPSState
*env
)
2263 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2265 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2266 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2267 if (!tlb
->G
&& tlb
->ASID
== ASID
) {
2271 cpu_mips_tlb_flush(env
);
2274 void r4k_helper_tlbinvf(CPUMIPSState
*env
)
2278 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2279 env
->tlb
->mmu
.r4k
.tlb
[idx
].EHINV
= 1;
2281 cpu_mips_tlb_flush(env
);
2284 void r4k_helper_tlbwi(CPUMIPSState
*env
)
2290 bool EHINV
, G
, V0
, D0
, V1
, D1
, XI0
, XI1
, RI0
, RI1
;
2292 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2293 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2294 VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
2295 #if defined(TARGET_MIPS64)
2296 VPN
&= env
->SEGMask
;
2298 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2299 EHINV
= (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) != 0;
2300 G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
2301 V0
= (env
->CP0_EntryLo0
& 2) != 0;
2302 D0
= (env
->CP0_EntryLo0
& 4) != 0;
2303 XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) &1;
2304 RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) &1;
2305 V1
= (env
->CP0_EntryLo1
& 2) != 0;
2306 D1
= (env
->CP0_EntryLo1
& 4) != 0;
2307 XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) &1;
2308 RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) &1;
2310 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2311 permissions on the current entry. */
2312 if (tlb
->VPN
!= VPN
|| tlb
->ASID
!= ASID
|| tlb
->G
!= G
||
2313 (!tlb
->EHINV
&& EHINV
) ||
2314 (tlb
->V0
&& !V0
) || (tlb
->D0
&& !D0
) ||
2315 (!tlb
->XI0
&& XI0
) || (!tlb
->RI0
&& RI0
) ||
2316 (tlb
->V1
&& !V1
) || (tlb
->D1
&& !D1
) ||
2317 (!tlb
->XI1
&& XI1
) || (!tlb
->RI1
&& RI1
)) {
2318 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2321 r4k_invalidate_tlb(env
, idx
, 0);
2322 r4k_fill_tlb(env
, idx
);
2325 void r4k_helper_tlbwr(CPUMIPSState
*env
)
2327 int r
= cpu_mips_get_random(env
);
2329 r4k_invalidate_tlb(env
, r
, 1);
2330 r4k_fill_tlb(env
, r
);
2333 void r4k_helper_tlbp(CPUMIPSState
*env
)
2342 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2343 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
2344 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2345 /* 1k pages are not supported. */
2346 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2347 tag
= env
->CP0_EntryHi
& ~mask
;
2348 VPN
= tlb
->VPN
& ~mask
;
2349 #if defined(TARGET_MIPS64)
2350 tag
&= env
->SEGMask
;
2352 /* Check ASID, virtual page number & size */
2353 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
&& !tlb
->EHINV
) {
2359 if (i
== env
->tlb
->nb_tlb
) {
2360 /* No match. Discard any shadow entries, if any of them match. */
2361 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
2362 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2363 /* 1k pages are not supported. */
2364 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2365 tag
= env
->CP0_EntryHi
& ~mask
;
2366 VPN
= tlb
->VPN
& ~mask
;
2367 #if defined(TARGET_MIPS64)
2368 tag
&= env
->SEGMask
;
2370 /* Check ASID, virtual page number & size */
2371 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
2372 r4k_mips_tlb_flush_extra (env
, i
);
2377 env
->CP0_Index
|= 0x80000000;
2381 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn
)
2383 #if defined(TARGET_MIPS64)
2384 return tlb_pfn
<< 6;
2386 return (extract64(tlb_pfn
, 0, 24) << 6) | /* PFN */
2387 (extract64(tlb_pfn
, 24, 32) << 32); /* PFNX */
2391 void r4k_helper_tlbr(CPUMIPSState
*env
)
2397 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2398 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2399 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2401 /* If this will change the current ASID, flush qemu's TLB. */
2402 if (ASID
!= tlb
->ASID
)
2403 cpu_mips_tlb_flush(env
);
2405 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2408 env
->CP0_EntryHi
= 1 << CP0EnHi_EHINV
;
2409 env
->CP0_PageMask
= 0;
2410 env
->CP0_EntryLo0
= 0;
2411 env
->CP0_EntryLo1
= 0;
2413 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
2414 env
->CP0_PageMask
= tlb
->PageMask
;
2415 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
2416 ((uint64_t)tlb
->RI0
<< CP0EnLo_RI
) |
2417 ((uint64_t)tlb
->XI0
<< CP0EnLo_XI
) | (tlb
->C0
<< 3) |
2418 get_entrylo_pfn_from_tlb(tlb
->PFN
[0] >> 12);
2419 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
2420 ((uint64_t)tlb
->RI1
<< CP0EnLo_RI
) |
2421 ((uint64_t)tlb
->XI1
<< CP0EnLo_XI
) | (tlb
->C1
<< 3) |
2422 get_entrylo_pfn_from_tlb(tlb
->PFN
[1] >> 12);
2426 void helper_tlbwi(CPUMIPSState
*env
)
2428 env
->tlb
->helper_tlbwi(env
);
2431 void helper_tlbwr(CPUMIPSState
*env
)
2433 env
->tlb
->helper_tlbwr(env
);
2436 void helper_tlbp(CPUMIPSState
*env
)
2438 env
->tlb
->helper_tlbp(env
);
2441 void helper_tlbr(CPUMIPSState
*env
)
2443 env
->tlb
->helper_tlbr(env
);
2446 void helper_tlbinv(CPUMIPSState
*env
)
2448 env
->tlb
->helper_tlbinv(env
);
2451 void helper_tlbinvf(CPUMIPSState
*env
)
2453 env
->tlb
->helper_tlbinvf(env
);
2457 target_ulong
helper_di(CPUMIPSState
*env
)
2459 target_ulong t0
= env
->CP0_Status
;
2461 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
2465 target_ulong
helper_ei(CPUMIPSState
*env
)
2467 target_ulong t0
= env
->CP0_Status
;
2469 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
2473 static void debug_pre_eret(CPUMIPSState
*env
)
2475 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2476 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2477 env
->active_tc
.PC
, env
->CP0_EPC
);
2478 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2479 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2480 if (env
->hflags
& MIPS_HFLAG_DM
)
2481 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2486 static void debug_post_eret(CPUMIPSState
*env
)
2488 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
2490 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2491 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2492 env
->active_tc
.PC
, env
->CP0_EPC
);
2493 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2494 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2495 if (env
->hflags
& MIPS_HFLAG_DM
)
2496 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2497 switch (cpu_mmu_index(env
, false)) {
2499 qemu_log(", ERL\n");
2501 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
2502 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
2503 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
2505 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
2511 static void set_pc(CPUMIPSState
*env
, target_ulong error_pc
)
2513 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
2515 env
->hflags
|= MIPS_HFLAG_M16
;
2517 env
->hflags
&= ~(MIPS_HFLAG_M16
);
2521 static inline void exception_return(CPUMIPSState
*env
)
2523 debug_pre_eret(env
);
2524 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2525 set_pc(env
, env
->CP0_ErrorEPC
);
2526 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2528 set_pc(env
, env
->CP0_EPC
);
2529 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2531 compute_hflags(env
);
2532 debug_post_eret(env
);
2535 void helper_eret(CPUMIPSState
*env
)
2537 exception_return(env
);
2538 env
->CP0_LLAddr
= 1;
2542 void helper_eretnc(CPUMIPSState
*env
)
2544 exception_return(env
);
2547 void helper_deret(CPUMIPSState
*env
)
2549 debug_pre_eret(env
);
2551 env
->hflags
&= ~MIPS_HFLAG_DM
;
2552 compute_hflags(env
);
2554 set_pc(env
, env
->CP0_DEPC
);
2556 debug_post_eret(env
);
2558 #endif /* !CONFIG_USER_ONLY */
2560 static inline void check_hwrena(CPUMIPSState
*env
, int reg
, uintptr_t pc
)
2562 if ((env
->hflags
& MIPS_HFLAG_CP0
) || (env
->CP0_HWREna
& (1 << reg
))) {
2565 do_raise_exception(env
, EXCP_RI
, pc
);
2568 target_ulong
helper_rdhwr_cpunum(CPUMIPSState
*env
)
2570 check_hwrena(env
, 0, GETPC());
2571 return env
->CP0_EBase
& 0x3ff;
2574 target_ulong
helper_rdhwr_synci_step(CPUMIPSState
*env
)
2576 check_hwrena(env
, 1, GETPC());
2577 return env
->SYNCI_Step
;
2580 target_ulong
helper_rdhwr_cc(CPUMIPSState
*env
)
2582 check_hwrena(env
, 2, GETPC());
2583 #ifdef CONFIG_USER_ONLY
2584 return env
->CP0_Count
;
2586 return (int32_t)cpu_mips_get_count(env
);
2590 target_ulong
helper_rdhwr_ccres(CPUMIPSState
*env
)
2592 check_hwrena(env
, 3, GETPC());
2596 target_ulong
helper_rdhwr_performance(CPUMIPSState
*env
)
2598 check_hwrena(env
, 4, GETPC());
2599 return env
->CP0_Performance0
;
2602 target_ulong
helper_rdhwr_xnp(CPUMIPSState
*env
)
2604 check_hwrena(env
, 5, GETPC());
2605 return (env
->CP0_Config5
>> CP0C5_XNP
) & 1;
2608 void helper_pmon(CPUMIPSState
*env
, int function
)
2612 case 2: /* TODO: char inbyte(int waitflag); */
2613 if (env
->active_tc
.gpr
[4] == 0)
2614 env
->active_tc
.gpr
[2] = -1;
2616 case 11: /* TODO: char inbyte (void); */
2617 env
->active_tc
.gpr
[2] = -1;
2621 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
2627 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
2634 void helper_wait(CPUMIPSState
*env
)
2636 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2639 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
2640 /* Last instruction in the block, PC was updated before
2641 - no need to recover PC and icount */
2642 raise_exception(env
, EXCP_HLT
);
2645 #if !defined(CONFIG_USER_ONLY)
2647 void mips_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
2648 MMUAccessType access_type
,
2649 int mmu_idx
, uintptr_t retaddr
)
2651 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2652 CPUMIPSState
*env
= &cpu
->env
;
2656 if (!(env
->hflags
& MIPS_HFLAG_DM
)) {
2657 env
->CP0_BadVAddr
= addr
;
2660 if (access_type
== MMU_DATA_STORE
) {
2664 if (access_type
== MMU_INST_FETCH
) {
2665 error_code
|= EXCP_INST_NOTAVAIL
;
2669 do_raise_exception_err(env
, excp
, error_code
, retaddr
);
2672 void tlb_fill(CPUState
*cs
, target_ulong addr
, int size
,
2673 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
2677 ret
= mips_cpu_handle_mmu_fault(cs
, addr
, size
, access_type
, mmu_idx
);
2679 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2680 CPUMIPSState
*env
= &cpu
->env
;
2682 do_raise_exception_err(env
, cs
->exception_index
,
2683 env
->error_code
, retaddr
);
2687 void mips_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2688 bool is_write
, bool is_exec
, int unused
,
2691 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2692 CPUMIPSState
*env
= &cpu
->env
;
2695 * Raising an exception with KVM enabled will crash because it won't be from
2696 * the main execution loop so the longjmp won't have a matching setjmp.
2697 * Until we can trigger a bus error exception through KVM lets just ignore
2700 if (kvm_enabled()) {
2705 raise_exception(env
, EXCP_IBE
);
2707 raise_exception(env
, EXCP_DBE
);
2710 #endif /* !CONFIG_USER_ONLY */
2712 /* Complex FPU operations which may need stack space. */
2714 #define FLOAT_TWO32 make_float32(1 << 30)
2715 #define FLOAT_TWO64 make_float64(1ULL << 62)
2717 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2718 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2720 /* convert MIPS rounding mode in FCR31 to IEEE library */
2721 unsigned int ieee_rm
[] = {
2722 float_round_nearest_even
,
2723 float_round_to_zero
,
2728 target_ulong
helper_cfc1(CPUMIPSState
*env
, uint32_t reg
)
2730 target_ulong arg1
= 0;
2734 arg1
= (int32_t)env
->active_fpu
.fcr0
;
2737 /* UFR Support - Read Status FR */
2738 if (env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) {
2739 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2741 ((env
->CP0_Status
& (1 << CP0St_FR
)) >> CP0St_FR
);
2743 do_raise_exception(env
, EXCP_RI
, GETPC());
2748 /* FRE Support - read Config5.FRE bit */
2749 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
2750 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2751 arg1
= (env
->CP0_Config5
>> CP0C5_FRE
) & 1;
2753 helper_raise_exception(env
, EXCP_RI
);
2758 arg1
= ((env
->active_fpu
.fcr31
>> 24) & 0xfe) | ((env
->active_fpu
.fcr31
>> 23) & 0x1);
2761 arg1
= env
->active_fpu
.fcr31
& 0x0003f07c;
2764 arg1
= (env
->active_fpu
.fcr31
& 0x00000f83) | ((env
->active_fpu
.fcr31
>> 22) & 0x4);
2767 arg1
= (int32_t)env
->active_fpu
.fcr31
;
2774 void helper_ctc1(CPUMIPSState
*env
, target_ulong arg1
, uint32_t fs
, uint32_t rt
)
2778 /* UFR Alias - Reset Status FR */
2779 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2782 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2783 env
->CP0_Status
&= ~(1 << CP0St_FR
);
2784 compute_hflags(env
);
2786 do_raise_exception(env
, EXCP_RI
, GETPC());
2790 /* UNFR Alias - Set Status FR */
2791 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2794 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2795 env
->CP0_Status
|= (1 << CP0St_FR
);
2796 compute_hflags(env
);
2798 do_raise_exception(env
, EXCP_RI
, GETPC());
2802 /* FRE Support - clear Config5.FRE bit */
2803 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2806 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2807 env
->CP0_Config5
&= ~(1 << CP0C5_FRE
);
2808 compute_hflags(env
);
2810 helper_raise_exception(env
, EXCP_RI
);
2814 /* FRE Support - set Config5.FRE bit */
2815 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2818 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2819 env
->CP0_Config5
|= (1 << CP0C5_FRE
);
2820 compute_hflags(env
);
2822 helper_raise_exception(env
, EXCP_RI
);
2826 if ((env
->insn_flags
& ISA_MIPS32R6
) || (arg1
& 0xffffff00)) {
2829 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0x017fffff) | ((arg1
& 0xfe) << 24) |
2830 ((arg1
& 0x1) << 23);
2833 if (arg1
& 0x007c0000)
2835 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfffc0f83) | (arg1
& 0x0003f07c);
2838 if (arg1
& 0x007c0000)
2840 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfefff07c) | (arg1
& 0x00000f83) |
2841 ((arg1
& 0x4) << 22);
2844 env
->active_fpu
.fcr31
= (arg1
& env
->active_fpu
.fcr31_rw_bitmask
) |
2845 (env
->active_fpu
.fcr31
& ~(env
->active_fpu
.fcr31_rw_bitmask
));
2848 if (env
->insn_flags
& ISA_MIPS32R6
) {
2849 do_raise_exception(env
, EXCP_RI
, GETPC());
2853 restore_fp_status(env
);
2854 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2855 if ((GET_FP_ENABLE(env
->active_fpu
.fcr31
) | 0x20) & GET_FP_CAUSE(env
->active_fpu
.fcr31
))
2856 do_raise_exception(env
, EXCP_FPE
, GETPC());
2859 int ieee_ex_to_mips(int xcpt
)
2863 if (xcpt
& float_flag_invalid
) {
2866 if (xcpt
& float_flag_overflow
) {
2869 if (xcpt
& float_flag_underflow
) {
2870 ret
|= FP_UNDERFLOW
;
2872 if (xcpt
& float_flag_divbyzero
) {
2875 if (xcpt
& float_flag_inexact
) {
2882 static inline void update_fcr31(CPUMIPSState
*env
, uintptr_t pc
)
2884 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->active_fpu
.fp_status
));
2886 SET_FP_CAUSE(env
->active_fpu
.fcr31
, tmp
);
2889 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2891 if (GET_FP_ENABLE(env
->active_fpu
.fcr31
) & tmp
) {
2892 do_raise_exception(env
, EXCP_FPE
, pc
);
2894 UPDATE_FP_FLAGS(env
->active_fpu
.fcr31
, tmp
);
2900 Single precition routines have a "s" suffix, double precision a
2901 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2902 paired single lower "pl", paired single upper "pu". */
2904 /* unary operations, modifying fp status */
2905 uint64_t helper_float_sqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2907 fdt0
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2908 update_fcr31(env
, GETPC());
2912 uint32_t helper_float_sqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
2914 fst0
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2915 update_fcr31(env
, GETPC());
2919 uint64_t helper_float_cvtd_s(CPUMIPSState
*env
, uint32_t fst0
)
2923 fdt2
= float32_to_float64(fst0
, &env
->active_fpu
.fp_status
);
2924 update_fcr31(env
, GETPC());
2928 uint64_t helper_float_cvtd_w(CPUMIPSState
*env
, uint32_t wt0
)
2932 fdt2
= int32_to_float64(wt0
, &env
->active_fpu
.fp_status
);
2933 update_fcr31(env
, GETPC());
2937 uint64_t helper_float_cvtd_l(CPUMIPSState
*env
, uint64_t dt0
)
2941 fdt2
= int64_to_float64(dt0
, &env
->active_fpu
.fp_status
);
2942 update_fcr31(env
, GETPC());
2946 uint64_t helper_float_cvt_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2950 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2951 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2952 & (float_flag_invalid
| float_flag_overflow
)) {
2953 dt2
= FP_TO_INT64_OVERFLOW
;
2955 update_fcr31(env
, GETPC());
2959 uint64_t helper_float_cvt_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2963 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2964 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2965 & (float_flag_invalid
| float_flag_overflow
)) {
2966 dt2
= FP_TO_INT64_OVERFLOW
;
2968 update_fcr31(env
, GETPC());
2972 uint64_t helper_float_cvtps_pw(CPUMIPSState
*env
, uint64_t dt0
)
2977 fst2
= int32_to_float32(dt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2978 fsth2
= int32_to_float32(dt0
>> 32, &env
->active_fpu
.fp_status
);
2979 update_fcr31(env
, GETPC());
2980 return ((uint64_t)fsth2
<< 32) | fst2
;
2983 uint64_t helper_float_cvtpw_ps(CPUMIPSState
*env
, uint64_t fdt0
)
2989 wt2
= float32_to_int32(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2990 excp
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2991 if (excp
& (float_flag_overflow
| float_flag_invalid
)) {
2992 wt2
= FP_TO_INT32_OVERFLOW
;
2995 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2996 wth2
= float32_to_int32(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2997 excph
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2998 if (excph
& (float_flag_overflow
| float_flag_invalid
)) {
2999 wth2
= FP_TO_INT32_OVERFLOW
;
3002 set_float_exception_flags(excp
| excph
, &env
->active_fpu
.fp_status
);
3003 update_fcr31(env
, GETPC());
3005 return ((uint64_t)wth2
<< 32) | wt2
;
3008 uint32_t helper_float_cvts_d(CPUMIPSState
*env
, uint64_t fdt0
)
3012 fst2
= float64_to_float32(fdt0
, &env
->active_fpu
.fp_status
);
3013 update_fcr31(env
, GETPC());
3017 uint32_t helper_float_cvts_w(CPUMIPSState
*env
, uint32_t wt0
)
3021 fst2
= int32_to_float32(wt0
, &env
->active_fpu
.fp_status
);
3022 update_fcr31(env
, GETPC());
3026 uint32_t helper_float_cvts_l(CPUMIPSState
*env
, uint64_t dt0
)
3030 fst2
= int64_to_float32(dt0
, &env
->active_fpu
.fp_status
);
3031 update_fcr31(env
, GETPC());
3035 uint32_t helper_float_cvts_pl(CPUMIPSState
*env
, uint32_t wt0
)
3040 update_fcr31(env
, GETPC());
3044 uint32_t helper_float_cvts_pu(CPUMIPSState
*env
, uint32_t wth0
)
3049 update_fcr31(env
, GETPC());
3053 uint32_t helper_float_cvt_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3057 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3058 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3059 & (float_flag_invalid
| float_flag_overflow
)) {
3060 wt2
= FP_TO_INT32_OVERFLOW
;
3062 update_fcr31(env
, GETPC());
3066 uint32_t helper_float_cvt_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3070 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3071 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3072 & (float_flag_invalid
| float_flag_overflow
)) {
3073 wt2
= FP_TO_INT32_OVERFLOW
;
3075 update_fcr31(env
, GETPC());
3079 uint64_t helper_float_round_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3083 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
3084 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3085 restore_rounding_mode(env
);
3086 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3087 & (float_flag_invalid
| float_flag_overflow
)) {
3088 dt2
= FP_TO_INT64_OVERFLOW
;
3090 update_fcr31(env
, GETPC());
3094 uint64_t helper_float_round_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3098 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
3099 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3100 restore_rounding_mode(env
);
3101 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3102 & (float_flag_invalid
| float_flag_overflow
)) {
3103 dt2
= FP_TO_INT64_OVERFLOW
;
3105 update_fcr31(env
, GETPC());
3109 uint32_t helper_float_round_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3113 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
3114 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3115 restore_rounding_mode(env
);
3116 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3117 & (float_flag_invalid
| float_flag_overflow
)) {
3118 wt2
= FP_TO_INT32_OVERFLOW
;
3120 update_fcr31(env
, GETPC());
3124 uint32_t helper_float_round_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3128 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
3129 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3130 restore_rounding_mode(env
);
3131 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3132 & (float_flag_invalid
| float_flag_overflow
)) {
3133 wt2
= FP_TO_INT32_OVERFLOW
;
3135 update_fcr31(env
, GETPC());
3139 uint64_t helper_float_trunc_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3143 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3144 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3145 & (float_flag_invalid
| float_flag_overflow
)) {
3146 dt2
= FP_TO_INT64_OVERFLOW
;
3148 update_fcr31(env
, GETPC());
3152 uint64_t helper_float_trunc_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3156 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3157 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3158 & (float_flag_invalid
| float_flag_overflow
)) {
3159 dt2
= FP_TO_INT64_OVERFLOW
;
3161 update_fcr31(env
, GETPC());
3165 uint32_t helper_float_trunc_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3169 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3170 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3171 & (float_flag_invalid
| float_flag_overflow
)) {
3172 wt2
= FP_TO_INT32_OVERFLOW
;
3174 update_fcr31(env
, GETPC());
3178 uint32_t helper_float_trunc_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3182 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3183 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3184 & (float_flag_invalid
| float_flag_overflow
)) {
3185 wt2
= FP_TO_INT32_OVERFLOW
;
3187 update_fcr31(env
, GETPC());
3191 uint64_t helper_float_ceil_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3195 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3196 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3197 restore_rounding_mode(env
);
3198 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3199 & (float_flag_invalid
| float_flag_overflow
)) {
3200 dt2
= FP_TO_INT64_OVERFLOW
;
3202 update_fcr31(env
, GETPC());
3206 uint64_t helper_float_ceil_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3210 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3211 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3212 restore_rounding_mode(env
);
3213 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3214 & (float_flag_invalid
| float_flag_overflow
)) {
3215 dt2
= FP_TO_INT64_OVERFLOW
;
3217 update_fcr31(env
, GETPC());
3221 uint32_t helper_float_ceil_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3225 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3226 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3227 restore_rounding_mode(env
);
3228 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3229 & (float_flag_invalid
| float_flag_overflow
)) {
3230 wt2
= FP_TO_INT32_OVERFLOW
;
3232 update_fcr31(env
, GETPC());
3236 uint32_t helper_float_ceil_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3240 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3241 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3242 restore_rounding_mode(env
);
3243 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3244 & (float_flag_invalid
| float_flag_overflow
)) {
3245 wt2
= FP_TO_INT32_OVERFLOW
;
3247 update_fcr31(env
, GETPC());
3251 uint64_t helper_float_floor_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3255 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3256 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3257 restore_rounding_mode(env
);
3258 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3259 & (float_flag_invalid
| float_flag_overflow
)) {
3260 dt2
= FP_TO_INT64_OVERFLOW
;
3262 update_fcr31(env
, GETPC());
3266 uint64_t helper_float_floor_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3270 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3271 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3272 restore_rounding_mode(env
);
3273 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3274 & (float_flag_invalid
| float_flag_overflow
)) {
3275 dt2
= FP_TO_INT64_OVERFLOW
;
3277 update_fcr31(env
, GETPC());
3281 uint32_t helper_float_floor_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3285 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3286 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3287 restore_rounding_mode(env
);
3288 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3289 & (float_flag_invalid
| float_flag_overflow
)) {
3290 wt2
= FP_TO_INT32_OVERFLOW
;
3292 update_fcr31(env
, GETPC());
3296 uint32_t helper_float_floor_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3300 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3301 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3302 restore_rounding_mode(env
);
3303 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3304 & (float_flag_invalid
| float_flag_overflow
)) {
3305 wt2
= FP_TO_INT32_OVERFLOW
;
3307 update_fcr31(env
, GETPC());
3311 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3315 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3316 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3317 & float_flag_invalid
) {
3318 if (float64_is_any_nan(fdt0
)) {
3322 update_fcr31(env
, GETPC());
3326 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3330 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3331 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3332 & float_flag_invalid
) {
3333 if (float32_is_any_nan(fst0
)) {
3337 update_fcr31(env
, GETPC());
3341 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3345 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3346 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3347 & float_flag_invalid
) {
3348 if (float64_is_any_nan(fdt0
)) {
3352 update_fcr31(env
, GETPC());
3356 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3360 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3361 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3362 & float_flag_invalid
) {
3363 if (float32_is_any_nan(fst0
)) {
3367 update_fcr31(env
, GETPC());
3371 uint64_t helper_float_round_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3375 set_float_rounding_mode(float_round_nearest_even
,
3376 &env
->active_fpu
.fp_status
);
3377 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3378 restore_rounding_mode(env
);
3379 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3380 & float_flag_invalid
) {
3381 if (float64_is_any_nan(fdt0
)) {
3385 update_fcr31(env
, GETPC());
3389 uint64_t helper_float_round_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3393 set_float_rounding_mode(float_round_nearest_even
,
3394 &env
->active_fpu
.fp_status
);
3395 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3396 restore_rounding_mode(env
);
3397 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3398 & float_flag_invalid
) {
3399 if (float32_is_any_nan(fst0
)) {
3403 update_fcr31(env
, GETPC());
3407 uint32_t helper_float_round_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3411 set_float_rounding_mode(float_round_nearest_even
,
3412 &env
->active_fpu
.fp_status
);
3413 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3414 restore_rounding_mode(env
);
3415 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3416 & float_flag_invalid
) {
3417 if (float64_is_any_nan(fdt0
)) {
3421 update_fcr31(env
, GETPC());
3425 uint32_t helper_float_round_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3429 set_float_rounding_mode(float_round_nearest_even
,
3430 &env
->active_fpu
.fp_status
);
3431 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3432 restore_rounding_mode(env
);
3433 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3434 & float_flag_invalid
) {
3435 if (float32_is_any_nan(fst0
)) {
3439 update_fcr31(env
, GETPC());
3443 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3447 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3448 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3449 & float_flag_invalid
) {
3450 if (float64_is_any_nan(fdt0
)) {
3454 update_fcr31(env
, GETPC());
3458 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3462 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3463 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3464 & float_flag_invalid
) {
3465 if (float32_is_any_nan(fst0
)) {
3469 update_fcr31(env
, GETPC());
3473 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3477 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3478 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3479 & float_flag_invalid
) {
3480 if (float64_is_any_nan(fdt0
)) {
3484 update_fcr31(env
, GETPC());
3488 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3492 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3493 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3494 & float_flag_invalid
) {
3495 if (float32_is_any_nan(fst0
)) {
3499 update_fcr31(env
, GETPC());
3503 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3507 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3508 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3509 restore_rounding_mode(env
);
3510 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3511 & float_flag_invalid
) {
3512 if (float64_is_any_nan(fdt0
)) {
3516 update_fcr31(env
, GETPC());
3520 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3524 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3525 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3526 restore_rounding_mode(env
);
3527 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3528 & float_flag_invalid
) {
3529 if (float32_is_any_nan(fst0
)) {
3533 update_fcr31(env
, GETPC());
3537 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3541 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3542 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3543 restore_rounding_mode(env
);
3544 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3545 & float_flag_invalid
) {
3546 if (float64_is_any_nan(fdt0
)) {
3550 update_fcr31(env
, GETPC());
3554 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3558 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3559 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3560 restore_rounding_mode(env
);
3561 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3562 & float_flag_invalid
) {
3563 if (float32_is_any_nan(fst0
)) {
3567 update_fcr31(env
, GETPC());
3571 uint64_t helper_float_floor_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3575 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3576 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3577 restore_rounding_mode(env
);
3578 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3579 & float_flag_invalid
) {
3580 if (float64_is_any_nan(fdt0
)) {
3584 update_fcr31(env
, GETPC());
3588 uint64_t helper_float_floor_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3592 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3593 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3594 restore_rounding_mode(env
);
3595 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3596 & float_flag_invalid
) {
3597 if (float32_is_any_nan(fst0
)) {
3601 update_fcr31(env
, GETPC());
3605 uint32_t helper_float_floor_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3609 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3610 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3611 restore_rounding_mode(env
);
3612 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3613 & float_flag_invalid
) {
3614 if (float64_is_any_nan(fdt0
)) {
3618 update_fcr31(env
, GETPC());
3622 uint32_t helper_float_floor_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3626 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3627 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3628 restore_rounding_mode(env
);
3629 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3630 & float_flag_invalid
) {
3631 if (float32_is_any_nan(fst0
)) {
3635 update_fcr31(env
, GETPC());
3639 /* unary operations, not modifying fp status */
3640 #define FLOAT_UNOP(name) \
3641 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3643 return float64_ ## name(fdt0); \
3645 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3647 return float32_ ## name(fst0); \
3649 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3654 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3655 wth0 = float32_ ## name(fdt0 >> 32); \
3656 return ((uint64_t)wth0 << 32) | wt0; \
3662 /* MIPS specific unary operations */
3663 uint64_t helper_float_recip_d(CPUMIPSState
*env
, uint64_t fdt0
)
3667 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3668 update_fcr31(env
, GETPC());
3672 uint32_t helper_float_recip_s(CPUMIPSState
*env
, uint32_t fst0
)
3676 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3677 update_fcr31(env
, GETPC());
3681 uint64_t helper_float_rsqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
3685 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3686 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3687 update_fcr31(env
, GETPC());
3691 uint32_t helper_float_rsqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
3695 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3696 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3697 update_fcr31(env
, GETPC());
3701 uint64_t helper_float_recip1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3705 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3706 update_fcr31(env
, GETPC());
3710 uint32_t helper_float_recip1_s(CPUMIPSState
*env
, uint32_t fst0
)
3714 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3715 update_fcr31(env
, GETPC());
3719 uint64_t helper_float_recip1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3724 fst2
= float32_div(float32_one
, fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3725 fsth2
= float32_div(float32_one
, fdt0
>> 32, &env
->active_fpu
.fp_status
);
3726 update_fcr31(env
, GETPC());
3727 return ((uint64_t)fsth2
<< 32) | fst2
;
3730 uint64_t helper_float_rsqrt1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3734 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3735 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3736 update_fcr31(env
, GETPC());
3740 uint32_t helper_float_rsqrt1_s(CPUMIPSState
*env
, uint32_t fst0
)
3744 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3745 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3746 update_fcr31(env
, GETPC());
3750 uint64_t helper_float_rsqrt1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3755 fst2
= float32_sqrt(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3756 fsth2
= float32_sqrt(fdt0
>> 32, &env
->active_fpu
.fp_status
);
3757 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3758 fsth2
= float32_div(float32_one
, fsth2
, &env
->active_fpu
.fp_status
);
3759 update_fcr31(env
, GETPC());
3760 return ((uint64_t)fsth2
<< 32) | fst2
;
3763 #define FLOAT_RINT(name, bits) \
3764 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3765 uint ## bits ## _t fs) \
3767 uint ## bits ## _t fdret; \
3769 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3770 update_fcr31(env, GETPC()); \
3774 FLOAT_RINT(rint_s
, 32)
3775 FLOAT_RINT(rint_d
, 64)
3778 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3779 #define FLOAT_CLASS_QUIET_NAN 0x002
3780 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3781 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3782 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3783 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3784 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3785 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3786 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3787 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3789 #define FLOAT_CLASS(name, bits) \
3790 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3791 float_status *status) \
3793 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3794 return FLOAT_CLASS_SIGNALING_NAN; \
3795 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3796 return FLOAT_CLASS_QUIET_NAN; \
3797 } else if (float ## bits ## _is_neg(arg)) { \
3798 if (float ## bits ## _is_infinity(arg)) { \
3799 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3800 } else if (float ## bits ## _is_zero(arg)) { \
3801 return FLOAT_CLASS_NEGATIVE_ZERO; \
3802 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3803 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3805 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3808 if (float ## bits ## _is_infinity(arg)) { \
3809 return FLOAT_CLASS_POSITIVE_INFINITY; \
3810 } else if (float ## bits ## _is_zero(arg)) { \
3811 return FLOAT_CLASS_POSITIVE_ZERO; \
3812 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3813 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3815 return FLOAT_CLASS_POSITIVE_NORMAL; \
3820 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3821 uint ## bits ## _t arg) \
3823 return float_ ## name(arg, &env->active_fpu.fp_status); \
3826 FLOAT_CLASS(class_s
, 32)
3827 FLOAT_CLASS(class_d
, 64)
3830 /* binary operations */
3831 #define FLOAT_BINOP(name) \
3832 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3833 uint64_t fdt0, uint64_t fdt1) \
3837 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3838 update_fcr31(env, GETPC()); \
3842 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3843 uint32_t fst0, uint32_t fst1) \
3847 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3848 update_fcr31(env, GETPC()); \
3852 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3856 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3857 uint32_t fsth0 = fdt0 >> 32; \
3858 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3859 uint32_t fsth1 = fdt1 >> 32; \
3863 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3864 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3865 update_fcr31(env, GETPC()); \
3866 return ((uint64_t)wth2 << 32) | wt2; \
3875 /* MIPS specific binary operations */
3876 uint64_t helper_float_recip2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3878 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3879 fdt2
= float64_chs(float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
));
3880 update_fcr31(env
, GETPC());
3884 uint32_t helper_float_recip2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3886 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3887 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3888 update_fcr31(env
, GETPC());
3892 uint64_t helper_float_recip2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3894 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3895 uint32_t fsth0
= fdt0
>> 32;
3896 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3897 uint32_t fsth2
= fdt2
>> 32;
3899 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3900 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3901 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3902 fsth2
= float32_chs(float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
));
3903 update_fcr31(env
, GETPC());
3904 return ((uint64_t)fsth2
<< 32) | fst2
;
3907 uint64_t helper_float_rsqrt2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3909 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3910 fdt2
= float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
);
3911 fdt2
= float64_chs(float64_div(fdt2
, FLOAT_TWO64
, &env
->active_fpu
.fp_status
));
3912 update_fcr31(env
, GETPC());
3916 uint32_t helper_float_rsqrt2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3918 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3919 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3920 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3921 update_fcr31(env
, GETPC());
3925 uint64_t helper_float_rsqrt2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3927 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3928 uint32_t fsth0
= fdt0
>> 32;
3929 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3930 uint32_t fsth2
= fdt2
>> 32;
3932 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3933 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3934 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3935 fsth2
= float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
);
3936 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3937 fsth2
= float32_chs(float32_div(fsth2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3938 update_fcr31(env
, GETPC());
3939 return ((uint64_t)fsth2
<< 32) | fst2
;
3942 uint64_t helper_float_addr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3944 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3945 uint32_t fsth0
= fdt0
>> 32;
3946 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3947 uint32_t fsth1
= fdt1
>> 32;
3951 fst2
= float32_add (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3952 fsth2
= float32_add (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3953 update_fcr31(env
, GETPC());
3954 return ((uint64_t)fsth2
<< 32) | fst2
;
3957 uint64_t helper_float_mulr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3959 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3960 uint32_t fsth0
= fdt0
>> 32;
3961 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3962 uint32_t fsth1
= fdt1
>> 32;
3966 fst2
= float32_mul (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3967 fsth2
= float32_mul (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3968 update_fcr31(env
, GETPC());
3969 return ((uint64_t)fsth2
<< 32) | fst2
;
3972 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3973 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3974 uint ## bits ## _t fs, \
3975 uint ## bits ## _t ft) \
3977 uint ## bits ## _t fdret; \
3979 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3980 &env->active_fpu.fp_status); \
3981 update_fcr31(env, GETPC()); \
3985 FLOAT_MINMAX(max_s
, 32, maxnum
)
3986 FLOAT_MINMAX(max_d
, 64, maxnum
)
3987 FLOAT_MINMAX(maxa_s
, 32, maxnummag
)
3988 FLOAT_MINMAX(maxa_d
, 64, maxnummag
)
3990 FLOAT_MINMAX(min_s
, 32, minnum
)
3991 FLOAT_MINMAX(min_d
, 64, minnum
)
3992 FLOAT_MINMAX(mina_s
, 32, minnummag
)
3993 FLOAT_MINMAX(mina_d
, 64, minnummag
)
3996 /* ternary operations */
3997 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3999 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
4000 if ((flags) & float_muladd_negate_c) { \
4001 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
4003 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
4005 if ((flags) & float_muladd_negate_result) { \
4006 a = prefix##_chs(a); \
4010 /* FMA based operations */
4011 #define FLOAT_FMA(name, type) \
4012 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
4013 uint64_t fdt0, uint64_t fdt1, \
4016 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
4017 update_fcr31(env, GETPC()); \
4021 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
4022 uint32_t fst0, uint32_t fst1, \
4025 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4026 update_fcr31(env, GETPC()); \
4030 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
4031 uint64_t fdt0, uint64_t fdt1, \
4034 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
4035 uint32_t fsth0 = fdt0 >> 32; \
4036 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
4037 uint32_t fsth1 = fdt1 >> 32; \
4038 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
4039 uint32_t fsth2 = fdt2 >> 32; \
4041 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4042 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
4043 update_fcr31(env, GETPC()); \
4044 return ((uint64_t)fsth0 << 32) | fst0; \
4047 FLOAT_FMA(msub
, float_muladd_negate_c
)
4048 FLOAT_FMA(nmadd
, float_muladd_negate_result
)
4049 FLOAT_FMA(nmsub
, float_muladd_negate_result
| float_muladd_negate_c
)
4052 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
4053 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
4054 uint ## bits ## _t fs, \
4055 uint ## bits ## _t ft, \
4056 uint ## bits ## _t fd) \
4058 uint ## bits ## _t fdret; \
4060 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
4061 &env->active_fpu.fp_status); \
4062 update_fcr31(env, GETPC()); \
4066 FLOAT_FMADDSUB(maddf_s
, 32, 0)
4067 FLOAT_FMADDSUB(maddf_d
, 64, 0)
4068 FLOAT_FMADDSUB(msubf_s
, 32, float_muladd_negate_product
)
4069 FLOAT_FMADDSUB(msubf_d
, 64, float_muladd_negate_product
)
4070 #undef FLOAT_FMADDSUB
4072 /* compare operations */
4073 #define FOP_COND_D(op, cond) \
4074 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4075 uint64_t fdt1, int cc) \
4079 update_fcr31(env, GETPC()); \
4081 SET_FP_COND(cc, env->active_fpu); \
4083 CLEAR_FP_COND(cc, env->active_fpu); \
4085 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4086 uint64_t fdt1, int cc) \
4089 fdt0 = float64_abs(fdt0); \
4090 fdt1 = float64_abs(fdt1); \
4092 update_fcr31(env, GETPC()); \
4094 SET_FP_COND(cc, env->active_fpu); \
4096 CLEAR_FP_COND(cc, env->active_fpu); \
4099 /* NOTE: the comma operator will make "cond" to eval to false,
4100 * but float64_unordered_quiet() is still called. */
4101 FOP_COND_D(f
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4102 FOP_COND_D(un
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
4103 FOP_COND_D(eq
, float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4104 FOP_COND_D(ueq
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4105 FOP_COND_D(olt
, float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4106 FOP_COND_D(ult
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4107 FOP_COND_D(ole
, float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4108 FOP_COND_D(ule
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4109 /* NOTE: the comma operator will make "cond" to eval to false,
4110 * but float64_unordered() is still called. */
4111 FOP_COND_D(sf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4112 FOP_COND_D(ngle
,float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
4113 FOP_COND_D(seq
, float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4114 FOP_COND_D(ngl
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4115 FOP_COND_D(lt
, float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4116 FOP_COND_D(nge
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4117 FOP_COND_D(le
, float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4118 FOP_COND_D(ngt
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4120 #define FOP_COND_S(op, cond) \
4121 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4122 uint32_t fst1, int cc) \
4126 update_fcr31(env, GETPC()); \
4128 SET_FP_COND(cc, env->active_fpu); \
4130 CLEAR_FP_COND(cc, env->active_fpu); \
4132 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4133 uint32_t fst1, int cc) \
4136 fst0 = float32_abs(fst0); \
4137 fst1 = float32_abs(fst1); \
4139 update_fcr31(env, GETPC()); \
4141 SET_FP_COND(cc, env->active_fpu); \
4143 CLEAR_FP_COND(cc, env->active_fpu); \
4146 /* NOTE: the comma operator will make "cond" to eval to false,
4147 * but float32_unordered_quiet() is still called. */
4148 FOP_COND_S(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4149 FOP_COND_S(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
))
4150 FOP_COND_S(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4151 FOP_COND_S(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4152 FOP_COND_S(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4153 FOP_COND_S(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4154 FOP_COND_S(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4155 FOP_COND_S(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4156 /* NOTE: the comma operator will make "cond" to eval to false,
4157 * but float32_unordered() is still called. */
4158 FOP_COND_S(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4159 FOP_COND_S(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
))
4160 FOP_COND_S(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4161 FOP_COND_S(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4162 FOP_COND_S(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4163 FOP_COND_S(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4164 FOP_COND_S(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4165 FOP_COND_S(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4167 #define FOP_COND_PS(op, condl, condh) \
4168 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4169 uint64_t fdt1, int cc) \
4171 uint32_t fst0, fsth0, fst1, fsth1; \
4173 fst0 = fdt0 & 0XFFFFFFFF; \
4174 fsth0 = fdt0 >> 32; \
4175 fst1 = fdt1 & 0XFFFFFFFF; \
4176 fsth1 = fdt1 >> 32; \
4179 update_fcr31(env, GETPC()); \
4181 SET_FP_COND(cc, env->active_fpu); \
4183 CLEAR_FP_COND(cc, env->active_fpu); \
4185 SET_FP_COND(cc + 1, env->active_fpu); \
4187 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4189 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4190 uint64_t fdt1, int cc) \
4192 uint32_t fst0, fsth0, fst1, fsth1; \
4194 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
4195 fsth0 = float32_abs(fdt0 >> 32); \
4196 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
4197 fsth1 = float32_abs(fdt1 >> 32); \
4200 update_fcr31(env, GETPC()); \
4202 SET_FP_COND(cc, env->active_fpu); \
4204 CLEAR_FP_COND(cc, env->active_fpu); \
4206 SET_FP_COND(cc + 1, env->active_fpu); \
4208 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4211 /* NOTE: the comma operator will make "cond" to eval to false,
4212 * but float32_unordered_quiet() is still called. */
4213 FOP_COND_PS(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
4214 (float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
4215 FOP_COND_PS(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
),
4216 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
4217 FOP_COND_PS(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4218 float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4219 FOP_COND_PS(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4220 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4221 FOP_COND_PS(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4222 float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4223 FOP_COND_PS(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4224 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4225 FOP_COND_PS(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4226 float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4227 FOP_COND_PS(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4228 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4229 /* NOTE: the comma operator will make "cond" to eval to false,
4230 * but float32_unordered() is still called. */
4231 FOP_COND_PS(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
4232 (float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
4233 FOP_COND_PS(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
),
4234 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
4235 FOP_COND_PS(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4236 float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4237 FOP_COND_PS(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4238 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4239 FOP_COND_PS(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4240 float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4241 FOP_COND_PS(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4242 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4243 FOP_COND_PS(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4244 float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4245 FOP_COND_PS(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4246 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4248 /* R6 compare operations */
4249 #define FOP_CONDN_D(op, cond) \
4250 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
4255 update_fcr31(env, GETPC()); \
4263 /* NOTE: the comma operator will make "cond" to eval to false,
4264 * but float64_unordered_quiet() is still called. */
4265 FOP_CONDN_D(af
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4266 FOP_CONDN_D(un
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
4267 FOP_CONDN_D(eq
, (float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4268 FOP_CONDN_D(ueq
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4269 || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4270 FOP_CONDN_D(lt
, (float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4271 FOP_CONDN_D(ult
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4272 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4273 FOP_CONDN_D(le
, (float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4274 FOP_CONDN_D(ule
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4275 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4276 /* NOTE: the comma operator will make "cond" to eval to false,
4277 * but float64_unordered() is still called. */
4278 FOP_CONDN_D(saf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4279 FOP_CONDN_D(sun
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
4280 FOP_CONDN_D(seq
, (float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4281 FOP_CONDN_D(sueq
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4282 || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4283 FOP_CONDN_D(slt
, (float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4284 FOP_CONDN_D(sult
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4285 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4286 FOP_CONDN_D(sle
, (float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4287 FOP_CONDN_D(sule
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4288 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4289 FOP_CONDN_D(or, (float64_le_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4290 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4291 FOP_CONDN_D(une
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4292 || float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4293 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4294 FOP_CONDN_D(ne
, (float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4295 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4296 FOP_CONDN_D(sor
, (float64_le(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4297 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4298 FOP_CONDN_D(sune
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4299 || float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4300 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4301 FOP_CONDN_D(sne
, (float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4302 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4304 #define FOP_CONDN_S(op, cond) \
4305 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4310 update_fcr31(env, GETPC()); \
4318 /* NOTE: the comma operator will make "cond" to eval to false,
4319 * but float32_unordered_quiet() is still called. */
4320 FOP_CONDN_S(af
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4321 FOP_CONDN_S(un
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
4322 FOP_CONDN_S(eq
, (float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4323 FOP_CONDN_S(ueq
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4324 || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4325 FOP_CONDN_S(lt
, (float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4326 FOP_CONDN_S(ult
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4327 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4328 FOP_CONDN_S(le
, (float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4329 FOP_CONDN_S(ule
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4330 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4331 /* NOTE: the comma operator will make "cond" to eval to false,
4332 * but float32_unordered() is still called. */
4333 FOP_CONDN_S(saf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4334 FOP_CONDN_S(sun
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
4335 FOP_CONDN_S(seq
, (float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4336 FOP_CONDN_S(sueq
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4337 || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4338 FOP_CONDN_S(slt
, (float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4339 FOP_CONDN_S(sult
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4340 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4341 FOP_CONDN_S(sle
, (float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4342 FOP_CONDN_S(sule
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4343 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4344 FOP_CONDN_S(or, (float32_le_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4345 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4346 FOP_CONDN_S(une
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4347 || float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4348 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4349 FOP_CONDN_S(ne
, (float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4350 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4351 FOP_CONDN_S(sor
, (float32_le(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4352 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4353 FOP_CONDN_S(sune
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4354 || float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4355 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4356 FOP_CONDN_S(sne
, (float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4357 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4360 /* Data format min and max values */
4361 #define DF_BITS(df) (1 << ((df) + 3))
4363 /* Element-by-element access macros */
4364 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4366 #if !defined(CONFIG_USER_ONLY)
4367 #define MEMOP_IDX(DF) \
4368 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4369 cpu_mmu_index(env, false));
4371 #define MEMOP_IDX(DF)
4374 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
4375 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4376 target_ulong addr) \
4378 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4382 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4383 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
4385 memcpy(pwd, &wx, sizeof(wr_t)); \
4388 #if !defined(CONFIG_USER_ONLY)
4389 MSA_LD_DF(DF_BYTE
, b
, helper_ret_ldub_mmu
, oi
, GETPC())
4390 MSA_LD_DF(DF_HALF
, h
, helper_ret_lduw_mmu
, oi
, GETPC())
4391 MSA_LD_DF(DF_WORD
, w
, helper_ret_ldul_mmu
, oi
, GETPC())
4392 MSA_LD_DF(DF_DOUBLE
, d
, helper_ret_ldq_mmu
, oi
, GETPC())
4394 MSA_LD_DF(DF_BYTE
, b
, cpu_ldub_data
)
4395 MSA_LD_DF(DF_HALF
, h
, cpu_lduw_data
)
4396 MSA_LD_DF(DF_WORD
, w
, cpu_ldl_data
)
4397 MSA_LD_DF(DF_DOUBLE
, d
, cpu_ldq_data
)
4400 #define MSA_PAGESPAN(x) \
4401 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4403 static inline void ensure_writable_pages(CPUMIPSState
*env
,
4408 #if !defined(CONFIG_USER_ONLY)
4409 target_ulong page_addr
;
4410 if (unlikely(MSA_PAGESPAN(addr
))) {
4412 probe_write(env
, addr
, 0, mmu_idx
, retaddr
);
4414 page_addr
= (addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
4415 probe_write(env
, page_addr
, 0, mmu_idx
, retaddr
);
4420 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
4421 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4422 target_ulong addr) \
4424 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4425 int mmu_idx = cpu_mmu_index(env, false); \
4428 ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
4429 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4430 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
4434 #if !defined(CONFIG_USER_ONLY)
4435 MSA_ST_DF(DF_BYTE
, b
, helper_ret_stb_mmu
, oi
, GETPC())
4436 MSA_ST_DF(DF_HALF
, h
, helper_ret_stw_mmu
, oi
, GETPC())
4437 MSA_ST_DF(DF_WORD
, w
, helper_ret_stl_mmu
, oi
, GETPC())
4438 MSA_ST_DF(DF_DOUBLE
, d
, helper_ret_stq_mmu
, oi
, GETPC())
4440 MSA_ST_DF(DF_BYTE
, b
, cpu_stb_data
)
4441 MSA_ST_DF(DF_HALF
, h
, cpu_stw_data
)
4442 MSA_ST_DF(DF_WORD
, w
, cpu_stl_data
)
4443 MSA_ST_DF(DF_DOUBLE
, d
, cpu_stq_data
)
4446 void helper_cache(CPUMIPSState
*env
, target_ulong addr
, uint32_t op
)
4448 #ifndef CONFIG_USER_ONLY
4449 target_ulong index
= addr
& 0x1fffffff;
4451 /* Index Store Tag */
4452 memory_region_dispatch_write(env
->itc_tag
, index
, env
->CP0_TagLo
,
4453 8, MEMTXATTRS_UNSPECIFIED
);
4454 } else if (op
== 5) {
4455 /* Index Load Tag */
4456 memory_region_dispatch_read(env
->itc_tag
, index
, &env
->CP0_TagLo
,
4457 8, MEMTXATTRS_UNSPECIFIED
);