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[mirror_qemu.git] / target / mips / op_helper.c
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "qemu/host-utils.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "sysemu/kvm.h"
28
29 /*****************************************************************************/
30 /* Exceptions processing helpers */
31
32 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
33 int error_code)
34 {
35 do_raise_exception_err(env, exception, error_code, 0);
36 }
37
38 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
39 {
40 do_raise_exception(env, exception, GETPC());
41 }
42
43 void helper_raise_exception_debug(CPUMIPSState *env)
44 {
45 do_raise_exception(env, EXCP_DEBUG, 0);
46 }
47
48 static void raise_exception(CPUMIPSState *env, uint32_t exception)
49 {
50 do_raise_exception(env, exception, 0);
51 }
52
53 #if defined(CONFIG_USER_ONLY)
54 #define HELPER_LD(name, insn, type) \
55 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
56 int mem_idx, uintptr_t retaddr) \
57 { \
58 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
59 }
60 #else
61 #define HELPER_LD(name, insn, type) \
62 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
63 int mem_idx, uintptr_t retaddr) \
64 { \
65 switch (mem_idx) \
66 { \
67 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
68 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
69 default: \
70 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
71 case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \
72 } \
73 }
74 #endif
75 HELPER_LD(lw, ldl, int32_t)
76 #if defined(TARGET_MIPS64)
77 HELPER_LD(ld, ldq, int64_t)
78 #endif
79 #undef HELPER_LD
80
81 #if defined(CONFIG_USER_ONLY)
82 #define HELPER_ST(name, insn, type) \
83 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
84 type val, int mem_idx, uintptr_t retaddr) \
85 { \
86 cpu_##insn##_data_ra(env, addr, val, retaddr); \
87 }
88 #else
89 #define HELPER_ST(name, insn, type) \
90 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
91 type val, int mem_idx, uintptr_t retaddr) \
92 { \
93 switch (mem_idx) \
94 { \
95 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
96 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
97 default: \
98 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
99 case 3: \
100 cpu_##insn##_error_ra(env, addr, val, retaddr); \
101 break; \
102 } \
103 }
104 #endif
105 HELPER_ST(sb, stb, uint8_t)
106 HELPER_ST(sw, stl, uint32_t)
107 #if defined(TARGET_MIPS64)
108 HELPER_ST(sd, stq, uint64_t)
109 #endif
110 #undef HELPER_ST
111
112 /* 64 bits arithmetic for 32 bits hosts */
113 static inline uint64_t get_HILO(CPUMIPSState *env)
114 {
115 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
116 }
117
118 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
119 {
120 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
121 return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
122 }
123
124 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
125 {
126 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
127 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
128 return tmp;
129 }
130
131 /* Multiplication variants of the vr54xx. */
132 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
133 target_ulong arg2)
134 {
135 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
136 (int64_t)(int32_t)arg2));
137 }
138
139 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
140 target_ulong arg2)
141 {
142 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
143 (uint64_t)(uint32_t)arg2);
144 }
145
146 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
147 target_ulong arg2)
148 {
149 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
150 (int64_t)(int32_t)arg2);
151 }
152
153 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
154 target_ulong arg2)
155 {
156 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
157 (int64_t)(int32_t)arg2);
158 }
159
160 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
161 target_ulong arg2)
162 {
163 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
164 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
165 }
166
167 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
168 target_ulong arg2)
169 {
170 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
171 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
172 }
173
174 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
175 target_ulong arg2)
176 {
177 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
178 (int64_t)(int32_t)arg2);
179 }
180
181 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
182 target_ulong arg2)
183 {
184 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
185 (int64_t)(int32_t)arg2);
186 }
187
188 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
189 target_ulong arg2)
190 {
191 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
192 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
193 }
194
195 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
196 target_ulong arg2)
197 {
198 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
199 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
200 }
201
202 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
203 target_ulong arg2)
204 {
205 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
206 }
207
208 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
209 target_ulong arg2)
210 {
211 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
212 (uint64_t)(uint32_t)arg2);
213 }
214
215 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
216 target_ulong arg2)
217 {
218 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
219 (int64_t)(int32_t)arg2);
220 }
221
222 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
223 target_ulong arg2)
224 {
225 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
226 (uint64_t)(uint32_t)arg2);
227 }
228
229 static inline target_ulong bitswap(target_ulong v)
230 {
231 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
232 ((v & (target_ulong)0x5555555555555555ULL) << 1);
233 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
234 ((v & (target_ulong)0x3333333333333333ULL) << 2);
235 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
236 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
237 return v;
238 }
239
240 #ifdef TARGET_MIPS64
241 target_ulong helper_dbitswap(target_ulong rt)
242 {
243 return bitswap(rt);
244 }
245 #endif
246
247 target_ulong helper_bitswap(target_ulong rt)
248 {
249 return (int32_t)bitswap(rt);
250 }
251
252 target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
253 uint32_t stripe)
254 {
255 int i;
256 uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);
257 uint64_t tmp1 = tmp0;
258 for (i = 0; i <= 46; i++) {
259 int s;
260 if (i & 0x8) {
261 s = shift;
262 } else {
263 s = shiftx;
264 }
265
266 if (stripe != 0 && !(i & 0x4)) {
267 s = ~s;
268 }
269 if (s & 0x10) {
270 if (tmp0 & (1LL << (i + 16))) {
271 tmp1 |= 1LL << i;
272 } else {
273 tmp1 &= ~(1LL << i);
274 }
275 }
276 }
277
278 uint64_t tmp2 = tmp1;
279 for (i = 0; i <= 38; i++) {
280 int s;
281 if (i & 0x4) {
282 s = shift;
283 } else {
284 s = shiftx;
285 }
286
287 if (s & 0x8) {
288 if (tmp1 & (1LL << (i + 8))) {
289 tmp2 |= 1LL << i;
290 } else {
291 tmp2 &= ~(1LL << i);
292 }
293 }
294 }
295
296 uint64_t tmp3 = tmp2;
297 for (i = 0; i <= 34; i++) {
298 int s;
299 if (i & 0x2) {
300 s = shift;
301 } else {
302 s = shiftx;
303 }
304 if (s & 0x4) {
305 if (tmp2 & (1LL << (i + 4))) {
306 tmp3 |= 1LL << i;
307 } else {
308 tmp3 &= ~(1LL << i);
309 }
310 }
311 }
312
313 uint64_t tmp4 = tmp3;
314 for (i = 0; i <= 32; i++) {
315 int s;
316 if (i & 0x1) {
317 s = shift;
318 } else {
319 s = shiftx;
320 }
321 if (s & 0x2) {
322 if (tmp3 & (1LL << (i + 2))) {
323 tmp4 |= 1LL << i;
324 } else {
325 tmp4 &= ~(1LL << i);
326 }
327 }
328 }
329
330 uint64_t tmp5 = tmp4;
331 for (i = 0; i <= 31; i++) {
332 int s;
333 s = shift;
334 if (s & 0x1) {
335 if (tmp4 & (1LL << (i + 1))) {
336 tmp5 |= 1LL << i;
337 } else {
338 tmp5 &= ~(1LL << i);
339 }
340 }
341 }
342
343 return (int64_t)(int32_t)(uint32_t)tmp5;
344 }
345
346 #ifndef CONFIG_USER_ONLY
347
348 static inline hwaddr do_translate_address(CPUMIPSState *env,
349 target_ulong address,
350 int rw, uintptr_t retaddr)
351 {
352 hwaddr paddr;
353 CPUState *cs = CPU(mips_env_get_cpu(env));
354
355 paddr = cpu_mips_translate_address(env, address, rw);
356
357 if (paddr == -1LL) {
358 cpu_loop_exit_restore(cs, retaddr);
359 } else {
360 return paddr;
361 }
362 }
363
364 #define HELPER_LD_ATOMIC(name, insn, almask) \
365 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
366 { \
367 if (arg & almask) { \
368 if (!(env->hflags & MIPS_HFLAG_DM)) { \
369 env->CP0_BadVAddr = arg; \
370 } \
371 do_raise_exception(env, EXCP_AdEL, GETPC()); \
372 } \
373 env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC()); \
374 env->lladdr = arg; \
375 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
376 return env->llval; \
377 }
378 HELPER_LD_ATOMIC(ll, lw, 0x3)
379 #ifdef TARGET_MIPS64
380 HELPER_LD_ATOMIC(lld, ld, 0x7)
381 #endif
382 #undef HELPER_LD_ATOMIC
383 #endif
384
385 #ifdef TARGET_WORDS_BIGENDIAN
386 #define GET_LMASK(v) ((v) & 3)
387 #define GET_OFFSET(addr, offset) (addr + (offset))
388 #else
389 #define GET_LMASK(v) (((v) & 3) ^ 3)
390 #define GET_OFFSET(addr, offset) (addr - (offset))
391 #endif
392
393 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
394 int mem_idx)
395 {
396 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
397
398 if (GET_LMASK(arg2) <= 2) {
399 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
400 GETPC());
401 }
402
403 if (GET_LMASK(arg2) <= 1) {
404 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
405 GETPC());
406 }
407
408 if (GET_LMASK(arg2) == 0) {
409 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
410 GETPC());
411 }
412 }
413
414 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
415 int mem_idx)
416 {
417 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
418
419 if (GET_LMASK(arg2) >= 1) {
420 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
421 GETPC());
422 }
423
424 if (GET_LMASK(arg2) >= 2) {
425 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
426 GETPC());
427 }
428
429 if (GET_LMASK(arg2) == 3) {
430 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
431 GETPC());
432 }
433 }
434
435 #if defined(TARGET_MIPS64)
436 /* "half" load and stores. We must do the memory access inline,
437 or fault handling won't work. */
438
439 #ifdef TARGET_WORDS_BIGENDIAN
440 #define GET_LMASK64(v) ((v) & 7)
441 #else
442 #define GET_LMASK64(v) (((v) & 7) ^ 7)
443 #endif
444
445 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
446 int mem_idx)
447 {
448 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
449
450 if (GET_LMASK64(arg2) <= 6) {
451 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
452 GETPC());
453 }
454
455 if (GET_LMASK64(arg2) <= 5) {
456 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
457 GETPC());
458 }
459
460 if (GET_LMASK64(arg2) <= 4) {
461 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
462 GETPC());
463 }
464
465 if (GET_LMASK64(arg2) <= 3) {
466 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
467 GETPC());
468 }
469
470 if (GET_LMASK64(arg2) <= 2) {
471 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
472 GETPC());
473 }
474
475 if (GET_LMASK64(arg2) <= 1) {
476 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
477 GETPC());
478 }
479
480 if (GET_LMASK64(arg2) <= 0) {
481 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
482 GETPC());
483 }
484 }
485
486 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
487 int mem_idx)
488 {
489 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
490
491 if (GET_LMASK64(arg2) >= 1) {
492 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
493 GETPC());
494 }
495
496 if (GET_LMASK64(arg2) >= 2) {
497 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
498 GETPC());
499 }
500
501 if (GET_LMASK64(arg2) >= 3) {
502 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
503 GETPC());
504 }
505
506 if (GET_LMASK64(arg2) >= 4) {
507 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
508 GETPC());
509 }
510
511 if (GET_LMASK64(arg2) >= 5) {
512 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
513 GETPC());
514 }
515
516 if (GET_LMASK64(arg2) >= 6) {
517 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
518 GETPC());
519 }
520
521 if (GET_LMASK64(arg2) == 7) {
522 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
523 GETPC());
524 }
525 }
526 #endif /* TARGET_MIPS64 */
527
528 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
529
530 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
531 uint32_t mem_idx)
532 {
533 target_ulong base_reglist = reglist & 0xf;
534 target_ulong do_r31 = reglist & 0x10;
535
536 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
537 target_ulong i;
538
539 for (i = 0; i < base_reglist; i++) {
540 env->active_tc.gpr[multiple_regs[i]] =
541 (target_long)do_lw(env, addr, mem_idx, GETPC());
542 addr += 4;
543 }
544 }
545
546 if (do_r31) {
547 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
548 GETPC());
549 }
550 }
551
552 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
553 uint32_t mem_idx)
554 {
555 target_ulong base_reglist = reglist & 0xf;
556 target_ulong do_r31 = reglist & 0x10;
557
558 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
559 target_ulong i;
560
561 for (i = 0; i < base_reglist; i++) {
562 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
563 GETPC());
564 addr += 4;
565 }
566 }
567
568 if (do_r31) {
569 do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
570 }
571 }
572
573 #if defined(TARGET_MIPS64)
574 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
575 uint32_t mem_idx)
576 {
577 target_ulong base_reglist = reglist & 0xf;
578 target_ulong do_r31 = reglist & 0x10;
579
580 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
581 target_ulong i;
582
583 for (i = 0; i < base_reglist; i++) {
584 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
585 GETPC());
586 addr += 8;
587 }
588 }
589
590 if (do_r31) {
591 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
592 }
593 }
594
595 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
596 uint32_t mem_idx)
597 {
598 target_ulong base_reglist = reglist & 0xf;
599 target_ulong do_r31 = reglist & 0x10;
600
601 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
602 target_ulong i;
603
604 for (i = 0; i < base_reglist; i++) {
605 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
606 GETPC());
607 addr += 8;
608 }
609 }
610
611 if (do_r31) {
612 do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
613 }
614 }
615 #endif
616
617 #ifndef CONFIG_USER_ONLY
618 /* SMP helpers. */
619 static bool mips_vpe_is_wfi(MIPSCPU *c)
620 {
621 CPUState *cpu = CPU(c);
622 CPUMIPSState *env = &c->env;
623
624 /* If the VPE is halted but otherwise active, it means it's waiting for
625 an interrupt. */
626 return cpu->halted && mips_vpe_active(env);
627 }
628
629 static bool mips_vp_is_wfi(MIPSCPU *c)
630 {
631 CPUState *cpu = CPU(c);
632 CPUMIPSState *env = &c->env;
633
634 return cpu->halted && mips_vp_active(env);
635 }
636
637 static inline void mips_vpe_wake(MIPSCPU *c)
638 {
639 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
640 because there might be other conditions that state that c should
641 be sleeping. */
642 qemu_mutex_lock_iothread();
643 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
644 qemu_mutex_unlock_iothread();
645 }
646
647 static inline void mips_vpe_sleep(MIPSCPU *cpu)
648 {
649 CPUState *cs = CPU(cpu);
650
651 /* The VPE was shut off, really go to bed.
652 Reset any old _WAKE requests. */
653 cs->halted = 1;
654 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
655 }
656
657 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
658 {
659 CPUMIPSState *c = &cpu->env;
660
661 /* FIXME: TC reschedule. */
662 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
663 mips_vpe_wake(cpu);
664 }
665 }
666
667 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
668 {
669 CPUMIPSState *c = &cpu->env;
670
671 /* FIXME: TC reschedule. */
672 if (!mips_vpe_active(c)) {
673 mips_vpe_sleep(cpu);
674 }
675 }
676
677 /**
678 * mips_cpu_map_tc:
679 * @env: CPU from which mapping is performed.
680 * @tc: Should point to an int with the value of the global TC index.
681 *
682 * This function will transform @tc into a local index within the
683 * returned #CPUMIPSState.
684 */
685 /* FIXME: This code assumes that all VPEs have the same number of TCs,
686 which depends on runtime setup. Can probably be fixed by
687 walking the list of CPUMIPSStates. */
688 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
689 {
690 MIPSCPU *cpu;
691 CPUState *cs;
692 CPUState *other_cs;
693 int vpe_idx;
694 int tc_idx = *tc;
695
696 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
697 /* Not allowed to address other CPUs. */
698 *tc = env->current_tc;
699 return env;
700 }
701
702 cs = CPU(mips_env_get_cpu(env));
703 vpe_idx = tc_idx / cs->nr_threads;
704 *tc = tc_idx % cs->nr_threads;
705 other_cs = qemu_get_cpu(vpe_idx);
706 if (other_cs == NULL) {
707 return env;
708 }
709 cpu = MIPS_CPU(other_cs);
710 return &cpu->env;
711 }
712
713 /* The per VPE CP0_Status register shares some fields with the per TC
714 CP0_TCStatus registers. These fields are wired to the same registers,
715 so changes to either of them should be reflected on both registers.
716
717 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
718
719 These helper call synchronizes the regs for a given cpu. */
720
721 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
722 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
723 int tc); */
724
725 /* Called for updates to CP0_TCStatus. */
726 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
727 target_ulong v)
728 {
729 uint32_t status;
730 uint32_t tcu, tmx, tasid, tksu;
731 uint32_t mask = ((1U << CP0St_CU3)
732 | (1 << CP0St_CU2)
733 | (1 << CP0St_CU1)
734 | (1 << CP0St_CU0)
735 | (1 << CP0St_MX)
736 | (3 << CP0St_KSU));
737
738 tcu = (v >> CP0TCSt_TCU0) & 0xf;
739 tmx = (v >> CP0TCSt_TMX) & 0x1;
740 tasid = v & cpu->CP0_EntryHi_ASID_mask;
741 tksu = (v >> CP0TCSt_TKSU) & 0x3;
742
743 status = tcu << CP0St_CU0;
744 status |= tmx << CP0St_MX;
745 status |= tksu << CP0St_KSU;
746
747 cpu->CP0_Status &= ~mask;
748 cpu->CP0_Status |= status;
749
750 /* Sync the TASID with EntryHi. */
751 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
752 cpu->CP0_EntryHi |= tasid;
753
754 compute_hflags(cpu);
755 }
756
757 /* Called for updates to CP0_EntryHi. */
758 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
759 {
760 int32_t *tcst;
761 uint32_t asid, v = cpu->CP0_EntryHi;
762
763 asid = v & cpu->CP0_EntryHi_ASID_mask;
764
765 if (tc == cpu->current_tc) {
766 tcst = &cpu->active_tc.CP0_TCStatus;
767 } else {
768 tcst = &cpu->tcs[tc].CP0_TCStatus;
769 }
770
771 *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
772 *tcst |= asid;
773 }
774
775 /* CP0 helpers */
776 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
777 {
778 return env->mvp->CP0_MVPControl;
779 }
780
781 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
782 {
783 return env->mvp->CP0_MVPConf0;
784 }
785
786 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
787 {
788 return env->mvp->CP0_MVPConf1;
789 }
790
791 target_ulong helper_mfc0_random(CPUMIPSState *env)
792 {
793 return (int32_t)cpu_mips_get_random(env);
794 }
795
796 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
797 {
798 return env->active_tc.CP0_TCStatus;
799 }
800
801 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
802 {
803 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
804 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
805
806 if (other_tc == other->current_tc)
807 return other->active_tc.CP0_TCStatus;
808 else
809 return other->tcs[other_tc].CP0_TCStatus;
810 }
811
812 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
813 {
814 return env->active_tc.CP0_TCBind;
815 }
816
817 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
818 {
819 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
820 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
821
822 if (other_tc == other->current_tc)
823 return other->active_tc.CP0_TCBind;
824 else
825 return other->tcs[other_tc].CP0_TCBind;
826 }
827
828 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
829 {
830 return env->active_tc.PC;
831 }
832
833 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
834 {
835 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
836 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
837
838 if (other_tc == other->current_tc)
839 return other->active_tc.PC;
840 else
841 return other->tcs[other_tc].PC;
842 }
843
844 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
845 {
846 return env->active_tc.CP0_TCHalt;
847 }
848
849 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
850 {
851 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
852 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
853
854 if (other_tc == other->current_tc)
855 return other->active_tc.CP0_TCHalt;
856 else
857 return other->tcs[other_tc].CP0_TCHalt;
858 }
859
860 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
861 {
862 return env->active_tc.CP0_TCContext;
863 }
864
865 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
866 {
867 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
868 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
869
870 if (other_tc == other->current_tc)
871 return other->active_tc.CP0_TCContext;
872 else
873 return other->tcs[other_tc].CP0_TCContext;
874 }
875
876 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
877 {
878 return env->active_tc.CP0_TCSchedule;
879 }
880
881 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
882 {
883 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
884 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
885
886 if (other_tc == other->current_tc)
887 return other->active_tc.CP0_TCSchedule;
888 else
889 return other->tcs[other_tc].CP0_TCSchedule;
890 }
891
892 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
893 {
894 return env->active_tc.CP0_TCScheFBack;
895 }
896
897 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
898 {
899 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
900 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
901
902 if (other_tc == other->current_tc)
903 return other->active_tc.CP0_TCScheFBack;
904 else
905 return other->tcs[other_tc].CP0_TCScheFBack;
906 }
907
908 target_ulong helper_mfc0_count(CPUMIPSState *env)
909 {
910 return (int32_t)cpu_mips_get_count(env);
911 }
912
913 target_ulong helper_mfc0_saar(CPUMIPSState *env)
914 {
915 if ((env->CP0_SAARI & 0x3f) < 2) {
916 return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
917 }
918 return 0;
919 }
920
921 target_ulong helper_mfhc0_saar(CPUMIPSState *env)
922 {
923 if ((env->CP0_SAARI & 0x3f) < 2) {
924 return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
925 }
926 return 0;
927 }
928
929 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
930 {
931 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
932 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
933
934 return other->CP0_EntryHi;
935 }
936
937 target_ulong helper_mftc0_cause(CPUMIPSState *env)
938 {
939 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
940 int32_t tccause;
941 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
942
943 if (other_tc == other->current_tc) {
944 tccause = other->CP0_Cause;
945 } else {
946 tccause = other->CP0_Cause;
947 }
948
949 return tccause;
950 }
951
952 target_ulong helper_mftc0_status(CPUMIPSState *env)
953 {
954 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
955 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
956
957 return other->CP0_Status;
958 }
959
960 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
961 {
962 return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift);
963 }
964
965 target_ulong helper_mfc0_maar(CPUMIPSState *env)
966 {
967 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
968 }
969
970 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
971 {
972 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
973 }
974
975 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
976 {
977 return (int32_t)env->CP0_WatchLo[sel];
978 }
979
980 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
981 {
982 return env->CP0_WatchHi[sel];
983 }
984
985 target_ulong helper_mfc0_debug(CPUMIPSState *env)
986 {
987 target_ulong t0 = env->CP0_Debug;
988 if (env->hflags & MIPS_HFLAG_DM)
989 t0 |= 1 << CP0DB_DM;
990
991 return t0;
992 }
993
994 target_ulong helper_mftc0_debug(CPUMIPSState *env)
995 {
996 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
997 int32_t tcstatus;
998 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
999
1000 if (other_tc == other->current_tc)
1001 tcstatus = other->active_tc.CP0_Debug_tcstatus;
1002 else
1003 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
1004
1005 /* XXX: Might be wrong, check with EJTAG spec. */
1006 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1007 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1008 }
1009
1010 #if defined(TARGET_MIPS64)
1011 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
1012 {
1013 return env->active_tc.PC;
1014 }
1015
1016 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
1017 {
1018 return env->active_tc.CP0_TCHalt;
1019 }
1020
1021 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
1022 {
1023 return env->active_tc.CP0_TCContext;
1024 }
1025
1026 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
1027 {
1028 return env->active_tc.CP0_TCSchedule;
1029 }
1030
1031 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
1032 {
1033 return env->active_tc.CP0_TCScheFBack;
1034 }
1035
1036 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
1037 {
1038 return env->CP0_LLAddr >> env->CP0_LLAddr_shift;
1039 }
1040
1041 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
1042 {
1043 return env->CP0_MAAR[env->CP0_MAARI];
1044 }
1045
1046 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
1047 {
1048 return env->CP0_WatchLo[sel];
1049 }
1050
1051 target_ulong helper_dmfc0_saar(CPUMIPSState *env)
1052 {
1053 if ((env->CP0_SAARI & 0x3f) < 2) {
1054 return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
1055 }
1056 return 0;
1057 }
1058 #endif /* TARGET_MIPS64 */
1059
1060 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
1061 {
1062 uint32_t index_p = env->CP0_Index & 0x80000000;
1063 uint32_t tlb_index = arg1 & 0x7fffffff;
1064 if (tlb_index < env->tlb->nb_tlb) {
1065 if (env->insn_flags & ISA_MIPS32R6) {
1066 index_p |= arg1 & 0x80000000;
1067 }
1068 env->CP0_Index = index_p | tlb_index;
1069 }
1070 }
1071
1072 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
1073 {
1074 uint32_t mask = 0;
1075 uint32_t newval;
1076
1077 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
1078 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
1079 (1 << CP0MVPCo_EVP);
1080 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1081 mask |= (1 << CP0MVPCo_STLB);
1082 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1083
1084 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1085
1086 env->mvp->CP0_MVPControl = newval;
1087 }
1088
1089 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1090 {
1091 uint32_t mask;
1092 uint32_t newval;
1093
1094 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1095 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1096 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1097
1098 /* Yield scheduler intercept not implemented. */
1099 /* Gating storage scheduler intercept not implemented. */
1100
1101 // TODO: Enable/disable TCs.
1102
1103 env->CP0_VPEControl = newval;
1104 }
1105
1106 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1107 {
1108 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1109 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1110 uint32_t mask;
1111 uint32_t newval;
1112
1113 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1114 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1115 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1116
1117 /* TODO: Enable/disable TCs. */
1118
1119 other->CP0_VPEControl = newval;
1120 }
1121
1122 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1123 {
1124 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1125 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1126 /* FIXME: Mask away return zero on read bits. */
1127 return other->CP0_VPEControl;
1128 }
1129
1130 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1131 {
1132 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1133 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1134
1135 return other->CP0_VPEConf0;
1136 }
1137
1138 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1139 {
1140 uint32_t mask = 0;
1141 uint32_t newval;
1142
1143 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1144 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1145 mask |= (0xff << CP0VPEC0_XTC);
1146 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1147 }
1148 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1149
1150 // TODO: TC exclusive handling due to ERL/EXL.
1151
1152 env->CP0_VPEConf0 = newval;
1153 }
1154
1155 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1156 {
1157 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1158 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1159 uint32_t mask = 0;
1160 uint32_t newval;
1161
1162 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1163 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1164
1165 /* TODO: TC exclusive handling due to ERL/EXL. */
1166 other->CP0_VPEConf0 = newval;
1167 }
1168
1169 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1170 {
1171 uint32_t mask = 0;
1172 uint32_t newval;
1173
1174 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1175 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1176 (0xff << CP0VPEC1_NCP1);
1177 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1178
1179 /* UDI not implemented. */
1180 /* CP2 not implemented. */
1181
1182 // TODO: Handle FPU (CP1) binding.
1183
1184 env->CP0_VPEConf1 = newval;
1185 }
1186
1187 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1188 {
1189 /* Yield qualifier inputs not implemented. */
1190 env->CP0_YQMask = 0x00000000;
1191 }
1192
1193 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1194 {
1195 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1196 }
1197
1198 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1199
1200 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1201 {
1202 /* 1k pages not implemented */
1203 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1204 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1205 | (rxi << (CP0EnLo_XI - 30));
1206 }
1207
1208 #if defined(TARGET_MIPS64)
1209 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1210
1211 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1212 {
1213 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1214 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1215 }
1216 #endif
1217
1218 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1219 {
1220 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1221 uint32_t newval;
1222
1223 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1224
1225 env->active_tc.CP0_TCStatus = newval;
1226 sync_c0_tcstatus(env, env->current_tc, newval);
1227 }
1228
1229 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1230 {
1231 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1232 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1233
1234 if (other_tc == other->current_tc)
1235 other->active_tc.CP0_TCStatus = arg1;
1236 else
1237 other->tcs[other_tc].CP0_TCStatus = arg1;
1238 sync_c0_tcstatus(other, other_tc, arg1);
1239 }
1240
1241 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1242 {
1243 uint32_t mask = (1 << CP0TCBd_TBE);
1244 uint32_t newval;
1245
1246 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1247 mask |= (1 << CP0TCBd_CurVPE);
1248 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1249 env->active_tc.CP0_TCBind = newval;
1250 }
1251
1252 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1253 {
1254 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1255 uint32_t mask = (1 << CP0TCBd_TBE);
1256 uint32_t newval;
1257 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1258
1259 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1260 mask |= (1 << CP0TCBd_CurVPE);
1261 if (other_tc == other->current_tc) {
1262 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1263 other->active_tc.CP0_TCBind = newval;
1264 } else {
1265 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1266 other->tcs[other_tc].CP0_TCBind = newval;
1267 }
1268 }
1269
1270 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1271 {
1272 env->active_tc.PC = arg1;
1273 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1274 env->CP0_LLAddr = 0;
1275 env->lladdr = 0;
1276 /* MIPS16 not implemented. */
1277 }
1278
1279 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1280 {
1281 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1282 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1283
1284 if (other_tc == other->current_tc) {
1285 other->active_tc.PC = arg1;
1286 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1287 other->CP0_LLAddr = 0;
1288 other->lladdr = 0;
1289 /* MIPS16 not implemented. */
1290 } else {
1291 other->tcs[other_tc].PC = arg1;
1292 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1293 other->CP0_LLAddr = 0;
1294 other->lladdr = 0;
1295 /* MIPS16 not implemented. */
1296 }
1297 }
1298
1299 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1300 {
1301 MIPSCPU *cpu = mips_env_get_cpu(env);
1302
1303 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1304
1305 // TODO: Halt TC / Restart (if allocated+active) TC.
1306 if (env->active_tc.CP0_TCHalt & 1) {
1307 mips_tc_sleep(cpu, env->current_tc);
1308 } else {
1309 mips_tc_wake(cpu, env->current_tc);
1310 }
1311 }
1312
1313 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1314 {
1315 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1316 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1317 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1318
1319 // TODO: Halt TC / Restart (if allocated+active) TC.
1320
1321 if (other_tc == other->current_tc)
1322 other->active_tc.CP0_TCHalt = arg1;
1323 else
1324 other->tcs[other_tc].CP0_TCHalt = arg1;
1325
1326 if (arg1 & 1) {
1327 mips_tc_sleep(other_cpu, other_tc);
1328 } else {
1329 mips_tc_wake(other_cpu, other_tc);
1330 }
1331 }
1332
1333 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1334 {
1335 env->active_tc.CP0_TCContext = arg1;
1336 }
1337
1338 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1339 {
1340 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1341 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1342
1343 if (other_tc == other->current_tc)
1344 other->active_tc.CP0_TCContext = arg1;
1345 else
1346 other->tcs[other_tc].CP0_TCContext = arg1;
1347 }
1348
1349 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1350 {
1351 env->active_tc.CP0_TCSchedule = arg1;
1352 }
1353
1354 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1355 {
1356 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1357 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1358
1359 if (other_tc == other->current_tc)
1360 other->active_tc.CP0_TCSchedule = arg1;
1361 else
1362 other->tcs[other_tc].CP0_TCSchedule = arg1;
1363 }
1364
1365 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1366 {
1367 env->active_tc.CP0_TCScheFBack = arg1;
1368 }
1369
1370 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1371 {
1372 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1373 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1374
1375 if (other_tc == other->current_tc)
1376 other->active_tc.CP0_TCScheFBack = arg1;
1377 else
1378 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1379 }
1380
1381 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1382 {
1383 /* 1k pages not implemented */
1384 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1385 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1386 | (rxi << (CP0EnLo_XI - 30));
1387 }
1388
1389 #if defined(TARGET_MIPS64)
1390 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1391 {
1392 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1393 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1394 }
1395 #endif
1396
1397 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1398 {
1399 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1400 }
1401
1402 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
1403 {
1404 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1405 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1406 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1407 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1408 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1409 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1410 }
1411 }
1412
1413 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1414 {
1415 update_pagemask(env, arg1, &env->CP0_PageMask);
1416 }
1417
1418 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1419 {
1420 /* SmartMIPS not implemented */
1421 /* 1k pages not implemented */
1422 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1423 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1424 compute_hflags(env);
1425 restore_pamask(env);
1426 }
1427
1428 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
1429 {
1430 CPUState *cs = CPU(mips_env_get_cpu(env));
1431
1432 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
1433 tlb_flush(cs);
1434 }
1435
1436 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
1437 {
1438 CPUState *cs = CPU(mips_env_get_cpu(env));
1439
1440 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
1441 tlb_flush(cs);
1442 }
1443
1444 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
1445 {
1446 CPUState *cs = CPU(mips_env_get_cpu(env));
1447
1448 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
1449 tlb_flush(cs);
1450 }
1451
1452 void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
1453 {
1454 #if defined(TARGET_MIPS64)
1455 uint64_t mask = 0x3F3FFFFFFFULL;
1456 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
1457 uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
1458
1459 if ((env->insn_flags & ISA_MIPS32R6)) {
1460 if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
1461 mask &= ~(0x3FULL << CP0PF_BDI);
1462 }
1463 if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) {
1464 mask &= ~(0x3FULL << CP0PF_GDI);
1465 }
1466 if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) {
1467 mask &= ~(0x3FULL << CP0PF_UDI);
1468 }
1469 if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) {
1470 mask &= ~(0x3FULL << CP0PF_MDI);
1471 }
1472 if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) {
1473 mask &= ~(0x3FULL << CP0PF_PTI);
1474 }
1475 }
1476 env->CP0_PWField = arg1 & mask;
1477
1478 if ((new_ptei >= 32) ||
1479 ((env->insn_flags & ISA_MIPS32R6) &&
1480 (new_ptei == 0 || new_ptei == 1))) {
1481 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
1482 (old_ptei << CP0PF_PTEI);
1483 }
1484 #else
1485 uint32_t mask = 0x3FFFFFFF;
1486 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
1487 uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
1488
1489 if ((env->insn_flags & ISA_MIPS32R6)) {
1490 if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
1491 mask &= ~(0x3F << CP0PF_GDW);
1492 }
1493 if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) {
1494 mask &= ~(0x3F << CP0PF_UDW);
1495 }
1496 if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) {
1497 mask &= ~(0x3F << CP0PF_MDW);
1498 }
1499 if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) {
1500 mask &= ~(0x3F << CP0PF_PTW);
1501 }
1502 }
1503 env->CP0_PWField = arg1 & mask;
1504
1505 if ((new_ptew >= 32) ||
1506 ((env->insn_flags & ISA_MIPS32R6) &&
1507 (new_ptew == 0 || new_ptew == 1))) {
1508 env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
1509 (old_ptew << CP0PF_PTEW);
1510 }
1511 #endif
1512 }
1513
1514 void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
1515 {
1516 #if defined(TARGET_MIPS64)
1517 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
1518 #else
1519 env->CP0_PWSize = arg1 & 0x3FFFFFFF;
1520 #endif
1521 }
1522
1523 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1524 {
1525 if (env->insn_flags & ISA_MIPS32R6) {
1526 if (arg1 < env->tlb->nb_tlb) {
1527 env->CP0_Wired = arg1;
1528 }
1529 } else {
1530 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1531 }
1532 }
1533
1534 void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
1535 {
1536 #if defined(TARGET_MIPS64)
1537 /* PWEn = 0. Hardware page table walking is not implemented. */
1538 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
1539 #else
1540 env->CP0_PWCtl = (arg1 & 0x800000FF);
1541 #endif
1542 }
1543
1544 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1545 {
1546 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1547 }
1548
1549 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1550 {
1551 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1552 }
1553
1554 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1555 {
1556 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1557 }
1558
1559 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1560 {
1561 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1562 }
1563
1564 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1565 {
1566 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1567 }
1568
1569 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1570 {
1571 uint32_t mask = 0x0000000F;
1572
1573 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1574 (env->insn_flags & ISA_MIPS32R6)) {
1575 mask |= (1 << 4);
1576 }
1577 if (env->insn_flags & ISA_MIPS32R6) {
1578 mask |= (1 << 5);
1579 }
1580 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1581 mask |= (1 << 29);
1582
1583 if (arg1 & (1 << 29)) {
1584 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1585 } else {
1586 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1587 }
1588 }
1589
1590 env->CP0_HWREna = arg1 & mask;
1591 }
1592
1593 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1594 {
1595 cpu_mips_store_count(env, arg1);
1596 }
1597
1598 void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
1599 {
1600 uint32_t target = arg1 & 0x3f;
1601 if (target <= 1) {
1602 env->CP0_SAARI = target;
1603 }
1604 }
1605
1606 void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
1607 {
1608 uint32_t target = env->CP0_SAARI & 0x3f;
1609 if (target < 2) {
1610 env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
1611 switch (target) {
1612 case 0:
1613 if (env->itu) {
1614 itc_reconfigure(env->itu);
1615 }
1616 break;
1617 }
1618 }
1619 }
1620
1621 void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
1622 {
1623 uint32_t target = env->CP0_SAARI & 0x3f;
1624 if (target < 2) {
1625 env->CP0_SAAR[target] =
1626 (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
1627 (env->CP0_SAAR[target] & 0x00000000ffffffffULL);
1628 switch (target) {
1629 case 0:
1630 if (env->itu) {
1631 itc_reconfigure(env->itu);
1632 }
1633 break;
1634 }
1635 }
1636 }
1637
1638 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1639 {
1640 target_ulong old, val, mask;
1641 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1642 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1643 mask |= 1 << CP0EnHi_EHINV;
1644 }
1645
1646 /* 1k pages not implemented */
1647 #if defined(TARGET_MIPS64)
1648 if (env->insn_flags & ISA_MIPS32R6) {
1649 int entryhi_r = extract64(arg1, 62, 2);
1650 int config0_at = extract32(env->CP0_Config0, 13, 2);
1651 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1652 if ((entryhi_r == 2) ||
1653 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1654 /* skip EntryHi.R field if new value is reserved */
1655 mask &= ~(0x3ull << 62);
1656 }
1657 }
1658 mask &= env->SEGMask;
1659 #endif
1660 old = env->CP0_EntryHi;
1661 val = (arg1 & mask) | (old & ~mask);
1662 env->CP0_EntryHi = val;
1663 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1664 sync_c0_entryhi(env, env->current_tc);
1665 }
1666 /* If the ASID changes, flush qemu's TLB. */
1667 if ((old & env->CP0_EntryHi_ASID_mask) !=
1668 (val & env->CP0_EntryHi_ASID_mask)) {
1669 tlb_flush(CPU(mips_env_get_cpu(env)));
1670 }
1671 }
1672
1673 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1674 {
1675 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1676 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1677
1678 other->CP0_EntryHi = arg1;
1679 sync_c0_entryhi(other, other_tc);
1680 }
1681
1682 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1683 {
1684 cpu_mips_store_compare(env, arg1);
1685 }
1686
1687 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1688 {
1689 MIPSCPU *cpu = mips_env_get_cpu(env);
1690 uint32_t val, old;
1691
1692 old = env->CP0_Status;
1693 cpu_mips_store_status(env, arg1);
1694 val = env->CP0_Status;
1695
1696 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1697 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1698 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1699 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1700 env->CP0_Cause);
1701 switch (cpu_mmu_index(env, false)) {
1702 case 3:
1703 qemu_log(", ERL\n");
1704 break;
1705 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1706 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1707 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1708 default:
1709 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1710 break;
1711 }
1712 }
1713 }
1714
1715 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1716 {
1717 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1718 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1719 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1720
1721 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1722 sync_c0_status(env, other, other_tc);
1723 }
1724
1725 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1726 {
1727 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1728 }
1729
1730 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1731 {
1732 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1733 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1734 }
1735
1736 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1737 {
1738 cpu_mips_store_cause(env, arg1);
1739 }
1740
1741 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1742 {
1743 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1744 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1745
1746 cpu_mips_store_cause(other, arg1);
1747 }
1748
1749 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1750 {
1751 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1752 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1753
1754 return other->CP0_EPC;
1755 }
1756
1757 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1758 {
1759 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1760 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1761
1762 return other->CP0_EBase;
1763 }
1764
1765 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1766 {
1767 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1768 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1769 mask |= ~0x3FFFFFFF;
1770 }
1771 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask);
1772 }
1773
1774 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1775 {
1776 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1777 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1778 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1779 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1780 mask |= ~0x3FFFFFFF;
1781 }
1782 other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask);
1783 }
1784
1785 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1786 {
1787 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1788 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1789
1790 switch (idx) {
1791 case 0: return other->CP0_Config0;
1792 case 1: return other->CP0_Config1;
1793 case 2: return other->CP0_Config2;
1794 case 3: return other->CP0_Config3;
1795 /* 4 and 5 are reserved. */
1796 case 6: return other->CP0_Config6;
1797 case 7: return other->CP0_Config7;
1798 default:
1799 break;
1800 }
1801 return 0;
1802 }
1803
1804 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1805 {
1806 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1807 }
1808
1809 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1810 {
1811 /* tertiary/secondary caches not implemented */
1812 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1813 }
1814
1815 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1816 {
1817 if (env->insn_flags & ASE_MICROMIPS) {
1818 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1819 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1820 }
1821 }
1822
1823 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1824 {
1825 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1826 (arg1 & env->CP0_Config4_rw_bitmask);
1827 }
1828
1829 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1830 {
1831 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1832 (arg1 & env->CP0_Config5_rw_bitmask);
1833 compute_hflags(env);
1834 }
1835
1836 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1837 {
1838 target_long mask = env->CP0_LLAddr_rw_bitmask;
1839 arg1 = arg1 << env->CP0_LLAddr_shift;
1840 env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask);
1841 }
1842
1843 #define MTC0_MAAR_MASK(env) \
1844 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1845
1846 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1847 {
1848 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1849 }
1850
1851 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1852 {
1853 env->CP0_MAAR[env->CP0_MAARI] =
1854 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1855 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1856 }
1857
1858 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1859 {
1860 int index = arg1 & 0x3f;
1861 if (index == 0x3f) {
1862 /* Software may write all ones to INDEX to determine the
1863 maximum value supported. */
1864 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1865 } else if (index < MIPS_MAAR_MAX) {
1866 env->CP0_MAARI = index;
1867 }
1868 /* Other than the all ones, if the
1869 value written is not supported, then INDEX is unchanged
1870 from its previous value. */
1871 }
1872
1873 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1874 {
1875 /* Watch exceptions for instructions, data loads, data stores
1876 not implemented. */
1877 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1878 }
1879
1880 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1881 {
1882 int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1883 env->CP0_WatchHi[sel] = arg1 & mask;
1884 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1885 }
1886
1887 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1888 {
1889 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1890 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1891 }
1892
1893 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1894 {
1895 env->CP0_Framemask = arg1; /* XXX */
1896 }
1897
1898 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1899 {
1900 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1901 if (arg1 & (1 << CP0DB_DM))
1902 env->hflags |= MIPS_HFLAG_DM;
1903 else
1904 env->hflags &= ~MIPS_HFLAG_DM;
1905 }
1906
1907 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1908 {
1909 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1910 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1911 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1912
1913 /* XXX: Might be wrong, check with EJTAG spec. */
1914 if (other_tc == other->current_tc)
1915 other->active_tc.CP0_Debug_tcstatus = val;
1916 else
1917 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1918 other->CP0_Debug = (other->CP0_Debug &
1919 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1920 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1921 }
1922
1923 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1924 {
1925 env->CP0_Performance0 = arg1 & 0x000007ff;
1926 }
1927
1928 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1929 {
1930 int32_t wst = arg1 & (1 << CP0EC_WST);
1931 int32_t spr = arg1 & (1 << CP0EC_SPR);
1932 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1933
1934 env->CP0_ErrCtl = wst | spr | itc;
1935
1936 if (itc && !wst && !spr) {
1937 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1938 } else {
1939 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1940 }
1941 }
1942
1943 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1944 {
1945 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1946 /* If CACHE instruction is configured for ITC tags then make all
1947 CP0.TagLo bits writable. The actual write to ITC Configuration
1948 Tag will take care of the read-only bits. */
1949 env->CP0_TagLo = arg1;
1950 } else {
1951 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1952 }
1953 }
1954
1955 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1956 {
1957 env->CP0_DataLo = arg1; /* XXX */
1958 }
1959
1960 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1961 {
1962 env->CP0_TagHi = arg1; /* XXX */
1963 }
1964
1965 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1966 {
1967 env->CP0_DataHi = arg1; /* XXX */
1968 }
1969
1970 /* MIPS MT functions */
1971 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1972 {
1973 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1974 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1975
1976 if (other_tc == other->current_tc)
1977 return other->active_tc.gpr[sel];
1978 else
1979 return other->tcs[other_tc].gpr[sel];
1980 }
1981
1982 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1983 {
1984 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1985 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1986
1987 if (other_tc == other->current_tc)
1988 return other->active_tc.LO[sel];
1989 else
1990 return other->tcs[other_tc].LO[sel];
1991 }
1992
1993 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1994 {
1995 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1996 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1997
1998 if (other_tc == other->current_tc)
1999 return other->active_tc.HI[sel];
2000 else
2001 return other->tcs[other_tc].HI[sel];
2002 }
2003
2004 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
2005 {
2006 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2007 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2008
2009 if (other_tc == other->current_tc)
2010 return other->active_tc.ACX[sel];
2011 else
2012 return other->tcs[other_tc].ACX[sel];
2013 }
2014
2015 target_ulong helper_mftdsp(CPUMIPSState *env)
2016 {
2017 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2018 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2019
2020 if (other_tc == other->current_tc)
2021 return other->active_tc.DSPControl;
2022 else
2023 return other->tcs[other_tc].DSPControl;
2024 }
2025
2026 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2027 {
2028 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2029 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2030
2031 if (other_tc == other->current_tc)
2032 other->active_tc.gpr[sel] = arg1;
2033 else
2034 other->tcs[other_tc].gpr[sel] = arg1;
2035 }
2036
2037 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2038 {
2039 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2040 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2041
2042 if (other_tc == other->current_tc)
2043 other->active_tc.LO[sel] = arg1;
2044 else
2045 other->tcs[other_tc].LO[sel] = arg1;
2046 }
2047
2048 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2049 {
2050 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2051 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2052
2053 if (other_tc == other->current_tc)
2054 other->active_tc.HI[sel] = arg1;
2055 else
2056 other->tcs[other_tc].HI[sel] = arg1;
2057 }
2058
2059 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2060 {
2061 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2062 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2063
2064 if (other_tc == other->current_tc)
2065 other->active_tc.ACX[sel] = arg1;
2066 else
2067 other->tcs[other_tc].ACX[sel] = arg1;
2068 }
2069
2070 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
2071 {
2072 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2073 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2074
2075 if (other_tc == other->current_tc)
2076 other->active_tc.DSPControl = arg1;
2077 else
2078 other->tcs[other_tc].DSPControl = arg1;
2079 }
2080
2081 /* MIPS MT functions */
2082 target_ulong helper_dmt(void)
2083 {
2084 // TODO
2085 return 0;
2086 }
2087
2088 target_ulong helper_emt(void)
2089 {
2090 // TODO
2091 return 0;
2092 }
2093
2094 target_ulong helper_dvpe(CPUMIPSState *env)
2095 {
2096 CPUState *other_cs = first_cpu;
2097 target_ulong prev = env->mvp->CP0_MVPControl;
2098
2099 CPU_FOREACH(other_cs) {
2100 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2101 /* Turn off all VPEs except the one executing the dvpe. */
2102 if (&other_cpu->env != env) {
2103 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
2104 mips_vpe_sleep(other_cpu);
2105 }
2106 }
2107 return prev;
2108 }
2109
2110 target_ulong helper_evpe(CPUMIPSState *env)
2111 {
2112 CPUState *other_cs = first_cpu;
2113 target_ulong prev = env->mvp->CP0_MVPControl;
2114
2115 CPU_FOREACH(other_cs) {
2116 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2117
2118 if (&other_cpu->env != env
2119 /* If the VPE is WFI, don't disturb its sleep. */
2120 && !mips_vpe_is_wfi(other_cpu)) {
2121 /* Enable the VPE. */
2122 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
2123 mips_vpe_wake(other_cpu); /* And wake it up. */
2124 }
2125 }
2126 return prev;
2127 }
2128 #endif /* !CONFIG_USER_ONLY */
2129
2130 void helper_fork(target_ulong arg1, target_ulong arg2)
2131 {
2132 // arg1 = rt, arg2 = rs
2133 // TODO: store to TC register
2134 }
2135
2136 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
2137 {
2138 target_long arg1 = arg;
2139
2140 if (arg1 < 0) {
2141 /* No scheduling policy implemented. */
2142 if (arg1 != -2) {
2143 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
2144 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
2145 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2146 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
2147 do_raise_exception(env, EXCP_THREAD, GETPC());
2148 }
2149 }
2150 } else if (arg1 == 0) {
2151 if (0 /* TODO: TC underflow */) {
2152 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2153 do_raise_exception(env, EXCP_THREAD, GETPC());
2154 } else {
2155 // TODO: Deallocate TC
2156 }
2157 } else if (arg1 > 0) {
2158 /* Yield qualifier inputs not implemented. */
2159 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2160 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
2161 do_raise_exception(env, EXCP_THREAD, GETPC());
2162 }
2163 return env->CP0_YQMask;
2164 }
2165
2166 /* R6 Multi-threading */
2167 #ifndef CONFIG_USER_ONLY
2168 target_ulong helper_dvp(CPUMIPSState *env)
2169 {
2170 CPUState *other_cs = first_cpu;
2171 target_ulong prev = env->CP0_VPControl;
2172
2173 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
2174 CPU_FOREACH(other_cs) {
2175 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2176 /* Turn off all VPs except the one executing the dvp. */
2177 if (&other_cpu->env != env) {
2178 mips_vpe_sleep(other_cpu);
2179 }
2180 }
2181 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
2182 }
2183 return prev;
2184 }
2185
2186 target_ulong helper_evp(CPUMIPSState *env)
2187 {
2188 CPUState *other_cs = first_cpu;
2189 target_ulong prev = env->CP0_VPControl;
2190
2191 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
2192 CPU_FOREACH(other_cs) {
2193 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2194 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
2195 /* If the VP is WFI, don't disturb its sleep.
2196 * Otherwise, wake it up. */
2197 mips_vpe_wake(other_cpu);
2198 }
2199 }
2200 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
2201 }
2202 return prev;
2203 }
2204 #endif /* !CONFIG_USER_ONLY */
2205
2206 #ifndef CONFIG_USER_ONLY
2207 /* TLB management */
2208 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
2209 {
2210 /* Discard entries from env->tlb[first] onwards. */
2211 while (env->tlb->tlb_in_use > first) {
2212 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
2213 }
2214 }
2215
2216 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
2217 {
2218 #if defined(TARGET_MIPS64)
2219 return extract64(entrylo, 6, 54);
2220 #else
2221 return extract64(entrylo, 6, 24) | /* PFN */
2222 (extract64(entrylo, 32, 32) << 24); /* PFNX */
2223 #endif
2224 }
2225
2226 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
2227 {
2228 r4k_tlb_t *tlb;
2229 uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
2230
2231 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
2232 tlb = &env->tlb->mmu.r4k.tlb[idx];
2233 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
2234 tlb->EHINV = 1;
2235 return;
2236 }
2237 tlb->EHINV = 0;
2238 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2239 #if defined(TARGET_MIPS64)
2240 tlb->VPN &= env->SEGMask;
2241 #endif
2242 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2243 tlb->PageMask = env->CP0_PageMask;
2244 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2245 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
2246 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
2247 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
2248 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
2249 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
2250 tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
2251 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
2252 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
2253 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
2254 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
2255 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
2256 tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
2257 }
2258
2259 void r4k_helper_tlbinv(CPUMIPSState *env)
2260 {
2261 int idx;
2262 r4k_tlb_t *tlb;
2263 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2264
2265 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2266 tlb = &env->tlb->mmu.r4k.tlb[idx];
2267 if (!tlb->G && tlb->ASID == ASID) {
2268 tlb->EHINV = 1;
2269 }
2270 }
2271 cpu_mips_tlb_flush(env);
2272 }
2273
2274 void r4k_helper_tlbinvf(CPUMIPSState *env)
2275 {
2276 int idx;
2277
2278 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2279 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2280 }
2281 cpu_mips_tlb_flush(env);
2282 }
2283
2284 void r4k_helper_tlbwi(CPUMIPSState *env)
2285 {
2286 r4k_tlb_t *tlb;
2287 int idx;
2288 target_ulong VPN;
2289 uint16_t ASID;
2290 bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1;
2291
2292 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2293 tlb = &env->tlb->mmu.r4k.tlb[idx];
2294 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2295 #if defined(TARGET_MIPS64)
2296 VPN &= env->SEGMask;
2297 #endif
2298 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2299 EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0;
2300 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2301 V0 = (env->CP0_EntryLo0 & 2) != 0;
2302 D0 = (env->CP0_EntryLo0 & 4) != 0;
2303 XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1;
2304 RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1;
2305 V1 = (env->CP0_EntryLo1 & 2) != 0;
2306 D1 = (env->CP0_EntryLo1 & 4) != 0;
2307 XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1;
2308 RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1;
2309
2310 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2311 permissions on the current entry. */
2312 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2313 (!tlb->EHINV && EHINV) ||
2314 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2315 (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) ||
2316 (tlb->V1 && !V1) || (tlb->D1 && !D1) ||
2317 (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) {
2318 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2319 }
2320
2321 r4k_invalidate_tlb(env, idx, 0);
2322 r4k_fill_tlb(env, idx);
2323 }
2324
2325 void r4k_helper_tlbwr(CPUMIPSState *env)
2326 {
2327 int r = cpu_mips_get_random(env);
2328
2329 r4k_invalidate_tlb(env, r, 1);
2330 r4k_fill_tlb(env, r);
2331 }
2332
2333 void r4k_helper_tlbp(CPUMIPSState *env)
2334 {
2335 r4k_tlb_t *tlb;
2336 target_ulong mask;
2337 target_ulong tag;
2338 target_ulong VPN;
2339 uint16_t ASID;
2340 int i;
2341
2342 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2343 for (i = 0; i < env->tlb->nb_tlb; i++) {
2344 tlb = &env->tlb->mmu.r4k.tlb[i];
2345 /* 1k pages are not supported. */
2346 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2347 tag = env->CP0_EntryHi & ~mask;
2348 VPN = tlb->VPN & ~mask;
2349 #if defined(TARGET_MIPS64)
2350 tag &= env->SEGMask;
2351 #endif
2352 /* Check ASID, virtual page number & size */
2353 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2354 /* TLB match */
2355 env->CP0_Index = i;
2356 break;
2357 }
2358 }
2359 if (i == env->tlb->nb_tlb) {
2360 /* No match. Discard any shadow entries, if any of them match. */
2361 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2362 tlb = &env->tlb->mmu.r4k.tlb[i];
2363 /* 1k pages are not supported. */
2364 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2365 tag = env->CP0_EntryHi & ~mask;
2366 VPN = tlb->VPN & ~mask;
2367 #if defined(TARGET_MIPS64)
2368 tag &= env->SEGMask;
2369 #endif
2370 /* Check ASID, virtual page number & size */
2371 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2372 r4k_mips_tlb_flush_extra (env, i);
2373 break;
2374 }
2375 }
2376
2377 env->CP0_Index |= 0x80000000;
2378 }
2379 }
2380
2381 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2382 {
2383 #if defined(TARGET_MIPS64)
2384 return tlb_pfn << 6;
2385 #else
2386 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2387 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2388 #endif
2389 }
2390
2391 void r4k_helper_tlbr(CPUMIPSState *env)
2392 {
2393 r4k_tlb_t *tlb;
2394 uint16_t ASID;
2395 int idx;
2396
2397 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2398 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2399 tlb = &env->tlb->mmu.r4k.tlb[idx];
2400
2401 /* If this will change the current ASID, flush qemu's TLB. */
2402 if (ASID != tlb->ASID)
2403 cpu_mips_tlb_flush(env);
2404
2405 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2406
2407 if (tlb->EHINV) {
2408 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2409 env->CP0_PageMask = 0;
2410 env->CP0_EntryLo0 = 0;
2411 env->CP0_EntryLo1 = 0;
2412 } else {
2413 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2414 env->CP0_PageMask = tlb->PageMask;
2415 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2416 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2417 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2418 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2419 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2420 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2421 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2422 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2423 }
2424 }
2425
2426 void helper_tlbwi(CPUMIPSState *env)
2427 {
2428 env->tlb->helper_tlbwi(env);
2429 }
2430
2431 void helper_tlbwr(CPUMIPSState *env)
2432 {
2433 env->tlb->helper_tlbwr(env);
2434 }
2435
2436 void helper_tlbp(CPUMIPSState *env)
2437 {
2438 env->tlb->helper_tlbp(env);
2439 }
2440
2441 void helper_tlbr(CPUMIPSState *env)
2442 {
2443 env->tlb->helper_tlbr(env);
2444 }
2445
2446 void helper_tlbinv(CPUMIPSState *env)
2447 {
2448 env->tlb->helper_tlbinv(env);
2449 }
2450
2451 void helper_tlbinvf(CPUMIPSState *env)
2452 {
2453 env->tlb->helper_tlbinvf(env);
2454 }
2455
2456 /* Specials */
2457 target_ulong helper_di(CPUMIPSState *env)
2458 {
2459 target_ulong t0 = env->CP0_Status;
2460
2461 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2462 return t0;
2463 }
2464
2465 target_ulong helper_ei(CPUMIPSState *env)
2466 {
2467 target_ulong t0 = env->CP0_Status;
2468
2469 env->CP0_Status = t0 | (1 << CP0St_IE);
2470 return t0;
2471 }
2472
2473 static void debug_pre_eret(CPUMIPSState *env)
2474 {
2475 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2476 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2477 env->active_tc.PC, env->CP0_EPC);
2478 if (env->CP0_Status & (1 << CP0St_ERL))
2479 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2480 if (env->hflags & MIPS_HFLAG_DM)
2481 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2482 qemu_log("\n");
2483 }
2484 }
2485
2486 static void debug_post_eret(CPUMIPSState *env)
2487 {
2488 MIPSCPU *cpu = mips_env_get_cpu(env);
2489
2490 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2491 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2492 env->active_tc.PC, env->CP0_EPC);
2493 if (env->CP0_Status & (1 << CP0St_ERL))
2494 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2495 if (env->hflags & MIPS_HFLAG_DM)
2496 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2497 switch (cpu_mmu_index(env, false)) {
2498 case 3:
2499 qemu_log(", ERL\n");
2500 break;
2501 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2502 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2503 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2504 default:
2505 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2506 break;
2507 }
2508 }
2509 }
2510
2511 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2512 {
2513 env->active_tc.PC = error_pc & ~(target_ulong)1;
2514 if (error_pc & 1) {
2515 env->hflags |= MIPS_HFLAG_M16;
2516 } else {
2517 env->hflags &= ~(MIPS_HFLAG_M16);
2518 }
2519 }
2520
2521 static inline void exception_return(CPUMIPSState *env)
2522 {
2523 debug_pre_eret(env);
2524 if (env->CP0_Status & (1 << CP0St_ERL)) {
2525 set_pc(env, env->CP0_ErrorEPC);
2526 env->CP0_Status &= ~(1 << CP0St_ERL);
2527 } else {
2528 set_pc(env, env->CP0_EPC);
2529 env->CP0_Status &= ~(1 << CP0St_EXL);
2530 }
2531 compute_hflags(env);
2532 debug_post_eret(env);
2533 }
2534
2535 void helper_eret(CPUMIPSState *env)
2536 {
2537 exception_return(env);
2538 env->CP0_LLAddr = 1;
2539 env->lladdr = 1;
2540 }
2541
2542 void helper_eretnc(CPUMIPSState *env)
2543 {
2544 exception_return(env);
2545 }
2546
2547 void helper_deret(CPUMIPSState *env)
2548 {
2549 debug_pre_eret(env);
2550
2551 env->hflags &= ~MIPS_HFLAG_DM;
2552 compute_hflags(env);
2553
2554 set_pc(env, env->CP0_DEPC);
2555
2556 debug_post_eret(env);
2557 }
2558 #endif /* !CONFIG_USER_ONLY */
2559
2560 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
2561 {
2562 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2563 return;
2564 }
2565 do_raise_exception(env, EXCP_RI, pc);
2566 }
2567
2568 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2569 {
2570 check_hwrena(env, 0, GETPC());
2571 return env->CP0_EBase & 0x3ff;
2572 }
2573
2574 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2575 {
2576 check_hwrena(env, 1, GETPC());
2577 return env->SYNCI_Step;
2578 }
2579
2580 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2581 {
2582 check_hwrena(env, 2, GETPC());
2583 #ifdef CONFIG_USER_ONLY
2584 return env->CP0_Count;
2585 #else
2586 return (int32_t)cpu_mips_get_count(env);
2587 #endif
2588 }
2589
2590 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2591 {
2592 check_hwrena(env, 3, GETPC());
2593 return env->CCRes;
2594 }
2595
2596 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2597 {
2598 check_hwrena(env, 4, GETPC());
2599 return env->CP0_Performance0;
2600 }
2601
2602 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2603 {
2604 check_hwrena(env, 5, GETPC());
2605 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2606 }
2607
2608 void helper_pmon(CPUMIPSState *env, int function)
2609 {
2610 function /= 2;
2611 switch (function) {
2612 case 2: /* TODO: char inbyte(int waitflag); */
2613 if (env->active_tc.gpr[4] == 0)
2614 env->active_tc.gpr[2] = -1;
2615 /* Fall through */
2616 case 11: /* TODO: char inbyte (void); */
2617 env->active_tc.gpr[2] = -1;
2618 break;
2619 case 3:
2620 case 12:
2621 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2622 break;
2623 case 17:
2624 break;
2625 case 158:
2626 {
2627 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2628 printf("%s", fmt);
2629 }
2630 break;
2631 }
2632 }
2633
2634 void helper_wait(CPUMIPSState *env)
2635 {
2636 CPUState *cs = CPU(mips_env_get_cpu(env));
2637
2638 cs->halted = 1;
2639 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2640 /* Last instruction in the block, PC was updated before
2641 - no need to recover PC and icount */
2642 raise_exception(env, EXCP_HLT);
2643 }
2644
2645 #if !defined(CONFIG_USER_ONLY)
2646
2647 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2648 MMUAccessType access_type,
2649 int mmu_idx, uintptr_t retaddr)
2650 {
2651 MIPSCPU *cpu = MIPS_CPU(cs);
2652 CPUMIPSState *env = &cpu->env;
2653 int error_code = 0;
2654 int excp;
2655
2656 if (!(env->hflags & MIPS_HFLAG_DM)) {
2657 env->CP0_BadVAddr = addr;
2658 }
2659
2660 if (access_type == MMU_DATA_STORE) {
2661 excp = EXCP_AdES;
2662 } else {
2663 excp = EXCP_AdEL;
2664 if (access_type == MMU_INST_FETCH) {
2665 error_code |= EXCP_INST_NOTAVAIL;
2666 }
2667 }
2668
2669 do_raise_exception_err(env, excp, error_code, retaddr);
2670 }
2671
2672 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2673 bool is_write, bool is_exec, int unused,
2674 unsigned size)
2675 {
2676 MIPSCPU *cpu = MIPS_CPU(cs);
2677 CPUMIPSState *env = &cpu->env;
2678
2679 /*
2680 * Raising an exception with KVM enabled will crash because it won't be from
2681 * the main execution loop so the longjmp won't have a matching setjmp.
2682 * Until we can trigger a bus error exception through KVM lets just ignore
2683 * the access.
2684 */
2685 if (kvm_enabled()) {
2686 return;
2687 }
2688
2689 if (is_exec) {
2690 raise_exception(env, EXCP_IBE);
2691 } else {
2692 raise_exception(env, EXCP_DBE);
2693 }
2694 }
2695 #endif /* !CONFIG_USER_ONLY */
2696
2697 /* Complex FPU operations which may need stack space. */
2698
2699 #define FLOAT_TWO32 make_float32(1 << 30)
2700 #define FLOAT_TWO64 make_float64(1ULL << 62)
2701
2702 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2703 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2704
2705 /* convert MIPS rounding mode in FCR31 to IEEE library */
2706 unsigned int ieee_rm[] = {
2707 float_round_nearest_even,
2708 float_round_to_zero,
2709 float_round_up,
2710 float_round_down
2711 };
2712
2713 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2714 {
2715 target_ulong arg1 = 0;
2716
2717 switch (reg) {
2718 case 0:
2719 arg1 = (int32_t)env->active_fpu.fcr0;
2720 break;
2721 case 1:
2722 /* UFR Support - Read Status FR */
2723 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2724 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2725 arg1 = (int32_t)
2726 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2727 } else {
2728 do_raise_exception(env, EXCP_RI, GETPC());
2729 }
2730 }
2731 break;
2732 case 5:
2733 /* FRE Support - read Config5.FRE bit */
2734 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2735 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2736 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2737 } else {
2738 helper_raise_exception(env, EXCP_RI);
2739 }
2740 }
2741 break;
2742 case 25:
2743 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2744 break;
2745 case 26:
2746 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2747 break;
2748 case 28:
2749 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2750 break;
2751 default:
2752 arg1 = (int32_t)env->active_fpu.fcr31;
2753 break;
2754 }
2755
2756 return arg1;
2757 }
2758
2759 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2760 {
2761 switch (fs) {
2762 case 1:
2763 /* UFR Alias - Reset Status FR */
2764 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2765 return;
2766 }
2767 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2768 env->CP0_Status &= ~(1 << CP0St_FR);
2769 compute_hflags(env);
2770 } else {
2771 do_raise_exception(env, EXCP_RI, GETPC());
2772 }
2773 break;
2774 case 4:
2775 /* UNFR Alias - Set Status FR */
2776 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2777 return;
2778 }
2779 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2780 env->CP0_Status |= (1 << CP0St_FR);
2781 compute_hflags(env);
2782 } else {
2783 do_raise_exception(env, EXCP_RI, GETPC());
2784 }
2785 break;
2786 case 5:
2787 /* FRE Support - clear Config5.FRE bit */
2788 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2789 return;
2790 }
2791 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2792 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2793 compute_hflags(env);
2794 } else {
2795 helper_raise_exception(env, EXCP_RI);
2796 }
2797 break;
2798 case 6:
2799 /* FRE Support - set Config5.FRE bit */
2800 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2801 return;
2802 }
2803 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2804 env->CP0_Config5 |= (1 << CP0C5_FRE);
2805 compute_hflags(env);
2806 } else {
2807 helper_raise_exception(env, EXCP_RI);
2808 }
2809 break;
2810 case 25:
2811 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2812 return;
2813 }
2814 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2815 ((arg1 & 0x1) << 23);
2816 break;
2817 case 26:
2818 if (arg1 & 0x007c0000)
2819 return;
2820 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2821 break;
2822 case 28:
2823 if (arg1 & 0x007c0000)
2824 return;
2825 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2826 ((arg1 & 0x4) << 22);
2827 break;
2828 case 31:
2829 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
2830 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
2831 break;
2832 default:
2833 if (env->insn_flags & ISA_MIPS32R6) {
2834 do_raise_exception(env, EXCP_RI, GETPC());
2835 }
2836 return;
2837 }
2838 restore_fp_status(env);
2839 set_float_exception_flags(0, &env->active_fpu.fp_status);
2840 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2841 do_raise_exception(env, EXCP_FPE, GETPC());
2842 }
2843
2844 int ieee_ex_to_mips(int xcpt)
2845 {
2846 int ret = 0;
2847 if (xcpt) {
2848 if (xcpt & float_flag_invalid) {
2849 ret |= FP_INVALID;
2850 }
2851 if (xcpt & float_flag_overflow) {
2852 ret |= FP_OVERFLOW;
2853 }
2854 if (xcpt & float_flag_underflow) {
2855 ret |= FP_UNDERFLOW;
2856 }
2857 if (xcpt & float_flag_divbyzero) {
2858 ret |= FP_DIV0;
2859 }
2860 if (xcpt & float_flag_inexact) {
2861 ret |= FP_INEXACT;
2862 }
2863 }
2864 return ret;
2865 }
2866
2867 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2868 {
2869 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2870
2871 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2872
2873 if (tmp) {
2874 set_float_exception_flags(0, &env->active_fpu.fp_status);
2875
2876 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2877 do_raise_exception(env, EXCP_FPE, pc);
2878 } else {
2879 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2880 }
2881 }
2882 }
2883
2884 /* Float support.
2885 Single precition routines have a "s" suffix, double precision a
2886 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2887 paired single lower "pl", paired single upper "pu". */
2888
2889 /* unary operations, modifying fp status */
2890 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2891 {
2892 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2893 update_fcr31(env, GETPC());
2894 return fdt0;
2895 }
2896
2897 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2898 {
2899 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2900 update_fcr31(env, GETPC());
2901 return fst0;
2902 }
2903
2904 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2905 {
2906 uint64_t fdt2;
2907
2908 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2909 update_fcr31(env, GETPC());
2910 return fdt2;
2911 }
2912
2913 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2914 {
2915 uint64_t fdt2;
2916
2917 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2918 update_fcr31(env, GETPC());
2919 return fdt2;
2920 }
2921
2922 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2923 {
2924 uint64_t fdt2;
2925
2926 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2927 update_fcr31(env, GETPC());
2928 return fdt2;
2929 }
2930
2931 uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
2932 {
2933 uint64_t dt2;
2934
2935 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2936 if (get_float_exception_flags(&env->active_fpu.fp_status)
2937 & (float_flag_invalid | float_flag_overflow)) {
2938 dt2 = FP_TO_INT64_OVERFLOW;
2939 }
2940 update_fcr31(env, GETPC());
2941 return dt2;
2942 }
2943
2944 uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
2945 {
2946 uint64_t dt2;
2947
2948 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2949 if (get_float_exception_flags(&env->active_fpu.fp_status)
2950 & (float_flag_invalid | float_flag_overflow)) {
2951 dt2 = FP_TO_INT64_OVERFLOW;
2952 }
2953 update_fcr31(env, GETPC());
2954 return dt2;
2955 }
2956
2957 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2958 {
2959 uint32_t fst2;
2960 uint32_t fsth2;
2961
2962 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2963 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2964 update_fcr31(env, GETPC());
2965 return ((uint64_t)fsth2 << 32) | fst2;
2966 }
2967
2968 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2969 {
2970 uint32_t wt2;
2971 uint32_t wth2;
2972 int excp, excph;
2973
2974 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2975 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2976 if (excp & (float_flag_overflow | float_flag_invalid)) {
2977 wt2 = FP_TO_INT32_OVERFLOW;
2978 }
2979
2980 set_float_exception_flags(0, &env->active_fpu.fp_status);
2981 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2982 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2983 if (excph & (float_flag_overflow | float_flag_invalid)) {
2984 wth2 = FP_TO_INT32_OVERFLOW;
2985 }
2986
2987 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2988 update_fcr31(env, GETPC());
2989
2990 return ((uint64_t)wth2 << 32) | wt2;
2991 }
2992
2993 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2994 {
2995 uint32_t fst2;
2996
2997 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2998 update_fcr31(env, GETPC());
2999 return fst2;
3000 }
3001
3002 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
3003 {
3004 uint32_t fst2;
3005
3006 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
3007 update_fcr31(env, GETPC());
3008 return fst2;
3009 }
3010
3011 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
3012 {
3013 uint32_t fst2;
3014
3015 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
3016 update_fcr31(env, GETPC());
3017 return fst2;
3018 }
3019
3020 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
3021 {
3022 uint32_t wt2;
3023
3024 wt2 = wt0;
3025 update_fcr31(env, GETPC());
3026 return wt2;
3027 }
3028
3029 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
3030 {
3031 uint32_t wt2;
3032
3033 wt2 = wth0;
3034 update_fcr31(env, GETPC());
3035 return wt2;
3036 }
3037
3038 uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
3039 {
3040 uint32_t wt2;
3041
3042 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3043 if (get_float_exception_flags(&env->active_fpu.fp_status)
3044 & (float_flag_invalid | float_flag_overflow)) {
3045 wt2 = FP_TO_INT32_OVERFLOW;
3046 }
3047 update_fcr31(env, GETPC());
3048 return wt2;
3049 }
3050
3051 uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
3052 {
3053 uint32_t wt2;
3054
3055 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3056 if (get_float_exception_flags(&env->active_fpu.fp_status)
3057 & (float_flag_invalid | float_flag_overflow)) {
3058 wt2 = FP_TO_INT32_OVERFLOW;
3059 }
3060 update_fcr31(env, GETPC());
3061 return wt2;
3062 }
3063
3064 uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
3065 {
3066 uint64_t dt2;
3067
3068 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3069 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3070 restore_rounding_mode(env);
3071 if (get_float_exception_flags(&env->active_fpu.fp_status)
3072 & (float_flag_invalid | float_flag_overflow)) {
3073 dt2 = FP_TO_INT64_OVERFLOW;
3074 }
3075 update_fcr31(env, GETPC());
3076 return dt2;
3077 }
3078
3079 uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
3080 {
3081 uint64_t dt2;
3082
3083 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3084 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3085 restore_rounding_mode(env);
3086 if (get_float_exception_flags(&env->active_fpu.fp_status)
3087 & (float_flag_invalid | float_flag_overflow)) {
3088 dt2 = FP_TO_INT64_OVERFLOW;
3089 }
3090 update_fcr31(env, GETPC());
3091 return dt2;
3092 }
3093
3094 uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
3095 {
3096 uint32_t wt2;
3097
3098 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3099 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3100 restore_rounding_mode(env);
3101 if (get_float_exception_flags(&env->active_fpu.fp_status)
3102 & (float_flag_invalid | float_flag_overflow)) {
3103 wt2 = FP_TO_INT32_OVERFLOW;
3104 }
3105 update_fcr31(env, GETPC());
3106 return wt2;
3107 }
3108
3109 uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
3110 {
3111 uint32_t wt2;
3112
3113 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3114 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3115 restore_rounding_mode(env);
3116 if (get_float_exception_flags(&env->active_fpu.fp_status)
3117 & (float_flag_invalid | float_flag_overflow)) {
3118 wt2 = FP_TO_INT32_OVERFLOW;
3119 }
3120 update_fcr31(env, GETPC());
3121 return wt2;
3122 }
3123
3124 uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
3125 {
3126 uint64_t dt2;
3127
3128 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3129 if (get_float_exception_flags(&env->active_fpu.fp_status)
3130 & (float_flag_invalid | float_flag_overflow)) {
3131 dt2 = FP_TO_INT64_OVERFLOW;
3132 }
3133 update_fcr31(env, GETPC());
3134 return dt2;
3135 }
3136
3137 uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
3138 {
3139 uint64_t dt2;
3140
3141 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3142 if (get_float_exception_flags(&env->active_fpu.fp_status)
3143 & (float_flag_invalid | float_flag_overflow)) {
3144 dt2 = FP_TO_INT64_OVERFLOW;
3145 }
3146 update_fcr31(env, GETPC());
3147 return dt2;
3148 }
3149
3150 uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
3151 {
3152 uint32_t wt2;
3153
3154 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3155 if (get_float_exception_flags(&env->active_fpu.fp_status)
3156 & (float_flag_invalid | float_flag_overflow)) {
3157 wt2 = FP_TO_INT32_OVERFLOW;
3158 }
3159 update_fcr31(env, GETPC());
3160 return wt2;
3161 }
3162
3163 uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
3164 {
3165 uint32_t wt2;
3166
3167 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3168 if (get_float_exception_flags(&env->active_fpu.fp_status)
3169 & (float_flag_invalid | float_flag_overflow)) {
3170 wt2 = FP_TO_INT32_OVERFLOW;
3171 }
3172 update_fcr31(env, GETPC());
3173 return wt2;
3174 }
3175
3176 uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
3177 {
3178 uint64_t dt2;
3179
3180 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3181 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3182 restore_rounding_mode(env);
3183 if (get_float_exception_flags(&env->active_fpu.fp_status)
3184 & (float_flag_invalid | float_flag_overflow)) {
3185 dt2 = FP_TO_INT64_OVERFLOW;
3186 }
3187 update_fcr31(env, GETPC());
3188 return dt2;
3189 }
3190
3191 uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
3192 {
3193 uint64_t dt2;
3194
3195 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3196 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3197 restore_rounding_mode(env);
3198 if (get_float_exception_flags(&env->active_fpu.fp_status)
3199 & (float_flag_invalid | float_flag_overflow)) {
3200 dt2 = FP_TO_INT64_OVERFLOW;
3201 }
3202 update_fcr31(env, GETPC());
3203 return dt2;
3204 }
3205
3206 uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
3207 {
3208 uint32_t wt2;
3209
3210 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3211 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3212 restore_rounding_mode(env);
3213 if (get_float_exception_flags(&env->active_fpu.fp_status)
3214 & (float_flag_invalid | float_flag_overflow)) {
3215 wt2 = FP_TO_INT32_OVERFLOW;
3216 }
3217 update_fcr31(env, GETPC());
3218 return wt2;
3219 }
3220
3221 uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
3222 {
3223 uint32_t wt2;
3224
3225 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3226 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3227 restore_rounding_mode(env);
3228 if (get_float_exception_flags(&env->active_fpu.fp_status)
3229 & (float_flag_invalid | float_flag_overflow)) {
3230 wt2 = FP_TO_INT32_OVERFLOW;
3231 }
3232 update_fcr31(env, GETPC());
3233 return wt2;
3234 }
3235
3236 uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
3237 {
3238 uint64_t dt2;
3239
3240 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3241 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3242 restore_rounding_mode(env);
3243 if (get_float_exception_flags(&env->active_fpu.fp_status)
3244 & (float_flag_invalid | float_flag_overflow)) {
3245 dt2 = FP_TO_INT64_OVERFLOW;
3246 }
3247 update_fcr31(env, GETPC());
3248 return dt2;
3249 }
3250
3251 uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
3252 {
3253 uint64_t dt2;
3254
3255 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3256 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3257 restore_rounding_mode(env);
3258 if (get_float_exception_flags(&env->active_fpu.fp_status)
3259 & (float_flag_invalid | float_flag_overflow)) {
3260 dt2 = FP_TO_INT64_OVERFLOW;
3261 }
3262 update_fcr31(env, GETPC());
3263 return dt2;
3264 }
3265
3266 uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
3267 {
3268 uint32_t wt2;
3269
3270 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3271 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3272 restore_rounding_mode(env);
3273 if (get_float_exception_flags(&env->active_fpu.fp_status)
3274 & (float_flag_invalid | float_flag_overflow)) {
3275 wt2 = FP_TO_INT32_OVERFLOW;
3276 }
3277 update_fcr31(env, GETPC());
3278 return wt2;
3279 }
3280
3281 uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
3282 {
3283 uint32_t wt2;
3284
3285 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3286 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3287 restore_rounding_mode(env);
3288 if (get_float_exception_flags(&env->active_fpu.fp_status)
3289 & (float_flag_invalid | float_flag_overflow)) {
3290 wt2 = FP_TO_INT32_OVERFLOW;
3291 }
3292 update_fcr31(env, GETPC());
3293 return wt2;
3294 }
3295
3296 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3297 {
3298 uint64_t dt2;
3299
3300 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3301 if (get_float_exception_flags(&env->active_fpu.fp_status)
3302 & float_flag_invalid) {
3303 if (float64_is_any_nan(fdt0)) {
3304 dt2 = 0;
3305 }
3306 }
3307 update_fcr31(env, GETPC());
3308 return dt2;
3309 }
3310
3311 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3312 {
3313 uint64_t dt2;
3314
3315 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3316 if (get_float_exception_flags(&env->active_fpu.fp_status)
3317 & float_flag_invalid) {
3318 if (float32_is_any_nan(fst0)) {
3319 dt2 = 0;
3320 }
3321 }
3322 update_fcr31(env, GETPC());
3323 return dt2;
3324 }
3325
3326 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3327 {
3328 uint32_t wt2;
3329
3330 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3331 if (get_float_exception_flags(&env->active_fpu.fp_status)
3332 & float_flag_invalid) {
3333 if (float64_is_any_nan(fdt0)) {
3334 wt2 = 0;
3335 }
3336 }
3337 update_fcr31(env, GETPC());
3338 return wt2;
3339 }
3340
3341 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3342 {
3343 uint32_t wt2;
3344
3345 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3346 if (get_float_exception_flags(&env->active_fpu.fp_status)
3347 & float_flag_invalid) {
3348 if (float32_is_any_nan(fst0)) {
3349 wt2 = 0;
3350 }
3351 }
3352 update_fcr31(env, GETPC());
3353 return wt2;
3354 }
3355
3356 uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3357 {
3358 uint64_t dt2;
3359
3360 set_float_rounding_mode(float_round_nearest_even,
3361 &env->active_fpu.fp_status);
3362 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3363 restore_rounding_mode(env);
3364 if (get_float_exception_flags(&env->active_fpu.fp_status)
3365 & float_flag_invalid) {
3366 if (float64_is_any_nan(fdt0)) {
3367 dt2 = 0;
3368 }
3369 }
3370 update_fcr31(env, GETPC());
3371 return dt2;
3372 }
3373
3374 uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3375 {
3376 uint64_t dt2;
3377
3378 set_float_rounding_mode(float_round_nearest_even,
3379 &env->active_fpu.fp_status);
3380 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3381 restore_rounding_mode(env);
3382 if (get_float_exception_flags(&env->active_fpu.fp_status)
3383 & float_flag_invalid) {
3384 if (float32_is_any_nan(fst0)) {
3385 dt2 = 0;
3386 }
3387 }
3388 update_fcr31(env, GETPC());
3389 return dt2;
3390 }
3391
3392 uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3393 {
3394 uint32_t wt2;
3395
3396 set_float_rounding_mode(float_round_nearest_even,
3397 &env->active_fpu.fp_status);
3398 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3399 restore_rounding_mode(env);
3400 if (get_float_exception_flags(&env->active_fpu.fp_status)
3401 & float_flag_invalid) {
3402 if (float64_is_any_nan(fdt0)) {
3403 wt2 = 0;
3404 }
3405 }
3406 update_fcr31(env, GETPC());
3407 return wt2;
3408 }
3409
3410 uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3411 {
3412 uint32_t wt2;
3413
3414 set_float_rounding_mode(float_round_nearest_even,
3415 &env->active_fpu.fp_status);
3416 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3417 restore_rounding_mode(env);
3418 if (get_float_exception_flags(&env->active_fpu.fp_status)
3419 & float_flag_invalid) {
3420 if (float32_is_any_nan(fst0)) {
3421 wt2 = 0;
3422 }
3423 }
3424 update_fcr31(env, GETPC());
3425 return wt2;
3426 }
3427
3428 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3429 {
3430 uint64_t dt2;
3431
3432 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3433 if (get_float_exception_flags(&env->active_fpu.fp_status)
3434 & float_flag_invalid) {
3435 if (float64_is_any_nan(fdt0)) {
3436 dt2 = 0;
3437 }
3438 }
3439 update_fcr31(env, GETPC());
3440 return dt2;
3441 }
3442
3443 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3444 {
3445 uint64_t dt2;
3446
3447 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3448 if (get_float_exception_flags(&env->active_fpu.fp_status)
3449 & float_flag_invalid) {
3450 if (float32_is_any_nan(fst0)) {
3451 dt2 = 0;
3452 }
3453 }
3454 update_fcr31(env, GETPC());
3455 return dt2;
3456 }
3457
3458 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3459 {
3460 uint32_t wt2;
3461
3462 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3463 if (get_float_exception_flags(&env->active_fpu.fp_status)
3464 & float_flag_invalid) {
3465 if (float64_is_any_nan(fdt0)) {
3466 wt2 = 0;
3467 }
3468 }
3469 update_fcr31(env, GETPC());
3470 return wt2;
3471 }
3472
3473 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3474 {
3475 uint32_t wt2;
3476
3477 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3478 if (get_float_exception_flags(&env->active_fpu.fp_status)
3479 & float_flag_invalid) {
3480 if (float32_is_any_nan(fst0)) {
3481 wt2 = 0;
3482 }
3483 }
3484 update_fcr31(env, GETPC());
3485 return wt2;
3486 }
3487
3488 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3489 {
3490 uint64_t dt2;
3491
3492 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3493 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3494 restore_rounding_mode(env);
3495 if (get_float_exception_flags(&env->active_fpu.fp_status)
3496 & float_flag_invalid) {
3497 if (float64_is_any_nan(fdt0)) {
3498 dt2 = 0;
3499 }
3500 }
3501 update_fcr31(env, GETPC());
3502 return dt2;
3503 }
3504
3505 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3506 {
3507 uint64_t dt2;
3508
3509 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3510 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3511 restore_rounding_mode(env);
3512 if (get_float_exception_flags(&env->active_fpu.fp_status)
3513 & float_flag_invalid) {
3514 if (float32_is_any_nan(fst0)) {
3515 dt2 = 0;
3516 }
3517 }
3518 update_fcr31(env, GETPC());
3519 return dt2;
3520 }
3521
3522 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3523 {
3524 uint32_t wt2;
3525
3526 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3527 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3528 restore_rounding_mode(env);
3529 if (get_float_exception_flags(&env->active_fpu.fp_status)
3530 & float_flag_invalid) {
3531 if (float64_is_any_nan(fdt0)) {
3532 wt2 = 0;
3533 }
3534 }
3535 update_fcr31(env, GETPC());
3536 return wt2;
3537 }
3538
3539 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3540 {
3541 uint32_t wt2;
3542
3543 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3544 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3545 restore_rounding_mode(env);
3546 if (get_float_exception_flags(&env->active_fpu.fp_status)
3547 & float_flag_invalid) {
3548 if (float32_is_any_nan(fst0)) {
3549 wt2 = 0;
3550 }
3551 }
3552 update_fcr31(env, GETPC());
3553 return wt2;
3554 }
3555
3556 uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3557 {
3558 uint64_t dt2;
3559
3560 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3561 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3562 restore_rounding_mode(env);
3563 if (get_float_exception_flags(&env->active_fpu.fp_status)
3564 & float_flag_invalid) {
3565 if (float64_is_any_nan(fdt0)) {
3566 dt2 = 0;
3567 }
3568 }
3569 update_fcr31(env, GETPC());
3570 return dt2;
3571 }
3572
3573 uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3574 {
3575 uint64_t dt2;
3576
3577 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3578 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3579 restore_rounding_mode(env);
3580 if (get_float_exception_flags(&env->active_fpu.fp_status)
3581 & float_flag_invalid) {
3582 if (float32_is_any_nan(fst0)) {
3583 dt2 = 0;
3584 }
3585 }
3586 update_fcr31(env, GETPC());
3587 return dt2;
3588 }
3589
3590 uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3591 {
3592 uint32_t wt2;
3593
3594 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3595 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3596 restore_rounding_mode(env);
3597 if (get_float_exception_flags(&env->active_fpu.fp_status)
3598 & float_flag_invalid) {
3599 if (float64_is_any_nan(fdt0)) {
3600 wt2 = 0;
3601 }
3602 }
3603 update_fcr31(env, GETPC());
3604 return wt2;
3605 }
3606
3607 uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3608 {
3609 uint32_t wt2;
3610
3611 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3612 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3613 restore_rounding_mode(env);
3614 if (get_float_exception_flags(&env->active_fpu.fp_status)
3615 & float_flag_invalid) {
3616 if (float32_is_any_nan(fst0)) {
3617 wt2 = 0;
3618 }
3619 }
3620 update_fcr31(env, GETPC());
3621 return wt2;
3622 }
3623
3624 /* unary operations, not modifying fp status */
3625 #define FLOAT_UNOP(name) \
3626 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3627 { \
3628 return float64_ ## name(fdt0); \
3629 } \
3630 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3631 { \
3632 return float32_ ## name(fst0); \
3633 } \
3634 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3635 { \
3636 uint32_t wt0; \
3637 uint32_t wth0; \
3638 \
3639 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3640 wth0 = float32_ ## name(fdt0 >> 32); \
3641 return ((uint64_t)wth0 << 32) | wt0; \
3642 }
3643 FLOAT_UNOP(abs)
3644 FLOAT_UNOP(chs)
3645 #undef FLOAT_UNOP
3646
3647 /* MIPS specific unary operations */
3648 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3649 {
3650 uint64_t fdt2;
3651
3652 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3653 update_fcr31(env, GETPC());
3654 return fdt2;
3655 }
3656
3657 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3658 {
3659 uint32_t fst2;
3660
3661 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3662 update_fcr31(env, GETPC());
3663 return fst2;
3664 }
3665
3666 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3667 {
3668 uint64_t fdt2;
3669
3670 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3671 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3672 update_fcr31(env, GETPC());
3673 return fdt2;
3674 }
3675
3676 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3677 {
3678 uint32_t fst2;
3679
3680 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3681 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3682 update_fcr31(env, GETPC());
3683 return fst2;
3684 }
3685
3686 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3687 {
3688 uint64_t fdt2;
3689
3690 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3691 update_fcr31(env, GETPC());
3692 return fdt2;
3693 }
3694
3695 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3696 {
3697 uint32_t fst2;
3698
3699 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3700 update_fcr31(env, GETPC());
3701 return fst2;
3702 }
3703
3704 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3705 {
3706 uint32_t fst2;
3707 uint32_t fsth2;
3708
3709 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3710 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3711 update_fcr31(env, GETPC());
3712 return ((uint64_t)fsth2 << 32) | fst2;
3713 }
3714
3715 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3716 {
3717 uint64_t fdt2;
3718
3719 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3720 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3721 update_fcr31(env, GETPC());
3722 return fdt2;
3723 }
3724
3725 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3726 {
3727 uint32_t fst2;
3728
3729 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3730 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3731 update_fcr31(env, GETPC());
3732 return fst2;
3733 }
3734
3735 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3736 {
3737 uint32_t fst2;
3738 uint32_t fsth2;
3739
3740 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3741 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3742 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3743 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3744 update_fcr31(env, GETPC());
3745 return ((uint64_t)fsth2 << 32) | fst2;
3746 }
3747
3748 #define FLOAT_RINT(name, bits) \
3749 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3750 uint ## bits ## _t fs) \
3751 { \
3752 uint ## bits ## _t fdret; \
3753 \
3754 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3755 update_fcr31(env, GETPC()); \
3756 return fdret; \
3757 }
3758
3759 FLOAT_RINT(rint_s, 32)
3760 FLOAT_RINT(rint_d, 64)
3761 #undef FLOAT_RINT
3762
3763 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3764 #define FLOAT_CLASS_QUIET_NAN 0x002
3765 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3766 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3767 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3768 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3769 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3770 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3771 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3772 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3773
3774 #define FLOAT_CLASS(name, bits) \
3775 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3776 float_status *status) \
3777 { \
3778 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3779 return FLOAT_CLASS_SIGNALING_NAN; \
3780 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3781 return FLOAT_CLASS_QUIET_NAN; \
3782 } else if (float ## bits ## _is_neg(arg)) { \
3783 if (float ## bits ## _is_infinity(arg)) { \
3784 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3785 } else if (float ## bits ## _is_zero(arg)) { \
3786 return FLOAT_CLASS_NEGATIVE_ZERO; \
3787 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3788 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3789 } else { \
3790 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3791 } \
3792 } else { \
3793 if (float ## bits ## _is_infinity(arg)) { \
3794 return FLOAT_CLASS_POSITIVE_INFINITY; \
3795 } else if (float ## bits ## _is_zero(arg)) { \
3796 return FLOAT_CLASS_POSITIVE_ZERO; \
3797 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3798 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3799 } else { \
3800 return FLOAT_CLASS_POSITIVE_NORMAL; \
3801 } \
3802 } \
3803 } \
3804 \
3805 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3806 uint ## bits ## _t arg) \
3807 { \
3808 return float_ ## name(arg, &env->active_fpu.fp_status); \
3809 }
3810
3811 FLOAT_CLASS(class_s, 32)
3812 FLOAT_CLASS(class_d, 64)
3813 #undef FLOAT_CLASS
3814
3815 /* binary operations */
3816 #define FLOAT_BINOP(name) \
3817 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3818 uint64_t fdt0, uint64_t fdt1) \
3819 { \
3820 uint64_t dt2; \
3821 \
3822 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3823 update_fcr31(env, GETPC()); \
3824 return dt2; \
3825 } \
3826 \
3827 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3828 uint32_t fst0, uint32_t fst1) \
3829 { \
3830 uint32_t wt2; \
3831 \
3832 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3833 update_fcr31(env, GETPC()); \
3834 return wt2; \
3835 } \
3836 \
3837 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3838 uint64_t fdt0, \
3839 uint64_t fdt1) \
3840 { \
3841 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3842 uint32_t fsth0 = fdt0 >> 32; \
3843 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3844 uint32_t fsth1 = fdt1 >> 32; \
3845 uint32_t wt2; \
3846 uint32_t wth2; \
3847 \
3848 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3849 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3850 update_fcr31(env, GETPC()); \
3851 return ((uint64_t)wth2 << 32) | wt2; \
3852 }
3853
3854 FLOAT_BINOP(add)
3855 FLOAT_BINOP(sub)
3856 FLOAT_BINOP(mul)
3857 FLOAT_BINOP(div)
3858 #undef FLOAT_BINOP
3859
3860 /* MIPS specific binary operations */
3861 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3862 {
3863 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3864 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3865 update_fcr31(env, GETPC());
3866 return fdt2;
3867 }
3868
3869 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3870 {
3871 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3872 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3873 update_fcr31(env, GETPC());
3874 return fst2;
3875 }
3876
3877 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3878 {
3879 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3880 uint32_t fsth0 = fdt0 >> 32;
3881 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3882 uint32_t fsth2 = fdt2 >> 32;
3883
3884 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3885 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3886 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3887 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3888 update_fcr31(env, GETPC());
3889 return ((uint64_t)fsth2 << 32) | fst2;
3890 }
3891
3892 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3893 {
3894 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3895 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3896 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3897 update_fcr31(env, GETPC());
3898 return fdt2;
3899 }
3900
3901 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3902 {
3903 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3904 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3905 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3906 update_fcr31(env, GETPC());
3907 return fst2;
3908 }
3909
3910 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3911 {
3912 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3913 uint32_t fsth0 = fdt0 >> 32;
3914 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3915 uint32_t fsth2 = fdt2 >> 32;
3916
3917 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3918 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3919 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3920 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3921 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3922 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3923 update_fcr31(env, GETPC());
3924 return ((uint64_t)fsth2 << 32) | fst2;
3925 }
3926
3927 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3928 {
3929 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3930 uint32_t fsth0 = fdt0 >> 32;
3931 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3932 uint32_t fsth1 = fdt1 >> 32;
3933 uint32_t fst2;
3934 uint32_t fsth2;
3935
3936 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3937 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3938 update_fcr31(env, GETPC());
3939 return ((uint64_t)fsth2 << 32) | fst2;
3940 }
3941
3942 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3943 {
3944 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3945 uint32_t fsth0 = fdt0 >> 32;
3946 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3947 uint32_t fsth1 = fdt1 >> 32;
3948 uint32_t fst2;
3949 uint32_t fsth2;
3950
3951 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3952 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3953 update_fcr31(env, GETPC());
3954 return ((uint64_t)fsth2 << 32) | fst2;
3955 }
3956
3957 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3958 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3959 uint ## bits ## _t fs, \
3960 uint ## bits ## _t ft) \
3961 { \
3962 uint ## bits ## _t fdret; \
3963 \
3964 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3965 &env->active_fpu.fp_status); \
3966 update_fcr31(env, GETPC()); \
3967 return fdret; \
3968 }
3969
3970 FLOAT_MINMAX(max_s, 32, maxnum)
3971 FLOAT_MINMAX(max_d, 64, maxnum)
3972 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3973 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3974
3975 FLOAT_MINMAX(min_s, 32, minnum)
3976 FLOAT_MINMAX(min_d, 64, minnum)
3977 FLOAT_MINMAX(mina_s, 32, minnummag)
3978 FLOAT_MINMAX(mina_d, 64, minnummag)
3979 #undef FLOAT_MINMAX
3980
3981 /* ternary operations */
3982 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3983 { \
3984 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3985 if ((flags) & float_muladd_negate_c) { \
3986 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3987 } else { \
3988 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3989 } \
3990 if ((flags) & float_muladd_negate_result) { \
3991 a = prefix##_chs(a); \
3992 } \
3993 }
3994
3995 /* FMA based operations */
3996 #define FLOAT_FMA(name, type) \
3997 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3998 uint64_t fdt0, uint64_t fdt1, \
3999 uint64_t fdt2) \
4000 { \
4001 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
4002 update_fcr31(env, GETPC()); \
4003 return fdt0; \
4004 } \
4005 \
4006 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
4007 uint32_t fst0, uint32_t fst1, \
4008 uint32_t fst2) \
4009 { \
4010 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4011 update_fcr31(env, GETPC()); \
4012 return fst0; \
4013 } \
4014 \
4015 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
4016 uint64_t fdt0, uint64_t fdt1, \
4017 uint64_t fdt2) \
4018 { \
4019 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
4020 uint32_t fsth0 = fdt0 >> 32; \
4021 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
4022 uint32_t fsth1 = fdt1 >> 32; \
4023 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
4024 uint32_t fsth2 = fdt2 >> 32; \
4025 \
4026 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4027 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
4028 update_fcr31(env, GETPC()); \
4029 return ((uint64_t)fsth0 << 32) | fst0; \
4030 }
4031 FLOAT_FMA(madd, 0)
4032 FLOAT_FMA(msub, float_muladd_negate_c)
4033 FLOAT_FMA(nmadd, float_muladd_negate_result)
4034 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
4035 #undef FLOAT_FMA
4036
4037 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
4038 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
4039 uint ## bits ## _t fs, \
4040 uint ## bits ## _t ft, \
4041 uint ## bits ## _t fd) \
4042 { \
4043 uint ## bits ## _t fdret; \
4044 \
4045 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
4046 &env->active_fpu.fp_status); \
4047 update_fcr31(env, GETPC()); \
4048 return fdret; \
4049 }
4050
4051 FLOAT_FMADDSUB(maddf_s, 32, 0)
4052 FLOAT_FMADDSUB(maddf_d, 64, 0)
4053 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
4054 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
4055 #undef FLOAT_FMADDSUB
4056
4057 /* compare operations */
4058 #define FOP_COND_D(op, cond) \
4059 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4060 uint64_t fdt1, int cc) \
4061 { \
4062 int c; \
4063 c = cond; \
4064 update_fcr31(env, GETPC()); \
4065 if (c) \
4066 SET_FP_COND(cc, env->active_fpu); \
4067 else \
4068 CLEAR_FP_COND(cc, env->active_fpu); \
4069 } \
4070 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4071 uint64_t fdt1, int cc) \
4072 { \
4073 int c; \
4074 fdt0 = float64_abs(fdt0); \
4075 fdt1 = float64_abs(fdt1); \
4076 c = cond; \
4077 update_fcr31(env, GETPC()); \
4078 if (c) \
4079 SET_FP_COND(cc, env->active_fpu); \
4080 else \
4081 CLEAR_FP_COND(cc, env->active_fpu); \
4082 }
4083
4084 /* NOTE: the comma operator will make "cond" to eval to false,
4085 * but float64_unordered_quiet() is still called. */
4086 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4087 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
4088 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4089 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4090 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4091 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4092 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4093 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4094 /* NOTE: the comma operator will make "cond" to eval to false,
4095 * but float64_unordered() is still called. */
4096 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4097 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
4098 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
4099 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
4100 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
4101 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
4102 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
4103 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
4104
4105 #define FOP_COND_S(op, cond) \
4106 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4107 uint32_t fst1, int cc) \
4108 { \
4109 int c; \
4110 c = cond; \
4111 update_fcr31(env, GETPC()); \
4112 if (c) \
4113 SET_FP_COND(cc, env->active_fpu); \
4114 else \
4115 CLEAR_FP_COND(cc, env->active_fpu); \
4116 } \
4117 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4118 uint32_t fst1, int cc) \
4119 { \
4120 int c; \
4121 fst0 = float32_abs(fst0); \
4122 fst1 = float32_abs(fst1); \
4123 c = cond; \
4124 update_fcr31(env, GETPC()); \
4125 if (c) \
4126 SET_FP_COND(cc, env->active_fpu); \
4127 else \
4128 CLEAR_FP_COND(cc, env->active_fpu); \
4129 }
4130
4131 /* NOTE: the comma operator will make "cond" to eval to false,
4132 * but float32_unordered_quiet() is still called. */
4133 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4134 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
4135 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
4136 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
4137 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
4138 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
4139 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
4140 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
4141 /* NOTE: the comma operator will make "cond" to eval to false,
4142 * but float32_unordered() is still called. */
4143 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4144 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
4145 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
4146 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
4147 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
4148 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
4149 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
4150 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
4151
4152 #define FOP_COND_PS(op, condl, condh) \
4153 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4154 uint64_t fdt1, int cc) \
4155 { \
4156 uint32_t fst0, fsth0, fst1, fsth1; \
4157 int ch, cl; \
4158 fst0 = fdt0 & 0XFFFFFFFF; \
4159 fsth0 = fdt0 >> 32; \
4160 fst1 = fdt1 & 0XFFFFFFFF; \
4161 fsth1 = fdt1 >> 32; \
4162 cl = condl; \
4163 ch = condh; \
4164 update_fcr31(env, GETPC()); \
4165 if (cl) \
4166 SET_FP_COND(cc, env->active_fpu); \
4167 else \
4168 CLEAR_FP_COND(cc, env->active_fpu); \
4169 if (ch) \
4170 SET_FP_COND(cc + 1, env->active_fpu); \
4171 else \
4172 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4173 } \
4174 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4175 uint64_t fdt1, int cc) \
4176 { \
4177 uint32_t fst0, fsth0, fst1, fsth1; \
4178 int ch, cl; \
4179 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
4180 fsth0 = float32_abs(fdt0 >> 32); \
4181 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
4182 fsth1 = float32_abs(fdt1 >> 32); \
4183 cl = condl; \
4184 ch = condh; \
4185 update_fcr31(env, GETPC()); \
4186 if (cl) \
4187 SET_FP_COND(cc, env->active_fpu); \
4188 else \
4189 CLEAR_FP_COND(cc, env->active_fpu); \
4190 if (ch) \
4191 SET_FP_COND(cc + 1, env->active_fpu); \
4192 else \
4193 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4194 }
4195
4196 /* NOTE: the comma operator will make "cond" to eval to false,
4197 * but float32_unordered_quiet() is still called. */
4198 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
4199 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
4200 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
4201 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
4202 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
4203 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4204 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
4205 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4206 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
4207 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4208 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
4209 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4210 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
4211 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4212 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
4213 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4214 /* NOTE: the comma operator will make "cond" to eval to false,
4215 * but float32_unordered() is still called. */
4216 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
4217 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
4218 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
4219 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
4220 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
4221 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
4222 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
4223 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
4224 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
4225 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
4226 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
4227 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
4228 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
4229 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
4230 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
4231 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
4232
4233 /* R6 compare operations */
4234 #define FOP_CONDN_D(op, cond) \
4235 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
4236 uint64_t fdt1) \
4237 { \
4238 uint64_t c; \
4239 c = cond; \
4240 update_fcr31(env, GETPC()); \
4241 if (c) { \
4242 return -1; \
4243 } else { \
4244 return 0; \
4245 } \
4246 }
4247
4248 /* NOTE: the comma operator will make "cond" to eval to false,
4249 * but float64_unordered_quiet() is still called. */
4250 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4251 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
4252 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4253 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4254 || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4255 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4256 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4257 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4258 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4259 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4260 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4261 /* NOTE: the comma operator will make "cond" to eval to false,
4262 * but float64_unordered() is still called. */
4263 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4264 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
4265 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4266 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4267 || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4268 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4269 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4270 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4271 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4272 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4273 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4274 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4275 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4276 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4277 || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4278 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4279 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4280 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4281 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
4282 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4283 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4284 || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4285 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4286 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4287 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4288
4289 #define FOP_CONDN_S(op, cond) \
4290 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4291 uint32_t fst1) \
4292 { \
4293 uint64_t c; \
4294 c = cond; \
4295 update_fcr31(env, GETPC()); \
4296 if (c) { \
4297 return -1; \
4298 } else { \
4299 return 0; \
4300 } \
4301 }
4302
4303 /* NOTE: the comma operator will make "cond" to eval to false,
4304 * but float32_unordered_quiet() is still called. */
4305 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4306 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
4307 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4308 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4309 || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4310 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4311 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4312 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4313 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4314 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4315 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4316 /* NOTE: the comma operator will make "cond" to eval to false,
4317 * but float32_unordered() is still called. */
4318 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4319 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
4320 FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4321 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4322 || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4323 FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4324 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4325 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4326 FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4327 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4328 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4329 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
4330 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4331 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4332 || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4333 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4334 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4335 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4336 FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
4337 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4338 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4339 || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4340 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4341 FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4342 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4343
4344 /* MSA */
4345 /* Data format min and max values */
4346 #define DF_BITS(df) (1 << ((df) + 3))
4347
4348 /* Element-by-element access macros */
4349 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4350
4351 #if !defined(CONFIG_USER_ONLY)
4352 #define MEMOP_IDX(DF) \
4353 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4354 cpu_mmu_index(env, false));
4355 #else
4356 #define MEMOP_IDX(DF)
4357 #endif
4358
4359 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
4360 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4361 target_ulong addr) \
4362 { \
4363 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4364 wr_t wx; \
4365 int i; \
4366 MEMOP_IDX(DF) \
4367 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4368 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
4369 } \
4370 memcpy(pwd, &wx, sizeof(wr_t)); \
4371 }
4372
4373 #if !defined(CONFIG_USER_ONLY)
4374 MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETPC())
4375 MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETPC())
4376 MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETPC())
4377 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETPC())
4378 #else
4379 MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
4380 MSA_LD_DF(DF_HALF, h, cpu_lduw_data)
4381 MSA_LD_DF(DF_WORD, w, cpu_ldl_data)
4382 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
4383 #endif
4384
4385 #define MSA_PAGESPAN(x) \
4386 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4387
4388 static inline void ensure_writable_pages(CPUMIPSState *env,
4389 target_ulong addr,
4390 int mmu_idx,
4391 uintptr_t retaddr)
4392 {
4393 #if !defined(CONFIG_USER_ONLY)
4394 target_ulong page_addr;
4395 if (unlikely(MSA_PAGESPAN(addr))) {
4396 /* first page */
4397 probe_write(env, addr, 0, mmu_idx, retaddr);
4398 /* second page */
4399 page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4400 probe_write(env, page_addr, 0, mmu_idx, retaddr);
4401 }
4402 #endif
4403 }
4404
4405 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
4406 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4407 target_ulong addr) \
4408 { \
4409 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4410 int mmu_idx = cpu_mmu_index(env, false); \
4411 int i; \
4412 MEMOP_IDX(DF) \
4413 ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
4414 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4415 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
4416 } \
4417 }
4418
4419 #if !defined(CONFIG_USER_ONLY)
4420 MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETPC())
4421 MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETPC())
4422 MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETPC())
4423 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETPC())
4424 #else
4425 MSA_ST_DF(DF_BYTE, b, cpu_stb_data)
4426 MSA_ST_DF(DF_HALF, h, cpu_stw_data)
4427 MSA_ST_DF(DF_WORD, w, cpu_stl_data)
4428 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
4429 #endif
4430
4431 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
4432 {
4433 #ifndef CONFIG_USER_ONLY
4434 target_ulong index = addr & 0x1fffffff;
4435 if (op == 9) {
4436 /* Index Store Tag */
4437 memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
4438 8, MEMTXATTRS_UNSPECIFIED);
4439 } else if (op == 5) {
4440 /* Index Load Tag */
4441 memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
4442 8, MEMTXATTRS_UNSPECIFIED);
4443 }
4444 #endif
4445 }
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