2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
22 #include "qemu/host-utils.h"
23 #include "exec/helper-proto.h"
24 #include "exec/exec-all.h"
25 #include "exec/cpu_ldst.h"
26 #include "sysemu/kvm.h"
28 /*****************************************************************************/
29 /* Exceptions processing helpers */
31 void helper_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
34 do_raise_exception_err(env
, exception
, error_code
, 0);
37 void helper_raise_exception(CPUMIPSState
*env
, uint32_t exception
)
39 do_raise_exception(env
, exception
, GETPC());
42 void helper_raise_exception_debug(CPUMIPSState
*env
)
44 do_raise_exception(env
, EXCP_DEBUG
, 0);
47 static void raise_exception(CPUMIPSState
*env
, uint32_t exception
)
49 do_raise_exception(env
, exception
, 0);
52 #if defined(CONFIG_USER_ONLY)
53 #define HELPER_LD(name, insn, type) \
54 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
55 int mem_idx, uintptr_t retaddr) \
57 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
60 #define HELPER_LD(name, insn, type) \
61 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
62 int mem_idx, uintptr_t retaddr) \
66 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
67 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
69 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
73 HELPER_LD(lw
, ldl
, int32_t)
74 #if defined(TARGET_MIPS64)
75 HELPER_LD(ld
, ldq
, int64_t)
79 #if defined(CONFIG_USER_ONLY)
80 #define HELPER_ST(name, insn, type) \
81 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
82 type val, int mem_idx, uintptr_t retaddr) \
84 cpu_##insn##_data_ra(env, addr, val, retaddr); \
87 #define HELPER_ST(name, insn, type) \
88 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
89 type val, int mem_idx, uintptr_t retaddr) \
93 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
94 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
96 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
100 HELPER_ST(sb
, stb
, uint8_t)
101 HELPER_ST(sw
, stl
, uint32_t)
102 #if defined(TARGET_MIPS64)
103 HELPER_ST(sd
, stq
, uint64_t)
107 /* 64 bits arithmetic for 32 bits hosts */
108 static inline uint64_t get_HILO(CPUMIPSState
*env
)
110 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) | (uint32_t)env
->active_tc
.LO
[0];
113 static inline target_ulong
set_HIT0_LO(CPUMIPSState
*env
, uint64_t HILO
)
115 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
116 return env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
119 static inline target_ulong
set_HI_LOT0(CPUMIPSState
*env
, uint64_t HILO
)
121 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
122 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
126 /* Multiplication variants of the vr54xx. */
127 target_ulong
helper_muls(CPUMIPSState
*env
, target_ulong arg1
,
130 return set_HI_LOT0(env
, 0 - ((int64_t)(int32_t)arg1
*
131 (int64_t)(int32_t)arg2
));
134 target_ulong
helper_mulsu(CPUMIPSState
*env
, target_ulong arg1
,
137 return set_HI_LOT0(env
, 0 - (uint64_t)(uint32_t)arg1
*
138 (uint64_t)(uint32_t)arg2
);
141 target_ulong
helper_macc(CPUMIPSState
*env
, target_ulong arg1
,
144 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
145 (int64_t)(int32_t)arg2
);
148 target_ulong
helper_macchi(CPUMIPSState
*env
, target_ulong arg1
,
151 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
152 (int64_t)(int32_t)arg2
);
155 target_ulong
helper_maccu(CPUMIPSState
*env
, target_ulong arg1
,
158 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) +
159 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
162 target_ulong
helper_macchiu(CPUMIPSState
*env
, target_ulong arg1
,
165 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) +
166 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
169 target_ulong
helper_msac(CPUMIPSState
*env
, target_ulong arg1
,
172 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
173 (int64_t)(int32_t)arg2
);
176 target_ulong
helper_msachi(CPUMIPSState
*env
, target_ulong arg1
,
179 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
180 (int64_t)(int32_t)arg2
);
183 target_ulong
helper_msacu(CPUMIPSState
*env
, target_ulong arg1
,
186 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) -
187 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
190 target_ulong
helper_msachiu(CPUMIPSState
*env
, target_ulong arg1
,
193 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) -
194 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
197 target_ulong
helper_mulhi(CPUMIPSState
*env
, target_ulong arg1
,
200 return set_HIT0_LO(env
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
203 target_ulong
helper_mulhiu(CPUMIPSState
*env
, target_ulong arg1
,
206 return set_HIT0_LO(env
, (uint64_t)(uint32_t)arg1
*
207 (uint64_t)(uint32_t)arg2
);
210 target_ulong
helper_mulshi(CPUMIPSState
*env
, target_ulong arg1
,
213 return set_HIT0_LO(env
, 0 - (int64_t)(int32_t)arg1
*
214 (int64_t)(int32_t)arg2
);
217 target_ulong
helper_mulshiu(CPUMIPSState
*env
, target_ulong arg1
,
220 return set_HIT0_LO(env
, 0 - (uint64_t)(uint32_t)arg1
*
221 (uint64_t)(uint32_t)arg2
);
224 static inline target_ulong
bitswap(target_ulong v
)
226 v
= ((v
>> 1) & (target_ulong
)0x5555555555555555ULL
) |
227 ((v
& (target_ulong
)0x5555555555555555ULL
) << 1);
228 v
= ((v
>> 2) & (target_ulong
)0x3333333333333333ULL
) |
229 ((v
& (target_ulong
)0x3333333333333333ULL
) << 2);
230 v
= ((v
>> 4) & (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) |
231 ((v
& (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) << 4);
236 target_ulong
helper_dbitswap(target_ulong rt
)
242 target_ulong
helper_bitswap(target_ulong rt
)
244 return (int32_t)bitswap(rt
);
247 #ifndef CONFIG_USER_ONLY
249 static inline hwaddr
do_translate_address(CPUMIPSState
*env
,
250 target_ulong address
,
251 int rw
, uintptr_t retaddr
)
254 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
256 lladdr
= cpu_mips_translate_address(env
, address
, rw
);
258 if (lladdr
== -1LL) {
259 cpu_loop_exit_restore(cs
, retaddr
);
265 #define HELPER_LD_ATOMIC(name, insn, almask) \
266 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
268 if (arg & almask) { \
269 env->CP0_BadVAddr = arg; \
270 do_raise_exception(env, EXCP_AdEL, GETPC()); \
272 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
273 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
276 HELPER_LD_ATOMIC(ll
, lw
, 0x3)
278 HELPER_LD_ATOMIC(lld
, ld
, 0x7)
280 #undef HELPER_LD_ATOMIC
282 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
283 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
284 target_ulong arg2, int mem_idx) \
288 if (arg2 & almask) { \
289 env->CP0_BadVAddr = arg2; \
290 do_raise_exception(env, EXCP_AdES, GETPC()); \
292 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
293 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
294 if (tmp == env->llval) { \
295 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
301 HELPER_ST_ATOMIC(sc
, lw
, sw
, 0x3)
303 HELPER_ST_ATOMIC(scd
, ld
, sd
, 0x7)
305 #undef HELPER_ST_ATOMIC
308 #ifdef TARGET_WORDS_BIGENDIAN
309 #define GET_LMASK(v) ((v) & 3)
310 #define GET_OFFSET(addr, offset) (addr + (offset))
312 #define GET_LMASK(v) (((v) & 3) ^ 3)
313 #define GET_OFFSET(addr, offset) (addr - (offset))
316 void helper_swl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
319 do_sb(env
, arg2
, (uint8_t)(arg1
>> 24), mem_idx
, GETPC());
321 if (GET_LMASK(arg2
) <= 2) {
322 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16), mem_idx
,
326 if (GET_LMASK(arg2
) <= 1) {
327 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8), mem_idx
,
331 if (GET_LMASK(arg2
) == 0) {
332 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)arg1
, mem_idx
,
337 void helper_swr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
340 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
342 if (GET_LMASK(arg2
) >= 1) {
343 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
347 if (GET_LMASK(arg2
) >= 2) {
348 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
352 if (GET_LMASK(arg2
) == 3) {
353 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
358 #if defined(TARGET_MIPS64)
359 /* "half" load and stores. We must do the memory access inline,
360 or fault handling won't work. */
362 #ifdef TARGET_WORDS_BIGENDIAN
363 #define GET_LMASK64(v) ((v) & 7)
365 #define GET_LMASK64(v) (((v) & 7) ^ 7)
368 void helper_sdl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
371 do_sb(env
, arg2
, (uint8_t)(arg1
>> 56), mem_idx
, GETPC());
373 if (GET_LMASK64(arg2
) <= 6) {
374 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48), mem_idx
,
378 if (GET_LMASK64(arg2
) <= 5) {
379 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40), mem_idx
,
383 if (GET_LMASK64(arg2
) <= 4) {
384 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32), mem_idx
,
388 if (GET_LMASK64(arg2
) <= 3) {
389 do_sb(env
, GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24), mem_idx
,
393 if (GET_LMASK64(arg2
) <= 2) {
394 do_sb(env
, GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16), mem_idx
,
398 if (GET_LMASK64(arg2
) <= 1) {
399 do_sb(env
, GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8), mem_idx
,
403 if (GET_LMASK64(arg2
) <= 0) {
404 do_sb(env
, GET_OFFSET(arg2
, 7), (uint8_t)arg1
, mem_idx
,
409 void helper_sdr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
412 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
414 if (GET_LMASK64(arg2
) >= 1) {
415 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
419 if (GET_LMASK64(arg2
) >= 2) {
420 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
424 if (GET_LMASK64(arg2
) >= 3) {
425 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
429 if (GET_LMASK64(arg2
) >= 4) {
430 do_sb(env
, GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32), mem_idx
,
434 if (GET_LMASK64(arg2
) >= 5) {
435 do_sb(env
, GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40), mem_idx
,
439 if (GET_LMASK64(arg2
) >= 6) {
440 do_sb(env
, GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48), mem_idx
,
444 if (GET_LMASK64(arg2
) == 7) {
445 do_sb(env
, GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56), mem_idx
,
449 #endif /* TARGET_MIPS64 */
451 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
453 void helper_lwm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
456 target_ulong base_reglist
= reglist
& 0xf;
457 target_ulong do_r31
= reglist
& 0x10;
459 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
462 for (i
= 0; i
< base_reglist
; i
++) {
463 env
->active_tc
.gpr
[multiple_regs
[i
]] =
464 (target_long
)do_lw(env
, addr
, mem_idx
, GETPC());
470 env
->active_tc
.gpr
[31] = (target_long
)do_lw(env
, addr
, mem_idx
,
475 void helper_swm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
478 target_ulong base_reglist
= reglist
& 0xf;
479 target_ulong do_r31
= reglist
& 0x10;
481 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
484 for (i
= 0; i
< base_reglist
; i
++) {
485 do_sw(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
492 do_sw(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
496 #if defined(TARGET_MIPS64)
497 void helper_ldm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
500 target_ulong base_reglist
= reglist
& 0xf;
501 target_ulong do_r31
= reglist
& 0x10;
503 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
506 for (i
= 0; i
< base_reglist
; i
++) {
507 env
->active_tc
.gpr
[multiple_regs
[i
]] = do_ld(env
, addr
, mem_idx
,
514 env
->active_tc
.gpr
[31] = do_ld(env
, addr
, mem_idx
, GETPC());
518 void helper_sdm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
521 target_ulong base_reglist
= reglist
& 0xf;
522 target_ulong do_r31
= reglist
& 0x10;
524 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
527 for (i
= 0; i
< base_reglist
; i
++) {
528 do_sd(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
535 do_sd(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
540 #ifndef CONFIG_USER_ONLY
542 static bool mips_vpe_is_wfi(MIPSCPU
*c
)
544 CPUState
*cpu
= CPU(c
);
545 CPUMIPSState
*env
= &c
->env
;
547 /* If the VPE is halted but otherwise active, it means it's waiting for
549 return cpu
->halted
&& mips_vpe_active(env
);
552 static bool mips_vp_is_wfi(MIPSCPU
*c
)
554 CPUState
*cpu
= CPU(c
);
555 CPUMIPSState
*env
= &c
->env
;
557 return cpu
->halted
&& mips_vp_active(env
);
560 static inline void mips_vpe_wake(MIPSCPU
*c
)
562 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
563 because there might be other conditions that state that c should
565 cpu_interrupt(CPU(c
), CPU_INTERRUPT_WAKE
);
568 static inline void mips_vpe_sleep(MIPSCPU
*cpu
)
570 CPUState
*cs
= CPU(cpu
);
572 /* The VPE was shut off, really go to bed.
573 Reset any old _WAKE requests. */
575 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
578 static inline void mips_tc_wake(MIPSCPU
*cpu
, int tc
)
580 CPUMIPSState
*c
= &cpu
->env
;
582 /* FIXME: TC reschedule. */
583 if (mips_vpe_active(c
) && !mips_vpe_is_wfi(cpu
)) {
588 static inline void mips_tc_sleep(MIPSCPU
*cpu
, int tc
)
590 CPUMIPSState
*c
= &cpu
->env
;
592 /* FIXME: TC reschedule. */
593 if (!mips_vpe_active(c
)) {
600 * @env: CPU from which mapping is performed.
601 * @tc: Should point to an int with the value of the global TC index.
603 * This function will transform @tc into a local index within the
604 * returned #CPUMIPSState.
606 /* FIXME: This code assumes that all VPEs have the same number of TCs,
607 which depends on runtime setup. Can probably be fixed by
608 walking the list of CPUMIPSStates. */
609 static CPUMIPSState
*mips_cpu_map_tc(CPUMIPSState
*env
, int *tc
)
617 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))) {
618 /* Not allowed to address other CPUs. */
619 *tc
= env
->current_tc
;
623 cs
= CPU(mips_env_get_cpu(env
));
624 vpe_idx
= tc_idx
/ cs
->nr_threads
;
625 *tc
= tc_idx
% cs
->nr_threads
;
626 other_cs
= qemu_get_cpu(vpe_idx
);
627 if (other_cs
== NULL
) {
630 cpu
= MIPS_CPU(other_cs
);
634 /* The per VPE CP0_Status register shares some fields with the per TC
635 CP0_TCStatus registers. These fields are wired to the same registers,
636 so changes to either of them should be reflected on both registers.
638 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
640 These helper call synchronizes the regs for a given cpu. */
642 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
643 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
646 /* Called for updates to CP0_TCStatus. */
647 static void sync_c0_tcstatus(CPUMIPSState
*cpu
, int tc
,
651 uint32_t tcu
, tmx
, tasid
, tksu
;
652 uint32_t mask
= ((1U << CP0St_CU3
)
659 tcu
= (v
>> CP0TCSt_TCU0
) & 0xf;
660 tmx
= (v
>> CP0TCSt_TMX
) & 0x1;
661 tasid
= v
& cpu
->CP0_EntryHi_ASID_mask
;
662 tksu
= (v
>> CP0TCSt_TKSU
) & 0x3;
664 status
= tcu
<< CP0St_CU0
;
665 status
|= tmx
<< CP0St_MX
;
666 status
|= tksu
<< CP0St_KSU
;
668 cpu
->CP0_Status
&= ~mask
;
669 cpu
->CP0_Status
|= status
;
671 /* Sync the TASID with EntryHi. */
672 cpu
->CP0_EntryHi
&= ~cpu
->CP0_EntryHi_ASID_mask
;
673 cpu
->CP0_EntryHi
|= tasid
;
678 /* Called for updates to CP0_EntryHi. */
679 static void sync_c0_entryhi(CPUMIPSState
*cpu
, int tc
)
682 uint32_t asid
, v
= cpu
->CP0_EntryHi
;
684 asid
= v
& cpu
->CP0_EntryHi_ASID_mask
;
686 if (tc
== cpu
->current_tc
) {
687 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
689 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
692 *tcst
&= ~cpu
->CP0_EntryHi_ASID_mask
;
697 target_ulong
helper_mfc0_mvpcontrol(CPUMIPSState
*env
)
699 return env
->mvp
->CP0_MVPControl
;
702 target_ulong
helper_mfc0_mvpconf0(CPUMIPSState
*env
)
704 return env
->mvp
->CP0_MVPConf0
;
707 target_ulong
helper_mfc0_mvpconf1(CPUMIPSState
*env
)
709 return env
->mvp
->CP0_MVPConf1
;
712 target_ulong
helper_mfc0_random(CPUMIPSState
*env
)
714 return (int32_t)cpu_mips_get_random(env
);
717 target_ulong
helper_mfc0_tcstatus(CPUMIPSState
*env
)
719 return env
->active_tc
.CP0_TCStatus
;
722 target_ulong
helper_mftc0_tcstatus(CPUMIPSState
*env
)
724 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
725 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
727 if (other_tc
== other
->current_tc
)
728 return other
->active_tc
.CP0_TCStatus
;
730 return other
->tcs
[other_tc
].CP0_TCStatus
;
733 target_ulong
helper_mfc0_tcbind(CPUMIPSState
*env
)
735 return env
->active_tc
.CP0_TCBind
;
738 target_ulong
helper_mftc0_tcbind(CPUMIPSState
*env
)
740 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
741 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
743 if (other_tc
== other
->current_tc
)
744 return other
->active_tc
.CP0_TCBind
;
746 return other
->tcs
[other_tc
].CP0_TCBind
;
749 target_ulong
helper_mfc0_tcrestart(CPUMIPSState
*env
)
751 return env
->active_tc
.PC
;
754 target_ulong
helper_mftc0_tcrestart(CPUMIPSState
*env
)
756 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
757 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
759 if (other_tc
== other
->current_tc
)
760 return other
->active_tc
.PC
;
762 return other
->tcs
[other_tc
].PC
;
765 target_ulong
helper_mfc0_tchalt(CPUMIPSState
*env
)
767 return env
->active_tc
.CP0_TCHalt
;
770 target_ulong
helper_mftc0_tchalt(CPUMIPSState
*env
)
772 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
773 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
775 if (other_tc
== other
->current_tc
)
776 return other
->active_tc
.CP0_TCHalt
;
778 return other
->tcs
[other_tc
].CP0_TCHalt
;
781 target_ulong
helper_mfc0_tccontext(CPUMIPSState
*env
)
783 return env
->active_tc
.CP0_TCContext
;
786 target_ulong
helper_mftc0_tccontext(CPUMIPSState
*env
)
788 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
789 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
791 if (other_tc
== other
->current_tc
)
792 return other
->active_tc
.CP0_TCContext
;
794 return other
->tcs
[other_tc
].CP0_TCContext
;
797 target_ulong
helper_mfc0_tcschedule(CPUMIPSState
*env
)
799 return env
->active_tc
.CP0_TCSchedule
;
802 target_ulong
helper_mftc0_tcschedule(CPUMIPSState
*env
)
804 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
805 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
807 if (other_tc
== other
->current_tc
)
808 return other
->active_tc
.CP0_TCSchedule
;
810 return other
->tcs
[other_tc
].CP0_TCSchedule
;
813 target_ulong
helper_mfc0_tcschefback(CPUMIPSState
*env
)
815 return env
->active_tc
.CP0_TCScheFBack
;
818 target_ulong
helper_mftc0_tcschefback(CPUMIPSState
*env
)
820 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
821 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
823 if (other_tc
== other
->current_tc
)
824 return other
->active_tc
.CP0_TCScheFBack
;
826 return other
->tcs
[other_tc
].CP0_TCScheFBack
;
829 target_ulong
helper_mfc0_count(CPUMIPSState
*env
)
832 qemu_mutex_lock_iothread();
833 count
= (int32_t) cpu_mips_get_count(env
);
834 qemu_mutex_unlock_iothread();
838 target_ulong
helper_mftc0_entryhi(CPUMIPSState
*env
)
840 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
841 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
843 return other
->CP0_EntryHi
;
846 target_ulong
helper_mftc0_cause(CPUMIPSState
*env
)
848 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
850 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
852 if (other_tc
== other
->current_tc
) {
853 tccause
= other
->CP0_Cause
;
855 tccause
= other
->CP0_Cause
;
861 target_ulong
helper_mftc0_status(CPUMIPSState
*env
)
863 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
864 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
866 return other
->CP0_Status
;
869 target_ulong
helper_mfc0_lladdr(CPUMIPSState
*env
)
871 return (int32_t)(env
->lladdr
>> env
->CP0_LLAddr_shift
);
874 target_ulong
helper_mfc0_maar(CPUMIPSState
*env
)
876 return (int32_t) env
->CP0_MAAR
[env
->CP0_MAARI
];
879 target_ulong
helper_mfhc0_maar(CPUMIPSState
*env
)
881 return env
->CP0_MAAR
[env
->CP0_MAARI
] >> 32;
884 target_ulong
helper_mfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
886 return (int32_t)env
->CP0_WatchLo
[sel
];
889 target_ulong
helper_mfc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
891 return env
->CP0_WatchHi
[sel
];
894 target_ulong
helper_mfc0_debug(CPUMIPSState
*env
)
896 target_ulong t0
= env
->CP0_Debug
;
897 if (env
->hflags
& MIPS_HFLAG_DM
)
903 target_ulong
helper_mftc0_debug(CPUMIPSState
*env
)
905 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
907 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
909 if (other_tc
== other
->current_tc
)
910 tcstatus
= other
->active_tc
.CP0_Debug_tcstatus
;
912 tcstatus
= other
->tcs
[other_tc
].CP0_Debug_tcstatus
;
914 /* XXX: Might be wrong, check with EJTAG spec. */
915 return (other
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
916 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
919 #if defined(TARGET_MIPS64)
920 target_ulong
helper_dmfc0_tcrestart(CPUMIPSState
*env
)
922 return env
->active_tc
.PC
;
925 target_ulong
helper_dmfc0_tchalt(CPUMIPSState
*env
)
927 return env
->active_tc
.CP0_TCHalt
;
930 target_ulong
helper_dmfc0_tccontext(CPUMIPSState
*env
)
932 return env
->active_tc
.CP0_TCContext
;
935 target_ulong
helper_dmfc0_tcschedule(CPUMIPSState
*env
)
937 return env
->active_tc
.CP0_TCSchedule
;
940 target_ulong
helper_dmfc0_tcschefback(CPUMIPSState
*env
)
942 return env
->active_tc
.CP0_TCScheFBack
;
945 target_ulong
helper_dmfc0_lladdr(CPUMIPSState
*env
)
947 return env
->lladdr
>> env
->CP0_LLAddr_shift
;
950 target_ulong
helper_dmfc0_maar(CPUMIPSState
*env
)
952 return env
->CP0_MAAR
[env
->CP0_MAARI
];
955 target_ulong
helper_dmfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
957 return env
->CP0_WatchLo
[sel
];
959 #endif /* TARGET_MIPS64 */
961 void helper_mtc0_index(CPUMIPSState
*env
, target_ulong arg1
)
963 uint32_t index_p
= env
->CP0_Index
& 0x80000000;
964 uint32_t tlb_index
= arg1
& 0x7fffffff;
965 if (tlb_index
< env
->tlb
->nb_tlb
) {
966 if (env
->insn_flags
& ISA_MIPS32R6
) {
967 index_p
|= arg1
& 0x80000000;
969 env
->CP0_Index
= index_p
| tlb_index
;
973 void helper_mtc0_mvpcontrol(CPUMIPSState
*env
, target_ulong arg1
)
978 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
979 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
981 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
982 mask
|= (1 << CP0MVPCo_STLB
);
983 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
985 // TODO: Enable/disable shared TLB, enable/disable VPEs.
987 env
->mvp
->CP0_MVPControl
= newval
;
990 void helper_mtc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
995 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
996 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
997 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
999 /* Yield scheduler intercept not implemented. */
1000 /* Gating storage scheduler intercept not implemented. */
1002 // TODO: Enable/disable TCs.
1004 env
->CP0_VPEControl
= newval
;
1007 void helper_mttc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1009 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1010 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1014 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1015 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1016 newval
= (other
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1018 /* TODO: Enable/disable TCs. */
1020 other
->CP0_VPEControl
= newval
;
1023 target_ulong
helper_mftc0_vpecontrol(CPUMIPSState
*env
)
1025 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1026 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1027 /* FIXME: Mask away return zero on read bits. */
1028 return other
->CP0_VPEControl
;
1031 target_ulong
helper_mftc0_vpeconf0(CPUMIPSState
*env
)
1033 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1034 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1036 return other
->CP0_VPEConf0
;
1039 void helper_mtc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1044 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
1045 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
1046 mask
|= (0xff << CP0VPEC0_XTC
);
1047 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1049 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1051 // TODO: TC exclusive handling due to ERL/EXL.
1053 env
->CP0_VPEConf0
= newval
;
1056 void helper_mttc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1058 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1059 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1063 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1064 newval
= (other
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1066 /* TODO: TC exclusive handling due to ERL/EXL. */
1067 other
->CP0_VPEConf0
= newval
;
1070 void helper_mtc0_vpeconf1(CPUMIPSState
*env
, target_ulong arg1
)
1075 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1076 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
1077 (0xff << CP0VPEC1_NCP1
);
1078 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
1080 /* UDI not implemented. */
1081 /* CP2 not implemented. */
1083 // TODO: Handle FPU (CP1) binding.
1085 env
->CP0_VPEConf1
= newval
;
1088 void helper_mtc0_yqmask(CPUMIPSState
*env
, target_ulong arg1
)
1090 /* Yield qualifier inputs not implemented. */
1091 env
->CP0_YQMask
= 0x00000000;
1094 void helper_mtc0_vpeopt(CPUMIPSState
*env
, target_ulong arg1
)
1096 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
1099 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1101 void helper_mtc0_entrylo0(CPUMIPSState
*env
, target_ulong arg1
)
1103 /* 1k pages not implemented */
1104 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1105 env
->CP0_EntryLo0
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1106 | (rxi
<< (CP0EnLo_XI
- 30));
1109 #if defined(TARGET_MIPS64)
1110 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1112 void helper_dmtc0_entrylo0(CPUMIPSState
*env
, uint64_t arg1
)
1114 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1115 env
->CP0_EntryLo0
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1119 void helper_mtc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1121 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
1124 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
1126 env
->active_tc
.CP0_TCStatus
= newval
;
1127 sync_c0_tcstatus(env
, env
->current_tc
, newval
);
1130 void helper_mttc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1132 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1133 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1135 if (other_tc
== other
->current_tc
)
1136 other
->active_tc
.CP0_TCStatus
= arg1
;
1138 other
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
1139 sync_c0_tcstatus(other
, other_tc
, arg1
);
1142 void helper_mtc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1144 uint32_t mask
= (1 << CP0TCBd_TBE
);
1147 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1148 mask
|= (1 << CP0TCBd_CurVPE
);
1149 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1150 env
->active_tc
.CP0_TCBind
= newval
;
1153 void helper_mttc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1155 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1156 uint32_t mask
= (1 << CP0TCBd_TBE
);
1158 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1160 if (other
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1161 mask
|= (1 << CP0TCBd_CurVPE
);
1162 if (other_tc
== other
->current_tc
) {
1163 newval
= (other
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1164 other
->active_tc
.CP0_TCBind
= newval
;
1166 newval
= (other
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
1167 other
->tcs
[other_tc
].CP0_TCBind
= newval
;
1171 void helper_mtc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1173 env
->active_tc
.PC
= arg1
;
1174 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1176 /* MIPS16 not implemented. */
1179 void helper_mttc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1181 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1182 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1184 if (other_tc
== other
->current_tc
) {
1185 other
->active_tc
.PC
= arg1
;
1186 other
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1187 other
->lladdr
= 0ULL;
1188 /* MIPS16 not implemented. */
1190 other
->tcs
[other_tc
].PC
= arg1
;
1191 other
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1192 other
->lladdr
= 0ULL;
1193 /* MIPS16 not implemented. */
1197 void helper_mtc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1199 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1201 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
1203 // TODO: Halt TC / Restart (if allocated+active) TC.
1204 if (env
->active_tc
.CP0_TCHalt
& 1) {
1205 mips_tc_sleep(cpu
, env
->current_tc
);
1207 mips_tc_wake(cpu
, env
->current_tc
);
1211 void helper_mttc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1213 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1214 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1215 MIPSCPU
*other_cpu
= mips_env_get_cpu(other
);
1217 // TODO: Halt TC / Restart (if allocated+active) TC.
1219 if (other_tc
== other
->current_tc
)
1220 other
->active_tc
.CP0_TCHalt
= arg1
;
1222 other
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
1225 mips_tc_sleep(other_cpu
, other_tc
);
1227 mips_tc_wake(other_cpu
, other_tc
);
1231 void helper_mtc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1233 env
->active_tc
.CP0_TCContext
= arg1
;
1236 void helper_mttc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1238 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1239 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1241 if (other_tc
== other
->current_tc
)
1242 other
->active_tc
.CP0_TCContext
= arg1
;
1244 other
->tcs
[other_tc
].CP0_TCContext
= arg1
;
1247 void helper_mtc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1249 env
->active_tc
.CP0_TCSchedule
= arg1
;
1252 void helper_mttc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1254 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1255 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1257 if (other_tc
== other
->current_tc
)
1258 other
->active_tc
.CP0_TCSchedule
= arg1
;
1260 other
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
1263 void helper_mtc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1265 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1268 void helper_mttc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1270 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1271 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1273 if (other_tc
== other
->current_tc
)
1274 other
->active_tc
.CP0_TCScheFBack
= arg1
;
1276 other
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
1279 void helper_mtc0_entrylo1(CPUMIPSState
*env
, target_ulong arg1
)
1281 /* 1k pages not implemented */
1282 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1283 env
->CP0_EntryLo1
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1284 | (rxi
<< (CP0EnLo_XI
- 30));
1287 #if defined(TARGET_MIPS64)
1288 void helper_dmtc0_entrylo1(CPUMIPSState
*env
, uint64_t arg1
)
1290 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1291 env
->CP0_EntryLo1
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1295 void helper_mtc0_context(CPUMIPSState
*env
, target_ulong arg1
)
1297 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
1300 void helper_mtc0_pagemask(CPUMIPSState
*env
, target_ulong arg1
)
1302 uint64_t mask
= arg1
>> (TARGET_PAGE_BITS
+ 1);
1303 if (!(env
->insn_flags
& ISA_MIPS32R6
) || (arg1
== ~0) ||
1304 (mask
== 0x0000 || mask
== 0x0003 || mask
== 0x000F ||
1305 mask
== 0x003F || mask
== 0x00FF || mask
== 0x03FF ||
1306 mask
== 0x0FFF || mask
== 0x3FFF || mask
== 0xFFFF)) {
1307 env
->CP0_PageMask
= arg1
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1311 void helper_mtc0_pagegrain(CPUMIPSState
*env
, target_ulong arg1
)
1313 /* SmartMIPS not implemented */
1314 /* 1k pages not implemented */
1315 env
->CP0_PageGrain
= (arg1
& env
->CP0_PageGrain_rw_bitmask
) |
1316 (env
->CP0_PageGrain
& ~env
->CP0_PageGrain_rw_bitmask
);
1317 compute_hflags(env
);
1318 restore_pamask(env
);
1321 void helper_mtc0_wired(CPUMIPSState
*env
, target_ulong arg1
)
1323 if (env
->insn_flags
& ISA_MIPS32R6
) {
1324 if (arg1
< env
->tlb
->nb_tlb
) {
1325 env
->CP0_Wired
= arg1
;
1328 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1332 void helper_mtc0_srsconf0(CPUMIPSState
*env
, target_ulong arg1
)
1334 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1337 void helper_mtc0_srsconf1(CPUMIPSState
*env
, target_ulong arg1
)
1339 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1342 void helper_mtc0_srsconf2(CPUMIPSState
*env
, target_ulong arg1
)
1344 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1347 void helper_mtc0_srsconf3(CPUMIPSState
*env
, target_ulong arg1
)
1349 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1352 void helper_mtc0_srsconf4(CPUMIPSState
*env
, target_ulong arg1
)
1354 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1357 void helper_mtc0_hwrena(CPUMIPSState
*env
, target_ulong arg1
)
1359 uint32_t mask
= 0x0000000F;
1361 if ((env
->CP0_Config1
& (1 << CP0C1_PC
)) &&
1362 (env
->insn_flags
& ISA_MIPS32R6
)) {
1365 if (env
->insn_flags
& ISA_MIPS32R6
) {
1368 if (env
->CP0_Config3
& (1 << CP0C3_ULRI
)) {
1371 if (arg1
& (1 << 29)) {
1372 env
->hflags
|= MIPS_HFLAG_HWRENA_ULR
;
1374 env
->hflags
&= ~MIPS_HFLAG_HWRENA_ULR
;
1378 env
->CP0_HWREna
= arg1
& mask
;
1381 void helper_mtc0_count(CPUMIPSState
*env
, target_ulong arg1
)
1383 qemu_mutex_lock_iothread();
1384 cpu_mips_store_count(env
, arg1
);
1385 qemu_mutex_unlock_iothread();
1388 void helper_mtc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1390 target_ulong old
, val
, mask
;
1391 mask
= (TARGET_PAGE_MASK
<< 1) | env
->CP0_EntryHi_ASID_mask
;
1392 if (((env
->CP0_Config4
>> CP0C4_IE
) & 0x3) >= 2) {
1393 mask
|= 1 << CP0EnHi_EHINV
;
1396 /* 1k pages not implemented */
1397 #if defined(TARGET_MIPS64)
1398 if (env
->insn_flags
& ISA_MIPS32R6
) {
1399 int entryhi_r
= extract64(arg1
, 62, 2);
1400 int config0_at
= extract32(env
->CP0_Config0
, 13, 2);
1401 bool no_supervisor
= (env
->CP0_Status_rw_bitmask
& 0x8) == 0;
1402 if ((entryhi_r
== 2) ||
1403 (entryhi_r
== 1 && (no_supervisor
|| config0_at
== 1))) {
1404 /* skip EntryHi.R field if new value is reserved */
1405 mask
&= ~(0x3ull
<< 62);
1408 mask
&= env
->SEGMask
;
1410 old
= env
->CP0_EntryHi
;
1411 val
= (arg1
& mask
) | (old
& ~mask
);
1412 env
->CP0_EntryHi
= val
;
1413 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1414 sync_c0_entryhi(env
, env
->current_tc
);
1416 /* If the ASID changes, flush qemu's TLB. */
1417 if ((old
& env
->CP0_EntryHi_ASID_mask
) !=
1418 (val
& env
->CP0_EntryHi_ASID_mask
)) {
1419 tlb_flush(CPU(mips_env_get_cpu(env
)));
1423 void helper_mttc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1425 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1426 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1428 other
->CP0_EntryHi
= arg1
;
1429 sync_c0_entryhi(other
, other_tc
);
1432 void helper_mtc0_compare(CPUMIPSState
*env
, target_ulong arg1
)
1434 qemu_mutex_lock_iothread();
1435 cpu_mips_store_compare(env
, arg1
);
1436 qemu_mutex_unlock_iothread();
1439 void helper_mtc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1441 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1444 old
= env
->CP0_Status
;
1445 cpu_mips_store_status(env
, arg1
);
1446 val
= env
->CP0_Status
;
1448 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1449 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1450 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1451 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1453 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
1454 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1455 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1456 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1458 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
1464 void helper_mttc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1466 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1467 uint32_t mask
= env
->CP0_Status_rw_bitmask
& ~0xf1000018;
1468 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1470 other
->CP0_Status
= (other
->CP0_Status
& ~mask
) | (arg1
& mask
);
1471 sync_c0_status(env
, other
, other_tc
);
1474 void helper_mtc0_intctl(CPUMIPSState
*env
, target_ulong arg1
)
1476 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000003e0) | (arg1
& 0x000003e0);
1479 void helper_mtc0_srsctl(CPUMIPSState
*env
, target_ulong arg1
)
1481 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1482 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1485 void helper_mtc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1487 qemu_mutex_lock_iothread();
1488 cpu_mips_store_cause(env
, arg1
);
1489 qemu_mutex_unlock_iothread();
1492 void helper_mttc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1494 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1495 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1497 cpu_mips_store_cause(other
, arg1
);
1500 target_ulong
helper_mftc0_epc(CPUMIPSState
*env
)
1502 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1503 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1505 return other
->CP0_EPC
;
1508 target_ulong
helper_mftc0_ebase(CPUMIPSState
*env
)
1510 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1511 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1513 return other
->CP0_EBase
;
1516 void helper_mtc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1518 env
->CP0_EBase
= (env
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1521 void helper_mttc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1523 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1524 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1525 other
->CP0_EBase
= (other
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1528 target_ulong
helper_mftc0_configx(CPUMIPSState
*env
, target_ulong idx
)
1530 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1531 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1534 case 0: return other
->CP0_Config0
;
1535 case 1: return other
->CP0_Config1
;
1536 case 2: return other
->CP0_Config2
;
1537 case 3: return other
->CP0_Config3
;
1538 /* 4 and 5 are reserved. */
1539 case 6: return other
->CP0_Config6
;
1540 case 7: return other
->CP0_Config7
;
1547 void helper_mtc0_config0(CPUMIPSState
*env
, target_ulong arg1
)
1549 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1552 void helper_mtc0_config2(CPUMIPSState
*env
, target_ulong arg1
)
1554 /* tertiary/secondary caches not implemented */
1555 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1558 void helper_mtc0_config3(CPUMIPSState
*env
, target_ulong arg1
)
1560 if (env
->insn_flags
& ASE_MICROMIPS
) {
1561 env
->CP0_Config3
= (env
->CP0_Config3
& ~(1 << CP0C3_ISA_ON_EXC
)) |
1562 (arg1
& (1 << CP0C3_ISA_ON_EXC
));
1566 void helper_mtc0_config4(CPUMIPSState
*env
, target_ulong arg1
)
1568 env
->CP0_Config4
= (env
->CP0_Config4
& (~env
->CP0_Config4_rw_bitmask
)) |
1569 (arg1
& env
->CP0_Config4_rw_bitmask
);
1572 void helper_mtc0_config5(CPUMIPSState
*env
, target_ulong arg1
)
1574 env
->CP0_Config5
= (env
->CP0_Config5
& (~env
->CP0_Config5_rw_bitmask
)) |
1575 (arg1
& env
->CP0_Config5_rw_bitmask
);
1576 compute_hflags(env
);
1579 void helper_mtc0_lladdr(CPUMIPSState
*env
, target_ulong arg1
)
1581 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1582 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1583 env
->lladdr
= (env
->lladdr
& ~mask
) | (arg1
& mask
);
1586 #define MTC0_MAAR_MASK(env) \
1587 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1589 void helper_mtc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1591 env
->CP0_MAAR
[env
->CP0_MAARI
] = arg1
& MTC0_MAAR_MASK(env
);
1594 void helper_mthc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1596 env
->CP0_MAAR
[env
->CP0_MAARI
] =
1597 (((uint64_t) arg1
<< 32) & MTC0_MAAR_MASK(env
)) |
1598 (env
->CP0_MAAR
[env
->CP0_MAARI
] & 0x00000000ffffffffULL
);
1601 void helper_mtc0_maari(CPUMIPSState
*env
, target_ulong arg1
)
1603 int index
= arg1
& 0x3f;
1604 if (index
== 0x3f) {
1605 /* Software may write all ones to INDEX to determine the
1606 maximum value supported. */
1607 env
->CP0_MAARI
= MIPS_MAAR_MAX
- 1;
1608 } else if (index
< MIPS_MAAR_MAX
) {
1609 env
->CP0_MAARI
= index
;
1611 /* Other than the all ones, if the
1612 value written is not supported, then INDEX is unchanged
1613 from its previous value. */
1616 void helper_mtc0_watchlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1618 /* Watch exceptions for instructions, data loads, data stores
1620 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1623 void helper_mtc0_watchhi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1625 int mask
= 0x40000FF8 | (env
->CP0_EntryHi_ASID_mask
<< CP0WH_ASID
);
1626 env
->CP0_WatchHi
[sel
] = arg1
& mask
;
1627 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1630 void helper_mtc0_xcontext(CPUMIPSState
*env
, target_ulong arg1
)
1632 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1633 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1636 void helper_mtc0_framemask(CPUMIPSState
*env
, target_ulong arg1
)
1638 env
->CP0_Framemask
= arg1
; /* XXX */
1641 void helper_mtc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1643 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1644 if (arg1
& (1 << CP0DB_DM
))
1645 env
->hflags
|= MIPS_HFLAG_DM
;
1647 env
->hflags
&= ~MIPS_HFLAG_DM
;
1650 void helper_mttc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1652 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1653 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1654 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1656 /* XXX: Might be wrong, check with EJTAG spec. */
1657 if (other_tc
== other
->current_tc
)
1658 other
->active_tc
.CP0_Debug_tcstatus
= val
;
1660 other
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1661 other
->CP0_Debug
= (other
->CP0_Debug
&
1662 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1663 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1666 void helper_mtc0_performance0(CPUMIPSState
*env
, target_ulong arg1
)
1668 env
->CP0_Performance0
= arg1
& 0x000007ff;
1671 void helper_mtc0_errctl(CPUMIPSState
*env
, target_ulong arg1
)
1673 int32_t wst
= arg1
& (1 << CP0EC_WST
);
1674 int32_t spr
= arg1
& (1 << CP0EC_SPR
);
1675 int32_t itc
= env
->itc_tag
? (arg1
& (1 << CP0EC_ITC
)) : 0;
1677 env
->CP0_ErrCtl
= wst
| spr
| itc
;
1679 if (itc
&& !wst
&& !spr
) {
1680 env
->hflags
|= MIPS_HFLAG_ITC_CACHE
;
1682 env
->hflags
&= ~MIPS_HFLAG_ITC_CACHE
;
1686 void helper_mtc0_taglo(CPUMIPSState
*env
, target_ulong arg1
)
1688 if (env
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
1689 /* If CACHE instruction is configured for ITC tags then make all
1690 CP0.TagLo bits writable. The actual write to ITC Configuration
1691 Tag will take care of the read-only bits. */
1692 env
->CP0_TagLo
= arg1
;
1694 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1698 void helper_mtc0_datalo(CPUMIPSState
*env
, target_ulong arg1
)
1700 env
->CP0_DataLo
= arg1
; /* XXX */
1703 void helper_mtc0_taghi(CPUMIPSState
*env
, target_ulong arg1
)
1705 env
->CP0_TagHi
= arg1
; /* XXX */
1708 void helper_mtc0_datahi(CPUMIPSState
*env
, target_ulong arg1
)
1710 env
->CP0_DataHi
= arg1
; /* XXX */
1713 /* MIPS MT functions */
1714 target_ulong
helper_mftgpr(CPUMIPSState
*env
, uint32_t sel
)
1716 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1717 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1719 if (other_tc
== other
->current_tc
)
1720 return other
->active_tc
.gpr
[sel
];
1722 return other
->tcs
[other_tc
].gpr
[sel
];
1725 target_ulong
helper_mftlo(CPUMIPSState
*env
, uint32_t sel
)
1727 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1728 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1730 if (other_tc
== other
->current_tc
)
1731 return other
->active_tc
.LO
[sel
];
1733 return other
->tcs
[other_tc
].LO
[sel
];
1736 target_ulong
helper_mfthi(CPUMIPSState
*env
, uint32_t sel
)
1738 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1739 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1741 if (other_tc
== other
->current_tc
)
1742 return other
->active_tc
.HI
[sel
];
1744 return other
->tcs
[other_tc
].HI
[sel
];
1747 target_ulong
helper_mftacx(CPUMIPSState
*env
, uint32_t sel
)
1749 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1750 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1752 if (other_tc
== other
->current_tc
)
1753 return other
->active_tc
.ACX
[sel
];
1755 return other
->tcs
[other_tc
].ACX
[sel
];
1758 target_ulong
helper_mftdsp(CPUMIPSState
*env
)
1760 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1761 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1763 if (other_tc
== other
->current_tc
)
1764 return other
->active_tc
.DSPControl
;
1766 return other
->tcs
[other_tc
].DSPControl
;
1769 void helper_mttgpr(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1771 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1772 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1774 if (other_tc
== other
->current_tc
)
1775 other
->active_tc
.gpr
[sel
] = arg1
;
1777 other
->tcs
[other_tc
].gpr
[sel
] = arg1
;
1780 void helper_mttlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1782 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1783 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1785 if (other_tc
== other
->current_tc
)
1786 other
->active_tc
.LO
[sel
] = arg1
;
1788 other
->tcs
[other_tc
].LO
[sel
] = arg1
;
1791 void helper_mtthi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1793 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1794 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1796 if (other_tc
== other
->current_tc
)
1797 other
->active_tc
.HI
[sel
] = arg1
;
1799 other
->tcs
[other_tc
].HI
[sel
] = arg1
;
1802 void helper_mttacx(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1804 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1805 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1807 if (other_tc
== other
->current_tc
)
1808 other
->active_tc
.ACX
[sel
] = arg1
;
1810 other
->tcs
[other_tc
].ACX
[sel
] = arg1
;
1813 void helper_mttdsp(CPUMIPSState
*env
, target_ulong arg1
)
1815 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1816 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1818 if (other_tc
== other
->current_tc
)
1819 other
->active_tc
.DSPControl
= arg1
;
1821 other
->tcs
[other_tc
].DSPControl
= arg1
;
1824 /* MIPS MT functions */
1825 target_ulong
helper_dmt(void)
1831 target_ulong
helper_emt(void)
1837 target_ulong
helper_dvpe(CPUMIPSState
*env
)
1839 CPUState
*other_cs
= first_cpu
;
1840 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1842 CPU_FOREACH(other_cs
) {
1843 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1844 /* Turn off all VPEs except the one executing the dvpe. */
1845 if (&other_cpu
->env
!= env
) {
1846 other_cpu
->env
.mvp
->CP0_MVPControl
&= ~(1 << CP0MVPCo_EVP
);
1847 mips_vpe_sleep(other_cpu
);
1853 target_ulong
helper_evpe(CPUMIPSState
*env
)
1855 CPUState
*other_cs
= first_cpu
;
1856 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1858 CPU_FOREACH(other_cs
) {
1859 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1861 if (&other_cpu
->env
!= env
1862 /* If the VPE is WFI, don't disturb its sleep. */
1863 && !mips_vpe_is_wfi(other_cpu
)) {
1864 /* Enable the VPE. */
1865 other_cpu
->env
.mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
1866 mips_vpe_wake(other_cpu
); /* And wake it up. */
1871 #endif /* !CONFIG_USER_ONLY */
1873 void helper_fork(target_ulong arg1
, target_ulong arg2
)
1875 // arg1 = rt, arg2 = rs
1876 // TODO: store to TC register
1879 target_ulong
helper_yield(CPUMIPSState
*env
, target_ulong arg
)
1881 target_long arg1
= arg
;
1884 /* No scheduling policy implemented. */
1886 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
1887 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
1888 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1889 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
1890 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1893 } else if (arg1
== 0) {
1894 if (0 /* TODO: TC underflow */) {
1895 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1896 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1898 // TODO: Deallocate TC
1900 } else if (arg1
> 0) {
1901 /* Yield qualifier inputs not implemented. */
1902 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1903 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
1904 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1906 return env
->CP0_YQMask
;
1909 /* R6 Multi-threading */
1910 #ifndef CONFIG_USER_ONLY
1911 target_ulong
helper_dvp(CPUMIPSState
*env
)
1913 CPUState
*other_cs
= first_cpu
;
1914 target_ulong prev
= env
->CP0_VPControl
;
1916 if (!((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
1917 CPU_FOREACH(other_cs
) {
1918 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1919 /* Turn off all VPs except the one executing the dvp. */
1920 if (&other_cpu
->env
!= env
) {
1921 mips_vpe_sleep(other_cpu
);
1924 env
->CP0_VPControl
|= (1 << CP0VPCtl_DIS
);
1929 target_ulong
helper_evp(CPUMIPSState
*env
)
1931 CPUState
*other_cs
= first_cpu
;
1932 target_ulong prev
= env
->CP0_VPControl
;
1934 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
1935 CPU_FOREACH(other_cs
) {
1936 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1937 if ((&other_cpu
->env
!= env
) && !mips_vp_is_wfi(other_cpu
)) {
1938 /* If the VP is WFI, don't disturb its sleep.
1939 * Otherwise, wake it up. */
1940 mips_vpe_wake(other_cpu
);
1943 env
->CP0_VPControl
&= ~(1 << CP0VPCtl_DIS
);
1947 #endif /* !CONFIG_USER_ONLY */
1949 #ifndef CONFIG_USER_ONLY
1950 /* TLB management */
1951 static void r4k_mips_tlb_flush_extra (CPUMIPSState
*env
, int first
)
1953 /* Discard entries from env->tlb[first] onwards. */
1954 while (env
->tlb
->tlb_in_use
> first
) {
1955 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
1959 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo
)
1961 #if defined(TARGET_MIPS64)
1962 return extract64(entrylo
, 6, 54);
1964 return extract64(entrylo
, 6, 24) | /* PFN */
1965 (extract64(entrylo
, 32, 32) << 24); /* PFNX */
1969 static void r4k_fill_tlb(CPUMIPSState
*env
, int idx
)
1973 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1974 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1975 if (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) {
1980 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
1981 #if defined(TARGET_MIPS64)
1982 tlb
->VPN
&= env
->SEGMask
;
1984 tlb
->ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
1985 tlb
->PageMask
= env
->CP0_PageMask
;
1986 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
1987 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
1988 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
1989 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
1990 tlb
->XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) & 1;
1991 tlb
->RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) & 1;
1992 tlb
->PFN
[0] = get_tlb_pfn_from_entrylo(env
->CP0_EntryLo0
) << 12;
1993 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
1994 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
1995 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
1996 tlb
->XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) & 1;
1997 tlb
->RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) & 1;
1998 tlb
->PFN
[1] = get_tlb_pfn_from_entrylo(env
->CP0_EntryLo1
) << 12;
2001 void r4k_helper_tlbinv(CPUMIPSState
*env
)
2005 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2007 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2008 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2009 if (!tlb
->G
&& tlb
->ASID
== ASID
) {
2013 cpu_mips_tlb_flush(env
);
2016 void r4k_helper_tlbinvf(CPUMIPSState
*env
)
2020 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2021 env
->tlb
->mmu
.r4k
.tlb
[idx
].EHINV
= 1;
2023 cpu_mips_tlb_flush(env
);
2026 void r4k_helper_tlbwi(CPUMIPSState
*env
)
2032 bool EHINV
, G
, V0
, D0
, V1
, D1
, XI0
, XI1
, RI0
, RI1
;
2034 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2035 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2036 VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
2037 #if defined(TARGET_MIPS64)
2038 VPN
&= env
->SEGMask
;
2040 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2041 EHINV
= (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) != 0;
2042 G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
2043 V0
= (env
->CP0_EntryLo0
& 2) != 0;
2044 D0
= (env
->CP0_EntryLo0
& 4) != 0;
2045 XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) &1;
2046 RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) &1;
2047 V1
= (env
->CP0_EntryLo1
& 2) != 0;
2048 D1
= (env
->CP0_EntryLo1
& 4) != 0;
2049 XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) &1;
2050 RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) &1;
2052 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2053 permissions on the current entry. */
2054 if (tlb
->VPN
!= VPN
|| tlb
->ASID
!= ASID
|| tlb
->G
!= G
||
2055 (!tlb
->EHINV
&& EHINV
) ||
2056 (tlb
->V0
&& !V0
) || (tlb
->D0
&& !D0
) ||
2057 (!tlb
->XI0
&& XI0
) || (!tlb
->RI0
&& RI0
) ||
2058 (tlb
->V1
&& !V1
) || (tlb
->D1
&& !D1
) ||
2059 (!tlb
->XI1
&& XI1
) || (!tlb
->RI1
&& RI1
)) {
2060 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2063 r4k_invalidate_tlb(env
, idx
, 0);
2064 r4k_fill_tlb(env
, idx
);
2067 void r4k_helper_tlbwr(CPUMIPSState
*env
)
2069 int r
= cpu_mips_get_random(env
);
2071 r4k_invalidate_tlb(env
, r
, 1);
2072 r4k_fill_tlb(env
, r
);
2075 void r4k_helper_tlbp(CPUMIPSState
*env
)
2084 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2085 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
2086 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2087 /* 1k pages are not supported. */
2088 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2089 tag
= env
->CP0_EntryHi
& ~mask
;
2090 VPN
= tlb
->VPN
& ~mask
;
2091 #if defined(TARGET_MIPS64)
2092 tag
&= env
->SEGMask
;
2094 /* Check ASID, virtual page number & size */
2095 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
&& !tlb
->EHINV
) {
2101 if (i
== env
->tlb
->nb_tlb
) {
2102 /* No match. Discard any shadow entries, if any of them match. */
2103 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
2104 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2105 /* 1k pages are not supported. */
2106 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2107 tag
= env
->CP0_EntryHi
& ~mask
;
2108 VPN
= tlb
->VPN
& ~mask
;
2109 #if defined(TARGET_MIPS64)
2110 tag
&= env
->SEGMask
;
2112 /* Check ASID, virtual page number & size */
2113 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
2114 r4k_mips_tlb_flush_extra (env
, i
);
2119 env
->CP0_Index
|= 0x80000000;
2123 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn
)
2125 #if defined(TARGET_MIPS64)
2126 return tlb_pfn
<< 6;
2128 return (extract64(tlb_pfn
, 0, 24) << 6) | /* PFN */
2129 (extract64(tlb_pfn
, 24, 32) << 32); /* PFNX */
2133 void r4k_helper_tlbr(CPUMIPSState
*env
)
2139 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2140 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2141 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2143 /* If this will change the current ASID, flush qemu's TLB. */
2144 if (ASID
!= tlb
->ASID
)
2145 cpu_mips_tlb_flush(env
);
2147 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2150 env
->CP0_EntryHi
= 1 << CP0EnHi_EHINV
;
2151 env
->CP0_PageMask
= 0;
2152 env
->CP0_EntryLo0
= 0;
2153 env
->CP0_EntryLo1
= 0;
2155 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
2156 env
->CP0_PageMask
= tlb
->PageMask
;
2157 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
2158 ((uint64_t)tlb
->RI0
<< CP0EnLo_RI
) |
2159 ((uint64_t)tlb
->XI0
<< CP0EnLo_XI
) | (tlb
->C0
<< 3) |
2160 get_entrylo_pfn_from_tlb(tlb
->PFN
[0] >> 12);
2161 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
2162 ((uint64_t)tlb
->RI1
<< CP0EnLo_RI
) |
2163 ((uint64_t)tlb
->XI1
<< CP0EnLo_XI
) | (tlb
->C1
<< 3) |
2164 get_entrylo_pfn_from_tlb(tlb
->PFN
[1] >> 12);
2168 void helper_tlbwi(CPUMIPSState
*env
)
2170 env
->tlb
->helper_tlbwi(env
);
2173 void helper_tlbwr(CPUMIPSState
*env
)
2175 env
->tlb
->helper_tlbwr(env
);
2178 void helper_tlbp(CPUMIPSState
*env
)
2180 env
->tlb
->helper_tlbp(env
);
2183 void helper_tlbr(CPUMIPSState
*env
)
2185 env
->tlb
->helper_tlbr(env
);
2188 void helper_tlbinv(CPUMIPSState
*env
)
2190 env
->tlb
->helper_tlbinv(env
);
2193 void helper_tlbinvf(CPUMIPSState
*env
)
2195 env
->tlb
->helper_tlbinvf(env
);
2199 target_ulong
helper_di(CPUMIPSState
*env
)
2201 target_ulong t0
= env
->CP0_Status
;
2203 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
2207 target_ulong
helper_ei(CPUMIPSState
*env
)
2209 target_ulong t0
= env
->CP0_Status
;
2211 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
2215 static void debug_pre_eret(CPUMIPSState
*env
)
2217 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2218 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2219 env
->active_tc
.PC
, env
->CP0_EPC
);
2220 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2221 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2222 if (env
->hflags
& MIPS_HFLAG_DM
)
2223 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2228 static void debug_post_eret(CPUMIPSState
*env
)
2230 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
2232 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2233 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2234 env
->active_tc
.PC
, env
->CP0_EPC
);
2235 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2236 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2237 if (env
->hflags
& MIPS_HFLAG_DM
)
2238 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2239 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
2240 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
2241 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
2242 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
2244 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
2250 static void set_pc(CPUMIPSState
*env
, target_ulong error_pc
)
2252 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
2254 env
->hflags
|= MIPS_HFLAG_M16
;
2256 env
->hflags
&= ~(MIPS_HFLAG_M16
);
2260 static inline void exception_return(CPUMIPSState
*env
)
2262 debug_pre_eret(env
);
2263 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2264 set_pc(env
, env
->CP0_ErrorEPC
);
2265 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2267 set_pc(env
, env
->CP0_EPC
);
2268 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2270 compute_hflags(env
);
2271 debug_post_eret(env
);
2274 void helper_eret(CPUMIPSState
*env
)
2276 exception_return(env
);
2280 void helper_eretnc(CPUMIPSState
*env
)
2282 exception_return(env
);
2285 void helper_deret(CPUMIPSState
*env
)
2287 debug_pre_eret(env
);
2288 set_pc(env
, env
->CP0_DEPC
);
2290 env
->hflags
&= ~MIPS_HFLAG_DM
;
2291 compute_hflags(env
);
2292 debug_post_eret(env
);
2294 #endif /* !CONFIG_USER_ONLY */
2296 static inline void check_hwrena(CPUMIPSState
*env
, int reg
, uintptr_t pc
)
2298 if ((env
->hflags
& MIPS_HFLAG_CP0
) || (env
->CP0_HWREna
& (1 << reg
))) {
2301 do_raise_exception(env
, EXCP_RI
, pc
);
2304 target_ulong
helper_rdhwr_cpunum(CPUMIPSState
*env
)
2306 check_hwrena(env
, 0, GETPC());
2307 return env
->CP0_EBase
& 0x3ff;
2310 target_ulong
helper_rdhwr_synci_step(CPUMIPSState
*env
)
2312 check_hwrena(env
, 1, GETPC());
2313 return env
->SYNCI_Step
;
2316 target_ulong
helper_rdhwr_cc(CPUMIPSState
*env
)
2319 check_hwrena(env
, 2, GETPC());
2320 #ifdef CONFIG_USER_ONLY
2321 count
= env
->CP0_Count
;
2323 qemu_mutex_lock_iothread();
2324 count
= (int32_t)cpu_mips_get_count(env
);
2325 qemu_mutex_unlock_iothread();
2330 target_ulong
helper_rdhwr_ccres(CPUMIPSState
*env
)
2332 check_hwrena(env
, 3, GETPC());
2336 target_ulong
helper_rdhwr_performance(CPUMIPSState
*env
)
2338 check_hwrena(env
, 4, GETPC());
2339 return env
->CP0_Performance0
;
2342 target_ulong
helper_rdhwr_xnp(CPUMIPSState
*env
)
2344 check_hwrena(env
, 5, GETPC());
2345 return (env
->CP0_Config5
>> CP0C5_XNP
) & 1;
2348 void helper_pmon(CPUMIPSState
*env
, int function
)
2352 case 2: /* TODO: char inbyte(int waitflag); */
2353 if (env
->active_tc
.gpr
[4] == 0)
2354 env
->active_tc
.gpr
[2] = -1;
2356 case 11: /* TODO: char inbyte (void); */
2357 env
->active_tc
.gpr
[2] = -1;
2361 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
2367 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
2374 void helper_wait(CPUMIPSState
*env
)
2376 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2379 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
2380 /* Last instruction in the block, PC was updated before
2381 - no need to recover PC and icount */
2382 raise_exception(env
, EXCP_HLT
);
2385 #if !defined(CONFIG_USER_ONLY)
2387 void mips_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
2388 MMUAccessType access_type
,
2389 int mmu_idx
, uintptr_t retaddr
)
2391 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2392 CPUMIPSState
*env
= &cpu
->env
;
2396 env
->CP0_BadVAddr
= addr
;
2398 if (access_type
== MMU_DATA_STORE
) {
2402 if (access_type
== MMU_INST_FETCH
) {
2403 error_code
|= EXCP_INST_NOTAVAIL
;
2407 do_raise_exception_err(env
, excp
, error_code
, retaddr
);
2410 void tlb_fill(CPUState
*cs
, target_ulong addr
, MMUAccessType access_type
,
2411 int mmu_idx
, uintptr_t retaddr
)
2415 ret
= mips_cpu_handle_mmu_fault(cs
, addr
, access_type
, mmu_idx
);
2417 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2418 CPUMIPSState
*env
= &cpu
->env
;
2420 do_raise_exception_err(env
, cs
->exception_index
,
2421 env
->error_code
, retaddr
);
2425 void mips_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2426 bool is_write
, bool is_exec
, int unused
,
2429 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2430 CPUMIPSState
*env
= &cpu
->env
;
2433 * Raising an exception with KVM enabled will crash because it won't be from
2434 * the main execution loop so the longjmp won't have a matching setjmp.
2435 * Until we can trigger a bus error exception through KVM lets just ignore
2438 if (kvm_enabled()) {
2443 raise_exception(env
, EXCP_IBE
);
2445 raise_exception(env
, EXCP_DBE
);
2448 #endif /* !CONFIG_USER_ONLY */
2450 /* Complex FPU operations which may need stack space. */
2452 #define FLOAT_TWO32 make_float32(1 << 30)
2453 #define FLOAT_TWO64 make_float64(1ULL << 62)
2455 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2456 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2458 /* convert MIPS rounding mode in FCR31 to IEEE library */
2459 unsigned int ieee_rm
[] = {
2460 float_round_nearest_even
,
2461 float_round_to_zero
,
2466 target_ulong
helper_cfc1(CPUMIPSState
*env
, uint32_t reg
)
2468 target_ulong arg1
= 0;
2472 arg1
= (int32_t)env
->active_fpu
.fcr0
;
2475 /* UFR Support - Read Status FR */
2476 if (env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) {
2477 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2479 ((env
->CP0_Status
& (1 << CP0St_FR
)) >> CP0St_FR
);
2481 do_raise_exception(env
, EXCP_RI
, GETPC());
2486 /* FRE Support - read Config5.FRE bit */
2487 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
2488 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2489 arg1
= (env
->CP0_Config5
>> CP0C5_FRE
) & 1;
2491 helper_raise_exception(env
, EXCP_RI
);
2496 arg1
= ((env
->active_fpu
.fcr31
>> 24) & 0xfe) | ((env
->active_fpu
.fcr31
>> 23) & 0x1);
2499 arg1
= env
->active_fpu
.fcr31
& 0x0003f07c;
2502 arg1
= (env
->active_fpu
.fcr31
& 0x00000f83) | ((env
->active_fpu
.fcr31
>> 22) & 0x4);
2505 arg1
= (int32_t)env
->active_fpu
.fcr31
;
2512 void helper_ctc1(CPUMIPSState
*env
, target_ulong arg1
, uint32_t fs
, uint32_t rt
)
2516 /* UFR Alias - Reset Status FR */
2517 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2520 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2521 env
->CP0_Status
&= ~(1 << CP0St_FR
);
2522 compute_hflags(env
);
2524 do_raise_exception(env
, EXCP_RI
, GETPC());
2528 /* UNFR Alias - Set Status FR */
2529 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2532 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2533 env
->CP0_Status
|= (1 << CP0St_FR
);
2534 compute_hflags(env
);
2536 do_raise_exception(env
, EXCP_RI
, GETPC());
2540 /* FRE Support - clear Config5.FRE bit */
2541 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2544 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2545 env
->CP0_Config5
&= ~(1 << CP0C5_FRE
);
2546 compute_hflags(env
);
2548 helper_raise_exception(env
, EXCP_RI
);
2552 /* FRE Support - set Config5.FRE bit */
2553 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2556 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2557 env
->CP0_Config5
|= (1 << CP0C5_FRE
);
2558 compute_hflags(env
);
2560 helper_raise_exception(env
, EXCP_RI
);
2564 if ((env
->insn_flags
& ISA_MIPS32R6
) || (arg1
& 0xffffff00)) {
2567 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0x017fffff) | ((arg1
& 0xfe) << 24) |
2568 ((arg1
& 0x1) << 23);
2571 if (arg1
& 0x007c0000)
2573 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfffc0f83) | (arg1
& 0x0003f07c);
2576 if (arg1
& 0x007c0000)
2578 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfefff07c) | (arg1
& 0x00000f83) |
2579 ((arg1
& 0x4) << 22);
2582 env
->active_fpu
.fcr31
= (arg1
& env
->active_fpu
.fcr31_rw_bitmask
) |
2583 (env
->active_fpu
.fcr31
& ~(env
->active_fpu
.fcr31_rw_bitmask
));
2588 restore_fp_status(env
);
2589 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2590 if ((GET_FP_ENABLE(env
->active_fpu
.fcr31
) | 0x20) & GET_FP_CAUSE(env
->active_fpu
.fcr31
))
2591 do_raise_exception(env
, EXCP_FPE
, GETPC());
2594 int ieee_ex_to_mips(int xcpt
)
2598 if (xcpt
& float_flag_invalid
) {
2601 if (xcpt
& float_flag_overflow
) {
2604 if (xcpt
& float_flag_underflow
) {
2605 ret
|= FP_UNDERFLOW
;
2607 if (xcpt
& float_flag_divbyzero
) {
2610 if (xcpt
& float_flag_inexact
) {
2617 static inline void update_fcr31(CPUMIPSState
*env
, uintptr_t pc
)
2619 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->active_fpu
.fp_status
));
2621 SET_FP_CAUSE(env
->active_fpu
.fcr31
, tmp
);
2624 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2626 if (GET_FP_ENABLE(env
->active_fpu
.fcr31
) & tmp
) {
2627 do_raise_exception(env
, EXCP_FPE
, pc
);
2629 UPDATE_FP_FLAGS(env
->active_fpu
.fcr31
, tmp
);
2635 Single precition routines have a "s" suffix, double precision a
2636 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2637 paired single lower "pl", paired single upper "pu". */
2639 /* unary operations, modifying fp status */
2640 uint64_t helper_float_sqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2642 fdt0
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2643 update_fcr31(env
, GETPC());
2647 uint32_t helper_float_sqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
2649 fst0
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2650 update_fcr31(env
, GETPC());
2654 uint64_t helper_float_cvtd_s(CPUMIPSState
*env
, uint32_t fst0
)
2658 fdt2
= float32_to_float64(fst0
, &env
->active_fpu
.fp_status
);
2659 fdt2
= float64_maybe_silence_nan(fdt2
, &env
->active_fpu
.fp_status
);
2660 update_fcr31(env
, GETPC());
2664 uint64_t helper_float_cvtd_w(CPUMIPSState
*env
, uint32_t wt0
)
2668 fdt2
= int32_to_float64(wt0
, &env
->active_fpu
.fp_status
);
2669 update_fcr31(env
, GETPC());
2673 uint64_t helper_float_cvtd_l(CPUMIPSState
*env
, uint64_t dt0
)
2677 fdt2
= int64_to_float64(dt0
, &env
->active_fpu
.fp_status
);
2678 update_fcr31(env
, GETPC());
2682 uint64_t helper_float_cvt_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2686 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2687 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2688 & (float_flag_invalid
| float_flag_overflow
)) {
2689 dt2
= FP_TO_INT64_OVERFLOW
;
2691 update_fcr31(env
, GETPC());
2695 uint64_t helper_float_cvt_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2699 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2700 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2701 & (float_flag_invalid
| float_flag_overflow
)) {
2702 dt2
= FP_TO_INT64_OVERFLOW
;
2704 update_fcr31(env
, GETPC());
2708 uint64_t helper_float_cvtps_pw(CPUMIPSState
*env
, uint64_t dt0
)
2713 fst2
= int32_to_float32(dt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2714 fsth2
= int32_to_float32(dt0
>> 32, &env
->active_fpu
.fp_status
);
2715 update_fcr31(env
, GETPC());
2716 return ((uint64_t)fsth2
<< 32) | fst2
;
2719 uint64_t helper_float_cvtpw_ps(CPUMIPSState
*env
, uint64_t fdt0
)
2725 wt2
= float32_to_int32(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2726 excp
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2727 if (excp
& (float_flag_overflow
| float_flag_invalid
)) {
2728 wt2
= FP_TO_INT32_OVERFLOW
;
2731 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2732 wth2
= float32_to_int32(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2733 excph
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2734 if (excph
& (float_flag_overflow
| float_flag_invalid
)) {
2735 wth2
= FP_TO_INT32_OVERFLOW
;
2738 set_float_exception_flags(excp
| excph
, &env
->active_fpu
.fp_status
);
2739 update_fcr31(env
, GETPC());
2741 return ((uint64_t)wth2
<< 32) | wt2
;
2744 uint32_t helper_float_cvts_d(CPUMIPSState
*env
, uint64_t fdt0
)
2748 fst2
= float64_to_float32(fdt0
, &env
->active_fpu
.fp_status
);
2749 fst2
= float32_maybe_silence_nan(fst2
, &env
->active_fpu
.fp_status
);
2750 update_fcr31(env
, GETPC());
2754 uint32_t helper_float_cvts_w(CPUMIPSState
*env
, uint32_t wt0
)
2758 fst2
= int32_to_float32(wt0
, &env
->active_fpu
.fp_status
);
2759 update_fcr31(env
, GETPC());
2763 uint32_t helper_float_cvts_l(CPUMIPSState
*env
, uint64_t dt0
)
2767 fst2
= int64_to_float32(dt0
, &env
->active_fpu
.fp_status
);
2768 update_fcr31(env
, GETPC());
2772 uint32_t helper_float_cvts_pl(CPUMIPSState
*env
, uint32_t wt0
)
2777 update_fcr31(env
, GETPC());
2781 uint32_t helper_float_cvts_pu(CPUMIPSState
*env
, uint32_t wth0
)
2786 update_fcr31(env
, GETPC());
2790 uint32_t helper_float_cvt_w_s(CPUMIPSState
*env
, uint32_t fst0
)
2794 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2795 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2796 & (float_flag_invalid
| float_flag_overflow
)) {
2797 wt2
= FP_TO_INT32_OVERFLOW
;
2799 update_fcr31(env
, GETPC());
2803 uint32_t helper_float_cvt_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
2807 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2808 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2809 & (float_flag_invalid
| float_flag_overflow
)) {
2810 wt2
= FP_TO_INT32_OVERFLOW
;
2812 update_fcr31(env
, GETPC());
2816 uint64_t helper_float_round_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2820 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2821 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2822 restore_rounding_mode(env
);
2823 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2824 & (float_flag_invalid
| float_flag_overflow
)) {
2825 dt2
= FP_TO_INT64_OVERFLOW
;
2827 update_fcr31(env
, GETPC());
2831 uint64_t helper_float_round_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2835 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2836 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2837 restore_rounding_mode(env
);
2838 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2839 & (float_flag_invalid
| float_flag_overflow
)) {
2840 dt2
= FP_TO_INT64_OVERFLOW
;
2842 update_fcr31(env
, GETPC());
2846 uint32_t helper_float_round_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
2850 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2851 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2852 restore_rounding_mode(env
);
2853 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2854 & (float_flag_invalid
| float_flag_overflow
)) {
2855 wt2
= FP_TO_INT32_OVERFLOW
;
2857 update_fcr31(env
, GETPC());
2861 uint32_t helper_float_round_w_s(CPUMIPSState
*env
, uint32_t fst0
)
2865 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2866 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2867 restore_rounding_mode(env
);
2868 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2869 & (float_flag_invalid
| float_flag_overflow
)) {
2870 wt2
= FP_TO_INT32_OVERFLOW
;
2872 update_fcr31(env
, GETPC());
2876 uint64_t helper_float_trunc_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2880 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2881 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2882 & (float_flag_invalid
| float_flag_overflow
)) {
2883 dt2
= FP_TO_INT64_OVERFLOW
;
2885 update_fcr31(env
, GETPC());
2889 uint64_t helper_float_trunc_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2893 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2894 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2895 & (float_flag_invalid
| float_flag_overflow
)) {
2896 dt2
= FP_TO_INT64_OVERFLOW
;
2898 update_fcr31(env
, GETPC());
2902 uint32_t helper_float_trunc_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
2906 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2907 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2908 & (float_flag_invalid
| float_flag_overflow
)) {
2909 wt2
= FP_TO_INT32_OVERFLOW
;
2911 update_fcr31(env
, GETPC());
2915 uint32_t helper_float_trunc_w_s(CPUMIPSState
*env
, uint32_t fst0
)
2919 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2920 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2921 & (float_flag_invalid
| float_flag_overflow
)) {
2922 wt2
= FP_TO_INT32_OVERFLOW
;
2924 update_fcr31(env
, GETPC());
2928 uint64_t helper_float_ceil_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2932 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2933 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2934 restore_rounding_mode(env
);
2935 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2936 & (float_flag_invalid
| float_flag_overflow
)) {
2937 dt2
= FP_TO_INT64_OVERFLOW
;
2939 update_fcr31(env
, GETPC());
2943 uint64_t helper_float_ceil_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2947 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2948 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2949 restore_rounding_mode(env
);
2950 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2951 & (float_flag_invalid
| float_flag_overflow
)) {
2952 dt2
= FP_TO_INT64_OVERFLOW
;
2954 update_fcr31(env
, GETPC());
2958 uint32_t helper_float_ceil_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
2962 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2963 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2964 restore_rounding_mode(env
);
2965 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2966 & (float_flag_invalid
| float_flag_overflow
)) {
2967 wt2
= FP_TO_INT32_OVERFLOW
;
2969 update_fcr31(env
, GETPC());
2973 uint32_t helper_float_ceil_w_s(CPUMIPSState
*env
, uint32_t fst0
)
2977 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2978 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2979 restore_rounding_mode(env
);
2980 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2981 & (float_flag_invalid
| float_flag_overflow
)) {
2982 wt2
= FP_TO_INT32_OVERFLOW
;
2984 update_fcr31(env
, GETPC());
2988 uint64_t helper_float_floor_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2992 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2993 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2994 restore_rounding_mode(env
);
2995 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2996 & (float_flag_invalid
| float_flag_overflow
)) {
2997 dt2
= FP_TO_INT64_OVERFLOW
;
2999 update_fcr31(env
, GETPC());
3003 uint64_t helper_float_floor_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3007 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3008 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3009 restore_rounding_mode(env
);
3010 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3011 & (float_flag_invalid
| float_flag_overflow
)) {
3012 dt2
= FP_TO_INT64_OVERFLOW
;
3014 update_fcr31(env
, GETPC());
3018 uint32_t helper_float_floor_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3022 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3023 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3024 restore_rounding_mode(env
);
3025 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3026 & (float_flag_invalid
| float_flag_overflow
)) {
3027 wt2
= FP_TO_INT32_OVERFLOW
;
3029 update_fcr31(env
, GETPC());
3033 uint32_t helper_float_floor_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3037 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3038 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3039 restore_rounding_mode(env
);
3040 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3041 & (float_flag_invalid
| float_flag_overflow
)) {
3042 wt2
= FP_TO_INT32_OVERFLOW
;
3044 update_fcr31(env
, GETPC());
3048 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3052 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3053 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3054 & float_flag_invalid
) {
3055 if (float64_is_any_nan(fdt0
)) {
3059 update_fcr31(env
, GETPC());
3063 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3067 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3068 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3069 & float_flag_invalid
) {
3070 if (float32_is_any_nan(fst0
)) {
3074 update_fcr31(env
, GETPC());
3078 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3082 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3083 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3084 & float_flag_invalid
) {
3085 if (float64_is_any_nan(fdt0
)) {
3089 update_fcr31(env
, GETPC());
3093 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3097 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3098 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3099 & float_flag_invalid
) {
3100 if (float32_is_any_nan(fst0
)) {
3104 update_fcr31(env
, GETPC());
3108 uint64_t helper_float_round_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3112 set_float_rounding_mode(float_round_nearest_even
,
3113 &env
->active_fpu
.fp_status
);
3114 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3115 restore_rounding_mode(env
);
3116 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3117 & float_flag_invalid
) {
3118 if (float64_is_any_nan(fdt0
)) {
3122 update_fcr31(env
, GETPC());
3126 uint64_t helper_float_round_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3130 set_float_rounding_mode(float_round_nearest_even
,
3131 &env
->active_fpu
.fp_status
);
3132 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3133 restore_rounding_mode(env
);
3134 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3135 & float_flag_invalid
) {
3136 if (float32_is_any_nan(fst0
)) {
3140 update_fcr31(env
, GETPC());
3144 uint32_t helper_float_round_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3148 set_float_rounding_mode(float_round_nearest_even
,
3149 &env
->active_fpu
.fp_status
);
3150 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3151 restore_rounding_mode(env
);
3152 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3153 & float_flag_invalid
) {
3154 if (float64_is_any_nan(fdt0
)) {
3158 update_fcr31(env
, GETPC());
3162 uint32_t helper_float_round_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3166 set_float_rounding_mode(float_round_nearest_even
,
3167 &env
->active_fpu
.fp_status
);
3168 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3169 restore_rounding_mode(env
);
3170 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3171 & float_flag_invalid
) {
3172 if (float32_is_any_nan(fst0
)) {
3176 update_fcr31(env
, GETPC());
3180 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3184 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3185 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3186 & float_flag_invalid
) {
3187 if (float64_is_any_nan(fdt0
)) {
3191 update_fcr31(env
, GETPC());
3195 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3199 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3200 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3201 & float_flag_invalid
) {
3202 if (float32_is_any_nan(fst0
)) {
3206 update_fcr31(env
, GETPC());
3210 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3214 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3215 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3216 & float_flag_invalid
) {
3217 if (float64_is_any_nan(fdt0
)) {
3221 update_fcr31(env
, GETPC());
3225 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3229 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3230 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3231 & float_flag_invalid
) {
3232 if (float32_is_any_nan(fst0
)) {
3236 update_fcr31(env
, GETPC());
3240 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3244 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3245 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3246 restore_rounding_mode(env
);
3247 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3248 & float_flag_invalid
) {
3249 if (float64_is_any_nan(fdt0
)) {
3253 update_fcr31(env
, GETPC());
3257 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3261 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3262 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3263 restore_rounding_mode(env
);
3264 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3265 & float_flag_invalid
) {
3266 if (float32_is_any_nan(fst0
)) {
3270 update_fcr31(env
, GETPC());
3274 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3278 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3279 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3280 restore_rounding_mode(env
);
3281 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3282 & float_flag_invalid
) {
3283 if (float64_is_any_nan(fdt0
)) {
3287 update_fcr31(env
, GETPC());
3291 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3295 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3296 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3297 restore_rounding_mode(env
);
3298 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3299 & float_flag_invalid
) {
3300 if (float32_is_any_nan(fst0
)) {
3304 update_fcr31(env
, GETPC());
3308 uint64_t helper_float_floor_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3312 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3313 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3314 restore_rounding_mode(env
);
3315 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3316 & float_flag_invalid
) {
3317 if (float64_is_any_nan(fdt0
)) {
3321 update_fcr31(env
, GETPC());
3325 uint64_t helper_float_floor_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3329 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3330 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3331 restore_rounding_mode(env
);
3332 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3333 & float_flag_invalid
) {
3334 if (float32_is_any_nan(fst0
)) {
3338 update_fcr31(env
, GETPC());
3342 uint32_t helper_float_floor_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3346 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3347 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3348 restore_rounding_mode(env
);
3349 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3350 & float_flag_invalid
) {
3351 if (float64_is_any_nan(fdt0
)) {
3355 update_fcr31(env
, GETPC());
3359 uint32_t helper_float_floor_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3363 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3364 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3365 restore_rounding_mode(env
);
3366 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3367 & float_flag_invalid
) {
3368 if (float32_is_any_nan(fst0
)) {
3372 update_fcr31(env
, GETPC());
3376 /* unary operations, not modifying fp status */
3377 #define FLOAT_UNOP(name) \
3378 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3380 return float64_ ## name(fdt0); \
3382 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3384 return float32_ ## name(fst0); \
3386 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3391 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3392 wth0 = float32_ ## name(fdt0 >> 32); \
3393 return ((uint64_t)wth0 << 32) | wt0; \
3399 /* MIPS specific unary operations */
3400 uint64_t helper_float_recip_d(CPUMIPSState
*env
, uint64_t fdt0
)
3404 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3405 update_fcr31(env
, GETPC());
3409 uint32_t helper_float_recip_s(CPUMIPSState
*env
, uint32_t fst0
)
3413 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3414 update_fcr31(env
, GETPC());
3418 uint64_t helper_float_rsqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
3422 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3423 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3424 update_fcr31(env
, GETPC());
3428 uint32_t helper_float_rsqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
3432 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3433 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3434 update_fcr31(env
, GETPC());
3438 uint64_t helper_float_recip1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3442 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3443 update_fcr31(env
, GETPC());
3447 uint32_t helper_float_recip1_s(CPUMIPSState
*env
, uint32_t fst0
)
3451 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3452 update_fcr31(env
, GETPC());
3456 uint64_t helper_float_recip1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3461 fst2
= float32_div(float32_one
, fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3462 fsth2
= float32_div(float32_one
, fdt0
>> 32, &env
->active_fpu
.fp_status
);
3463 update_fcr31(env
, GETPC());
3464 return ((uint64_t)fsth2
<< 32) | fst2
;
3467 uint64_t helper_float_rsqrt1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3471 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3472 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3473 update_fcr31(env
, GETPC());
3477 uint32_t helper_float_rsqrt1_s(CPUMIPSState
*env
, uint32_t fst0
)
3481 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3482 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3483 update_fcr31(env
, GETPC());
3487 uint64_t helper_float_rsqrt1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3492 fst2
= float32_sqrt(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3493 fsth2
= float32_sqrt(fdt0
>> 32, &env
->active_fpu
.fp_status
);
3494 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3495 fsth2
= float32_div(float32_one
, fsth2
, &env
->active_fpu
.fp_status
);
3496 update_fcr31(env
, GETPC());
3497 return ((uint64_t)fsth2
<< 32) | fst2
;
3500 #define FLOAT_RINT(name, bits) \
3501 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3502 uint ## bits ## _t fs) \
3504 uint ## bits ## _t fdret; \
3506 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3507 update_fcr31(env, GETPC()); \
3511 FLOAT_RINT(rint_s
, 32)
3512 FLOAT_RINT(rint_d
, 64)
3515 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3516 #define FLOAT_CLASS_QUIET_NAN 0x002
3517 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3518 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3519 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3520 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3521 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3522 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3523 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3524 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3526 #define FLOAT_CLASS(name, bits) \
3527 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3528 float_status *status) \
3530 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3531 return FLOAT_CLASS_SIGNALING_NAN; \
3532 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3533 return FLOAT_CLASS_QUIET_NAN; \
3534 } else if (float ## bits ## _is_neg(arg)) { \
3535 if (float ## bits ## _is_infinity(arg)) { \
3536 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3537 } else if (float ## bits ## _is_zero(arg)) { \
3538 return FLOAT_CLASS_NEGATIVE_ZERO; \
3539 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3540 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3542 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3545 if (float ## bits ## _is_infinity(arg)) { \
3546 return FLOAT_CLASS_POSITIVE_INFINITY; \
3547 } else if (float ## bits ## _is_zero(arg)) { \
3548 return FLOAT_CLASS_POSITIVE_ZERO; \
3549 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3550 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3552 return FLOAT_CLASS_POSITIVE_NORMAL; \
3557 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3558 uint ## bits ## _t arg) \
3560 return float_ ## name(arg, &env->active_fpu.fp_status); \
3563 FLOAT_CLASS(class_s
, 32)
3564 FLOAT_CLASS(class_d
, 64)
3567 /* binary operations */
3568 #define FLOAT_BINOP(name) \
3569 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3570 uint64_t fdt0, uint64_t fdt1) \
3574 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3575 update_fcr31(env, GETPC()); \
3579 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3580 uint32_t fst0, uint32_t fst1) \
3584 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3585 update_fcr31(env, GETPC()); \
3589 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3593 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3594 uint32_t fsth0 = fdt0 >> 32; \
3595 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3596 uint32_t fsth1 = fdt1 >> 32; \
3600 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3601 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3602 update_fcr31(env, GETPC()); \
3603 return ((uint64_t)wth2 << 32) | wt2; \
3612 /* MIPS specific binary operations */
3613 uint64_t helper_float_recip2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3615 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3616 fdt2
= float64_chs(float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
));
3617 update_fcr31(env
, GETPC());
3621 uint32_t helper_float_recip2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3623 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3624 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3625 update_fcr31(env
, GETPC());
3629 uint64_t helper_float_recip2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3631 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3632 uint32_t fsth0
= fdt0
>> 32;
3633 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3634 uint32_t fsth2
= fdt2
>> 32;
3636 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3637 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3638 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3639 fsth2
= float32_chs(float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
));
3640 update_fcr31(env
, GETPC());
3641 return ((uint64_t)fsth2
<< 32) | fst2
;
3644 uint64_t helper_float_rsqrt2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3646 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3647 fdt2
= float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
);
3648 fdt2
= float64_chs(float64_div(fdt2
, FLOAT_TWO64
, &env
->active_fpu
.fp_status
));
3649 update_fcr31(env
, GETPC());
3653 uint32_t helper_float_rsqrt2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3655 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3656 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3657 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3658 update_fcr31(env
, GETPC());
3662 uint64_t helper_float_rsqrt2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3664 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3665 uint32_t fsth0
= fdt0
>> 32;
3666 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3667 uint32_t fsth2
= fdt2
>> 32;
3669 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3670 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3671 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3672 fsth2
= float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
);
3673 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3674 fsth2
= float32_chs(float32_div(fsth2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3675 update_fcr31(env
, GETPC());
3676 return ((uint64_t)fsth2
<< 32) | fst2
;
3679 uint64_t helper_float_addr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3681 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3682 uint32_t fsth0
= fdt0
>> 32;
3683 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3684 uint32_t fsth1
= fdt1
>> 32;
3688 fst2
= float32_add (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3689 fsth2
= float32_add (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3690 update_fcr31(env
, GETPC());
3691 return ((uint64_t)fsth2
<< 32) | fst2
;
3694 uint64_t helper_float_mulr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3696 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3697 uint32_t fsth0
= fdt0
>> 32;
3698 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3699 uint32_t fsth1
= fdt1
>> 32;
3703 fst2
= float32_mul (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3704 fsth2
= float32_mul (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3705 update_fcr31(env
, GETPC());
3706 return ((uint64_t)fsth2
<< 32) | fst2
;
3709 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3710 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3711 uint ## bits ## _t fs, \
3712 uint ## bits ## _t ft) \
3714 uint ## bits ## _t fdret; \
3716 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3717 &env->active_fpu.fp_status); \
3718 update_fcr31(env, GETPC()); \
3722 FLOAT_MINMAX(max_s
, 32, maxnum
)
3723 FLOAT_MINMAX(max_d
, 64, maxnum
)
3724 FLOAT_MINMAX(maxa_s
, 32, maxnummag
)
3725 FLOAT_MINMAX(maxa_d
, 64, maxnummag
)
3727 FLOAT_MINMAX(min_s
, 32, minnum
)
3728 FLOAT_MINMAX(min_d
, 64, minnum
)
3729 FLOAT_MINMAX(mina_s
, 32, minnummag
)
3730 FLOAT_MINMAX(mina_d
, 64, minnummag
)
3733 /* ternary operations */
3734 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3736 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3737 if ((flags) & float_muladd_negate_c) { \
3738 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3740 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3742 if ((flags) & float_muladd_negate_result) { \
3743 a = prefix##_chs(a); \
3747 /* FMA based operations */
3748 #define FLOAT_FMA(name, type) \
3749 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3750 uint64_t fdt0, uint64_t fdt1, \
3753 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3754 update_fcr31(env, GETPC()); \
3758 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3759 uint32_t fst0, uint32_t fst1, \
3762 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3763 update_fcr31(env, GETPC()); \
3767 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3768 uint64_t fdt0, uint64_t fdt1, \
3771 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3772 uint32_t fsth0 = fdt0 >> 32; \
3773 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3774 uint32_t fsth1 = fdt1 >> 32; \
3775 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3776 uint32_t fsth2 = fdt2 >> 32; \
3778 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3779 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
3780 update_fcr31(env, GETPC()); \
3781 return ((uint64_t)fsth0 << 32) | fst0; \
3784 FLOAT_FMA(msub
, float_muladd_negate_c
)
3785 FLOAT_FMA(nmadd
, float_muladd_negate_result
)
3786 FLOAT_FMA(nmsub
, float_muladd_negate_result
| float_muladd_negate_c
)
3789 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
3790 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3791 uint ## bits ## _t fs, \
3792 uint ## bits ## _t ft, \
3793 uint ## bits ## _t fd) \
3795 uint ## bits ## _t fdret; \
3797 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
3798 &env->active_fpu.fp_status); \
3799 update_fcr31(env, GETPC()); \
3803 FLOAT_FMADDSUB(maddf_s
, 32, 0)
3804 FLOAT_FMADDSUB(maddf_d
, 64, 0)
3805 FLOAT_FMADDSUB(msubf_s
, 32, float_muladd_negate_product
)
3806 FLOAT_FMADDSUB(msubf_d
, 64, float_muladd_negate_product
)
3807 #undef FLOAT_FMADDSUB
3809 /* compare operations */
3810 #define FOP_COND_D(op, cond) \
3811 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3812 uint64_t fdt1, int cc) \
3816 update_fcr31(env, GETPC()); \
3818 SET_FP_COND(cc, env->active_fpu); \
3820 CLEAR_FP_COND(cc, env->active_fpu); \
3822 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3823 uint64_t fdt1, int cc) \
3826 fdt0 = float64_abs(fdt0); \
3827 fdt1 = float64_abs(fdt1); \
3829 update_fcr31(env, GETPC()); \
3831 SET_FP_COND(cc, env->active_fpu); \
3833 CLEAR_FP_COND(cc, env->active_fpu); \
3836 /* NOTE: the comma operator will make "cond" to eval to false,
3837 * but float64_unordered_quiet() is still called. */
3838 FOP_COND_D(f
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3839 FOP_COND_D(un
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3840 FOP_COND_D(eq
, float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3841 FOP_COND_D(ueq
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3842 FOP_COND_D(olt
, float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3843 FOP_COND_D(ult
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3844 FOP_COND_D(ole
, float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3845 FOP_COND_D(ule
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3846 /* NOTE: the comma operator will make "cond" to eval to false,
3847 * but float64_unordered() is still called. */
3848 FOP_COND_D(sf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3849 FOP_COND_D(ngle
,float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3850 FOP_COND_D(seq
, float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3851 FOP_COND_D(ngl
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3852 FOP_COND_D(lt
, float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3853 FOP_COND_D(nge
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3854 FOP_COND_D(le
, float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3855 FOP_COND_D(ngt
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3857 #define FOP_COND_S(op, cond) \
3858 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3859 uint32_t fst1, int cc) \
3863 update_fcr31(env, GETPC()); \
3865 SET_FP_COND(cc, env->active_fpu); \
3867 CLEAR_FP_COND(cc, env->active_fpu); \
3869 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3870 uint32_t fst1, int cc) \
3873 fst0 = float32_abs(fst0); \
3874 fst1 = float32_abs(fst1); \
3876 update_fcr31(env, GETPC()); \
3878 SET_FP_COND(cc, env->active_fpu); \
3880 CLEAR_FP_COND(cc, env->active_fpu); \
3883 /* NOTE: the comma operator will make "cond" to eval to false,
3884 * but float32_unordered_quiet() is still called. */
3885 FOP_COND_S(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3886 FOP_COND_S(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3887 FOP_COND_S(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3888 FOP_COND_S(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3889 FOP_COND_S(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3890 FOP_COND_S(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3891 FOP_COND_S(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3892 FOP_COND_S(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3893 /* NOTE: the comma operator will make "cond" to eval to false,
3894 * but float32_unordered() is still called. */
3895 FOP_COND_S(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3896 FOP_COND_S(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3897 FOP_COND_S(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3898 FOP_COND_S(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3899 FOP_COND_S(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3900 FOP_COND_S(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3901 FOP_COND_S(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3902 FOP_COND_S(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3904 #define FOP_COND_PS(op, condl, condh) \
3905 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3906 uint64_t fdt1, int cc) \
3908 uint32_t fst0, fsth0, fst1, fsth1; \
3910 fst0 = fdt0 & 0XFFFFFFFF; \
3911 fsth0 = fdt0 >> 32; \
3912 fst1 = fdt1 & 0XFFFFFFFF; \
3913 fsth1 = fdt1 >> 32; \
3916 update_fcr31(env, GETPC()); \
3918 SET_FP_COND(cc, env->active_fpu); \
3920 CLEAR_FP_COND(cc, env->active_fpu); \
3922 SET_FP_COND(cc + 1, env->active_fpu); \
3924 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3926 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3927 uint64_t fdt1, int cc) \
3929 uint32_t fst0, fsth0, fst1, fsth1; \
3931 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3932 fsth0 = float32_abs(fdt0 >> 32); \
3933 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3934 fsth1 = float32_abs(fdt1 >> 32); \
3937 update_fcr31(env, GETPC()); \
3939 SET_FP_COND(cc, env->active_fpu); \
3941 CLEAR_FP_COND(cc, env->active_fpu); \
3943 SET_FP_COND(cc + 1, env->active_fpu); \
3945 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3948 /* NOTE: the comma operator will make "cond" to eval to false,
3949 * but float32_unordered_quiet() is still called. */
3950 FOP_COND_PS(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3951 (float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3952 FOP_COND_PS(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3953 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3954 FOP_COND_PS(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3955 float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3956 FOP_COND_PS(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3957 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3958 FOP_COND_PS(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3959 float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3960 FOP_COND_PS(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3961 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3962 FOP_COND_PS(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3963 float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3964 FOP_COND_PS(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3965 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3966 /* NOTE: the comma operator will make "cond" to eval to false,
3967 * but float32_unordered() is still called. */
3968 FOP_COND_PS(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3969 (float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3970 FOP_COND_PS(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3971 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3972 FOP_COND_PS(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3973 float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3974 FOP_COND_PS(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3975 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3976 FOP_COND_PS(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3977 float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3978 FOP_COND_PS(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3979 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3980 FOP_COND_PS(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3981 float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3982 FOP_COND_PS(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3983 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3985 /* R6 compare operations */
3986 #define FOP_CONDN_D(op, cond) \
3987 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
3992 update_fcr31(env, GETPC()); \
4000 /* NOTE: the comma operator will make "cond" to eval to false,
4001 * but float64_unordered_quiet() is still called. */
4002 FOP_CONDN_D(af
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4003 FOP_CONDN_D(un
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
4004 FOP_CONDN_D(eq
, (float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4005 FOP_CONDN_D(ueq
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4006 || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4007 FOP_CONDN_D(lt
, (float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4008 FOP_CONDN_D(ult
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4009 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4010 FOP_CONDN_D(le
, (float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4011 FOP_CONDN_D(ule
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4012 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4013 /* NOTE: the comma operator will make "cond" to eval to false,
4014 * but float64_unordered() is still called. */
4015 FOP_CONDN_D(saf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4016 FOP_CONDN_D(sun
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
4017 FOP_CONDN_D(seq
, (float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4018 FOP_CONDN_D(sueq
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4019 || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4020 FOP_CONDN_D(slt
, (float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4021 FOP_CONDN_D(sult
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4022 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4023 FOP_CONDN_D(sle
, (float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4024 FOP_CONDN_D(sule
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4025 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4026 FOP_CONDN_D(or, (float64_le_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4027 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4028 FOP_CONDN_D(une
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4029 || float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4030 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4031 FOP_CONDN_D(ne
, (float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4032 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4033 FOP_CONDN_D(sor
, (float64_le(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4034 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4035 FOP_CONDN_D(sune
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4036 || float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4037 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4038 FOP_CONDN_D(sne
, (float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4039 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4041 #define FOP_CONDN_S(op, cond) \
4042 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4047 update_fcr31(env, GETPC()); \
4055 /* NOTE: the comma operator will make "cond" to eval to false,
4056 * but float32_unordered_quiet() is still called. */
4057 FOP_CONDN_S(af
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4058 FOP_CONDN_S(un
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
4059 FOP_CONDN_S(eq
, (float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4060 FOP_CONDN_S(ueq
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4061 || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4062 FOP_CONDN_S(lt
, (float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4063 FOP_CONDN_S(ult
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4064 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4065 FOP_CONDN_S(le
, (float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4066 FOP_CONDN_S(ule
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4067 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4068 /* NOTE: the comma operator will make "cond" to eval to false,
4069 * but float32_unordered() is still called. */
4070 FOP_CONDN_S(saf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4071 FOP_CONDN_S(sun
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
4072 FOP_CONDN_S(seq
, (float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4073 FOP_CONDN_S(sueq
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4074 || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4075 FOP_CONDN_S(slt
, (float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4076 FOP_CONDN_S(sult
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4077 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4078 FOP_CONDN_S(sle
, (float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4079 FOP_CONDN_S(sule
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4080 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4081 FOP_CONDN_S(or, (float32_le_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4082 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4083 FOP_CONDN_S(une
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4084 || float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4085 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4086 FOP_CONDN_S(ne
, (float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4087 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4088 FOP_CONDN_S(sor
, (float32_le(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4089 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4090 FOP_CONDN_S(sune
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4091 || float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4092 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4093 FOP_CONDN_S(sne
, (float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4094 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4097 /* Data format min and max values */
4098 #define DF_BITS(df) (1 << ((df) + 3))
4100 /* Element-by-element access macros */
4101 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4103 #if !defined(CONFIG_USER_ONLY)
4104 #define MEMOP_IDX(DF) \
4105 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4106 cpu_mmu_index(env, false));
4108 #define MEMOP_IDX(DF)
4111 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
4112 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4113 target_ulong addr) \
4115 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4119 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4120 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
4122 memcpy(pwd, &wx, sizeof(wr_t)); \
4125 #if !defined(CONFIG_USER_ONLY)
4126 MSA_LD_DF(DF_BYTE
, b
, helper_ret_ldub_mmu
, oi
, GETPC())
4127 MSA_LD_DF(DF_HALF
, h
, helper_ret_lduw_mmu
, oi
, GETPC())
4128 MSA_LD_DF(DF_WORD
, w
, helper_ret_ldul_mmu
, oi
, GETPC())
4129 MSA_LD_DF(DF_DOUBLE
, d
, helper_ret_ldq_mmu
, oi
, GETPC())
4131 MSA_LD_DF(DF_BYTE
, b
, cpu_ldub_data
)
4132 MSA_LD_DF(DF_HALF
, h
, cpu_lduw_data
)
4133 MSA_LD_DF(DF_WORD
, w
, cpu_ldl_data
)
4134 MSA_LD_DF(DF_DOUBLE
, d
, cpu_ldq_data
)
4137 #define MSA_PAGESPAN(x) \
4138 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4140 static inline void ensure_writable_pages(CPUMIPSState
*env
,
4145 #if !defined(CONFIG_USER_ONLY)
4146 target_ulong page_addr
;
4147 if (unlikely(MSA_PAGESPAN(addr
))) {
4149 probe_write(env
, addr
, mmu_idx
, retaddr
);
4151 page_addr
= (addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
4152 probe_write(env
, page_addr
, mmu_idx
, retaddr
);
4157 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
4158 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4159 target_ulong addr) \
4161 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4162 int mmu_idx = cpu_mmu_index(env, false); \
4165 ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
4166 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4167 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
4171 #if !defined(CONFIG_USER_ONLY)
4172 MSA_ST_DF(DF_BYTE
, b
, helper_ret_stb_mmu
, oi
, GETPC())
4173 MSA_ST_DF(DF_HALF
, h
, helper_ret_stw_mmu
, oi
, GETPC())
4174 MSA_ST_DF(DF_WORD
, w
, helper_ret_stl_mmu
, oi
, GETPC())
4175 MSA_ST_DF(DF_DOUBLE
, d
, helper_ret_stq_mmu
, oi
, GETPC())
4177 MSA_ST_DF(DF_BYTE
, b
, cpu_stb_data
)
4178 MSA_ST_DF(DF_HALF
, h
, cpu_stw_data
)
4179 MSA_ST_DF(DF_WORD
, w
, cpu_stl_data
)
4180 MSA_ST_DF(DF_DOUBLE
, d
, cpu_stq_data
)
4183 void helper_cache(CPUMIPSState
*env
, target_ulong addr
, uint32_t op
)
4185 #ifndef CONFIG_USER_ONLY
4186 target_ulong index
= addr
& 0x1fffffff;
4188 /* Index Store Tag */
4189 memory_region_dispatch_write(env
->itc_tag
, index
, env
->CP0_TagLo
,
4190 8, MEMTXATTRS_UNSPECIFIED
);
4191 } else if (op
== 5) {
4192 /* Index Load Tag */
4193 memory_region_dispatch_read(env
->itc_tag
, index
, &env
->CP0_TagLo
,
4194 8, MEMTXATTRS_UNSPECIFIED
);