2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
23 #include "qemu/host-utils.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "sysemu/kvm.h"
29 /*****************************************************************************/
30 /* Exceptions processing helpers */
32 void helper_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
35 do_raise_exception_err(env
, exception
, error_code
, 0);
38 void helper_raise_exception(CPUMIPSState
*env
, uint32_t exception
)
40 do_raise_exception(env
, exception
, GETPC());
43 void helper_raise_exception_debug(CPUMIPSState
*env
)
45 do_raise_exception(env
, EXCP_DEBUG
, 0);
48 static void raise_exception(CPUMIPSState
*env
, uint32_t exception
)
50 do_raise_exception(env
, exception
, 0);
53 #if defined(CONFIG_USER_ONLY)
54 #define HELPER_LD(name, insn, type) \
55 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
56 int mem_idx, uintptr_t retaddr) \
58 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
61 #define HELPER_LD(name, insn, type) \
62 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
63 int mem_idx, uintptr_t retaddr) \
67 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
68 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
70 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
71 case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \
75 HELPER_LD(lw
, ldl
, int32_t)
76 #if defined(TARGET_MIPS64)
77 HELPER_LD(ld
, ldq
, int64_t)
81 #if defined(CONFIG_USER_ONLY)
82 #define HELPER_ST(name, insn, type) \
83 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
84 type val, int mem_idx, uintptr_t retaddr) \
86 cpu_##insn##_data_ra(env, addr, val, retaddr); \
89 #define HELPER_ST(name, insn, type) \
90 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
91 type val, int mem_idx, uintptr_t retaddr) \
95 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
96 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
98 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
100 cpu_##insn##_error_ra(env, addr, val, retaddr); \
105 HELPER_ST(sb
, stb
, uint8_t)
106 HELPER_ST(sw
, stl
, uint32_t)
107 #if defined(TARGET_MIPS64)
108 HELPER_ST(sd
, stq
, uint64_t)
112 /* 64 bits arithmetic for 32 bits hosts */
113 static inline uint64_t get_HILO(CPUMIPSState
*env
)
115 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) | (uint32_t)env
->active_tc
.LO
[0];
118 static inline target_ulong
set_HIT0_LO(CPUMIPSState
*env
, uint64_t HILO
)
120 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
121 return env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
124 static inline target_ulong
set_HI_LOT0(CPUMIPSState
*env
, uint64_t HILO
)
126 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
127 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
131 /* Multiplication variants of the vr54xx. */
132 target_ulong
helper_muls(CPUMIPSState
*env
, target_ulong arg1
,
135 return set_HI_LOT0(env
, 0 - ((int64_t)(int32_t)arg1
*
136 (int64_t)(int32_t)arg2
));
139 target_ulong
helper_mulsu(CPUMIPSState
*env
, target_ulong arg1
,
142 return set_HI_LOT0(env
, 0 - (uint64_t)(uint32_t)arg1
*
143 (uint64_t)(uint32_t)arg2
);
146 target_ulong
helper_macc(CPUMIPSState
*env
, target_ulong arg1
,
149 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
150 (int64_t)(int32_t)arg2
);
153 target_ulong
helper_macchi(CPUMIPSState
*env
, target_ulong arg1
,
156 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
157 (int64_t)(int32_t)arg2
);
160 target_ulong
helper_maccu(CPUMIPSState
*env
, target_ulong arg1
,
163 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) +
164 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
167 target_ulong
helper_macchiu(CPUMIPSState
*env
, target_ulong arg1
,
170 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) +
171 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
174 target_ulong
helper_msac(CPUMIPSState
*env
, target_ulong arg1
,
177 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
178 (int64_t)(int32_t)arg2
);
181 target_ulong
helper_msachi(CPUMIPSState
*env
, target_ulong arg1
,
184 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
185 (int64_t)(int32_t)arg2
);
188 target_ulong
helper_msacu(CPUMIPSState
*env
, target_ulong arg1
,
191 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) -
192 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
195 target_ulong
helper_msachiu(CPUMIPSState
*env
, target_ulong arg1
,
198 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) -
199 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
202 target_ulong
helper_mulhi(CPUMIPSState
*env
, target_ulong arg1
,
205 return set_HIT0_LO(env
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
208 target_ulong
helper_mulhiu(CPUMIPSState
*env
, target_ulong arg1
,
211 return set_HIT0_LO(env
, (uint64_t)(uint32_t)arg1
*
212 (uint64_t)(uint32_t)arg2
);
215 target_ulong
helper_mulshi(CPUMIPSState
*env
, target_ulong arg1
,
218 return set_HIT0_LO(env
, 0 - (int64_t)(int32_t)arg1
*
219 (int64_t)(int32_t)arg2
);
222 target_ulong
helper_mulshiu(CPUMIPSState
*env
, target_ulong arg1
,
225 return set_HIT0_LO(env
, 0 - (uint64_t)(uint32_t)arg1
*
226 (uint64_t)(uint32_t)arg2
);
229 static inline target_ulong
bitswap(target_ulong v
)
231 v
= ((v
>> 1) & (target_ulong
)0x5555555555555555ULL
) |
232 ((v
& (target_ulong
)0x5555555555555555ULL
) << 1);
233 v
= ((v
>> 2) & (target_ulong
)0x3333333333333333ULL
) |
234 ((v
& (target_ulong
)0x3333333333333333ULL
) << 2);
235 v
= ((v
>> 4) & (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) |
236 ((v
& (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) << 4);
241 target_ulong
helper_dbitswap(target_ulong rt
)
247 target_ulong
helper_bitswap(target_ulong rt
)
249 return (int32_t)bitswap(rt
);
252 #ifndef CONFIG_USER_ONLY
254 static inline hwaddr
do_translate_address(CPUMIPSState
*env
,
255 target_ulong address
,
256 int rw
, uintptr_t retaddr
)
259 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
261 lladdr
= cpu_mips_translate_address(env
, address
, rw
);
263 if (lladdr
== -1LL) {
264 cpu_loop_exit_restore(cs
, retaddr
);
270 #define HELPER_LD_ATOMIC(name, insn, almask) \
271 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
273 if (arg & almask) { \
274 if (!(env->hflags & MIPS_HFLAG_DM)) { \
275 env->CP0_BadVAddr = arg; \
277 do_raise_exception(env, EXCP_AdEL, GETPC()); \
279 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
280 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
283 HELPER_LD_ATOMIC(ll
, lw
, 0x3)
285 HELPER_LD_ATOMIC(lld
, ld
, 0x7)
287 #undef HELPER_LD_ATOMIC
289 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
290 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
291 target_ulong arg2, int mem_idx) \
295 if (arg2 & almask) { \
296 if (!(env->hflags & MIPS_HFLAG_DM)) { \
297 env->CP0_BadVAddr = arg2; \
299 do_raise_exception(env, EXCP_AdES, GETPC()); \
301 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
302 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
303 if (tmp == env->llval) { \
304 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
310 HELPER_ST_ATOMIC(sc
, lw
, sw
, 0x3)
312 HELPER_ST_ATOMIC(scd
, ld
, sd
, 0x7)
314 #undef HELPER_ST_ATOMIC
317 #ifdef TARGET_WORDS_BIGENDIAN
318 #define GET_LMASK(v) ((v) & 3)
319 #define GET_OFFSET(addr, offset) (addr + (offset))
321 #define GET_LMASK(v) (((v) & 3) ^ 3)
322 #define GET_OFFSET(addr, offset) (addr - (offset))
325 void helper_swl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
328 do_sb(env
, arg2
, (uint8_t)(arg1
>> 24), mem_idx
, GETPC());
330 if (GET_LMASK(arg2
) <= 2) {
331 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16), mem_idx
,
335 if (GET_LMASK(arg2
) <= 1) {
336 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8), mem_idx
,
340 if (GET_LMASK(arg2
) == 0) {
341 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)arg1
, mem_idx
,
346 void helper_swr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
349 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
351 if (GET_LMASK(arg2
) >= 1) {
352 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
356 if (GET_LMASK(arg2
) >= 2) {
357 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
361 if (GET_LMASK(arg2
) == 3) {
362 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
367 #if defined(TARGET_MIPS64)
368 /* "half" load and stores. We must do the memory access inline,
369 or fault handling won't work. */
371 #ifdef TARGET_WORDS_BIGENDIAN
372 #define GET_LMASK64(v) ((v) & 7)
374 #define GET_LMASK64(v) (((v) & 7) ^ 7)
377 void helper_sdl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
380 do_sb(env
, arg2
, (uint8_t)(arg1
>> 56), mem_idx
, GETPC());
382 if (GET_LMASK64(arg2
) <= 6) {
383 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48), mem_idx
,
387 if (GET_LMASK64(arg2
) <= 5) {
388 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40), mem_idx
,
392 if (GET_LMASK64(arg2
) <= 4) {
393 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32), mem_idx
,
397 if (GET_LMASK64(arg2
) <= 3) {
398 do_sb(env
, GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24), mem_idx
,
402 if (GET_LMASK64(arg2
) <= 2) {
403 do_sb(env
, GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16), mem_idx
,
407 if (GET_LMASK64(arg2
) <= 1) {
408 do_sb(env
, GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8), mem_idx
,
412 if (GET_LMASK64(arg2
) <= 0) {
413 do_sb(env
, GET_OFFSET(arg2
, 7), (uint8_t)arg1
, mem_idx
,
418 void helper_sdr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
421 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
423 if (GET_LMASK64(arg2
) >= 1) {
424 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
428 if (GET_LMASK64(arg2
) >= 2) {
429 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
433 if (GET_LMASK64(arg2
) >= 3) {
434 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
438 if (GET_LMASK64(arg2
) >= 4) {
439 do_sb(env
, GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32), mem_idx
,
443 if (GET_LMASK64(arg2
) >= 5) {
444 do_sb(env
, GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40), mem_idx
,
448 if (GET_LMASK64(arg2
) >= 6) {
449 do_sb(env
, GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48), mem_idx
,
453 if (GET_LMASK64(arg2
) == 7) {
454 do_sb(env
, GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56), mem_idx
,
458 #endif /* TARGET_MIPS64 */
460 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
462 void helper_lwm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
465 target_ulong base_reglist
= reglist
& 0xf;
466 target_ulong do_r31
= reglist
& 0x10;
468 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
471 for (i
= 0; i
< base_reglist
; i
++) {
472 env
->active_tc
.gpr
[multiple_regs
[i
]] =
473 (target_long
)do_lw(env
, addr
, mem_idx
, GETPC());
479 env
->active_tc
.gpr
[31] = (target_long
)do_lw(env
, addr
, mem_idx
,
484 void helper_swm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
487 target_ulong base_reglist
= reglist
& 0xf;
488 target_ulong do_r31
= reglist
& 0x10;
490 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
493 for (i
= 0; i
< base_reglist
; i
++) {
494 do_sw(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
501 do_sw(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
505 #if defined(TARGET_MIPS64)
506 void helper_ldm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
509 target_ulong base_reglist
= reglist
& 0xf;
510 target_ulong do_r31
= reglist
& 0x10;
512 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
515 for (i
= 0; i
< base_reglist
; i
++) {
516 env
->active_tc
.gpr
[multiple_regs
[i
]] = do_ld(env
, addr
, mem_idx
,
523 env
->active_tc
.gpr
[31] = do_ld(env
, addr
, mem_idx
, GETPC());
527 void helper_sdm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
530 target_ulong base_reglist
= reglist
& 0xf;
531 target_ulong do_r31
= reglist
& 0x10;
533 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
536 for (i
= 0; i
< base_reglist
; i
++) {
537 do_sd(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
544 do_sd(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
549 #ifndef CONFIG_USER_ONLY
551 static bool mips_vpe_is_wfi(MIPSCPU
*c
)
553 CPUState
*cpu
= CPU(c
);
554 CPUMIPSState
*env
= &c
->env
;
556 /* If the VPE is halted but otherwise active, it means it's waiting for
558 return cpu
->halted
&& mips_vpe_active(env
);
561 static bool mips_vp_is_wfi(MIPSCPU
*c
)
563 CPUState
*cpu
= CPU(c
);
564 CPUMIPSState
*env
= &c
->env
;
566 return cpu
->halted
&& mips_vp_active(env
);
569 static inline void mips_vpe_wake(MIPSCPU
*c
)
571 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
572 because there might be other conditions that state that c should
574 cpu_interrupt(CPU(c
), CPU_INTERRUPT_WAKE
);
577 static inline void mips_vpe_sleep(MIPSCPU
*cpu
)
579 CPUState
*cs
= CPU(cpu
);
581 /* The VPE was shut off, really go to bed.
582 Reset any old _WAKE requests. */
584 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
587 static inline void mips_tc_wake(MIPSCPU
*cpu
, int tc
)
589 CPUMIPSState
*c
= &cpu
->env
;
591 /* FIXME: TC reschedule. */
592 if (mips_vpe_active(c
) && !mips_vpe_is_wfi(cpu
)) {
597 static inline void mips_tc_sleep(MIPSCPU
*cpu
, int tc
)
599 CPUMIPSState
*c
= &cpu
->env
;
601 /* FIXME: TC reschedule. */
602 if (!mips_vpe_active(c
)) {
609 * @env: CPU from which mapping is performed.
610 * @tc: Should point to an int with the value of the global TC index.
612 * This function will transform @tc into a local index within the
613 * returned #CPUMIPSState.
615 /* FIXME: This code assumes that all VPEs have the same number of TCs,
616 which depends on runtime setup. Can probably be fixed by
617 walking the list of CPUMIPSStates. */
618 static CPUMIPSState
*mips_cpu_map_tc(CPUMIPSState
*env
, int *tc
)
626 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))) {
627 /* Not allowed to address other CPUs. */
628 *tc
= env
->current_tc
;
632 cs
= CPU(mips_env_get_cpu(env
));
633 vpe_idx
= tc_idx
/ cs
->nr_threads
;
634 *tc
= tc_idx
% cs
->nr_threads
;
635 other_cs
= qemu_get_cpu(vpe_idx
);
636 if (other_cs
== NULL
) {
639 cpu
= MIPS_CPU(other_cs
);
643 /* The per VPE CP0_Status register shares some fields with the per TC
644 CP0_TCStatus registers. These fields are wired to the same registers,
645 so changes to either of them should be reflected on both registers.
647 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
649 These helper call synchronizes the regs for a given cpu. */
651 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
652 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
655 /* Called for updates to CP0_TCStatus. */
656 static void sync_c0_tcstatus(CPUMIPSState
*cpu
, int tc
,
660 uint32_t tcu
, tmx
, tasid
, tksu
;
661 uint32_t mask
= ((1U << CP0St_CU3
)
668 tcu
= (v
>> CP0TCSt_TCU0
) & 0xf;
669 tmx
= (v
>> CP0TCSt_TMX
) & 0x1;
670 tasid
= v
& cpu
->CP0_EntryHi_ASID_mask
;
671 tksu
= (v
>> CP0TCSt_TKSU
) & 0x3;
673 status
= tcu
<< CP0St_CU0
;
674 status
|= tmx
<< CP0St_MX
;
675 status
|= tksu
<< CP0St_KSU
;
677 cpu
->CP0_Status
&= ~mask
;
678 cpu
->CP0_Status
|= status
;
680 /* Sync the TASID with EntryHi. */
681 cpu
->CP0_EntryHi
&= ~cpu
->CP0_EntryHi_ASID_mask
;
682 cpu
->CP0_EntryHi
|= tasid
;
687 /* Called for updates to CP0_EntryHi. */
688 static void sync_c0_entryhi(CPUMIPSState
*cpu
, int tc
)
691 uint32_t asid
, v
= cpu
->CP0_EntryHi
;
693 asid
= v
& cpu
->CP0_EntryHi_ASID_mask
;
695 if (tc
== cpu
->current_tc
) {
696 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
698 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
701 *tcst
&= ~cpu
->CP0_EntryHi_ASID_mask
;
706 target_ulong
helper_mfc0_mvpcontrol(CPUMIPSState
*env
)
708 return env
->mvp
->CP0_MVPControl
;
711 target_ulong
helper_mfc0_mvpconf0(CPUMIPSState
*env
)
713 return env
->mvp
->CP0_MVPConf0
;
716 target_ulong
helper_mfc0_mvpconf1(CPUMIPSState
*env
)
718 return env
->mvp
->CP0_MVPConf1
;
721 target_ulong
helper_mfc0_random(CPUMIPSState
*env
)
723 return (int32_t)cpu_mips_get_random(env
);
726 target_ulong
helper_mfc0_tcstatus(CPUMIPSState
*env
)
728 return env
->active_tc
.CP0_TCStatus
;
731 target_ulong
helper_mftc0_tcstatus(CPUMIPSState
*env
)
733 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
734 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
736 if (other_tc
== other
->current_tc
)
737 return other
->active_tc
.CP0_TCStatus
;
739 return other
->tcs
[other_tc
].CP0_TCStatus
;
742 target_ulong
helper_mfc0_tcbind(CPUMIPSState
*env
)
744 return env
->active_tc
.CP0_TCBind
;
747 target_ulong
helper_mftc0_tcbind(CPUMIPSState
*env
)
749 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
750 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
752 if (other_tc
== other
->current_tc
)
753 return other
->active_tc
.CP0_TCBind
;
755 return other
->tcs
[other_tc
].CP0_TCBind
;
758 target_ulong
helper_mfc0_tcrestart(CPUMIPSState
*env
)
760 return env
->active_tc
.PC
;
763 target_ulong
helper_mftc0_tcrestart(CPUMIPSState
*env
)
765 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
766 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
768 if (other_tc
== other
->current_tc
)
769 return other
->active_tc
.PC
;
771 return other
->tcs
[other_tc
].PC
;
774 target_ulong
helper_mfc0_tchalt(CPUMIPSState
*env
)
776 return env
->active_tc
.CP0_TCHalt
;
779 target_ulong
helper_mftc0_tchalt(CPUMIPSState
*env
)
781 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
782 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
784 if (other_tc
== other
->current_tc
)
785 return other
->active_tc
.CP0_TCHalt
;
787 return other
->tcs
[other_tc
].CP0_TCHalt
;
790 target_ulong
helper_mfc0_tccontext(CPUMIPSState
*env
)
792 return env
->active_tc
.CP0_TCContext
;
795 target_ulong
helper_mftc0_tccontext(CPUMIPSState
*env
)
797 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
798 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
800 if (other_tc
== other
->current_tc
)
801 return other
->active_tc
.CP0_TCContext
;
803 return other
->tcs
[other_tc
].CP0_TCContext
;
806 target_ulong
helper_mfc0_tcschedule(CPUMIPSState
*env
)
808 return env
->active_tc
.CP0_TCSchedule
;
811 target_ulong
helper_mftc0_tcschedule(CPUMIPSState
*env
)
813 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
814 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
816 if (other_tc
== other
->current_tc
)
817 return other
->active_tc
.CP0_TCSchedule
;
819 return other
->tcs
[other_tc
].CP0_TCSchedule
;
822 target_ulong
helper_mfc0_tcschefback(CPUMIPSState
*env
)
824 return env
->active_tc
.CP0_TCScheFBack
;
827 target_ulong
helper_mftc0_tcschefback(CPUMIPSState
*env
)
829 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
830 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
832 if (other_tc
== other
->current_tc
)
833 return other
->active_tc
.CP0_TCScheFBack
;
835 return other
->tcs
[other_tc
].CP0_TCScheFBack
;
838 target_ulong
helper_mfc0_count(CPUMIPSState
*env
)
841 qemu_mutex_lock_iothread();
842 count
= (int32_t) cpu_mips_get_count(env
);
843 qemu_mutex_unlock_iothread();
847 target_ulong
helper_mftc0_entryhi(CPUMIPSState
*env
)
849 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
850 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
852 return other
->CP0_EntryHi
;
855 target_ulong
helper_mftc0_cause(CPUMIPSState
*env
)
857 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
859 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
861 if (other_tc
== other
->current_tc
) {
862 tccause
= other
->CP0_Cause
;
864 tccause
= other
->CP0_Cause
;
870 target_ulong
helper_mftc0_status(CPUMIPSState
*env
)
872 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
873 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
875 return other
->CP0_Status
;
878 target_ulong
helper_mfc0_lladdr(CPUMIPSState
*env
)
880 return (int32_t)(env
->lladdr
>> env
->CP0_LLAddr_shift
);
883 target_ulong
helper_mfc0_maar(CPUMIPSState
*env
)
885 return (int32_t) env
->CP0_MAAR
[env
->CP0_MAARI
];
888 target_ulong
helper_mfhc0_maar(CPUMIPSState
*env
)
890 return env
->CP0_MAAR
[env
->CP0_MAARI
] >> 32;
893 target_ulong
helper_mfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
895 return (int32_t)env
->CP0_WatchLo
[sel
];
898 target_ulong
helper_mfc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
900 return env
->CP0_WatchHi
[sel
];
903 target_ulong
helper_mfc0_debug(CPUMIPSState
*env
)
905 target_ulong t0
= env
->CP0_Debug
;
906 if (env
->hflags
& MIPS_HFLAG_DM
)
912 target_ulong
helper_mftc0_debug(CPUMIPSState
*env
)
914 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
916 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
918 if (other_tc
== other
->current_tc
)
919 tcstatus
= other
->active_tc
.CP0_Debug_tcstatus
;
921 tcstatus
= other
->tcs
[other_tc
].CP0_Debug_tcstatus
;
923 /* XXX: Might be wrong, check with EJTAG spec. */
924 return (other
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
925 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
928 #if defined(TARGET_MIPS64)
929 target_ulong
helper_dmfc0_tcrestart(CPUMIPSState
*env
)
931 return env
->active_tc
.PC
;
934 target_ulong
helper_dmfc0_tchalt(CPUMIPSState
*env
)
936 return env
->active_tc
.CP0_TCHalt
;
939 target_ulong
helper_dmfc0_tccontext(CPUMIPSState
*env
)
941 return env
->active_tc
.CP0_TCContext
;
944 target_ulong
helper_dmfc0_tcschedule(CPUMIPSState
*env
)
946 return env
->active_tc
.CP0_TCSchedule
;
949 target_ulong
helper_dmfc0_tcschefback(CPUMIPSState
*env
)
951 return env
->active_tc
.CP0_TCScheFBack
;
954 target_ulong
helper_dmfc0_lladdr(CPUMIPSState
*env
)
956 return env
->lladdr
>> env
->CP0_LLAddr_shift
;
959 target_ulong
helper_dmfc0_maar(CPUMIPSState
*env
)
961 return env
->CP0_MAAR
[env
->CP0_MAARI
];
964 target_ulong
helper_dmfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
966 return env
->CP0_WatchLo
[sel
];
968 #endif /* TARGET_MIPS64 */
970 void helper_mtc0_index(CPUMIPSState
*env
, target_ulong arg1
)
972 uint32_t index_p
= env
->CP0_Index
& 0x80000000;
973 uint32_t tlb_index
= arg1
& 0x7fffffff;
974 if (tlb_index
< env
->tlb
->nb_tlb
) {
975 if (env
->insn_flags
& ISA_MIPS32R6
) {
976 index_p
|= arg1
& 0x80000000;
978 env
->CP0_Index
= index_p
| tlb_index
;
982 void helper_mtc0_mvpcontrol(CPUMIPSState
*env
, target_ulong arg1
)
987 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
988 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
990 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
991 mask
|= (1 << CP0MVPCo_STLB
);
992 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
994 // TODO: Enable/disable shared TLB, enable/disable VPEs.
996 env
->mvp
->CP0_MVPControl
= newval
;
999 void helper_mtc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1004 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1005 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1006 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1008 /* Yield scheduler intercept not implemented. */
1009 /* Gating storage scheduler intercept not implemented. */
1011 // TODO: Enable/disable TCs.
1013 env
->CP0_VPEControl
= newval
;
1016 void helper_mttc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1018 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1019 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1023 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1024 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1025 newval
= (other
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1027 /* TODO: Enable/disable TCs. */
1029 other
->CP0_VPEControl
= newval
;
1032 target_ulong
helper_mftc0_vpecontrol(CPUMIPSState
*env
)
1034 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1035 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1036 /* FIXME: Mask away return zero on read bits. */
1037 return other
->CP0_VPEControl
;
1040 target_ulong
helper_mftc0_vpeconf0(CPUMIPSState
*env
)
1042 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1043 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1045 return other
->CP0_VPEConf0
;
1048 void helper_mtc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1053 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
1054 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
1055 mask
|= (0xff << CP0VPEC0_XTC
);
1056 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1058 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1060 // TODO: TC exclusive handling due to ERL/EXL.
1062 env
->CP0_VPEConf0
= newval
;
1065 void helper_mttc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1067 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1068 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1072 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1073 newval
= (other
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1075 /* TODO: TC exclusive handling due to ERL/EXL. */
1076 other
->CP0_VPEConf0
= newval
;
1079 void helper_mtc0_vpeconf1(CPUMIPSState
*env
, target_ulong arg1
)
1084 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1085 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
1086 (0xff << CP0VPEC1_NCP1
);
1087 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
1089 /* UDI not implemented. */
1090 /* CP2 not implemented. */
1092 // TODO: Handle FPU (CP1) binding.
1094 env
->CP0_VPEConf1
= newval
;
1097 void helper_mtc0_yqmask(CPUMIPSState
*env
, target_ulong arg1
)
1099 /* Yield qualifier inputs not implemented. */
1100 env
->CP0_YQMask
= 0x00000000;
1103 void helper_mtc0_vpeopt(CPUMIPSState
*env
, target_ulong arg1
)
1105 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
1108 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1110 void helper_mtc0_entrylo0(CPUMIPSState
*env
, target_ulong arg1
)
1112 /* 1k pages not implemented */
1113 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1114 env
->CP0_EntryLo0
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1115 | (rxi
<< (CP0EnLo_XI
- 30));
1118 #if defined(TARGET_MIPS64)
1119 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1121 void helper_dmtc0_entrylo0(CPUMIPSState
*env
, uint64_t arg1
)
1123 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1124 env
->CP0_EntryLo0
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1128 void helper_mtc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1130 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
1133 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
1135 env
->active_tc
.CP0_TCStatus
= newval
;
1136 sync_c0_tcstatus(env
, env
->current_tc
, newval
);
1139 void helper_mttc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1141 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1142 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1144 if (other_tc
== other
->current_tc
)
1145 other
->active_tc
.CP0_TCStatus
= arg1
;
1147 other
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
1148 sync_c0_tcstatus(other
, other_tc
, arg1
);
1151 void helper_mtc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1153 uint32_t mask
= (1 << CP0TCBd_TBE
);
1156 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1157 mask
|= (1 << CP0TCBd_CurVPE
);
1158 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1159 env
->active_tc
.CP0_TCBind
= newval
;
1162 void helper_mttc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1164 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1165 uint32_t mask
= (1 << CP0TCBd_TBE
);
1167 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1169 if (other
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1170 mask
|= (1 << CP0TCBd_CurVPE
);
1171 if (other_tc
== other
->current_tc
) {
1172 newval
= (other
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1173 other
->active_tc
.CP0_TCBind
= newval
;
1175 newval
= (other
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
1176 other
->tcs
[other_tc
].CP0_TCBind
= newval
;
1180 void helper_mtc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1182 env
->active_tc
.PC
= arg1
;
1183 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1185 /* MIPS16 not implemented. */
1188 void helper_mttc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1190 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1191 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1193 if (other_tc
== other
->current_tc
) {
1194 other
->active_tc
.PC
= arg1
;
1195 other
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1196 other
->lladdr
= 0ULL;
1197 /* MIPS16 not implemented. */
1199 other
->tcs
[other_tc
].PC
= arg1
;
1200 other
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1201 other
->lladdr
= 0ULL;
1202 /* MIPS16 not implemented. */
1206 void helper_mtc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1208 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1210 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
1212 // TODO: Halt TC / Restart (if allocated+active) TC.
1213 if (env
->active_tc
.CP0_TCHalt
& 1) {
1214 mips_tc_sleep(cpu
, env
->current_tc
);
1216 mips_tc_wake(cpu
, env
->current_tc
);
1220 void helper_mttc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1222 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1223 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1224 MIPSCPU
*other_cpu
= mips_env_get_cpu(other
);
1226 // TODO: Halt TC / Restart (if allocated+active) TC.
1228 if (other_tc
== other
->current_tc
)
1229 other
->active_tc
.CP0_TCHalt
= arg1
;
1231 other
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
1234 mips_tc_sleep(other_cpu
, other_tc
);
1236 mips_tc_wake(other_cpu
, other_tc
);
1240 void helper_mtc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1242 env
->active_tc
.CP0_TCContext
= arg1
;
1245 void helper_mttc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1247 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1248 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1250 if (other_tc
== other
->current_tc
)
1251 other
->active_tc
.CP0_TCContext
= arg1
;
1253 other
->tcs
[other_tc
].CP0_TCContext
= arg1
;
1256 void helper_mtc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1258 env
->active_tc
.CP0_TCSchedule
= arg1
;
1261 void helper_mttc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1263 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1264 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1266 if (other_tc
== other
->current_tc
)
1267 other
->active_tc
.CP0_TCSchedule
= arg1
;
1269 other
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
1272 void helper_mtc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1274 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1277 void helper_mttc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1279 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1280 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1282 if (other_tc
== other
->current_tc
)
1283 other
->active_tc
.CP0_TCScheFBack
= arg1
;
1285 other
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
1288 void helper_mtc0_entrylo1(CPUMIPSState
*env
, target_ulong arg1
)
1290 /* 1k pages not implemented */
1291 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1292 env
->CP0_EntryLo1
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1293 | (rxi
<< (CP0EnLo_XI
- 30));
1296 #if defined(TARGET_MIPS64)
1297 void helper_dmtc0_entrylo1(CPUMIPSState
*env
, uint64_t arg1
)
1299 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1300 env
->CP0_EntryLo1
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1304 void helper_mtc0_context(CPUMIPSState
*env
, target_ulong arg1
)
1306 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
1309 void helper_mtc0_pagemask(CPUMIPSState
*env
, target_ulong arg1
)
1311 uint64_t mask
= arg1
>> (TARGET_PAGE_BITS
+ 1);
1312 if (!(env
->insn_flags
& ISA_MIPS32R6
) || (arg1
== ~0) ||
1313 (mask
== 0x0000 || mask
== 0x0003 || mask
== 0x000F ||
1314 mask
== 0x003F || mask
== 0x00FF || mask
== 0x03FF ||
1315 mask
== 0x0FFF || mask
== 0x3FFF || mask
== 0xFFFF)) {
1316 env
->CP0_PageMask
= arg1
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1320 void helper_mtc0_pagegrain(CPUMIPSState
*env
, target_ulong arg1
)
1322 /* SmartMIPS not implemented */
1323 /* 1k pages not implemented */
1324 env
->CP0_PageGrain
= (arg1
& env
->CP0_PageGrain_rw_bitmask
) |
1325 (env
->CP0_PageGrain
& ~env
->CP0_PageGrain_rw_bitmask
);
1326 compute_hflags(env
);
1327 restore_pamask(env
);
1330 void helper_mtc0_segctl0(CPUMIPSState
*env
, target_ulong arg1
)
1332 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1334 env
->CP0_SegCtl0
= arg1
& CP0SC0_MASK
;
1338 void helper_mtc0_segctl1(CPUMIPSState
*env
, target_ulong arg1
)
1340 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1342 env
->CP0_SegCtl1
= arg1
& CP0SC1_MASK
;
1346 void helper_mtc0_segctl2(CPUMIPSState
*env
, target_ulong arg1
)
1348 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1350 env
->CP0_SegCtl2
= arg1
& CP0SC2_MASK
;
1354 void helper_mtc0_wired(CPUMIPSState
*env
, target_ulong arg1
)
1356 if (env
->insn_flags
& ISA_MIPS32R6
) {
1357 if (arg1
< env
->tlb
->nb_tlb
) {
1358 env
->CP0_Wired
= arg1
;
1361 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1365 void helper_mtc0_srsconf0(CPUMIPSState
*env
, target_ulong arg1
)
1367 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1370 void helper_mtc0_srsconf1(CPUMIPSState
*env
, target_ulong arg1
)
1372 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1375 void helper_mtc0_srsconf2(CPUMIPSState
*env
, target_ulong arg1
)
1377 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1380 void helper_mtc0_srsconf3(CPUMIPSState
*env
, target_ulong arg1
)
1382 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1385 void helper_mtc0_srsconf4(CPUMIPSState
*env
, target_ulong arg1
)
1387 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1390 void helper_mtc0_hwrena(CPUMIPSState
*env
, target_ulong arg1
)
1392 uint32_t mask
= 0x0000000F;
1394 if ((env
->CP0_Config1
& (1 << CP0C1_PC
)) &&
1395 (env
->insn_flags
& ISA_MIPS32R6
)) {
1398 if (env
->insn_flags
& ISA_MIPS32R6
) {
1401 if (env
->CP0_Config3
& (1 << CP0C3_ULRI
)) {
1404 if (arg1
& (1 << 29)) {
1405 env
->hflags
|= MIPS_HFLAG_HWRENA_ULR
;
1407 env
->hflags
&= ~MIPS_HFLAG_HWRENA_ULR
;
1411 env
->CP0_HWREna
= arg1
& mask
;
1414 void helper_mtc0_count(CPUMIPSState
*env
, target_ulong arg1
)
1416 qemu_mutex_lock_iothread();
1417 cpu_mips_store_count(env
, arg1
);
1418 qemu_mutex_unlock_iothread();
1421 void helper_mtc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1423 target_ulong old
, val
, mask
;
1424 mask
= (TARGET_PAGE_MASK
<< 1) | env
->CP0_EntryHi_ASID_mask
;
1425 if (((env
->CP0_Config4
>> CP0C4_IE
) & 0x3) >= 2) {
1426 mask
|= 1 << CP0EnHi_EHINV
;
1429 /* 1k pages not implemented */
1430 #if defined(TARGET_MIPS64)
1431 if (env
->insn_flags
& ISA_MIPS32R6
) {
1432 int entryhi_r
= extract64(arg1
, 62, 2);
1433 int config0_at
= extract32(env
->CP0_Config0
, 13, 2);
1434 bool no_supervisor
= (env
->CP0_Status_rw_bitmask
& 0x8) == 0;
1435 if ((entryhi_r
== 2) ||
1436 (entryhi_r
== 1 && (no_supervisor
|| config0_at
== 1))) {
1437 /* skip EntryHi.R field if new value is reserved */
1438 mask
&= ~(0x3ull
<< 62);
1441 mask
&= env
->SEGMask
;
1443 old
= env
->CP0_EntryHi
;
1444 val
= (arg1
& mask
) | (old
& ~mask
);
1445 env
->CP0_EntryHi
= val
;
1446 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1447 sync_c0_entryhi(env
, env
->current_tc
);
1449 /* If the ASID changes, flush qemu's TLB. */
1450 if ((old
& env
->CP0_EntryHi_ASID_mask
) !=
1451 (val
& env
->CP0_EntryHi_ASID_mask
)) {
1452 tlb_flush(CPU(mips_env_get_cpu(env
)));
1456 void helper_mttc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1458 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1459 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1461 other
->CP0_EntryHi
= arg1
;
1462 sync_c0_entryhi(other
, other_tc
);
1465 void helper_mtc0_compare(CPUMIPSState
*env
, target_ulong arg1
)
1467 qemu_mutex_lock_iothread();
1468 cpu_mips_store_compare(env
, arg1
);
1469 qemu_mutex_unlock_iothread();
1472 void helper_mtc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1474 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1477 old
= env
->CP0_Status
;
1478 cpu_mips_store_status(env
, arg1
);
1479 val
= env
->CP0_Status
;
1481 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1482 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1483 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1484 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1486 switch (cpu_mmu_index(env
, false)) {
1488 qemu_log(", ERL\n");
1490 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1491 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1492 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1494 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
1500 void helper_mttc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1502 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1503 uint32_t mask
= env
->CP0_Status_rw_bitmask
& ~0xf1000018;
1504 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1506 other
->CP0_Status
= (other
->CP0_Status
& ~mask
) | (arg1
& mask
);
1507 sync_c0_status(env
, other
, other_tc
);
1510 void helper_mtc0_intctl(CPUMIPSState
*env
, target_ulong arg1
)
1512 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000003e0) | (arg1
& 0x000003e0);
1515 void helper_mtc0_srsctl(CPUMIPSState
*env
, target_ulong arg1
)
1517 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1518 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1521 void helper_mtc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1523 qemu_mutex_lock_iothread();
1524 cpu_mips_store_cause(env
, arg1
);
1525 qemu_mutex_unlock_iothread();
1528 void helper_mttc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1530 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1531 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1533 cpu_mips_store_cause(other
, arg1
);
1536 target_ulong
helper_mftc0_epc(CPUMIPSState
*env
)
1538 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1539 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1541 return other
->CP0_EPC
;
1544 target_ulong
helper_mftc0_ebase(CPUMIPSState
*env
)
1546 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1547 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1549 return other
->CP0_EBase
;
1552 void helper_mtc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1554 target_ulong mask
= 0x3FFFF000 | env
->CP0_EBaseWG_rw_bitmask
;
1555 if (arg1
& env
->CP0_EBaseWG_rw_bitmask
) {
1556 mask
|= ~0x3FFFFFFF;
1558 env
->CP0_EBase
= (env
->CP0_EBase
& ~mask
) | (arg1
& mask
);
1561 void helper_mttc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1563 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1564 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1565 target_ulong mask
= 0x3FFFF000 | env
->CP0_EBaseWG_rw_bitmask
;
1566 if (arg1
& env
->CP0_EBaseWG_rw_bitmask
) {
1567 mask
|= ~0x3FFFFFFF;
1569 other
->CP0_EBase
= (other
->CP0_EBase
& ~mask
) | (arg1
& mask
);
1572 target_ulong
helper_mftc0_configx(CPUMIPSState
*env
, target_ulong idx
)
1574 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1575 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1578 case 0: return other
->CP0_Config0
;
1579 case 1: return other
->CP0_Config1
;
1580 case 2: return other
->CP0_Config2
;
1581 case 3: return other
->CP0_Config3
;
1582 /* 4 and 5 are reserved. */
1583 case 6: return other
->CP0_Config6
;
1584 case 7: return other
->CP0_Config7
;
1591 void helper_mtc0_config0(CPUMIPSState
*env
, target_ulong arg1
)
1593 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1596 void helper_mtc0_config2(CPUMIPSState
*env
, target_ulong arg1
)
1598 /* tertiary/secondary caches not implemented */
1599 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1602 void helper_mtc0_config3(CPUMIPSState
*env
, target_ulong arg1
)
1604 if (env
->insn_flags
& ASE_MICROMIPS
) {
1605 env
->CP0_Config3
= (env
->CP0_Config3
& ~(1 << CP0C3_ISA_ON_EXC
)) |
1606 (arg1
& (1 << CP0C3_ISA_ON_EXC
));
1610 void helper_mtc0_config4(CPUMIPSState
*env
, target_ulong arg1
)
1612 env
->CP0_Config4
= (env
->CP0_Config4
& (~env
->CP0_Config4_rw_bitmask
)) |
1613 (arg1
& env
->CP0_Config4_rw_bitmask
);
1616 void helper_mtc0_config5(CPUMIPSState
*env
, target_ulong arg1
)
1618 env
->CP0_Config5
= (env
->CP0_Config5
& (~env
->CP0_Config5_rw_bitmask
)) |
1619 (arg1
& env
->CP0_Config5_rw_bitmask
);
1620 compute_hflags(env
);
1623 void helper_mtc0_lladdr(CPUMIPSState
*env
, target_ulong arg1
)
1625 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1626 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1627 env
->lladdr
= (env
->lladdr
& ~mask
) | (arg1
& mask
);
1630 #define MTC0_MAAR_MASK(env) \
1631 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1633 void helper_mtc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1635 env
->CP0_MAAR
[env
->CP0_MAARI
] = arg1
& MTC0_MAAR_MASK(env
);
1638 void helper_mthc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1640 env
->CP0_MAAR
[env
->CP0_MAARI
] =
1641 (((uint64_t) arg1
<< 32) & MTC0_MAAR_MASK(env
)) |
1642 (env
->CP0_MAAR
[env
->CP0_MAARI
] & 0x00000000ffffffffULL
);
1645 void helper_mtc0_maari(CPUMIPSState
*env
, target_ulong arg1
)
1647 int index
= arg1
& 0x3f;
1648 if (index
== 0x3f) {
1649 /* Software may write all ones to INDEX to determine the
1650 maximum value supported. */
1651 env
->CP0_MAARI
= MIPS_MAAR_MAX
- 1;
1652 } else if (index
< MIPS_MAAR_MAX
) {
1653 env
->CP0_MAARI
= index
;
1655 /* Other than the all ones, if the
1656 value written is not supported, then INDEX is unchanged
1657 from its previous value. */
1660 void helper_mtc0_watchlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1662 /* Watch exceptions for instructions, data loads, data stores
1664 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1667 void helper_mtc0_watchhi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1669 int mask
= 0x40000FF8 | (env
->CP0_EntryHi_ASID_mask
<< CP0WH_ASID
);
1670 env
->CP0_WatchHi
[sel
] = arg1
& mask
;
1671 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1674 void helper_mtc0_xcontext(CPUMIPSState
*env
, target_ulong arg1
)
1676 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1677 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1680 void helper_mtc0_framemask(CPUMIPSState
*env
, target_ulong arg1
)
1682 env
->CP0_Framemask
= arg1
; /* XXX */
1685 void helper_mtc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1687 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1688 if (arg1
& (1 << CP0DB_DM
))
1689 env
->hflags
|= MIPS_HFLAG_DM
;
1691 env
->hflags
&= ~MIPS_HFLAG_DM
;
1694 void helper_mttc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1696 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1697 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1698 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1700 /* XXX: Might be wrong, check with EJTAG spec. */
1701 if (other_tc
== other
->current_tc
)
1702 other
->active_tc
.CP0_Debug_tcstatus
= val
;
1704 other
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1705 other
->CP0_Debug
= (other
->CP0_Debug
&
1706 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1707 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1710 void helper_mtc0_performance0(CPUMIPSState
*env
, target_ulong arg1
)
1712 env
->CP0_Performance0
= arg1
& 0x000007ff;
1715 void helper_mtc0_errctl(CPUMIPSState
*env
, target_ulong arg1
)
1717 int32_t wst
= arg1
& (1 << CP0EC_WST
);
1718 int32_t spr
= arg1
& (1 << CP0EC_SPR
);
1719 int32_t itc
= env
->itc_tag
? (arg1
& (1 << CP0EC_ITC
)) : 0;
1721 env
->CP0_ErrCtl
= wst
| spr
| itc
;
1723 if (itc
&& !wst
&& !spr
) {
1724 env
->hflags
|= MIPS_HFLAG_ITC_CACHE
;
1726 env
->hflags
&= ~MIPS_HFLAG_ITC_CACHE
;
1730 void helper_mtc0_taglo(CPUMIPSState
*env
, target_ulong arg1
)
1732 if (env
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
1733 /* If CACHE instruction is configured for ITC tags then make all
1734 CP0.TagLo bits writable. The actual write to ITC Configuration
1735 Tag will take care of the read-only bits. */
1736 env
->CP0_TagLo
= arg1
;
1738 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1742 void helper_mtc0_datalo(CPUMIPSState
*env
, target_ulong arg1
)
1744 env
->CP0_DataLo
= arg1
; /* XXX */
1747 void helper_mtc0_taghi(CPUMIPSState
*env
, target_ulong arg1
)
1749 env
->CP0_TagHi
= arg1
; /* XXX */
1752 void helper_mtc0_datahi(CPUMIPSState
*env
, target_ulong arg1
)
1754 env
->CP0_DataHi
= arg1
; /* XXX */
1757 /* MIPS MT functions */
1758 target_ulong
helper_mftgpr(CPUMIPSState
*env
, uint32_t sel
)
1760 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1761 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1763 if (other_tc
== other
->current_tc
)
1764 return other
->active_tc
.gpr
[sel
];
1766 return other
->tcs
[other_tc
].gpr
[sel
];
1769 target_ulong
helper_mftlo(CPUMIPSState
*env
, uint32_t sel
)
1771 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1772 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1774 if (other_tc
== other
->current_tc
)
1775 return other
->active_tc
.LO
[sel
];
1777 return other
->tcs
[other_tc
].LO
[sel
];
1780 target_ulong
helper_mfthi(CPUMIPSState
*env
, uint32_t sel
)
1782 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1783 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1785 if (other_tc
== other
->current_tc
)
1786 return other
->active_tc
.HI
[sel
];
1788 return other
->tcs
[other_tc
].HI
[sel
];
1791 target_ulong
helper_mftacx(CPUMIPSState
*env
, uint32_t sel
)
1793 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1794 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1796 if (other_tc
== other
->current_tc
)
1797 return other
->active_tc
.ACX
[sel
];
1799 return other
->tcs
[other_tc
].ACX
[sel
];
1802 target_ulong
helper_mftdsp(CPUMIPSState
*env
)
1804 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1805 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1807 if (other_tc
== other
->current_tc
)
1808 return other
->active_tc
.DSPControl
;
1810 return other
->tcs
[other_tc
].DSPControl
;
1813 void helper_mttgpr(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1815 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1816 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1818 if (other_tc
== other
->current_tc
)
1819 other
->active_tc
.gpr
[sel
] = arg1
;
1821 other
->tcs
[other_tc
].gpr
[sel
] = arg1
;
1824 void helper_mttlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1826 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1827 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1829 if (other_tc
== other
->current_tc
)
1830 other
->active_tc
.LO
[sel
] = arg1
;
1832 other
->tcs
[other_tc
].LO
[sel
] = arg1
;
1835 void helper_mtthi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1837 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1838 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1840 if (other_tc
== other
->current_tc
)
1841 other
->active_tc
.HI
[sel
] = arg1
;
1843 other
->tcs
[other_tc
].HI
[sel
] = arg1
;
1846 void helper_mttacx(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1848 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1849 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1851 if (other_tc
== other
->current_tc
)
1852 other
->active_tc
.ACX
[sel
] = arg1
;
1854 other
->tcs
[other_tc
].ACX
[sel
] = arg1
;
1857 void helper_mttdsp(CPUMIPSState
*env
, target_ulong arg1
)
1859 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1860 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1862 if (other_tc
== other
->current_tc
)
1863 other
->active_tc
.DSPControl
= arg1
;
1865 other
->tcs
[other_tc
].DSPControl
= arg1
;
1868 /* MIPS MT functions */
1869 target_ulong
helper_dmt(void)
1875 target_ulong
helper_emt(void)
1881 target_ulong
helper_dvpe(CPUMIPSState
*env
)
1883 CPUState
*other_cs
= first_cpu
;
1884 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1886 CPU_FOREACH(other_cs
) {
1887 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1888 /* Turn off all VPEs except the one executing the dvpe. */
1889 if (&other_cpu
->env
!= env
) {
1890 other_cpu
->env
.mvp
->CP0_MVPControl
&= ~(1 << CP0MVPCo_EVP
);
1891 mips_vpe_sleep(other_cpu
);
1897 target_ulong
helper_evpe(CPUMIPSState
*env
)
1899 CPUState
*other_cs
= first_cpu
;
1900 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1902 CPU_FOREACH(other_cs
) {
1903 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1905 if (&other_cpu
->env
!= env
1906 /* If the VPE is WFI, don't disturb its sleep. */
1907 && !mips_vpe_is_wfi(other_cpu
)) {
1908 /* Enable the VPE. */
1909 other_cpu
->env
.mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
1910 mips_vpe_wake(other_cpu
); /* And wake it up. */
1915 #endif /* !CONFIG_USER_ONLY */
1917 void helper_fork(target_ulong arg1
, target_ulong arg2
)
1919 // arg1 = rt, arg2 = rs
1920 // TODO: store to TC register
1923 target_ulong
helper_yield(CPUMIPSState
*env
, target_ulong arg
)
1925 target_long arg1
= arg
;
1928 /* No scheduling policy implemented. */
1930 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
1931 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
1932 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1933 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
1934 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1937 } else if (arg1
== 0) {
1938 if (0 /* TODO: TC underflow */) {
1939 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1940 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1942 // TODO: Deallocate TC
1944 } else if (arg1
> 0) {
1945 /* Yield qualifier inputs not implemented. */
1946 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1947 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
1948 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1950 return env
->CP0_YQMask
;
1953 /* R6 Multi-threading */
1954 #ifndef CONFIG_USER_ONLY
1955 target_ulong
helper_dvp(CPUMIPSState
*env
)
1957 CPUState
*other_cs
= first_cpu
;
1958 target_ulong prev
= env
->CP0_VPControl
;
1960 if (!((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
1961 CPU_FOREACH(other_cs
) {
1962 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1963 /* Turn off all VPs except the one executing the dvp. */
1964 if (&other_cpu
->env
!= env
) {
1965 mips_vpe_sleep(other_cpu
);
1968 env
->CP0_VPControl
|= (1 << CP0VPCtl_DIS
);
1973 target_ulong
helper_evp(CPUMIPSState
*env
)
1975 CPUState
*other_cs
= first_cpu
;
1976 target_ulong prev
= env
->CP0_VPControl
;
1978 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
1979 CPU_FOREACH(other_cs
) {
1980 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1981 if ((&other_cpu
->env
!= env
) && !mips_vp_is_wfi(other_cpu
)) {
1982 /* If the VP is WFI, don't disturb its sleep.
1983 * Otherwise, wake it up. */
1984 mips_vpe_wake(other_cpu
);
1987 env
->CP0_VPControl
&= ~(1 << CP0VPCtl_DIS
);
1991 #endif /* !CONFIG_USER_ONLY */
1993 #ifndef CONFIG_USER_ONLY
1994 /* TLB management */
1995 static void r4k_mips_tlb_flush_extra (CPUMIPSState
*env
, int first
)
1997 /* Discard entries from env->tlb[first] onwards. */
1998 while (env
->tlb
->tlb_in_use
> first
) {
1999 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
2003 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo
)
2005 #if defined(TARGET_MIPS64)
2006 return extract64(entrylo
, 6, 54);
2008 return extract64(entrylo
, 6, 24) | /* PFN */
2009 (extract64(entrylo
, 32, 32) << 24); /* PFNX */
2013 static void r4k_fill_tlb(CPUMIPSState
*env
, int idx
)
2016 uint64_t mask
= env
->CP0_PageMask
>> (TARGET_PAGE_BITS
+ 1);
2018 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
2019 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2020 if (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) {
2025 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
2026 #if defined(TARGET_MIPS64)
2027 tlb
->VPN
&= env
->SEGMask
;
2029 tlb
->ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2030 tlb
->PageMask
= env
->CP0_PageMask
;
2031 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
2032 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
2033 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
2034 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
2035 tlb
->XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) & 1;
2036 tlb
->RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) & 1;
2037 tlb
->PFN
[0] = (get_tlb_pfn_from_entrylo(env
->CP0_EntryLo0
) & ~mask
) << 12;
2038 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
2039 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
2040 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
2041 tlb
->XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) & 1;
2042 tlb
->RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) & 1;
2043 tlb
->PFN
[1] = (get_tlb_pfn_from_entrylo(env
->CP0_EntryLo1
) & ~mask
) << 12;
2046 void r4k_helper_tlbinv(CPUMIPSState
*env
)
2050 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2052 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2053 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2054 if (!tlb
->G
&& tlb
->ASID
== ASID
) {
2058 cpu_mips_tlb_flush(env
);
2061 void r4k_helper_tlbinvf(CPUMIPSState
*env
)
2065 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2066 env
->tlb
->mmu
.r4k
.tlb
[idx
].EHINV
= 1;
2068 cpu_mips_tlb_flush(env
);
2071 void r4k_helper_tlbwi(CPUMIPSState
*env
)
2077 bool EHINV
, G
, V0
, D0
, V1
, D1
, XI0
, XI1
, RI0
, RI1
;
2079 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2080 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2081 VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
2082 #if defined(TARGET_MIPS64)
2083 VPN
&= env
->SEGMask
;
2085 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2086 EHINV
= (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) != 0;
2087 G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
2088 V0
= (env
->CP0_EntryLo0
& 2) != 0;
2089 D0
= (env
->CP0_EntryLo0
& 4) != 0;
2090 XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) &1;
2091 RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) &1;
2092 V1
= (env
->CP0_EntryLo1
& 2) != 0;
2093 D1
= (env
->CP0_EntryLo1
& 4) != 0;
2094 XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) &1;
2095 RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) &1;
2097 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2098 permissions on the current entry. */
2099 if (tlb
->VPN
!= VPN
|| tlb
->ASID
!= ASID
|| tlb
->G
!= G
||
2100 (!tlb
->EHINV
&& EHINV
) ||
2101 (tlb
->V0
&& !V0
) || (tlb
->D0
&& !D0
) ||
2102 (!tlb
->XI0
&& XI0
) || (!tlb
->RI0
&& RI0
) ||
2103 (tlb
->V1
&& !V1
) || (tlb
->D1
&& !D1
) ||
2104 (!tlb
->XI1
&& XI1
) || (!tlb
->RI1
&& RI1
)) {
2105 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2108 r4k_invalidate_tlb(env
, idx
, 0);
2109 r4k_fill_tlb(env
, idx
);
2112 void r4k_helper_tlbwr(CPUMIPSState
*env
)
2114 int r
= cpu_mips_get_random(env
);
2116 r4k_invalidate_tlb(env
, r
, 1);
2117 r4k_fill_tlb(env
, r
);
2120 void r4k_helper_tlbp(CPUMIPSState
*env
)
2129 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2130 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
2131 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2132 /* 1k pages are not supported. */
2133 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2134 tag
= env
->CP0_EntryHi
& ~mask
;
2135 VPN
= tlb
->VPN
& ~mask
;
2136 #if defined(TARGET_MIPS64)
2137 tag
&= env
->SEGMask
;
2139 /* Check ASID, virtual page number & size */
2140 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
&& !tlb
->EHINV
) {
2146 if (i
== env
->tlb
->nb_tlb
) {
2147 /* No match. Discard any shadow entries, if any of them match. */
2148 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
2149 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2150 /* 1k pages are not supported. */
2151 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2152 tag
= env
->CP0_EntryHi
& ~mask
;
2153 VPN
= tlb
->VPN
& ~mask
;
2154 #if defined(TARGET_MIPS64)
2155 tag
&= env
->SEGMask
;
2157 /* Check ASID, virtual page number & size */
2158 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
2159 r4k_mips_tlb_flush_extra (env
, i
);
2164 env
->CP0_Index
|= 0x80000000;
2168 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn
)
2170 #if defined(TARGET_MIPS64)
2171 return tlb_pfn
<< 6;
2173 return (extract64(tlb_pfn
, 0, 24) << 6) | /* PFN */
2174 (extract64(tlb_pfn
, 24, 32) << 32); /* PFNX */
2178 void r4k_helper_tlbr(CPUMIPSState
*env
)
2184 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2185 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2186 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2188 /* If this will change the current ASID, flush qemu's TLB. */
2189 if (ASID
!= tlb
->ASID
)
2190 cpu_mips_tlb_flush(env
);
2192 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2195 env
->CP0_EntryHi
= 1 << CP0EnHi_EHINV
;
2196 env
->CP0_PageMask
= 0;
2197 env
->CP0_EntryLo0
= 0;
2198 env
->CP0_EntryLo1
= 0;
2200 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
2201 env
->CP0_PageMask
= tlb
->PageMask
;
2202 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
2203 ((uint64_t)tlb
->RI0
<< CP0EnLo_RI
) |
2204 ((uint64_t)tlb
->XI0
<< CP0EnLo_XI
) | (tlb
->C0
<< 3) |
2205 get_entrylo_pfn_from_tlb(tlb
->PFN
[0] >> 12);
2206 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
2207 ((uint64_t)tlb
->RI1
<< CP0EnLo_RI
) |
2208 ((uint64_t)tlb
->XI1
<< CP0EnLo_XI
) | (tlb
->C1
<< 3) |
2209 get_entrylo_pfn_from_tlb(tlb
->PFN
[1] >> 12);
2213 void helper_tlbwi(CPUMIPSState
*env
)
2215 env
->tlb
->helper_tlbwi(env
);
2218 void helper_tlbwr(CPUMIPSState
*env
)
2220 env
->tlb
->helper_tlbwr(env
);
2223 void helper_tlbp(CPUMIPSState
*env
)
2225 env
->tlb
->helper_tlbp(env
);
2228 void helper_tlbr(CPUMIPSState
*env
)
2230 env
->tlb
->helper_tlbr(env
);
2233 void helper_tlbinv(CPUMIPSState
*env
)
2235 env
->tlb
->helper_tlbinv(env
);
2238 void helper_tlbinvf(CPUMIPSState
*env
)
2240 env
->tlb
->helper_tlbinvf(env
);
2244 target_ulong
helper_di(CPUMIPSState
*env
)
2246 target_ulong t0
= env
->CP0_Status
;
2248 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
2252 target_ulong
helper_ei(CPUMIPSState
*env
)
2254 target_ulong t0
= env
->CP0_Status
;
2256 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
2260 static void debug_pre_eret(CPUMIPSState
*env
)
2262 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2263 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2264 env
->active_tc
.PC
, env
->CP0_EPC
);
2265 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2266 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2267 if (env
->hflags
& MIPS_HFLAG_DM
)
2268 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2273 static void debug_post_eret(CPUMIPSState
*env
)
2275 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
2277 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2278 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2279 env
->active_tc
.PC
, env
->CP0_EPC
);
2280 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2281 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2282 if (env
->hflags
& MIPS_HFLAG_DM
)
2283 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2284 switch (cpu_mmu_index(env
, false)) {
2286 qemu_log(", ERL\n");
2288 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
2289 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
2290 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
2292 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
2298 static void set_pc(CPUMIPSState
*env
, target_ulong error_pc
)
2300 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
2302 env
->hflags
|= MIPS_HFLAG_M16
;
2304 env
->hflags
&= ~(MIPS_HFLAG_M16
);
2308 static inline void exception_return(CPUMIPSState
*env
)
2310 debug_pre_eret(env
);
2311 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2312 set_pc(env
, env
->CP0_ErrorEPC
);
2313 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2315 set_pc(env
, env
->CP0_EPC
);
2316 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2318 compute_hflags(env
);
2319 debug_post_eret(env
);
2322 void helper_eret(CPUMIPSState
*env
)
2324 exception_return(env
);
2328 void helper_eretnc(CPUMIPSState
*env
)
2330 exception_return(env
);
2333 void helper_deret(CPUMIPSState
*env
)
2335 debug_pre_eret(env
);
2336 set_pc(env
, env
->CP0_DEPC
);
2338 env
->hflags
&= ~MIPS_HFLAG_DM
;
2339 compute_hflags(env
);
2340 debug_post_eret(env
);
2342 #endif /* !CONFIG_USER_ONLY */
2344 static inline void check_hwrena(CPUMIPSState
*env
, int reg
, uintptr_t pc
)
2346 if ((env
->hflags
& MIPS_HFLAG_CP0
) || (env
->CP0_HWREna
& (1 << reg
))) {
2349 do_raise_exception(env
, EXCP_RI
, pc
);
2352 target_ulong
helper_rdhwr_cpunum(CPUMIPSState
*env
)
2354 check_hwrena(env
, 0, GETPC());
2355 return env
->CP0_EBase
& 0x3ff;
2358 target_ulong
helper_rdhwr_synci_step(CPUMIPSState
*env
)
2360 check_hwrena(env
, 1, GETPC());
2361 return env
->SYNCI_Step
;
2364 target_ulong
helper_rdhwr_cc(CPUMIPSState
*env
)
2367 check_hwrena(env
, 2, GETPC());
2368 #ifdef CONFIG_USER_ONLY
2369 count
= env
->CP0_Count
;
2371 qemu_mutex_lock_iothread();
2372 count
= (int32_t)cpu_mips_get_count(env
);
2373 qemu_mutex_unlock_iothread();
2378 target_ulong
helper_rdhwr_ccres(CPUMIPSState
*env
)
2380 check_hwrena(env
, 3, GETPC());
2384 target_ulong
helper_rdhwr_performance(CPUMIPSState
*env
)
2386 check_hwrena(env
, 4, GETPC());
2387 return env
->CP0_Performance0
;
2390 target_ulong
helper_rdhwr_xnp(CPUMIPSState
*env
)
2392 check_hwrena(env
, 5, GETPC());
2393 return (env
->CP0_Config5
>> CP0C5_XNP
) & 1;
2396 void helper_pmon(CPUMIPSState
*env
, int function
)
2400 case 2: /* TODO: char inbyte(int waitflag); */
2401 if (env
->active_tc
.gpr
[4] == 0)
2402 env
->active_tc
.gpr
[2] = -1;
2404 case 11: /* TODO: char inbyte (void); */
2405 env
->active_tc
.gpr
[2] = -1;
2409 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
2415 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
2422 void helper_wait(CPUMIPSState
*env
)
2424 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2427 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
2428 /* Last instruction in the block, PC was updated before
2429 - no need to recover PC and icount */
2430 raise_exception(env
, EXCP_HLT
);
2433 #if !defined(CONFIG_USER_ONLY)
2435 void mips_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
2436 MMUAccessType access_type
,
2437 int mmu_idx
, uintptr_t retaddr
)
2439 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2440 CPUMIPSState
*env
= &cpu
->env
;
2444 if (!(env
->hflags
& MIPS_HFLAG_DM
)) {
2445 env
->CP0_BadVAddr
= addr
;
2448 if (access_type
== MMU_DATA_STORE
) {
2452 if (access_type
== MMU_INST_FETCH
) {
2453 error_code
|= EXCP_INST_NOTAVAIL
;
2457 do_raise_exception_err(env
, excp
, error_code
, retaddr
);
2460 void tlb_fill(CPUState
*cs
, target_ulong addr
, int size
,
2461 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
2465 ret
= mips_cpu_handle_mmu_fault(cs
, addr
, size
, access_type
, mmu_idx
);
2467 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2468 CPUMIPSState
*env
= &cpu
->env
;
2470 do_raise_exception_err(env
, cs
->exception_index
,
2471 env
->error_code
, retaddr
);
2475 void mips_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2476 bool is_write
, bool is_exec
, int unused
,
2479 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2480 CPUMIPSState
*env
= &cpu
->env
;
2483 * Raising an exception with KVM enabled will crash because it won't be from
2484 * the main execution loop so the longjmp won't have a matching setjmp.
2485 * Until we can trigger a bus error exception through KVM lets just ignore
2488 if (kvm_enabled()) {
2493 raise_exception(env
, EXCP_IBE
);
2495 raise_exception(env
, EXCP_DBE
);
2498 #endif /* !CONFIG_USER_ONLY */
2500 /* Complex FPU operations which may need stack space. */
2502 #define FLOAT_TWO32 make_float32(1 << 30)
2503 #define FLOAT_TWO64 make_float64(1ULL << 62)
2505 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2506 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2508 /* convert MIPS rounding mode in FCR31 to IEEE library */
2509 unsigned int ieee_rm
[] = {
2510 float_round_nearest_even
,
2511 float_round_to_zero
,
2516 target_ulong
helper_cfc1(CPUMIPSState
*env
, uint32_t reg
)
2518 target_ulong arg1
= 0;
2522 arg1
= (int32_t)env
->active_fpu
.fcr0
;
2525 /* UFR Support - Read Status FR */
2526 if (env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) {
2527 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2529 ((env
->CP0_Status
& (1 << CP0St_FR
)) >> CP0St_FR
);
2531 do_raise_exception(env
, EXCP_RI
, GETPC());
2536 /* FRE Support - read Config5.FRE bit */
2537 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
2538 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2539 arg1
= (env
->CP0_Config5
>> CP0C5_FRE
) & 1;
2541 helper_raise_exception(env
, EXCP_RI
);
2546 arg1
= ((env
->active_fpu
.fcr31
>> 24) & 0xfe) | ((env
->active_fpu
.fcr31
>> 23) & 0x1);
2549 arg1
= env
->active_fpu
.fcr31
& 0x0003f07c;
2552 arg1
= (env
->active_fpu
.fcr31
& 0x00000f83) | ((env
->active_fpu
.fcr31
>> 22) & 0x4);
2555 arg1
= (int32_t)env
->active_fpu
.fcr31
;
2562 void helper_ctc1(CPUMIPSState
*env
, target_ulong arg1
, uint32_t fs
, uint32_t rt
)
2566 /* UFR Alias - Reset Status FR */
2567 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2570 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2571 env
->CP0_Status
&= ~(1 << CP0St_FR
);
2572 compute_hflags(env
);
2574 do_raise_exception(env
, EXCP_RI
, GETPC());
2578 /* UNFR Alias - Set Status FR */
2579 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2582 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2583 env
->CP0_Status
|= (1 << CP0St_FR
);
2584 compute_hflags(env
);
2586 do_raise_exception(env
, EXCP_RI
, GETPC());
2590 /* FRE Support - clear Config5.FRE bit */
2591 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2594 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2595 env
->CP0_Config5
&= ~(1 << CP0C5_FRE
);
2596 compute_hflags(env
);
2598 helper_raise_exception(env
, EXCP_RI
);
2602 /* FRE Support - set Config5.FRE bit */
2603 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2606 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2607 env
->CP0_Config5
|= (1 << CP0C5_FRE
);
2608 compute_hflags(env
);
2610 helper_raise_exception(env
, EXCP_RI
);
2614 if ((env
->insn_flags
& ISA_MIPS32R6
) || (arg1
& 0xffffff00)) {
2617 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0x017fffff) | ((arg1
& 0xfe) << 24) |
2618 ((arg1
& 0x1) << 23);
2621 if (arg1
& 0x007c0000)
2623 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfffc0f83) | (arg1
& 0x0003f07c);
2626 if (arg1
& 0x007c0000)
2628 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfefff07c) | (arg1
& 0x00000f83) |
2629 ((arg1
& 0x4) << 22);
2632 env
->active_fpu
.fcr31
= (arg1
& env
->active_fpu
.fcr31_rw_bitmask
) |
2633 (env
->active_fpu
.fcr31
& ~(env
->active_fpu
.fcr31_rw_bitmask
));
2636 if (env
->insn_flags
& ISA_MIPS32R6
) {
2637 do_raise_exception(env
, EXCP_RI
, GETPC());
2641 restore_fp_status(env
);
2642 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2643 if ((GET_FP_ENABLE(env
->active_fpu
.fcr31
) | 0x20) & GET_FP_CAUSE(env
->active_fpu
.fcr31
))
2644 do_raise_exception(env
, EXCP_FPE
, GETPC());
2647 int ieee_ex_to_mips(int xcpt
)
2651 if (xcpt
& float_flag_invalid
) {
2654 if (xcpt
& float_flag_overflow
) {
2657 if (xcpt
& float_flag_underflow
) {
2658 ret
|= FP_UNDERFLOW
;
2660 if (xcpt
& float_flag_divbyzero
) {
2663 if (xcpt
& float_flag_inexact
) {
2670 static inline void update_fcr31(CPUMIPSState
*env
, uintptr_t pc
)
2672 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->active_fpu
.fp_status
));
2674 SET_FP_CAUSE(env
->active_fpu
.fcr31
, tmp
);
2677 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2679 if (GET_FP_ENABLE(env
->active_fpu
.fcr31
) & tmp
) {
2680 do_raise_exception(env
, EXCP_FPE
, pc
);
2682 UPDATE_FP_FLAGS(env
->active_fpu
.fcr31
, tmp
);
2688 Single precition routines have a "s" suffix, double precision a
2689 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2690 paired single lower "pl", paired single upper "pu". */
2692 /* unary operations, modifying fp status */
2693 uint64_t helper_float_sqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2695 fdt0
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2696 update_fcr31(env
, GETPC());
2700 uint32_t helper_float_sqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
2702 fst0
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2703 update_fcr31(env
, GETPC());
2707 uint64_t helper_float_cvtd_s(CPUMIPSState
*env
, uint32_t fst0
)
2711 fdt2
= float32_to_float64(fst0
, &env
->active_fpu
.fp_status
);
2712 update_fcr31(env
, GETPC());
2716 uint64_t helper_float_cvtd_w(CPUMIPSState
*env
, uint32_t wt0
)
2720 fdt2
= int32_to_float64(wt0
, &env
->active_fpu
.fp_status
);
2721 update_fcr31(env
, GETPC());
2725 uint64_t helper_float_cvtd_l(CPUMIPSState
*env
, uint64_t dt0
)
2729 fdt2
= int64_to_float64(dt0
, &env
->active_fpu
.fp_status
);
2730 update_fcr31(env
, GETPC());
2734 uint64_t helper_float_cvt_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2738 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2739 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2740 & (float_flag_invalid
| float_flag_overflow
)) {
2741 dt2
= FP_TO_INT64_OVERFLOW
;
2743 update_fcr31(env
, GETPC());
2747 uint64_t helper_float_cvt_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2751 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2752 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2753 & (float_flag_invalid
| float_flag_overflow
)) {
2754 dt2
= FP_TO_INT64_OVERFLOW
;
2756 update_fcr31(env
, GETPC());
2760 uint64_t helper_float_cvtps_pw(CPUMIPSState
*env
, uint64_t dt0
)
2765 fst2
= int32_to_float32(dt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2766 fsth2
= int32_to_float32(dt0
>> 32, &env
->active_fpu
.fp_status
);
2767 update_fcr31(env
, GETPC());
2768 return ((uint64_t)fsth2
<< 32) | fst2
;
2771 uint64_t helper_float_cvtpw_ps(CPUMIPSState
*env
, uint64_t fdt0
)
2777 wt2
= float32_to_int32(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2778 excp
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2779 if (excp
& (float_flag_overflow
| float_flag_invalid
)) {
2780 wt2
= FP_TO_INT32_OVERFLOW
;
2783 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2784 wth2
= float32_to_int32(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2785 excph
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2786 if (excph
& (float_flag_overflow
| float_flag_invalid
)) {
2787 wth2
= FP_TO_INT32_OVERFLOW
;
2790 set_float_exception_flags(excp
| excph
, &env
->active_fpu
.fp_status
);
2791 update_fcr31(env
, GETPC());
2793 return ((uint64_t)wth2
<< 32) | wt2
;
2796 uint32_t helper_float_cvts_d(CPUMIPSState
*env
, uint64_t fdt0
)
2800 fst2
= float64_to_float32(fdt0
, &env
->active_fpu
.fp_status
);
2801 update_fcr31(env
, GETPC());
2805 uint32_t helper_float_cvts_w(CPUMIPSState
*env
, uint32_t wt0
)
2809 fst2
= int32_to_float32(wt0
, &env
->active_fpu
.fp_status
);
2810 update_fcr31(env
, GETPC());
2814 uint32_t helper_float_cvts_l(CPUMIPSState
*env
, uint64_t dt0
)
2818 fst2
= int64_to_float32(dt0
, &env
->active_fpu
.fp_status
);
2819 update_fcr31(env
, GETPC());
2823 uint32_t helper_float_cvts_pl(CPUMIPSState
*env
, uint32_t wt0
)
2828 update_fcr31(env
, GETPC());
2832 uint32_t helper_float_cvts_pu(CPUMIPSState
*env
, uint32_t wth0
)
2837 update_fcr31(env
, GETPC());
2841 uint32_t helper_float_cvt_w_s(CPUMIPSState
*env
, uint32_t fst0
)
2845 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2846 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2847 & (float_flag_invalid
| float_flag_overflow
)) {
2848 wt2
= FP_TO_INT32_OVERFLOW
;
2850 update_fcr31(env
, GETPC());
2854 uint32_t helper_float_cvt_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
2858 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2859 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2860 & (float_flag_invalid
| float_flag_overflow
)) {
2861 wt2
= FP_TO_INT32_OVERFLOW
;
2863 update_fcr31(env
, GETPC());
2867 uint64_t helper_float_round_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2871 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2872 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2873 restore_rounding_mode(env
);
2874 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2875 & (float_flag_invalid
| float_flag_overflow
)) {
2876 dt2
= FP_TO_INT64_OVERFLOW
;
2878 update_fcr31(env
, GETPC());
2882 uint64_t helper_float_round_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2886 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2887 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2888 restore_rounding_mode(env
);
2889 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2890 & (float_flag_invalid
| float_flag_overflow
)) {
2891 dt2
= FP_TO_INT64_OVERFLOW
;
2893 update_fcr31(env
, GETPC());
2897 uint32_t helper_float_round_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
2901 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2902 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2903 restore_rounding_mode(env
);
2904 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2905 & (float_flag_invalid
| float_flag_overflow
)) {
2906 wt2
= FP_TO_INT32_OVERFLOW
;
2908 update_fcr31(env
, GETPC());
2912 uint32_t helper_float_round_w_s(CPUMIPSState
*env
, uint32_t fst0
)
2916 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2917 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2918 restore_rounding_mode(env
);
2919 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2920 & (float_flag_invalid
| float_flag_overflow
)) {
2921 wt2
= FP_TO_INT32_OVERFLOW
;
2923 update_fcr31(env
, GETPC());
2927 uint64_t helper_float_trunc_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2931 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2932 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2933 & (float_flag_invalid
| float_flag_overflow
)) {
2934 dt2
= FP_TO_INT64_OVERFLOW
;
2936 update_fcr31(env
, GETPC());
2940 uint64_t helper_float_trunc_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2944 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2945 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2946 & (float_flag_invalid
| float_flag_overflow
)) {
2947 dt2
= FP_TO_INT64_OVERFLOW
;
2949 update_fcr31(env
, GETPC());
2953 uint32_t helper_float_trunc_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
2957 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2958 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2959 & (float_flag_invalid
| float_flag_overflow
)) {
2960 wt2
= FP_TO_INT32_OVERFLOW
;
2962 update_fcr31(env
, GETPC());
2966 uint32_t helper_float_trunc_w_s(CPUMIPSState
*env
, uint32_t fst0
)
2970 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2971 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2972 & (float_flag_invalid
| float_flag_overflow
)) {
2973 wt2
= FP_TO_INT32_OVERFLOW
;
2975 update_fcr31(env
, GETPC());
2979 uint64_t helper_float_ceil_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2983 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2984 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2985 restore_rounding_mode(env
);
2986 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2987 & (float_flag_invalid
| float_flag_overflow
)) {
2988 dt2
= FP_TO_INT64_OVERFLOW
;
2990 update_fcr31(env
, GETPC());
2994 uint64_t helper_float_ceil_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2998 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2999 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3000 restore_rounding_mode(env
);
3001 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3002 & (float_flag_invalid
| float_flag_overflow
)) {
3003 dt2
= FP_TO_INT64_OVERFLOW
;
3005 update_fcr31(env
, GETPC());
3009 uint32_t helper_float_ceil_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3013 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3014 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3015 restore_rounding_mode(env
);
3016 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3017 & (float_flag_invalid
| float_flag_overflow
)) {
3018 wt2
= FP_TO_INT32_OVERFLOW
;
3020 update_fcr31(env
, GETPC());
3024 uint32_t helper_float_ceil_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3028 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3029 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3030 restore_rounding_mode(env
);
3031 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3032 & (float_flag_invalid
| float_flag_overflow
)) {
3033 wt2
= FP_TO_INT32_OVERFLOW
;
3035 update_fcr31(env
, GETPC());
3039 uint64_t helper_float_floor_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3043 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3044 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3045 restore_rounding_mode(env
);
3046 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3047 & (float_flag_invalid
| float_flag_overflow
)) {
3048 dt2
= FP_TO_INT64_OVERFLOW
;
3050 update_fcr31(env
, GETPC());
3054 uint64_t helper_float_floor_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3058 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3059 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3060 restore_rounding_mode(env
);
3061 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3062 & (float_flag_invalid
| float_flag_overflow
)) {
3063 dt2
= FP_TO_INT64_OVERFLOW
;
3065 update_fcr31(env
, GETPC());
3069 uint32_t helper_float_floor_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3073 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3074 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3075 restore_rounding_mode(env
);
3076 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3077 & (float_flag_invalid
| float_flag_overflow
)) {
3078 wt2
= FP_TO_INT32_OVERFLOW
;
3080 update_fcr31(env
, GETPC());
3084 uint32_t helper_float_floor_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3088 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3089 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3090 restore_rounding_mode(env
);
3091 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3092 & (float_flag_invalid
| float_flag_overflow
)) {
3093 wt2
= FP_TO_INT32_OVERFLOW
;
3095 update_fcr31(env
, GETPC());
3099 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3103 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3104 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3105 & float_flag_invalid
) {
3106 if (float64_is_any_nan(fdt0
)) {
3110 update_fcr31(env
, GETPC());
3114 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3118 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3119 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3120 & float_flag_invalid
) {
3121 if (float32_is_any_nan(fst0
)) {
3125 update_fcr31(env
, GETPC());
3129 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3133 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3134 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3135 & float_flag_invalid
) {
3136 if (float64_is_any_nan(fdt0
)) {
3140 update_fcr31(env
, GETPC());
3144 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3148 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3149 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3150 & float_flag_invalid
) {
3151 if (float32_is_any_nan(fst0
)) {
3155 update_fcr31(env
, GETPC());
3159 uint64_t helper_float_round_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3163 set_float_rounding_mode(float_round_nearest_even
,
3164 &env
->active_fpu
.fp_status
);
3165 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3166 restore_rounding_mode(env
);
3167 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3168 & float_flag_invalid
) {
3169 if (float64_is_any_nan(fdt0
)) {
3173 update_fcr31(env
, GETPC());
3177 uint64_t helper_float_round_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3181 set_float_rounding_mode(float_round_nearest_even
,
3182 &env
->active_fpu
.fp_status
);
3183 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3184 restore_rounding_mode(env
);
3185 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3186 & float_flag_invalid
) {
3187 if (float32_is_any_nan(fst0
)) {
3191 update_fcr31(env
, GETPC());
3195 uint32_t helper_float_round_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3199 set_float_rounding_mode(float_round_nearest_even
,
3200 &env
->active_fpu
.fp_status
);
3201 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3202 restore_rounding_mode(env
);
3203 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3204 & float_flag_invalid
) {
3205 if (float64_is_any_nan(fdt0
)) {
3209 update_fcr31(env
, GETPC());
3213 uint32_t helper_float_round_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3217 set_float_rounding_mode(float_round_nearest_even
,
3218 &env
->active_fpu
.fp_status
);
3219 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3220 restore_rounding_mode(env
);
3221 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3222 & float_flag_invalid
) {
3223 if (float32_is_any_nan(fst0
)) {
3227 update_fcr31(env
, GETPC());
3231 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3235 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3236 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3237 & float_flag_invalid
) {
3238 if (float64_is_any_nan(fdt0
)) {
3242 update_fcr31(env
, GETPC());
3246 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3250 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3251 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3252 & float_flag_invalid
) {
3253 if (float32_is_any_nan(fst0
)) {
3257 update_fcr31(env
, GETPC());
3261 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3265 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3266 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3267 & float_flag_invalid
) {
3268 if (float64_is_any_nan(fdt0
)) {
3272 update_fcr31(env
, GETPC());
3276 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3280 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3281 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3282 & float_flag_invalid
) {
3283 if (float32_is_any_nan(fst0
)) {
3287 update_fcr31(env
, GETPC());
3291 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3295 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3296 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3297 restore_rounding_mode(env
);
3298 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3299 & float_flag_invalid
) {
3300 if (float64_is_any_nan(fdt0
)) {
3304 update_fcr31(env
, GETPC());
3308 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3312 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3313 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3314 restore_rounding_mode(env
);
3315 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3316 & float_flag_invalid
) {
3317 if (float32_is_any_nan(fst0
)) {
3321 update_fcr31(env
, GETPC());
3325 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3329 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3330 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3331 restore_rounding_mode(env
);
3332 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3333 & float_flag_invalid
) {
3334 if (float64_is_any_nan(fdt0
)) {
3338 update_fcr31(env
, GETPC());
3342 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3346 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3347 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3348 restore_rounding_mode(env
);
3349 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3350 & float_flag_invalid
) {
3351 if (float32_is_any_nan(fst0
)) {
3355 update_fcr31(env
, GETPC());
3359 uint64_t helper_float_floor_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3363 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3364 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3365 restore_rounding_mode(env
);
3366 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3367 & float_flag_invalid
) {
3368 if (float64_is_any_nan(fdt0
)) {
3372 update_fcr31(env
, GETPC());
3376 uint64_t helper_float_floor_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3380 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3381 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3382 restore_rounding_mode(env
);
3383 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3384 & float_flag_invalid
) {
3385 if (float32_is_any_nan(fst0
)) {
3389 update_fcr31(env
, GETPC());
3393 uint32_t helper_float_floor_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3397 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3398 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3399 restore_rounding_mode(env
);
3400 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3401 & float_flag_invalid
) {
3402 if (float64_is_any_nan(fdt0
)) {
3406 update_fcr31(env
, GETPC());
3410 uint32_t helper_float_floor_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3414 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3415 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3416 restore_rounding_mode(env
);
3417 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3418 & float_flag_invalid
) {
3419 if (float32_is_any_nan(fst0
)) {
3423 update_fcr31(env
, GETPC());
3427 /* unary operations, not modifying fp status */
3428 #define FLOAT_UNOP(name) \
3429 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3431 return float64_ ## name(fdt0); \
3433 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3435 return float32_ ## name(fst0); \
3437 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3442 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3443 wth0 = float32_ ## name(fdt0 >> 32); \
3444 return ((uint64_t)wth0 << 32) | wt0; \
3450 /* MIPS specific unary operations */
3451 uint64_t helper_float_recip_d(CPUMIPSState
*env
, uint64_t fdt0
)
3455 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3456 update_fcr31(env
, GETPC());
3460 uint32_t helper_float_recip_s(CPUMIPSState
*env
, uint32_t fst0
)
3464 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3465 update_fcr31(env
, GETPC());
3469 uint64_t helper_float_rsqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
3473 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3474 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3475 update_fcr31(env
, GETPC());
3479 uint32_t helper_float_rsqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
3483 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3484 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3485 update_fcr31(env
, GETPC());
3489 uint64_t helper_float_recip1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3493 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3494 update_fcr31(env
, GETPC());
3498 uint32_t helper_float_recip1_s(CPUMIPSState
*env
, uint32_t fst0
)
3502 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3503 update_fcr31(env
, GETPC());
3507 uint64_t helper_float_recip1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3512 fst2
= float32_div(float32_one
, fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3513 fsth2
= float32_div(float32_one
, fdt0
>> 32, &env
->active_fpu
.fp_status
);
3514 update_fcr31(env
, GETPC());
3515 return ((uint64_t)fsth2
<< 32) | fst2
;
3518 uint64_t helper_float_rsqrt1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3522 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3523 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3524 update_fcr31(env
, GETPC());
3528 uint32_t helper_float_rsqrt1_s(CPUMIPSState
*env
, uint32_t fst0
)
3532 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3533 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3534 update_fcr31(env
, GETPC());
3538 uint64_t helper_float_rsqrt1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3543 fst2
= float32_sqrt(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3544 fsth2
= float32_sqrt(fdt0
>> 32, &env
->active_fpu
.fp_status
);
3545 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3546 fsth2
= float32_div(float32_one
, fsth2
, &env
->active_fpu
.fp_status
);
3547 update_fcr31(env
, GETPC());
3548 return ((uint64_t)fsth2
<< 32) | fst2
;
3551 #define FLOAT_RINT(name, bits) \
3552 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3553 uint ## bits ## _t fs) \
3555 uint ## bits ## _t fdret; \
3557 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3558 update_fcr31(env, GETPC()); \
3562 FLOAT_RINT(rint_s
, 32)
3563 FLOAT_RINT(rint_d
, 64)
3566 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3567 #define FLOAT_CLASS_QUIET_NAN 0x002
3568 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3569 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3570 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3571 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3572 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3573 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3574 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3575 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3577 #define FLOAT_CLASS(name, bits) \
3578 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3579 float_status *status) \
3581 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3582 return FLOAT_CLASS_SIGNALING_NAN; \
3583 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3584 return FLOAT_CLASS_QUIET_NAN; \
3585 } else if (float ## bits ## _is_neg(arg)) { \
3586 if (float ## bits ## _is_infinity(arg)) { \
3587 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3588 } else if (float ## bits ## _is_zero(arg)) { \
3589 return FLOAT_CLASS_NEGATIVE_ZERO; \
3590 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3591 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3593 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3596 if (float ## bits ## _is_infinity(arg)) { \
3597 return FLOAT_CLASS_POSITIVE_INFINITY; \
3598 } else if (float ## bits ## _is_zero(arg)) { \
3599 return FLOAT_CLASS_POSITIVE_ZERO; \
3600 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3601 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3603 return FLOAT_CLASS_POSITIVE_NORMAL; \
3608 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3609 uint ## bits ## _t arg) \
3611 return float_ ## name(arg, &env->active_fpu.fp_status); \
3614 FLOAT_CLASS(class_s
, 32)
3615 FLOAT_CLASS(class_d
, 64)
3618 /* binary operations */
3619 #define FLOAT_BINOP(name) \
3620 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3621 uint64_t fdt0, uint64_t fdt1) \
3625 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3626 update_fcr31(env, GETPC()); \
3630 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3631 uint32_t fst0, uint32_t fst1) \
3635 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3636 update_fcr31(env, GETPC()); \
3640 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3644 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3645 uint32_t fsth0 = fdt0 >> 32; \
3646 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3647 uint32_t fsth1 = fdt1 >> 32; \
3651 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3652 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3653 update_fcr31(env, GETPC()); \
3654 return ((uint64_t)wth2 << 32) | wt2; \
3663 /* MIPS specific binary operations */
3664 uint64_t helper_float_recip2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3666 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3667 fdt2
= float64_chs(float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
));
3668 update_fcr31(env
, GETPC());
3672 uint32_t helper_float_recip2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3674 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3675 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3676 update_fcr31(env
, GETPC());
3680 uint64_t helper_float_recip2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3682 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3683 uint32_t fsth0
= fdt0
>> 32;
3684 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3685 uint32_t fsth2
= fdt2
>> 32;
3687 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3688 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3689 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3690 fsth2
= float32_chs(float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
));
3691 update_fcr31(env
, GETPC());
3692 return ((uint64_t)fsth2
<< 32) | fst2
;
3695 uint64_t helper_float_rsqrt2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3697 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3698 fdt2
= float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
);
3699 fdt2
= float64_chs(float64_div(fdt2
, FLOAT_TWO64
, &env
->active_fpu
.fp_status
));
3700 update_fcr31(env
, GETPC());
3704 uint32_t helper_float_rsqrt2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3706 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3707 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3708 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3709 update_fcr31(env
, GETPC());
3713 uint64_t helper_float_rsqrt2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3715 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3716 uint32_t fsth0
= fdt0
>> 32;
3717 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3718 uint32_t fsth2
= fdt2
>> 32;
3720 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3721 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3722 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3723 fsth2
= float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
);
3724 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3725 fsth2
= float32_chs(float32_div(fsth2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3726 update_fcr31(env
, GETPC());
3727 return ((uint64_t)fsth2
<< 32) | fst2
;
3730 uint64_t helper_float_addr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3732 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3733 uint32_t fsth0
= fdt0
>> 32;
3734 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3735 uint32_t fsth1
= fdt1
>> 32;
3739 fst2
= float32_add (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3740 fsth2
= float32_add (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3741 update_fcr31(env
, GETPC());
3742 return ((uint64_t)fsth2
<< 32) | fst2
;
3745 uint64_t helper_float_mulr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3747 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3748 uint32_t fsth0
= fdt0
>> 32;
3749 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3750 uint32_t fsth1
= fdt1
>> 32;
3754 fst2
= float32_mul (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3755 fsth2
= float32_mul (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3756 update_fcr31(env
, GETPC());
3757 return ((uint64_t)fsth2
<< 32) | fst2
;
3760 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3761 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3762 uint ## bits ## _t fs, \
3763 uint ## bits ## _t ft) \
3765 uint ## bits ## _t fdret; \
3767 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3768 &env->active_fpu.fp_status); \
3769 update_fcr31(env, GETPC()); \
3773 FLOAT_MINMAX(max_s
, 32, maxnum
)
3774 FLOAT_MINMAX(max_d
, 64, maxnum
)
3775 FLOAT_MINMAX(maxa_s
, 32, maxnummag
)
3776 FLOAT_MINMAX(maxa_d
, 64, maxnummag
)
3778 FLOAT_MINMAX(min_s
, 32, minnum
)
3779 FLOAT_MINMAX(min_d
, 64, minnum
)
3780 FLOAT_MINMAX(mina_s
, 32, minnummag
)
3781 FLOAT_MINMAX(mina_d
, 64, minnummag
)
3784 /* ternary operations */
3785 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3787 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3788 if ((flags) & float_muladd_negate_c) { \
3789 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3791 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3793 if ((flags) & float_muladd_negate_result) { \
3794 a = prefix##_chs(a); \
3798 /* FMA based operations */
3799 #define FLOAT_FMA(name, type) \
3800 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3801 uint64_t fdt0, uint64_t fdt1, \
3804 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3805 update_fcr31(env, GETPC()); \
3809 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3810 uint32_t fst0, uint32_t fst1, \
3813 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3814 update_fcr31(env, GETPC()); \
3818 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3819 uint64_t fdt0, uint64_t fdt1, \
3822 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3823 uint32_t fsth0 = fdt0 >> 32; \
3824 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3825 uint32_t fsth1 = fdt1 >> 32; \
3826 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3827 uint32_t fsth2 = fdt2 >> 32; \
3829 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3830 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
3831 update_fcr31(env, GETPC()); \
3832 return ((uint64_t)fsth0 << 32) | fst0; \
3835 FLOAT_FMA(msub
, float_muladd_negate_c
)
3836 FLOAT_FMA(nmadd
, float_muladd_negate_result
)
3837 FLOAT_FMA(nmsub
, float_muladd_negate_result
| float_muladd_negate_c
)
3840 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
3841 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3842 uint ## bits ## _t fs, \
3843 uint ## bits ## _t ft, \
3844 uint ## bits ## _t fd) \
3846 uint ## bits ## _t fdret; \
3848 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
3849 &env->active_fpu.fp_status); \
3850 update_fcr31(env, GETPC()); \
3854 FLOAT_FMADDSUB(maddf_s
, 32, 0)
3855 FLOAT_FMADDSUB(maddf_d
, 64, 0)
3856 FLOAT_FMADDSUB(msubf_s
, 32, float_muladd_negate_product
)
3857 FLOAT_FMADDSUB(msubf_d
, 64, float_muladd_negate_product
)
3858 #undef FLOAT_FMADDSUB
3860 /* compare operations */
3861 #define FOP_COND_D(op, cond) \
3862 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3863 uint64_t fdt1, int cc) \
3867 update_fcr31(env, GETPC()); \
3869 SET_FP_COND(cc, env->active_fpu); \
3871 CLEAR_FP_COND(cc, env->active_fpu); \
3873 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3874 uint64_t fdt1, int cc) \
3877 fdt0 = float64_abs(fdt0); \
3878 fdt1 = float64_abs(fdt1); \
3880 update_fcr31(env, GETPC()); \
3882 SET_FP_COND(cc, env->active_fpu); \
3884 CLEAR_FP_COND(cc, env->active_fpu); \
3887 /* NOTE: the comma operator will make "cond" to eval to false,
3888 * but float64_unordered_quiet() is still called. */
3889 FOP_COND_D(f
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3890 FOP_COND_D(un
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3891 FOP_COND_D(eq
, float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3892 FOP_COND_D(ueq
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3893 FOP_COND_D(olt
, float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3894 FOP_COND_D(ult
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3895 FOP_COND_D(ole
, float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3896 FOP_COND_D(ule
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3897 /* NOTE: the comma operator will make "cond" to eval to false,
3898 * but float64_unordered() is still called. */
3899 FOP_COND_D(sf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3900 FOP_COND_D(ngle
,float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3901 FOP_COND_D(seq
, float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3902 FOP_COND_D(ngl
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3903 FOP_COND_D(lt
, float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3904 FOP_COND_D(nge
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3905 FOP_COND_D(le
, float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3906 FOP_COND_D(ngt
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3908 #define FOP_COND_S(op, cond) \
3909 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3910 uint32_t fst1, int cc) \
3914 update_fcr31(env, GETPC()); \
3916 SET_FP_COND(cc, env->active_fpu); \
3918 CLEAR_FP_COND(cc, env->active_fpu); \
3920 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3921 uint32_t fst1, int cc) \
3924 fst0 = float32_abs(fst0); \
3925 fst1 = float32_abs(fst1); \
3927 update_fcr31(env, GETPC()); \
3929 SET_FP_COND(cc, env->active_fpu); \
3931 CLEAR_FP_COND(cc, env->active_fpu); \
3934 /* NOTE: the comma operator will make "cond" to eval to false,
3935 * but float32_unordered_quiet() is still called. */
3936 FOP_COND_S(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3937 FOP_COND_S(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3938 FOP_COND_S(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3939 FOP_COND_S(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3940 FOP_COND_S(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3941 FOP_COND_S(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3942 FOP_COND_S(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3943 FOP_COND_S(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3944 /* NOTE: the comma operator will make "cond" to eval to false,
3945 * but float32_unordered() is still called. */
3946 FOP_COND_S(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3947 FOP_COND_S(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3948 FOP_COND_S(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3949 FOP_COND_S(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3950 FOP_COND_S(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3951 FOP_COND_S(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3952 FOP_COND_S(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3953 FOP_COND_S(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3955 #define FOP_COND_PS(op, condl, condh) \
3956 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3957 uint64_t fdt1, int cc) \
3959 uint32_t fst0, fsth0, fst1, fsth1; \
3961 fst0 = fdt0 & 0XFFFFFFFF; \
3962 fsth0 = fdt0 >> 32; \
3963 fst1 = fdt1 & 0XFFFFFFFF; \
3964 fsth1 = fdt1 >> 32; \
3967 update_fcr31(env, GETPC()); \
3969 SET_FP_COND(cc, env->active_fpu); \
3971 CLEAR_FP_COND(cc, env->active_fpu); \
3973 SET_FP_COND(cc + 1, env->active_fpu); \
3975 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3977 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3978 uint64_t fdt1, int cc) \
3980 uint32_t fst0, fsth0, fst1, fsth1; \
3982 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3983 fsth0 = float32_abs(fdt0 >> 32); \
3984 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3985 fsth1 = float32_abs(fdt1 >> 32); \
3988 update_fcr31(env, GETPC()); \
3990 SET_FP_COND(cc, env->active_fpu); \
3992 CLEAR_FP_COND(cc, env->active_fpu); \
3994 SET_FP_COND(cc + 1, env->active_fpu); \
3996 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3999 /* NOTE: the comma operator will make "cond" to eval to false,
4000 * but float32_unordered_quiet() is still called. */
4001 FOP_COND_PS(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
4002 (float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
4003 FOP_COND_PS(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
),
4004 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
4005 FOP_COND_PS(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4006 float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4007 FOP_COND_PS(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4008 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4009 FOP_COND_PS(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4010 float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4011 FOP_COND_PS(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4012 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4013 FOP_COND_PS(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4014 float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4015 FOP_COND_PS(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4016 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4017 /* NOTE: the comma operator will make "cond" to eval to false,
4018 * but float32_unordered() is still called. */
4019 FOP_COND_PS(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
4020 (float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
4021 FOP_COND_PS(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
),
4022 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
4023 FOP_COND_PS(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4024 float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4025 FOP_COND_PS(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4026 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4027 FOP_COND_PS(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4028 float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4029 FOP_COND_PS(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4030 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4031 FOP_COND_PS(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4032 float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4033 FOP_COND_PS(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4034 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4036 /* R6 compare operations */
4037 #define FOP_CONDN_D(op, cond) \
4038 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
4043 update_fcr31(env, GETPC()); \
4051 /* NOTE: the comma operator will make "cond" to eval to false,
4052 * but float64_unordered_quiet() is still called. */
4053 FOP_CONDN_D(af
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4054 FOP_CONDN_D(un
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
4055 FOP_CONDN_D(eq
, (float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4056 FOP_CONDN_D(ueq
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4057 || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4058 FOP_CONDN_D(lt
, (float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4059 FOP_CONDN_D(ult
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4060 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4061 FOP_CONDN_D(le
, (float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4062 FOP_CONDN_D(ule
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4063 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4064 /* NOTE: the comma operator will make "cond" to eval to false,
4065 * but float64_unordered() is still called. */
4066 FOP_CONDN_D(saf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4067 FOP_CONDN_D(sun
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
4068 FOP_CONDN_D(seq
, (float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4069 FOP_CONDN_D(sueq
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4070 || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4071 FOP_CONDN_D(slt
, (float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4072 FOP_CONDN_D(sult
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4073 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4074 FOP_CONDN_D(sle
, (float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4075 FOP_CONDN_D(sule
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4076 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4077 FOP_CONDN_D(or, (float64_le_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4078 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4079 FOP_CONDN_D(une
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4080 || float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4081 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4082 FOP_CONDN_D(ne
, (float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4083 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4084 FOP_CONDN_D(sor
, (float64_le(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4085 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4086 FOP_CONDN_D(sune
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4087 || float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4088 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4089 FOP_CONDN_D(sne
, (float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4090 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4092 #define FOP_CONDN_S(op, cond) \
4093 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4098 update_fcr31(env, GETPC()); \
4106 /* NOTE: the comma operator will make "cond" to eval to false,
4107 * but float32_unordered_quiet() is still called. */
4108 FOP_CONDN_S(af
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4109 FOP_CONDN_S(un
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
4110 FOP_CONDN_S(eq
, (float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4111 FOP_CONDN_S(ueq
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4112 || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4113 FOP_CONDN_S(lt
, (float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4114 FOP_CONDN_S(ult
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4115 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4116 FOP_CONDN_S(le
, (float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4117 FOP_CONDN_S(ule
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4118 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4119 /* NOTE: the comma operator will make "cond" to eval to false,
4120 * but float32_unordered() is still called. */
4121 FOP_CONDN_S(saf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4122 FOP_CONDN_S(sun
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
4123 FOP_CONDN_S(seq
, (float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4124 FOP_CONDN_S(sueq
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4125 || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4126 FOP_CONDN_S(slt
, (float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4127 FOP_CONDN_S(sult
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4128 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4129 FOP_CONDN_S(sle
, (float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4130 FOP_CONDN_S(sule
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4131 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4132 FOP_CONDN_S(or, (float32_le_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4133 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4134 FOP_CONDN_S(une
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4135 || float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4136 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4137 FOP_CONDN_S(ne
, (float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4138 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4139 FOP_CONDN_S(sor
, (float32_le(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4140 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4141 FOP_CONDN_S(sune
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4142 || float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4143 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4144 FOP_CONDN_S(sne
, (float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4145 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4148 /* Data format min and max values */
4149 #define DF_BITS(df) (1 << ((df) + 3))
4151 /* Element-by-element access macros */
4152 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4154 #if !defined(CONFIG_USER_ONLY)
4155 #define MEMOP_IDX(DF) \
4156 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4157 cpu_mmu_index(env, false));
4159 #define MEMOP_IDX(DF)
4162 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
4163 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4164 target_ulong addr) \
4166 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4170 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4171 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
4173 memcpy(pwd, &wx, sizeof(wr_t)); \
4176 #if !defined(CONFIG_USER_ONLY)
4177 MSA_LD_DF(DF_BYTE
, b
, helper_ret_ldub_mmu
, oi
, GETPC())
4178 MSA_LD_DF(DF_HALF
, h
, helper_ret_lduw_mmu
, oi
, GETPC())
4179 MSA_LD_DF(DF_WORD
, w
, helper_ret_ldul_mmu
, oi
, GETPC())
4180 MSA_LD_DF(DF_DOUBLE
, d
, helper_ret_ldq_mmu
, oi
, GETPC())
4182 MSA_LD_DF(DF_BYTE
, b
, cpu_ldub_data
)
4183 MSA_LD_DF(DF_HALF
, h
, cpu_lduw_data
)
4184 MSA_LD_DF(DF_WORD
, w
, cpu_ldl_data
)
4185 MSA_LD_DF(DF_DOUBLE
, d
, cpu_ldq_data
)
4188 #define MSA_PAGESPAN(x) \
4189 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4191 static inline void ensure_writable_pages(CPUMIPSState
*env
,
4196 #if !defined(CONFIG_USER_ONLY)
4197 target_ulong page_addr
;
4198 if (unlikely(MSA_PAGESPAN(addr
))) {
4200 probe_write(env
, addr
, 0, mmu_idx
, retaddr
);
4202 page_addr
= (addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
4203 probe_write(env
, page_addr
, 0, mmu_idx
, retaddr
);
4208 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
4209 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4210 target_ulong addr) \
4212 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4213 int mmu_idx = cpu_mmu_index(env, false); \
4216 ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
4217 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4218 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
4222 #if !defined(CONFIG_USER_ONLY)
4223 MSA_ST_DF(DF_BYTE
, b
, helper_ret_stb_mmu
, oi
, GETPC())
4224 MSA_ST_DF(DF_HALF
, h
, helper_ret_stw_mmu
, oi
, GETPC())
4225 MSA_ST_DF(DF_WORD
, w
, helper_ret_stl_mmu
, oi
, GETPC())
4226 MSA_ST_DF(DF_DOUBLE
, d
, helper_ret_stq_mmu
, oi
, GETPC())
4228 MSA_ST_DF(DF_BYTE
, b
, cpu_stb_data
)
4229 MSA_ST_DF(DF_HALF
, h
, cpu_stw_data
)
4230 MSA_ST_DF(DF_WORD
, w
, cpu_stl_data
)
4231 MSA_ST_DF(DF_DOUBLE
, d
, cpu_stq_data
)
4234 void helper_cache(CPUMIPSState
*env
, target_ulong addr
, uint32_t op
)
4236 #ifndef CONFIG_USER_ONLY
4237 target_ulong index
= addr
& 0x1fffffff;
4239 /* Index Store Tag */
4240 memory_region_dispatch_write(env
->itc_tag
, index
, env
->CP0_TagLo
,
4241 8, MEMTXATTRS_UNSPECIFIED
);
4242 } else if (op
== 5) {
4243 /* Index Load Tag */
4244 memory_region_dispatch_read(env
->itc_tag
, index
, &env
->CP0_TagLo
,
4245 8, MEMTXATTRS_UNSPECIFIED
);