2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
23 #include "qemu/host-utils.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "sysemu/kvm.h"
29 /*****************************************************************************/
30 /* Exceptions processing helpers */
32 void helper_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
35 do_raise_exception_err(env
, exception
, error_code
, 0);
38 void helper_raise_exception(CPUMIPSState
*env
, uint32_t exception
)
40 do_raise_exception(env
, exception
, GETPC());
43 void helper_raise_exception_debug(CPUMIPSState
*env
)
45 do_raise_exception(env
, EXCP_DEBUG
, 0);
48 static void raise_exception(CPUMIPSState
*env
, uint32_t exception
)
50 do_raise_exception(env
, exception
, 0);
53 #if defined(CONFIG_USER_ONLY)
54 #define HELPER_LD(name, insn, type) \
55 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
56 int mem_idx, uintptr_t retaddr) \
58 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
61 #define HELPER_LD(name, insn, type) \
62 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
63 int mem_idx, uintptr_t retaddr) \
67 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
68 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
70 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
71 case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \
75 HELPER_LD(lw
, ldl
, int32_t)
76 #if defined(TARGET_MIPS64)
77 HELPER_LD(ld
, ldq
, int64_t)
81 #if defined(CONFIG_USER_ONLY)
82 #define HELPER_ST(name, insn, type) \
83 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
84 type val, int mem_idx, uintptr_t retaddr) \
86 cpu_##insn##_data_ra(env, addr, val, retaddr); \
89 #define HELPER_ST(name, insn, type) \
90 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
91 type val, int mem_idx, uintptr_t retaddr) \
95 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
96 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
98 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
100 cpu_##insn##_error_ra(env, addr, val, retaddr); \
105 HELPER_ST(sb
, stb
, uint8_t)
106 HELPER_ST(sw
, stl
, uint32_t)
107 #if defined(TARGET_MIPS64)
108 HELPER_ST(sd
, stq
, uint64_t)
112 /* 64 bits arithmetic for 32 bits hosts */
113 static inline uint64_t get_HILO(CPUMIPSState
*env
)
115 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) | (uint32_t)env
->active_tc
.LO
[0];
118 static inline target_ulong
set_HIT0_LO(CPUMIPSState
*env
, uint64_t HILO
)
120 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
121 return env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
124 static inline target_ulong
set_HI_LOT0(CPUMIPSState
*env
, uint64_t HILO
)
126 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
127 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
131 /* Multiplication variants of the vr54xx. */
132 target_ulong
helper_muls(CPUMIPSState
*env
, target_ulong arg1
,
135 return set_HI_LOT0(env
, 0 - ((int64_t)(int32_t)arg1
*
136 (int64_t)(int32_t)arg2
));
139 target_ulong
helper_mulsu(CPUMIPSState
*env
, target_ulong arg1
,
142 return set_HI_LOT0(env
, 0 - (uint64_t)(uint32_t)arg1
*
143 (uint64_t)(uint32_t)arg2
);
146 target_ulong
helper_macc(CPUMIPSState
*env
, target_ulong arg1
,
149 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
150 (int64_t)(int32_t)arg2
);
153 target_ulong
helper_macchi(CPUMIPSState
*env
, target_ulong arg1
,
156 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
157 (int64_t)(int32_t)arg2
);
160 target_ulong
helper_maccu(CPUMIPSState
*env
, target_ulong arg1
,
163 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) +
164 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
167 target_ulong
helper_macchiu(CPUMIPSState
*env
, target_ulong arg1
,
170 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) +
171 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
174 target_ulong
helper_msac(CPUMIPSState
*env
, target_ulong arg1
,
177 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
178 (int64_t)(int32_t)arg2
);
181 target_ulong
helper_msachi(CPUMIPSState
*env
, target_ulong arg1
,
184 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
185 (int64_t)(int32_t)arg2
);
188 target_ulong
helper_msacu(CPUMIPSState
*env
, target_ulong arg1
,
191 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) -
192 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
195 target_ulong
helper_msachiu(CPUMIPSState
*env
, target_ulong arg1
,
198 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) -
199 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
202 target_ulong
helper_mulhi(CPUMIPSState
*env
, target_ulong arg1
,
205 return set_HIT0_LO(env
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
208 target_ulong
helper_mulhiu(CPUMIPSState
*env
, target_ulong arg1
,
211 return set_HIT0_LO(env
, (uint64_t)(uint32_t)arg1
*
212 (uint64_t)(uint32_t)arg2
);
215 target_ulong
helper_mulshi(CPUMIPSState
*env
, target_ulong arg1
,
218 return set_HIT0_LO(env
, 0 - (int64_t)(int32_t)arg1
*
219 (int64_t)(int32_t)arg2
);
222 target_ulong
helper_mulshiu(CPUMIPSState
*env
, target_ulong arg1
,
225 return set_HIT0_LO(env
, 0 - (uint64_t)(uint32_t)arg1
*
226 (uint64_t)(uint32_t)arg2
);
229 static inline target_ulong
bitswap(target_ulong v
)
231 v
= ((v
>> 1) & (target_ulong
)0x5555555555555555ULL
) |
232 ((v
& (target_ulong
)0x5555555555555555ULL
) << 1);
233 v
= ((v
>> 2) & (target_ulong
)0x3333333333333333ULL
) |
234 ((v
& (target_ulong
)0x3333333333333333ULL
) << 2);
235 v
= ((v
>> 4) & (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) |
236 ((v
& (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) << 4);
241 target_ulong
helper_dbitswap(target_ulong rt
)
247 target_ulong
helper_bitswap(target_ulong rt
)
249 return (int32_t)bitswap(rt
);
252 target_ulong
helper_rotx(target_ulong rs
, uint32_t shift
, uint32_t shiftx
,
256 uint64_t tmp0
= ((uint64_t)rs
) << 32 | ((uint64_t)rs
& 0xffffffff);
257 uint64_t tmp1
= tmp0
;
258 for (i
= 0; i
<= 46; i
++) {
266 if (stripe
!= 0 && !(i
& 0x4)) {
270 if (tmp0
& (1LL << (i
+ 16))) {
278 uint64_t tmp2
= tmp1
;
279 for (i
= 0; i
<= 38; i
++) {
288 if (tmp1
& (1LL << (i
+ 8))) {
296 uint64_t tmp3
= tmp2
;
297 for (i
= 0; i
<= 34; i
++) {
305 if (tmp2
& (1LL << (i
+ 4))) {
313 uint64_t tmp4
= tmp3
;
314 for (i
= 0; i
<= 32; i
++) {
322 if (tmp3
& (1LL << (i
+ 2))) {
330 uint64_t tmp5
= tmp4
;
331 for (i
= 0; i
<= 31; i
++) {
335 if (tmp4
& (1LL << (i
+ 1))) {
343 return (int64_t)(int32_t)(uint32_t)tmp5
;
346 #ifndef CONFIG_USER_ONLY
348 static inline hwaddr
do_translate_address(CPUMIPSState
*env
,
349 target_ulong address
,
350 int rw
, uintptr_t retaddr
)
353 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
355 paddr
= cpu_mips_translate_address(env
, address
, rw
);
358 cpu_loop_exit_restore(cs
, retaddr
);
364 #define HELPER_LD_ATOMIC(name, insn, almask) \
365 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
367 if (arg & almask) { \
368 if (!(env->hflags & MIPS_HFLAG_DM)) { \
369 env->CP0_BadVAddr = arg; \
371 do_raise_exception(env, EXCP_AdEL, GETPC()); \
373 env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC()); \
375 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
378 HELPER_LD_ATOMIC(ll
, lw
, 0x3)
380 HELPER_LD_ATOMIC(lld
, ld
, 0x7)
382 #undef HELPER_LD_ATOMIC
384 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
385 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
386 target_ulong arg2, int mem_idx) \
390 if (arg2 & almask) { \
391 if (!(env->hflags & MIPS_HFLAG_DM)) { \
392 env->CP0_BadVAddr = arg2; \
394 do_raise_exception(env, EXCP_AdES, GETPC()); \
396 if (arg2 == env->lladdr) { \
397 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
398 if (tmp == env->llval) { \
399 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
405 HELPER_ST_ATOMIC(sc
, lw
, sw
, 0x3)
407 HELPER_ST_ATOMIC(scd
, ld
, sd
, 0x7)
409 #undef HELPER_ST_ATOMIC
412 #ifdef TARGET_WORDS_BIGENDIAN
413 #define GET_LMASK(v) ((v) & 3)
414 #define GET_OFFSET(addr, offset) (addr + (offset))
416 #define GET_LMASK(v) (((v) & 3) ^ 3)
417 #define GET_OFFSET(addr, offset) (addr - (offset))
420 void helper_swl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
423 do_sb(env
, arg2
, (uint8_t)(arg1
>> 24), mem_idx
, GETPC());
425 if (GET_LMASK(arg2
) <= 2) {
426 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16), mem_idx
,
430 if (GET_LMASK(arg2
) <= 1) {
431 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8), mem_idx
,
435 if (GET_LMASK(arg2
) == 0) {
436 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)arg1
, mem_idx
,
441 void helper_swr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
444 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
446 if (GET_LMASK(arg2
) >= 1) {
447 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
451 if (GET_LMASK(arg2
) >= 2) {
452 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
456 if (GET_LMASK(arg2
) == 3) {
457 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
462 #if defined(TARGET_MIPS64)
463 /* "half" load and stores. We must do the memory access inline,
464 or fault handling won't work. */
466 #ifdef TARGET_WORDS_BIGENDIAN
467 #define GET_LMASK64(v) ((v) & 7)
469 #define GET_LMASK64(v) (((v) & 7) ^ 7)
472 void helper_sdl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
475 do_sb(env
, arg2
, (uint8_t)(arg1
>> 56), mem_idx
, GETPC());
477 if (GET_LMASK64(arg2
) <= 6) {
478 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48), mem_idx
,
482 if (GET_LMASK64(arg2
) <= 5) {
483 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40), mem_idx
,
487 if (GET_LMASK64(arg2
) <= 4) {
488 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32), mem_idx
,
492 if (GET_LMASK64(arg2
) <= 3) {
493 do_sb(env
, GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24), mem_idx
,
497 if (GET_LMASK64(arg2
) <= 2) {
498 do_sb(env
, GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16), mem_idx
,
502 if (GET_LMASK64(arg2
) <= 1) {
503 do_sb(env
, GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8), mem_idx
,
507 if (GET_LMASK64(arg2
) <= 0) {
508 do_sb(env
, GET_OFFSET(arg2
, 7), (uint8_t)arg1
, mem_idx
,
513 void helper_sdr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
516 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
518 if (GET_LMASK64(arg2
) >= 1) {
519 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
523 if (GET_LMASK64(arg2
) >= 2) {
524 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
528 if (GET_LMASK64(arg2
) >= 3) {
529 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
533 if (GET_LMASK64(arg2
) >= 4) {
534 do_sb(env
, GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32), mem_idx
,
538 if (GET_LMASK64(arg2
) >= 5) {
539 do_sb(env
, GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40), mem_idx
,
543 if (GET_LMASK64(arg2
) >= 6) {
544 do_sb(env
, GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48), mem_idx
,
548 if (GET_LMASK64(arg2
) == 7) {
549 do_sb(env
, GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56), mem_idx
,
553 #endif /* TARGET_MIPS64 */
555 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
557 void helper_lwm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
560 target_ulong base_reglist
= reglist
& 0xf;
561 target_ulong do_r31
= reglist
& 0x10;
563 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
566 for (i
= 0; i
< base_reglist
; i
++) {
567 env
->active_tc
.gpr
[multiple_regs
[i
]] =
568 (target_long
)do_lw(env
, addr
, mem_idx
, GETPC());
574 env
->active_tc
.gpr
[31] = (target_long
)do_lw(env
, addr
, mem_idx
,
579 void helper_swm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
582 target_ulong base_reglist
= reglist
& 0xf;
583 target_ulong do_r31
= reglist
& 0x10;
585 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
588 for (i
= 0; i
< base_reglist
; i
++) {
589 do_sw(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
596 do_sw(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
600 #if defined(TARGET_MIPS64)
601 void helper_ldm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
604 target_ulong base_reglist
= reglist
& 0xf;
605 target_ulong do_r31
= reglist
& 0x10;
607 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
610 for (i
= 0; i
< base_reglist
; i
++) {
611 env
->active_tc
.gpr
[multiple_regs
[i
]] = do_ld(env
, addr
, mem_idx
,
618 env
->active_tc
.gpr
[31] = do_ld(env
, addr
, mem_idx
, GETPC());
622 void helper_sdm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
625 target_ulong base_reglist
= reglist
& 0xf;
626 target_ulong do_r31
= reglist
& 0x10;
628 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
631 for (i
= 0; i
< base_reglist
; i
++) {
632 do_sd(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
639 do_sd(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
644 #ifndef CONFIG_USER_ONLY
646 static bool mips_vpe_is_wfi(MIPSCPU
*c
)
648 CPUState
*cpu
= CPU(c
);
649 CPUMIPSState
*env
= &c
->env
;
651 /* If the VPE is halted but otherwise active, it means it's waiting for
653 return cpu
->halted
&& mips_vpe_active(env
);
656 static bool mips_vp_is_wfi(MIPSCPU
*c
)
658 CPUState
*cpu
= CPU(c
);
659 CPUMIPSState
*env
= &c
->env
;
661 return cpu
->halted
&& mips_vp_active(env
);
664 static inline void mips_vpe_wake(MIPSCPU
*c
)
666 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
667 because there might be other conditions that state that c should
669 cpu_interrupt(CPU(c
), CPU_INTERRUPT_WAKE
);
672 static inline void mips_vpe_sleep(MIPSCPU
*cpu
)
674 CPUState
*cs
= CPU(cpu
);
676 /* The VPE was shut off, really go to bed.
677 Reset any old _WAKE requests. */
679 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
682 static inline void mips_tc_wake(MIPSCPU
*cpu
, int tc
)
684 CPUMIPSState
*c
= &cpu
->env
;
686 /* FIXME: TC reschedule. */
687 if (mips_vpe_active(c
) && !mips_vpe_is_wfi(cpu
)) {
692 static inline void mips_tc_sleep(MIPSCPU
*cpu
, int tc
)
694 CPUMIPSState
*c
= &cpu
->env
;
696 /* FIXME: TC reschedule. */
697 if (!mips_vpe_active(c
)) {
704 * @env: CPU from which mapping is performed.
705 * @tc: Should point to an int with the value of the global TC index.
707 * This function will transform @tc into a local index within the
708 * returned #CPUMIPSState.
710 /* FIXME: This code assumes that all VPEs have the same number of TCs,
711 which depends on runtime setup. Can probably be fixed by
712 walking the list of CPUMIPSStates. */
713 static CPUMIPSState
*mips_cpu_map_tc(CPUMIPSState
*env
, int *tc
)
721 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))) {
722 /* Not allowed to address other CPUs. */
723 *tc
= env
->current_tc
;
727 cs
= CPU(mips_env_get_cpu(env
));
728 vpe_idx
= tc_idx
/ cs
->nr_threads
;
729 *tc
= tc_idx
% cs
->nr_threads
;
730 other_cs
= qemu_get_cpu(vpe_idx
);
731 if (other_cs
== NULL
) {
734 cpu
= MIPS_CPU(other_cs
);
738 /* The per VPE CP0_Status register shares some fields with the per TC
739 CP0_TCStatus registers. These fields are wired to the same registers,
740 so changes to either of them should be reflected on both registers.
742 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
744 These helper call synchronizes the regs for a given cpu. */
746 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
747 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
750 /* Called for updates to CP0_TCStatus. */
751 static void sync_c0_tcstatus(CPUMIPSState
*cpu
, int tc
,
755 uint32_t tcu
, tmx
, tasid
, tksu
;
756 uint32_t mask
= ((1U << CP0St_CU3
)
763 tcu
= (v
>> CP0TCSt_TCU0
) & 0xf;
764 tmx
= (v
>> CP0TCSt_TMX
) & 0x1;
765 tasid
= v
& cpu
->CP0_EntryHi_ASID_mask
;
766 tksu
= (v
>> CP0TCSt_TKSU
) & 0x3;
768 status
= tcu
<< CP0St_CU0
;
769 status
|= tmx
<< CP0St_MX
;
770 status
|= tksu
<< CP0St_KSU
;
772 cpu
->CP0_Status
&= ~mask
;
773 cpu
->CP0_Status
|= status
;
775 /* Sync the TASID with EntryHi. */
776 cpu
->CP0_EntryHi
&= ~cpu
->CP0_EntryHi_ASID_mask
;
777 cpu
->CP0_EntryHi
|= tasid
;
782 /* Called for updates to CP0_EntryHi. */
783 static void sync_c0_entryhi(CPUMIPSState
*cpu
, int tc
)
786 uint32_t asid
, v
= cpu
->CP0_EntryHi
;
788 asid
= v
& cpu
->CP0_EntryHi_ASID_mask
;
790 if (tc
== cpu
->current_tc
) {
791 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
793 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
796 *tcst
&= ~cpu
->CP0_EntryHi_ASID_mask
;
801 target_ulong
helper_mfc0_mvpcontrol(CPUMIPSState
*env
)
803 return env
->mvp
->CP0_MVPControl
;
806 target_ulong
helper_mfc0_mvpconf0(CPUMIPSState
*env
)
808 return env
->mvp
->CP0_MVPConf0
;
811 target_ulong
helper_mfc0_mvpconf1(CPUMIPSState
*env
)
813 return env
->mvp
->CP0_MVPConf1
;
816 target_ulong
helper_mfc0_random(CPUMIPSState
*env
)
818 return (int32_t)cpu_mips_get_random(env
);
821 target_ulong
helper_mfc0_tcstatus(CPUMIPSState
*env
)
823 return env
->active_tc
.CP0_TCStatus
;
826 target_ulong
helper_mftc0_tcstatus(CPUMIPSState
*env
)
828 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
829 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
831 if (other_tc
== other
->current_tc
)
832 return other
->active_tc
.CP0_TCStatus
;
834 return other
->tcs
[other_tc
].CP0_TCStatus
;
837 target_ulong
helper_mfc0_tcbind(CPUMIPSState
*env
)
839 return env
->active_tc
.CP0_TCBind
;
842 target_ulong
helper_mftc0_tcbind(CPUMIPSState
*env
)
844 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
845 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
847 if (other_tc
== other
->current_tc
)
848 return other
->active_tc
.CP0_TCBind
;
850 return other
->tcs
[other_tc
].CP0_TCBind
;
853 target_ulong
helper_mfc0_tcrestart(CPUMIPSState
*env
)
855 return env
->active_tc
.PC
;
858 target_ulong
helper_mftc0_tcrestart(CPUMIPSState
*env
)
860 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
861 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
863 if (other_tc
== other
->current_tc
)
864 return other
->active_tc
.PC
;
866 return other
->tcs
[other_tc
].PC
;
869 target_ulong
helper_mfc0_tchalt(CPUMIPSState
*env
)
871 return env
->active_tc
.CP0_TCHalt
;
874 target_ulong
helper_mftc0_tchalt(CPUMIPSState
*env
)
876 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
877 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
879 if (other_tc
== other
->current_tc
)
880 return other
->active_tc
.CP0_TCHalt
;
882 return other
->tcs
[other_tc
].CP0_TCHalt
;
885 target_ulong
helper_mfc0_tccontext(CPUMIPSState
*env
)
887 return env
->active_tc
.CP0_TCContext
;
890 target_ulong
helper_mftc0_tccontext(CPUMIPSState
*env
)
892 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
893 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
895 if (other_tc
== other
->current_tc
)
896 return other
->active_tc
.CP0_TCContext
;
898 return other
->tcs
[other_tc
].CP0_TCContext
;
901 target_ulong
helper_mfc0_tcschedule(CPUMIPSState
*env
)
903 return env
->active_tc
.CP0_TCSchedule
;
906 target_ulong
helper_mftc0_tcschedule(CPUMIPSState
*env
)
908 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
909 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
911 if (other_tc
== other
->current_tc
)
912 return other
->active_tc
.CP0_TCSchedule
;
914 return other
->tcs
[other_tc
].CP0_TCSchedule
;
917 target_ulong
helper_mfc0_tcschefback(CPUMIPSState
*env
)
919 return env
->active_tc
.CP0_TCScheFBack
;
922 target_ulong
helper_mftc0_tcschefback(CPUMIPSState
*env
)
924 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
925 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
927 if (other_tc
== other
->current_tc
)
928 return other
->active_tc
.CP0_TCScheFBack
;
930 return other
->tcs
[other_tc
].CP0_TCScheFBack
;
933 target_ulong
helper_mfc0_count(CPUMIPSState
*env
)
936 qemu_mutex_lock_iothread();
937 count
= (int32_t) cpu_mips_get_count(env
);
938 qemu_mutex_unlock_iothread();
942 target_ulong
helper_mfc0_saar(CPUMIPSState
*env
)
944 if ((env
->CP0_SAARI
& 0x3f) < 2) {
945 return (int32_t) env
->CP0_SAAR
[env
->CP0_SAARI
& 0x3f];
950 target_ulong
helper_mfhc0_saar(CPUMIPSState
*env
)
952 if ((env
->CP0_SAARI
& 0x3f) < 2) {
953 return env
->CP0_SAAR
[env
->CP0_SAARI
& 0x3f] >> 32;
958 target_ulong
helper_mftc0_entryhi(CPUMIPSState
*env
)
960 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
961 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
963 return other
->CP0_EntryHi
;
966 target_ulong
helper_mftc0_cause(CPUMIPSState
*env
)
968 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
970 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
972 if (other_tc
== other
->current_tc
) {
973 tccause
= other
->CP0_Cause
;
975 tccause
= other
->CP0_Cause
;
981 target_ulong
helper_mftc0_status(CPUMIPSState
*env
)
983 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
984 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
986 return other
->CP0_Status
;
989 target_ulong
helper_mfc0_lladdr(CPUMIPSState
*env
)
991 return (int32_t)(env
->CP0_LLAddr
>> env
->CP0_LLAddr_shift
);
994 target_ulong
helper_mfc0_maar(CPUMIPSState
*env
)
996 return (int32_t) env
->CP0_MAAR
[env
->CP0_MAARI
];
999 target_ulong
helper_mfhc0_maar(CPUMIPSState
*env
)
1001 return env
->CP0_MAAR
[env
->CP0_MAARI
] >> 32;
1004 target_ulong
helper_mfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
1006 return (int32_t)env
->CP0_WatchLo
[sel
];
1009 target_ulong
helper_mfc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
1011 return env
->CP0_WatchHi
[sel
];
1014 target_ulong
helper_mfc0_debug(CPUMIPSState
*env
)
1016 target_ulong t0
= env
->CP0_Debug
;
1017 if (env
->hflags
& MIPS_HFLAG_DM
)
1018 t0
|= 1 << CP0DB_DM
;
1023 target_ulong
helper_mftc0_debug(CPUMIPSState
*env
)
1025 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1027 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1029 if (other_tc
== other
->current_tc
)
1030 tcstatus
= other
->active_tc
.CP0_Debug_tcstatus
;
1032 tcstatus
= other
->tcs
[other_tc
].CP0_Debug_tcstatus
;
1034 /* XXX: Might be wrong, check with EJTAG spec. */
1035 return (other
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1036 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1039 #if defined(TARGET_MIPS64)
1040 target_ulong
helper_dmfc0_tcrestart(CPUMIPSState
*env
)
1042 return env
->active_tc
.PC
;
1045 target_ulong
helper_dmfc0_tchalt(CPUMIPSState
*env
)
1047 return env
->active_tc
.CP0_TCHalt
;
1050 target_ulong
helper_dmfc0_tccontext(CPUMIPSState
*env
)
1052 return env
->active_tc
.CP0_TCContext
;
1055 target_ulong
helper_dmfc0_tcschedule(CPUMIPSState
*env
)
1057 return env
->active_tc
.CP0_TCSchedule
;
1060 target_ulong
helper_dmfc0_tcschefback(CPUMIPSState
*env
)
1062 return env
->active_tc
.CP0_TCScheFBack
;
1065 target_ulong
helper_dmfc0_lladdr(CPUMIPSState
*env
)
1067 return env
->CP0_LLAddr
>> env
->CP0_LLAddr_shift
;
1070 target_ulong
helper_dmfc0_maar(CPUMIPSState
*env
)
1072 return env
->CP0_MAAR
[env
->CP0_MAARI
];
1075 target_ulong
helper_dmfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
1077 return env
->CP0_WatchLo
[sel
];
1080 target_ulong
helper_dmfc0_saar(CPUMIPSState
*env
)
1082 if ((env
->CP0_SAARI
& 0x3f) < 2) {
1083 return env
->CP0_SAAR
[env
->CP0_SAARI
& 0x3f];
1087 #endif /* TARGET_MIPS64 */
1089 void helper_mtc0_index(CPUMIPSState
*env
, target_ulong arg1
)
1091 uint32_t index_p
= env
->CP0_Index
& 0x80000000;
1092 uint32_t tlb_index
= arg1
& 0x7fffffff;
1093 if (tlb_index
< env
->tlb
->nb_tlb
) {
1094 if (env
->insn_flags
& ISA_MIPS32R6
) {
1095 index_p
|= arg1
& 0x80000000;
1097 env
->CP0_Index
= index_p
| tlb_index
;
1101 void helper_mtc0_mvpcontrol(CPUMIPSState
*env
, target_ulong arg1
)
1106 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
1107 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
1108 (1 << CP0MVPCo_EVP
);
1109 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1110 mask
|= (1 << CP0MVPCo_STLB
);
1111 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
1113 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1115 env
->mvp
->CP0_MVPControl
= newval
;
1118 void helper_mtc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1123 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1124 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1125 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1127 /* Yield scheduler intercept not implemented. */
1128 /* Gating storage scheduler intercept not implemented. */
1130 // TODO: Enable/disable TCs.
1132 env
->CP0_VPEControl
= newval
;
1135 void helper_mttc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1137 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1138 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1142 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1143 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1144 newval
= (other
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1146 /* TODO: Enable/disable TCs. */
1148 other
->CP0_VPEControl
= newval
;
1151 target_ulong
helper_mftc0_vpecontrol(CPUMIPSState
*env
)
1153 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1154 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1155 /* FIXME: Mask away return zero on read bits. */
1156 return other
->CP0_VPEControl
;
1159 target_ulong
helper_mftc0_vpeconf0(CPUMIPSState
*env
)
1161 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1162 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1164 return other
->CP0_VPEConf0
;
1167 void helper_mtc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1172 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
1173 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
1174 mask
|= (0xff << CP0VPEC0_XTC
);
1175 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1177 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1179 // TODO: TC exclusive handling due to ERL/EXL.
1181 env
->CP0_VPEConf0
= newval
;
1184 void helper_mttc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1186 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1187 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1191 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1192 newval
= (other
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1194 /* TODO: TC exclusive handling due to ERL/EXL. */
1195 other
->CP0_VPEConf0
= newval
;
1198 void helper_mtc0_vpeconf1(CPUMIPSState
*env
, target_ulong arg1
)
1203 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1204 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
1205 (0xff << CP0VPEC1_NCP1
);
1206 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
1208 /* UDI not implemented. */
1209 /* CP2 not implemented. */
1211 // TODO: Handle FPU (CP1) binding.
1213 env
->CP0_VPEConf1
= newval
;
1216 void helper_mtc0_yqmask(CPUMIPSState
*env
, target_ulong arg1
)
1218 /* Yield qualifier inputs not implemented. */
1219 env
->CP0_YQMask
= 0x00000000;
1222 void helper_mtc0_vpeopt(CPUMIPSState
*env
, target_ulong arg1
)
1224 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
1227 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1229 void helper_mtc0_entrylo0(CPUMIPSState
*env
, target_ulong arg1
)
1231 /* 1k pages not implemented */
1232 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1233 env
->CP0_EntryLo0
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1234 | (rxi
<< (CP0EnLo_XI
- 30));
1237 #if defined(TARGET_MIPS64)
1238 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1240 void helper_dmtc0_entrylo0(CPUMIPSState
*env
, uint64_t arg1
)
1242 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1243 env
->CP0_EntryLo0
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1247 void helper_mtc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1249 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
1252 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
1254 env
->active_tc
.CP0_TCStatus
= newval
;
1255 sync_c0_tcstatus(env
, env
->current_tc
, newval
);
1258 void helper_mttc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1260 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1261 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1263 if (other_tc
== other
->current_tc
)
1264 other
->active_tc
.CP0_TCStatus
= arg1
;
1266 other
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
1267 sync_c0_tcstatus(other
, other_tc
, arg1
);
1270 void helper_mtc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1272 uint32_t mask
= (1 << CP0TCBd_TBE
);
1275 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1276 mask
|= (1 << CP0TCBd_CurVPE
);
1277 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1278 env
->active_tc
.CP0_TCBind
= newval
;
1281 void helper_mttc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1283 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1284 uint32_t mask
= (1 << CP0TCBd_TBE
);
1286 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1288 if (other
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1289 mask
|= (1 << CP0TCBd_CurVPE
);
1290 if (other_tc
== other
->current_tc
) {
1291 newval
= (other
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1292 other
->active_tc
.CP0_TCBind
= newval
;
1294 newval
= (other
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
1295 other
->tcs
[other_tc
].CP0_TCBind
= newval
;
1299 void helper_mtc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1301 env
->active_tc
.PC
= arg1
;
1302 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1303 env
->CP0_LLAddr
= 0;
1305 /* MIPS16 not implemented. */
1308 void helper_mttc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1310 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1311 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1313 if (other_tc
== other
->current_tc
) {
1314 other
->active_tc
.PC
= arg1
;
1315 other
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1316 other
->CP0_LLAddr
= 0;
1318 /* MIPS16 not implemented. */
1320 other
->tcs
[other_tc
].PC
= arg1
;
1321 other
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1322 other
->CP0_LLAddr
= 0;
1324 /* MIPS16 not implemented. */
1328 void helper_mtc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1330 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1332 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
1334 // TODO: Halt TC / Restart (if allocated+active) TC.
1335 if (env
->active_tc
.CP0_TCHalt
& 1) {
1336 mips_tc_sleep(cpu
, env
->current_tc
);
1338 mips_tc_wake(cpu
, env
->current_tc
);
1342 void helper_mttc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1344 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1345 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1346 MIPSCPU
*other_cpu
= mips_env_get_cpu(other
);
1348 // TODO: Halt TC / Restart (if allocated+active) TC.
1350 if (other_tc
== other
->current_tc
)
1351 other
->active_tc
.CP0_TCHalt
= arg1
;
1353 other
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
1356 mips_tc_sleep(other_cpu
, other_tc
);
1358 mips_tc_wake(other_cpu
, other_tc
);
1362 void helper_mtc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1364 env
->active_tc
.CP0_TCContext
= arg1
;
1367 void helper_mttc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1369 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1370 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1372 if (other_tc
== other
->current_tc
)
1373 other
->active_tc
.CP0_TCContext
= arg1
;
1375 other
->tcs
[other_tc
].CP0_TCContext
= arg1
;
1378 void helper_mtc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1380 env
->active_tc
.CP0_TCSchedule
= arg1
;
1383 void helper_mttc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1385 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1386 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1388 if (other_tc
== other
->current_tc
)
1389 other
->active_tc
.CP0_TCSchedule
= arg1
;
1391 other
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
1394 void helper_mtc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1396 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1399 void helper_mttc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1401 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1402 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1404 if (other_tc
== other
->current_tc
)
1405 other
->active_tc
.CP0_TCScheFBack
= arg1
;
1407 other
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
1410 void helper_mtc0_entrylo1(CPUMIPSState
*env
, target_ulong arg1
)
1412 /* 1k pages not implemented */
1413 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1414 env
->CP0_EntryLo1
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1415 | (rxi
<< (CP0EnLo_XI
- 30));
1418 #if defined(TARGET_MIPS64)
1419 void helper_dmtc0_entrylo1(CPUMIPSState
*env
, uint64_t arg1
)
1421 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1422 env
->CP0_EntryLo1
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1426 void helper_mtc0_context(CPUMIPSState
*env
, target_ulong arg1
)
1428 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
1431 void update_pagemask(CPUMIPSState
*env
, target_ulong arg1
, int32_t *pagemask
)
1433 uint64_t mask
= arg1
>> (TARGET_PAGE_BITS
+ 1);
1434 if (!(env
->insn_flags
& ISA_MIPS32R6
) || (arg1
== ~0) ||
1435 (mask
== 0x0000 || mask
== 0x0003 || mask
== 0x000F ||
1436 mask
== 0x003F || mask
== 0x00FF || mask
== 0x03FF ||
1437 mask
== 0x0FFF || mask
== 0x3FFF || mask
== 0xFFFF)) {
1438 env
->CP0_PageMask
= arg1
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1442 void helper_mtc0_pagemask(CPUMIPSState
*env
, target_ulong arg1
)
1444 update_pagemask(env
, arg1
, &env
->CP0_PageMask
);
1447 void helper_mtc0_pagegrain(CPUMIPSState
*env
, target_ulong arg1
)
1449 /* SmartMIPS not implemented */
1450 /* 1k pages not implemented */
1451 env
->CP0_PageGrain
= (arg1
& env
->CP0_PageGrain_rw_bitmask
) |
1452 (env
->CP0_PageGrain
& ~env
->CP0_PageGrain_rw_bitmask
);
1453 compute_hflags(env
);
1454 restore_pamask(env
);
1457 void helper_mtc0_segctl0(CPUMIPSState
*env
, target_ulong arg1
)
1459 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1461 env
->CP0_SegCtl0
= arg1
& CP0SC0_MASK
;
1465 void helper_mtc0_segctl1(CPUMIPSState
*env
, target_ulong arg1
)
1467 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1469 env
->CP0_SegCtl1
= arg1
& CP0SC1_MASK
;
1473 void helper_mtc0_segctl2(CPUMIPSState
*env
, target_ulong arg1
)
1475 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
1477 env
->CP0_SegCtl2
= arg1
& CP0SC2_MASK
;
1481 void helper_mtc0_pwfield(CPUMIPSState
*env
, target_ulong arg1
)
1483 #if defined(TARGET_MIPS64)
1484 uint64_t mask
= 0x3F3FFFFFFFULL
;
1485 uint32_t old_ptei
= (env
->CP0_PWField
>> CP0PF_PTEI
) & 0x3FULL
;
1486 uint32_t new_ptei
= (arg1
>> CP0PF_PTEI
) & 0x3FULL
;
1488 if ((env
->insn_flags
& ISA_MIPS32R6
)) {
1489 if (((arg1
>> CP0PF_BDI
) & 0x3FULL
) < 12) {
1490 mask
&= ~(0x3FULL
<< CP0PF_BDI
);
1492 if (((arg1
>> CP0PF_GDI
) & 0x3FULL
) < 12) {
1493 mask
&= ~(0x3FULL
<< CP0PF_GDI
);
1495 if (((arg1
>> CP0PF_UDI
) & 0x3FULL
) < 12) {
1496 mask
&= ~(0x3FULL
<< CP0PF_UDI
);
1498 if (((arg1
>> CP0PF_MDI
) & 0x3FULL
) < 12) {
1499 mask
&= ~(0x3FULL
<< CP0PF_MDI
);
1501 if (((arg1
>> CP0PF_PTI
) & 0x3FULL
) < 12) {
1502 mask
&= ~(0x3FULL
<< CP0PF_PTI
);
1505 env
->CP0_PWField
= arg1
& mask
;
1507 if ((new_ptei
>= 32) ||
1508 ((env
->insn_flags
& ISA_MIPS32R6
) &&
1509 (new_ptei
== 0 || new_ptei
== 1))) {
1510 env
->CP0_PWField
= (env
->CP0_PWField
& ~0x3FULL
) |
1511 (old_ptei
<< CP0PF_PTEI
);
1514 uint32_t mask
= 0x3FFFFFFF;
1515 uint32_t old_ptew
= (env
->CP0_PWField
>> CP0PF_PTEW
) & 0x3F;
1516 uint32_t new_ptew
= (arg1
>> CP0PF_PTEW
) & 0x3F;
1518 if ((env
->insn_flags
& ISA_MIPS32R6
)) {
1519 if (((arg1
>> CP0PF_GDW
) & 0x3F) < 12) {
1520 mask
&= ~(0x3F << CP0PF_GDW
);
1522 if (((arg1
>> CP0PF_UDW
) & 0x3F) < 12) {
1523 mask
&= ~(0x3F << CP0PF_UDW
);
1525 if (((arg1
>> CP0PF_MDW
) & 0x3F) < 12) {
1526 mask
&= ~(0x3F << CP0PF_MDW
);
1528 if (((arg1
>> CP0PF_PTW
) & 0x3F) < 12) {
1529 mask
&= ~(0x3F << CP0PF_PTW
);
1532 env
->CP0_PWField
= arg1
& mask
;
1534 if ((new_ptew
>= 32) ||
1535 ((env
->insn_flags
& ISA_MIPS32R6
) &&
1536 (new_ptew
== 0 || new_ptew
== 1))) {
1537 env
->CP0_PWField
= (env
->CP0_PWField
& ~0x3F) |
1538 (old_ptew
<< CP0PF_PTEW
);
1543 void helper_mtc0_pwsize(CPUMIPSState
*env
, target_ulong arg1
)
1545 #if defined(TARGET_MIPS64)
1546 env
->CP0_PWSize
= arg1
& 0x3F7FFFFFFFULL
;
1548 env
->CP0_PWSize
= arg1
& 0x3FFFFFFF;
1552 void helper_mtc0_wired(CPUMIPSState
*env
, target_ulong arg1
)
1554 if (env
->insn_flags
& ISA_MIPS32R6
) {
1555 if (arg1
< env
->tlb
->nb_tlb
) {
1556 env
->CP0_Wired
= arg1
;
1559 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1563 void helper_mtc0_pwctl(CPUMIPSState
*env
, target_ulong arg1
)
1565 #if defined(TARGET_MIPS64)
1566 /* PWEn = 0. Hardware page table walking is not implemented. */
1567 env
->CP0_PWCtl
= (env
->CP0_PWCtl
& 0x000000C0) | (arg1
& 0x5C00003F);
1569 env
->CP0_PWCtl
= (arg1
& 0x800000FF);
1573 void helper_mtc0_srsconf0(CPUMIPSState
*env
, target_ulong arg1
)
1575 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1578 void helper_mtc0_srsconf1(CPUMIPSState
*env
, target_ulong arg1
)
1580 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1583 void helper_mtc0_srsconf2(CPUMIPSState
*env
, target_ulong arg1
)
1585 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1588 void helper_mtc0_srsconf3(CPUMIPSState
*env
, target_ulong arg1
)
1590 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1593 void helper_mtc0_srsconf4(CPUMIPSState
*env
, target_ulong arg1
)
1595 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1598 void helper_mtc0_hwrena(CPUMIPSState
*env
, target_ulong arg1
)
1600 uint32_t mask
= 0x0000000F;
1602 if ((env
->CP0_Config1
& (1 << CP0C1_PC
)) &&
1603 (env
->insn_flags
& ISA_MIPS32R6
)) {
1606 if (env
->insn_flags
& ISA_MIPS32R6
) {
1609 if (env
->CP0_Config3
& (1 << CP0C3_ULRI
)) {
1612 if (arg1
& (1 << 29)) {
1613 env
->hflags
|= MIPS_HFLAG_HWRENA_ULR
;
1615 env
->hflags
&= ~MIPS_HFLAG_HWRENA_ULR
;
1619 env
->CP0_HWREna
= arg1
& mask
;
1622 void helper_mtc0_count(CPUMIPSState
*env
, target_ulong arg1
)
1624 qemu_mutex_lock_iothread();
1625 cpu_mips_store_count(env
, arg1
);
1626 qemu_mutex_unlock_iothread();
1629 void helper_mtc0_saari(CPUMIPSState
*env
, target_ulong arg1
)
1631 uint32_t target
= arg1
& 0x3f;
1633 env
->CP0_SAARI
= target
;
1637 void helper_mtc0_saar(CPUMIPSState
*env
, target_ulong arg1
)
1639 uint32_t target
= env
->CP0_SAARI
& 0x3f;
1641 env
->CP0_SAAR
[target
] = arg1
& 0x00000ffffffff03fULL
;
1645 itc_reconfigure(env
->itu
);
1652 void helper_mthc0_saar(CPUMIPSState
*env
, target_ulong arg1
)
1654 uint32_t target
= env
->CP0_SAARI
& 0x3f;
1656 env
->CP0_SAAR
[target
] =
1657 (((uint64_t) arg1
<< 32) & 0x00000fff00000000ULL
) |
1658 (env
->CP0_SAAR
[target
] & 0x00000000ffffffffULL
);
1662 itc_reconfigure(env
->itu
);
1669 void helper_mtc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1671 target_ulong old
, val
, mask
;
1672 mask
= (TARGET_PAGE_MASK
<< 1) | env
->CP0_EntryHi_ASID_mask
;
1673 if (((env
->CP0_Config4
>> CP0C4_IE
) & 0x3) >= 2) {
1674 mask
|= 1 << CP0EnHi_EHINV
;
1677 /* 1k pages not implemented */
1678 #if defined(TARGET_MIPS64)
1679 if (env
->insn_flags
& ISA_MIPS32R6
) {
1680 int entryhi_r
= extract64(arg1
, 62, 2);
1681 int config0_at
= extract32(env
->CP0_Config0
, 13, 2);
1682 bool no_supervisor
= (env
->CP0_Status_rw_bitmask
& 0x8) == 0;
1683 if ((entryhi_r
== 2) ||
1684 (entryhi_r
== 1 && (no_supervisor
|| config0_at
== 1))) {
1685 /* skip EntryHi.R field if new value is reserved */
1686 mask
&= ~(0x3ull
<< 62);
1689 mask
&= env
->SEGMask
;
1691 old
= env
->CP0_EntryHi
;
1692 val
= (arg1
& mask
) | (old
& ~mask
);
1693 env
->CP0_EntryHi
= val
;
1694 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1695 sync_c0_entryhi(env
, env
->current_tc
);
1697 /* If the ASID changes, flush qemu's TLB. */
1698 if ((old
& env
->CP0_EntryHi_ASID_mask
) !=
1699 (val
& env
->CP0_EntryHi_ASID_mask
)) {
1700 tlb_flush(CPU(mips_env_get_cpu(env
)));
1704 void helper_mttc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1706 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1707 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1709 other
->CP0_EntryHi
= arg1
;
1710 sync_c0_entryhi(other
, other_tc
);
1713 void helper_mtc0_compare(CPUMIPSState
*env
, target_ulong arg1
)
1715 qemu_mutex_lock_iothread();
1716 cpu_mips_store_compare(env
, arg1
);
1717 qemu_mutex_unlock_iothread();
1720 void helper_mtc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1722 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1725 old
= env
->CP0_Status
;
1726 cpu_mips_store_status(env
, arg1
);
1727 val
= env
->CP0_Status
;
1729 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1730 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1731 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1732 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1734 switch (cpu_mmu_index(env
, false)) {
1736 qemu_log(", ERL\n");
1738 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1739 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1740 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1742 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
1748 void helper_mttc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1750 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1751 uint32_t mask
= env
->CP0_Status_rw_bitmask
& ~0xf1000018;
1752 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1754 other
->CP0_Status
= (other
->CP0_Status
& ~mask
) | (arg1
& mask
);
1755 sync_c0_status(env
, other
, other_tc
);
1758 void helper_mtc0_intctl(CPUMIPSState
*env
, target_ulong arg1
)
1760 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000003e0) | (arg1
& 0x000003e0);
1763 void helper_mtc0_srsctl(CPUMIPSState
*env
, target_ulong arg1
)
1765 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1766 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1769 void helper_mtc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1771 qemu_mutex_lock_iothread();
1772 cpu_mips_store_cause(env
, arg1
);
1773 qemu_mutex_unlock_iothread();
1776 void helper_mttc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1778 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1779 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1781 cpu_mips_store_cause(other
, arg1
);
1784 target_ulong
helper_mftc0_epc(CPUMIPSState
*env
)
1786 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1787 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1789 return other
->CP0_EPC
;
1792 target_ulong
helper_mftc0_ebase(CPUMIPSState
*env
)
1794 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1795 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1797 return other
->CP0_EBase
;
1800 void helper_mtc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1802 target_ulong mask
= 0x3FFFF000 | env
->CP0_EBaseWG_rw_bitmask
;
1803 if (arg1
& env
->CP0_EBaseWG_rw_bitmask
) {
1804 mask
|= ~0x3FFFFFFF;
1806 env
->CP0_EBase
= (env
->CP0_EBase
& ~mask
) | (arg1
& mask
);
1809 void helper_mttc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1811 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1812 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1813 target_ulong mask
= 0x3FFFF000 | env
->CP0_EBaseWG_rw_bitmask
;
1814 if (arg1
& env
->CP0_EBaseWG_rw_bitmask
) {
1815 mask
|= ~0x3FFFFFFF;
1817 other
->CP0_EBase
= (other
->CP0_EBase
& ~mask
) | (arg1
& mask
);
1820 target_ulong
helper_mftc0_configx(CPUMIPSState
*env
, target_ulong idx
)
1822 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1823 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1826 case 0: return other
->CP0_Config0
;
1827 case 1: return other
->CP0_Config1
;
1828 case 2: return other
->CP0_Config2
;
1829 case 3: return other
->CP0_Config3
;
1830 /* 4 and 5 are reserved. */
1831 case 6: return other
->CP0_Config6
;
1832 case 7: return other
->CP0_Config7
;
1839 void helper_mtc0_config0(CPUMIPSState
*env
, target_ulong arg1
)
1841 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1844 void helper_mtc0_config2(CPUMIPSState
*env
, target_ulong arg1
)
1846 /* tertiary/secondary caches not implemented */
1847 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1850 void helper_mtc0_config3(CPUMIPSState
*env
, target_ulong arg1
)
1852 if (env
->insn_flags
& ASE_MICROMIPS
) {
1853 env
->CP0_Config3
= (env
->CP0_Config3
& ~(1 << CP0C3_ISA_ON_EXC
)) |
1854 (arg1
& (1 << CP0C3_ISA_ON_EXC
));
1858 void helper_mtc0_config4(CPUMIPSState
*env
, target_ulong arg1
)
1860 env
->CP0_Config4
= (env
->CP0_Config4
& (~env
->CP0_Config4_rw_bitmask
)) |
1861 (arg1
& env
->CP0_Config4_rw_bitmask
);
1864 void helper_mtc0_config5(CPUMIPSState
*env
, target_ulong arg1
)
1866 env
->CP0_Config5
= (env
->CP0_Config5
& (~env
->CP0_Config5_rw_bitmask
)) |
1867 (arg1
& env
->CP0_Config5_rw_bitmask
);
1868 compute_hflags(env
);
1871 void helper_mtc0_lladdr(CPUMIPSState
*env
, target_ulong arg1
)
1873 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1874 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1875 env
->CP0_LLAddr
= (env
->CP0_LLAddr
& ~mask
) | (arg1
& mask
);
1878 #define MTC0_MAAR_MASK(env) \
1879 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1881 void helper_mtc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1883 env
->CP0_MAAR
[env
->CP0_MAARI
] = arg1
& MTC0_MAAR_MASK(env
);
1886 void helper_mthc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1888 env
->CP0_MAAR
[env
->CP0_MAARI
] =
1889 (((uint64_t) arg1
<< 32) & MTC0_MAAR_MASK(env
)) |
1890 (env
->CP0_MAAR
[env
->CP0_MAARI
] & 0x00000000ffffffffULL
);
1893 void helper_mtc0_maari(CPUMIPSState
*env
, target_ulong arg1
)
1895 int index
= arg1
& 0x3f;
1896 if (index
== 0x3f) {
1897 /* Software may write all ones to INDEX to determine the
1898 maximum value supported. */
1899 env
->CP0_MAARI
= MIPS_MAAR_MAX
- 1;
1900 } else if (index
< MIPS_MAAR_MAX
) {
1901 env
->CP0_MAARI
= index
;
1903 /* Other than the all ones, if the
1904 value written is not supported, then INDEX is unchanged
1905 from its previous value. */
1908 void helper_mtc0_watchlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1910 /* Watch exceptions for instructions, data loads, data stores
1912 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1915 void helper_mtc0_watchhi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1917 int mask
= 0x40000FF8 | (env
->CP0_EntryHi_ASID_mask
<< CP0WH_ASID
);
1918 env
->CP0_WatchHi
[sel
] = arg1
& mask
;
1919 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1922 void helper_mtc0_xcontext(CPUMIPSState
*env
, target_ulong arg1
)
1924 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1925 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1928 void helper_mtc0_framemask(CPUMIPSState
*env
, target_ulong arg1
)
1930 env
->CP0_Framemask
= arg1
; /* XXX */
1933 void helper_mtc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1935 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1936 if (arg1
& (1 << CP0DB_DM
))
1937 env
->hflags
|= MIPS_HFLAG_DM
;
1939 env
->hflags
&= ~MIPS_HFLAG_DM
;
1942 void helper_mttc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1944 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1945 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1946 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1948 /* XXX: Might be wrong, check with EJTAG spec. */
1949 if (other_tc
== other
->current_tc
)
1950 other
->active_tc
.CP0_Debug_tcstatus
= val
;
1952 other
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1953 other
->CP0_Debug
= (other
->CP0_Debug
&
1954 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1955 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1958 void helper_mtc0_performance0(CPUMIPSState
*env
, target_ulong arg1
)
1960 env
->CP0_Performance0
= arg1
& 0x000007ff;
1963 void helper_mtc0_errctl(CPUMIPSState
*env
, target_ulong arg1
)
1965 int32_t wst
= arg1
& (1 << CP0EC_WST
);
1966 int32_t spr
= arg1
& (1 << CP0EC_SPR
);
1967 int32_t itc
= env
->itc_tag
? (arg1
& (1 << CP0EC_ITC
)) : 0;
1969 env
->CP0_ErrCtl
= wst
| spr
| itc
;
1971 if (itc
&& !wst
&& !spr
) {
1972 env
->hflags
|= MIPS_HFLAG_ITC_CACHE
;
1974 env
->hflags
&= ~MIPS_HFLAG_ITC_CACHE
;
1978 void helper_mtc0_taglo(CPUMIPSState
*env
, target_ulong arg1
)
1980 if (env
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
1981 /* If CACHE instruction is configured for ITC tags then make all
1982 CP0.TagLo bits writable. The actual write to ITC Configuration
1983 Tag will take care of the read-only bits. */
1984 env
->CP0_TagLo
= arg1
;
1986 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1990 void helper_mtc0_datalo(CPUMIPSState
*env
, target_ulong arg1
)
1992 env
->CP0_DataLo
= arg1
; /* XXX */
1995 void helper_mtc0_taghi(CPUMIPSState
*env
, target_ulong arg1
)
1997 env
->CP0_TagHi
= arg1
; /* XXX */
2000 void helper_mtc0_datahi(CPUMIPSState
*env
, target_ulong arg1
)
2002 env
->CP0_DataHi
= arg1
; /* XXX */
2005 /* MIPS MT functions */
2006 target_ulong
helper_mftgpr(CPUMIPSState
*env
, uint32_t sel
)
2008 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2009 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2011 if (other_tc
== other
->current_tc
)
2012 return other
->active_tc
.gpr
[sel
];
2014 return other
->tcs
[other_tc
].gpr
[sel
];
2017 target_ulong
helper_mftlo(CPUMIPSState
*env
, uint32_t sel
)
2019 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2020 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2022 if (other_tc
== other
->current_tc
)
2023 return other
->active_tc
.LO
[sel
];
2025 return other
->tcs
[other_tc
].LO
[sel
];
2028 target_ulong
helper_mfthi(CPUMIPSState
*env
, uint32_t sel
)
2030 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2031 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2033 if (other_tc
== other
->current_tc
)
2034 return other
->active_tc
.HI
[sel
];
2036 return other
->tcs
[other_tc
].HI
[sel
];
2039 target_ulong
helper_mftacx(CPUMIPSState
*env
, uint32_t sel
)
2041 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2042 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2044 if (other_tc
== other
->current_tc
)
2045 return other
->active_tc
.ACX
[sel
];
2047 return other
->tcs
[other_tc
].ACX
[sel
];
2050 target_ulong
helper_mftdsp(CPUMIPSState
*env
)
2052 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2053 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2055 if (other_tc
== other
->current_tc
)
2056 return other
->active_tc
.DSPControl
;
2058 return other
->tcs
[other_tc
].DSPControl
;
2061 void helper_mttgpr(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
2063 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2064 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2066 if (other_tc
== other
->current_tc
)
2067 other
->active_tc
.gpr
[sel
] = arg1
;
2069 other
->tcs
[other_tc
].gpr
[sel
] = arg1
;
2072 void helper_mttlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
2074 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2075 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2077 if (other_tc
== other
->current_tc
)
2078 other
->active_tc
.LO
[sel
] = arg1
;
2080 other
->tcs
[other_tc
].LO
[sel
] = arg1
;
2083 void helper_mtthi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
2085 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2086 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2088 if (other_tc
== other
->current_tc
)
2089 other
->active_tc
.HI
[sel
] = arg1
;
2091 other
->tcs
[other_tc
].HI
[sel
] = arg1
;
2094 void helper_mttacx(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
2096 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2097 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2099 if (other_tc
== other
->current_tc
)
2100 other
->active_tc
.ACX
[sel
] = arg1
;
2102 other
->tcs
[other_tc
].ACX
[sel
] = arg1
;
2105 void helper_mttdsp(CPUMIPSState
*env
, target_ulong arg1
)
2107 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
2108 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
2110 if (other_tc
== other
->current_tc
)
2111 other
->active_tc
.DSPControl
= arg1
;
2113 other
->tcs
[other_tc
].DSPControl
= arg1
;
2116 /* MIPS MT functions */
2117 target_ulong
helper_dmt(void)
2123 target_ulong
helper_emt(void)
2129 target_ulong
helper_dvpe(CPUMIPSState
*env
)
2131 CPUState
*other_cs
= first_cpu
;
2132 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
2134 CPU_FOREACH(other_cs
) {
2135 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
2136 /* Turn off all VPEs except the one executing the dvpe. */
2137 if (&other_cpu
->env
!= env
) {
2138 other_cpu
->env
.mvp
->CP0_MVPControl
&= ~(1 << CP0MVPCo_EVP
);
2139 mips_vpe_sleep(other_cpu
);
2145 target_ulong
helper_evpe(CPUMIPSState
*env
)
2147 CPUState
*other_cs
= first_cpu
;
2148 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
2150 CPU_FOREACH(other_cs
) {
2151 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
2153 if (&other_cpu
->env
!= env
2154 /* If the VPE is WFI, don't disturb its sleep. */
2155 && !mips_vpe_is_wfi(other_cpu
)) {
2156 /* Enable the VPE. */
2157 other_cpu
->env
.mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
2158 mips_vpe_wake(other_cpu
); /* And wake it up. */
2163 #endif /* !CONFIG_USER_ONLY */
2165 void helper_fork(target_ulong arg1
, target_ulong arg2
)
2167 // arg1 = rt, arg2 = rs
2168 // TODO: store to TC register
2171 target_ulong
helper_yield(CPUMIPSState
*env
, target_ulong arg
)
2173 target_long arg1
= arg
;
2176 /* No scheduling policy implemented. */
2178 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
2179 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
2180 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
2181 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
2182 do_raise_exception(env
, EXCP_THREAD
, GETPC());
2185 } else if (arg1
== 0) {
2186 if (0 /* TODO: TC underflow */) {
2187 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
2188 do_raise_exception(env
, EXCP_THREAD
, GETPC());
2190 // TODO: Deallocate TC
2192 } else if (arg1
> 0) {
2193 /* Yield qualifier inputs not implemented. */
2194 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
2195 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
2196 do_raise_exception(env
, EXCP_THREAD
, GETPC());
2198 return env
->CP0_YQMask
;
2201 /* R6 Multi-threading */
2202 #ifndef CONFIG_USER_ONLY
2203 target_ulong
helper_dvp(CPUMIPSState
*env
)
2205 CPUState
*other_cs
= first_cpu
;
2206 target_ulong prev
= env
->CP0_VPControl
;
2208 if (!((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
2209 CPU_FOREACH(other_cs
) {
2210 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
2211 /* Turn off all VPs except the one executing the dvp. */
2212 if (&other_cpu
->env
!= env
) {
2213 mips_vpe_sleep(other_cpu
);
2216 env
->CP0_VPControl
|= (1 << CP0VPCtl_DIS
);
2221 target_ulong
helper_evp(CPUMIPSState
*env
)
2223 CPUState
*other_cs
= first_cpu
;
2224 target_ulong prev
= env
->CP0_VPControl
;
2226 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
2227 CPU_FOREACH(other_cs
) {
2228 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
2229 if ((&other_cpu
->env
!= env
) && !mips_vp_is_wfi(other_cpu
)) {
2230 /* If the VP is WFI, don't disturb its sleep.
2231 * Otherwise, wake it up. */
2232 mips_vpe_wake(other_cpu
);
2235 env
->CP0_VPControl
&= ~(1 << CP0VPCtl_DIS
);
2239 #endif /* !CONFIG_USER_ONLY */
2241 #ifndef CONFIG_USER_ONLY
2242 /* TLB management */
2243 static void r4k_mips_tlb_flush_extra (CPUMIPSState
*env
, int first
)
2245 /* Discard entries from env->tlb[first] onwards. */
2246 while (env
->tlb
->tlb_in_use
> first
) {
2247 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
2251 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo
)
2253 #if defined(TARGET_MIPS64)
2254 return extract64(entrylo
, 6, 54);
2256 return extract64(entrylo
, 6, 24) | /* PFN */
2257 (extract64(entrylo
, 32, 32) << 24); /* PFNX */
2261 static void r4k_fill_tlb(CPUMIPSState
*env
, int idx
)
2264 uint64_t mask
= env
->CP0_PageMask
>> (TARGET_PAGE_BITS
+ 1);
2266 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
2267 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2268 if (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) {
2273 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
2274 #if defined(TARGET_MIPS64)
2275 tlb
->VPN
&= env
->SEGMask
;
2277 tlb
->ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2278 tlb
->PageMask
= env
->CP0_PageMask
;
2279 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
2280 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
2281 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
2282 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
2283 tlb
->XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) & 1;
2284 tlb
->RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) & 1;
2285 tlb
->PFN
[0] = (get_tlb_pfn_from_entrylo(env
->CP0_EntryLo0
) & ~mask
) << 12;
2286 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
2287 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
2288 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
2289 tlb
->XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) & 1;
2290 tlb
->RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) & 1;
2291 tlb
->PFN
[1] = (get_tlb_pfn_from_entrylo(env
->CP0_EntryLo1
) & ~mask
) << 12;
2294 void r4k_helper_tlbinv(CPUMIPSState
*env
)
2298 uint16_t ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2300 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2301 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2302 if (!tlb
->G
&& tlb
->ASID
== ASID
) {
2306 cpu_mips_tlb_flush(env
);
2309 void r4k_helper_tlbinvf(CPUMIPSState
*env
)
2313 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2314 env
->tlb
->mmu
.r4k
.tlb
[idx
].EHINV
= 1;
2316 cpu_mips_tlb_flush(env
);
2319 void r4k_helper_tlbwi(CPUMIPSState
*env
)
2325 bool EHINV
, G
, V0
, D0
, V1
, D1
, XI0
, XI1
, RI0
, RI1
;
2327 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2328 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2329 VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
2330 #if defined(TARGET_MIPS64)
2331 VPN
&= env
->SEGMask
;
2333 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2334 EHINV
= (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) != 0;
2335 G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
2336 V0
= (env
->CP0_EntryLo0
& 2) != 0;
2337 D0
= (env
->CP0_EntryLo0
& 4) != 0;
2338 XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) &1;
2339 RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) &1;
2340 V1
= (env
->CP0_EntryLo1
& 2) != 0;
2341 D1
= (env
->CP0_EntryLo1
& 4) != 0;
2342 XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) &1;
2343 RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) &1;
2345 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2346 permissions on the current entry. */
2347 if (tlb
->VPN
!= VPN
|| tlb
->ASID
!= ASID
|| tlb
->G
!= G
||
2348 (!tlb
->EHINV
&& EHINV
) ||
2349 (tlb
->V0
&& !V0
) || (tlb
->D0
&& !D0
) ||
2350 (!tlb
->XI0
&& XI0
) || (!tlb
->RI0
&& RI0
) ||
2351 (tlb
->V1
&& !V1
) || (tlb
->D1
&& !D1
) ||
2352 (!tlb
->XI1
&& XI1
) || (!tlb
->RI1
&& RI1
)) {
2353 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2356 r4k_invalidate_tlb(env
, idx
, 0);
2357 r4k_fill_tlb(env
, idx
);
2360 void r4k_helper_tlbwr(CPUMIPSState
*env
)
2362 int r
= cpu_mips_get_random(env
);
2364 r4k_invalidate_tlb(env
, r
, 1);
2365 r4k_fill_tlb(env
, r
);
2368 void r4k_helper_tlbp(CPUMIPSState
*env
)
2377 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2378 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
2379 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2380 /* 1k pages are not supported. */
2381 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2382 tag
= env
->CP0_EntryHi
& ~mask
;
2383 VPN
= tlb
->VPN
& ~mask
;
2384 #if defined(TARGET_MIPS64)
2385 tag
&= env
->SEGMask
;
2387 /* Check ASID, virtual page number & size */
2388 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
&& !tlb
->EHINV
) {
2394 if (i
== env
->tlb
->nb_tlb
) {
2395 /* No match. Discard any shadow entries, if any of them match. */
2396 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
2397 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2398 /* 1k pages are not supported. */
2399 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2400 tag
= env
->CP0_EntryHi
& ~mask
;
2401 VPN
= tlb
->VPN
& ~mask
;
2402 #if defined(TARGET_MIPS64)
2403 tag
&= env
->SEGMask
;
2405 /* Check ASID, virtual page number & size */
2406 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
2407 r4k_mips_tlb_flush_extra (env
, i
);
2412 env
->CP0_Index
|= 0x80000000;
2416 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn
)
2418 #if defined(TARGET_MIPS64)
2419 return tlb_pfn
<< 6;
2421 return (extract64(tlb_pfn
, 0, 24) << 6) | /* PFN */
2422 (extract64(tlb_pfn
, 24, 32) << 32); /* PFNX */
2426 void r4k_helper_tlbr(CPUMIPSState
*env
)
2432 ASID
= env
->CP0_EntryHi
& env
->CP0_EntryHi_ASID_mask
;
2433 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2434 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2436 /* If this will change the current ASID, flush qemu's TLB. */
2437 if (ASID
!= tlb
->ASID
)
2438 cpu_mips_tlb_flush(env
);
2440 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2443 env
->CP0_EntryHi
= 1 << CP0EnHi_EHINV
;
2444 env
->CP0_PageMask
= 0;
2445 env
->CP0_EntryLo0
= 0;
2446 env
->CP0_EntryLo1
= 0;
2448 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
2449 env
->CP0_PageMask
= tlb
->PageMask
;
2450 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
2451 ((uint64_t)tlb
->RI0
<< CP0EnLo_RI
) |
2452 ((uint64_t)tlb
->XI0
<< CP0EnLo_XI
) | (tlb
->C0
<< 3) |
2453 get_entrylo_pfn_from_tlb(tlb
->PFN
[0] >> 12);
2454 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
2455 ((uint64_t)tlb
->RI1
<< CP0EnLo_RI
) |
2456 ((uint64_t)tlb
->XI1
<< CP0EnLo_XI
) | (tlb
->C1
<< 3) |
2457 get_entrylo_pfn_from_tlb(tlb
->PFN
[1] >> 12);
2461 void helper_tlbwi(CPUMIPSState
*env
)
2463 env
->tlb
->helper_tlbwi(env
);
2466 void helper_tlbwr(CPUMIPSState
*env
)
2468 env
->tlb
->helper_tlbwr(env
);
2471 void helper_tlbp(CPUMIPSState
*env
)
2473 env
->tlb
->helper_tlbp(env
);
2476 void helper_tlbr(CPUMIPSState
*env
)
2478 env
->tlb
->helper_tlbr(env
);
2481 void helper_tlbinv(CPUMIPSState
*env
)
2483 env
->tlb
->helper_tlbinv(env
);
2486 void helper_tlbinvf(CPUMIPSState
*env
)
2488 env
->tlb
->helper_tlbinvf(env
);
2492 target_ulong
helper_di(CPUMIPSState
*env
)
2494 target_ulong t0
= env
->CP0_Status
;
2496 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
2500 target_ulong
helper_ei(CPUMIPSState
*env
)
2502 target_ulong t0
= env
->CP0_Status
;
2504 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
2508 static void debug_pre_eret(CPUMIPSState
*env
)
2510 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2511 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2512 env
->active_tc
.PC
, env
->CP0_EPC
);
2513 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2514 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2515 if (env
->hflags
& MIPS_HFLAG_DM
)
2516 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2521 static void debug_post_eret(CPUMIPSState
*env
)
2523 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
2525 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2526 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2527 env
->active_tc
.PC
, env
->CP0_EPC
);
2528 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2529 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2530 if (env
->hflags
& MIPS_HFLAG_DM
)
2531 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2532 switch (cpu_mmu_index(env
, false)) {
2534 qemu_log(", ERL\n");
2536 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
2537 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
2538 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
2540 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
2546 static void set_pc(CPUMIPSState
*env
, target_ulong error_pc
)
2548 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
2550 env
->hflags
|= MIPS_HFLAG_M16
;
2552 env
->hflags
&= ~(MIPS_HFLAG_M16
);
2556 static inline void exception_return(CPUMIPSState
*env
)
2558 debug_pre_eret(env
);
2559 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2560 set_pc(env
, env
->CP0_ErrorEPC
);
2561 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2563 set_pc(env
, env
->CP0_EPC
);
2564 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2566 compute_hflags(env
);
2567 debug_post_eret(env
);
2570 void helper_eret(CPUMIPSState
*env
)
2572 exception_return(env
);
2573 env
->CP0_LLAddr
= 1;
2577 void helper_eretnc(CPUMIPSState
*env
)
2579 exception_return(env
);
2582 void helper_deret(CPUMIPSState
*env
)
2584 debug_pre_eret(env
);
2586 env
->hflags
&= ~MIPS_HFLAG_DM
;
2587 compute_hflags(env
);
2589 set_pc(env
, env
->CP0_DEPC
);
2591 debug_post_eret(env
);
2593 #endif /* !CONFIG_USER_ONLY */
2595 static inline void check_hwrena(CPUMIPSState
*env
, int reg
, uintptr_t pc
)
2597 if ((env
->hflags
& MIPS_HFLAG_CP0
) || (env
->CP0_HWREna
& (1 << reg
))) {
2600 do_raise_exception(env
, EXCP_RI
, pc
);
2603 target_ulong
helper_rdhwr_cpunum(CPUMIPSState
*env
)
2605 check_hwrena(env
, 0, GETPC());
2606 return env
->CP0_EBase
& 0x3ff;
2609 target_ulong
helper_rdhwr_synci_step(CPUMIPSState
*env
)
2611 check_hwrena(env
, 1, GETPC());
2612 return env
->SYNCI_Step
;
2615 target_ulong
helper_rdhwr_cc(CPUMIPSState
*env
)
2618 check_hwrena(env
, 2, GETPC());
2619 #ifdef CONFIG_USER_ONLY
2620 count
= env
->CP0_Count
;
2622 qemu_mutex_lock_iothread();
2623 count
= (int32_t)cpu_mips_get_count(env
);
2624 qemu_mutex_unlock_iothread();
2629 target_ulong
helper_rdhwr_ccres(CPUMIPSState
*env
)
2631 check_hwrena(env
, 3, GETPC());
2635 target_ulong
helper_rdhwr_performance(CPUMIPSState
*env
)
2637 check_hwrena(env
, 4, GETPC());
2638 return env
->CP0_Performance0
;
2641 target_ulong
helper_rdhwr_xnp(CPUMIPSState
*env
)
2643 check_hwrena(env
, 5, GETPC());
2644 return (env
->CP0_Config5
>> CP0C5_XNP
) & 1;
2647 void helper_pmon(CPUMIPSState
*env
, int function
)
2651 case 2: /* TODO: char inbyte(int waitflag); */
2652 if (env
->active_tc
.gpr
[4] == 0)
2653 env
->active_tc
.gpr
[2] = -1;
2655 case 11: /* TODO: char inbyte (void); */
2656 env
->active_tc
.gpr
[2] = -1;
2660 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
2666 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
2673 void helper_wait(CPUMIPSState
*env
)
2675 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2678 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
2679 /* Last instruction in the block, PC was updated before
2680 - no need to recover PC and icount */
2681 raise_exception(env
, EXCP_HLT
);
2684 #if !defined(CONFIG_USER_ONLY)
2686 void mips_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
2687 MMUAccessType access_type
,
2688 int mmu_idx
, uintptr_t retaddr
)
2690 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2691 CPUMIPSState
*env
= &cpu
->env
;
2695 if (!(env
->hflags
& MIPS_HFLAG_DM
)) {
2696 env
->CP0_BadVAddr
= addr
;
2699 if (access_type
== MMU_DATA_STORE
) {
2703 if (access_type
== MMU_INST_FETCH
) {
2704 error_code
|= EXCP_INST_NOTAVAIL
;
2708 do_raise_exception_err(env
, excp
, error_code
, retaddr
);
2711 void tlb_fill(CPUState
*cs
, target_ulong addr
, int size
,
2712 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
2716 ret
= mips_cpu_handle_mmu_fault(cs
, addr
, size
, access_type
, mmu_idx
);
2718 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2719 CPUMIPSState
*env
= &cpu
->env
;
2721 do_raise_exception_err(env
, cs
->exception_index
,
2722 env
->error_code
, retaddr
);
2726 void mips_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2727 bool is_write
, bool is_exec
, int unused
,
2730 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2731 CPUMIPSState
*env
= &cpu
->env
;
2734 * Raising an exception with KVM enabled will crash because it won't be from
2735 * the main execution loop so the longjmp won't have a matching setjmp.
2736 * Until we can trigger a bus error exception through KVM lets just ignore
2739 if (kvm_enabled()) {
2744 raise_exception(env
, EXCP_IBE
);
2746 raise_exception(env
, EXCP_DBE
);
2749 #endif /* !CONFIG_USER_ONLY */
2751 /* Complex FPU operations which may need stack space. */
2753 #define FLOAT_TWO32 make_float32(1 << 30)
2754 #define FLOAT_TWO64 make_float64(1ULL << 62)
2756 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2757 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2759 /* convert MIPS rounding mode in FCR31 to IEEE library */
2760 unsigned int ieee_rm
[] = {
2761 float_round_nearest_even
,
2762 float_round_to_zero
,
2767 target_ulong
helper_cfc1(CPUMIPSState
*env
, uint32_t reg
)
2769 target_ulong arg1
= 0;
2773 arg1
= (int32_t)env
->active_fpu
.fcr0
;
2776 /* UFR Support - Read Status FR */
2777 if (env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) {
2778 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2780 ((env
->CP0_Status
& (1 << CP0St_FR
)) >> CP0St_FR
);
2782 do_raise_exception(env
, EXCP_RI
, GETPC());
2787 /* FRE Support - read Config5.FRE bit */
2788 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
2789 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2790 arg1
= (env
->CP0_Config5
>> CP0C5_FRE
) & 1;
2792 helper_raise_exception(env
, EXCP_RI
);
2797 arg1
= ((env
->active_fpu
.fcr31
>> 24) & 0xfe) | ((env
->active_fpu
.fcr31
>> 23) & 0x1);
2800 arg1
= env
->active_fpu
.fcr31
& 0x0003f07c;
2803 arg1
= (env
->active_fpu
.fcr31
& 0x00000f83) | ((env
->active_fpu
.fcr31
>> 22) & 0x4);
2806 arg1
= (int32_t)env
->active_fpu
.fcr31
;
2813 void helper_ctc1(CPUMIPSState
*env
, target_ulong arg1
, uint32_t fs
, uint32_t rt
)
2817 /* UFR Alias - Reset Status FR */
2818 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2821 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2822 env
->CP0_Status
&= ~(1 << CP0St_FR
);
2823 compute_hflags(env
);
2825 do_raise_exception(env
, EXCP_RI
, GETPC());
2829 /* UNFR Alias - Set Status FR */
2830 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2833 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2834 env
->CP0_Status
|= (1 << CP0St_FR
);
2835 compute_hflags(env
);
2837 do_raise_exception(env
, EXCP_RI
, GETPC());
2841 /* FRE Support - clear Config5.FRE bit */
2842 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2845 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2846 env
->CP0_Config5
&= ~(1 << CP0C5_FRE
);
2847 compute_hflags(env
);
2849 helper_raise_exception(env
, EXCP_RI
);
2853 /* FRE Support - set Config5.FRE bit */
2854 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2857 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2858 env
->CP0_Config5
|= (1 << CP0C5_FRE
);
2859 compute_hflags(env
);
2861 helper_raise_exception(env
, EXCP_RI
);
2865 if ((env
->insn_flags
& ISA_MIPS32R6
) || (arg1
& 0xffffff00)) {
2868 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0x017fffff) | ((arg1
& 0xfe) << 24) |
2869 ((arg1
& 0x1) << 23);
2872 if (arg1
& 0x007c0000)
2874 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfffc0f83) | (arg1
& 0x0003f07c);
2877 if (arg1
& 0x007c0000)
2879 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfefff07c) | (arg1
& 0x00000f83) |
2880 ((arg1
& 0x4) << 22);
2883 env
->active_fpu
.fcr31
= (arg1
& env
->active_fpu
.fcr31_rw_bitmask
) |
2884 (env
->active_fpu
.fcr31
& ~(env
->active_fpu
.fcr31_rw_bitmask
));
2887 if (env
->insn_flags
& ISA_MIPS32R6
) {
2888 do_raise_exception(env
, EXCP_RI
, GETPC());
2892 restore_fp_status(env
);
2893 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2894 if ((GET_FP_ENABLE(env
->active_fpu
.fcr31
) | 0x20) & GET_FP_CAUSE(env
->active_fpu
.fcr31
))
2895 do_raise_exception(env
, EXCP_FPE
, GETPC());
2898 int ieee_ex_to_mips(int xcpt
)
2902 if (xcpt
& float_flag_invalid
) {
2905 if (xcpt
& float_flag_overflow
) {
2908 if (xcpt
& float_flag_underflow
) {
2909 ret
|= FP_UNDERFLOW
;
2911 if (xcpt
& float_flag_divbyzero
) {
2914 if (xcpt
& float_flag_inexact
) {
2921 static inline void update_fcr31(CPUMIPSState
*env
, uintptr_t pc
)
2923 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->active_fpu
.fp_status
));
2925 SET_FP_CAUSE(env
->active_fpu
.fcr31
, tmp
);
2928 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2930 if (GET_FP_ENABLE(env
->active_fpu
.fcr31
) & tmp
) {
2931 do_raise_exception(env
, EXCP_FPE
, pc
);
2933 UPDATE_FP_FLAGS(env
->active_fpu
.fcr31
, tmp
);
2939 Single precition routines have a "s" suffix, double precision a
2940 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2941 paired single lower "pl", paired single upper "pu". */
2943 /* unary operations, modifying fp status */
2944 uint64_t helper_float_sqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2946 fdt0
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2947 update_fcr31(env
, GETPC());
2951 uint32_t helper_float_sqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
2953 fst0
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2954 update_fcr31(env
, GETPC());
2958 uint64_t helper_float_cvtd_s(CPUMIPSState
*env
, uint32_t fst0
)
2962 fdt2
= float32_to_float64(fst0
, &env
->active_fpu
.fp_status
);
2963 update_fcr31(env
, GETPC());
2967 uint64_t helper_float_cvtd_w(CPUMIPSState
*env
, uint32_t wt0
)
2971 fdt2
= int32_to_float64(wt0
, &env
->active_fpu
.fp_status
);
2972 update_fcr31(env
, GETPC());
2976 uint64_t helper_float_cvtd_l(CPUMIPSState
*env
, uint64_t dt0
)
2980 fdt2
= int64_to_float64(dt0
, &env
->active_fpu
.fp_status
);
2981 update_fcr31(env
, GETPC());
2985 uint64_t helper_float_cvt_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2989 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2990 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2991 & (float_flag_invalid
| float_flag_overflow
)) {
2992 dt2
= FP_TO_INT64_OVERFLOW
;
2994 update_fcr31(env
, GETPC());
2998 uint64_t helper_float_cvt_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3002 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3003 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3004 & (float_flag_invalid
| float_flag_overflow
)) {
3005 dt2
= FP_TO_INT64_OVERFLOW
;
3007 update_fcr31(env
, GETPC());
3011 uint64_t helper_float_cvtps_pw(CPUMIPSState
*env
, uint64_t dt0
)
3016 fst2
= int32_to_float32(dt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3017 fsth2
= int32_to_float32(dt0
>> 32, &env
->active_fpu
.fp_status
);
3018 update_fcr31(env
, GETPC());
3019 return ((uint64_t)fsth2
<< 32) | fst2
;
3022 uint64_t helper_float_cvtpw_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3028 wt2
= float32_to_int32(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3029 excp
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
3030 if (excp
& (float_flag_overflow
| float_flag_invalid
)) {
3031 wt2
= FP_TO_INT32_OVERFLOW
;
3034 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
3035 wth2
= float32_to_int32(fdt0
>> 32, &env
->active_fpu
.fp_status
);
3036 excph
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
3037 if (excph
& (float_flag_overflow
| float_flag_invalid
)) {
3038 wth2
= FP_TO_INT32_OVERFLOW
;
3041 set_float_exception_flags(excp
| excph
, &env
->active_fpu
.fp_status
);
3042 update_fcr31(env
, GETPC());
3044 return ((uint64_t)wth2
<< 32) | wt2
;
3047 uint32_t helper_float_cvts_d(CPUMIPSState
*env
, uint64_t fdt0
)
3051 fst2
= float64_to_float32(fdt0
, &env
->active_fpu
.fp_status
);
3052 update_fcr31(env
, GETPC());
3056 uint32_t helper_float_cvts_w(CPUMIPSState
*env
, uint32_t wt0
)
3060 fst2
= int32_to_float32(wt0
, &env
->active_fpu
.fp_status
);
3061 update_fcr31(env
, GETPC());
3065 uint32_t helper_float_cvts_l(CPUMIPSState
*env
, uint64_t dt0
)
3069 fst2
= int64_to_float32(dt0
, &env
->active_fpu
.fp_status
);
3070 update_fcr31(env
, GETPC());
3074 uint32_t helper_float_cvts_pl(CPUMIPSState
*env
, uint32_t wt0
)
3079 update_fcr31(env
, GETPC());
3083 uint32_t helper_float_cvts_pu(CPUMIPSState
*env
, uint32_t wth0
)
3088 update_fcr31(env
, GETPC());
3092 uint32_t helper_float_cvt_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3096 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3097 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3098 & (float_flag_invalid
| float_flag_overflow
)) {
3099 wt2
= FP_TO_INT32_OVERFLOW
;
3101 update_fcr31(env
, GETPC());
3105 uint32_t helper_float_cvt_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3109 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3110 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3111 & (float_flag_invalid
| float_flag_overflow
)) {
3112 wt2
= FP_TO_INT32_OVERFLOW
;
3114 update_fcr31(env
, GETPC());
3118 uint64_t helper_float_round_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3122 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
3123 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3124 restore_rounding_mode(env
);
3125 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3126 & (float_flag_invalid
| float_flag_overflow
)) {
3127 dt2
= FP_TO_INT64_OVERFLOW
;
3129 update_fcr31(env
, GETPC());
3133 uint64_t helper_float_round_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3137 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
3138 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3139 restore_rounding_mode(env
);
3140 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3141 & (float_flag_invalid
| float_flag_overflow
)) {
3142 dt2
= FP_TO_INT64_OVERFLOW
;
3144 update_fcr31(env
, GETPC());
3148 uint32_t helper_float_round_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3152 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
3153 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3154 restore_rounding_mode(env
);
3155 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3156 & (float_flag_invalid
| float_flag_overflow
)) {
3157 wt2
= FP_TO_INT32_OVERFLOW
;
3159 update_fcr31(env
, GETPC());
3163 uint32_t helper_float_round_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3167 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
3168 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3169 restore_rounding_mode(env
);
3170 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3171 & (float_flag_invalid
| float_flag_overflow
)) {
3172 wt2
= FP_TO_INT32_OVERFLOW
;
3174 update_fcr31(env
, GETPC());
3178 uint64_t helper_float_trunc_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3182 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3183 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3184 & (float_flag_invalid
| float_flag_overflow
)) {
3185 dt2
= FP_TO_INT64_OVERFLOW
;
3187 update_fcr31(env
, GETPC());
3191 uint64_t helper_float_trunc_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3195 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3196 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3197 & (float_flag_invalid
| float_flag_overflow
)) {
3198 dt2
= FP_TO_INT64_OVERFLOW
;
3200 update_fcr31(env
, GETPC());
3204 uint32_t helper_float_trunc_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3208 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3209 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3210 & (float_flag_invalid
| float_flag_overflow
)) {
3211 wt2
= FP_TO_INT32_OVERFLOW
;
3213 update_fcr31(env
, GETPC());
3217 uint32_t helper_float_trunc_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3221 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3222 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3223 & (float_flag_invalid
| float_flag_overflow
)) {
3224 wt2
= FP_TO_INT32_OVERFLOW
;
3226 update_fcr31(env
, GETPC());
3230 uint64_t helper_float_ceil_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3234 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3235 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3236 restore_rounding_mode(env
);
3237 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3238 & (float_flag_invalid
| float_flag_overflow
)) {
3239 dt2
= FP_TO_INT64_OVERFLOW
;
3241 update_fcr31(env
, GETPC());
3245 uint64_t helper_float_ceil_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3249 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3250 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3251 restore_rounding_mode(env
);
3252 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3253 & (float_flag_invalid
| float_flag_overflow
)) {
3254 dt2
= FP_TO_INT64_OVERFLOW
;
3256 update_fcr31(env
, GETPC());
3260 uint32_t helper_float_ceil_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3264 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3265 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3266 restore_rounding_mode(env
);
3267 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3268 & (float_flag_invalid
| float_flag_overflow
)) {
3269 wt2
= FP_TO_INT32_OVERFLOW
;
3271 update_fcr31(env
, GETPC());
3275 uint32_t helper_float_ceil_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3279 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3280 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3281 restore_rounding_mode(env
);
3282 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3283 & (float_flag_invalid
| float_flag_overflow
)) {
3284 wt2
= FP_TO_INT32_OVERFLOW
;
3286 update_fcr31(env
, GETPC());
3290 uint64_t helper_float_floor_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3294 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3295 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3296 restore_rounding_mode(env
);
3297 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3298 & (float_flag_invalid
| float_flag_overflow
)) {
3299 dt2
= FP_TO_INT64_OVERFLOW
;
3301 update_fcr31(env
, GETPC());
3305 uint64_t helper_float_floor_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3309 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3310 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3311 restore_rounding_mode(env
);
3312 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3313 & (float_flag_invalid
| float_flag_overflow
)) {
3314 dt2
= FP_TO_INT64_OVERFLOW
;
3316 update_fcr31(env
, GETPC());
3320 uint32_t helper_float_floor_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3324 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3325 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3326 restore_rounding_mode(env
);
3327 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3328 & (float_flag_invalid
| float_flag_overflow
)) {
3329 wt2
= FP_TO_INT32_OVERFLOW
;
3331 update_fcr31(env
, GETPC());
3335 uint32_t helper_float_floor_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3339 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3340 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3341 restore_rounding_mode(env
);
3342 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3343 & (float_flag_invalid
| float_flag_overflow
)) {
3344 wt2
= FP_TO_INT32_OVERFLOW
;
3346 update_fcr31(env
, GETPC());
3350 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3354 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3355 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3356 & float_flag_invalid
) {
3357 if (float64_is_any_nan(fdt0
)) {
3361 update_fcr31(env
, GETPC());
3365 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3369 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3370 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3371 & float_flag_invalid
) {
3372 if (float32_is_any_nan(fst0
)) {
3376 update_fcr31(env
, GETPC());
3380 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3384 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3385 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3386 & float_flag_invalid
) {
3387 if (float64_is_any_nan(fdt0
)) {
3391 update_fcr31(env
, GETPC());
3395 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3399 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3400 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3401 & float_flag_invalid
) {
3402 if (float32_is_any_nan(fst0
)) {
3406 update_fcr31(env
, GETPC());
3410 uint64_t helper_float_round_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3414 set_float_rounding_mode(float_round_nearest_even
,
3415 &env
->active_fpu
.fp_status
);
3416 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3417 restore_rounding_mode(env
);
3418 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3419 & float_flag_invalid
) {
3420 if (float64_is_any_nan(fdt0
)) {
3424 update_fcr31(env
, GETPC());
3428 uint64_t helper_float_round_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3432 set_float_rounding_mode(float_round_nearest_even
,
3433 &env
->active_fpu
.fp_status
);
3434 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3435 restore_rounding_mode(env
);
3436 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3437 & float_flag_invalid
) {
3438 if (float32_is_any_nan(fst0
)) {
3442 update_fcr31(env
, GETPC());
3446 uint32_t helper_float_round_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3450 set_float_rounding_mode(float_round_nearest_even
,
3451 &env
->active_fpu
.fp_status
);
3452 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3453 restore_rounding_mode(env
);
3454 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3455 & float_flag_invalid
) {
3456 if (float64_is_any_nan(fdt0
)) {
3460 update_fcr31(env
, GETPC());
3464 uint32_t helper_float_round_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3468 set_float_rounding_mode(float_round_nearest_even
,
3469 &env
->active_fpu
.fp_status
);
3470 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3471 restore_rounding_mode(env
);
3472 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3473 & float_flag_invalid
) {
3474 if (float32_is_any_nan(fst0
)) {
3478 update_fcr31(env
, GETPC());
3482 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3486 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3487 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3488 & float_flag_invalid
) {
3489 if (float64_is_any_nan(fdt0
)) {
3493 update_fcr31(env
, GETPC());
3497 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3501 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3502 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3503 & float_flag_invalid
) {
3504 if (float32_is_any_nan(fst0
)) {
3508 update_fcr31(env
, GETPC());
3512 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3516 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3517 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3518 & float_flag_invalid
) {
3519 if (float64_is_any_nan(fdt0
)) {
3523 update_fcr31(env
, GETPC());
3527 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3531 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3532 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3533 & float_flag_invalid
) {
3534 if (float32_is_any_nan(fst0
)) {
3538 update_fcr31(env
, GETPC());
3542 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3546 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3547 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3548 restore_rounding_mode(env
);
3549 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3550 & float_flag_invalid
) {
3551 if (float64_is_any_nan(fdt0
)) {
3555 update_fcr31(env
, GETPC());
3559 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3563 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3564 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3565 restore_rounding_mode(env
);
3566 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3567 & float_flag_invalid
) {
3568 if (float32_is_any_nan(fst0
)) {
3572 update_fcr31(env
, GETPC());
3576 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3580 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3581 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3582 restore_rounding_mode(env
);
3583 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3584 & float_flag_invalid
) {
3585 if (float64_is_any_nan(fdt0
)) {
3589 update_fcr31(env
, GETPC());
3593 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3597 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3598 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3599 restore_rounding_mode(env
);
3600 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3601 & float_flag_invalid
) {
3602 if (float32_is_any_nan(fst0
)) {
3606 update_fcr31(env
, GETPC());
3610 uint64_t helper_float_floor_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3614 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3615 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3616 restore_rounding_mode(env
);
3617 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3618 & float_flag_invalid
) {
3619 if (float64_is_any_nan(fdt0
)) {
3623 update_fcr31(env
, GETPC());
3627 uint64_t helper_float_floor_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3631 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3632 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3633 restore_rounding_mode(env
);
3634 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3635 & float_flag_invalid
) {
3636 if (float32_is_any_nan(fst0
)) {
3640 update_fcr31(env
, GETPC());
3644 uint32_t helper_float_floor_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3648 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3649 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3650 restore_rounding_mode(env
);
3651 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3652 & float_flag_invalid
) {
3653 if (float64_is_any_nan(fdt0
)) {
3657 update_fcr31(env
, GETPC());
3661 uint32_t helper_float_floor_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3665 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3666 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3667 restore_rounding_mode(env
);
3668 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3669 & float_flag_invalid
) {
3670 if (float32_is_any_nan(fst0
)) {
3674 update_fcr31(env
, GETPC());
3678 /* unary operations, not modifying fp status */
3679 #define FLOAT_UNOP(name) \
3680 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3682 return float64_ ## name(fdt0); \
3684 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3686 return float32_ ## name(fst0); \
3688 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3693 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3694 wth0 = float32_ ## name(fdt0 >> 32); \
3695 return ((uint64_t)wth0 << 32) | wt0; \
3701 /* MIPS specific unary operations */
3702 uint64_t helper_float_recip_d(CPUMIPSState
*env
, uint64_t fdt0
)
3706 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3707 update_fcr31(env
, GETPC());
3711 uint32_t helper_float_recip_s(CPUMIPSState
*env
, uint32_t fst0
)
3715 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3716 update_fcr31(env
, GETPC());
3720 uint64_t helper_float_rsqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
3724 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3725 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3726 update_fcr31(env
, GETPC());
3730 uint32_t helper_float_rsqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
3734 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3735 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3736 update_fcr31(env
, GETPC());
3740 uint64_t helper_float_recip1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3744 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3745 update_fcr31(env
, GETPC());
3749 uint32_t helper_float_recip1_s(CPUMIPSState
*env
, uint32_t fst0
)
3753 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3754 update_fcr31(env
, GETPC());
3758 uint64_t helper_float_recip1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3763 fst2
= float32_div(float32_one
, fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3764 fsth2
= float32_div(float32_one
, fdt0
>> 32, &env
->active_fpu
.fp_status
);
3765 update_fcr31(env
, GETPC());
3766 return ((uint64_t)fsth2
<< 32) | fst2
;
3769 uint64_t helper_float_rsqrt1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3773 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3774 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3775 update_fcr31(env
, GETPC());
3779 uint32_t helper_float_rsqrt1_s(CPUMIPSState
*env
, uint32_t fst0
)
3783 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3784 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3785 update_fcr31(env
, GETPC());
3789 uint64_t helper_float_rsqrt1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3794 fst2
= float32_sqrt(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3795 fsth2
= float32_sqrt(fdt0
>> 32, &env
->active_fpu
.fp_status
);
3796 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3797 fsth2
= float32_div(float32_one
, fsth2
, &env
->active_fpu
.fp_status
);
3798 update_fcr31(env
, GETPC());
3799 return ((uint64_t)fsth2
<< 32) | fst2
;
3802 #define FLOAT_RINT(name, bits) \
3803 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3804 uint ## bits ## _t fs) \
3806 uint ## bits ## _t fdret; \
3808 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3809 update_fcr31(env, GETPC()); \
3813 FLOAT_RINT(rint_s
, 32)
3814 FLOAT_RINT(rint_d
, 64)
3817 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3818 #define FLOAT_CLASS_QUIET_NAN 0x002
3819 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3820 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3821 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3822 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3823 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3824 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3825 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3826 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3828 #define FLOAT_CLASS(name, bits) \
3829 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3830 float_status *status) \
3832 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3833 return FLOAT_CLASS_SIGNALING_NAN; \
3834 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3835 return FLOAT_CLASS_QUIET_NAN; \
3836 } else if (float ## bits ## _is_neg(arg)) { \
3837 if (float ## bits ## _is_infinity(arg)) { \
3838 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3839 } else if (float ## bits ## _is_zero(arg)) { \
3840 return FLOAT_CLASS_NEGATIVE_ZERO; \
3841 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3842 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3844 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3847 if (float ## bits ## _is_infinity(arg)) { \
3848 return FLOAT_CLASS_POSITIVE_INFINITY; \
3849 } else if (float ## bits ## _is_zero(arg)) { \
3850 return FLOAT_CLASS_POSITIVE_ZERO; \
3851 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3852 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3854 return FLOAT_CLASS_POSITIVE_NORMAL; \
3859 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3860 uint ## bits ## _t arg) \
3862 return float_ ## name(arg, &env->active_fpu.fp_status); \
3865 FLOAT_CLASS(class_s
, 32)
3866 FLOAT_CLASS(class_d
, 64)
3869 /* binary operations */
3870 #define FLOAT_BINOP(name) \
3871 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3872 uint64_t fdt0, uint64_t fdt1) \
3876 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3877 update_fcr31(env, GETPC()); \
3881 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3882 uint32_t fst0, uint32_t fst1) \
3886 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3887 update_fcr31(env, GETPC()); \
3891 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3895 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3896 uint32_t fsth0 = fdt0 >> 32; \
3897 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3898 uint32_t fsth1 = fdt1 >> 32; \
3902 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3903 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3904 update_fcr31(env, GETPC()); \
3905 return ((uint64_t)wth2 << 32) | wt2; \
3914 /* MIPS specific binary operations */
3915 uint64_t helper_float_recip2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3917 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3918 fdt2
= float64_chs(float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
));
3919 update_fcr31(env
, GETPC());
3923 uint32_t helper_float_recip2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3925 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3926 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3927 update_fcr31(env
, GETPC());
3931 uint64_t helper_float_recip2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3933 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3934 uint32_t fsth0
= fdt0
>> 32;
3935 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3936 uint32_t fsth2
= fdt2
>> 32;
3938 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3939 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3940 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3941 fsth2
= float32_chs(float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
));
3942 update_fcr31(env
, GETPC());
3943 return ((uint64_t)fsth2
<< 32) | fst2
;
3946 uint64_t helper_float_rsqrt2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3948 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3949 fdt2
= float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
);
3950 fdt2
= float64_chs(float64_div(fdt2
, FLOAT_TWO64
, &env
->active_fpu
.fp_status
));
3951 update_fcr31(env
, GETPC());
3955 uint32_t helper_float_rsqrt2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3957 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3958 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3959 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3960 update_fcr31(env
, GETPC());
3964 uint64_t helper_float_rsqrt2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3966 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3967 uint32_t fsth0
= fdt0
>> 32;
3968 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3969 uint32_t fsth2
= fdt2
>> 32;
3971 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3972 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3973 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3974 fsth2
= float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
);
3975 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3976 fsth2
= float32_chs(float32_div(fsth2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3977 update_fcr31(env
, GETPC());
3978 return ((uint64_t)fsth2
<< 32) | fst2
;
3981 uint64_t helper_float_addr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3983 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3984 uint32_t fsth0
= fdt0
>> 32;
3985 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3986 uint32_t fsth1
= fdt1
>> 32;
3990 fst2
= float32_add (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3991 fsth2
= float32_add (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3992 update_fcr31(env
, GETPC());
3993 return ((uint64_t)fsth2
<< 32) | fst2
;
3996 uint64_t helper_float_mulr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3998 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3999 uint32_t fsth0
= fdt0
>> 32;
4000 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
4001 uint32_t fsth1
= fdt1
>> 32;
4005 fst2
= float32_mul (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
4006 fsth2
= float32_mul (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
4007 update_fcr31(env
, GETPC());
4008 return ((uint64_t)fsth2
<< 32) | fst2
;
4011 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
4012 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
4013 uint ## bits ## _t fs, \
4014 uint ## bits ## _t ft) \
4016 uint ## bits ## _t fdret; \
4018 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
4019 &env->active_fpu.fp_status); \
4020 update_fcr31(env, GETPC()); \
4024 FLOAT_MINMAX(max_s
, 32, maxnum
)
4025 FLOAT_MINMAX(max_d
, 64, maxnum
)
4026 FLOAT_MINMAX(maxa_s
, 32, maxnummag
)
4027 FLOAT_MINMAX(maxa_d
, 64, maxnummag
)
4029 FLOAT_MINMAX(min_s
, 32, minnum
)
4030 FLOAT_MINMAX(min_d
, 64, minnum
)
4031 FLOAT_MINMAX(mina_s
, 32, minnummag
)
4032 FLOAT_MINMAX(mina_d
, 64, minnummag
)
4035 /* ternary operations */
4036 #define UNFUSED_FMA(prefix, a, b, c, flags) \
4038 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
4039 if ((flags) & float_muladd_negate_c) { \
4040 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
4042 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
4044 if ((flags) & float_muladd_negate_result) { \
4045 a = prefix##_chs(a); \
4049 /* FMA based operations */
4050 #define FLOAT_FMA(name, type) \
4051 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
4052 uint64_t fdt0, uint64_t fdt1, \
4055 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
4056 update_fcr31(env, GETPC()); \
4060 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
4061 uint32_t fst0, uint32_t fst1, \
4064 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4065 update_fcr31(env, GETPC()); \
4069 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
4070 uint64_t fdt0, uint64_t fdt1, \
4073 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
4074 uint32_t fsth0 = fdt0 >> 32; \
4075 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
4076 uint32_t fsth1 = fdt1 >> 32; \
4077 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
4078 uint32_t fsth2 = fdt2 >> 32; \
4080 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4081 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
4082 update_fcr31(env, GETPC()); \
4083 return ((uint64_t)fsth0 << 32) | fst0; \
4086 FLOAT_FMA(msub
, float_muladd_negate_c
)
4087 FLOAT_FMA(nmadd
, float_muladd_negate_result
)
4088 FLOAT_FMA(nmsub
, float_muladd_negate_result
| float_muladd_negate_c
)
4091 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
4092 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
4093 uint ## bits ## _t fs, \
4094 uint ## bits ## _t ft, \
4095 uint ## bits ## _t fd) \
4097 uint ## bits ## _t fdret; \
4099 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
4100 &env->active_fpu.fp_status); \
4101 update_fcr31(env, GETPC()); \
4105 FLOAT_FMADDSUB(maddf_s
, 32, 0)
4106 FLOAT_FMADDSUB(maddf_d
, 64, 0)
4107 FLOAT_FMADDSUB(msubf_s
, 32, float_muladd_negate_product
)
4108 FLOAT_FMADDSUB(msubf_d
, 64, float_muladd_negate_product
)
4109 #undef FLOAT_FMADDSUB
4111 /* compare operations */
4112 #define FOP_COND_D(op, cond) \
4113 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4114 uint64_t fdt1, int cc) \
4118 update_fcr31(env, GETPC()); \
4120 SET_FP_COND(cc, env->active_fpu); \
4122 CLEAR_FP_COND(cc, env->active_fpu); \
4124 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4125 uint64_t fdt1, int cc) \
4128 fdt0 = float64_abs(fdt0); \
4129 fdt1 = float64_abs(fdt1); \
4131 update_fcr31(env, GETPC()); \
4133 SET_FP_COND(cc, env->active_fpu); \
4135 CLEAR_FP_COND(cc, env->active_fpu); \
4138 /* NOTE: the comma operator will make "cond" to eval to false,
4139 * but float64_unordered_quiet() is still called. */
4140 FOP_COND_D(f
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4141 FOP_COND_D(un
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
4142 FOP_COND_D(eq
, float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4143 FOP_COND_D(ueq
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4144 FOP_COND_D(olt
, float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4145 FOP_COND_D(ult
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4146 FOP_COND_D(ole
, float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4147 FOP_COND_D(ule
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4148 /* NOTE: the comma operator will make "cond" to eval to false,
4149 * but float64_unordered() is still called. */
4150 FOP_COND_D(sf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4151 FOP_COND_D(ngle
,float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
4152 FOP_COND_D(seq
, float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4153 FOP_COND_D(ngl
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4154 FOP_COND_D(lt
, float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4155 FOP_COND_D(nge
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4156 FOP_COND_D(le
, float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4157 FOP_COND_D(ngt
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
4159 #define FOP_COND_S(op, cond) \
4160 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4161 uint32_t fst1, int cc) \
4165 update_fcr31(env, GETPC()); \
4167 SET_FP_COND(cc, env->active_fpu); \
4169 CLEAR_FP_COND(cc, env->active_fpu); \
4171 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4172 uint32_t fst1, int cc) \
4175 fst0 = float32_abs(fst0); \
4176 fst1 = float32_abs(fst1); \
4178 update_fcr31(env, GETPC()); \
4180 SET_FP_COND(cc, env->active_fpu); \
4182 CLEAR_FP_COND(cc, env->active_fpu); \
4185 /* NOTE: the comma operator will make "cond" to eval to false,
4186 * but float32_unordered_quiet() is still called. */
4187 FOP_COND_S(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4188 FOP_COND_S(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
))
4189 FOP_COND_S(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4190 FOP_COND_S(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4191 FOP_COND_S(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4192 FOP_COND_S(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4193 FOP_COND_S(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4194 FOP_COND_S(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4195 /* NOTE: the comma operator will make "cond" to eval to false,
4196 * but float32_unordered() is still called. */
4197 FOP_COND_S(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4198 FOP_COND_S(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
))
4199 FOP_COND_S(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4200 FOP_COND_S(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4201 FOP_COND_S(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4202 FOP_COND_S(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4203 FOP_COND_S(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4204 FOP_COND_S(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
4206 #define FOP_COND_PS(op, condl, condh) \
4207 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4208 uint64_t fdt1, int cc) \
4210 uint32_t fst0, fsth0, fst1, fsth1; \
4212 fst0 = fdt0 & 0XFFFFFFFF; \
4213 fsth0 = fdt0 >> 32; \
4214 fst1 = fdt1 & 0XFFFFFFFF; \
4215 fsth1 = fdt1 >> 32; \
4218 update_fcr31(env, GETPC()); \
4220 SET_FP_COND(cc, env->active_fpu); \
4222 CLEAR_FP_COND(cc, env->active_fpu); \
4224 SET_FP_COND(cc + 1, env->active_fpu); \
4226 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4228 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4229 uint64_t fdt1, int cc) \
4231 uint32_t fst0, fsth0, fst1, fsth1; \
4233 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
4234 fsth0 = float32_abs(fdt0 >> 32); \
4235 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
4236 fsth1 = float32_abs(fdt1 >> 32); \
4239 update_fcr31(env, GETPC()); \
4241 SET_FP_COND(cc, env->active_fpu); \
4243 CLEAR_FP_COND(cc, env->active_fpu); \
4245 SET_FP_COND(cc + 1, env->active_fpu); \
4247 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4250 /* NOTE: the comma operator will make "cond" to eval to false,
4251 * but float32_unordered_quiet() is still called. */
4252 FOP_COND_PS(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
4253 (float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
4254 FOP_COND_PS(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
),
4255 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
4256 FOP_COND_PS(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4257 float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4258 FOP_COND_PS(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4259 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4260 FOP_COND_PS(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4261 float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4262 FOP_COND_PS(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4263 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4264 FOP_COND_PS(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4265 float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4266 FOP_COND_PS(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4267 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4268 /* NOTE: the comma operator will make "cond" to eval to false,
4269 * but float32_unordered() is still called. */
4270 FOP_COND_PS(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
4271 (float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
4272 FOP_COND_PS(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
),
4273 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
4274 FOP_COND_PS(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4275 float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4276 FOP_COND_PS(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4277 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4278 FOP_COND_PS(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4279 float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4280 FOP_COND_PS(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4281 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4282 FOP_COND_PS(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4283 float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4284 FOP_COND_PS(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
4285 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
4287 /* R6 compare operations */
4288 #define FOP_CONDN_D(op, cond) \
4289 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
4294 update_fcr31(env, GETPC()); \
4302 /* NOTE: the comma operator will make "cond" to eval to false,
4303 * but float64_unordered_quiet() is still called. */
4304 FOP_CONDN_D(af
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4305 FOP_CONDN_D(un
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
4306 FOP_CONDN_D(eq
, (float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4307 FOP_CONDN_D(ueq
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4308 || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4309 FOP_CONDN_D(lt
, (float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4310 FOP_CONDN_D(ult
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4311 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4312 FOP_CONDN_D(le
, (float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4313 FOP_CONDN_D(ule
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4314 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4315 /* NOTE: the comma operator will make "cond" to eval to false,
4316 * but float64_unordered() is still called. */
4317 FOP_CONDN_D(saf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4318 FOP_CONDN_D(sun
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
4319 FOP_CONDN_D(seq
, (float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4320 FOP_CONDN_D(sueq
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4321 || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4322 FOP_CONDN_D(slt
, (float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4323 FOP_CONDN_D(sult
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4324 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4325 FOP_CONDN_D(sle
, (float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4326 FOP_CONDN_D(sule
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4327 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4328 FOP_CONDN_D(or, (float64_le_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4329 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4330 FOP_CONDN_D(une
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4331 || float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4332 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4333 FOP_CONDN_D(ne
, (float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4334 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4335 FOP_CONDN_D(sor
, (float64_le(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4336 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4337 FOP_CONDN_D(sune
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4338 || float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4339 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4340 FOP_CONDN_D(sne
, (float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4341 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4343 #define FOP_CONDN_S(op, cond) \
4344 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4349 update_fcr31(env, GETPC()); \
4357 /* NOTE: the comma operator will make "cond" to eval to false,
4358 * but float32_unordered_quiet() is still called. */
4359 FOP_CONDN_S(af
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4360 FOP_CONDN_S(un
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
4361 FOP_CONDN_S(eq
, (float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4362 FOP_CONDN_S(ueq
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4363 || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4364 FOP_CONDN_S(lt
, (float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4365 FOP_CONDN_S(ult
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4366 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4367 FOP_CONDN_S(le
, (float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4368 FOP_CONDN_S(ule
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4369 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4370 /* NOTE: the comma operator will make "cond" to eval to false,
4371 * but float32_unordered() is still called. */
4372 FOP_CONDN_S(saf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4373 FOP_CONDN_S(sun
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
4374 FOP_CONDN_S(seq
, (float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4375 FOP_CONDN_S(sueq
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4376 || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4377 FOP_CONDN_S(slt
, (float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4378 FOP_CONDN_S(sult
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4379 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4380 FOP_CONDN_S(sle
, (float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4381 FOP_CONDN_S(sule
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4382 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4383 FOP_CONDN_S(or, (float32_le_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4384 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4385 FOP_CONDN_S(une
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4386 || float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4387 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4388 FOP_CONDN_S(ne
, (float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4389 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4390 FOP_CONDN_S(sor
, (float32_le(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4391 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4392 FOP_CONDN_S(sune
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4393 || float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4394 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4395 FOP_CONDN_S(sne
, (float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4396 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4399 /* Data format min and max values */
4400 #define DF_BITS(df) (1 << ((df) + 3))
4402 /* Element-by-element access macros */
4403 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4405 #if !defined(CONFIG_USER_ONLY)
4406 #define MEMOP_IDX(DF) \
4407 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4408 cpu_mmu_index(env, false));
4410 #define MEMOP_IDX(DF)
4413 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
4414 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4415 target_ulong addr) \
4417 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4421 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4422 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
4424 memcpy(pwd, &wx, sizeof(wr_t)); \
4427 #if !defined(CONFIG_USER_ONLY)
4428 MSA_LD_DF(DF_BYTE
, b
, helper_ret_ldub_mmu
, oi
, GETPC())
4429 MSA_LD_DF(DF_HALF
, h
, helper_ret_lduw_mmu
, oi
, GETPC())
4430 MSA_LD_DF(DF_WORD
, w
, helper_ret_ldul_mmu
, oi
, GETPC())
4431 MSA_LD_DF(DF_DOUBLE
, d
, helper_ret_ldq_mmu
, oi
, GETPC())
4433 MSA_LD_DF(DF_BYTE
, b
, cpu_ldub_data
)
4434 MSA_LD_DF(DF_HALF
, h
, cpu_lduw_data
)
4435 MSA_LD_DF(DF_WORD
, w
, cpu_ldl_data
)
4436 MSA_LD_DF(DF_DOUBLE
, d
, cpu_ldq_data
)
4439 #define MSA_PAGESPAN(x) \
4440 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4442 static inline void ensure_writable_pages(CPUMIPSState
*env
,
4447 #if !defined(CONFIG_USER_ONLY)
4448 target_ulong page_addr
;
4449 if (unlikely(MSA_PAGESPAN(addr
))) {
4451 probe_write(env
, addr
, 0, mmu_idx
, retaddr
);
4453 page_addr
= (addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
4454 probe_write(env
, page_addr
, 0, mmu_idx
, retaddr
);
4459 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
4460 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4461 target_ulong addr) \
4463 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4464 int mmu_idx = cpu_mmu_index(env, false); \
4467 ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
4468 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4469 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
4473 #if !defined(CONFIG_USER_ONLY)
4474 MSA_ST_DF(DF_BYTE
, b
, helper_ret_stb_mmu
, oi
, GETPC())
4475 MSA_ST_DF(DF_HALF
, h
, helper_ret_stw_mmu
, oi
, GETPC())
4476 MSA_ST_DF(DF_WORD
, w
, helper_ret_stl_mmu
, oi
, GETPC())
4477 MSA_ST_DF(DF_DOUBLE
, d
, helper_ret_stq_mmu
, oi
, GETPC())
4479 MSA_ST_DF(DF_BYTE
, b
, cpu_stb_data
)
4480 MSA_ST_DF(DF_HALF
, h
, cpu_stw_data
)
4481 MSA_ST_DF(DF_WORD
, w
, cpu_stl_data
)
4482 MSA_ST_DF(DF_DOUBLE
, d
, cpu_stq_data
)
4485 void helper_cache(CPUMIPSState
*env
, target_ulong addr
, uint32_t op
)
4487 #ifndef CONFIG_USER_ONLY
4488 target_ulong index
= addr
& 0x1fffffff;
4490 /* Index Store Tag */
4491 memory_region_dispatch_write(env
->itc_tag
, index
, env
->CP0_TagLo
,
4492 8, MEMTXATTRS_UNSPECIFIED
);
4493 } else if (op
== 5) {
4494 /* Index Load Tag */
4495 memory_region_dispatch_read(env
->itc_tag
, index
, &env
->CP0_TagLo
,
4496 8, MEMTXATTRS_UNSPECIFIED
);