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target/mips: Extract break code into env->error_code
[mirror_qemu.git] / target / mips / tcg / translate.c
1 /*
2 * MIPS emulation for QEMU - main translation routines
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
9 * Copyright (c) 2020 Philippe Mathieu-Daudé
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2.1 of the License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "qemu/osdep.h"
26 #include "cpu.h"
27 #include "internal.h"
28 #include "tcg/tcg-op.h"
29 #include "exec/translator.h"
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32 #include "semihosting/semihost.h"
33
34 #include "trace.h"
35 #include "exec/translator.h"
36 #include "exec/log.h"
37 #include "qemu/qemu-print.h"
38 #include "fpu_helper.h"
39 #include "translate.h"
40
41 /*
42 * Many sysemu-only helpers are not reachable for user-only.
43 * Define stub generators here, so that we need not either sprinkle
44 * ifdefs through the translator, nor provide the helper function.
45 */
46 #define STUB_HELPER(NAME, ...) \
47 static inline void gen_helper_##NAME(__VA_ARGS__) \
48 { g_assert_not_reached(); }
49
50 #ifdef CONFIG_USER_ONLY
51 STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg)
52 #endif
53
54 enum {
55 /* indirect opcode tables */
56 OPC_SPECIAL = (0x00 << 26),
57 OPC_REGIMM = (0x01 << 26),
58 OPC_CP0 = (0x10 << 26),
59 OPC_CP2 = (0x12 << 26),
60 OPC_CP3 = (0x13 << 26),
61 OPC_SPECIAL2 = (0x1C << 26),
62 OPC_SPECIAL3 = (0x1F << 26),
63 /* arithmetic with immediate */
64 OPC_ADDI = (0x08 << 26),
65 OPC_ADDIU = (0x09 << 26),
66 OPC_SLTI = (0x0A << 26),
67 OPC_SLTIU = (0x0B << 26),
68 /* logic with immediate */
69 OPC_ANDI = (0x0C << 26),
70 OPC_ORI = (0x0D << 26),
71 OPC_XORI = (0x0E << 26),
72 OPC_LUI = (0x0F << 26),
73 /* arithmetic with immediate */
74 OPC_DADDI = (0x18 << 26),
75 OPC_DADDIU = (0x19 << 26),
76 /* Jump and branches */
77 OPC_J = (0x02 << 26),
78 OPC_JAL = (0x03 << 26),
79 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
80 OPC_BEQL = (0x14 << 26),
81 OPC_BNE = (0x05 << 26),
82 OPC_BNEL = (0x15 << 26),
83 OPC_BLEZ = (0x06 << 26),
84 OPC_BLEZL = (0x16 << 26),
85 OPC_BGTZ = (0x07 << 26),
86 OPC_BGTZL = (0x17 << 26),
87 OPC_JALX = (0x1D << 26),
88 OPC_DAUI = (0x1D << 26),
89 /* Load and stores */
90 OPC_LDL = (0x1A << 26),
91 OPC_LDR = (0x1B << 26),
92 OPC_LB = (0x20 << 26),
93 OPC_LH = (0x21 << 26),
94 OPC_LWL = (0x22 << 26),
95 OPC_LW = (0x23 << 26),
96 OPC_LWPC = OPC_LW | 0x5,
97 OPC_LBU = (0x24 << 26),
98 OPC_LHU = (0x25 << 26),
99 OPC_LWR = (0x26 << 26),
100 OPC_LWU = (0x27 << 26),
101 OPC_SB = (0x28 << 26),
102 OPC_SH = (0x29 << 26),
103 OPC_SWL = (0x2A << 26),
104 OPC_SW = (0x2B << 26),
105 OPC_SDL = (0x2C << 26),
106 OPC_SDR = (0x2D << 26),
107 OPC_SWR = (0x2E << 26),
108 OPC_LL = (0x30 << 26),
109 OPC_LLD = (0x34 << 26),
110 OPC_LD = (0x37 << 26),
111 OPC_LDPC = OPC_LD | 0x5,
112 OPC_SC = (0x38 << 26),
113 OPC_SCD = (0x3C << 26),
114 OPC_SD = (0x3F << 26),
115 /* Floating point load/store */
116 OPC_LWC1 = (0x31 << 26),
117 OPC_LWC2 = (0x32 << 26),
118 OPC_LDC1 = (0x35 << 26),
119 OPC_LDC2 = (0x36 << 26),
120 OPC_SWC1 = (0x39 << 26),
121 OPC_SWC2 = (0x3A << 26),
122 OPC_SDC1 = (0x3D << 26),
123 OPC_SDC2 = (0x3E << 26),
124 /* Compact Branches */
125 OPC_BLEZALC = (0x06 << 26),
126 OPC_BGEZALC = (0x06 << 26),
127 OPC_BGEUC = (0x06 << 26),
128 OPC_BGTZALC = (0x07 << 26),
129 OPC_BLTZALC = (0x07 << 26),
130 OPC_BLTUC = (0x07 << 26),
131 OPC_BOVC = (0x08 << 26),
132 OPC_BEQZALC = (0x08 << 26),
133 OPC_BEQC = (0x08 << 26),
134 OPC_BLEZC = (0x16 << 26),
135 OPC_BGEZC = (0x16 << 26),
136 OPC_BGEC = (0x16 << 26),
137 OPC_BGTZC = (0x17 << 26),
138 OPC_BLTZC = (0x17 << 26),
139 OPC_BLTC = (0x17 << 26),
140 OPC_BNVC = (0x18 << 26),
141 OPC_BNEZALC = (0x18 << 26),
142 OPC_BNEC = (0x18 << 26),
143 OPC_BC = (0x32 << 26),
144 OPC_BEQZC = (0x36 << 26),
145 OPC_JIC = (0x36 << 26),
146 OPC_BALC = (0x3A << 26),
147 OPC_BNEZC = (0x3E << 26),
148 OPC_JIALC = (0x3E << 26),
149 /* MDMX ASE specific */
150 OPC_MDMX = (0x1E << 26),
151 /* Cache and prefetch */
152 OPC_CACHE = (0x2F << 26),
153 OPC_PREF = (0x33 << 26),
154 /* PC-relative address computation / loads */
155 OPC_PCREL = (0x3B << 26),
156 };
157
158 /* PC-relative address computation / loads */
159 #define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19)))
160 #define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16)))
161 enum {
162 /* Instructions determined by bits 19 and 20 */
163 OPC_ADDIUPC = OPC_PCREL | (0 << 19),
164 R6_OPC_LWPC = OPC_PCREL | (1 << 19),
165 OPC_LWUPC = OPC_PCREL | (2 << 19),
166
167 /* Instructions determined by bits 16 ... 20 */
168 OPC_AUIPC = OPC_PCREL | (0x1e << 16),
169 OPC_ALUIPC = OPC_PCREL | (0x1f << 16),
170
171 /* Other */
172 R6_OPC_LDPC = OPC_PCREL | (6 << 18),
173 };
174
175 /* MIPS special opcodes */
176 #define MASK_SPECIAL(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
177
178 enum {
179 /* Shifts */
180 OPC_SLL = 0x00 | OPC_SPECIAL,
181 /* NOP is SLL r0, r0, 0 */
182 /* SSNOP is SLL r0, r0, 1 */
183 /* EHB is SLL r0, r0, 3 */
184 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
185 OPC_ROTR = OPC_SRL | (1 << 21),
186 OPC_SRA = 0x03 | OPC_SPECIAL,
187 OPC_SLLV = 0x04 | OPC_SPECIAL,
188 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */
189 OPC_ROTRV = OPC_SRLV | (1 << 6),
190 OPC_SRAV = 0x07 | OPC_SPECIAL,
191 OPC_DSLLV = 0x14 | OPC_SPECIAL,
192 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
193 OPC_DROTRV = OPC_DSRLV | (1 << 6),
194 OPC_DSRAV = 0x17 | OPC_SPECIAL,
195 OPC_DSLL = 0x38 | OPC_SPECIAL,
196 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
197 OPC_DROTR = OPC_DSRL | (1 << 21),
198 OPC_DSRA = 0x3B | OPC_SPECIAL,
199 OPC_DSLL32 = 0x3C | OPC_SPECIAL,
200 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */
201 OPC_DROTR32 = OPC_DSRL32 | (1 << 21),
202 OPC_DSRA32 = 0x3F | OPC_SPECIAL,
203 /* Multiplication / division */
204 OPC_MULT = 0x18 | OPC_SPECIAL,
205 OPC_MULTU = 0x19 | OPC_SPECIAL,
206 OPC_DIV = 0x1A | OPC_SPECIAL,
207 OPC_DIVU = 0x1B | OPC_SPECIAL,
208 OPC_DMULT = 0x1C | OPC_SPECIAL,
209 OPC_DMULTU = 0x1D | OPC_SPECIAL,
210 OPC_DDIV = 0x1E | OPC_SPECIAL,
211 OPC_DDIVU = 0x1F | OPC_SPECIAL,
212
213 /* 2 registers arithmetic / logic */
214 OPC_ADD = 0x20 | OPC_SPECIAL,
215 OPC_ADDU = 0x21 | OPC_SPECIAL,
216 OPC_SUB = 0x22 | OPC_SPECIAL,
217 OPC_SUBU = 0x23 | OPC_SPECIAL,
218 OPC_AND = 0x24 | OPC_SPECIAL,
219 OPC_OR = 0x25 | OPC_SPECIAL,
220 OPC_XOR = 0x26 | OPC_SPECIAL,
221 OPC_NOR = 0x27 | OPC_SPECIAL,
222 OPC_SLT = 0x2A | OPC_SPECIAL,
223 OPC_SLTU = 0x2B | OPC_SPECIAL,
224 OPC_DADD = 0x2C | OPC_SPECIAL,
225 OPC_DADDU = 0x2D | OPC_SPECIAL,
226 OPC_DSUB = 0x2E | OPC_SPECIAL,
227 OPC_DSUBU = 0x2F | OPC_SPECIAL,
228 /* Jumps */
229 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */
230 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
231 /* Traps */
232 OPC_TGE = 0x30 | OPC_SPECIAL,
233 OPC_TGEU = 0x31 | OPC_SPECIAL,
234 OPC_TLT = 0x32 | OPC_SPECIAL,
235 OPC_TLTU = 0x33 | OPC_SPECIAL,
236 OPC_TEQ = 0x34 | OPC_SPECIAL,
237 OPC_TNE = 0x36 | OPC_SPECIAL,
238 /* HI / LO registers load & stores */
239 OPC_MFHI = 0x10 | OPC_SPECIAL,
240 OPC_MTHI = 0x11 | OPC_SPECIAL,
241 OPC_MFLO = 0x12 | OPC_SPECIAL,
242 OPC_MTLO = 0x13 | OPC_SPECIAL,
243 /* Conditional moves */
244 OPC_MOVZ = 0x0A | OPC_SPECIAL,
245 OPC_MOVN = 0x0B | OPC_SPECIAL,
246
247 OPC_SELEQZ = 0x35 | OPC_SPECIAL,
248 OPC_SELNEZ = 0x37 | OPC_SPECIAL,
249
250 OPC_MOVCI = 0x01 | OPC_SPECIAL,
251
252 /* Special */
253 OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */
254 OPC_SYSCALL = 0x0C | OPC_SPECIAL,
255 OPC_BREAK = 0x0D | OPC_SPECIAL,
256 OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */
257 OPC_SYNC = 0x0F | OPC_SPECIAL,
258
259 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
260 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
261 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
262 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
263 };
264
265 /*
266 * R6 Multiply and Divide instructions have the same opcode
267 * and function field as legacy OPC_MULT[U]/OPC_DIV[U]
268 */
269 #define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff)))
270
271 enum {
272 R6_OPC_MUL = OPC_MULT | (2 << 6),
273 R6_OPC_MUH = OPC_MULT | (3 << 6),
274 R6_OPC_MULU = OPC_MULTU | (2 << 6),
275 R6_OPC_MUHU = OPC_MULTU | (3 << 6),
276 R6_OPC_DIV = OPC_DIV | (2 << 6),
277 R6_OPC_MOD = OPC_DIV | (3 << 6),
278 R6_OPC_DIVU = OPC_DIVU | (2 << 6),
279 R6_OPC_MODU = OPC_DIVU | (3 << 6),
280
281 R6_OPC_DMUL = OPC_DMULT | (2 << 6),
282 R6_OPC_DMUH = OPC_DMULT | (3 << 6),
283 R6_OPC_DMULU = OPC_DMULTU | (2 << 6),
284 R6_OPC_DMUHU = OPC_DMULTU | (3 << 6),
285 R6_OPC_DDIV = OPC_DDIV | (2 << 6),
286 R6_OPC_DMOD = OPC_DDIV | (3 << 6),
287 R6_OPC_DDIVU = OPC_DDIVU | (2 << 6),
288 R6_OPC_DMODU = OPC_DDIVU | (3 << 6),
289
290 R6_OPC_CLZ = 0x10 | OPC_SPECIAL,
291 R6_OPC_CLO = 0x11 | OPC_SPECIAL,
292 R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
293 R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
294 R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
295 };
296
297 /* REGIMM (rt field) opcodes */
298 #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16)))
299
300 enum {
301 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
302 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM,
303 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM,
304 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM,
305 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM,
306 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM,
307 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM,
308 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM,
309 OPC_TGEI = (0x08 << 16) | OPC_REGIMM,
310 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM,
311 OPC_TLTI = (0x0A << 16) | OPC_REGIMM,
312 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
313 OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
314 OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
315 OPC_SIGRIE = (0x17 << 16) | OPC_REGIMM,
316 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
317
318 OPC_DAHI = (0x06 << 16) | OPC_REGIMM,
319 OPC_DATI = (0x1e << 16) | OPC_REGIMM,
320 };
321
322 /* Special2 opcodes */
323 #define MASK_SPECIAL2(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
324
325 enum {
326 /* Multiply & xxx operations */
327 OPC_MADD = 0x00 | OPC_SPECIAL2,
328 OPC_MADDU = 0x01 | OPC_SPECIAL2,
329 OPC_MUL = 0x02 | OPC_SPECIAL2,
330 OPC_MSUB = 0x04 | OPC_SPECIAL2,
331 OPC_MSUBU = 0x05 | OPC_SPECIAL2,
332 /* Loongson 2F */
333 OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2,
334 OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
335 OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
336 OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
337 OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2,
338 OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2,
339 OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
340 OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
341 OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
342 OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2,
343 OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
344 OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2,
345 /* Misc */
346 OPC_CLZ = 0x20 | OPC_SPECIAL2,
347 OPC_CLO = 0x21 | OPC_SPECIAL2,
348 OPC_DCLZ = 0x24 | OPC_SPECIAL2,
349 OPC_DCLO = 0x25 | OPC_SPECIAL2,
350 /* Special */
351 OPC_SDBBP = 0x3F | OPC_SPECIAL2,
352 };
353
354 /* Special3 opcodes */
355 #define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
356
357 enum {
358 OPC_EXT = 0x00 | OPC_SPECIAL3,
359 OPC_DEXTM = 0x01 | OPC_SPECIAL3,
360 OPC_DEXTU = 0x02 | OPC_SPECIAL3,
361 OPC_DEXT = 0x03 | OPC_SPECIAL3,
362 OPC_INS = 0x04 | OPC_SPECIAL3,
363 OPC_DINSM = 0x05 | OPC_SPECIAL3,
364 OPC_DINSU = 0x06 | OPC_SPECIAL3,
365 OPC_DINS = 0x07 | OPC_SPECIAL3,
366 OPC_FORK = 0x08 | OPC_SPECIAL3,
367 OPC_YIELD = 0x09 | OPC_SPECIAL3,
368 OPC_BSHFL = 0x20 | OPC_SPECIAL3,
369 OPC_DBSHFL = 0x24 | OPC_SPECIAL3,
370 OPC_RDHWR = 0x3B | OPC_SPECIAL3,
371 OPC_GINV = 0x3D | OPC_SPECIAL3,
372
373 /* Loongson 2E */
374 OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3,
375 OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
376 OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3,
377 OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
378 OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
379 OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
380 OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3,
381 OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3,
382 OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
383 OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
384 OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
385 OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3,
386
387 /* MIPS DSP Load */
388 OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
389 /* MIPS DSP Arithmetic */
390 OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3,
391 OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3,
392 OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3,
393 OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3,
394 /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
395 /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
396 OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
397 OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3,
398 /* MIPS DSP GPR-Based Shift Sub-class */
399 OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3,
400 OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3,
401 /* MIPS DSP Multiply Sub-class insns */
402 /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */
403 /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */
404 OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3,
405 OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3,
406 /* DSP Bit/Manipulation Sub-class */
407 OPC_INSV_DSP = 0x0C | OPC_SPECIAL3,
408 OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3,
409 /* MIPS DSP Append Sub-class */
410 OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3,
411 OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3,
412 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
413 OPC_EXTR_W_DSP = 0x38 | OPC_SPECIAL3,
414 OPC_DEXTR_W_DSP = 0x3C | OPC_SPECIAL3,
415
416 /* EVA */
417 OPC_LWLE = 0x19 | OPC_SPECIAL3,
418 OPC_LWRE = 0x1A | OPC_SPECIAL3,
419 OPC_CACHEE = 0x1B | OPC_SPECIAL3,
420 OPC_SBE = 0x1C | OPC_SPECIAL3,
421 OPC_SHE = 0x1D | OPC_SPECIAL3,
422 OPC_SCE = 0x1E | OPC_SPECIAL3,
423 OPC_SWE = 0x1F | OPC_SPECIAL3,
424 OPC_SWLE = 0x21 | OPC_SPECIAL3,
425 OPC_SWRE = 0x22 | OPC_SPECIAL3,
426 OPC_PREFE = 0x23 | OPC_SPECIAL3,
427 OPC_LBUE = 0x28 | OPC_SPECIAL3,
428 OPC_LHUE = 0x29 | OPC_SPECIAL3,
429 OPC_LBE = 0x2C | OPC_SPECIAL3,
430 OPC_LHE = 0x2D | OPC_SPECIAL3,
431 OPC_LLE = 0x2E | OPC_SPECIAL3,
432 OPC_LWE = 0x2F | OPC_SPECIAL3,
433
434 /* R6 */
435 R6_OPC_PREF = 0x35 | OPC_SPECIAL3,
436 R6_OPC_CACHE = 0x25 | OPC_SPECIAL3,
437 R6_OPC_LL = 0x36 | OPC_SPECIAL3,
438 R6_OPC_SC = 0x26 | OPC_SPECIAL3,
439 R6_OPC_LLD = 0x37 | OPC_SPECIAL3,
440 R6_OPC_SCD = 0x27 | OPC_SPECIAL3,
441 };
442
443 /* Loongson EXT load/store quad word opcodes */
444 #define MASK_LOONGSON_GSLSQ(op) (MASK_OP_MAJOR(op) | (op & 0x8020))
445 enum {
446 OPC_GSLQ = 0x0020 | OPC_LWC2,
447 OPC_GSLQC1 = 0x8020 | OPC_LWC2,
448 OPC_GSSHFL = OPC_LWC2,
449 OPC_GSSQ = 0x0020 | OPC_SWC2,
450 OPC_GSSQC1 = 0x8020 | OPC_SWC2,
451 OPC_GSSHFS = OPC_SWC2,
452 };
453
454 /* Loongson EXT shifted load/store opcodes */
455 #define MASK_LOONGSON_GSSHFLS(op) (MASK_OP_MAJOR(op) | (op & 0xc03f))
456 enum {
457 OPC_GSLWLC1 = 0x4 | OPC_GSSHFL,
458 OPC_GSLWRC1 = 0x5 | OPC_GSSHFL,
459 OPC_GSLDLC1 = 0x6 | OPC_GSSHFL,
460 OPC_GSLDRC1 = 0x7 | OPC_GSSHFL,
461 OPC_GSSWLC1 = 0x4 | OPC_GSSHFS,
462 OPC_GSSWRC1 = 0x5 | OPC_GSSHFS,
463 OPC_GSSDLC1 = 0x6 | OPC_GSSHFS,
464 OPC_GSSDRC1 = 0x7 | OPC_GSSHFS,
465 };
466
467 /* Loongson EXT LDC2/SDC2 opcodes */
468 #define MASK_LOONGSON_LSDC2(op) (MASK_OP_MAJOR(op) | (op & 0x7))
469
470 enum {
471 OPC_GSLBX = 0x0 | OPC_LDC2,
472 OPC_GSLHX = 0x1 | OPC_LDC2,
473 OPC_GSLWX = 0x2 | OPC_LDC2,
474 OPC_GSLDX = 0x3 | OPC_LDC2,
475 OPC_GSLWXC1 = 0x6 | OPC_LDC2,
476 OPC_GSLDXC1 = 0x7 | OPC_LDC2,
477 OPC_GSSBX = 0x0 | OPC_SDC2,
478 OPC_GSSHX = 0x1 | OPC_SDC2,
479 OPC_GSSWX = 0x2 | OPC_SDC2,
480 OPC_GSSDX = 0x3 | OPC_SDC2,
481 OPC_GSSWXC1 = 0x6 | OPC_SDC2,
482 OPC_GSSDXC1 = 0x7 | OPC_SDC2,
483 };
484
485 /* BSHFL opcodes */
486 #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
487
488 enum {
489 OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
490 OPC_SEB = (0x10 << 6) | OPC_BSHFL,
491 OPC_SEH = (0x18 << 6) | OPC_BSHFL,
492 OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp (010.00 to 010.11) */
493 OPC_ALIGN_1 = (0x09 << 6) | OPC_BSHFL,
494 OPC_ALIGN_2 = (0x0A << 6) | OPC_BSHFL,
495 OPC_ALIGN_3 = (0x0B << 6) | OPC_BSHFL,
496 OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 00000 */
497 };
498
499 /* DBSHFL opcodes */
500 #define MASK_DBSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
501
502 enum {
503 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
504 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
505 OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp (01.000 to 01.111) */
506 OPC_DALIGN_1 = (0x09 << 6) | OPC_DBSHFL,
507 OPC_DALIGN_2 = (0x0A << 6) | OPC_DBSHFL,
508 OPC_DALIGN_3 = (0x0B << 6) | OPC_DBSHFL,
509 OPC_DALIGN_4 = (0x0C << 6) | OPC_DBSHFL,
510 OPC_DALIGN_5 = (0x0D << 6) | OPC_DBSHFL,
511 OPC_DALIGN_6 = (0x0E << 6) | OPC_DBSHFL,
512 OPC_DALIGN_7 = (0x0F << 6) | OPC_DBSHFL,
513 OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 00000 */
514 };
515
516 /* MIPS DSP REGIMM opcodes */
517 enum {
518 OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM,
519 OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM,
520 };
521
522 #define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
523 /* MIPS DSP Load */
524 enum {
525 OPC_LBUX = (0x06 << 6) | OPC_LX_DSP,
526 OPC_LHX = (0x04 << 6) | OPC_LX_DSP,
527 OPC_LWX = (0x00 << 6) | OPC_LX_DSP,
528 OPC_LDX = (0x08 << 6) | OPC_LX_DSP,
529 };
530
531 #define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
532 enum {
533 /* MIPS DSP Arithmetic Sub-class */
534 OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP,
535 OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP,
536 OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP,
537 OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP,
538 OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP,
539 OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP,
540 OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP,
541 OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP,
542 OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP,
543 OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP,
544 OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP,
545 OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP,
546 OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP,
547 OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP,
548 OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP,
549 OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP,
550 OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP,
551 OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP,
552 /* MIPS DSP Multiply Sub-class insns */
553 OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP,
554 OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP,
555 OPC_MULQ_RS_PH = (0x1F << 6) | OPC_ADDU_QB_DSP,
556 OPC_MULEQ_S_W_PHL = (0x1C << 6) | OPC_ADDU_QB_DSP,
557 OPC_MULEQ_S_W_PHR = (0x1D << 6) | OPC_ADDU_QB_DSP,
558 OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP,
559 };
560
561 #define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
562 #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
563 enum {
564 /* MIPS DSP Arithmetic Sub-class */
565 OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP,
566 OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP,
567 OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP,
568 OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP,
569 OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP,
570 OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP,
571 OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP,
572 OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP,
573 OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP,
574 OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP,
575 OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP,
576 OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP,
577 /* MIPS DSP Multiply Sub-class insns */
578 OPC_MUL_PH = (0x0C << 6) | OPC_ADDUH_QB_DSP,
579 OPC_MUL_S_PH = (0x0E << 6) | OPC_ADDUH_QB_DSP,
580 OPC_MULQ_S_W = (0x16 << 6) | OPC_ADDUH_QB_DSP,
581 OPC_MULQ_RS_W = (0x17 << 6) | OPC_ADDUH_QB_DSP,
582 };
583
584 #define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
585 enum {
586 /* MIPS DSP Arithmetic Sub-class */
587 OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP,
588 OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP,
589 OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP,
590 OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP,
591 OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP,
592 OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP,
593 OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP,
594 OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP,
595 OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP,
596 OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP,
597 OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP,
598 OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP,
599 OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP,
600 /* DSP Bit/Manipulation Sub-class */
601 OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP,
602 OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP,
603 OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP,
604 OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP,
605 OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP,
606 };
607
608 #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
609 enum {
610 /* MIPS DSP Arithmetic Sub-class */
611 OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP,
612 OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP,
613 OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP,
614 OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP,
615 OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP,
616 OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP,
617 OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP,
618 /* DSP Compare-Pick Sub-class */
619 OPC_CMPU_EQ_QB = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP,
620 OPC_CMPU_LT_QB = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP,
621 OPC_CMPU_LE_QB = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP,
622 OPC_CMPGU_EQ_QB = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP,
623 OPC_CMPGU_LT_QB = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP,
624 OPC_CMPGU_LE_QB = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP,
625 OPC_CMPGDU_EQ_QB = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP,
626 OPC_CMPGDU_LT_QB = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP,
627 OPC_CMPGDU_LE_QB = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP,
628 OPC_CMP_EQ_PH = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP,
629 OPC_CMP_LT_PH = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP,
630 OPC_CMP_LE_PH = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP,
631 OPC_PICK_QB = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP,
632 OPC_PICK_PH = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP,
633 OPC_PACKRL_PH = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP,
634 };
635
636 #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
637 enum {
638 /* MIPS DSP GPR-Based Shift Sub-class */
639 OPC_SHLL_QB = (0x00 << 6) | OPC_SHLL_QB_DSP,
640 OPC_SHLLV_QB = (0x02 << 6) | OPC_SHLL_QB_DSP,
641 OPC_SHLL_PH = (0x08 << 6) | OPC_SHLL_QB_DSP,
642 OPC_SHLLV_PH = (0x0A << 6) | OPC_SHLL_QB_DSP,
643 OPC_SHLL_S_PH = (0x0C << 6) | OPC_SHLL_QB_DSP,
644 OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP,
645 OPC_SHLL_S_W = (0x14 << 6) | OPC_SHLL_QB_DSP,
646 OPC_SHLLV_S_W = (0x16 << 6) | OPC_SHLL_QB_DSP,
647 OPC_SHRL_QB = (0x01 << 6) | OPC_SHLL_QB_DSP,
648 OPC_SHRLV_QB = (0x03 << 6) | OPC_SHLL_QB_DSP,
649 OPC_SHRL_PH = (0x19 << 6) | OPC_SHLL_QB_DSP,
650 OPC_SHRLV_PH = (0x1B << 6) | OPC_SHLL_QB_DSP,
651 OPC_SHRA_QB = (0x04 << 6) | OPC_SHLL_QB_DSP,
652 OPC_SHRA_R_QB = (0x05 << 6) | OPC_SHLL_QB_DSP,
653 OPC_SHRAV_QB = (0x06 << 6) | OPC_SHLL_QB_DSP,
654 OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP,
655 OPC_SHRA_PH = (0x09 << 6) | OPC_SHLL_QB_DSP,
656 OPC_SHRAV_PH = (0x0B << 6) | OPC_SHLL_QB_DSP,
657 OPC_SHRA_R_PH = (0x0D << 6) | OPC_SHLL_QB_DSP,
658 OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP,
659 OPC_SHRA_R_W = (0x15 << 6) | OPC_SHLL_QB_DSP,
660 OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP,
661 };
662
663 #define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
664 enum {
665 /* MIPS DSP Multiply Sub-class insns */
666 OPC_DPAU_H_QBL = (0x03 << 6) | OPC_DPA_W_PH_DSP,
667 OPC_DPAU_H_QBR = (0x07 << 6) | OPC_DPA_W_PH_DSP,
668 OPC_DPSU_H_QBL = (0x0B << 6) | OPC_DPA_W_PH_DSP,
669 OPC_DPSU_H_QBR = (0x0F << 6) | OPC_DPA_W_PH_DSP,
670 OPC_DPA_W_PH = (0x00 << 6) | OPC_DPA_W_PH_DSP,
671 OPC_DPAX_W_PH = (0x08 << 6) | OPC_DPA_W_PH_DSP,
672 OPC_DPAQ_S_W_PH = (0x04 << 6) | OPC_DPA_W_PH_DSP,
673 OPC_DPAQX_S_W_PH = (0x18 << 6) | OPC_DPA_W_PH_DSP,
674 OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP,
675 OPC_DPS_W_PH = (0x01 << 6) | OPC_DPA_W_PH_DSP,
676 OPC_DPSX_W_PH = (0x09 << 6) | OPC_DPA_W_PH_DSP,
677 OPC_DPSQ_S_W_PH = (0x05 << 6) | OPC_DPA_W_PH_DSP,
678 OPC_DPSQX_S_W_PH = (0x19 << 6) | OPC_DPA_W_PH_DSP,
679 OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP,
680 OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP,
681 OPC_DPAQ_SA_L_W = (0x0C << 6) | OPC_DPA_W_PH_DSP,
682 OPC_DPSQ_SA_L_W = (0x0D << 6) | OPC_DPA_W_PH_DSP,
683 OPC_MAQ_S_W_PHL = (0x14 << 6) | OPC_DPA_W_PH_DSP,
684 OPC_MAQ_S_W_PHR = (0x16 << 6) | OPC_DPA_W_PH_DSP,
685 OPC_MAQ_SA_W_PHL = (0x10 << 6) | OPC_DPA_W_PH_DSP,
686 OPC_MAQ_SA_W_PHR = (0x12 << 6) | OPC_DPA_W_PH_DSP,
687 OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP,
688 };
689
690 #define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
691 enum {
692 /* DSP Bit/Manipulation Sub-class */
693 OPC_INSV = (0x00 << 6) | OPC_INSV_DSP,
694 };
695
696 #define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
697 enum {
698 /* MIPS DSP Append Sub-class */
699 OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP,
700 OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP,
701 OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP,
702 };
703
704 #define MASK_EXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
705 enum {
706 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
707 OPC_EXTR_W = (0x00 << 6) | OPC_EXTR_W_DSP,
708 OPC_EXTR_R_W = (0x04 << 6) | OPC_EXTR_W_DSP,
709 OPC_EXTR_RS_W = (0x06 << 6) | OPC_EXTR_W_DSP,
710 OPC_EXTR_S_H = (0x0E << 6) | OPC_EXTR_W_DSP,
711 OPC_EXTRV_S_H = (0x0F << 6) | OPC_EXTR_W_DSP,
712 OPC_EXTRV_W = (0x01 << 6) | OPC_EXTR_W_DSP,
713 OPC_EXTRV_R_W = (0x05 << 6) | OPC_EXTR_W_DSP,
714 OPC_EXTRV_RS_W = (0x07 << 6) | OPC_EXTR_W_DSP,
715 OPC_EXTP = (0x02 << 6) | OPC_EXTR_W_DSP,
716 OPC_EXTPV = (0x03 << 6) | OPC_EXTR_W_DSP,
717 OPC_EXTPDP = (0x0A << 6) | OPC_EXTR_W_DSP,
718 OPC_EXTPDPV = (0x0B << 6) | OPC_EXTR_W_DSP,
719 OPC_SHILO = (0x1A << 6) | OPC_EXTR_W_DSP,
720 OPC_SHILOV = (0x1B << 6) | OPC_EXTR_W_DSP,
721 OPC_MTHLIP = (0x1F << 6) | OPC_EXTR_W_DSP,
722 OPC_WRDSP = (0x13 << 6) | OPC_EXTR_W_DSP,
723 OPC_RDDSP = (0x12 << 6) | OPC_EXTR_W_DSP,
724 };
725
726 #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
727 enum {
728 /* MIPS DSP Arithmetic Sub-class */
729 OPC_PRECEQ_L_PWL = (0x14 << 6) | OPC_ABSQ_S_QH_DSP,
730 OPC_PRECEQ_L_PWR = (0x15 << 6) | OPC_ABSQ_S_QH_DSP,
731 OPC_PRECEQ_PW_QHL = (0x0C << 6) | OPC_ABSQ_S_QH_DSP,
732 OPC_PRECEQ_PW_QHR = (0x0D << 6) | OPC_ABSQ_S_QH_DSP,
733 OPC_PRECEQ_PW_QHLA = (0x0E << 6) | OPC_ABSQ_S_QH_DSP,
734 OPC_PRECEQ_PW_QHRA = (0x0F << 6) | OPC_ABSQ_S_QH_DSP,
735 OPC_PRECEQU_QH_OBL = (0x04 << 6) | OPC_ABSQ_S_QH_DSP,
736 OPC_PRECEQU_QH_OBR = (0x05 << 6) | OPC_ABSQ_S_QH_DSP,
737 OPC_PRECEQU_QH_OBLA = (0x06 << 6) | OPC_ABSQ_S_QH_DSP,
738 OPC_PRECEQU_QH_OBRA = (0x07 << 6) | OPC_ABSQ_S_QH_DSP,
739 OPC_PRECEU_QH_OBL = (0x1C << 6) | OPC_ABSQ_S_QH_DSP,
740 OPC_PRECEU_QH_OBR = (0x1D << 6) | OPC_ABSQ_S_QH_DSP,
741 OPC_PRECEU_QH_OBLA = (0x1E << 6) | OPC_ABSQ_S_QH_DSP,
742 OPC_PRECEU_QH_OBRA = (0x1F << 6) | OPC_ABSQ_S_QH_DSP,
743 OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP,
744 OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP,
745 OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP,
746 /* DSP Bit/Manipulation Sub-class */
747 OPC_REPL_OB = (0x02 << 6) | OPC_ABSQ_S_QH_DSP,
748 OPC_REPL_PW = (0x12 << 6) | OPC_ABSQ_S_QH_DSP,
749 OPC_REPL_QH = (0x0A << 6) | OPC_ABSQ_S_QH_DSP,
750 OPC_REPLV_OB = (0x03 << 6) | OPC_ABSQ_S_QH_DSP,
751 OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP,
752 OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP,
753 };
754
755 #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
756 enum {
757 /* MIPS DSP Multiply Sub-class insns */
758 OPC_MULEQ_S_PW_QHL = (0x1C << 6) | OPC_ADDU_OB_DSP,
759 OPC_MULEQ_S_PW_QHR = (0x1D << 6) | OPC_ADDU_OB_DSP,
760 OPC_MULEU_S_QH_OBL = (0x06 << 6) | OPC_ADDU_OB_DSP,
761 OPC_MULEU_S_QH_OBR = (0x07 << 6) | OPC_ADDU_OB_DSP,
762 OPC_MULQ_RS_QH = (0x1F << 6) | OPC_ADDU_OB_DSP,
763 /* MIPS DSP Arithmetic Sub-class */
764 OPC_RADDU_L_OB = (0x14 << 6) | OPC_ADDU_OB_DSP,
765 OPC_SUBQ_PW = (0x13 << 6) | OPC_ADDU_OB_DSP,
766 OPC_SUBQ_S_PW = (0x17 << 6) | OPC_ADDU_OB_DSP,
767 OPC_SUBQ_QH = (0x0B << 6) | OPC_ADDU_OB_DSP,
768 OPC_SUBQ_S_QH = (0x0F << 6) | OPC_ADDU_OB_DSP,
769 OPC_SUBU_OB = (0x01 << 6) | OPC_ADDU_OB_DSP,
770 OPC_SUBU_S_OB = (0x05 << 6) | OPC_ADDU_OB_DSP,
771 OPC_SUBU_QH = (0x09 << 6) | OPC_ADDU_OB_DSP,
772 OPC_SUBU_S_QH = (0x0D << 6) | OPC_ADDU_OB_DSP,
773 OPC_SUBUH_OB = (0x19 << 6) | OPC_ADDU_OB_DSP,
774 OPC_SUBUH_R_OB = (0x1B << 6) | OPC_ADDU_OB_DSP,
775 OPC_ADDQ_PW = (0x12 << 6) | OPC_ADDU_OB_DSP,
776 OPC_ADDQ_S_PW = (0x16 << 6) | OPC_ADDU_OB_DSP,
777 OPC_ADDQ_QH = (0x0A << 6) | OPC_ADDU_OB_DSP,
778 OPC_ADDQ_S_QH = (0x0E << 6) | OPC_ADDU_OB_DSP,
779 OPC_ADDU_OB = (0x00 << 6) | OPC_ADDU_OB_DSP,
780 OPC_ADDU_S_OB = (0x04 << 6) | OPC_ADDU_OB_DSP,
781 OPC_ADDU_QH = (0x08 << 6) | OPC_ADDU_OB_DSP,
782 OPC_ADDU_S_QH = (0x0C << 6) | OPC_ADDU_OB_DSP,
783 OPC_ADDUH_OB = (0x18 << 6) | OPC_ADDU_OB_DSP,
784 OPC_ADDUH_R_OB = (0x1A << 6) | OPC_ADDU_OB_DSP,
785 };
786
787 #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
788 enum {
789 /* DSP Compare-Pick Sub-class */
790 OPC_CMP_EQ_PW = (0x10 << 6) | OPC_CMPU_EQ_OB_DSP,
791 OPC_CMP_LT_PW = (0x11 << 6) | OPC_CMPU_EQ_OB_DSP,
792 OPC_CMP_LE_PW = (0x12 << 6) | OPC_CMPU_EQ_OB_DSP,
793 OPC_CMP_EQ_QH = (0x08 << 6) | OPC_CMPU_EQ_OB_DSP,
794 OPC_CMP_LT_QH = (0x09 << 6) | OPC_CMPU_EQ_OB_DSP,
795 OPC_CMP_LE_QH = (0x0A << 6) | OPC_CMPU_EQ_OB_DSP,
796 OPC_CMPGDU_EQ_OB = (0x18 << 6) | OPC_CMPU_EQ_OB_DSP,
797 OPC_CMPGDU_LT_OB = (0x19 << 6) | OPC_CMPU_EQ_OB_DSP,
798 OPC_CMPGDU_LE_OB = (0x1A << 6) | OPC_CMPU_EQ_OB_DSP,
799 OPC_CMPGU_EQ_OB = (0x04 << 6) | OPC_CMPU_EQ_OB_DSP,
800 OPC_CMPGU_LT_OB = (0x05 << 6) | OPC_CMPU_EQ_OB_DSP,
801 OPC_CMPGU_LE_OB = (0x06 << 6) | OPC_CMPU_EQ_OB_DSP,
802 OPC_CMPU_EQ_OB = (0x00 << 6) | OPC_CMPU_EQ_OB_DSP,
803 OPC_CMPU_LT_OB = (0x01 << 6) | OPC_CMPU_EQ_OB_DSP,
804 OPC_CMPU_LE_OB = (0x02 << 6) | OPC_CMPU_EQ_OB_DSP,
805 OPC_PACKRL_PW = (0x0E << 6) | OPC_CMPU_EQ_OB_DSP,
806 OPC_PICK_OB = (0x03 << 6) | OPC_CMPU_EQ_OB_DSP,
807 OPC_PICK_PW = (0x13 << 6) | OPC_CMPU_EQ_OB_DSP,
808 OPC_PICK_QH = (0x0B << 6) | OPC_CMPU_EQ_OB_DSP,
809 /* MIPS DSP Arithmetic Sub-class */
810 OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP,
811 OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP,
812 OPC_PRECR_SRA_R_QH_PW = (0x1F << 6) | OPC_CMPU_EQ_OB_DSP,
813 OPC_PRECRQ_OB_QH = (0x0C << 6) | OPC_CMPU_EQ_OB_DSP,
814 OPC_PRECRQ_PW_L = (0x1C << 6) | OPC_CMPU_EQ_OB_DSP,
815 OPC_PRECRQ_QH_PW = (0x14 << 6) | OPC_CMPU_EQ_OB_DSP,
816 OPC_PRECRQ_RS_QH_PW = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP,
817 OPC_PRECRQU_S_OB_QH = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP,
818 };
819
820 #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
821 enum {
822 /* DSP Append Sub-class */
823 OPC_DAPPEND = (0x00 << 6) | OPC_DAPPEND_DSP,
824 OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP,
825 OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP,
826 OPC_DBALIGN = (0x10 << 6) | OPC_DAPPEND_DSP,
827 };
828
829 #define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
830 enum {
831 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
832 OPC_DMTHLIP = (0x1F << 6) | OPC_DEXTR_W_DSP,
833 OPC_DSHILO = (0x1A << 6) | OPC_DEXTR_W_DSP,
834 OPC_DEXTP = (0x02 << 6) | OPC_DEXTR_W_DSP,
835 OPC_DEXTPDP = (0x0A << 6) | OPC_DEXTR_W_DSP,
836 OPC_DEXTPDPV = (0x0B << 6) | OPC_DEXTR_W_DSP,
837 OPC_DEXTPV = (0x03 << 6) | OPC_DEXTR_W_DSP,
838 OPC_DEXTR_L = (0x10 << 6) | OPC_DEXTR_W_DSP,
839 OPC_DEXTR_R_L = (0x14 << 6) | OPC_DEXTR_W_DSP,
840 OPC_DEXTR_RS_L = (0x16 << 6) | OPC_DEXTR_W_DSP,
841 OPC_DEXTR_W = (0x00 << 6) | OPC_DEXTR_W_DSP,
842 OPC_DEXTR_R_W = (0x04 << 6) | OPC_DEXTR_W_DSP,
843 OPC_DEXTR_RS_W = (0x06 << 6) | OPC_DEXTR_W_DSP,
844 OPC_DEXTR_S_H = (0x0E << 6) | OPC_DEXTR_W_DSP,
845 OPC_DEXTRV_L = (0x11 << 6) | OPC_DEXTR_W_DSP,
846 OPC_DEXTRV_R_L = (0x15 << 6) | OPC_DEXTR_W_DSP,
847 OPC_DEXTRV_RS_L = (0x17 << 6) | OPC_DEXTR_W_DSP,
848 OPC_DEXTRV_S_H = (0x0F << 6) | OPC_DEXTR_W_DSP,
849 OPC_DEXTRV_W = (0x01 << 6) | OPC_DEXTR_W_DSP,
850 OPC_DEXTRV_R_W = (0x05 << 6) | OPC_DEXTR_W_DSP,
851 OPC_DEXTRV_RS_W = (0x07 << 6) | OPC_DEXTR_W_DSP,
852 OPC_DSHILOV = (0x1B << 6) | OPC_DEXTR_W_DSP,
853 };
854
855 #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
856 enum {
857 /* DSP Bit/Manipulation Sub-class */
858 OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP,
859 };
860
861 #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
862 enum {
863 /* MIPS DSP Multiply Sub-class insns */
864 OPC_DMADD = (0x19 << 6) | OPC_DPAQ_W_QH_DSP,
865 OPC_DMADDU = (0x1D << 6) | OPC_DPAQ_W_QH_DSP,
866 OPC_DMSUB = (0x1B << 6) | OPC_DPAQ_W_QH_DSP,
867 OPC_DMSUBU = (0x1F << 6) | OPC_DPAQ_W_QH_DSP,
868 OPC_DPA_W_QH = (0x00 << 6) | OPC_DPAQ_W_QH_DSP,
869 OPC_DPAQ_S_W_QH = (0x04 << 6) | OPC_DPAQ_W_QH_DSP,
870 OPC_DPAQ_SA_L_PW = (0x0C << 6) | OPC_DPAQ_W_QH_DSP,
871 OPC_DPAU_H_OBL = (0x03 << 6) | OPC_DPAQ_W_QH_DSP,
872 OPC_DPAU_H_OBR = (0x07 << 6) | OPC_DPAQ_W_QH_DSP,
873 OPC_DPS_W_QH = (0x01 << 6) | OPC_DPAQ_W_QH_DSP,
874 OPC_DPSQ_S_W_QH = (0x05 << 6) | OPC_DPAQ_W_QH_DSP,
875 OPC_DPSQ_SA_L_PW = (0x0D << 6) | OPC_DPAQ_W_QH_DSP,
876 OPC_DPSU_H_OBL = (0x0B << 6) | OPC_DPAQ_W_QH_DSP,
877 OPC_DPSU_H_OBR = (0x0F << 6) | OPC_DPAQ_W_QH_DSP,
878 OPC_MAQ_S_L_PWL = (0x1C << 6) | OPC_DPAQ_W_QH_DSP,
879 OPC_MAQ_S_L_PWR = (0x1E << 6) | OPC_DPAQ_W_QH_DSP,
880 OPC_MAQ_S_W_QHLL = (0x14 << 6) | OPC_DPAQ_W_QH_DSP,
881 OPC_MAQ_SA_W_QHLL = (0x10 << 6) | OPC_DPAQ_W_QH_DSP,
882 OPC_MAQ_S_W_QHLR = (0x15 << 6) | OPC_DPAQ_W_QH_DSP,
883 OPC_MAQ_SA_W_QHLR = (0x11 << 6) | OPC_DPAQ_W_QH_DSP,
884 OPC_MAQ_S_W_QHRL = (0x16 << 6) | OPC_DPAQ_W_QH_DSP,
885 OPC_MAQ_SA_W_QHRL = (0x12 << 6) | OPC_DPAQ_W_QH_DSP,
886 OPC_MAQ_S_W_QHRR = (0x17 << 6) | OPC_DPAQ_W_QH_DSP,
887 OPC_MAQ_SA_W_QHRR = (0x13 << 6) | OPC_DPAQ_W_QH_DSP,
888 OPC_MULSAQ_S_L_PW = (0x0E << 6) | OPC_DPAQ_W_QH_DSP,
889 OPC_MULSAQ_S_W_QH = (0x06 << 6) | OPC_DPAQ_W_QH_DSP,
890 };
891
892 #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
893 enum {
894 /* MIPS DSP GPR-Based Shift Sub-class */
895 OPC_SHLL_PW = (0x10 << 6) | OPC_SHLL_OB_DSP,
896 OPC_SHLL_S_PW = (0x14 << 6) | OPC_SHLL_OB_DSP,
897 OPC_SHLLV_OB = (0x02 << 6) | OPC_SHLL_OB_DSP,
898 OPC_SHLLV_PW = (0x12 << 6) | OPC_SHLL_OB_DSP,
899 OPC_SHLLV_S_PW = (0x16 << 6) | OPC_SHLL_OB_DSP,
900 OPC_SHLLV_QH = (0x0A << 6) | OPC_SHLL_OB_DSP,
901 OPC_SHLLV_S_QH = (0x0E << 6) | OPC_SHLL_OB_DSP,
902 OPC_SHRA_PW = (0x11 << 6) | OPC_SHLL_OB_DSP,
903 OPC_SHRA_R_PW = (0x15 << 6) | OPC_SHLL_OB_DSP,
904 OPC_SHRAV_OB = (0x06 << 6) | OPC_SHLL_OB_DSP,
905 OPC_SHRAV_R_OB = (0x07 << 6) | OPC_SHLL_OB_DSP,
906 OPC_SHRAV_PW = (0x13 << 6) | OPC_SHLL_OB_DSP,
907 OPC_SHRAV_R_PW = (0x17 << 6) | OPC_SHLL_OB_DSP,
908 OPC_SHRAV_QH = (0x0B << 6) | OPC_SHLL_OB_DSP,
909 OPC_SHRAV_R_QH = (0x0F << 6) | OPC_SHLL_OB_DSP,
910 OPC_SHRLV_OB = (0x03 << 6) | OPC_SHLL_OB_DSP,
911 OPC_SHRLV_QH = (0x1B << 6) | OPC_SHLL_OB_DSP,
912 OPC_SHLL_OB = (0x00 << 6) | OPC_SHLL_OB_DSP,
913 OPC_SHLL_QH = (0x08 << 6) | OPC_SHLL_OB_DSP,
914 OPC_SHLL_S_QH = (0x0C << 6) | OPC_SHLL_OB_DSP,
915 OPC_SHRA_OB = (0x04 << 6) | OPC_SHLL_OB_DSP,
916 OPC_SHRA_R_OB = (0x05 << 6) | OPC_SHLL_OB_DSP,
917 OPC_SHRA_QH = (0x09 << 6) | OPC_SHLL_OB_DSP,
918 OPC_SHRA_R_QH = (0x0D << 6) | OPC_SHLL_OB_DSP,
919 OPC_SHRL_OB = (0x01 << 6) | OPC_SHLL_OB_DSP,
920 OPC_SHRL_QH = (0x19 << 6) | OPC_SHLL_OB_DSP,
921 };
922
923 /* Coprocessor 0 (rs field) */
924 #define MASK_CP0(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
925
926 enum {
927 OPC_MFC0 = (0x00 << 21) | OPC_CP0,
928 OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
929 OPC_MFHC0 = (0x02 << 21) | OPC_CP0,
930 OPC_MTC0 = (0x04 << 21) | OPC_CP0,
931 OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
932 OPC_MTHC0 = (0x06 << 21) | OPC_CP0,
933 OPC_MFTR = (0x08 << 21) | OPC_CP0,
934 OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
935 OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
936 OPC_MTTR = (0x0C << 21) | OPC_CP0,
937 OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
938 OPC_C0 = (0x10 << 21) | OPC_CP0,
939 OPC_C0_1 = (0x11 << 21) | OPC_CP0,
940 OPC_C0_2 = (0x12 << 21) | OPC_CP0,
941 OPC_C0_3 = (0x13 << 21) | OPC_CP0,
942 OPC_C0_4 = (0x14 << 21) | OPC_CP0,
943 OPC_C0_5 = (0x15 << 21) | OPC_CP0,
944 OPC_C0_6 = (0x16 << 21) | OPC_CP0,
945 OPC_C0_7 = (0x17 << 21) | OPC_CP0,
946 OPC_C0_8 = (0x18 << 21) | OPC_CP0,
947 OPC_C0_9 = (0x19 << 21) | OPC_CP0,
948 OPC_C0_A = (0x1A << 21) | OPC_CP0,
949 OPC_C0_B = (0x1B << 21) | OPC_CP0,
950 OPC_C0_C = (0x1C << 21) | OPC_CP0,
951 OPC_C0_D = (0x1D << 21) | OPC_CP0,
952 OPC_C0_E = (0x1E << 21) | OPC_CP0,
953 OPC_C0_F = (0x1F << 21) | OPC_CP0,
954 };
955
956 /* MFMC0 opcodes */
957 #define MASK_MFMC0(op) (MASK_CP0(op) | (op & 0xFFFF))
958
959 enum {
960 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
961 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
962 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0,
963 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0,
964 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
965 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
966 OPC_DVP = 0x04 | (0 << 3) | (1 << 5) | (0 << 11) | OPC_MFMC0,
967 OPC_EVP = 0x04 | (0 << 3) | (0 << 5) | (0 << 11) | OPC_MFMC0,
968 };
969
970 /* Coprocessor 0 (with rs == C0) */
971 #define MASK_C0(op) (MASK_CP0(op) | (op & 0x3F))
972
973 enum {
974 OPC_TLBR = 0x01 | OPC_C0,
975 OPC_TLBWI = 0x02 | OPC_C0,
976 OPC_TLBINV = 0x03 | OPC_C0,
977 OPC_TLBINVF = 0x04 | OPC_C0,
978 OPC_TLBWR = 0x06 | OPC_C0,
979 OPC_TLBP = 0x08 | OPC_C0,
980 OPC_RFE = 0x10 | OPC_C0,
981 OPC_ERET = 0x18 | OPC_C0,
982 OPC_DERET = 0x1F | OPC_C0,
983 OPC_WAIT = 0x20 | OPC_C0,
984 };
985
986 #define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
987
988 enum {
989 OPC_MFC2 = (0x00 << 21) | OPC_CP2,
990 OPC_DMFC2 = (0x01 << 21) | OPC_CP2,
991 OPC_CFC2 = (0x02 << 21) | OPC_CP2,
992 OPC_MFHC2 = (0x03 << 21) | OPC_CP2,
993 OPC_MTC2 = (0x04 << 21) | OPC_CP2,
994 OPC_DMTC2 = (0x05 << 21) | OPC_CP2,
995 OPC_CTC2 = (0x06 << 21) | OPC_CP2,
996 OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
997 OPC_BC2 = (0x08 << 21) | OPC_CP2,
998 OPC_BC2EQZ = (0x09 << 21) | OPC_CP2,
999 OPC_BC2NEZ = (0x0D << 21) | OPC_CP2,
1000 };
1001
1002 #define MASK_LMMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
1003
1004 enum {
1005 OPC_PADDSH = (24 << 21) | (0x00) | OPC_CP2,
1006 OPC_PADDUSH = (25 << 21) | (0x00) | OPC_CP2,
1007 OPC_PADDH = (26 << 21) | (0x00) | OPC_CP2,
1008 OPC_PADDW = (27 << 21) | (0x00) | OPC_CP2,
1009 OPC_PADDSB = (28 << 21) | (0x00) | OPC_CP2,
1010 OPC_PADDUSB = (29 << 21) | (0x00) | OPC_CP2,
1011 OPC_PADDB = (30 << 21) | (0x00) | OPC_CP2,
1012 OPC_PADDD = (31 << 21) | (0x00) | OPC_CP2,
1013
1014 OPC_PSUBSH = (24 << 21) | (0x01) | OPC_CP2,
1015 OPC_PSUBUSH = (25 << 21) | (0x01) | OPC_CP2,
1016 OPC_PSUBH = (26 << 21) | (0x01) | OPC_CP2,
1017 OPC_PSUBW = (27 << 21) | (0x01) | OPC_CP2,
1018 OPC_PSUBSB = (28 << 21) | (0x01) | OPC_CP2,
1019 OPC_PSUBUSB = (29 << 21) | (0x01) | OPC_CP2,
1020 OPC_PSUBB = (30 << 21) | (0x01) | OPC_CP2,
1021 OPC_PSUBD = (31 << 21) | (0x01) | OPC_CP2,
1022
1023 OPC_PSHUFH = (24 << 21) | (0x02) | OPC_CP2,
1024 OPC_PACKSSWH = (25 << 21) | (0x02) | OPC_CP2,
1025 OPC_PACKSSHB = (26 << 21) | (0x02) | OPC_CP2,
1026 OPC_PACKUSHB = (27 << 21) | (0x02) | OPC_CP2,
1027 OPC_XOR_CP2 = (28 << 21) | (0x02) | OPC_CP2,
1028 OPC_NOR_CP2 = (29 << 21) | (0x02) | OPC_CP2,
1029 OPC_AND_CP2 = (30 << 21) | (0x02) | OPC_CP2,
1030 OPC_PANDN = (31 << 21) | (0x02) | OPC_CP2,
1031
1032 OPC_PUNPCKLHW = (24 << 21) | (0x03) | OPC_CP2,
1033 OPC_PUNPCKHHW = (25 << 21) | (0x03) | OPC_CP2,
1034 OPC_PUNPCKLBH = (26 << 21) | (0x03) | OPC_CP2,
1035 OPC_PUNPCKHBH = (27 << 21) | (0x03) | OPC_CP2,
1036 OPC_PINSRH_0 = (28 << 21) | (0x03) | OPC_CP2,
1037 OPC_PINSRH_1 = (29 << 21) | (0x03) | OPC_CP2,
1038 OPC_PINSRH_2 = (30 << 21) | (0x03) | OPC_CP2,
1039 OPC_PINSRH_3 = (31 << 21) | (0x03) | OPC_CP2,
1040
1041 OPC_PAVGH = (24 << 21) | (0x08) | OPC_CP2,
1042 OPC_PAVGB = (25 << 21) | (0x08) | OPC_CP2,
1043 OPC_PMAXSH = (26 << 21) | (0x08) | OPC_CP2,
1044 OPC_PMINSH = (27 << 21) | (0x08) | OPC_CP2,
1045 OPC_PMAXUB = (28 << 21) | (0x08) | OPC_CP2,
1046 OPC_PMINUB = (29 << 21) | (0x08) | OPC_CP2,
1047
1048 OPC_PCMPEQW = (24 << 21) | (0x09) | OPC_CP2,
1049 OPC_PCMPGTW = (25 << 21) | (0x09) | OPC_CP2,
1050 OPC_PCMPEQH = (26 << 21) | (0x09) | OPC_CP2,
1051 OPC_PCMPGTH = (27 << 21) | (0x09) | OPC_CP2,
1052 OPC_PCMPEQB = (28 << 21) | (0x09) | OPC_CP2,
1053 OPC_PCMPGTB = (29 << 21) | (0x09) | OPC_CP2,
1054
1055 OPC_PSLLW = (24 << 21) | (0x0A) | OPC_CP2,
1056 OPC_PSLLH = (25 << 21) | (0x0A) | OPC_CP2,
1057 OPC_PMULLH = (26 << 21) | (0x0A) | OPC_CP2,
1058 OPC_PMULHH = (27 << 21) | (0x0A) | OPC_CP2,
1059 OPC_PMULUW = (28 << 21) | (0x0A) | OPC_CP2,
1060 OPC_PMULHUH = (29 << 21) | (0x0A) | OPC_CP2,
1061
1062 OPC_PSRLW = (24 << 21) | (0x0B) | OPC_CP2,
1063 OPC_PSRLH = (25 << 21) | (0x0B) | OPC_CP2,
1064 OPC_PSRAW = (26 << 21) | (0x0B) | OPC_CP2,
1065 OPC_PSRAH = (27 << 21) | (0x0B) | OPC_CP2,
1066 OPC_PUNPCKLWD = (28 << 21) | (0x0B) | OPC_CP2,
1067 OPC_PUNPCKHWD = (29 << 21) | (0x0B) | OPC_CP2,
1068
1069 OPC_ADDU_CP2 = (24 << 21) | (0x0C) | OPC_CP2,
1070 OPC_OR_CP2 = (25 << 21) | (0x0C) | OPC_CP2,
1071 OPC_ADD_CP2 = (26 << 21) | (0x0C) | OPC_CP2,
1072 OPC_DADD_CP2 = (27 << 21) | (0x0C) | OPC_CP2,
1073 OPC_SEQU_CP2 = (28 << 21) | (0x0C) | OPC_CP2,
1074 OPC_SEQ_CP2 = (29 << 21) | (0x0C) | OPC_CP2,
1075
1076 OPC_SUBU_CP2 = (24 << 21) | (0x0D) | OPC_CP2,
1077 OPC_PASUBUB = (25 << 21) | (0x0D) | OPC_CP2,
1078 OPC_SUB_CP2 = (26 << 21) | (0x0D) | OPC_CP2,
1079 OPC_DSUB_CP2 = (27 << 21) | (0x0D) | OPC_CP2,
1080 OPC_SLTU_CP2 = (28 << 21) | (0x0D) | OPC_CP2,
1081 OPC_SLT_CP2 = (29 << 21) | (0x0D) | OPC_CP2,
1082
1083 OPC_SLL_CP2 = (24 << 21) | (0x0E) | OPC_CP2,
1084 OPC_DSLL_CP2 = (25 << 21) | (0x0E) | OPC_CP2,
1085 OPC_PEXTRH = (26 << 21) | (0x0E) | OPC_CP2,
1086 OPC_PMADDHW = (27 << 21) | (0x0E) | OPC_CP2,
1087 OPC_SLEU_CP2 = (28 << 21) | (0x0E) | OPC_CP2,
1088 OPC_SLE_CP2 = (29 << 21) | (0x0E) | OPC_CP2,
1089
1090 OPC_SRL_CP2 = (24 << 21) | (0x0F) | OPC_CP2,
1091 OPC_DSRL_CP2 = (25 << 21) | (0x0F) | OPC_CP2,
1092 OPC_SRA_CP2 = (26 << 21) | (0x0F) | OPC_CP2,
1093 OPC_DSRA_CP2 = (27 << 21) | (0x0F) | OPC_CP2,
1094 OPC_BIADD = (28 << 21) | (0x0F) | OPC_CP2,
1095 OPC_PMOVMSKB = (29 << 21) | (0x0F) | OPC_CP2,
1096 };
1097
1098
1099 #define MASK_CP3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
1100
1101 enum {
1102 OPC_LWXC1 = 0x00 | OPC_CP3,
1103 OPC_LDXC1 = 0x01 | OPC_CP3,
1104 OPC_LUXC1 = 0x05 | OPC_CP3,
1105 OPC_SWXC1 = 0x08 | OPC_CP3,
1106 OPC_SDXC1 = 0x09 | OPC_CP3,
1107 OPC_SUXC1 = 0x0D | OPC_CP3,
1108 OPC_PREFX = 0x0F | OPC_CP3,
1109 OPC_ALNV_PS = 0x1E | OPC_CP3,
1110 OPC_MADD_S = 0x20 | OPC_CP3,
1111 OPC_MADD_D = 0x21 | OPC_CP3,
1112 OPC_MADD_PS = 0x26 | OPC_CP3,
1113 OPC_MSUB_S = 0x28 | OPC_CP3,
1114 OPC_MSUB_D = 0x29 | OPC_CP3,
1115 OPC_MSUB_PS = 0x2E | OPC_CP3,
1116 OPC_NMADD_S = 0x30 | OPC_CP3,
1117 OPC_NMADD_D = 0x31 | OPC_CP3,
1118 OPC_NMADD_PS = 0x36 | OPC_CP3,
1119 OPC_NMSUB_S = 0x38 | OPC_CP3,
1120 OPC_NMSUB_D = 0x39 | OPC_CP3,
1121 OPC_NMSUB_PS = 0x3E | OPC_CP3,
1122 };
1123
1124 /*
1125 * MMI (MultiMedia Instruction) encodings
1126 * ======================================
1127 *
1128 * MMI instructions encoding table keys:
1129 *
1130 * * This code is reserved for future use. An attempt to execute it
1131 * causes a Reserved Instruction exception.
1132 * % This code indicates an instruction class. The instruction word
1133 * must be further decoded by examining additional tables that show
1134 * the values for other instruction fields.
1135 * # This code is reserved for the unsupported instructions DMULT,
1136 * DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt
1137 * to execute it causes a Reserved Instruction exception.
1138 *
1139 * MMI instructions encoded by opcode field (MMI, LQ, SQ):
1140 *
1141 * 31 26 0
1142 * +--------+----------------------------------------+
1143 * | opcode | |
1144 * +--------+----------------------------------------+
1145 *
1146 * opcode bits 28..26
1147 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
1148 * 31..29 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
1149 * -------+-------+-------+-------+-------+-------+-------+-------+-------
1150 * 0 000 |SPECIAL| REGIMM| J | JAL | BEQ | BNE | BLEZ | BGTZ
1151 * 1 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI
1152 * 2 010 | COP0 | COP1 | * | * | BEQL | BNEL | BLEZL | BGTZL
1153 * 3 011 | DADDI | DADDIU| LDL | LDR | MMI% | * | LQ | SQ
1154 * 4 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU
1155 * 5 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE
1156 * 6 110 | # | LWC1 | # | PREF | # | LDC1 | # | LD
1157 * 7 111 | # | SWC1 | # | * | # | SDC1 | # | SD
1158 */
1159
1160 enum {
1161 MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
1162 MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
1163 };
1164
1165 /*
1166 * MMI instructions with opcode field = MMI:
1167 *
1168 * 31 26 5 0
1169 * +--------+-------------------------------+--------+
1170 * | MMI | |function|
1171 * +--------+-------------------------------+--------+
1172 *
1173 * function bits 2..0
1174 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
1175 * 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
1176 * -------+-------+-------+-------+-------+-------+-------+-------+-------
1177 * 0 000 | MADD | MADDU | * | * | PLZCW | * | * | *
1178 * 1 001 | MMI0% | MMI2% | * | * | * | * | * | *
1179 * 2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | * | * | * | *
1180 * 3 011 | MULT1 | MULTU1| DIV1 | DIVU1 | * | * | * | *
1181 * 4 100 | MADD1 | MADDU1| * | * | * | * | * | *
1182 * 5 101 | MMI1% | MMI3% | * | * | * | * | * | *
1183 * 6 110 | PMFHL | PMTHL | * | * | PSLLH | * | PSRLH | PSRAH
1184 * 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW
1185 */
1186
1187 #define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
1188 enum {
1189 MMI_OPC_MADD = 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */
1190 MMI_OPC_MADDU = 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU */
1191 MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */
1192 MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */
1193 MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */
1194 MMI_OPC_DIVU1 = 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIVU */
1195 MMI_OPC_MADD1 = 0x20 | MMI_OPC_CLASS_MMI,
1196 MMI_OPC_MADDU1 = 0x21 | MMI_OPC_CLASS_MMI,
1197 };
1198
1199 /* global register indices */
1200 TCGv cpu_gpr[32], cpu_PC;
1201 /*
1202 * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[])
1203 * and the upper halves in cpu_gpr_hi[].
1204 */
1205 TCGv_i64 cpu_gpr_hi[32];
1206 TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
1207 static TCGv cpu_dspctrl, btarget;
1208 TCGv bcond;
1209 static TCGv cpu_lladdr, cpu_llval;
1210 static TCGv_i32 hflags;
1211 TCGv_i32 fpu_fcr0, fpu_fcr31;
1212 TCGv_i64 fpu_f64[32];
1213
1214 #include "exec/gen-icount.h"
1215
1216 #define DISAS_STOP DISAS_TARGET_0
1217 #define DISAS_EXIT DISAS_TARGET_1
1218
1219 static const char regnames_HI[][4] = {
1220 "HI0", "HI1", "HI2", "HI3",
1221 };
1222
1223 static const char regnames_LO[][4] = {
1224 "LO0", "LO1", "LO2", "LO3",
1225 };
1226
1227 /* General purpose registers moves. */
1228 void gen_load_gpr(TCGv t, int reg)
1229 {
1230 if (reg == 0) {
1231 tcg_gen_movi_tl(t, 0);
1232 } else {
1233 tcg_gen_mov_tl(t, cpu_gpr[reg]);
1234 }
1235 }
1236
1237 void gen_store_gpr(TCGv t, int reg)
1238 {
1239 if (reg != 0) {
1240 tcg_gen_mov_tl(cpu_gpr[reg], t);
1241 }
1242 }
1243
1244 #if defined(TARGET_MIPS64)
1245 void gen_load_gpr_hi(TCGv_i64 t, int reg)
1246 {
1247 if (reg == 0) {
1248 tcg_gen_movi_i64(t, 0);
1249 } else {
1250 tcg_gen_mov_i64(t, cpu_gpr_hi[reg]);
1251 }
1252 }
1253
1254 void gen_store_gpr_hi(TCGv_i64 t, int reg)
1255 {
1256 if (reg != 0) {
1257 tcg_gen_mov_i64(cpu_gpr_hi[reg], t);
1258 }
1259 }
1260 #endif /* TARGET_MIPS64 */
1261
1262 /* Moves to/from shadow registers. */
1263 static inline void gen_load_srsgpr(int from, int to)
1264 {
1265 TCGv t0 = tcg_temp_new();
1266
1267 if (from == 0) {
1268 tcg_gen_movi_tl(t0, 0);
1269 } else {
1270 TCGv_i32 t2 = tcg_temp_new_i32();
1271 TCGv_ptr addr = tcg_temp_new_ptr();
1272
1273 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
1274 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
1275 tcg_gen_andi_i32(t2, t2, 0xf);
1276 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
1277 tcg_gen_ext_i32_ptr(addr, t2);
1278 tcg_gen_add_ptr(addr, cpu_env, addr);
1279
1280 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
1281 tcg_temp_free_ptr(addr);
1282 tcg_temp_free_i32(t2);
1283 }
1284 gen_store_gpr(t0, to);
1285 tcg_temp_free(t0);
1286 }
1287
1288 static inline void gen_store_srsgpr(int from, int to)
1289 {
1290 if (to != 0) {
1291 TCGv t0 = tcg_temp_new();
1292 TCGv_i32 t2 = tcg_temp_new_i32();
1293 TCGv_ptr addr = tcg_temp_new_ptr();
1294
1295 gen_load_gpr(t0, from);
1296 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
1297 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
1298 tcg_gen_andi_i32(t2, t2, 0xf);
1299 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
1300 tcg_gen_ext_i32_ptr(addr, t2);
1301 tcg_gen_add_ptr(addr, cpu_env, addr);
1302
1303 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
1304 tcg_temp_free_ptr(addr);
1305 tcg_temp_free_i32(t2);
1306 tcg_temp_free(t0);
1307 }
1308 }
1309
1310 /* Tests */
1311 static inline void gen_save_pc(target_ulong pc)
1312 {
1313 tcg_gen_movi_tl(cpu_PC, pc);
1314 }
1315
1316 static inline void save_cpu_state(DisasContext *ctx, int do_save_pc)
1317 {
1318 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
1319 if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) {
1320 gen_save_pc(ctx->base.pc_next);
1321 ctx->saved_pc = ctx->base.pc_next;
1322 }
1323 if (ctx->hflags != ctx->saved_hflags) {
1324 tcg_gen_movi_i32(hflags, ctx->hflags);
1325 ctx->saved_hflags = ctx->hflags;
1326 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
1327 case MIPS_HFLAG_BR:
1328 break;
1329 case MIPS_HFLAG_BC:
1330 case MIPS_HFLAG_BL:
1331 case MIPS_HFLAG_B:
1332 tcg_gen_movi_tl(btarget, ctx->btarget);
1333 break;
1334 }
1335 }
1336 }
1337
1338 static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
1339 {
1340 ctx->saved_hflags = ctx->hflags;
1341 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
1342 case MIPS_HFLAG_BR:
1343 break;
1344 case MIPS_HFLAG_BC:
1345 case MIPS_HFLAG_BL:
1346 case MIPS_HFLAG_B:
1347 ctx->btarget = env->btarget;
1348 break;
1349 }
1350 }
1351
1352 void generate_exception_err(DisasContext *ctx, int excp, int err)
1353 {
1354 save_cpu_state(ctx, 1);
1355 gen_helper_raise_exception_err(cpu_env, tcg_constant_i32(excp),
1356 tcg_constant_i32(err));
1357 ctx->base.is_jmp = DISAS_NORETURN;
1358 }
1359
1360 void generate_exception(DisasContext *ctx, int excp)
1361 {
1362 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
1363 }
1364
1365 void generate_exception_end(DisasContext *ctx, int excp)
1366 {
1367 generate_exception_err(ctx, excp, 0);
1368 }
1369
1370 void generate_exception_break(DisasContext *ctx, int code)
1371 {
1372 #ifdef CONFIG_USER_ONLY
1373 /* Pass the break code along to cpu_loop. */
1374 tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
1375 offsetof(CPUMIPSState, error_code));
1376 #endif
1377 generate_exception_end(ctx, EXCP_BREAK);
1378 }
1379
1380 void gen_reserved_instruction(DisasContext *ctx)
1381 {
1382 generate_exception_end(ctx, EXCP_RI);
1383 }
1384
1385 /* Floating point register moves. */
1386 void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
1387 {
1388 if (ctx->hflags & MIPS_HFLAG_FRE) {
1389 generate_exception(ctx, EXCP_RI);
1390 }
1391 tcg_gen_extrl_i64_i32(t, fpu_f64[reg]);
1392 }
1393
1394 void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
1395 {
1396 TCGv_i64 t64;
1397 if (ctx->hflags & MIPS_HFLAG_FRE) {
1398 generate_exception(ctx, EXCP_RI);
1399 }
1400 t64 = tcg_temp_new_i64();
1401 tcg_gen_extu_i32_i64(t64, t);
1402 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32);
1403 tcg_temp_free_i64(t64);
1404 }
1405
1406 static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
1407 {
1408 if (ctx->hflags & MIPS_HFLAG_F64) {
1409 tcg_gen_extrh_i64_i32(t, fpu_f64[reg]);
1410 } else {
1411 gen_load_fpr32(ctx, t, reg | 1);
1412 }
1413 }
1414
1415 static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
1416 {
1417 if (ctx->hflags & MIPS_HFLAG_F64) {
1418 TCGv_i64 t64 = tcg_temp_new_i64();
1419 tcg_gen_extu_i32_i64(t64, t);
1420 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32);
1421 tcg_temp_free_i64(t64);
1422 } else {
1423 gen_store_fpr32(ctx, t, reg | 1);
1424 }
1425 }
1426
1427 void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
1428 {
1429 if (ctx->hflags & MIPS_HFLAG_F64) {
1430 tcg_gen_mov_i64(t, fpu_f64[reg]);
1431 } else {
1432 tcg_gen_concat32_i64(t, fpu_f64[reg & ~1], fpu_f64[reg | 1]);
1433 }
1434 }
1435
1436 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
1437 {
1438 if (ctx->hflags & MIPS_HFLAG_F64) {
1439 tcg_gen_mov_i64(fpu_f64[reg], t);
1440 } else {
1441 TCGv_i64 t0;
1442 tcg_gen_deposit_i64(fpu_f64[reg & ~1], fpu_f64[reg & ~1], t, 0, 32);
1443 t0 = tcg_temp_new_i64();
1444 tcg_gen_shri_i64(t0, t, 32);
1445 tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32);
1446 tcg_temp_free_i64(t0);
1447 }
1448 }
1449
1450 int get_fp_bit(int cc)
1451 {
1452 if (cc) {
1453 return 24 + cc;
1454 } else {
1455 return 23;
1456 }
1457 }
1458
1459 /* Addresses computation */
1460 void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
1461 {
1462 tcg_gen_add_tl(ret, arg0, arg1);
1463
1464 #if defined(TARGET_MIPS64)
1465 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1466 tcg_gen_ext32s_i64(ret, ret);
1467 }
1468 #endif
1469 }
1470
1471 static inline void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base,
1472 target_long ofs)
1473 {
1474 tcg_gen_addi_tl(ret, base, ofs);
1475
1476 #if defined(TARGET_MIPS64)
1477 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1478 tcg_gen_ext32s_i64(ret, ret);
1479 }
1480 #endif
1481 }
1482
1483 /* Addresses computation (translation time) */
1484 static target_long addr_add(DisasContext *ctx, target_long base,
1485 target_long offset)
1486 {
1487 target_long sum = base + offset;
1488
1489 #if defined(TARGET_MIPS64)
1490 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1491 sum = (int32_t)sum;
1492 }
1493 #endif
1494 return sum;
1495 }
1496
1497 /* Sign-extract the low 32-bits to a target_long. */
1498 void gen_move_low32(TCGv ret, TCGv_i64 arg)
1499 {
1500 #if defined(TARGET_MIPS64)
1501 tcg_gen_ext32s_i64(ret, arg);
1502 #else
1503 tcg_gen_extrl_i64_i32(ret, arg);
1504 #endif
1505 }
1506
1507 /* Sign-extract the high 32-bits to a target_long. */
1508 void gen_move_high32(TCGv ret, TCGv_i64 arg)
1509 {
1510 #if defined(TARGET_MIPS64)
1511 tcg_gen_sari_i64(ret, arg, 32);
1512 #else
1513 tcg_gen_extrh_i64_i32(ret, arg);
1514 #endif
1515 }
1516
1517 bool check_cp0_enabled(DisasContext *ctx)
1518 {
1519 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
1520 generate_exception_end(ctx, EXCP_CpU);
1521 return false;
1522 }
1523 return true;
1524 }
1525
1526 void check_cp1_enabled(DisasContext *ctx)
1527 {
1528 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
1529 generate_exception_err(ctx, EXCP_CpU, 1);
1530 }
1531 }
1532
1533 /*
1534 * Verify that the processor is running with COP1X instructions enabled.
1535 * This is associated with the nabla symbol in the MIPS32 and MIPS64
1536 * opcode tables.
1537 */
1538 void check_cop1x(DisasContext *ctx)
1539 {
1540 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {
1541 gen_reserved_instruction(ctx);
1542 }
1543 }
1544
1545 /*
1546 * Verify that the processor is running with 64-bit floating-point
1547 * operations enabled.
1548 */
1549 void check_cp1_64bitmode(DisasContext *ctx)
1550 {
1551 if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {
1552 gen_reserved_instruction(ctx);
1553 }
1554 }
1555
1556 /*
1557 * Verify if floating point register is valid; an operation is not defined
1558 * if bit 0 of any register specification is set and the FR bit in the
1559 * Status register equals zero, since the register numbers specify an
1560 * even-odd pair of adjacent coprocessor general registers. When the FR bit
1561 * in the Status register equals one, both even and odd register numbers
1562 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
1563 *
1564 * Multiple 64 bit wide registers can be checked by calling
1565 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
1566 */
1567 void check_cp1_registers(DisasContext *ctx, int regs)
1568 {
1569 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {
1570 gen_reserved_instruction(ctx);
1571 }
1572 }
1573
1574 /*
1575 * Verify that the processor is running with DSP instructions enabled.
1576 * This is enabled by CP0 Status register MX(24) bit.
1577 */
1578 static inline void check_dsp(DisasContext *ctx)
1579 {
1580 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) {
1581 if (ctx->insn_flags & ASE_DSP) {
1582 generate_exception_end(ctx, EXCP_DSPDIS);
1583 } else {
1584 gen_reserved_instruction(ctx);
1585 }
1586 }
1587 }
1588
1589 static inline void check_dsp_r2(DisasContext *ctx)
1590 {
1591 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) {
1592 if (ctx->insn_flags & ASE_DSP) {
1593 generate_exception_end(ctx, EXCP_DSPDIS);
1594 } else {
1595 gen_reserved_instruction(ctx);
1596 }
1597 }
1598 }
1599
1600 static inline void check_dsp_r3(DisasContext *ctx)
1601 {
1602 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) {
1603 if (ctx->insn_flags & ASE_DSP) {
1604 generate_exception_end(ctx, EXCP_DSPDIS);
1605 } else {
1606 gen_reserved_instruction(ctx);
1607 }
1608 }
1609 }
1610
1611 /*
1612 * This code generates a "reserved instruction" exception if the
1613 * CPU does not support the instruction set corresponding to flags.
1614 */
1615 void check_insn(DisasContext *ctx, uint64_t flags)
1616 {
1617 if (unlikely(!(ctx->insn_flags & flags))) {
1618 gen_reserved_instruction(ctx);
1619 }
1620 }
1621
1622 /*
1623 * This code generates a "reserved instruction" exception if the
1624 * CPU has corresponding flag set which indicates that the instruction
1625 * has been removed.
1626 */
1627 static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
1628 {
1629 if (unlikely(ctx->insn_flags & flags)) {
1630 gen_reserved_instruction(ctx);
1631 }
1632 }
1633
1634 /*
1635 * The Linux kernel traps certain reserved instruction exceptions to
1636 * emulate the corresponding instructions. QEMU is the kernel in user
1637 * mode, so those traps are emulated by accepting the instructions.
1638 *
1639 * A reserved instruction exception is generated for flagged CPUs if
1640 * QEMU runs in system mode.
1641 */
1642 static inline void check_insn_opc_user_only(DisasContext *ctx, uint64_t flags)
1643 {
1644 #ifndef CONFIG_USER_ONLY
1645 check_insn_opc_removed(ctx, flags);
1646 #endif
1647 }
1648
1649 /*
1650 * This code generates a "reserved instruction" exception if the
1651 * CPU does not support 64-bit paired-single (PS) floating point data type.
1652 */
1653 static inline void check_ps(DisasContext *ctx)
1654 {
1655 if (unlikely(!ctx->ps)) {
1656 generate_exception(ctx, EXCP_RI);
1657 }
1658 check_cp1_64bitmode(ctx);
1659 }
1660
1661 /*
1662 * This code generates a "reserved instruction" exception if cpu is not
1663 * 64-bit or 64-bit instructions are not enabled.
1664 */
1665 void check_mips_64(DisasContext *ctx)
1666 {
1667 if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) {
1668 gen_reserved_instruction(ctx);
1669 }
1670 }
1671
1672 #ifndef CONFIG_USER_ONLY
1673 static inline void check_mvh(DisasContext *ctx)
1674 {
1675 if (unlikely(!ctx->mvh)) {
1676 generate_exception(ctx, EXCP_RI);
1677 }
1678 }
1679 #endif
1680
1681 /*
1682 * This code generates a "reserved instruction" exception if the
1683 * Config5 XNP bit is set.
1684 */
1685 static inline void check_xnp(DisasContext *ctx)
1686 {
1687 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) {
1688 gen_reserved_instruction(ctx);
1689 }
1690 }
1691
1692 #ifndef CONFIG_USER_ONLY
1693 /*
1694 * This code generates a "reserved instruction" exception if the
1695 * Config3 PW bit is NOT set.
1696 */
1697 static inline void check_pw(DisasContext *ctx)
1698 {
1699 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) {
1700 gen_reserved_instruction(ctx);
1701 }
1702 }
1703 #endif
1704
1705 /*
1706 * This code generates a "reserved instruction" exception if the
1707 * Config3 MT bit is NOT set.
1708 */
1709 static inline void check_mt(DisasContext *ctx)
1710 {
1711 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
1712 gen_reserved_instruction(ctx);
1713 }
1714 }
1715
1716 #ifndef CONFIG_USER_ONLY
1717 /*
1718 * This code generates a "coprocessor unusable" exception if CP0 is not
1719 * available, and, if that is not the case, generates a "reserved instruction"
1720 * exception if the Config5 MT bit is NOT set. This is needed for availability
1721 * control of some of MT ASE instructions.
1722 */
1723 static inline void check_cp0_mt(DisasContext *ctx)
1724 {
1725 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
1726 generate_exception_end(ctx, EXCP_CpU);
1727 } else {
1728 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
1729 gen_reserved_instruction(ctx);
1730 }
1731 }
1732 }
1733 #endif
1734
1735 /*
1736 * This code generates a "reserved instruction" exception if the
1737 * Config5 NMS bit is set.
1738 */
1739 static inline void check_nms(DisasContext *ctx)
1740 {
1741 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) {
1742 gen_reserved_instruction(ctx);
1743 }
1744 }
1745
1746 /*
1747 * This code generates a "reserved instruction" exception if the
1748 * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL,
1749 * Config2 TL, and Config5 L2C are unset.
1750 */
1751 static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
1752 {
1753 if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&
1754 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&
1755 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
1756 !(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
1757 !(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
1758 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) {
1759 gen_reserved_instruction(ctx);
1760 }
1761 }
1762
1763 /*
1764 * This code generates a "reserved instruction" exception if the
1765 * Config5 EVA bit is NOT set.
1766 */
1767 static inline void check_eva(DisasContext *ctx)
1768 {
1769 if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) {
1770 gen_reserved_instruction(ctx);
1771 }
1772 }
1773
1774
1775 /*
1776 * Define small wrappers for gen_load_fpr* so that we have a uniform
1777 * calling interface for 32 and 64-bit FPRs. No sense in changing
1778 * all callers for gen_load_fpr32 when we need the CTX parameter for
1779 * this one use.
1780 */
1781 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y)
1782 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
1783 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \
1784 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
1785 int ft, int fs, int cc) \
1786 { \
1787 TCGv_i##bits fp0 = tcg_temp_new_i##bits(); \
1788 TCGv_i##bits fp1 = tcg_temp_new_i##bits(); \
1789 switch (ifmt) { \
1790 case FMT_PS: \
1791 check_ps(ctx); \
1792 break; \
1793 case FMT_D: \
1794 if (abs) { \
1795 check_cop1x(ctx); \
1796 } \
1797 check_cp1_registers(ctx, fs | ft); \
1798 break; \
1799 case FMT_S: \
1800 if (abs) { \
1801 check_cop1x(ctx); \
1802 } \
1803 break; \
1804 } \
1805 gen_ldcmp_fpr##bits(ctx, fp0, fs); \
1806 gen_ldcmp_fpr##bits(ctx, fp1, ft); \
1807 switch (n) { \
1808 case 0: \
1809 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \
1810 break; \
1811 case 1: \
1812 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); \
1813 break; \
1814 case 2: \
1815 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); \
1816 break; \
1817 case 3: \
1818 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); \
1819 break; \
1820 case 4: \
1821 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); \
1822 break; \
1823 case 5: \
1824 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); \
1825 break; \
1826 case 6: \
1827 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); \
1828 break; \
1829 case 7: \
1830 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); \
1831 break; \
1832 case 8: \
1833 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); \
1834 break; \
1835 case 9: \
1836 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); \
1837 break; \
1838 case 10: \
1839 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); \
1840 break; \
1841 case 11: \
1842 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); \
1843 break; \
1844 case 12: \
1845 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); \
1846 break; \
1847 case 13: \
1848 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); \
1849 break; \
1850 case 14: \
1851 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); \
1852 break; \
1853 case 15: \
1854 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); \
1855 break; \
1856 default: \
1857 abort(); \
1858 } \
1859 tcg_temp_free_i##bits(fp0); \
1860 tcg_temp_free_i##bits(fp1); \
1861 }
1862
1863 FOP_CONDS(, 0, d, FMT_D, 64)
1864 FOP_CONDS(abs, 1, d, FMT_D, 64)
1865 FOP_CONDS(, 0, s, FMT_S, 32)
1866 FOP_CONDS(abs, 1, s, FMT_S, 32)
1867 FOP_CONDS(, 0, ps, FMT_PS, 64)
1868 FOP_CONDS(abs, 1, ps, FMT_PS, 64)
1869 #undef FOP_CONDS
1870
1871 #define FOP_CONDNS(fmt, ifmt, bits, STORE) \
1872 static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \
1873 int ft, int fs, int fd) \
1874 { \
1875 TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \
1876 TCGv_i ## bits fp1 = tcg_temp_new_i ## bits(); \
1877 if (ifmt == FMT_D) { \
1878 check_cp1_registers(ctx, fs | ft | fd); \
1879 } \
1880 gen_ldcmp_fpr ## bits(ctx, fp0, fs); \
1881 gen_ldcmp_fpr ## bits(ctx, fp1, ft); \
1882 switch (n) { \
1883 case 0: \
1884 gen_helper_r6_cmp_ ## fmt ## _af(fp0, cpu_env, fp0, fp1); \
1885 break; \
1886 case 1: \
1887 gen_helper_r6_cmp_ ## fmt ## _un(fp0, cpu_env, fp0, fp1); \
1888 break; \
1889 case 2: \
1890 gen_helper_r6_cmp_ ## fmt ## _eq(fp0, cpu_env, fp0, fp1); \
1891 break; \
1892 case 3: \
1893 gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, cpu_env, fp0, fp1); \
1894 break; \
1895 case 4: \
1896 gen_helper_r6_cmp_ ## fmt ## _lt(fp0, cpu_env, fp0, fp1); \
1897 break; \
1898 case 5: \
1899 gen_helper_r6_cmp_ ## fmt ## _ult(fp0, cpu_env, fp0, fp1); \
1900 break; \
1901 case 6: \
1902 gen_helper_r6_cmp_ ## fmt ## _le(fp0, cpu_env, fp0, fp1); \
1903 break; \
1904 case 7: \
1905 gen_helper_r6_cmp_ ## fmt ## _ule(fp0, cpu_env, fp0, fp1); \
1906 break; \
1907 case 8: \
1908 gen_helper_r6_cmp_ ## fmt ## _saf(fp0, cpu_env, fp0, fp1); \
1909 break; \
1910 case 9: \
1911 gen_helper_r6_cmp_ ## fmt ## _sun(fp0, cpu_env, fp0, fp1); \
1912 break; \
1913 case 10: \
1914 gen_helper_r6_cmp_ ## fmt ## _seq(fp0, cpu_env, fp0, fp1); \
1915 break; \
1916 case 11: \
1917 gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, cpu_env, fp0, fp1); \
1918 break; \
1919 case 12: \
1920 gen_helper_r6_cmp_ ## fmt ## _slt(fp0, cpu_env, fp0, fp1); \
1921 break; \
1922 case 13: \
1923 gen_helper_r6_cmp_ ## fmt ## _sult(fp0, cpu_env, fp0, fp1); \
1924 break; \
1925 case 14: \
1926 gen_helper_r6_cmp_ ## fmt ## _sle(fp0, cpu_env, fp0, fp1); \
1927 break; \
1928 case 15: \
1929 gen_helper_r6_cmp_ ## fmt ## _sule(fp0, cpu_env, fp0, fp1); \
1930 break; \
1931 case 17: \
1932 gen_helper_r6_cmp_ ## fmt ## _or(fp0, cpu_env, fp0, fp1); \
1933 break; \
1934 case 18: \
1935 gen_helper_r6_cmp_ ## fmt ## _une(fp0, cpu_env, fp0, fp1); \
1936 break; \
1937 case 19: \
1938 gen_helper_r6_cmp_ ## fmt ## _ne(fp0, cpu_env, fp0, fp1); \
1939 break; \
1940 case 25: \
1941 gen_helper_r6_cmp_ ## fmt ## _sor(fp0, cpu_env, fp0, fp1); \
1942 break; \
1943 case 26: \
1944 gen_helper_r6_cmp_ ## fmt ## _sune(fp0, cpu_env, fp0, fp1); \
1945 break; \
1946 case 27: \
1947 gen_helper_r6_cmp_ ## fmt ## _sne(fp0, cpu_env, fp0, fp1); \
1948 break; \
1949 default: \
1950 abort(); \
1951 } \
1952 STORE; \
1953 tcg_temp_free_i ## bits(fp0); \
1954 tcg_temp_free_i ## bits(fp1); \
1955 }
1956
1957 FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd))
1958 FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
1959 #undef FOP_CONDNS
1960 #undef gen_ldcmp_fpr32
1961 #undef gen_ldcmp_fpr64
1962
1963 /* load/store instructions. */
1964 #ifdef CONFIG_USER_ONLY
1965 #define OP_LD_ATOMIC(insn, fname) \
1966 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
1967 DisasContext *ctx) \
1968 { \
1969 TCGv t0 = tcg_temp_new(); \
1970 tcg_gen_mov_tl(t0, arg1); \
1971 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
1972 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
1973 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
1974 tcg_temp_free(t0); \
1975 }
1976 #else
1977 #define OP_LD_ATOMIC(insn, fname) \
1978 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
1979 DisasContext *ctx) \
1980 { \
1981 gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); \
1982 }
1983 #endif
1984 OP_LD_ATOMIC(ll, ld32s);
1985 #if defined(TARGET_MIPS64)
1986 OP_LD_ATOMIC(lld, ld64);
1987 #endif
1988 #undef OP_LD_ATOMIC
1989
1990 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
1991 {
1992 if (base == 0) {
1993 tcg_gen_movi_tl(addr, offset);
1994 } else if (offset == 0) {
1995 gen_load_gpr(addr, base);
1996 } else {
1997 tcg_gen_movi_tl(addr, offset);
1998 gen_op_addr_add(ctx, addr, cpu_gpr[base], addr);
1999 }
2000 }
2001
2002 static target_ulong pc_relative_pc(DisasContext *ctx)
2003 {
2004 target_ulong pc = ctx->base.pc_next;
2005
2006 if (ctx->hflags & MIPS_HFLAG_BMASK) {
2007 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4;
2008
2009 pc -= branch_bytes;
2010 }
2011
2012 pc &= ~(target_ulong)3;
2013 return pc;
2014 }
2015
2016 /* Load */
2017 static void gen_ld(DisasContext *ctx, uint32_t opc,
2018 int rt, int base, int offset)
2019 {
2020 TCGv t0, t1, t2;
2021 int mem_idx = ctx->mem_idx;
2022
2023 if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F |
2024 INSN_LOONGSON3A)) {
2025 /*
2026 * Loongson CPU uses a load to zero register for prefetch.
2027 * We emulate it as a NOP. On other CPU we must perform the
2028 * actual memory access.
2029 */
2030 return;
2031 }
2032
2033 t0 = tcg_temp_new();
2034 gen_base_offset_addr(ctx, t0, base, offset);
2035
2036 switch (opc) {
2037 #if defined(TARGET_MIPS64)
2038 case OPC_LWU:
2039 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL |
2040 ctx->default_tcg_memop_mask);
2041 gen_store_gpr(t0, rt);
2042 break;
2043 case OPC_LD:
2044 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ |
2045 ctx->default_tcg_memop_mask);
2046 gen_store_gpr(t0, rt);
2047 break;
2048 case OPC_LLD:
2049 case R6_OPC_LLD:
2050 op_ld_lld(t0, t0, mem_idx, ctx);
2051 gen_store_gpr(t0, rt);
2052 break;
2053 case OPC_LDL:
2054 t1 = tcg_temp_new();
2055 /*
2056 * Do a byte access to possibly trigger a page
2057 * fault with the unaligned address.
2058 */
2059 tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
2060 tcg_gen_andi_tl(t1, t0, 7);
2061 if (!cpu_is_bigendian(ctx)) {
2062 tcg_gen_xori_tl(t1, t1, 7);
2063 }
2064 tcg_gen_shli_tl(t1, t1, 3);
2065 tcg_gen_andi_tl(t0, t0, ~7);
2066 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
2067 tcg_gen_shl_tl(t0, t0, t1);
2068 t2 = tcg_const_tl(-1);
2069 tcg_gen_shl_tl(t2, t2, t1);
2070 gen_load_gpr(t1, rt);
2071 tcg_gen_andc_tl(t1, t1, t2);
2072 tcg_temp_free(t2);
2073 tcg_gen_or_tl(t0, t0, t1);
2074 tcg_temp_free(t1);
2075 gen_store_gpr(t0, rt);
2076 break;
2077 case OPC_LDR:
2078 t1 = tcg_temp_new();
2079 /*
2080 * Do a byte access to possibly trigger a page
2081 * fault with the unaligned address.
2082 */
2083 tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
2084 tcg_gen_andi_tl(t1, t0, 7);
2085 if (cpu_is_bigendian(ctx)) {
2086 tcg_gen_xori_tl(t1, t1, 7);
2087 }
2088 tcg_gen_shli_tl(t1, t1, 3);
2089 tcg_gen_andi_tl(t0, t0, ~7);
2090 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
2091 tcg_gen_shr_tl(t0, t0, t1);
2092 tcg_gen_xori_tl(t1, t1, 63);
2093 t2 = tcg_const_tl(0xfffffffffffffffeull);
2094 tcg_gen_shl_tl(t2, t2, t1);
2095 gen_load_gpr(t1, rt);
2096 tcg_gen_and_tl(t1, t1, t2);
2097 tcg_temp_free(t2);
2098 tcg_gen_or_tl(t0, t0, t1);
2099 tcg_temp_free(t1);
2100 gen_store_gpr(t0, rt);
2101 break;
2102 case OPC_LDPC:
2103 t1 = tcg_const_tl(pc_relative_pc(ctx));
2104 gen_op_addr_add(ctx, t0, t0, t1);
2105 tcg_temp_free(t1);
2106 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
2107 gen_store_gpr(t0, rt);
2108 break;
2109 #endif
2110 case OPC_LWPC:
2111 t1 = tcg_const_tl(pc_relative_pc(ctx));
2112 gen_op_addr_add(ctx, t0, t0, t1);
2113 tcg_temp_free(t1);
2114 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL);
2115 gen_store_gpr(t0, rt);
2116 break;
2117 case OPC_LWE:
2118 mem_idx = MIPS_HFLAG_UM;
2119 /* fall through */
2120 case OPC_LW:
2121 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL |
2122 ctx->default_tcg_memop_mask);
2123 gen_store_gpr(t0, rt);
2124 break;
2125 case OPC_LHE:
2126 mem_idx = MIPS_HFLAG_UM;
2127 /* fall through */
2128 case OPC_LH:
2129 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESW |
2130 ctx->default_tcg_memop_mask);
2131 gen_store_gpr(t0, rt);
2132 break;
2133 case OPC_LHUE:
2134 mem_idx = MIPS_HFLAG_UM;
2135 /* fall through */
2136 case OPC_LHU:
2137 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUW |
2138 ctx->default_tcg_memop_mask);
2139 gen_store_gpr(t0, rt);
2140 break;
2141 case OPC_LBE:
2142 mem_idx = MIPS_HFLAG_UM;
2143 /* fall through */
2144 case OPC_LB:
2145 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_SB);
2146 gen_store_gpr(t0, rt);
2147 break;
2148 case OPC_LBUE:
2149 mem_idx = MIPS_HFLAG_UM;
2150 /* fall through */
2151 case OPC_LBU:
2152 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_UB);
2153 gen_store_gpr(t0, rt);
2154 break;
2155 case OPC_LWLE:
2156 mem_idx = MIPS_HFLAG_UM;
2157 /* fall through */
2158 case OPC_LWL:
2159 t1 = tcg_temp_new();
2160 /*
2161 * Do a byte access to possibly trigger a page
2162 * fault with the unaligned address.
2163 */
2164 tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
2165 tcg_gen_andi_tl(t1, t0, 3);
2166 if (!cpu_is_bigendian(ctx)) {
2167 tcg_gen_xori_tl(t1, t1, 3);
2168 }
2169 tcg_gen_shli_tl(t1, t1, 3);
2170 tcg_gen_andi_tl(t0, t0, ~3);
2171 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL);
2172 tcg_gen_shl_tl(t0, t0, t1);
2173 t2 = tcg_const_tl(-1);
2174 tcg_gen_shl_tl(t2, t2, t1);
2175 gen_load_gpr(t1, rt);
2176 tcg_gen_andc_tl(t1, t1, t2);
2177 tcg_temp_free(t2);
2178 tcg_gen_or_tl(t0, t0, t1);
2179 tcg_temp_free(t1);
2180 tcg_gen_ext32s_tl(t0, t0);
2181 gen_store_gpr(t0, rt);
2182 break;
2183 case OPC_LWRE:
2184 mem_idx = MIPS_HFLAG_UM;
2185 /* fall through */
2186 case OPC_LWR:
2187 t1 = tcg_temp_new();
2188 /*
2189 * Do a byte access to possibly trigger a page
2190 * fault with the unaligned address.
2191 */
2192 tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
2193 tcg_gen_andi_tl(t1, t0, 3);
2194 if (cpu_is_bigendian(ctx)) {
2195 tcg_gen_xori_tl(t1, t1, 3);
2196 }
2197 tcg_gen_shli_tl(t1, t1, 3);
2198 tcg_gen_andi_tl(t0, t0, ~3);
2199 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL);
2200 tcg_gen_shr_tl(t0, t0, t1);
2201 tcg_gen_xori_tl(t1, t1, 31);
2202 t2 = tcg_const_tl(0xfffffffeull);
2203 tcg_gen_shl_tl(t2, t2, t1);
2204 gen_load_gpr(t1, rt);
2205 tcg_gen_and_tl(t1, t1, t2);
2206 tcg_temp_free(t2);
2207 tcg_gen_or_tl(t0, t0, t1);
2208 tcg_temp_free(t1);
2209 tcg_gen_ext32s_tl(t0, t0);
2210 gen_store_gpr(t0, rt);
2211 break;
2212 case OPC_LLE:
2213 mem_idx = MIPS_HFLAG_UM;
2214 /* fall through */
2215 case OPC_LL:
2216 case R6_OPC_LL:
2217 op_ld_ll(t0, t0, mem_idx, ctx);
2218 gen_store_gpr(t0, rt);
2219 break;
2220 }
2221 tcg_temp_free(t0);
2222 }
2223
2224 /* Store */
2225 static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
2226 int base, int offset)
2227 {
2228 TCGv t0 = tcg_temp_new();
2229 TCGv t1 = tcg_temp_new();
2230 int mem_idx = ctx->mem_idx;
2231
2232 gen_base_offset_addr(ctx, t0, base, offset);
2233 gen_load_gpr(t1, rt);
2234 switch (opc) {
2235 #if defined(TARGET_MIPS64)
2236 case OPC_SD:
2237 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUQ |
2238 ctx->default_tcg_memop_mask);
2239 break;
2240 case OPC_SDL:
2241 gen_helper_0e2i(sdl, t1, t0, mem_idx);
2242 break;
2243 case OPC_SDR:
2244 gen_helper_0e2i(sdr, t1, t0, mem_idx);
2245 break;
2246 #endif
2247 case OPC_SWE:
2248 mem_idx = MIPS_HFLAG_UM;
2249 /* fall through */
2250 case OPC_SW:
2251 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUL |
2252 ctx->default_tcg_memop_mask);
2253 break;
2254 case OPC_SHE:
2255 mem_idx = MIPS_HFLAG_UM;
2256 /* fall through */
2257 case OPC_SH:
2258 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUW |
2259 ctx->default_tcg_memop_mask);
2260 break;
2261 case OPC_SBE:
2262 mem_idx = MIPS_HFLAG_UM;
2263 /* fall through */
2264 case OPC_SB:
2265 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_8);
2266 break;
2267 case OPC_SWLE:
2268 mem_idx = MIPS_HFLAG_UM;
2269 /* fall through */
2270 case OPC_SWL:
2271 gen_helper_0e2i(swl, t1, t0, mem_idx);
2272 break;
2273 case OPC_SWRE:
2274 mem_idx = MIPS_HFLAG_UM;
2275 /* fall through */
2276 case OPC_SWR:
2277 gen_helper_0e2i(swr, t1, t0, mem_idx);
2278 break;
2279 }
2280 tcg_temp_free(t0);
2281 tcg_temp_free(t1);
2282 }
2283
2284
2285 /* Store conditional */
2286 static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
2287 MemOp tcg_mo, bool eva)
2288 {
2289 TCGv addr, t0, val;
2290 TCGLabel *l1 = gen_new_label();
2291 TCGLabel *done = gen_new_label();
2292
2293 t0 = tcg_temp_new();
2294 addr = tcg_temp_new();
2295 /* compare the address against that of the preceding LL */
2296 gen_base_offset_addr(ctx, addr, base, offset);
2297 tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
2298 tcg_temp_free(addr);
2299 tcg_gen_movi_tl(t0, 0);
2300 gen_store_gpr(t0, rt);
2301 tcg_gen_br(done);
2302
2303 gen_set_label(l1);
2304 /* generate cmpxchg */
2305 val = tcg_temp_new();
2306 gen_load_gpr(val, rt);
2307 tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval, val,
2308 eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo);
2309 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval);
2310 gen_store_gpr(t0, rt);
2311 tcg_temp_free(val);
2312
2313 gen_set_label(done);
2314 tcg_temp_free(t0);
2315 }
2316
2317 /* Load and store */
2318 static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
2319 TCGv t0)
2320 {
2321 /*
2322 * Don't do NOP if destination is zero: we must perform the actual
2323 * memory access.
2324 */
2325 switch (opc) {
2326 case OPC_LWC1:
2327 {
2328 TCGv_i32 fp0 = tcg_temp_new_i32();
2329 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
2330 ctx->default_tcg_memop_mask);
2331 gen_store_fpr32(ctx, fp0, ft);
2332 tcg_temp_free_i32(fp0);
2333 }
2334 break;
2335 case OPC_SWC1:
2336 {
2337 TCGv_i32 fp0 = tcg_temp_new_i32();
2338 gen_load_fpr32(ctx, fp0, ft);
2339 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
2340 ctx->default_tcg_memop_mask);
2341 tcg_temp_free_i32(fp0);
2342 }
2343 break;
2344 case OPC_LDC1:
2345 {
2346 TCGv_i64 fp0 = tcg_temp_new_i64();
2347 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ |
2348 ctx->default_tcg_memop_mask);
2349 gen_store_fpr64(ctx, fp0, ft);
2350 tcg_temp_free_i64(fp0);
2351 }
2352 break;
2353 case OPC_SDC1:
2354 {
2355 TCGv_i64 fp0 = tcg_temp_new_i64();
2356 gen_load_fpr64(ctx, fp0, ft);
2357 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ |
2358 ctx->default_tcg_memop_mask);
2359 tcg_temp_free_i64(fp0);
2360 }
2361 break;
2362 default:
2363 MIPS_INVAL("flt_ldst");
2364 gen_reserved_instruction(ctx);
2365 break;
2366 }
2367 }
2368
2369 static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
2370 int rs, int16_t imm)
2371 {
2372 TCGv t0 = tcg_temp_new();
2373
2374 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
2375 check_cp1_enabled(ctx);
2376 switch (op) {
2377 case OPC_LDC1:
2378 case OPC_SDC1:
2379 check_insn(ctx, ISA_MIPS2);
2380 /* Fallthrough */
2381 default:
2382 gen_base_offset_addr(ctx, t0, rs, imm);
2383 gen_flt_ldst(ctx, op, rt, t0);
2384 }
2385 } else {
2386 generate_exception_err(ctx, EXCP_CpU, 1);
2387 }
2388 tcg_temp_free(t0);
2389 }
2390
2391 /* Arithmetic with immediate operand */
2392 static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
2393 int rt, int rs, int imm)
2394 {
2395 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
2396
2397 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
2398 /*
2399 * If no destination, treat it as a NOP.
2400 * For addi, we must generate the overflow exception when needed.
2401 */
2402 return;
2403 }
2404 switch (opc) {
2405 case OPC_ADDI:
2406 {
2407 TCGv t0 = tcg_temp_local_new();
2408 TCGv t1 = tcg_temp_new();
2409 TCGv t2 = tcg_temp_new();
2410 TCGLabel *l1 = gen_new_label();
2411
2412 gen_load_gpr(t1, rs);
2413 tcg_gen_addi_tl(t0, t1, uimm);
2414 tcg_gen_ext32s_tl(t0, t0);
2415
2416 tcg_gen_xori_tl(t1, t1, ~uimm);
2417 tcg_gen_xori_tl(t2, t0, uimm);
2418 tcg_gen_and_tl(t1, t1, t2);
2419 tcg_temp_free(t2);
2420 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2421 tcg_temp_free(t1);
2422 /* operands of same sign, result different sign */
2423 generate_exception(ctx, EXCP_OVERFLOW);
2424 gen_set_label(l1);
2425 tcg_gen_ext32s_tl(t0, t0);
2426 gen_store_gpr(t0, rt);
2427 tcg_temp_free(t0);
2428 }
2429 break;
2430 case OPC_ADDIU:
2431 if (rs != 0) {
2432 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2433 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
2434 } else {
2435 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2436 }
2437 break;
2438 #if defined(TARGET_MIPS64)
2439 case OPC_DADDI:
2440 {
2441 TCGv t0 = tcg_temp_local_new();
2442 TCGv t1 = tcg_temp_new();
2443 TCGv t2 = tcg_temp_new();
2444 TCGLabel *l1 = gen_new_label();
2445
2446 gen_load_gpr(t1, rs);
2447 tcg_gen_addi_tl(t0, t1, uimm);
2448
2449 tcg_gen_xori_tl(t1, t1, ~uimm);
2450 tcg_gen_xori_tl(t2, t0, uimm);
2451 tcg_gen_and_tl(t1, t1, t2);
2452 tcg_temp_free(t2);
2453 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2454 tcg_temp_free(t1);
2455 /* operands of same sign, result different sign */
2456 generate_exception(ctx, EXCP_OVERFLOW);
2457 gen_set_label(l1);
2458 gen_store_gpr(t0, rt);
2459 tcg_temp_free(t0);
2460 }
2461 break;
2462 case OPC_DADDIU:
2463 if (rs != 0) {
2464 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2465 } else {
2466 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2467 }
2468 break;
2469 #endif
2470 }
2471 }
2472
2473 /* Logic with immediate operand */
2474 static void gen_logic_imm(DisasContext *ctx, uint32_t opc,
2475 int rt, int rs, int16_t imm)
2476 {
2477 target_ulong uimm;
2478
2479 if (rt == 0) {
2480 /* If no destination, treat it as a NOP. */
2481 return;
2482 }
2483 uimm = (uint16_t)imm;
2484 switch (opc) {
2485 case OPC_ANDI:
2486 if (likely(rs != 0)) {
2487 tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2488 } else {
2489 tcg_gen_movi_tl(cpu_gpr[rt], 0);
2490 }
2491 break;
2492 case OPC_ORI:
2493 if (rs != 0) {
2494 tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2495 } else {
2496 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2497 }
2498 break;
2499 case OPC_XORI:
2500 if (likely(rs != 0)) {
2501 tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2502 } else {
2503 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2504 }
2505 break;
2506 case OPC_LUI:
2507 if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) {
2508 /* OPC_AUI */
2509 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16);
2510 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
2511 } else {
2512 tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
2513 }
2514 break;
2515
2516 default:
2517 break;
2518 }
2519 }
2520
2521 /* Set on less than with immediate operand */
2522 static void gen_slt_imm(DisasContext *ctx, uint32_t opc,
2523 int rt, int rs, int16_t imm)
2524 {
2525 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
2526 TCGv t0;
2527
2528 if (rt == 0) {
2529 /* If no destination, treat it as a NOP. */
2530 return;
2531 }
2532 t0 = tcg_temp_new();
2533 gen_load_gpr(t0, rs);
2534 switch (opc) {
2535 case OPC_SLTI:
2536 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm);
2537 break;
2538 case OPC_SLTIU:
2539 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm);
2540 break;
2541 }
2542 tcg_temp_free(t0);
2543 }
2544
2545 /* Shifts with immediate operand */
2546 static void gen_shift_imm(DisasContext *ctx, uint32_t opc,
2547 int rt, int rs, int16_t imm)
2548 {
2549 target_ulong uimm = ((uint16_t)imm) & 0x1f;
2550 TCGv t0;
2551
2552 if (rt == 0) {
2553 /* If no destination, treat it as a NOP. */
2554 return;
2555 }
2556
2557 t0 = tcg_temp_new();
2558 gen_load_gpr(t0, rs);
2559 switch (opc) {
2560 case OPC_SLL:
2561 tcg_gen_shli_tl(t0, t0, uimm);
2562 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2563 break;
2564 case OPC_SRA:
2565 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
2566 break;
2567 case OPC_SRL:
2568 if (uimm != 0) {
2569 tcg_gen_ext32u_tl(t0, t0);
2570 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
2571 } else {
2572 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2573 }
2574 break;
2575 case OPC_ROTR:
2576 if (uimm != 0) {
2577 TCGv_i32 t1 = tcg_temp_new_i32();
2578
2579 tcg_gen_trunc_tl_i32(t1, t0);
2580 tcg_gen_rotri_i32(t1, t1, uimm);
2581 tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
2582 tcg_temp_free_i32(t1);
2583 } else {
2584 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2585 }
2586 break;
2587 #if defined(TARGET_MIPS64)
2588 case OPC_DSLL:
2589 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm);
2590 break;
2591 case OPC_DSRA:
2592 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
2593 break;
2594 case OPC_DSRL:
2595 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
2596 break;
2597 case OPC_DROTR:
2598 if (uimm != 0) {
2599 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
2600 } else {
2601 tcg_gen_mov_tl(cpu_gpr[rt], t0);
2602 }
2603 break;
2604 case OPC_DSLL32:
2605 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32);
2606 break;
2607 case OPC_DSRA32:
2608 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32);
2609 break;
2610 case OPC_DSRL32:
2611 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
2612 break;
2613 case OPC_DROTR32:
2614 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32);
2615 break;
2616 #endif
2617 }
2618 tcg_temp_free(t0);
2619 }
2620
2621 /* Arithmetic */
2622 static void gen_arith(DisasContext *ctx, uint32_t opc,
2623 int rd, int rs, int rt)
2624 {
2625 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
2626 && opc != OPC_DADD && opc != OPC_DSUB) {
2627 /*
2628 * If no destination, treat it as a NOP.
2629 * For add & sub, we must generate the overflow exception when needed.
2630 */
2631 return;
2632 }
2633
2634 switch (opc) {
2635 case OPC_ADD:
2636 {
2637 TCGv t0 = tcg_temp_local_new();
2638 TCGv t1 = tcg_temp_new();
2639 TCGv t2 = tcg_temp_new();
2640 TCGLabel *l1 = gen_new_label();
2641
2642 gen_load_gpr(t1, rs);
2643 gen_load_gpr(t2, rt);
2644 tcg_gen_add_tl(t0, t1, t2);
2645 tcg_gen_ext32s_tl(t0, t0);
2646 tcg_gen_xor_tl(t1, t1, t2);
2647 tcg_gen_xor_tl(t2, t0, t2);
2648 tcg_gen_andc_tl(t1, t2, t1);
2649 tcg_temp_free(t2);
2650 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2651 tcg_temp_free(t1);
2652 /* operands of same sign, result different sign */
2653 generate_exception(ctx, EXCP_OVERFLOW);
2654 gen_set_label(l1);
2655 gen_store_gpr(t0, rd);
2656 tcg_temp_free(t0);
2657 }
2658 break;
2659 case OPC_ADDU:
2660 if (rs != 0 && rt != 0) {
2661 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2662 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2663 } else if (rs == 0 && rt != 0) {
2664 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2665 } else if (rs != 0 && rt == 0) {
2666 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2667 } else {
2668 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2669 }
2670 break;
2671 case OPC_SUB:
2672 {
2673 TCGv t0 = tcg_temp_local_new();
2674 TCGv t1 = tcg_temp_new();
2675 TCGv t2 = tcg_temp_new();
2676 TCGLabel *l1 = gen_new_label();
2677
2678 gen_load_gpr(t1, rs);
2679 gen_load_gpr(t2, rt);
2680 tcg_gen_sub_tl(t0, t1, t2);
2681 tcg_gen_ext32s_tl(t0, t0);
2682 tcg_gen_xor_tl(t2, t1, t2);
2683 tcg_gen_xor_tl(t1, t0, t1);
2684 tcg_gen_and_tl(t1, t1, t2);
2685 tcg_temp_free(t2);
2686 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2687 tcg_temp_free(t1);
2688 /*
2689 * operands of different sign, first operand and the result
2690 * of different sign
2691 */
2692 generate_exception(ctx, EXCP_OVERFLOW);
2693 gen_set_label(l1);
2694 gen_store_gpr(t0, rd);
2695 tcg_temp_free(t0);
2696 }
2697 break;
2698 case OPC_SUBU:
2699 if (rs != 0 && rt != 0) {
2700 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2701 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2702 } else if (rs == 0 && rt != 0) {
2703 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
2704 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2705 } else if (rs != 0 && rt == 0) {
2706 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2707 } else {
2708 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2709 }
2710 break;
2711 #if defined(TARGET_MIPS64)
2712 case OPC_DADD:
2713 {
2714 TCGv t0 = tcg_temp_local_new();
2715 TCGv t1 = tcg_temp_new();
2716 TCGv t2 = tcg_temp_new();
2717 TCGLabel *l1 = gen_new_label();
2718
2719 gen_load_gpr(t1, rs);
2720 gen_load_gpr(t2, rt);
2721 tcg_gen_add_tl(t0, t1, t2);
2722 tcg_gen_xor_tl(t1, t1, t2);
2723 tcg_gen_xor_tl(t2, t0, t2);
2724 tcg_gen_andc_tl(t1, t2, t1);
2725 tcg_temp_free(t2);
2726 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2727 tcg_temp_free(t1);
2728 /* operands of same sign, result different sign */
2729 generate_exception(ctx, EXCP_OVERFLOW);
2730 gen_set_label(l1);
2731 gen_store_gpr(t0, rd);
2732 tcg_temp_free(t0);
2733 }
2734 break;
2735 case OPC_DADDU:
2736 if (rs != 0 && rt != 0) {
2737 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2738 } else if (rs == 0 && rt != 0) {
2739 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2740 } else if (rs != 0 && rt == 0) {
2741 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2742 } else {
2743 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2744 }
2745 break;
2746 case OPC_DSUB:
2747 {
2748 TCGv t0 = tcg_temp_local_new();
2749 TCGv t1 = tcg_temp_new();
2750 TCGv t2 = tcg_temp_new();
2751 TCGLabel *l1 = gen_new_label();
2752
2753 gen_load_gpr(t1, rs);
2754 gen_load_gpr(t2, rt);
2755 tcg_gen_sub_tl(t0, t1, t2);
2756 tcg_gen_xor_tl(t2, t1, t2);
2757 tcg_gen_xor_tl(t1, t0, t1);
2758 tcg_gen_and_tl(t1, t1, t2);
2759 tcg_temp_free(t2);
2760 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2761 tcg_temp_free(t1);
2762 /*
2763 * Operands of different sign, first operand and result different
2764 * sign.
2765 */
2766 generate_exception(ctx, EXCP_OVERFLOW);
2767 gen_set_label(l1);
2768 gen_store_gpr(t0, rd);
2769 tcg_temp_free(t0);
2770 }
2771 break;
2772 case OPC_DSUBU:
2773 if (rs != 0 && rt != 0) {
2774 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2775 } else if (rs == 0 && rt != 0) {
2776 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
2777 } else if (rs != 0 && rt == 0) {
2778 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2779 } else {
2780 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2781 }
2782 break;
2783 #endif
2784 case OPC_MUL:
2785 if (likely(rs != 0 && rt != 0)) {
2786 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2787 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2788 } else {
2789 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2790 }
2791 break;
2792 }
2793 }
2794
2795 /* Conditional move */
2796 static void gen_cond_move(DisasContext *ctx, uint32_t opc,
2797 int rd, int rs, int rt)
2798 {
2799 TCGv t0, t1, t2;
2800
2801 if (rd == 0) {
2802 /* If no destination, treat it as a NOP. */
2803 return;
2804 }
2805
2806 t0 = tcg_temp_new();
2807 gen_load_gpr(t0, rt);
2808 t1 = tcg_const_tl(0);
2809 t2 = tcg_temp_new();
2810 gen_load_gpr(t2, rs);
2811 switch (opc) {
2812 case OPC_MOVN:
2813 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
2814 break;
2815 case OPC_MOVZ:
2816 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
2817 break;
2818 case OPC_SELNEZ:
2819 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1);
2820 break;
2821 case OPC_SELEQZ:
2822 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1);
2823 break;
2824 }
2825 tcg_temp_free(t2);
2826 tcg_temp_free(t1);
2827 tcg_temp_free(t0);
2828 }
2829
2830 /* Logic */
2831 static void gen_logic(DisasContext *ctx, uint32_t opc,
2832 int rd, int rs, int rt)
2833 {
2834 if (rd == 0) {
2835 /* If no destination, treat it as a NOP. */
2836 return;
2837 }
2838
2839 switch (opc) {
2840 case OPC_AND:
2841 if (likely(rs != 0 && rt != 0)) {
2842 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2843 } else {
2844 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2845 }
2846 break;
2847 case OPC_NOR:
2848 if (rs != 0 && rt != 0) {
2849 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2850 } else if (rs == 0 && rt != 0) {
2851 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]);
2852 } else if (rs != 0 && rt == 0) {
2853 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]);
2854 } else {
2855 tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0));
2856 }
2857 break;
2858 case OPC_OR:
2859 if (likely(rs != 0 && rt != 0)) {
2860 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2861 } else if (rs == 0 && rt != 0) {
2862 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2863 } else if (rs != 0 && rt == 0) {
2864 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2865 } else {
2866 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2867 }
2868 break;
2869 case OPC_XOR:
2870 if (likely(rs != 0 && rt != 0)) {
2871 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2872 } else if (rs == 0 && rt != 0) {
2873 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2874 } else if (rs != 0 && rt == 0) {
2875 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2876 } else {
2877 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2878 }
2879 break;
2880 }
2881 }
2882
2883 /* Set on lower than */
2884 static void gen_slt(DisasContext *ctx, uint32_t opc,
2885 int rd, int rs, int rt)
2886 {
2887 TCGv t0, t1;
2888
2889 if (rd == 0) {
2890 /* If no destination, treat it as a NOP. */
2891 return;
2892 }
2893
2894 t0 = tcg_temp_new();
2895 t1 = tcg_temp_new();
2896 gen_load_gpr(t0, rs);
2897 gen_load_gpr(t1, rt);
2898 switch (opc) {
2899 case OPC_SLT:
2900 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1);
2901 break;
2902 case OPC_SLTU:
2903 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1);
2904 break;
2905 }
2906 tcg_temp_free(t0);
2907 tcg_temp_free(t1);
2908 }
2909
2910 /* Shifts */
2911 static void gen_shift(DisasContext *ctx, uint32_t opc,
2912 int rd, int rs, int rt)
2913 {
2914 TCGv t0, t1;
2915
2916 if (rd == 0) {
2917 /*
2918 * If no destination, treat it as a NOP.
2919 * For add & sub, we must generate the overflow exception when needed.
2920 */
2921 return;
2922 }
2923
2924 t0 = tcg_temp_new();
2925 t1 = tcg_temp_new();
2926 gen_load_gpr(t0, rs);
2927 gen_load_gpr(t1, rt);
2928 switch (opc) {
2929 case OPC_SLLV:
2930 tcg_gen_andi_tl(t0, t0, 0x1f);
2931 tcg_gen_shl_tl(t0, t1, t0);
2932 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
2933 break;
2934 case OPC_SRAV:
2935 tcg_gen_andi_tl(t0, t0, 0x1f);
2936 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
2937 break;
2938 case OPC_SRLV:
2939 tcg_gen_ext32u_tl(t1, t1);
2940 tcg_gen_andi_tl(t0, t0, 0x1f);
2941 tcg_gen_shr_tl(t0, t1, t0);
2942 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
2943 break;
2944 case OPC_ROTRV:
2945 {
2946 TCGv_i32 t2 = tcg_temp_new_i32();
2947 TCGv_i32 t3 = tcg_temp_new_i32();
2948
2949 tcg_gen_trunc_tl_i32(t2, t0);
2950 tcg_gen_trunc_tl_i32(t3, t1);
2951 tcg_gen_andi_i32(t2, t2, 0x1f);
2952 tcg_gen_rotr_i32(t2, t3, t2);
2953 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
2954 tcg_temp_free_i32(t2);
2955 tcg_temp_free_i32(t3);
2956 }
2957 break;
2958 #if defined(TARGET_MIPS64)
2959 case OPC_DSLLV:
2960 tcg_gen_andi_tl(t0, t0, 0x3f);
2961 tcg_gen_shl_tl(cpu_gpr[rd], t1, t0);
2962 break;
2963 case OPC_DSRAV:
2964 tcg_gen_andi_tl(t0, t0, 0x3f);
2965 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
2966 break;
2967 case OPC_DSRLV:
2968 tcg_gen_andi_tl(t0, t0, 0x3f);
2969 tcg_gen_shr_tl(cpu_gpr[rd], t1, t0);
2970 break;
2971 case OPC_DROTRV:
2972 tcg_gen_andi_tl(t0, t0, 0x3f);
2973 tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0);
2974 break;
2975 #endif
2976 }
2977 tcg_temp_free(t0);
2978 tcg_temp_free(t1);
2979 }
2980
2981 /* Arithmetic on HI/LO registers */
2982 static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
2983 {
2984 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
2985 /* Treat as NOP. */
2986 return;
2987 }
2988
2989 if (acc != 0) {
2990 check_dsp(ctx);
2991 }
2992
2993 switch (opc) {
2994 case OPC_MFHI:
2995 #if defined(TARGET_MIPS64)
2996 if (acc != 0) {
2997 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]);
2998 } else
2999 #endif
3000 {
3001 tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]);
3002 }
3003 break;
3004 case OPC_MFLO:
3005 #if defined(TARGET_MIPS64)
3006 if (acc != 0) {
3007 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]);
3008 } else
3009 #endif
3010 {
3011 tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]);
3012 }
3013 break;
3014 case OPC_MTHI:
3015 if (reg != 0) {
3016 #if defined(TARGET_MIPS64)
3017 if (acc != 0) {
3018 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]);
3019 } else
3020 #endif
3021 {
3022 tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]);
3023 }
3024 } else {
3025 tcg_gen_movi_tl(cpu_HI[acc], 0);
3026 }
3027 break;
3028 case OPC_MTLO:
3029 if (reg != 0) {
3030 #if defined(TARGET_MIPS64)
3031 if (acc != 0) {
3032 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]);
3033 } else
3034 #endif
3035 {
3036 tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]);
3037 }
3038 } else {
3039 tcg_gen_movi_tl(cpu_LO[acc], 0);
3040 }
3041 break;
3042 }
3043 }
3044
3045 static inline void gen_r6_ld(target_long addr, int reg, int memidx,
3046 MemOp memop)
3047 {
3048 TCGv t0 = tcg_const_tl(addr);
3049 tcg_gen_qemu_ld_tl(t0, t0, memidx, memop);
3050 gen_store_gpr(t0, reg);
3051 tcg_temp_free(t0);
3052 }
3053
3054 static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
3055 int rs)
3056 {
3057 target_long offset;
3058 target_long addr;
3059
3060 switch (MASK_OPC_PCREL_TOP2BITS(opc)) {
3061 case OPC_ADDIUPC:
3062 if (rs != 0) {
3063 offset = sextract32(ctx->opcode << 2, 0, 21);
3064 addr = addr_add(ctx, pc, offset);
3065 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3066 }
3067 break;
3068 case R6_OPC_LWPC:
3069 offset = sextract32(ctx->opcode << 2, 0, 21);
3070 addr = addr_add(ctx, pc, offset);
3071 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL);
3072 break;
3073 #if defined(TARGET_MIPS64)
3074 case OPC_LWUPC:
3075 check_mips_64(ctx);
3076 offset = sextract32(ctx->opcode << 2, 0, 21);
3077 addr = addr_add(ctx, pc, offset);
3078 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL);
3079 break;
3080 #endif
3081 default:
3082 switch (MASK_OPC_PCREL_TOP5BITS(opc)) {
3083 case OPC_AUIPC:
3084 if (rs != 0) {
3085 offset = sextract32(ctx->opcode, 0, 16) << 16;
3086 addr = addr_add(ctx, pc, offset);
3087 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3088 }
3089 break;
3090 case OPC_ALUIPC:
3091 if (rs != 0) {
3092 offset = sextract32(ctx->opcode, 0, 16) << 16;
3093 addr = ~0xFFFF & addr_add(ctx, pc, offset);
3094 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3095 }
3096 break;
3097 #if defined(TARGET_MIPS64)
3098 case R6_OPC_LDPC: /* bits 16 and 17 are part of immediate */
3099 case R6_OPC_LDPC + (1 << 16):
3100 case R6_OPC_LDPC + (2 << 16):
3101 case R6_OPC_LDPC + (3 << 16):
3102 check_mips_64(ctx);
3103 offset = sextract32(ctx->opcode << 3, 0, 21);
3104 addr = addr_add(ctx, (pc & ~0x7), offset);
3105 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUQ);
3106 break;
3107 #endif
3108 default:
3109 MIPS_INVAL("OPC_PCREL");
3110 gen_reserved_instruction(ctx);
3111 break;
3112 }
3113 break;
3114 }
3115 }
3116
3117 static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
3118 {
3119 TCGv t0, t1;
3120
3121 if (rd == 0) {
3122 /* Treat as NOP. */
3123 return;
3124 }
3125
3126 t0 = tcg_temp_new();
3127 t1 = tcg_temp_new();
3128
3129 gen_load_gpr(t0, rs);
3130 gen_load_gpr(t1, rt);
3131
3132 switch (opc) {
3133 case R6_OPC_DIV:
3134 {
3135 TCGv t2 = tcg_temp_new();
3136 TCGv t3 = tcg_temp_new();
3137 tcg_gen_ext32s_tl(t0, t0);
3138 tcg_gen_ext32s_tl(t1, t1);
3139 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3140 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3141 tcg_gen_and_tl(t2, t2, t3);
3142 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3143 tcg_gen_or_tl(t2, t2, t3);
3144 tcg_gen_movi_tl(t3, 0);
3145 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3146 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3147 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3148 tcg_temp_free(t3);
3149 tcg_temp_free(t2);
3150 }
3151 break;
3152 case R6_OPC_MOD:
3153 {
3154 TCGv t2 = tcg_temp_new();
3155 TCGv t3 = tcg_temp_new();
3156 tcg_gen_ext32s_tl(t0, t0);
3157 tcg_gen_ext32s_tl(t1, t1);
3158 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3159 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3160 tcg_gen_and_tl(t2, t2, t3);
3161 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3162 tcg_gen_or_tl(t2, t2, t3);
3163 tcg_gen_movi_tl(t3, 0);
3164 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3165 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3166 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3167 tcg_temp_free(t3);
3168 tcg_temp_free(t2);
3169 }
3170 break;
3171 case R6_OPC_DIVU:
3172 {
3173 TCGv t2 = tcg_const_tl(0);
3174 TCGv t3 = tcg_const_tl(1);
3175 tcg_gen_ext32u_tl(t0, t0);
3176 tcg_gen_ext32u_tl(t1, t1);
3177 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3178 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3179 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3180 tcg_temp_free(t3);
3181 tcg_temp_free(t2);
3182 }
3183 break;
3184 case R6_OPC_MODU:
3185 {
3186 TCGv t2 = tcg_const_tl(0);
3187 TCGv t3 = tcg_const_tl(1);
3188 tcg_gen_ext32u_tl(t0, t0);
3189 tcg_gen_ext32u_tl(t1, t1);
3190 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3191 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3192 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3193 tcg_temp_free(t3);
3194 tcg_temp_free(t2);
3195 }
3196 break;
3197 case R6_OPC_MUL:
3198 {
3199 TCGv_i32 t2 = tcg_temp_new_i32();
3200 TCGv_i32 t3 = tcg_temp_new_i32();
3201 tcg_gen_trunc_tl_i32(t2, t0);
3202 tcg_gen_trunc_tl_i32(t3, t1);
3203 tcg_gen_mul_i32(t2, t2, t3);
3204 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3205 tcg_temp_free_i32(t2);
3206 tcg_temp_free_i32(t3);
3207 }
3208 break;
3209 case R6_OPC_MUH:
3210 {
3211 TCGv_i32 t2 = tcg_temp_new_i32();
3212 TCGv_i32 t3 = tcg_temp_new_i32();
3213 tcg_gen_trunc_tl_i32(t2, t0);
3214 tcg_gen_trunc_tl_i32(t3, t1);
3215 tcg_gen_muls2_i32(t2, t3, t2, t3);
3216 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
3217 tcg_temp_free_i32(t2);
3218 tcg_temp_free_i32(t3);
3219 }
3220 break;
3221 case R6_OPC_MULU:
3222 {
3223 TCGv_i32 t2 = tcg_temp_new_i32();
3224 TCGv_i32 t3 = tcg_temp_new_i32();
3225 tcg_gen_trunc_tl_i32(t2, t0);
3226 tcg_gen_trunc_tl_i32(t3, t1);
3227 tcg_gen_mul_i32(t2, t2, t3);
3228 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3229 tcg_temp_free_i32(t2);
3230 tcg_temp_free_i32(t3);
3231 }
3232 break;
3233 case R6_OPC_MUHU:
3234 {
3235 TCGv_i32 t2 = tcg_temp_new_i32();
3236 TCGv_i32 t3 = tcg_temp_new_i32();
3237 tcg_gen_trunc_tl_i32(t2, t0);
3238 tcg_gen_trunc_tl_i32(t3, t1);
3239 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3240 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
3241 tcg_temp_free_i32(t2);
3242 tcg_temp_free_i32(t3);
3243 }
3244 break;
3245 #if defined(TARGET_MIPS64)
3246 case R6_OPC_DDIV:
3247 {
3248 TCGv t2 = tcg_temp_new();
3249 TCGv t3 = tcg_temp_new();
3250 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3251 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3252 tcg_gen_and_tl(t2, t2, t3);
3253 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3254 tcg_gen_or_tl(t2, t2, t3);
3255 tcg_gen_movi_tl(t3, 0);
3256 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3257 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3258 tcg_temp_free(t3);
3259 tcg_temp_free(t2);
3260 }
3261 break;
3262 case R6_OPC_DMOD:
3263 {
3264 TCGv t2 = tcg_temp_new();
3265 TCGv t3 = tcg_temp_new();
3266 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3267 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3268 tcg_gen_and_tl(t2, t2, t3);
3269 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3270 tcg_gen_or_tl(t2, t2, t3);
3271 tcg_gen_movi_tl(t3, 0);
3272 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3273 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3274 tcg_temp_free(t3);
3275 tcg_temp_free(t2);
3276 }
3277 break;
3278 case R6_OPC_DDIVU:
3279 {
3280 TCGv t2 = tcg_const_tl(0);
3281 TCGv t3 = tcg_const_tl(1);
3282 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3283 tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
3284 tcg_temp_free(t3);
3285 tcg_temp_free(t2);
3286 }
3287 break;
3288 case R6_OPC_DMODU:
3289 {
3290 TCGv t2 = tcg_const_tl(0);
3291 TCGv t3 = tcg_const_tl(1);
3292 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3293 tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
3294 tcg_temp_free(t3);
3295 tcg_temp_free(t2);
3296 }
3297 break;
3298 case R6_OPC_DMUL:
3299 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
3300 break;
3301 case R6_OPC_DMUH:
3302 {
3303 TCGv t2 = tcg_temp_new();
3304 tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1);
3305 tcg_temp_free(t2);
3306 }
3307 break;
3308 case R6_OPC_DMULU:
3309 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
3310 break;
3311 case R6_OPC_DMUHU:
3312 {
3313 TCGv t2 = tcg_temp_new();
3314 tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1);
3315 tcg_temp_free(t2);
3316 }
3317 break;
3318 #endif
3319 default:
3320 MIPS_INVAL("r6 mul/div");
3321 gen_reserved_instruction(ctx);
3322 goto out;
3323 }
3324 out:
3325 tcg_temp_free(t0);
3326 tcg_temp_free(t1);
3327 }
3328
3329 #if defined(TARGET_MIPS64)
3330 static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
3331 {
3332 TCGv t0, t1;
3333
3334 t0 = tcg_temp_new();
3335 t1 = tcg_temp_new();
3336
3337 gen_load_gpr(t0, rs);
3338 gen_load_gpr(t1, rt);
3339
3340 switch (opc) {
3341 case MMI_OPC_DIV1:
3342 {
3343 TCGv t2 = tcg_temp_new();
3344 TCGv t3 = tcg_temp_new();
3345 tcg_gen_ext32s_tl(t0, t0);
3346 tcg_gen_ext32s_tl(t1, t1);
3347 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3348 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3349 tcg_gen_and_tl(t2, t2, t3);
3350 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3351 tcg_gen_or_tl(t2, t2, t3);
3352 tcg_gen_movi_tl(t3, 0);
3353 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3354 tcg_gen_div_tl(cpu_LO[1], t0, t1);
3355 tcg_gen_rem_tl(cpu_HI[1], t0, t1);
3356 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
3357 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
3358 tcg_temp_free(t3);
3359 tcg_temp_free(t2);
3360 }
3361 break;
3362 case MMI_OPC_DIVU1:
3363 {
3364 TCGv t2 = tcg_const_tl(0);
3365 TCGv t3 = tcg_const_tl(1);
3366 tcg_gen_ext32u_tl(t0, t0);
3367 tcg_gen_ext32u_tl(t1, t1);
3368 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3369 tcg_gen_divu_tl(cpu_LO[1], t0, t1);
3370 tcg_gen_remu_tl(cpu_HI[1], t0, t1);
3371 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
3372 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
3373 tcg_temp_free(t3);
3374 tcg_temp_free(t2);
3375 }
3376 break;
3377 default:
3378 MIPS_INVAL("div1 TX79");
3379 gen_reserved_instruction(ctx);
3380 goto out;
3381 }
3382 out:
3383 tcg_temp_free(t0);
3384 tcg_temp_free(t1);
3385 }
3386 #endif
3387
3388 static void gen_muldiv(DisasContext *ctx, uint32_t opc,
3389 int acc, int rs, int rt)
3390 {
3391 TCGv t0, t1;
3392
3393 t0 = tcg_temp_new();
3394 t1 = tcg_temp_new();
3395
3396 gen_load_gpr(t0, rs);
3397 gen_load_gpr(t1, rt);
3398
3399 if (acc != 0) {
3400 check_dsp(ctx);
3401 }
3402
3403 switch (opc) {
3404 case OPC_DIV:
3405 {
3406 TCGv t2 = tcg_temp_new();
3407 TCGv t3 = tcg_temp_new();
3408 tcg_gen_ext32s_tl(t0, t0);
3409 tcg_gen_ext32s_tl(t1, t1);
3410 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3411 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3412 tcg_gen_and_tl(t2, t2, t3);
3413 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3414 tcg_gen_or_tl(t2, t2, t3);
3415 tcg_gen_movi_tl(t3, 0);
3416 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3417 tcg_gen_div_tl(cpu_LO[acc], t0, t1);
3418 tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
3419 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
3420 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
3421 tcg_temp_free(t3);
3422 tcg_temp_free(t2);
3423 }
3424 break;
3425 case OPC_DIVU:
3426 {
3427 TCGv t2 = tcg_const_tl(0);
3428 TCGv t3 = tcg_const_tl(1);
3429 tcg_gen_ext32u_tl(t0, t0);
3430 tcg_gen_ext32u_tl(t1, t1);
3431 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3432 tcg_gen_divu_tl(cpu_LO[acc], t0, t1);
3433 tcg_gen_remu_tl(cpu_HI[acc], t0, t1);
3434 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
3435 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
3436 tcg_temp_free(t3);
3437 tcg_temp_free(t2);
3438 }
3439 break;
3440 case OPC_MULT:
3441 {
3442 TCGv_i32 t2 = tcg_temp_new_i32();
3443 TCGv_i32 t3 = tcg_temp_new_i32();
3444 tcg_gen_trunc_tl_i32(t2, t0);
3445 tcg_gen_trunc_tl_i32(t3, t1);
3446 tcg_gen_muls2_i32(t2, t3, t2, t3);
3447 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3448 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3449 tcg_temp_free_i32(t2);
3450 tcg_temp_free_i32(t3);
3451 }
3452 break;
3453 case OPC_MULTU:
3454 {
3455 TCGv_i32 t2 = tcg_temp_new_i32();
3456 TCGv_i32 t3 = tcg_temp_new_i32();
3457 tcg_gen_trunc_tl_i32(t2, t0);
3458 tcg_gen_trunc_tl_i32(t3, t1);
3459 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3460 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3461 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3462 tcg_temp_free_i32(t2);
3463 tcg_temp_free_i32(t3);
3464 }
3465 break;
3466 #if defined(TARGET_MIPS64)
3467 case OPC_DDIV:
3468 {
3469 TCGv t2 = tcg_temp_new();
3470 TCGv t3 = tcg_temp_new();
3471 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3472 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3473 tcg_gen_and_tl(t2, t2, t3);
3474 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3475 tcg_gen_or_tl(t2, t2, t3);
3476 tcg_gen_movi_tl(t3, 0);
3477 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3478 tcg_gen_div_tl(cpu_LO[acc], t0, t1);
3479 tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
3480 tcg_temp_free(t3);
3481 tcg_temp_free(t2);
3482 }
3483 break;
3484 case OPC_DDIVU:
3485 {
3486 TCGv t2 = tcg_const_tl(0);
3487 TCGv t3 = tcg_const_tl(1);
3488 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3489 tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
3490 tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
3491 tcg_temp_free(t3);
3492 tcg_temp_free(t2);
3493 }
3494 break;
3495 case OPC_DMULT:
3496 tcg_gen_muls2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1);
3497 break;
3498 case OPC_DMULTU:
3499 tcg_gen_mulu2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1);
3500 break;
3501 #endif
3502 case OPC_MADD:
3503 {
3504 TCGv_i64 t2 = tcg_temp_new_i64();
3505 TCGv_i64 t3 = tcg_temp_new_i64();
3506
3507 tcg_gen_ext_tl_i64(t2, t0);
3508 tcg_gen_ext_tl_i64(t3, t1);
3509 tcg_gen_mul_i64(t2, t2, t3);
3510 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3511 tcg_gen_add_i64(t2, t2, t3);
3512 tcg_temp_free_i64(t3);
3513 gen_move_low32(cpu_LO[acc], t2);
3514 gen_move_high32(cpu_HI[acc], t2);
3515 tcg_temp_free_i64(t2);
3516 }
3517 break;
3518 case OPC_MADDU:
3519 {
3520 TCGv_i64 t2 = tcg_temp_new_i64();
3521 TCGv_i64 t3 = tcg_temp_new_i64();
3522
3523 tcg_gen_ext32u_tl(t0, t0);
3524 tcg_gen_ext32u_tl(t1, t1);
3525 tcg_gen_extu_tl_i64(t2, t0);
3526 tcg_gen_extu_tl_i64(t3, t1);
3527 tcg_gen_mul_i64(t2, t2, t3);
3528 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3529 tcg_gen_add_i64(t2, t2, t3);
3530 tcg_temp_free_i64(t3);
3531 gen_move_low32(cpu_LO[acc], t2);
3532 gen_move_high32(cpu_HI[acc], t2);
3533 tcg_temp_free_i64(t2);
3534 }
3535 break;
3536 case OPC_MSUB:
3537 {
3538 TCGv_i64 t2 = tcg_temp_new_i64();
3539 TCGv_i64 t3 = tcg_temp_new_i64();
3540
3541 tcg_gen_ext_tl_i64(t2, t0);
3542 tcg_gen_ext_tl_i64(t3, t1);
3543 tcg_gen_mul_i64(t2, t2, t3);
3544 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3545 tcg_gen_sub_i64(t2, t3, t2);
3546 tcg_temp_free_i64(t3);
3547 gen_move_low32(cpu_LO[acc], t2);
3548 gen_move_high32(cpu_HI[acc], t2);
3549 tcg_temp_free_i64(t2);
3550 }
3551 break;
3552 case OPC_MSUBU:
3553 {
3554 TCGv_i64 t2 = tcg_temp_new_i64();
3555 TCGv_i64 t3 = tcg_temp_new_i64();
3556
3557 tcg_gen_ext32u_tl(t0, t0);
3558 tcg_gen_ext32u_tl(t1, t1);
3559 tcg_gen_extu_tl_i64(t2, t0);
3560 tcg_gen_extu_tl_i64(t3, t1);
3561 tcg_gen_mul_i64(t2, t2, t3);
3562 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3563 tcg_gen_sub_i64(t2, t3, t2);
3564 tcg_temp_free_i64(t3);
3565 gen_move_low32(cpu_LO[acc], t2);
3566 gen_move_high32(cpu_HI[acc], t2);
3567 tcg_temp_free_i64(t2);
3568 }
3569 break;
3570 default:
3571 MIPS_INVAL("mul/div");
3572 gen_reserved_instruction(ctx);
3573 goto out;
3574 }
3575 out:
3576 tcg_temp_free(t0);
3577 tcg_temp_free(t1);
3578 }
3579
3580 /*
3581 * These MULT[U] and MADD[U] instructions implemented in for example
3582 * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
3583 * architectures are special three-operand variants with the syntax
3584 *
3585 * MULT[U][1] rd, rs, rt
3586 *
3587 * such that
3588 *
3589 * (rd, LO, HI) <- rs * rt
3590 *
3591 * and
3592 *
3593 * MADD[U][1] rd, rs, rt
3594 *
3595 * such that
3596 *
3597 * (rd, LO, HI) <- (LO, HI) + rs * rt
3598 *
3599 * where the low-order 32-bits of the result is placed into both the
3600 * GPR rd and the special register LO. The high-order 32-bits of the
3601 * result is placed into the special register HI.
3602 *
3603 * If the GPR rd is omitted in assembly language, it is taken to be 0,
3604 * which is the zero register that always reads as 0.
3605 */
3606 static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
3607 int rd, int rs, int rt)
3608 {
3609 TCGv t0 = tcg_temp_new();
3610 TCGv t1 = tcg_temp_new();
3611 int acc = 0;
3612
3613 gen_load_gpr(t0, rs);
3614 gen_load_gpr(t1, rt);
3615
3616 switch (opc) {
3617 case MMI_OPC_MULT1:
3618 acc = 1;
3619 /* Fall through */
3620 case OPC_MULT:
3621 {
3622 TCGv_i32 t2 = tcg_temp_new_i32();
3623 TCGv_i32 t3 = tcg_temp_new_i32();
3624 tcg_gen_trunc_tl_i32(t2, t0);
3625 tcg_gen_trunc_tl_i32(t3, t1);
3626 tcg_gen_muls2_i32(t2, t3, t2, t3);
3627 if (rd) {
3628 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3629 }
3630 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3631 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3632 tcg_temp_free_i32(t2);
3633 tcg_temp_free_i32(t3);
3634 }
3635 break;
3636 case MMI_OPC_MULTU1:
3637 acc = 1;
3638 /* Fall through */
3639 case OPC_MULTU:
3640 {
3641 TCGv_i32 t2 = tcg_temp_new_i32();
3642 TCGv_i32 t3 = tcg_temp_new_i32();
3643 tcg_gen_trunc_tl_i32(t2, t0);
3644 tcg_gen_trunc_tl_i32(t3, t1);
3645 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3646 if (rd) {
3647 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3648 }
3649 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3650 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3651 tcg_temp_free_i32(t2);
3652 tcg_temp_free_i32(t3);
3653 }
3654 break;
3655 case MMI_OPC_MADD1:
3656 acc = 1;
3657 /* Fall through */
3658 case MMI_OPC_MADD:
3659 {
3660 TCGv_i64 t2 = tcg_temp_new_i64();
3661 TCGv_i64 t3 = tcg_temp_new_i64();
3662
3663 tcg_gen_ext_tl_i64(t2, t0);
3664 tcg_gen_ext_tl_i64(t3, t1);
3665 tcg_gen_mul_i64(t2, t2, t3);
3666 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3667 tcg_gen_add_i64(t2, t2, t3);
3668 tcg_temp_free_i64(t3);
3669 gen_move_low32(cpu_LO[acc], t2);
3670 gen_move_high32(cpu_HI[acc], t2);
3671 if (rd) {
3672 gen_move_low32(cpu_gpr[rd], t2);
3673 }
3674 tcg_temp_free_i64(t2);
3675 }
3676 break;
3677 case MMI_OPC_MADDU1:
3678 acc = 1;
3679 /* Fall through */
3680 case MMI_OPC_MADDU:
3681 {
3682 TCGv_i64 t2 = tcg_temp_new_i64();
3683 TCGv_i64 t3 = tcg_temp_new_i64();
3684
3685 tcg_gen_ext32u_tl(t0, t0);
3686 tcg_gen_ext32u_tl(t1, t1);
3687 tcg_gen_extu_tl_i64(t2, t0);
3688 tcg_gen_extu_tl_i64(t3, t1);
3689 tcg_gen_mul_i64(t2, t2, t3);
3690 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3691 tcg_gen_add_i64(t2, t2, t3);
3692 tcg_temp_free_i64(t3);
3693 gen_move_low32(cpu_LO[acc], t2);
3694 gen_move_high32(cpu_HI[acc], t2);
3695 if (rd) {
3696 gen_move_low32(cpu_gpr[rd], t2);
3697 }
3698 tcg_temp_free_i64(t2);
3699 }
3700 break;
3701 default:
3702 MIPS_INVAL("mul/madd TXx9");
3703 gen_reserved_instruction(ctx);
3704 goto out;
3705 }
3706
3707 out:
3708 tcg_temp_free(t0);
3709 tcg_temp_free(t1);
3710 }
3711
3712 static void gen_cl(DisasContext *ctx, uint32_t opc,
3713 int rd, int rs)
3714 {
3715 TCGv t0;
3716
3717 if (rd == 0) {
3718 /* Treat as NOP. */
3719 return;
3720 }
3721 t0 = cpu_gpr[rd];
3722 gen_load_gpr(t0, rs);
3723
3724 switch (opc) {
3725 case OPC_CLO:
3726 case R6_OPC_CLO:
3727 #if defined(TARGET_MIPS64)
3728 case OPC_DCLO:
3729 case R6_OPC_DCLO:
3730 #endif
3731 tcg_gen_not_tl(t0, t0);
3732 break;
3733 }
3734
3735 switch (opc) {
3736 case OPC_CLO:
3737 case R6_OPC_CLO:
3738 case OPC_CLZ:
3739 case R6_OPC_CLZ:
3740 tcg_gen_ext32u_tl(t0, t0);
3741 tcg_gen_clzi_tl(t0, t0, TARGET_LONG_BITS);
3742 tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32);
3743 break;
3744 #if defined(TARGET_MIPS64)
3745 case OPC_DCLO:
3746 case R6_OPC_DCLO:
3747 case OPC_DCLZ:
3748 case R6_OPC_DCLZ:
3749 tcg_gen_clzi_i64(t0, t0, 64);
3750 break;
3751 #endif
3752 }
3753 }
3754
3755 /* Godson integer instructions */
3756 static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
3757 int rd, int rs, int rt)
3758 {
3759 TCGv t0, t1;
3760
3761 if (rd == 0) {
3762 /* Treat as NOP. */
3763 return;
3764 }
3765
3766 switch (opc) {
3767 case OPC_MULT_G_2E:
3768 case OPC_MULT_G_2F:
3769 case OPC_MULTU_G_2E:
3770 case OPC_MULTU_G_2F:
3771 #if defined(TARGET_MIPS64)
3772 case OPC_DMULT_G_2E:
3773 case OPC_DMULT_G_2F:
3774 case OPC_DMULTU_G_2E:
3775 case OPC_DMULTU_G_2F:
3776 #endif
3777 t0 = tcg_temp_new();
3778 t1 = tcg_temp_new();
3779 break;
3780 default:
3781 t0 = tcg_temp_local_new();
3782 t1 = tcg_temp_local_new();
3783 break;
3784 }
3785
3786 gen_load_gpr(t0, rs);
3787 gen_load_gpr(t1, rt);
3788
3789 switch (opc) {
3790 case OPC_MULT_G_2E:
3791 case OPC_MULT_G_2F:
3792 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3793 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3794 break;
3795 case OPC_MULTU_G_2E:
3796 case OPC_MULTU_G_2F:
3797 tcg_gen_ext32u_tl(t0, t0);
3798 tcg_gen_ext32u_tl(t1, t1);
3799 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3800 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3801 break;
3802 case OPC_DIV_G_2E:
3803 case OPC_DIV_G_2F:
3804 {
3805 TCGLabel *l1 = gen_new_label();
3806 TCGLabel *l2 = gen_new_label();
3807 TCGLabel *l3 = gen_new_label();
3808 tcg_gen_ext32s_tl(t0, t0);
3809 tcg_gen_ext32s_tl(t1, t1);
3810 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3811 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3812 tcg_gen_br(l3);
3813 gen_set_label(l1);
3814 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
3815 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
3816 tcg_gen_mov_tl(cpu_gpr[rd], t0);
3817 tcg_gen_br(l3);
3818 gen_set_label(l2);
3819 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3820 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3821 gen_set_label(l3);
3822 }
3823 break;
3824 case OPC_DIVU_G_2E:
3825 case OPC_DIVU_G_2F:
3826 {
3827 TCGLabel *l1 = gen_new_label();
3828 TCGLabel *l2 = gen_new_label();
3829 tcg_gen_ext32u_tl(t0, t0);
3830 tcg_gen_ext32u_tl(t1, t1);
3831 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3832 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3833 tcg_gen_br(l2);
3834 gen_set_label(l1);
3835 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3836 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3837 gen_set_label(l2);
3838 }
3839 break;
3840 case OPC_MOD_G_2E:
3841 case OPC_MOD_G_2F:
3842 {
3843 TCGLabel *l1 = gen_new_label();
3844 TCGLabel *l2 = gen_new_label();
3845 TCGLabel *l3 = gen_new_label();
3846 tcg_gen_ext32u_tl(t0, t0);
3847 tcg_gen_ext32u_tl(t1, t1);
3848 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
3849 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
3850 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
3851 gen_set_label(l1);
3852 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3853 tcg_gen_br(l3);
3854 gen_set_label(l2);
3855 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3856 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3857 gen_set_label(l3);
3858 }
3859 break;
3860 case OPC_MODU_G_2E:
3861 case OPC_MODU_G_2F:
3862 {
3863 TCGLabel *l1 = gen_new_label();
3864 TCGLabel *l2 = gen_new_label();
3865 tcg_gen_ext32u_tl(t0, t0);
3866 tcg_gen_ext32u_tl(t1, t1);
3867 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3868 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3869 tcg_gen_br(l2);
3870 gen_set_label(l1);
3871 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3872 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3873 gen_set_label(l2);
3874 }
3875 break;
3876 #if defined(TARGET_MIPS64)
3877 case OPC_DMULT_G_2E:
3878 case OPC_DMULT_G_2F:
3879 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3880 break;
3881 case OPC_DMULTU_G_2E:
3882 case OPC_DMULTU_G_2F:
3883 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3884 break;
3885 case OPC_DDIV_G_2E:
3886 case OPC_DDIV_G_2F:
3887 {
3888 TCGLabel *l1 = gen_new_label();
3889 TCGLabel *l2 = gen_new_label();
3890 TCGLabel *l3 = gen_new_label();
3891 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3892 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3893 tcg_gen_br(l3);
3894 gen_set_label(l1);
3895 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
3896 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
3897 tcg_gen_mov_tl(cpu_gpr[rd], t0);
3898 tcg_gen_br(l3);
3899 gen_set_label(l2);
3900 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3901 gen_set_label(l3);
3902 }
3903 break;
3904 case OPC_DDIVU_G_2E:
3905 case OPC_DDIVU_G_2F:
3906 {
3907 TCGLabel *l1 = gen_new_label();
3908 TCGLabel *l2 = gen_new_label();
3909 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3910 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3911 tcg_gen_br(l2);
3912 gen_set_label(l1);
3913 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3914 gen_set_label(l2);
3915 }
3916 break;
3917 case OPC_DMOD_G_2E:
3918 case OPC_DMOD_G_2F:
3919 {
3920 TCGLabel *l1 = gen_new_label();
3921 TCGLabel *l2 = gen_new_label();
3922 TCGLabel *l3 = gen_new_label();
3923 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
3924 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
3925 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
3926 gen_set_label(l1);
3927 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3928 tcg_gen_br(l3);
3929 gen_set_label(l2);
3930 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3931 gen_set_label(l3);
3932 }
3933 break;
3934 case OPC_DMODU_G_2E:
3935 case OPC_DMODU_G_2F:
3936 {
3937 TCGLabel *l1 = gen_new_label();
3938 TCGLabel *l2 = gen_new_label();
3939 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3940 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3941 tcg_gen_br(l2);
3942 gen_set_label(l1);
3943 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3944 gen_set_label(l2);
3945 }
3946 break;
3947 #endif
3948 }
3949
3950 tcg_temp_free(t0);
3951 tcg_temp_free(t1);
3952 }
3953
3954 /* Loongson multimedia instructions */
3955 static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
3956 {
3957 uint32_t opc, shift_max;
3958 TCGv_i64 t0, t1;
3959 TCGCond cond;
3960
3961 opc = MASK_LMMI(ctx->opcode);
3962 switch (opc) {
3963 case OPC_ADD_CP2:
3964 case OPC_SUB_CP2:
3965 case OPC_DADD_CP2:
3966 case OPC_DSUB_CP2:
3967 t0 = tcg_temp_local_new_i64();
3968 t1 = tcg_temp_local_new_i64();
3969 break;
3970 default:
3971 t0 = tcg_temp_new_i64();
3972 t1 = tcg_temp_new_i64();
3973 break;
3974 }
3975
3976 check_cp1_enabled(ctx);
3977 gen_load_fpr64(ctx, t0, rs);
3978 gen_load_fpr64(ctx, t1, rt);
3979
3980 switch (opc) {
3981 case OPC_PADDSH:
3982 gen_helper_paddsh(t0, t0, t1);
3983 break;
3984 case OPC_PADDUSH:
3985 gen_helper_paddush(t0, t0, t1);
3986 break;
3987 case OPC_PADDH:
3988 gen_helper_paddh(t0, t0, t1);
3989 break;
3990 case OPC_PADDW:
3991 gen_helper_paddw(t0, t0, t1);
3992 break;
3993 case OPC_PADDSB:
3994 gen_helper_paddsb(t0, t0, t1);
3995 break;
3996 case OPC_PADDUSB:
3997 gen_helper_paddusb(t0, t0, t1);
3998 break;
3999 case OPC_PADDB:
4000 gen_helper_paddb(t0, t0, t1);
4001 break;
4002
4003 case OPC_PSUBSH:
4004 gen_helper_psubsh(t0, t0, t1);
4005 break;
4006 case OPC_PSUBUSH:
4007 gen_helper_psubush(t0, t0, t1);
4008 break;
4009 case OPC_PSUBH:
4010 gen_helper_psubh(t0, t0, t1);
4011 break;
4012 case OPC_PSUBW:
4013 gen_helper_psubw(t0, t0, t1);
4014 break;
4015 case OPC_PSUBSB:
4016 gen_helper_psubsb(t0, t0, t1);
4017 break;
4018 case OPC_PSUBUSB:
4019 gen_helper_psubusb(t0, t0, t1);
4020 break;
4021 case OPC_PSUBB:
4022 gen_helper_psubb(t0, t0, t1);
4023 break;
4024
4025 case OPC_PSHUFH:
4026 gen_helper_pshufh(t0, t0, t1);
4027 break;
4028 case OPC_PACKSSWH:
4029 gen_helper_packsswh(t0, t0, t1);
4030 break;
4031 case OPC_PACKSSHB:
4032 gen_helper_packsshb(t0, t0, t1);
4033 break;
4034 case OPC_PACKUSHB:
4035 gen_helper_packushb(t0, t0, t1);
4036 break;
4037
4038 case OPC_PUNPCKLHW:
4039 gen_helper_punpcklhw(t0, t0, t1);
4040 break;
4041 case OPC_PUNPCKHHW:
4042 gen_helper_punpckhhw(t0, t0, t1);
4043 break;
4044 case OPC_PUNPCKLBH:
4045 gen_helper_punpcklbh(t0, t0, t1);
4046 break;
4047 case OPC_PUNPCKHBH:
4048 gen_helper_punpckhbh(t0, t0, t1);
4049 break;
4050 case OPC_PUNPCKLWD:
4051 gen_helper_punpcklwd(t0, t0, t1);
4052 break;
4053 case OPC_PUNPCKHWD:
4054 gen_helper_punpckhwd(t0, t0, t1);
4055 break;
4056
4057 case OPC_PAVGH:
4058 gen_helper_pavgh(t0, t0, t1);
4059 break;
4060 case OPC_PAVGB:
4061 gen_helper_pavgb(t0, t0, t1);
4062 break;
4063 case OPC_PMAXSH:
4064 gen_helper_pmaxsh(t0, t0, t1);
4065 break;
4066 case OPC_PMINSH:
4067 gen_helper_pminsh(t0, t0, t1);
4068 break;
4069 case OPC_PMAXUB:
4070 gen_helper_pmaxub(t0, t0, t1);
4071 break;
4072 case OPC_PMINUB:
4073 gen_helper_pminub(t0, t0, t1);
4074 break;
4075
4076 case OPC_PCMPEQW:
4077 gen_helper_pcmpeqw(t0, t0, t1);
4078 break;
4079 case OPC_PCMPGTW:
4080 gen_helper_pcmpgtw(t0, t0, t1);
4081 break;
4082 case OPC_PCMPEQH:
4083 gen_helper_pcmpeqh(t0, t0, t1);
4084 break;
4085 case OPC_PCMPGTH:
4086 gen_helper_pcmpgth(t0, t0, t1);
4087 break;
4088 case OPC_PCMPEQB:
4089 gen_helper_pcmpeqb(t0, t0, t1);
4090 break;
4091 case OPC_PCMPGTB:
4092 gen_helper_pcmpgtb(t0, t0, t1);
4093 break;
4094
4095 case OPC_PSLLW:
4096 gen_helper_psllw(t0, t0, t1);
4097 break;
4098 case OPC_PSLLH:
4099 gen_helper_psllh(t0, t0, t1);
4100 break;
4101 case OPC_PSRLW:
4102 gen_helper_psrlw(t0, t0, t1);
4103 break;
4104 case OPC_PSRLH:
4105 gen_helper_psrlh(t0, t0, t1);
4106 break;
4107 case OPC_PSRAW:
4108 gen_helper_psraw(t0, t0, t1);
4109 break;
4110 case OPC_PSRAH:
4111 gen_helper_psrah(t0, t0, t1);
4112 break;
4113
4114 case OPC_PMULLH:
4115 gen_helper_pmullh(t0, t0, t1);
4116 break;
4117 case OPC_PMULHH:
4118 gen_helper_pmulhh(t0, t0, t1);
4119 break;
4120 case OPC_PMULHUH:
4121 gen_helper_pmulhuh(t0, t0, t1);
4122 break;
4123 case OPC_PMADDHW:
4124 gen_helper_pmaddhw(t0, t0, t1);
4125 break;
4126
4127 case OPC_PASUBUB:
4128 gen_helper_pasubub(t0, t0, t1);
4129 break;
4130 case OPC_BIADD:
4131 gen_helper_biadd(t0, t0);
4132 break;
4133 case OPC_PMOVMSKB:
4134 gen_helper_pmovmskb(t0, t0);
4135 break;
4136
4137 case OPC_PADDD:
4138 tcg_gen_add_i64(t0, t0, t1);
4139 break;
4140 case OPC_PSUBD:
4141 tcg_gen_sub_i64(t0, t0, t1);
4142 break;
4143 case OPC_XOR_CP2:
4144 tcg_gen_xor_i64(t0, t0, t1);
4145 break;
4146 case OPC_NOR_CP2:
4147 tcg_gen_nor_i64(t0, t0, t1);
4148 break;
4149 case OPC_AND_CP2:
4150 tcg_gen_and_i64(t0, t0, t1);
4151 break;
4152 case OPC_OR_CP2:
4153 tcg_gen_or_i64(t0, t0, t1);
4154 break;
4155
4156 case OPC_PANDN:
4157 tcg_gen_andc_i64(t0, t1, t0);
4158 break;
4159
4160 case OPC_PINSRH_0:
4161 tcg_gen_deposit_i64(t0, t0, t1, 0, 16);
4162 break;
4163 case OPC_PINSRH_1:
4164 tcg_gen_deposit_i64(t0, t0, t1, 16, 16);
4165 break;
4166 case OPC_PINSRH_2:
4167 tcg_gen_deposit_i64(t0, t0, t1, 32, 16);
4168 break;
4169 case OPC_PINSRH_3:
4170 tcg_gen_deposit_i64(t0, t0, t1, 48, 16);
4171 break;
4172
4173 case OPC_PEXTRH:
4174 tcg_gen_andi_i64(t1, t1, 3);
4175 tcg_gen_shli_i64(t1, t1, 4);
4176 tcg_gen_shr_i64(t0, t0, t1);
4177 tcg_gen_ext16u_i64(t0, t0);
4178 break;
4179
4180 case OPC_ADDU_CP2:
4181 tcg_gen_add_i64(t0, t0, t1);
4182 tcg_gen_ext32s_i64(t0, t0);
4183 break;
4184 case OPC_SUBU_CP2:
4185 tcg_gen_sub_i64(t0, t0, t1);
4186 tcg_gen_ext32s_i64(t0, t0);
4187 break;
4188
4189 case OPC_SLL_CP2:
4190 shift_max = 32;
4191 goto do_shift;
4192 case OPC_SRL_CP2:
4193 shift_max = 32;
4194 goto do_shift;
4195 case OPC_SRA_CP2:
4196 shift_max = 32;
4197 goto do_shift;
4198 case OPC_DSLL_CP2:
4199 shift_max = 64;
4200 goto do_shift;
4201 case OPC_DSRL_CP2:
4202 shift_max = 64;
4203 goto do_shift;
4204 case OPC_DSRA_CP2:
4205 shift_max = 64;
4206 goto do_shift;
4207 do_shift:
4208 /* Make sure shift count isn't TCG undefined behaviour. */
4209 tcg_gen_andi_i64(t1, t1, shift_max - 1);
4210
4211 switch (opc) {
4212 case OPC_SLL_CP2:
4213 case OPC_DSLL_CP2:
4214 tcg_gen_shl_i64(t0, t0, t1);
4215 break;
4216 case OPC_SRA_CP2:
4217 case OPC_DSRA_CP2:
4218 /*
4219 * Since SRA is UndefinedResult without sign-extended inputs,
4220 * we can treat SRA and DSRA the same.
4221 */
4222 tcg_gen_sar_i64(t0, t0, t1);
4223 break;
4224 case OPC_SRL_CP2:
4225 /* We want to shift in zeros for SRL; zero-extend first. */
4226 tcg_gen_ext32u_i64(t0, t0);
4227 /* FALLTHRU */
4228 case OPC_DSRL_CP2:
4229 tcg_gen_shr_i64(t0, t0, t1);
4230 break;
4231 }
4232
4233 if (shift_max == 32) {
4234 tcg_gen_ext32s_i64(t0, t0);
4235 }
4236
4237 /* Shifts larger than MAX produce zero. */
4238 tcg_gen_setcondi_i64(TCG_COND_LTU, t1, t1, shift_max);
4239 tcg_gen_neg_i64(t1, t1);
4240 tcg_gen_and_i64(t0, t0, t1);
4241 break;
4242
4243 case OPC_ADD_CP2:
4244 case OPC_DADD_CP2:
4245 {
4246 TCGv_i64 t2 = tcg_temp_new_i64();
4247 TCGLabel *lab = gen_new_label();
4248
4249 tcg_gen_mov_i64(t2, t0);
4250 tcg_gen_add_i64(t0, t1, t2);
4251 if (opc == OPC_ADD_CP2) {
4252 tcg_gen_ext32s_i64(t0, t0);
4253 }
4254 tcg_gen_xor_i64(t1, t1, t2);
4255 tcg_gen_xor_i64(t2, t2, t0);
4256 tcg_gen_andc_i64(t1, t2, t1);
4257 tcg_temp_free_i64(t2);
4258 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
4259 generate_exception(ctx, EXCP_OVERFLOW);
4260 gen_set_label(lab);
4261 break;
4262 }
4263
4264 case OPC_SUB_CP2:
4265 case OPC_DSUB_CP2:
4266 {
4267 TCGv_i64 t2 = tcg_temp_new_i64();
4268 TCGLabel *lab = gen_new_label();
4269
4270 tcg_gen_mov_i64(t2, t0);
4271 tcg_gen_sub_i64(t0, t1, t2);
4272 if (opc == OPC_SUB_CP2) {
4273 tcg_gen_ext32s_i64(t0, t0);
4274 }
4275 tcg_gen_xor_i64(t1, t1, t2);
4276 tcg_gen_xor_i64(t2, t2, t0);
4277 tcg_gen_and_i64(t1, t1, t2);
4278 tcg_temp_free_i64(t2);
4279 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
4280 generate_exception(ctx, EXCP_OVERFLOW);
4281 gen_set_label(lab);
4282 break;
4283 }
4284
4285 case OPC_PMULUW:
4286 tcg_gen_ext32u_i64(t0, t0);
4287 tcg_gen_ext32u_i64(t1, t1);
4288 tcg_gen_mul_i64(t0, t0, t1);
4289 break;
4290
4291 case OPC_SEQU_CP2:
4292 case OPC_SEQ_CP2:
4293 cond = TCG_COND_EQ;
4294 goto do_cc_cond;
4295 break;
4296 case OPC_SLTU_CP2:
4297 cond = TCG_COND_LTU;
4298 goto do_cc_cond;
4299 break;
4300 case OPC_SLT_CP2:
4301 cond = TCG_COND_LT;
4302 goto do_cc_cond;
4303 break;
4304 case OPC_SLEU_CP2:
4305 cond = TCG_COND_LEU;
4306 goto do_cc_cond;
4307 break;
4308 case OPC_SLE_CP2:
4309 cond = TCG_COND_LE;
4310 do_cc_cond:
4311 {
4312 int cc = (ctx->opcode >> 8) & 0x7;
4313 TCGv_i64 t64 = tcg_temp_new_i64();
4314 TCGv_i32 t32 = tcg_temp_new_i32();
4315
4316 tcg_gen_setcond_i64(cond, t64, t0, t1);
4317 tcg_gen_extrl_i64_i32(t32, t64);
4318 tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32,
4319 get_fp_bit(cc), 1);
4320
4321 tcg_temp_free_i32(t32);
4322 tcg_temp_free_i64(t64);
4323 }
4324 goto no_rd;
4325 break;
4326 default:
4327 MIPS_INVAL("loongson_cp2");
4328 gen_reserved_instruction(ctx);
4329 return;
4330 }
4331
4332 gen_store_fpr64(ctx, t0, rd);
4333
4334 no_rd:
4335 tcg_temp_free_i64(t0);
4336 tcg_temp_free_i64(t1);
4337 }
4338
4339 static void gen_loongson_lswc2(DisasContext *ctx, int rt,
4340 int rs, int rd)
4341 {
4342 TCGv t0, t1, t2;
4343 TCGv_i32 fp0;
4344 #if defined(TARGET_MIPS64)
4345 int lsq_rt1 = ctx->opcode & 0x1f;
4346 int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4;
4347 #endif
4348 int shf_offset = sextract32(ctx->opcode, 6, 8);
4349
4350 t0 = tcg_temp_new();
4351
4352 switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) {
4353 #if defined(TARGET_MIPS64)
4354 case OPC_GSLQ:
4355 t1 = tcg_temp_new();
4356 gen_base_offset_addr(ctx, t0, rs, lsq_offset);
4357 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
4358 ctx->default_tcg_memop_mask);
4359 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
4360 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ |
4361 ctx->default_tcg_memop_mask);
4362 gen_store_gpr(t1, rt);
4363 gen_store_gpr(t0, lsq_rt1);
4364 tcg_temp_free(t1);
4365 break;
4366 case OPC_GSLQC1:
4367 check_cp1_enabled(ctx);
4368 t1 = tcg_temp_new();
4369 gen_base_offset_addr(ctx, t0, rs, lsq_offset);
4370 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
4371 ctx->default_tcg_memop_mask);
4372 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
4373 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ |
4374 ctx->default_tcg_memop_mask);
4375 gen_store_fpr64(ctx, t1, rt);
4376 gen_store_fpr64(ctx, t0, lsq_rt1);
4377 tcg_temp_free(t1);
4378 break;
4379 case OPC_GSSQ:
4380 t1 = tcg_temp_new();
4381 gen_base_offset_addr(ctx, t0, rs, lsq_offset);
4382 gen_load_gpr(t1, rt);
4383 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
4384 ctx->default_tcg_memop_mask);
4385 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
4386 gen_load_gpr(t1, lsq_rt1);
4387 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
4388 ctx->default_tcg_memop_mask);
4389 tcg_temp_free(t1);
4390 break;
4391 case OPC_GSSQC1:
4392 check_cp1_enabled(ctx);
4393 t1 = tcg_temp_new();
4394 gen_base_offset_addr(ctx, t0, rs, lsq_offset);
4395 gen_load_fpr64(ctx, t1, rt);
4396 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
4397 ctx->default_tcg_memop_mask);
4398 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
4399 gen_load_fpr64(ctx, t1, lsq_rt1);
4400 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
4401 ctx->default_tcg_memop_mask);
4402 tcg_temp_free(t1);
4403 break;
4404 #endif
4405 case OPC_GSSHFL:
4406 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
4407 case OPC_GSLWLC1:
4408 check_cp1_enabled(ctx);
4409 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4410 t1 = tcg_temp_new();
4411 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
4412 tcg_gen_andi_tl(t1, t0, 3);
4413 if (!cpu_is_bigendian(ctx)) {
4414 tcg_gen_xori_tl(t1, t1, 3);
4415 }
4416 tcg_gen_shli_tl(t1, t1, 3);
4417 tcg_gen_andi_tl(t0, t0, ~3);
4418 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
4419 tcg_gen_shl_tl(t0, t0, t1);
4420 t2 = tcg_const_tl(-1);
4421 tcg_gen_shl_tl(t2, t2, t1);
4422 fp0 = tcg_temp_new_i32();
4423 gen_load_fpr32(ctx, fp0, rt);
4424 tcg_gen_ext_i32_tl(t1, fp0);
4425 tcg_gen_andc_tl(t1, t1, t2);
4426 tcg_temp_free(t2);
4427 tcg_gen_or_tl(t0, t0, t1);
4428 tcg_temp_free(t1);
4429 #if defined(TARGET_MIPS64)
4430 tcg_gen_extrl_i64_i32(fp0, t0);
4431 #else
4432 tcg_gen_ext32s_tl(fp0, t0);
4433 #endif
4434 gen_store_fpr32(ctx, fp0, rt);
4435 tcg_temp_free_i32(fp0);
4436 break;
4437 case OPC_GSLWRC1:
4438 check_cp1_enabled(ctx);
4439 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4440 t1 = tcg_temp_new();
4441 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
4442 tcg_gen_andi_tl(t1, t0, 3);
4443 if (cpu_is_bigendian(ctx)) {
4444 tcg_gen_xori_tl(t1, t1, 3);
4445 }
4446 tcg_gen_shli_tl(t1, t1, 3);
4447 tcg_gen_andi_tl(t0, t0, ~3);
4448 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
4449 tcg_gen_shr_tl(t0, t0, t1);
4450 tcg_gen_xori_tl(t1, t1, 31);
4451 t2 = tcg_const_tl(0xfffffffeull);
4452 tcg_gen_shl_tl(t2, t2, t1);
4453 fp0 = tcg_temp_new_i32();
4454 gen_load_fpr32(ctx, fp0, rt);
4455 tcg_gen_ext_i32_tl(t1, fp0);
4456 tcg_gen_and_tl(t1, t1, t2);
4457 tcg_temp_free(t2);
4458 tcg_gen_or_tl(t0, t0, t1);
4459 tcg_temp_free(t1);
4460 #if defined(TARGET_MIPS64)
4461 tcg_gen_extrl_i64_i32(fp0, t0);
4462 #else
4463 tcg_gen_ext32s_tl(fp0, t0);
4464 #endif
4465 gen_store_fpr32(ctx, fp0, rt);
4466 tcg_temp_free_i32(fp0);
4467 break;
4468 #if defined(TARGET_MIPS64)
4469 case OPC_GSLDLC1:
4470 check_cp1_enabled(ctx);
4471 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4472 t1 = tcg_temp_new();
4473 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
4474 tcg_gen_andi_tl(t1, t0, 7);
4475 if (!cpu_is_bigendian(ctx)) {
4476 tcg_gen_xori_tl(t1, t1, 7);
4477 }
4478 tcg_gen_shli_tl(t1, t1, 3);
4479 tcg_gen_andi_tl(t0, t0, ~7);
4480 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ);
4481 tcg_gen_shl_tl(t0, t0, t1);
4482 t2 = tcg_const_tl(-1);
4483 tcg_gen_shl_tl(t2, t2, t1);
4484 gen_load_fpr64(ctx, t1, rt);
4485 tcg_gen_andc_tl(t1, t1, t2);
4486 tcg_temp_free(t2);
4487 tcg_gen_or_tl(t0, t0, t1);
4488 tcg_temp_free(t1);
4489 gen_store_fpr64(ctx, t0, rt);
4490 break;
4491 case OPC_GSLDRC1:
4492 check_cp1_enabled(ctx);
4493 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4494 t1 = tcg_temp_new();
4495 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
4496 tcg_gen_andi_tl(t1, t0, 7);
4497 if (cpu_is_bigendian(ctx)) {
4498 tcg_gen_xori_tl(t1, t1, 7);
4499 }
4500 tcg_gen_shli_tl(t1, t1, 3);
4501 tcg_gen_andi_tl(t0, t0, ~7);
4502 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ);
4503 tcg_gen_shr_tl(t0, t0, t1);
4504 tcg_gen_xori_tl(t1, t1, 63);
4505 t2 = tcg_const_tl(0xfffffffffffffffeull);
4506 tcg_gen_shl_tl(t2, t2, t1);
4507 gen_load_fpr64(ctx, t1, rt);
4508 tcg_gen_and_tl(t1, t1, t2);
4509 tcg_temp_free(t2);
4510 tcg_gen_or_tl(t0, t0, t1);
4511 tcg_temp_free(t1);
4512 gen_store_fpr64(ctx, t0, rt);
4513 break;
4514 #endif
4515 default:
4516 MIPS_INVAL("loongson_gsshfl");
4517 gen_reserved_instruction(ctx);
4518 break;
4519 }
4520 break;
4521 case OPC_GSSHFS:
4522 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
4523 case OPC_GSSWLC1:
4524 check_cp1_enabled(ctx);
4525 t1 = tcg_temp_new();
4526 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4527 fp0 = tcg_temp_new_i32();
4528 gen_load_fpr32(ctx, fp0, rt);
4529 tcg_gen_ext_i32_tl(t1, fp0);
4530 gen_helper_0e2i(swl, t1, t0, ctx->mem_idx);
4531 tcg_temp_free_i32(fp0);
4532 tcg_temp_free(t1);
4533 break;
4534 case OPC_GSSWRC1:
4535 check_cp1_enabled(ctx);
4536 t1 = tcg_temp_new();
4537 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4538 fp0 = tcg_temp_new_i32();
4539 gen_load_fpr32(ctx, fp0, rt);
4540 tcg_gen_ext_i32_tl(t1, fp0);
4541 gen_helper_0e2i(swr, t1, t0, ctx->mem_idx);
4542 tcg_temp_free_i32(fp0);
4543 tcg_temp_free(t1);
4544 break;
4545 #if defined(TARGET_MIPS64)
4546 case OPC_GSSDLC1:
4547 check_cp1_enabled(ctx);
4548 t1 = tcg_temp_new();
4549 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4550 gen_load_fpr64(ctx, t1, rt);
4551 gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx);
4552 tcg_temp_free(t1);
4553 break;
4554 case OPC_GSSDRC1:
4555 check_cp1_enabled(ctx);
4556 t1 = tcg_temp_new();
4557 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4558 gen_load_fpr64(ctx, t1, rt);
4559 gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx);
4560 tcg_temp_free(t1);
4561 break;
4562 #endif
4563 default:
4564 MIPS_INVAL("loongson_gsshfs");
4565 gen_reserved_instruction(ctx);
4566 break;
4567 }
4568 break;
4569 default:
4570 MIPS_INVAL("loongson_gslsq");
4571 gen_reserved_instruction(ctx);
4572 break;
4573 }
4574 tcg_temp_free(t0);
4575 }
4576
4577 /* Loongson EXT LDC2/SDC2 */
4578 static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
4579 int rs, int rd)
4580 {
4581 int offset = sextract32(ctx->opcode, 3, 8);
4582 uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode);
4583 TCGv t0, t1;
4584 TCGv_i32 fp0;
4585
4586 /* Pre-conditions */
4587 switch (opc) {
4588 case OPC_GSLBX:
4589 case OPC_GSLHX:
4590 case OPC_GSLWX:
4591 case OPC_GSLDX:
4592 /* prefetch, implement as NOP */
4593 if (rt == 0) {
4594 return;
4595 }
4596 break;
4597 case OPC_GSSBX:
4598 case OPC_GSSHX:
4599 case OPC_GSSWX:
4600 case OPC_GSSDX:
4601 break;
4602 case OPC_GSLWXC1:
4603 #if defined(TARGET_MIPS64)
4604 case OPC_GSLDXC1:
4605 #endif
4606 check_cp1_enabled(ctx);
4607 /* prefetch, implement as NOP */
4608 if (rt == 0) {
4609 return;
4610 }
4611 break;
4612 case OPC_GSSWXC1:
4613 #if defined(TARGET_MIPS64)
4614 case OPC_GSSDXC1:
4615 #endif
4616 check_cp1_enabled(ctx);
4617 break;
4618 default:
4619 MIPS_INVAL("loongson_lsdc2");
4620 gen_reserved_instruction(ctx);
4621 return;
4622 break;
4623 }
4624
4625 t0 = tcg_temp_new();
4626
4627 gen_base_offset_addr(ctx, t0, rs, offset);
4628 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4629
4630 switch (opc) {
4631 case OPC_GSLBX:
4632 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
4633 gen_store_gpr(t0, rt);
4634 break;
4635 case OPC_GSLHX:
4636 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
4637 ctx->default_tcg_memop_mask);
4638 gen_store_gpr(t0, rt);
4639 break;
4640 case OPC_GSLWX:
4641 gen_base_offset_addr(ctx, t0, rs, offset);
4642 if (rd) {
4643 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4644 }
4645 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
4646 ctx->default_tcg_memop_mask);
4647 gen_store_gpr(t0, rt);
4648 break;
4649 #if defined(TARGET_MIPS64)
4650 case OPC_GSLDX:
4651 gen_base_offset_addr(ctx, t0, rs, offset);
4652 if (rd) {
4653 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4654 }
4655 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ |
4656 ctx->default_tcg_memop_mask);
4657 gen_store_gpr(t0, rt);
4658 break;
4659 #endif
4660 case OPC_GSLWXC1:
4661 gen_base_offset_addr(ctx, t0, rs, offset);
4662 if (rd) {
4663 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4664 }
4665 fp0 = tcg_temp_new_i32();
4666 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
4667 ctx->default_tcg_memop_mask);
4668 gen_store_fpr32(ctx, fp0, rt);
4669 tcg_temp_free_i32(fp0);
4670 break;
4671 #if defined(TARGET_MIPS64)
4672 case OPC_GSLDXC1:
4673 gen_base_offset_addr(ctx, t0, rs, offset);
4674 if (rd) {
4675 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4676 }
4677 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ |
4678 ctx->default_tcg_memop_mask);
4679 gen_store_fpr64(ctx, t0, rt);
4680 break;
4681 #endif
4682 case OPC_GSSBX:
4683 t1 = tcg_temp_new();
4684 gen_load_gpr(t1, rt);
4685 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB);
4686 tcg_temp_free(t1);
4687 break;
4688 case OPC_GSSHX:
4689 t1 = tcg_temp_new();
4690 gen_load_gpr(t1, rt);
4691 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
4692 ctx->default_tcg_memop_mask);
4693 tcg_temp_free(t1);
4694 break;
4695 case OPC_GSSWX:
4696 t1 = tcg_temp_new();
4697 gen_load_gpr(t1, rt);
4698 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
4699 ctx->default_tcg_memop_mask);
4700 tcg_temp_free(t1);
4701 break;
4702 #if defined(TARGET_MIPS64)
4703 case OPC_GSSDX:
4704 t1 = tcg_temp_new();
4705 gen_load_gpr(t1, rt);
4706 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
4707 ctx->default_tcg_memop_mask);
4708 tcg_temp_free(t1);
4709 break;
4710 #endif
4711 case OPC_GSSWXC1:
4712 fp0 = tcg_temp_new_i32();
4713 gen_load_fpr32(ctx, fp0, rt);
4714 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
4715 ctx->default_tcg_memop_mask);
4716 tcg_temp_free_i32(fp0);
4717 break;
4718 #if defined(TARGET_MIPS64)
4719 case OPC_GSSDXC1:
4720 t1 = tcg_temp_new();
4721 gen_load_fpr64(ctx, t1, rt);
4722 tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEUQ |
4723 ctx->default_tcg_memop_mask);
4724 tcg_temp_free(t1);
4725 break;
4726 #endif
4727 default:
4728 break;
4729 }
4730
4731 tcg_temp_free(t0);
4732 }
4733
4734 /* Traps */
4735 static void gen_trap(DisasContext *ctx, uint32_t opc,
4736 int rs, int rt, int16_t imm)
4737 {
4738 int cond;
4739 TCGv t0 = tcg_temp_new();
4740 TCGv t1 = tcg_temp_new();
4741
4742 cond = 0;
4743 /* Load needed operands */
4744 switch (opc) {
4745 case OPC_TEQ:
4746 case OPC_TGE:
4747 case OPC_TGEU:
4748 case OPC_TLT:
4749 case OPC_TLTU:
4750 case OPC_TNE:
4751 /* Compare two registers */
4752 if (rs != rt) {
4753 gen_load_gpr(t0, rs);
4754 gen_load_gpr(t1, rt);
4755 cond = 1;
4756 }
4757 break;
4758 case OPC_TEQI:
4759 case OPC_TGEI:
4760 case OPC_TGEIU:
4761 case OPC_TLTI:
4762 case OPC_TLTIU:
4763 case OPC_TNEI:
4764 /* Compare register to immediate */
4765 if (rs != 0 || imm != 0) {
4766 gen_load_gpr(t0, rs);
4767 tcg_gen_movi_tl(t1, (int32_t)imm);
4768 cond = 1;
4769 }
4770 break;
4771 }
4772 if (cond == 0) {
4773 switch (opc) {
4774 case OPC_TEQ: /* rs == rs */
4775 case OPC_TEQI: /* r0 == 0 */
4776 case OPC_TGE: /* rs >= rs */
4777 case OPC_TGEI: /* r0 >= 0 */
4778 case OPC_TGEU: /* rs >= rs unsigned */
4779 case OPC_TGEIU: /* r0 >= 0 unsigned */
4780 /* Always trap */
4781 generate_exception_end(ctx, EXCP_TRAP);
4782 break;
4783 case OPC_TLT: /* rs < rs */
4784 case OPC_TLTI: /* r0 < 0 */
4785 case OPC_TLTU: /* rs < rs unsigned */
4786 case OPC_TLTIU: /* r0 < 0 unsigned */
4787 case OPC_TNE: /* rs != rs */
4788 case OPC_TNEI: /* r0 != 0 */
4789 /* Never trap: treat as NOP. */
4790 break;
4791 }
4792 } else {
4793 TCGLabel *l1 = gen_new_label();
4794
4795 switch (opc) {
4796 case OPC_TEQ:
4797 case OPC_TEQI:
4798 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1);
4799 break;
4800 case OPC_TGE:
4801 case OPC_TGEI:
4802 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
4803 break;
4804 case OPC_TGEU:
4805 case OPC_TGEIU:
4806 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
4807 break;
4808 case OPC_TLT:
4809 case OPC_TLTI:
4810 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4811 break;
4812 case OPC_TLTU:
4813 case OPC_TLTIU:
4814 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
4815 break;
4816 case OPC_TNE:
4817 case OPC_TNEI:
4818 tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1);
4819 break;
4820 }
4821 generate_exception(ctx, EXCP_TRAP);
4822 gen_set_label(l1);
4823 }
4824 tcg_temp_free(t0);
4825 tcg_temp_free(t1);
4826 }
4827
4828 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4829 {
4830 if (translator_use_goto_tb(&ctx->base, dest)) {
4831 tcg_gen_goto_tb(n);
4832 gen_save_pc(dest);
4833 tcg_gen_exit_tb(ctx->base.tb, n);
4834 } else {
4835 gen_save_pc(dest);
4836 tcg_gen_lookup_and_goto_ptr();
4837 }
4838 }
4839
4840 /* Branches (before delay slot) */
4841 static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
4842 int insn_bytes,
4843 int rs, int rt, int32_t offset,
4844 int delayslot_size)
4845 {
4846 target_ulong btgt = -1;
4847 int blink = 0;
4848 int bcond_compute = 0;
4849 TCGv t0 = tcg_temp_new();
4850 TCGv t1 = tcg_temp_new();
4851
4852 if (ctx->hflags & MIPS_HFLAG_BMASK) {
4853 #ifdef MIPS_DEBUG_DISAS
4854 LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
4855 TARGET_FMT_lx "\n", ctx->base.pc_next);
4856 #endif
4857 gen_reserved_instruction(ctx);
4858 goto out;
4859 }
4860
4861 /* Load needed operands */
4862 switch (opc) {
4863 case OPC_BEQ:
4864 case OPC_BEQL:
4865 case OPC_BNE:
4866 case OPC_BNEL:
4867 /* Compare two registers */
4868 if (rs != rt) {
4869 gen_load_gpr(t0, rs);
4870 gen_load_gpr(t1, rt);
4871 bcond_compute = 1;
4872 }
4873 btgt = ctx->base.pc_next + insn_bytes + offset;
4874 break;
4875 case OPC_BGEZ:
4876 case OPC_BGEZAL:
4877 case OPC_BGEZALL:
4878 case OPC_BGEZL:
4879 case OPC_BGTZ:
4880 case OPC_BGTZL:
4881 case OPC_BLEZ:
4882 case OPC_BLEZL:
4883 case OPC_BLTZ:
4884 case OPC_BLTZAL:
4885 case OPC_BLTZALL:
4886 case OPC_BLTZL:
4887 /* Compare to zero */
4888 if (rs != 0) {
4889 gen_load_gpr(t0, rs);
4890 bcond_compute = 1;
4891 }
4892 btgt = ctx->base.pc_next + insn_bytes + offset;
4893 break;
4894 case OPC_BPOSGE32:
4895 #if defined(TARGET_MIPS64)
4896 case OPC_BPOSGE64:
4897 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
4898 #else
4899 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
4900 #endif
4901 bcond_compute = 1;
4902 btgt = ctx->base.pc_next + insn_bytes + offset;
4903 break;
4904 case OPC_J:
4905 case OPC_JAL:
4906 case OPC_JALX:
4907 /* Jump to immediate */
4908 btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) |
4909 (uint32_t)offset;
4910 break;
4911 case OPC_JR:
4912 case OPC_JALR:
4913 /* Jump to register */
4914 if (offset != 0 && offset != 16) {
4915 /*
4916 * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
4917 * others are reserved.
4918 */
4919 MIPS_INVAL("jump hint");
4920 gen_reserved_instruction(ctx);
4921 goto out;
4922 }
4923 gen_load_gpr(btarget, rs);
4924 break;
4925 default:
4926 MIPS_INVAL("branch/jump");
4927 gen_reserved_instruction(ctx);
4928 goto out;
4929 }
4930 if (bcond_compute == 0) {
4931 /* No condition to be computed */
4932 switch (opc) {
4933 case OPC_BEQ: /* rx == rx */
4934 case OPC_BEQL: /* rx == rx likely */
4935 case OPC_BGEZ: /* 0 >= 0 */
4936 case OPC_BGEZL: /* 0 >= 0 likely */
4937 case OPC_BLEZ: /* 0 <= 0 */
4938 case OPC_BLEZL: /* 0 <= 0 likely */
4939 /* Always take */
4940 ctx->hflags |= MIPS_HFLAG_B;
4941 break;
4942 case OPC_BGEZAL: /* 0 >= 0 */
4943 case OPC_BGEZALL: /* 0 >= 0 likely */
4944 /* Always take and link */
4945 blink = 31;
4946 ctx->hflags |= MIPS_HFLAG_B;
4947 break;
4948 case OPC_BNE: /* rx != rx */
4949 case OPC_BGTZ: /* 0 > 0 */
4950 case OPC_BLTZ: /* 0 < 0 */
4951 /* Treat as NOP. */
4952 goto out;
4953 case OPC_BLTZAL: /* 0 < 0 */
4954 /*
4955 * Handle as an unconditional branch to get correct delay
4956 * slot checking.
4957 */
4958 blink = 31;
4959 btgt = ctx->base.pc_next + insn_bytes + delayslot_size;
4960 ctx->hflags |= MIPS_HFLAG_B;
4961 break;
4962 case OPC_BLTZALL: /* 0 < 0 likely */
4963 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8);
4964 /* Skip the instruction in the delay slot */
4965 ctx->base.pc_next += 4;
4966 goto out;
4967 case OPC_BNEL: /* rx != rx likely */
4968 case OPC_BGTZL: /* 0 > 0 likely */
4969 case OPC_BLTZL: /* 0 < 0 likely */
4970 /* Skip the instruction in the delay slot */
4971 ctx->base.pc_next += 4;
4972 goto out;
4973 case OPC_J:
4974 ctx->hflags |= MIPS_HFLAG_B;
4975 break;
4976 case OPC_JALX:
4977 ctx->hflags |= MIPS_HFLAG_BX;
4978 /* Fallthrough */
4979 case OPC_JAL:
4980 blink = 31;
4981 ctx->hflags |= MIPS_HFLAG_B;
4982 break;
4983 case OPC_JR:
4984 ctx->hflags |= MIPS_HFLAG_BR;
4985 break;
4986 case OPC_JALR:
4987 blink = rt;
4988 ctx->hflags |= MIPS_HFLAG_BR;
4989 break;
4990 default:
4991 MIPS_INVAL("branch/jump");
4992 gen_reserved_instruction(ctx);
4993 goto out;
4994 }
4995 } else {
4996 switch (opc) {
4997 case OPC_BEQ:
4998 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
4999 goto not_likely;
5000 case OPC_BEQL:
5001 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
5002 goto likely;
5003 case OPC_BNE:
5004 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
5005 goto not_likely;
5006 case OPC_BNEL:
5007 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
5008 goto likely;
5009 case OPC_BGEZ:
5010 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
5011 goto not_likely;
5012 case OPC_BGEZL:
5013 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
5014 goto likely;
5015 case OPC_BGEZAL:
5016 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
5017 blink = 31;
5018 goto not_likely;
5019 case OPC_BGEZALL:
5020 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
5021 blink = 31;
5022 goto likely;
5023 case OPC_BGTZ:
5024 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
5025 goto not_likely;
5026 case OPC_BGTZL:
5027 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
5028 goto likely;
5029 case OPC_BLEZ:
5030 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
5031 goto not_likely;
5032 case OPC_BLEZL:
5033 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
5034 goto likely;
5035 case OPC_BLTZ:
5036 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
5037 goto not_likely;
5038 case OPC_BLTZL:
5039 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
5040 goto likely;
5041 case OPC_BPOSGE32:
5042 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
5043 goto not_likely;
5044 #if defined(TARGET_MIPS64)
5045 case OPC_BPOSGE64:
5046 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64);
5047 goto not_likely;
5048 #endif
5049 case OPC_BLTZAL:
5050 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
5051 blink = 31;
5052 not_likely:
5053 ctx->hflags |= MIPS_HFLAG_BC;
5054 break;
5055 case OPC_BLTZALL:
5056 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
5057 blink = 31;
5058 likely:
5059 ctx->hflags |= MIPS_HFLAG_BL;
5060 break;
5061 default:
5062 MIPS_INVAL("conditional branch/jump");
5063 gen_reserved_instruction(ctx);
5064 goto out;
5065 }
5066 }
5067
5068 ctx->btarget = btgt;
5069
5070 switch (delayslot_size) {
5071 case 2:
5072 ctx->hflags |= MIPS_HFLAG_BDS16;
5073 break;
5074 case 4:
5075 ctx->hflags |= MIPS_HFLAG_BDS32;
5076 break;
5077 }
5078
5079 if (blink > 0) {
5080 int post_delay = insn_bytes + delayslot_size;
5081 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
5082
5083 tcg_gen_movi_tl(cpu_gpr[blink],
5084 ctx->base.pc_next + post_delay + lowbit);
5085 }
5086
5087 out:
5088 if (insn_bytes == 2) {
5089 ctx->hflags |= MIPS_HFLAG_B16;
5090 }
5091 tcg_temp_free(t0);
5092 tcg_temp_free(t1);
5093 }
5094
5095
5096 /* special3 bitfield operations */
5097 static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt,
5098 int rs, int lsb, int msb)
5099 {
5100 TCGv t0 = tcg_temp_new();
5101 TCGv t1 = tcg_temp_new();
5102
5103 gen_load_gpr(t1, rs);
5104 switch (opc) {
5105 case OPC_EXT:
5106 if (lsb + msb > 31) {
5107 goto fail;
5108 }
5109 if (msb != 31) {
5110 tcg_gen_extract_tl(t0, t1, lsb, msb + 1);
5111 } else {
5112 /*
5113 * The two checks together imply that lsb == 0,
5114 * so this is a simple sign-extension.
5115 */
5116 tcg_gen_ext32s_tl(t0, t1);
5117 }
5118 break;
5119 #if defined(TARGET_MIPS64)
5120 case OPC_DEXTU:
5121 lsb += 32;
5122 goto do_dext;
5123 case OPC_DEXTM:
5124 msb += 32;
5125 goto do_dext;
5126 case OPC_DEXT:
5127 do_dext:
5128 if (lsb + msb > 63) {
5129 goto fail;
5130 }
5131 tcg_gen_extract_tl(t0, t1, lsb, msb + 1);
5132 break;
5133 #endif
5134 case OPC_INS:
5135 if (lsb > msb) {
5136 goto fail;
5137 }
5138 gen_load_gpr(t0, rt);
5139 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
5140 tcg_gen_ext32s_tl(t0, t0);
5141 break;
5142 #if defined(TARGET_MIPS64)
5143 case OPC_DINSU:
5144 lsb += 32;
5145 /* FALLTHRU */
5146 case OPC_DINSM:
5147 msb += 32;
5148 /* FALLTHRU */
5149 case OPC_DINS:
5150 if (lsb > msb) {
5151 goto fail;
5152 }
5153 gen_load_gpr(t0, rt);
5154 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
5155 break;
5156 #endif
5157 default:
5158 fail:
5159 MIPS_INVAL("bitops");
5160 gen_reserved_instruction(ctx);
5161 tcg_temp_free(t0);
5162 tcg_temp_free(t1);
5163 return;
5164 }
5165 gen_store_gpr(t0, rt);
5166 tcg_temp_free(t0);
5167 tcg_temp_free(t1);
5168 }
5169
5170 static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
5171 {
5172 TCGv t0;
5173
5174 if (rd == 0) {
5175 /* If no destination, treat it as a NOP. */
5176 return;
5177 }
5178
5179 t0 = tcg_temp_new();
5180 gen_load_gpr(t0, rt);
5181 switch (op2) {
5182 case OPC_WSBH:
5183 {
5184 TCGv t1 = tcg_temp_new();
5185 TCGv t2 = tcg_const_tl(0x00FF00FF);
5186
5187 tcg_gen_shri_tl(t1, t0, 8);
5188 tcg_gen_and_tl(t1, t1, t2);
5189 tcg_gen_and_tl(t0, t0, t2);
5190 tcg_gen_shli_tl(t0, t0, 8);
5191 tcg_gen_or_tl(t0, t0, t1);
5192 tcg_temp_free(t2);
5193 tcg_temp_free(t1);
5194 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
5195 }
5196 break;
5197 case OPC_SEB:
5198 tcg_gen_ext8s_tl(cpu_gpr[rd], t0);
5199 break;
5200 case OPC_SEH:
5201 tcg_gen_ext16s_tl(cpu_gpr[rd], t0);
5202 break;
5203 #if defined(TARGET_MIPS64)
5204 case OPC_DSBH:
5205 {
5206 TCGv t1 = tcg_temp_new();
5207 TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL);
5208
5209 tcg_gen_shri_tl(t1, t0, 8);
5210 tcg_gen_and_tl(t1, t1, t2);
5211 tcg_gen_and_tl(t0, t0, t2);
5212 tcg_gen_shli_tl(t0, t0, 8);
5213 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
5214 tcg_temp_free(t2);
5215 tcg_temp_free(t1);
5216 }
5217 break;
5218 case OPC_DSHD:
5219 {
5220 TCGv t1 = tcg_temp_new();
5221 TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL);
5222
5223 tcg_gen_shri_tl(t1, t0, 16);
5224 tcg_gen_and_tl(t1, t1, t2);
5225 tcg_gen_and_tl(t0, t0, t2);
5226 tcg_gen_shli_tl(t0, t0, 16);
5227 tcg_gen_or_tl(t0, t0, t1);
5228 tcg_gen_shri_tl(t1, t0, 32);
5229 tcg_gen_shli_tl(t0, t0, 32);
5230 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
5231 tcg_temp_free(t2);
5232 tcg_temp_free(t1);
5233 }
5234 break;
5235 #endif
5236 default:
5237 MIPS_INVAL("bsfhl");
5238 gen_reserved_instruction(ctx);
5239 tcg_temp_free(t0);
5240 return;
5241 }
5242 tcg_temp_free(t0);
5243 }
5244
5245 static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
5246 int rt, int bits)
5247 {
5248 TCGv t0;
5249 if (rd == 0) {
5250 /* Treat as NOP. */
5251 return;
5252 }
5253 t0 = tcg_temp_new();
5254 if (bits == 0 || bits == wordsz) {
5255 if (bits == 0) {
5256 gen_load_gpr(t0, rt);
5257 } else {
5258 gen_load_gpr(t0, rs);
5259 }
5260 switch (wordsz) {
5261 case 32:
5262 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
5263 break;
5264 #if defined(TARGET_MIPS64)
5265 case 64:
5266 tcg_gen_mov_tl(cpu_gpr[rd], t0);
5267 break;
5268 #endif
5269 }
5270 } else {
5271 TCGv t1 = tcg_temp_new();
5272 gen_load_gpr(t0, rt);
5273 gen_load_gpr(t1, rs);
5274 switch (wordsz) {
5275 case 32:
5276 {
5277 TCGv_i64 t2 = tcg_temp_new_i64();
5278 tcg_gen_concat_tl_i64(t2, t1, t0);
5279 tcg_gen_shri_i64(t2, t2, 32 - bits);
5280 gen_move_low32(cpu_gpr[rd], t2);
5281 tcg_temp_free_i64(t2);
5282 }
5283 break;
5284 #if defined(TARGET_MIPS64)
5285 case 64:
5286 tcg_gen_shli_tl(t0, t0, bits);
5287 tcg_gen_shri_tl(t1, t1, 64 - bits);
5288 tcg_gen_or_tl(cpu_gpr[rd], t1, t0);
5289 break;
5290 #endif
5291 }
5292 tcg_temp_free(t1);
5293 }
5294
5295 tcg_temp_free(t0);
5296 }
5297
5298 void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp)
5299 {
5300 gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8);
5301 }
5302
5303 static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt)
5304 {
5305 TCGv t0;
5306 if (rd == 0) {
5307 /* Treat as NOP. */
5308 return;
5309 }
5310 t0 = tcg_temp_new();
5311 gen_load_gpr(t0, rt);
5312 switch (opc) {
5313 case OPC_BITSWAP:
5314 gen_helper_bitswap(cpu_gpr[rd], t0);
5315 break;
5316 #if defined(TARGET_MIPS64)
5317 case OPC_DBITSWAP:
5318 gen_helper_dbitswap(cpu_gpr[rd], t0);
5319 break;
5320 #endif
5321 }
5322 tcg_temp_free(t0);
5323 }
5324
5325 #ifndef CONFIG_USER_ONLY
5326 /* CP0 (MMU and control) */
5327 static inline void gen_mthc0_entrylo(TCGv arg, target_ulong off)
5328 {
5329 TCGv_i64 t0 = tcg_temp_new_i64();
5330 TCGv_i64 t1 = tcg_temp_new_i64();
5331
5332 tcg_gen_ext_tl_i64(t0, arg);
5333 tcg_gen_ld_i64(t1, cpu_env, off);
5334 #if defined(TARGET_MIPS64)
5335 tcg_gen_deposit_i64(t1, t1, t0, 30, 32);
5336 #else
5337 tcg_gen_concat32_i64(t1, t1, t0);
5338 #endif
5339 tcg_gen_st_i64(t1, cpu_env, off);
5340 tcg_temp_free_i64(t1);
5341 tcg_temp_free_i64(t0);
5342 }
5343
5344 static inline void gen_mthc0_store64(TCGv arg, target_ulong off)
5345 {
5346 TCGv_i64 t0 = tcg_temp_new_i64();
5347 TCGv_i64 t1 = tcg_temp_new_i64();
5348
5349 tcg_gen_ext_tl_i64(t0, arg);
5350 tcg_gen_ld_i64(t1, cpu_env, off);
5351 tcg_gen_concat32_i64(t1, t1, t0);
5352 tcg_gen_st_i64(t1, cpu_env, off);
5353 tcg_temp_free_i64(t1);
5354 tcg_temp_free_i64(t0);
5355 }
5356
5357 static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off)
5358 {
5359 TCGv_i64 t0 = tcg_temp_new_i64();
5360
5361 tcg_gen_ld_i64(t0, cpu_env, off);
5362 #if defined(TARGET_MIPS64)
5363 tcg_gen_shri_i64(t0, t0, 30);
5364 #else
5365 tcg_gen_shri_i64(t0, t0, 32);
5366 #endif
5367 gen_move_low32(arg, t0);
5368 tcg_temp_free_i64(t0);
5369 }
5370
5371 static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift)
5372 {
5373 TCGv_i64 t0 = tcg_temp_new_i64();
5374
5375 tcg_gen_ld_i64(t0, cpu_env, off);
5376 tcg_gen_shri_i64(t0, t0, 32 + shift);
5377 gen_move_low32(arg, t0);
5378 tcg_temp_free_i64(t0);
5379 }
5380
5381 static inline void gen_mfc0_load32(TCGv arg, target_ulong off)
5382 {
5383 TCGv_i32 t0 = tcg_temp_new_i32();
5384
5385 tcg_gen_ld_i32(t0, cpu_env, off);
5386 tcg_gen_ext_i32_tl(arg, t0);
5387 tcg_temp_free_i32(t0);
5388 }
5389
5390 static inline void gen_mfc0_load64(TCGv arg, target_ulong off)
5391 {
5392 tcg_gen_ld_tl(arg, cpu_env, off);
5393 tcg_gen_ext32s_tl(arg, arg);
5394 }
5395
5396 static inline void gen_mtc0_store32(TCGv arg, target_ulong off)
5397 {
5398 TCGv_i32 t0 = tcg_temp_new_i32();
5399
5400 tcg_gen_trunc_tl_i32(t0, arg);
5401 tcg_gen_st_i32(t0, cpu_env, off);
5402 tcg_temp_free_i32(t0);
5403 }
5404
5405 #define CP0_CHECK(c) \
5406 do { \
5407 if (!(c)) { \
5408 goto cp0_unimplemented; \
5409 } \
5410 } while (0)
5411
5412 static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
5413 {
5414 const char *register_name = "invalid";
5415
5416 switch (reg) {
5417 case CP0_REGISTER_02:
5418 switch (sel) {
5419 case 0:
5420 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
5421 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
5422 register_name = "EntryLo0";
5423 break;
5424 default:
5425 goto cp0_unimplemented;
5426 }
5427 break;
5428 case CP0_REGISTER_03:
5429 switch (sel) {
5430 case CP0_REG03__ENTRYLO1:
5431 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
5432 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
5433 register_name = "EntryLo1";
5434 break;
5435 default:
5436 goto cp0_unimplemented;
5437 }
5438 break;
5439 case CP0_REGISTER_09:
5440 switch (sel) {
5441 case CP0_REG09__SAAR:
5442 CP0_CHECK(ctx->saar);
5443 gen_helper_mfhc0_saar(arg, cpu_env);
5444 register_name = "SAAR";
5445 break;
5446 default:
5447 goto cp0_unimplemented;
5448 }
5449 break;
5450 case CP0_REGISTER_17:
5451 switch (sel) {
5452 case CP0_REG17__LLADDR:
5453 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr),
5454 ctx->CP0_LLAddr_shift);
5455 register_name = "LLAddr";
5456 break;
5457 case CP0_REG17__MAAR:
5458 CP0_CHECK(ctx->mrp);
5459 gen_helper_mfhc0_maar(arg, cpu_env);
5460 register_name = "MAAR";
5461 break;
5462 default:
5463 goto cp0_unimplemented;
5464 }
5465 break;
5466 case CP0_REGISTER_19:
5467 switch (sel) {
5468 case CP0_REG19__WATCHHI0:
5469 case CP0_REG19__WATCHHI1:
5470 case CP0_REG19__WATCHHI2:
5471 case CP0_REG19__WATCHHI3:
5472 case CP0_REG19__WATCHHI4:
5473 case CP0_REG19__WATCHHI5:
5474 case CP0_REG19__WATCHHI6:
5475 case CP0_REG19__WATCHHI7:
5476 /* upper 32 bits are only available when Config5MI != 0 */
5477 CP0_CHECK(ctx->mi);
5478 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0);
5479 register_name = "WatchHi";
5480 break;
5481 default:
5482 goto cp0_unimplemented;
5483 }
5484 break;
5485 case CP0_REGISTER_28:
5486 switch (sel) {
5487 case 0:
5488 case 2:
5489 case 4:
5490 case 6:
5491 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_TagLo), 0);
5492 register_name = "TagLo";
5493 break;
5494 default:
5495 goto cp0_unimplemented;
5496 }
5497 break;
5498 default:
5499 goto cp0_unimplemented;
5500 }
5501 trace_mips_translate_c0("mfhc0", register_name, reg, sel);
5502 return;
5503
5504 cp0_unimplemented:
5505 qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n",
5506 register_name, reg, sel);
5507 tcg_gen_movi_tl(arg, 0);
5508 }
5509
5510 static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
5511 {
5512 const char *register_name = "invalid";
5513 uint64_t mask = ctx->PAMask >> 36;
5514
5515 switch (reg) {
5516 case CP0_REGISTER_02:
5517 switch (sel) {
5518 case 0:
5519 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
5520 tcg_gen_andi_tl(arg, arg, mask);
5521 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
5522 register_name = "EntryLo0";
5523 break;
5524 default:
5525 goto cp0_unimplemented;
5526 }
5527 break;
5528 case CP0_REGISTER_03:
5529 switch (sel) {
5530 case CP0_REG03__ENTRYLO1:
5531 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
5532 tcg_gen_andi_tl(arg, arg, mask);
5533 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
5534 register_name = "EntryLo1";
5535 break;
5536 default:
5537 goto cp0_unimplemented;
5538 }
5539 break;
5540 case CP0_REGISTER_09:
5541 switch (sel) {
5542 case CP0_REG09__SAAR:
5543 CP0_CHECK(ctx->saar);
5544 gen_helper_mthc0_saar(cpu_env, arg);
5545 register_name = "SAAR";
5546 break;
5547 default:
5548 goto cp0_unimplemented;
5549 }
5550 break;
5551 case CP0_REGISTER_17:
5552 switch (sel) {
5553 case CP0_REG17__LLADDR:
5554 /*
5555 * LLAddr is read-only (the only exception is bit 0 if LLB is
5556 * supported); the CP0_LLAddr_rw_bitmask does not seem to be
5557 * relevant for modern MIPS cores supporting MTHC0, therefore
5558 * treating MTHC0 to LLAddr as NOP.
5559 */
5560 register_name = "LLAddr";
5561 break;
5562 case CP0_REG17__MAAR:
5563 CP0_CHECK(ctx->mrp);
5564 gen_helper_mthc0_maar(cpu_env, arg);
5565 register_name = "MAAR";
5566 break;
5567 default:
5568 goto cp0_unimplemented;
5569 }
5570 break;
5571 case CP0_REGISTER_19:
5572 switch (sel) {
5573 case CP0_REG19__WATCHHI0:
5574 case CP0_REG19__WATCHHI1:
5575 case CP0_REG19__WATCHHI2:
5576 case CP0_REG19__WATCHHI3:
5577 case CP0_REG19__WATCHHI4:
5578 case CP0_REG19__WATCHHI5:
5579 case CP0_REG19__WATCHHI6:
5580 case CP0_REG19__WATCHHI7:
5581 /* upper 32 bits are only available when Config5MI != 0 */
5582 CP0_CHECK(ctx->mi);
5583 gen_helper_0e1i(mthc0_watchhi, arg, sel);
5584 register_name = "WatchHi";
5585 break;
5586 default:
5587 goto cp0_unimplemented;
5588 }
5589 break;
5590 case CP0_REGISTER_28:
5591 switch (sel) {
5592 case 0:
5593 case 2:
5594 case 4:
5595 case 6:
5596 tcg_gen_andi_tl(arg, arg, mask);
5597 gen_mthc0_store64(arg, offsetof(CPUMIPSState, CP0_TagLo));
5598 register_name = "TagLo";
5599 break;
5600 default:
5601 goto cp0_unimplemented;
5602 }
5603 break;
5604 default:
5605 goto cp0_unimplemented;
5606 }
5607 trace_mips_translate_c0("mthc0", register_name, reg, sel);
5608 return;
5609
5610 cp0_unimplemented:
5611 qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n",
5612 register_name, reg, sel);
5613 }
5614
5615 static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
5616 {
5617 if (ctx->insn_flags & ISA_MIPS_R6) {
5618 tcg_gen_movi_tl(arg, 0);
5619 } else {
5620 tcg_gen_movi_tl(arg, ~0);
5621 }
5622 }
5623
5624 static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
5625 {
5626 const char *register_name = "invalid";
5627
5628 if (sel != 0) {
5629 check_insn(ctx, ISA_MIPS_R1);
5630 }
5631
5632 switch (reg) {
5633 case CP0_REGISTER_00:
5634 switch (sel) {
5635 case CP0_REG00__INDEX:
5636 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
5637 register_name = "Index";
5638 break;
5639 case CP0_REG00__MVPCONTROL:
5640 CP0_CHECK(ctx->insn_flags & ASE_MT);
5641 gen_helper_mfc0_mvpcontrol(arg, cpu_env);
5642 register_name = "MVPControl";
5643 break;
5644 case CP0_REG00__MVPCONF0:
5645 CP0_CHECK(ctx->insn_flags & ASE_MT);
5646 gen_helper_mfc0_mvpconf0(arg, cpu_env);
5647 register_name = "MVPConf0";
5648 break;
5649 case CP0_REG00__MVPCONF1:
5650 CP0_CHECK(ctx->insn_flags & ASE_MT);
5651 gen_helper_mfc0_mvpconf1(arg, cpu_env);
5652 register_name = "MVPConf1";
5653 break;
5654 case CP0_REG00__VPCONTROL:
5655 CP0_CHECK(ctx->vp);
5656 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
5657 register_name = "VPControl";
5658 break;
5659 default:
5660 goto cp0_unimplemented;
5661 }
5662 break;
5663 case CP0_REGISTER_01:
5664 switch (sel) {
5665 case CP0_REG01__RANDOM:
5666 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
5667 gen_helper_mfc0_random(arg, cpu_env);
5668 register_name = "Random";
5669 break;
5670 case CP0_REG01__VPECONTROL:
5671 CP0_CHECK(ctx->insn_flags & ASE_MT);
5672 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
5673 register_name = "VPEControl";
5674 break;
5675 case CP0_REG01__VPECONF0:
5676 CP0_CHECK(ctx->insn_flags & ASE_MT);
5677 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
5678 register_name = "VPEConf0";
5679 break;
5680 case CP0_REG01__VPECONF1:
5681 CP0_CHECK(ctx->insn_flags & ASE_MT);
5682 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
5683 register_name = "VPEConf1";
5684 break;
5685 case CP0_REG01__YQMASK:
5686 CP0_CHECK(ctx->insn_flags & ASE_MT);
5687 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
5688 register_name = "YQMask";
5689 break;
5690 case CP0_REG01__VPESCHEDULE:
5691 CP0_CHECK(ctx->insn_flags & ASE_MT);
5692 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
5693 register_name = "VPESchedule";
5694 break;
5695 case CP0_REG01__VPESCHEFBACK:
5696 CP0_CHECK(ctx->insn_flags & ASE_MT);
5697 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
5698 register_name = "VPEScheFBack";
5699 break;
5700 case CP0_REG01__VPEOPT:
5701 CP0_CHECK(ctx->insn_flags & ASE_MT);
5702 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
5703 register_name = "VPEOpt";
5704 break;
5705 default:
5706 goto cp0_unimplemented;
5707 }
5708 break;
5709 case CP0_REGISTER_02:
5710 switch (sel) {
5711 case CP0_REG02__ENTRYLO0:
5712 {
5713 TCGv_i64 tmp = tcg_temp_new_i64();
5714 tcg_gen_ld_i64(tmp, cpu_env,
5715 offsetof(CPUMIPSState, CP0_EntryLo0));
5716 #if defined(TARGET_MIPS64)
5717 if (ctx->rxi) {
5718 /* Move RI/XI fields to bits 31:30 */
5719 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI);
5720 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2);
5721 }
5722 #endif
5723 gen_move_low32(arg, tmp);
5724 tcg_temp_free_i64(tmp);
5725 }
5726 register_name = "EntryLo0";
5727 break;
5728 case CP0_REG02__TCSTATUS:
5729 CP0_CHECK(ctx->insn_flags & ASE_MT);
5730 gen_helper_mfc0_tcstatus(arg, cpu_env);
5731 register_name = "TCStatus";
5732 break;
5733 case CP0_REG02__TCBIND:
5734 CP0_CHECK(ctx->insn_flags & ASE_MT);
5735 gen_helper_mfc0_tcbind(arg, cpu_env);
5736 register_name = "TCBind";
5737 break;
5738 case CP0_REG02__TCRESTART:
5739 CP0_CHECK(ctx->insn_flags & ASE_MT);
5740 gen_helper_mfc0_tcrestart(arg, cpu_env);
5741 register_name = "TCRestart";
5742 break;
5743 case CP0_REG02__TCHALT:
5744 CP0_CHECK(ctx->insn_flags & ASE_MT);
5745 gen_helper_mfc0_tchalt(arg, cpu_env);
5746 register_name = "TCHalt";
5747 break;
5748 case CP0_REG02__TCCONTEXT:
5749 CP0_CHECK(ctx->insn_flags & ASE_MT);
5750 gen_helper_mfc0_tccontext(arg, cpu_env);
5751 register_name = "TCContext";
5752 break;
5753 case CP0_REG02__TCSCHEDULE:
5754 CP0_CHECK(ctx->insn_flags & ASE_MT);
5755 gen_helper_mfc0_tcschedule(arg, cpu_env);
5756 register_name = "TCSchedule";
5757 break;
5758 case CP0_REG02__TCSCHEFBACK:
5759 CP0_CHECK(ctx->insn_flags & ASE_MT);
5760 gen_helper_mfc0_tcschefback(arg, cpu_env);
5761 register_name = "TCScheFBack";
5762 break;
5763 default:
5764 goto cp0_unimplemented;
5765 }
5766 break;
5767 case CP0_REGISTER_03:
5768 switch (sel) {
5769 case CP0_REG03__ENTRYLO1:
5770 {
5771 TCGv_i64 tmp = tcg_temp_new_i64();
5772 tcg_gen_ld_i64(tmp, cpu_env,
5773 offsetof(CPUMIPSState, CP0_EntryLo1));
5774 #if defined(TARGET_MIPS64)
5775 if (ctx->rxi) {
5776 /* Move RI/XI fields to bits 31:30 */
5777 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI);
5778 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2);
5779 }
5780 #endif
5781 gen_move_low32(arg, tmp);
5782 tcg_temp_free_i64(tmp);
5783 }
5784 register_name = "EntryLo1";
5785 break;
5786 case CP0_REG03__GLOBALNUM:
5787 CP0_CHECK(ctx->vp);
5788 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
5789 register_name = "GlobalNumber";
5790 break;
5791 default:
5792 goto cp0_unimplemented;
5793 }
5794 break;
5795 case CP0_REGISTER_04:
5796 switch (sel) {
5797 case CP0_REG04__CONTEXT:
5798 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
5799 tcg_gen_ext32s_tl(arg, arg);
5800 register_name = "Context";
5801 break;
5802 case CP0_REG04__CONTEXTCONFIG:
5803 /* SmartMIPS ASE */
5804 /* gen_helper_mfc0_contextconfig(arg); */
5805 register_name = "ContextConfig";
5806 goto cp0_unimplemented;
5807 case CP0_REG04__USERLOCAL:
5808 CP0_CHECK(ctx->ulri);
5809 tcg_gen_ld_tl(arg, cpu_env,
5810 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
5811 tcg_gen_ext32s_tl(arg, arg);
5812 register_name = "UserLocal";
5813 break;
5814 case CP0_REG04__MMID:
5815 CP0_CHECK(ctx->mi);
5816 gen_helper_mtc0_memorymapid(cpu_env, arg);
5817 register_name = "MMID";
5818 break;
5819 default:
5820 goto cp0_unimplemented;
5821 }
5822 break;
5823 case CP0_REGISTER_05:
5824 switch (sel) {
5825 case CP0_REG05__PAGEMASK:
5826 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
5827 register_name = "PageMask";
5828 break;
5829 case CP0_REG05__PAGEGRAIN:
5830 check_insn(ctx, ISA_MIPS_R2);
5831 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
5832 register_name = "PageGrain";
5833 break;
5834 case CP0_REG05__SEGCTL0:
5835 CP0_CHECK(ctx->sc);
5836 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
5837 tcg_gen_ext32s_tl(arg, arg);
5838 register_name = "SegCtl0";
5839 break;
5840 case CP0_REG05__SEGCTL1:
5841 CP0_CHECK(ctx->sc);
5842 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
5843 tcg_gen_ext32s_tl(arg, arg);
5844 register_name = "SegCtl1";
5845 break;
5846 case CP0_REG05__SEGCTL2:
5847 CP0_CHECK(ctx->sc);
5848 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
5849 tcg_gen_ext32s_tl(arg, arg);
5850 register_name = "SegCtl2";
5851 break;
5852 case CP0_REG05__PWBASE:
5853 check_pw(ctx);
5854 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
5855 register_name = "PWBase";
5856 break;
5857 case CP0_REG05__PWFIELD:
5858 check_pw(ctx);
5859 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
5860 register_name = "PWField";
5861 break;
5862 case CP0_REG05__PWSIZE:
5863 check_pw(ctx);
5864 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
5865 register_name = "PWSize";
5866 break;
5867 default:
5868 goto cp0_unimplemented;
5869 }
5870 break;
5871 case CP0_REGISTER_06:
5872 switch (sel) {
5873 case CP0_REG06__WIRED:
5874 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
5875 register_name = "Wired";
5876 break;
5877 case CP0_REG06__SRSCONF0:
5878 check_insn(ctx, ISA_MIPS_R2);
5879 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
5880 register_name = "SRSConf0";
5881 break;
5882 case CP0_REG06__SRSCONF1:
5883 check_insn(ctx, ISA_MIPS_R2);
5884 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
5885 register_name = "SRSConf1";
5886 break;
5887 case CP0_REG06__SRSCONF2:
5888 check_insn(ctx, ISA_MIPS_R2);
5889 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
5890 register_name = "SRSConf2";
5891 break;
5892 case CP0_REG06__SRSCONF3:
5893 check_insn(ctx, ISA_MIPS_R2);
5894 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
5895 register_name = "SRSConf3";
5896 break;
5897 case CP0_REG06__SRSCONF4:
5898 check_insn(ctx, ISA_MIPS_R2);
5899 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
5900 register_name = "SRSConf4";
5901 break;
5902 case CP0_REG06__PWCTL:
5903 check_pw(ctx);
5904 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
5905 register_name = "PWCtl";
5906 break;
5907 default:
5908 goto cp0_unimplemented;
5909 }
5910 break;
5911 case CP0_REGISTER_07:
5912 switch (sel) {
5913 case CP0_REG07__HWRENA:
5914 check_insn(ctx, ISA_MIPS_R2);
5915 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
5916 register_name = "HWREna";
5917 break;
5918 default:
5919 goto cp0_unimplemented;
5920 }
5921 break;
5922 case CP0_REGISTER_08:
5923 switch (sel) {
5924 case CP0_REG08__BADVADDR:
5925 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
5926 tcg_gen_ext32s_tl(arg, arg);
5927 register_name = "BadVAddr";
5928 break;
5929 case CP0_REG08__BADINSTR:
5930 CP0_CHECK(ctx->bi);
5931 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
5932 register_name = "BadInstr";
5933 break;
5934 case CP0_REG08__BADINSTRP:
5935 CP0_CHECK(ctx->bp);
5936 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
5937 register_name = "BadInstrP";
5938 break;
5939 case CP0_REG08__BADINSTRX:
5940 CP0_CHECK(ctx->bi);
5941 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
5942 tcg_gen_andi_tl(arg, arg, ~0xffff);
5943 register_name = "BadInstrX";
5944 break;
5945 default:
5946 goto cp0_unimplemented;
5947 }
5948 break;
5949 case CP0_REGISTER_09:
5950 switch (sel) {
5951 case CP0_REG09__COUNT:
5952 /* Mark as an IO operation because we read the time. */
5953 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5954 gen_io_start();
5955 }
5956 gen_helper_mfc0_count(arg, cpu_env);
5957 /*
5958 * Break the TB to be able to take timer interrupts immediately
5959 * after reading count. DISAS_STOP isn't sufficient, we need to
5960 * ensure we break completely out of translated code.
5961 */
5962 gen_save_pc(ctx->base.pc_next + 4);
5963 ctx->base.is_jmp = DISAS_EXIT;
5964 register_name = "Count";
5965 break;
5966 case CP0_REG09__SAARI:
5967 CP0_CHECK(ctx->saar);
5968 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
5969 register_name = "SAARI";
5970 break;
5971 case CP0_REG09__SAAR:
5972 CP0_CHECK(ctx->saar);
5973 gen_helper_mfc0_saar(arg, cpu_env);
5974 register_name = "SAAR";
5975 break;
5976 default:
5977 goto cp0_unimplemented;
5978 }
5979 break;
5980 case CP0_REGISTER_10:
5981 switch (sel) {
5982 case CP0_REG10__ENTRYHI:
5983 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
5984 tcg_gen_ext32s_tl(arg, arg);
5985 register_name = "EntryHi";
5986 break;
5987 default:
5988 goto cp0_unimplemented;
5989 }
5990 break;
5991 case CP0_REGISTER_11:
5992 switch (sel) {
5993 case CP0_REG11__COMPARE:
5994 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
5995 register_name = "Compare";
5996 break;
5997 /* 6,7 are implementation dependent */
5998 default:
5999 goto cp0_unimplemented;
6000 }
6001 break;
6002 case CP0_REGISTER_12:
6003 switch (sel) {
6004 case CP0_REG12__STATUS:
6005 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
6006 register_name = "Status";
6007 break;
6008 case CP0_REG12__INTCTL:
6009 check_insn(ctx, ISA_MIPS_R2);
6010 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
6011 register_name = "IntCtl";
6012 break;
6013 case CP0_REG12__SRSCTL:
6014 check_insn(ctx, ISA_MIPS_R2);
6015 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
6016 register_name = "SRSCtl";
6017 break;
6018 case CP0_REG12__SRSMAP:
6019 check_insn(ctx, ISA_MIPS_R2);
6020 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
6021 register_name = "SRSMap";
6022 break;
6023 default:
6024 goto cp0_unimplemented;
6025 }
6026 break;
6027 case CP0_REGISTER_13:
6028 switch (sel) {
6029 case CP0_REG13__CAUSE:
6030 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
6031 register_name = "Cause";
6032 break;
6033 default:
6034 goto cp0_unimplemented;
6035 }
6036 break;
6037 case CP0_REGISTER_14:
6038 switch (sel) {
6039 case CP0_REG14__EPC:
6040 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
6041 tcg_gen_ext32s_tl(arg, arg);
6042 register_name = "EPC";
6043 break;
6044 default:
6045 goto cp0_unimplemented;
6046 }
6047 break;
6048 case CP0_REGISTER_15:
6049 switch (sel) {
6050 case CP0_REG15__PRID:
6051 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
6052 register_name = "PRid";
6053 break;
6054 case CP0_REG15__EBASE:
6055 check_insn(ctx, ISA_MIPS_R2);
6056 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
6057 tcg_gen_ext32s_tl(arg, arg);
6058 register_name = "EBase";
6059 break;
6060 case CP0_REG15__CMGCRBASE:
6061 check_insn(ctx, ISA_MIPS_R2);
6062 CP0_CHECK(ctx->cmgcr);
6063 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
6064 tcg_gen_ext32s_tl(arg, arg);
6065 register_name = "CMGCRBase";
6066 break;
6067 default:
6068 goto cp0_unimplemented;
6069 }
6070 break;
6071 case CP0_REGISTER_16:
6072 switch (sel) {
6073 case CP0_REG16__CONFIG:
6074 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
6075 register_name = "Config";
6076 break;
6077 case CP0_REG16__CONFIG1:
6078 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
6079 register_name = "Config1";
6080 break;
6081 case CP0_REG16__CONFIG2:
6082 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
6083 register_name = "Config2";
6084 break;
6085 case CP0_REG16__CONFIG3:
6086 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
6087 register_name = "Config3";
6088 break;
6089 case CP0_REG16__CONFIG4:
6090 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
6091 register_name = "Config4";
6092 break;
6093 case CP0_REG16__CONFIG5:
6094 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
6095 register_name = "Config5";
6096 break;
6097 /* 6,7 are implementation dependent */
6098 case CP0_REG16__CONFIG6:
6099 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
6100 register_name = "Config6";
6101 break;
6102 case CP0_REG16__CONFIG7:
6103 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
6104 register_name = "Config7";
6105 break;
6106 default:
6107 goto cp0_unimplemented;
6108 }
6109 break;
6110 case CP0_REGISTER_17:
6111 switch (sel) {
6112 case CP0_REG17__LLADDR:
6113 gen_helper_mfc0_lladdr(arg, cpu_env);
6114 register_name = "LLAddr";
6115 break;
6116 case CP0_REG17__MAAR:
6117 CP0_CHECK(ctx->mrp);
6118 gen_helper_mfc0_maar(arg, cpu_env);
6119 register_name = "MAAR";
6120 break;
6121 case CP0_REG17__MAARI:
6122 CP0_CHECK(ctx->mrp);
6123 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
6124 register_name = "MAARI";
6125 break;
6126 default:
6127 goto cp0_unimplemented;
6128 }
6129 break;
6130 case CP0_REGISTER_18:
6131 switch (sel) {
6132 case CP0_REG18__WATCHLO0:
6133 case CP0_REG18__WATCHLO1:
6134 case CP0_REG18__WATCHLO2:
6135 case CP0_REG18__WATCHLO3:
6136 case CP0_REG18__WATCHLO4:
6137 case CP0_REG18__WATCHLO5:
6138 case CP0_REG18__WATCHLO6:
6139 case CP0_REG18__WATCHLO7:
6140 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
6141 gen_helper_1e0i(mfc0_watchlo, arg, sel);
6142 register_name = "WatchLo";
6143 break;
6144 default:
6145 goto cp0_unimplemented;
6146 }
6147 break;
6148 case CP0_REGISTER_19:
6149 switch (sel) {
6150 case CP0_REG19__WATCHHI0:
6151 case CP0_REG19__WATCHHI1:
6152 case CP0_REG19__WATCHHI2:
6153 case CP0_REG19__WATCHHI3:
6154 case CP0_REG19__WATCHHI4:
6155 case CP0_REG19__WATCHHI5:
6156 case CP0_REG19__WATCHHI6:
6157 case CP0_REG19__WATCHHI7:
6158 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
6159 gen_helper_1e0i(mfc0_watchhi, arg, sel);
6160 register_name = "WatchHi";
6161 break;
6162 default:
6163 goto cp0_unimplemented;
6164 }
6165 break;
6166 case CP0_REGISTER_20:
6167 switch (sel) {
6168 case CP0_REG20__XCONTEXT:
6169 #if defined(TARGET_MIPS64)
6170 check_insn(ctx, ISA_MIPS3);
6171 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
6172 tcg_gen_ext32s_tl(arg, arg);
6173 register_name = "XContext";
6174 break;
6175 #endif
6176 default:
6177 goto cp0_unimplemented;
6178 }
6179 break;
6180 case CP0_REGISTER_21:
6181 /* Officially reserved, but sel 0 is used for R1x000 framemask */
6182 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
6183 switch (sel) {
6184 case 0:
6185 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
6186 register_name = "Framemask";
6187 break;
6188 default:
6189 goto cp0_unimplemented;
6190 }
6191 break;
6192 case CP0_REGISTER_22:
6193 tcg_gen_movi_tl(arg, 0); /* unimplemented */
6194 register_name = "'Diagnostic"; /* implementation dependent */
6195 break;
6196 case CP0_REGISTER_23:
6197 switch (sel) {
6198 case CP0_REG23__DEBUG:
6199 gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
6200 register_name = "Debug";
6201 break;
6202 case CP0_REG23__TRACECONTROL:
6203 /* PDtrace support */
6204 /* gen_helper_mfc0_tracecontrol(arg); */
6205 register_name = "TraceControl";
6206 goto cp0_unimplemented;
6207 case CP0_REG23__TRACECONTROL2:
6208 /* PDtrace support */
6209 /* gen_helper_mfc0_tracecontrol2(arg); */
6210 register_name = "TraceControl2";
6211 goto cp0_unimplemented;
6212 case CP0_REG23__USERTRACEDATA1:
6213 /* PDtrace support */
6214 /* gen_helper_mfc0_usertracedata1(arg);*/
6215 register_name = "UserTraceData1";
6216 goto cp0_unimplemented;
6217 case CP0_REG23__TRACEIBPC:
6218 /* PDtrace support */
6219 /* gen_helper_mfc0_traceibpc(arg); */
6220 register_name = "TraceIBPC";
6221 goto cp0_unimplemented;
6222 case CP0_REG23__TRACEDBPC:
6223 /* PDtrace support */
6224 /* gen_helper_mfc0_tracedbpc(arg); */
6225 register_name = "TraceDBPC";
6226 goto cp0_unimplemented;
6227 default:
6228 goto cp0_unimplemented;
6229 }
6230 break;
6231 case CP0_REGISTER_24:
6232 switch (sel) {
6233 case CP0_REG24__DEPC:
6234 /* EJTAG support */
6235 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
6236 tcg_gen_ext32s_tl(arg, arg);
6237 register_name = "DEPC";
6238 break;
6239 default:
6240 goto cp0_unimplemented;
6241 }
6242 break;
6243 case CP0_REGISTER_25:
6244 switch (sel) {
6245 case CP0_REG25__PERFCTL0:
6246 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
6247 register_name = "Performance0";
6248 break;
6249 case CP0_REG25__PERFCNT0:
6250 /* gen_helper_mfc0_performance1(arg); */
6251 register_name = "Performance1";
6252 goto cp0_unimplemented;
6253 case CP0_REG25__PERFCTL1:
6254 /* gen_helper_mfc0_performance2(arg); */
6255 register_name = "Performance2";
6256 goto cp0_unimplemented;
6257 case CP0_REG25__PERFCNT1:
6258 /* gen_helper_mfc0_performance3(arg); */
6259 register_name = "Performance3";
6260 goto cp0_unimplemented;
6261 case CP0_REG25__PERFCTL2:
6262 /* gen_helper_mfc0_performance4(arg); */
6263 register_name = "Performance4";
6264 goto cp0_unimplemented;
6265 case CP0_REG25__PERFCNT2:
6266 /* gen_helper_mfc0_performance5(arg); */
6267 register_name = "Performance5";
6268 goto cp0_unimplemented;
6269 case CP0_REG25__PERFCTL3:
6270 /* gen_helper_mfc0_performance6(arg); */
6271 register_name = "Performance6";
6272 goto cp0_unimplemented;
6273 case CP0_REG25__PERFCNT3:
6274 /* gen_helper_mfc0_performance7(arg); */
6275 register_name = "Performance7";
6276 goto cp0_unimplemented;
6277 default:
6278 goto cp0_unimplemented;
6279 }
6280 break;
6281 case CP0_REGISTER_26:
6282 switch (sel) {
6283 case CP0_REG26__ERRCTL:
6284 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
6285 register_name = "ErrCtl";
6286 break;
6287 default:
6288 goto cp0_unimplemented;
6289 }
6290 break;
6291 case CP0_REGISTER_27:
6292 switch (sel) {
6293 case CP0_REG27__CACHERR:
6294 tcg_gen_movi_tl(arg, 0); /* unimplemented */
6295 register_name = "CacheErr";
6296 break;
6297 default:
6298 goto cp0_unimplemented;
6299 }
6300 break;
6301 case CP0_REGISTER_28:
6302 switch (sel) {
6303 case CP0_REG28__TAGLO:
6304 case CP0_REG28__TAGLO1:
6305 case CP0_REG28__TAGLO2:
6306 case CP0_REG28__TAGLO3:
6307 {
6308 TCGv_i64 tmp = tcg_temp_new_i64();
6309 tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
6310 gen_move_low32(arg, tmp);
6311 tcg_temp_free_i64(tmp);
6312 }
6313 register_name = "TagLo";
6314 break;
6315 case CP0_REG28__DATALO:
6316 case CP0_REG28__DATALO1:
6317 case CP0_REG28__DATALO2:
6318 case CP0_REG28__DATALO3:
6319 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
6320 register_name = "DataLo";
6321 break;
6322 default:
6323 goto cp0_unimplemented;
6324 }
6325 break;
6326 case CP0_REGISTER_29:
6327 switch (sel) {
6328 case CP0_REG29__TAGHI:
6329 case CP0_REG29__TAGHI1:
6330 case CP0_REG29__TAGHI2:
6331 case CP0_REG29__TAGHI3:
6332 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
6333 register_name = "TagHi";
6334 break;
6335 case CP0_REG29__DATAHI:
6336 case CP0_REG29__DATAHI1:
6337 case CP0_REG29__DATAHI2:
6338 case CP0_REG29__DATAHI3:
6339 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
6340 register_name = "DataHi";
6341 break;
6342 default:
6343 goto cp0_unimplemented;
6344 }
6345 break;
6346 case CP0_REGISTER_30:
6347 switch (sel) {
6348 case CP0_REG30__ERROREPC:
6349 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
6350 tcg_gen_ext32s_tl(arg, arg);
6351 register_name = "ErrorEPC";
6352 break;
6353 default:
6354 goto cp0_unimplemented;
6355 }
6356 break;
6357 case CP0_REGISTER_31:
6358 switch (sel) {
6359 case CP0_REG31__DESAVE:
6360 /* EJTAG support */
6361 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
6362 register_name = "DESAVE";
6363 break;
6364 case CP0_REG31__KSCRATCH1:
6365 case CP0_REG31__KSCRATCH2:
6366 case CP0_REG31__KSCRATCH3:
6367 case CP0_REG31__KSCRATCH4:
6368 case CP0_REG31__KSCRATCH5:
6369 case CP0_REG31__KSCRATCH6:
6370 CP0_CHECK(ctx->kscrexist & (1 << sel));
6371 tcg_gen_ld_tl(arg, cpu_env,
6372 offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
6373 tcg_gen_ext32s_tl(arg, arg);
6374 register_name = "KScratch";
6375 break;
6376 default:
6377 goto cp0_unimplemented;
6378 }
6379 break;
6380 default:
6381 goto cp0_unimplemented;
6382 }
6383 trace_mips_translate_c0("mfc0", register_name, reg, sel);
6384 return;
6385
6386 cp0_unimplemented:
6387 qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n",
6388 register_name, reg, sel);
6389 gen_mfc0_unimplemented(ctx, arg);
6390 }
6391
6392 static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
6393 {
6394 const char *register_name = "invalid";
6395
6396 if (sel != 0) {
6397 check_insn(ctx, ISA_MIPS_R1);
6398 }
6399
6400 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
6401 gen_io_start();
6402 }
6403
6404 switch (reg) {
6405 case CP0_REGISTER_00:
6406 switch (sel) {
6407 case CP0_REG00__INDEX:
6408 gen_helper_mtc0_index(cpu_env, arg);
6409 register_name = "Index";
6410 break;
6411 case CP0_REG00__MVPCONTROL:
6412 CP0_CHECK(ctx->insn_flags & ASE_MT);
6413 gen_helper_mtc0_mvpcontrol(cpu_env, arg);
6414 register_name = "MVPControl";
6415 break;
6416 case CP0_REG00__MVPCONF0:
6417 CP0_CHECK(ctx->insn_flags & ASE_MT);
6418 /* ignored */
6419 register_name = "MVPConf0";
6420 break;
6421 case CP0_REG00__MVPCONF1:
6422 CP0_CHECK(ctx->insn_flags & ASE_MT);
6423 /* ignored */
6424 register_name = "MVPConf1";
6425 break;
6426 case CP0_REG00__VPCONTROL:
6427 CP0_CHECK(ctx->vp);
6428 /* ignored */
6429 register_name = "VPControl";
6430 break;
6431 default:
6432 goto cp0_unimplemented;
6433 }
6434 break;
6435 case CP0_REGISTER_01:
6436 switch (sel) {
6437 case CP0_REG01__RANDOM:
6438 /* ignored */
6439 register_name = "Random";
6440 break;
6441 case CP0_REG01__VPECONTROL:
6442 CP0_CHECK(ctx->insn_flags & ASE_MT);
6443 gen_helper_mtc0_vpecontrol(cpu_env, arg);
6444 register_name = "VPEControl";
6445 break;
6446 case CP0_REG01__VPECONF0:
6447 CP0_CHECK(ctx->insn_flags & ASE_MT);
6448 gen_helper_mtc0_vpeconf0(cpu_env, arg);
6449 register_name = "VPEConf0";
6450 break;
6451 case CP0_REG01__VPECONF1:
6452 CP0_CHECK(ctx->insn_flags & ASE_MT);
6453 gen_helper_mtc0_vpeconf1(cpu_env, arg);
6454 register_name = "VPEConf1";
6455 break;
6456 case CP0_REG01__YQMASK:
6457 CP0_CHECK(ctx->insn_flags & ASE_MT);
6458 gen_helper_mtc0_yqmask(cpu_env, arg);
6459 register_name = "YQMask";
6460 break;
6461 case CP0_REG01__VPESCHEDULE:
6462 CP0_CHECK(ctx->insn_flags & ASE_MT);
6463 tcg_gen_st_tl(arg, cpu_env,
6464 offsetof(CPUMIPSState, CP0_VPESchedule));
6465 register_name = "VPESchedule";
6466 break;
6467 case CP0_REG01__VPESCHEFBACK:
6468 CP0_CHECK(ctx->insn_flags & ASE_MT);
6469 tcg_gen_st_tl(arg, cpu_env,
6470 offsetof(CPUMIPSState, CP0_VPEScheFBack));
6471 register_name = "VPEScheFBack";
6472 break;
6473 case CP0_REG01__VPEOPT:
6474 CP0_CHECK(ctx->insn_flags & ASE_MT);
6475 gen_helper_mtc0_vpeopt(cpu_env, arg);
6476 register_name = "VPEOpt";
6477 break;
6478 default:
6479 goto cp0_unimplemented;
6480 }
6481 break;
6482 case CP0_REGISTER_02:
6483 switch (sel) {
6484 case CP0_REG02__ENTRYLO0:
6485 gen_helper_mtc0_entrylo0(cpu_env, arg);
6486 register_name = "EntryLo0";
6487 break;
6488 case CP0_REG02__TCSTATUS:
6489 CP0_CHECK(ctx->insn_flags & ASE_MT);
6490 gen_helper_mtc0_tcstatus(cpu_env, arg);
6491 register_name = "TCStatus";
6492 break;
6493 case CP0_REG02__TCBIND:
6494 CP0_CHECK(ctx->insn_flags & ASE_MT);
6495 gen_helper_mtc0_tcbind(cpu_env, arg);
6496 register_name = "TCBind";
6497 break;
6498 case CP0_REG02__TCRESTART:
6499 CP0_CHECK(ctx->insn_flags & ASE_MT);
6500 gen_helper_mtc0_tcrestart(cpu_env, arg);
6501 register_name = "TCRestart";
6502 break;
6503 case CP0_REG02__TCHALT:
6504 CP0_CHECK(ctx->insn_flags & ASE_MT);
6505 gen_helper_mtc0_tchalt(cpu_env, arg);
6506 register_name = "TCHalt";
6507 break;
6508 case CP0_REG02__TCCONTEXT:
6509 CP0_CHECK(ctx->insn_flags & ASE_MT);
6510 gen_helper_mtc0_tccontext(cpu_env, arg);
6511 register_name = "TCContext";
6512 break;
6513 case CP0_REG02__TCSCHEDULE:
6514 CP0_CHECK(ctx->insn_flags & ASE_MT);
6515 gen_helper_mtc0_tcschedule(cpu_env, arg);
6516 register_name = "TCSchedule";
6517 break;
6518 case CP0_REG02__TCSCHEFBACK:
6519 CP0_CHECK(ctx->insn_flags & ASE_MT);
6520 gen_helper_mtc0_tcschefback(cpu_env, arg);
6521 register_name = "TCScheFBack";
6522 break;
6523 default:
6524 goto cp0_unimplemented;
6525 }
6526 break;
6527 case CP0_REGISTER_03:
6528 switch (sel) {
6529 case CP0_REG03__ENTRYLO1:
6530 gen_helper_mtc0_entrylo1(cpu_env, arg);
6531 register_name = "EntryLo1";
6532 break;
6533 case CP0_REG03__GLOBALNUM:
6534 CP0_CHECK(ctx->vp);
6535 /* ignored */
6536 register_name = "GlobalNumber";
6537 break;
6538 default:
6539 goto cp0_unimplemented;
6540 }
6541 break;
6542 case CP0_REGISTER_04:
6543 switch (sel) {
6544 case CP0_REG04__CONTEXT:
6545 gen_helper_mtc0_context(cpu_env, arg);
6546 register_name = "Context";
6547 break;
6548 case CP0_REG04__CONTEXTCONFIG:
6549 /* SmartMIPS ASE */
6550 /* gen_helper_mtc0_contextconfig(arg); */
6551 register_name = "ContextConfig";
6552 goto cp0_unimplemented;
6553 case CP0_REG04__USERLOCAL:
6554 CP0_CHECK(ctx->ulri);
6555 tcg_gen_st_tl(arg, cpu_env,
6556 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
6557 register_name = "UserLocal";
6558 break;
6559 case CP0_REG04__MMID:
6560 CP0_CHECK(ctx->mi);
6561 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID));
6562 register_name = "MMID";
6563 break;
6564 default:
6565 goto cp0_unimplemented;
6566 }
6567 break;
6568 case CP0_REGISTER_05:
6569 switch (sel) {
6570 case CP0_REG05__PAGEMASK:
6571 gen_helper_mtc0_pagemask(cpu_env, arg);
6572 register_name = "PageMask";
6573 break;
6574 case CP0_REG05__PAGEGRAIN:
6575 check_insn(ctx, ISA_MIPS_R2);
6576 gen_helper_mtc0_pagegrain(cpu_env, arg);
6577 register_name = "PageGrain";
6578 ctx->base.is_jmp = DISAS_STOP;
6579 break;
6580 case CP0_REG05__SEGCTL0:
6581 CP0_CHECK(ctx->sc);
6582 gen_helper_mtc0_segctl0(cpu_env, arg);
6583 register_name = "SegCtl0";
6584 break;
6585 case CP0_REG05__SEGCTL1:
6586 CP0_CHECK(ctx->sc);
6587 gen_helper_mtc0_segctl1(cpu_env, arg);
6588 register_name = "SegCtl1";
6589 break;
6590 case CP0_REG05__SEGCTL2:
6591 CP0_CHECK(ctx->sc);
6592 gen_helper_mtc0_segctl2(cpu_env, arg);
6593 register_name = "SegCtl2";
6594 break;
6595 case CP0_REG05__PWBASE:
6596 check_pw(ctx);
6597 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
6598 register_name = "PWBase";
6599 break;
6600 case CP0_REG05__PWFIELD:
6601 check_pw(ctx);
6602 gen_helper_mtc0_pwfield(cpu_env, arg);
6603 register_name = "PWField";
6604 break;
6605 case CP0_REG05__PWSIZE:
6606 check_pw(ctx);
6607 gen_helper_mtc0_pwsize(cpu_env, arg);
6608 register_name = "PWSize";
6609 break;
6610 default:
6611 goto cp0_unimplemented;
6612 }
6613 break;
6614 case CP0_REGISTER_06:
6615 switch (sel) {
6616 case CP0_REG06__WIRED:
6617 gen_helper_mtc0_wired(cpu_env, arg);
6618 register_name = "Wired";
6619 break;
6620 case CP0_REG06__SRSCONF0:
6621 check_insn(ctx, ISA_MIPS_R2);
6622 gen_helper_mtc0_srsconf0(cpu_env, arg);
6623 register_name = "SRSConf0";
6624 break;
6625 case CP0_REG06__SRSCONF1:
6626 check_insn(ctx, ISA_MIPS_R2);
6627 gen_helper_mtc0_srsconf1(cpu_env, arg);
6628 register_name = "SRSConf1";
6629 break;
6630 case CP0_REG06__SRSCONF2:
6631 check_insn(ctx, ISA_MIPS_R2);
6632 gen_helper_mtc0_srsconf2(cpu_env, arg);
6633 register_name = "SRSConf2";
6634 break;
6635 case CP0_REG06__SRSCONF3:
6636 check_insn(ctx, ISA_MIPS_R2);
6637 gen_helper_mtc0_srsconf3(cpu_env, arg);
6638 register_name = "SRSConf3";
6639 break;
6640 case CP0_REG06__SRSCONF4:
6641 check_insn(ctx, ISA_MIPS_R2);
6642 gen_helper_mtc0_srsconf4(cpu_env, arg);
6643 register_name = "SRSConf4";
6644 break;
6645 case CP0_REG06__PWCTL:
6646 check_pw(ctx);
6647 gen_helper_mtc0_pwctl(cpu_env, arg);
6648 register_name = "PWCtl";
6649 break;
6650 default:
6651 goto cp0_unimplemented;
6652 }
6653 break;
6654 case CP0_REGISTER_07:
6655 switch (sel) {
6656 case CP0_REG07__HWRENA:
6657 check_insn(ctx, ISA_MIPS_R2);
6658 gen_helper_mtc0_hwrena(cpu_env, arg);
6659 ctx->base.is_jmp = DISAS_STOP;
6660 register_name = "HWREna";
6661 break;
6662 default:
6663 goto cp0_unimplemented;
6664 }
6665 break;
6666 case CP0_REGISTER_08:
6667 switch (sel) {
6668 case CP0_REG08__BADVADDR:
6669 /* ignored */
6670 register_name = "BadVAddr";
6671 break;
6672 case CP0_REG08__BADINSTR:
6673 /* ignored */
6674 register_name = "BadInstr";
6675 break;
6676 case CP0_REG08__BADINSTRP:
6677 /* ignored */
6678 register_name = "BadInstrP";
6679 break;
6680 case CP0_REG08__BADINSTRX:
6681 /* ignored */
6682 register_name = "BadInstrX";
6683 break;
6684 default:
6685 goto cp0_unimplemented;
6686 }
6687 break;
6688 case CP0_REGISTER_09:
6689 switch (sel) {
6690 case CP0_REG09__COUNT:
6691 gen_helper_mtc0_count(cpu_env, arg);
6692 register_name = "Count";
6693 break;
6694 case CP0_REG09__SAARI:
6695 CP0_CHECK(ctx->saar);
6696 gen_helper_mtc0_saari(cpu_env, arg);
6697 register_name = "SAARI";
6698 break;
6699 case CP0_REG09__SAAR:
6700 CP0_CHECK(ctx->saar);
6701 gen_helper_mtc0_saar(cpu_env, arg);
6702 register_name = "SAAR";
6703 break;
6704 default:
6705 goto cp0_unimplemented;
6706 }
6707 break;
6708 case CP0_REGISTER_10:
6709 switch (sel) {
6710 case CP0_REG10__ENTRYHI:
6711 gen_helper_mtc0_entryhi(cpu_env, arg);
6712 register_name = "EntryHi";
6713 break;
6714 default:
6715 goto cp0_unimplemented;
6716 }
6717 break;
6718 case CP0_REGISTER_11:
6719 switch (sel) {
6720 case CP0_REG11__COMPARE:
6721 gen_helper_mtc0_compare(cpu_env, arg);
6722 register_name = "Compare";
6723 break;
6724 /* 6,7 are implementation dependent */
6725 default:
6726 goto cp0_unimplemented;
6727 }
6728 break;
6729 case CP0_REGISTER_12:
6730 switch (sel) {
6731 case CP0_REG12__STATUS:
6732 save_cpu_state(ctx, 1);
6733 gen_helper_mtc0_status(cpu_env, arg);
6734 /* DISAS_STOP isn't good enough here, hflags may have changed. */
6735 gen_save_pc(ctx->base.pc_next + 4);
6736 ctx->base.is_jmp = DISAS_EXIT;
6737 register_name = "Status";
6738 break;
6739 case CP0_REG12__INTCTL:
6740 check_insn(ctx, ISA_MIPS_R2);
6741 gen_helper_mtc0_intctl(cpu_env, arg);
6742 /* Stop translation as we may have switched the execution mode */
6743 ctx->base.is_jmp = DISAS_STOP;
6744 register_name = "IntCtl";
6745 break;
6746 case CP0_REG12__SRSCTL:
6747 check_insn(ctx, ISA_MIPS_R2);
6748 gen_helper_mtc0_srsctl(cpu_env, arg);
6749 /* Stop translation as we may have switched the execution mode */
6750 ctx->base.is_jmp = DISAS_STOP;
6751 register_name = "SRSCtl";
6752 break;
6753 case CP0_REG12__SRSMAP:
6754 check_insn(ctx, ISA_MIPS_R2);
6755 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
6756 /* Stop translation as we may have switched the execution mode */
6757 ctx->base.is_jmp = DISAS_STOP;
6758 register_name = "SRSMap";
6759 break;
6760 default:
6761 goto cp0_unimplemented;
6762 }
6763 break;
6764 case CP0_REGISTER_13:
6765 switch (sel) {
6766 case CP0_REG13__CAUSE:
6767 save_cpu_state(ctx, 1);
6768 gen_helper_mtc0_cause(cpu_env, arg);
6769 /*
6770 * Stop translation as we may have triggered an interrupt.
6771 * DISAS_STOP isn't sufficient, we need to ensure we break out of
6772 * translated code to check for pending interrupts.
6773 */
6774 gen_save_pc(ctx->base.pc_next + 4);
6775 ctx->base.is_jmp = DISAS_EXIT;
6776 register_name = "Cause";
6777 break;
6778 default:
6779 goto cp0_unimplemented;
6780 }
6781 break;
6782 case CP0_REGISTER_14:
6783 switch (sel) {
6784 case CP0_REG14__EPC:
6785 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
6786 register_name = "EPC";
6787 break;
6788 default:
6789 goto cp0_unimplemented;
6790 }
6791 break;
6792 case CP0_REGISTER_15:
6793 switch (sel) {
6794 case CP0_REG15__PRID:
6795 /* ignored */
6796 register_name = "PRid";
6797 break;
6798 case CP0_REG15__EBASE:
6799 check_insn(ctx, ISA_MIPS_R2);
6800 gen_helper_mtc0_ebase(cpu_env, arg);
6801 register_name = "EBase";
6802 break;
6803 default:
6804 goto cp0_unimplemented;
6805 }
6806 break;
6807 case CP0_REGISTER_16:
6808 switch (sel) {
6809 case CP0_REG16__CONFIG:
6810 gen_helper_mtc0_config0(cpu_env, arg);
6811 register_name = "Config";
6812 /* Stop translation as we may have switched the execution mode */
6813 ctx->base.is_jmp = DISAS_STOP;
6814 break;
6815 case CP0_REG16__CONFIG1:
6816 /* ignored, read only */
6817 register_name = "Config1";
6818 break;
6819 case CP0_REG16__CONFIG2:
6820 gen_helper_mtc0_config2(cpu_env, arg);
6821 register_name = "Config2";
6822 /* Stop translation as we may have switched the execution mode */
6823 ctx->base.is_jmp = DISAS_STOP;
6824 break;
6825 case CP0_REG16__CONFIG3:
6826 gen_helper_mtc0_config3(cpu_env, arg);
6827 register_name = "Config3";
6828 /* Stop translation as we may have switched the execution mode */
6829 ctx->base.is_jmp = DISAS_STOP;
6830 break;
6831 case CP0_REG16__CONFIG4:
6832 gen_helper_mtc0_config4(cpu_env, arg);
6833 register_name = "Config4";
6834 ctx->base.is_jmp = DISAS_STOP;
6835 break;
6836 case CP0_REG16__CONFIG5:
6837 gen_helper_mtc0_config5(cpu_env, arg);
6838 register_name = "Config5";
6839 /* Stop translation as we may have switched the execution mode */
6840 ctx->base.is_jmp = DISAS_STOP;
6841 break;
6842 /* 6,7 are implementation dependent */
6843 case CP0_REG16__CONFIG6:
6844 /* ignored */
6845 register_name = "Config6";
6846 break;
6847 case CP0_REG16__CONFIG7:
6848 /* ignored */
6849 register_name = "Config7";
6850 break;
6851 default:
6852 register_name = "Invalid config selector";
6853 goto cp0_unimplemented;
6854 }
6855 break;
6856 case CP0_REGISTER_17:
6857 switch (sel) {
6858 case CP0_REG17__LLADDR:
6859 gen_helper_mtc0_lladdr(cpu_env, arg);
6860 register_name = "LLAddr";
6861 break;
6862 case CP0_REG17__MAAR:
6863 CP0_CHECK(ctx->mrp);
6864 gen_helper_mtc0_maar(cpu_env, arg);
6865 register_name = "MAAR";
6866 break;
6867 case CP0_REG17__MAARI:
6868 CP0_CHECK(ctx->mrp);
6869 gen_helper_mtc0_maari(cpu_env, arg);
6870 register_name = "MAARI";
6871 break;
6872 default:
6873 goto cp0_unimplemented;
6874 }
6875 break;
6876 case CP0_REGISTER_18:
6877 switch (sel) {
6878 case CP0_REG18__WATCHLO0:
6879 case CP0_REG18__WATCHLO1:
6880 case CP0_REG18__WATCHLO2:
6881 case CP0_REG18__WATCHLO3:
6882 case CP0_REG18__WATCHLO4:
6883 case CP0_REG18__WATCHLO5:
6884 case CP0_REG18__WATCHLO6:
6885 case CP0_REG18__WATCHLO7:
6886 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
6887 gen_helper_0e1i(mtc0_watchlo, arg, sel);
6888 register_name = "WatchLo";
6889 break;
6890 default:
6891 goto cp0_unimplemented;
6892 }
6893 break;
6894 case CP0_REGISTER_19:
6895 switch (sel) {
6896 case CP0_REG19__WATCHHI0:
6897 case CP0_REG19__WATCHHI1:
6898 case CP0_REG19__WATCHHI2:
6899 case CP0_REG19__WATCHHI3:
6900 case CP0_REG19__WATCHHI4:
6901 case CP0_REG19__WATCHHI5:
6902 case CP0_REG19__WATCHHI6:
6903 case CP0_REG19__WATCHHI7:
6904 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
6905 gen_helper_0e1i(mtc0_watchhi, arg, sel);
6906 register_name = "WatchHi";
6907 break;
6908 default:
6909 goto cp0_unimplemented;
6910 }
6911 break;
6912 case CP0_REGISTER_20:
6913 switch (sel) {
6914 case CP0_REG20__XCONTEXT:
6915 #if defined(TARGET_MIPS64)
6916 check_insn(ctx, ISA_MIPS3);
6917 gen_helper_mtc0_xcontext(cpu_env, arg);
6918 register_name = "XContext";
6919 break;
6920 #endif
6921 default:
6922 goto cp0_unimplemented;
6923 }
6924 break;
6925 case CP0_REGISTER_21:
6926 /* Officially reserved, but sel 0 is used for R1x000 framemask */
6927 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
6928 switch (sel) {
6929 case 0:
6930 gen_helper_mtc0_framemask(cpu_env, arg);
6931 register_name = "Framemask";
6932 break;
6933 default:
6934 goto cp0_unimplemented;
6935 }
6936 break;
6937 case CP0_REGISTER_22:
6938 /* ignored */
6939 register_name = "Diagnostic"; /* implementation dependent */
6940 break;
6941 case CP0_REGISTER_23:
6942 switch (sel) {
6943 case CP0_REG23__DEBUG:
6944 gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
6945 /* DISAS_STOP isn't good enough here, hflags may have changed. */
6946 gen_save_pc(ctx->base.pc_next + 4);
6947 ctx->base.is_jmp = DISAS_EXIT;
6948 register_name = "Debug";
6949 break;
6950 case CP0_REG23__TRACECONTROL:
6951 /* PDtrace support */
6952 /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
6953 register_name = "TraceControl";
6954 /* Stop translation as we may have switched the execution mode */
6955 ctx->base.is_jmp = DISAS_STOP;
6956 goto cp0_unimplemented;
6957 case CP0_REG23__TRACECONTROL2:
6958 /* PDtrace support */
6959 /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
6960 register_name = "TraceControl2";
6961 /* Stop translation as we may have switched the execution mode */
6962 ctx->base.is_jmp = DISAS_STOP;
6963 goto cp0_unimplemented;
6964 case CP0_REG23__USERTRACEDATA1:
6965 /* Stop translation as we may have switched the execution mode */
6966 ctx->base.is_jmp = DISAS_STOP;
6967 /* PDtrace support */
6968 /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
6969 register_name = "UserTraceData";
6970 /* Stop translation as we may have switched the execution mode */
6971 ctx->base.is_jmp = DISAS_STOP;
6972 goto cp0_unimplemented;
6973 case CP0_REG23__TRACEIBPC:
6974 /* PDtrace support */
6975 /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
6976 /* Stop translation as we may have switched the execution mode */
6977 ctx->base.is_jmp = DISAS_STOP;
6978 register_name = "TraceIBPC";
6979 goto cp0_unimplemented;
6980 case CP0_REG23__TRACEDBPC:
6981 /* PDtrace support */
6982 /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
6983 /* Stop translation as we may have switched the execution mode */
6984 ctx->base.is_jmp = DISAS_STOP;
6985 register_name = "TraceDBPC";
6986 goto cp0_unimplemented;
6987 default:
6988 goto cp0_unimplemented;
6989 }
6990 break;
6991 case CP0_REGISTER_24:
6992 switch (sel) {
6993 case CP0_REG24__DEPC:
6994 /* EJTAG support */
6995 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
6996 register_name = "DEPC";
6997 break;
6998 default:
6999 goto cp0_unimplemented;
7000 }
7001 break;
7002 case CP0_REGISTER_25:
7003 switch (sel) {
7004 case CP0_REG25__PERFCTL0:
7005 gen_helper_mtc0_performance0(cpu_env, arg);
7006 register_name = "Performance0";
7007 break;
7008 case CP0_REG25__PERFCNT0:
7009 /* gen_helper_mtc0_performance1(arg); */
7010 register_name = "Performance1";
7011 goto cp0_unimplemented;
7012 case CP0_REG25__PERFCTL1:
7013 /* gen_helper_mtc0_performance2(arg); */
7014 register_name = "Performance2";
7015 goto cp0_unimplemented;
7016 case CP0_REG25__PERFCNT1:
7017 /* gen_helper_mtc0_performance3(arg); */
7018 register_name = "Performance3";
7019 goto cp0_unimplemented;
7020 case CP0_REG25__PERFCTL2:
7021 /* gen_helper_mtc0_performance4(arg); */
7022 register_name = "Performance4";
7023 goto cp0_unimplemented;
7024 case CP0_REG25__PERFCNT2:
7025 /* gen_helper_mtc0_performance5(arg); */
7026 register_name = "Performance5";
7027 goto cp0_unimplemented;
7028 case CP0_REG25__PERFCTL3:
7029 /* gen_helper_mtc0_performance6(arg); */
7030 register_name = "Performance6";
7031 goto cp0_unimplemented;
7032 case CP0_REG25__PERFCNT3:
7033 /* gen_helper_mtc0_performance7(arg); */
7034 register_name = "Performance7";
7035 goto cp0_unimplemented;
7036 default:
7037 goto cp0_unimplemented;
7038 }
7039 break;
7040 case CP0_REGISTER_26:
7041 switch (sel) {
7042 case CP0_REG26__ERRCTL:
7043 gen_helper_mtc0_errctl(cpu_env, arg);
7044 ctx->base.is_jmp = DISAS_STOP;
7045 register_name = "ErrCtl";
7046 break;
7047 default:
7048 goto cp0_unimplemented;
7049 }
7050 break;
7051 case CP0_REGISTER_27:
7052 switch (sel) {
7053 case CP0_REG27__CACHERR:
7054 /* ignored */
7055 register_name = "CacheErr";
7056 break;
7057 default:
7058 goto cp0_unimplemented;
7059 }
7060 break;
7061 case CP0_REGISTER_28:
7062 switch (sel) {
7063 case CP0_REG28__TAGLO:
7064 case CP0_REG28__TAGLO1:
7065 case CP0_REG28__TAGLO2:
7066 case CP0_REG28__TAGLO3:
7067 gen_helper_mtc0_taglo(cpu_env, arg);
7068 register_name = "TagLo";
7069 break;
7070 case CP0_REG28__DATALO:
7071 case CP0_REG28__DATALO1:
7072 case CP0_REG28__DATALO2:
7073 case CP0_REG28__DATALO3:
7074 gen_helper_mtc0_datalo(cpu_env, arg);
7075 register_name = "DataLo";
7076 break;
7077 default:
7078 goto cp0_unimplemented;
7079 }
7080 break;
7081 case CP0_REGISTER_29:
7082 switch (sel) {
7083 case CP0_REG29__TAGHI:
7084 case CP0_REG29__TAGHI1:
7085 case CP0_REG29__TAGHI2:
7086 case CP0_REG29__TAGHI3:
7087 gen_helper_mtc0_taghi(cpu_env, arg);
7088 register_name = "TagHi";
7089 break;
7090 case CP0_REG29__DATAHI:
7091 case CP0_REG29__DATAHI1:
7092 case CP0_REG29__DATAHI2:
7093 case CP0_REG29__DATAHI3:
7094 gen_helper_mtc0_datahi(cpu_env, arg);
7095 register_name = "DataHi";
7096 break;
7097 default:
7098 register_name = "invalid sel";
7099 goto cp0_unimplemented;
7100 }
7101 break;
7102 case CP0_REGISTER_30:
7103 switch (sel) {
7104 case CP0_REG30__ERROREPC:
7105 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
7106 register_name = "ErrorEPC";
7107 break;
7108 default:
7109 goto cp0_unimplemented;
7110 }
7111 break;
7112 case CP0_REGISTER_31:
7113 switch (sel) {
7114 case CP0_REG31__DESAVE:
7115 /* EJTAG support */
7116 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
7117 register_name = "DESAVE";
7118 break;
7119 case CP0_REG31__KSCRATCH1:
7120 case CP0_REG31__KSCRATCH2:
7121 case CP0_REG31__KSCRATCH3:
7122 case CP0_REG31__KSCRATCH4:
7123 case CP0_REG31__KSCRATCH5:
7124 case CP0_REG31__KSCRATCH6:
7125 CP0_CHECK(ctx->kscrexist & (1 << sel));
7126 tcg_gen_st_tl(arg, cpu_env,
7127 offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
7128 register_name = "KScratch";
7129 break;
7130 default:
7131 goto cp0_unimplemented;
7132 }
7133 break;
7134 default:
7135 goto cp0_unimplemented;
7136 }
7137 trace_mips_translate_c0("mtc0", register_name, reg, sel);
7138
7139 /* For simplicity assume that all writes can cause interrupts. */
7140 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
7141 /*
7142 * DISAS_STOP isn't sufficient, we need to ensure we break out of
7143 * translated code to check for pending interrupts.
7144 */
7145 gen_save_pc(ctx->base.pc_next + 4);
7146 ctx->base.is_jmp = DISAS_EXIT;
7147 }
7148 return;
7149
7150 cp0_unimplemented:
7151 qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n",
7152 register_name, reg, sel);
7153 }
7154
7155 #if defined(TARGET_MIPS64)
7156 static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
7157 {
7158 const char *register_name = "invalid";
7159
7160 if (sel != 0) {
7161 check_insn(ctx, ISA_MIPS_R1);
7162 }
7163
7164 switch (reg) {
7165 case CP0_REGISTER_00:
7166 switch (sel) {
7167 case CP0_REG00__INDEX:
7168 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
7169 register_name = "Index";
7170 break;
7171 case CP0_REG00__MVPCONTROL:
7172 CP0_CHECK(ctx->insn_flags & ASE_MT);
7173 gen_helper_mfc0_mvpcontrol(arg, cpu_env);
7174 register_name = "MVPControl";
7175 break;
7176 case CP0_REG00__MVPCONF0:
7177 CP0_CHECK(ctx->insn_flags & ASE_MT);
7178 gen_helper_mfc0_mvpconf0(arg, cpu_env);
7179 register_name = "MVPConf0";
7180 break;
7181 case CP0_REG00__MVPCONF1:
7182 CP0_CHECK(ctx->insn_flags & ASE_MT);
7183 gen_helper_mfc0_mvpconf1(arg, cpu_env);
7184 register_name = "MVPConf1";
7185 break;
7186 case CP0_REG00__VPCONTROL:
7187 CP0_CHECK(ctx->vp);
7188 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
7189 register_name = "VPControl";
7190 break;
7191 default:
7192 goto cp0_unimplemented;
7193 }
7194 break;
7195 case CP0_REGISTER_01:
7196 switch (sel) {
7197 case CP0_REG01__RANDOM:
7198 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
7199 gen_helper_mfc0_random(arg, cpu_env);
7200 register_name = "Random";
7201 break;
7202 case CP0_REG01__VPECONTROL:
7203 CP0_CHECK(ctx->insn_flags & ASE_MT);
7204 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
7205 register_name = "VPEControl";
7206 break;
7207 case CP0_REG01__VPECONF0:
7208 CP0_CHECK(ctx->insn_flags & ASE_MT);
7209 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
7210 register_name = "VPEConf0";
7211 break;
7212 case CP0_REG01__VPECONF1:
7213 CP0_CHECK(ctx->insn_flags & ASE_MT);
7214 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
7215 register_name = "VPEConf1";
7216 break;
7217 case CP0_REG01__YQMASK:
7218 CP0_CHECK(ctx->insn_flags & ASE_MT);
7219 tcg_gen_ld_tl(arg, cpu_env,
7220 offsetof(CPUMIPSState, CP0_YQMask));
7221 register_name = "YQMask";
7222 break;
7223 case CP0_REG01__VPESCHEDULE:
7224 CP0_CHECK(ctx->insn_flags & ASE_MT);
7225 tcg_gen_ld_tl(arg, cpu_env,
7226 offsetof(CPUMIPSState, CP0_VPESchedule));
7227 register_name = "VPESchedule";
7228 break;
7229 case CP0_REG01__VPESCHEFBACK:
7230 CP0_CHECK(ctx->insn_flags & ASE_MT);
7231 tcg_gen_ld_tl(arg, cpu_env,
7232 offsetof(CPUMIPSState, CP0_VPEScheFBack));
7233 register_name = "VPEScheFBack";
7234 break;
7235 case CP0_REG01__VPEOPT:
7236 CP0_CHECK(ctx->insn_flags & ASE_MT);
7237 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
7238 register_name = "VPEOpt";
7239 break;
7240 default:
7241 goto cp0_unimplemented;
7242 }
7243 break;
7244 case CP0_REGISTER_02:
7245 switch (sel) {
7246 case CP0_REG02__ENTRYLO0:
7247 tcg_gen_ld_tl(arg, cpu_env,
7248 offsetof(CPUMIPSState, CP0_EntryLo0));
7249 register_name = "EntryLo0";
7250 break;
7251 case CP0_REG02__TCSTATUS:
7252 CP0_CHECK(ctx->insn_flags & ASE_MT);
7253 gen_helper_mfc0_tcstatus(arg, cpu_env);
7254 register_name = "TCStatus";
7255 break;
7256 case CP0_REG02__TCBIND:
7257 CP0_CHECK(ctx->insn_flags & ASE_MT);
7258 gen_helper_mfc0_tcbind(arg, cpu_env);
7259 register_name = "TCBind";
7260 break;
7261 case CP0_REG02__TCRESTART:
7262 CP0_CHECK(ctx->insn_flags & ASE_MT);
7263 gen_helper_dmfc0_tcrestart(arg, cpu_env);
7264 register_name = "TCRestart";
7265 break;
7266 case CP0_REG02__TCHALT:
7267 CP0_CHECK(ctx->insn_flags & ASE_MT);
7268 gen_helper_dmfc0_tchalt(arg, cpu_env);
7269 register_name = "TCHalt";
7270 break;
7271 case CP0_REG02__TCCONTEXT:
7272 CP0_CHECK(ctx->insn_flags & ASE_MT);
7273 gen_helper_dmfc0_tccontext(arg, cpu_env);
7274 register_name = "TCContext";
7275 break;
7276 case CP0_REG02__TCSCHEDULE:
7277 CP0_CHECK(ctx->insn_flags & ASE_MT);
7278 gen_helper_dmfc0_tcschedule(arg, cpu_env);
7279 register_name = "TCSchedule";
7280 break;
7281 case CP0_REG02__TCSCHEFBACK:
7282 CP0_CHECK(ctx->insn_flags & ASE_MT);
7283 gen_helper_dmfc0_tcschefback(arg, cpu_env);
7284 register_name = "TCScheFBack";
7285 break;
7286 default:
7287 goto cp0_unimplemented;
7288 }
7289 break;
7290 case CP0_REGISTER_03:
7291 switch (sel) {
7292 case CP0_REG03__ENTRYLO1:
7293 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
7294 register_name = "EntryLo1";
7295 break;
7296 case CP0_REG03__GLOBALNUM:
7297 CP0_CHECK(ctx->vp);
7298 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
7299 register_name = "GlobalNumber";
7300 break;
7301 default:
7302 goto cp0_unimplemented;
7303 }
7304 break;
7305 case CP0_REGISTER_04:
7306 switch (sel) {
7307 case CP0_REG04__CONTEXT:
7308 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
7309 register_name = "Context";
7310 break;
7311 case CP0_REG04__CONTEXTCONFIG:
7312 /* SmartMIPS ASE */
7313 /* gen_helper_dmfc0_contextconfig(arg); */
7314 register_name = "ContextConfig";
7315 goto cp0_unimplemented;
7316 case CP0_REG04__USERLOCAL:
7317 CP0_CHECK(ctx->ulri);
7318 tcg_gen_ld_tl(arg, cpu_env,
7319 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
7320 register_name = "UserLocal";
7321 break;
7322 case CP0_REG04__MMID:
7323 CP0_CHECK(ctx->mi);
7324 gen_helper_mtc0_memorymapid(cpu_env, arg);
7325 register_name = "MMID";
7326 break;
7327 default:
7328 goto cp0_unimplemented;
7329 }
7330 break;
7331 case CP0_REGISTER_05:
7332 switch (sel) {
7333 case CP0_REG05__PAGEMASK:
7334 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
7335 register_name = "PageMask";
7336 break;
7337 case CP0_REG05__PAGEGRAIN:
7338 check_insn(ctx, ISA_MIPS_R2);
7339 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
7340 register_name = "PageGrain";
7341 break;
7342 case CP0_REG05__SEGCTL0:
7343 CP0_CHECK(ctx->sc);
7344 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
7345 register_name = "SegCtl0";
7346 break;
7347 case CP0_REG05__SEGCTL1:
7348 CP0_CHECK(ctx->sc);
7349 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
7350 register_name = "SegCtl1";
7351 break;
7352 case CP0_REG05__SEGCTL2:
7353 CP0_CHECK(ctx->sc);
7354 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
7355 register_name = "SegCtl2";
7356 break;
7357 case CP0_REG05__PWBASE:
7358 check_pw(ctx);
7359 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
7360 register_name = "PWBase";
7361 break;
7362 case CP0_REG05__PWFIELD:
7363 check_pw(ctx);
7364 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
7365 register_name = "PWField";
7366 break;
7367 case CP0_REG05__PWSIZE:
7368 check_pw(ctx);
7369 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
7370 register_name = "PWSize";
7371 break;
7372 default:
7373 goto cp0_unimplemented;
7374 }
7375 break;
7376 case CP0_REGISTER_06:
7377 switch (sel) {
7378 case CP0_REG06__WIRED:
7379 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
7380 register_name = "Wired";
7381 break;
7382 case CP0_REG06__SRSCONF0:
7383 check_insn(ctx, ISA_MIPS_R2);
7384 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
7385 register_name = "SRSConf0";
7386 break;
7387 case CP0_REG06__SRSCONF1:
7388 check_insn(ctx, ISA_MIPS_R2);
7389 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
7390 register_name = "SRSConf1";
7391 break;
7392 case CP0_REG06__SRSCONF2:
7393 check_insn(ctx, ISA_MIPS_R2);
7394 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
7395 register_name = "SRSConf2";
7396 break;
7397 case CP0_REG06__SRSCONF3:
7398 check_insn(ctx, ISA_MIPS_R2);
7399 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
7400 register_name = "SRSConf3";
7401 break;
7402 case CP0_REG06__SRSCONF4:
7403 check_insn(ctx, ISA_MIPS_R2);
7404 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
7405 register_name = "SRSConf4";
7406 break;
7407 case CP0_REG06__PWCTL:
7408 check_pw(ctx);
7409 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
7410 register_name = "PWCtl";
7411 break;
7412 default:
7413 goto cp0_unimplemented;
7414 }
7415 break;
7416 case CP0_REGISTER_07:
7417 switch (sel) {
7418 case CP0_REG07__HWRENA:
7419 check_insn(ctx, ISA_MIPS_R2);
7420 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
7421 register_name = "HWREna";
7422 break;
7423 default:
7424 goto cp0_unimplemented;
7425 }
7426 break;
7427 case CP0_REGISTER_08:
7428 switch (sel) {
7429 case CP0_REG08__BADVADDR:
7430 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
7431 register_name = "BadVAddr";
7432 break;
7433 case CP0_REG08__BADINSTR:
7434 CP0_CHECK(ctx->bi);
7435 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
7436 register_name = "BadInstr";
7437 break;
7438 case CP0_REG08__BADINSTRP:
7439 CP0_CHECK(ctx->bp);
7440 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
7441 register_name = "BadInstrP";
7442 break;
7443 case CP0_REG08__BADINSTRX:
7444 CP0_CHECK(ctx->bi);
7445 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
7446 tcg_gen_andi_tl(arg, arg, ~0xffff);
7447 register_name = "BadInstrX";
7448 break;
7449 default:
7450 goto cp0_unimplemented;
7451 }
7452 break;
7453 case CP0_REGISTER_09:
7454 switch (sel) {
7455 case CP0_REG09__COUNT:
7456 /* Mark as an IO operation because we read the time. */
7457 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
7458 gen_io_start();
7459 }
7460 gen_helper_mfc0_count(arg, cpu_env);
7461 /*
7462 * Break the TB to be able to take timer interrupts immediately
7463 * after reading count. DISAS_STOP isn't sufficient, we need to
7464 * ensure we break completely out of translated code.
7465 */
7466 gen_save_pc(ctx->base.pc_next + 4);
7467 ctx->base.is_jmp = DISAS_EXIT;
7468 register_name = "Count";
7469 break;
7470 case CP0_REG09__SAARI:
7471 CP0_CHECK(ctx->saar);
7472 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
7473 register_name = "SAARI";
7474 break;
7475 case CP0_REG09__SAAR:
7476 CP0_CHECK(ctx->saar);
7477 gen_helper_dmfc0_saar(arg, cpu_env);
7478 register_name = "SAAR";
7479 break;
7480 default:
7481 goto cp0_unimplemented;
7482 }
7483 break;
7484 case CP0_REGISTER_10:
7485 switch (sel) {
7486 case CP0_REG10__ENTRYHI:
7487 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
7488 register_name = "EntryHi";
7489 break;
7490 default:
7491 goto cp0_unimplemented;
7492 }
7493 break;
7494 case CP0_REGISTER_11:
7495 switch (sel) {
7496 case CP0_REG11__COMPARE:
7497 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
7498 register_name = "Compare";
7499 break;
7500 /* 6,7 are implementation dependent */
7501 default:
7502 goto cp0_unimplemented;
7503 }
7504 break;
7505 case CP0_REGISTER_12:
7506 switch (sel) {
7507 case CP0_REG12__STATUS:
7508 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
7509 register_name = "Status";
7510 break;
7511 case CP0_REG12__INTCTL:
7512 check_insn(ctx, ISA_MIPS_R2);
7513 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
7514 register_name = "IntCtl";
7515 break;
7516 case CP0_REG12__SRSCTL:
7517 check_insn(ctx, ISA_MIPS_R2);
7518 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
7519 register_name = "SRSCtl";
7520 break;
7521 case CP0_REG12__SRSMAP:
7522 check_insn(ctx, ISA_MIPS_R2);
7523 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
7524 register_name = "SRSMap";
7525 break;
7526 default:
7527 goto cp0_unimplemented;
7528 }
7529 break;
7530 case CP0_REGISTER_13:
7531 switch (sel) {
7532 case CP0_REG13__CAUSE:
7533 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
7534 register_name = "Cause";
7535 break;
7536 default:
7537 goto cp0_unimplemented;
7538 }
7539 break;
7540 case CP0_REGISTER_14:
7541 switch (sel) {
7542 case CP0_REG14__EPC:
7543 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
7544 register_name = "EPC";
7545 break;
7546 default:
7547 goto cp0_unimplemented;
7548 }
7549 break;
7550 case CP0_REGISTER_15:
7551 switch (sel) {
7552 case CP0_REG15__PRID:
7553 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
7554 register_name = "PRid";
7555 break;
7556 case CP0_REG15__EBASE:
7557 check_insn(ctx, ISA_MIPS_R2);
7558 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
7559 register_name = "EBase";
7560 break;
7561 case CP0_REG15__CMGCRBASE:
7562 check_insn(ctx, ISA_MIPS_R2);
7563 CP0_CHECK(ctx->cmgcr);
7564 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
7565 register_name = "CMGCRBase";
7566 break;
7567 default:
7568 goto cp0_unimplemented;
7569 }
7570 break;
7571 case CP0_REGISTER_16:
7572 switch (sel) {
7573 case CP0_REG16__CONFIG:
7574 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
7575 register_name = "Config";
7576 break;
7577 case CP0_REG16__CONFIG1:
7578 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
7579 register_name = "Config1";
7580 break;
7581 case CP0_REG16__CONFIG2:
7582 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
7583 register_name = "Config2";
7584 break;
7585 case CP0_REG16__CONFIG3:
7586 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
7587 register_name = "Config3";
7588 break;
7589 case CP0_REG16__CONFIG4:
7590 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
7591 register_name = "Config4";
7592 break;
7593 case CP0_REG16__CONFIG5:
7594 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
7595 register_name = "Config5";
7596 break;
7597 /* 6,7 are implementation dependent */
7598 case CP0_REG16__CONFIG6:
7599 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
7600 register_name = "Config6";
7601 break;
7602 case CP0_REG16__CONFIG7:
7603 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
7604 register_name = "Config7";
7605 break;
7606 default:
7607 goto cp0_unimplemented;
7608 }
7609 break;
7610 case CP0_REGISTER_17:
7611 switch (sel) {
7612 case CP0_REG17__LLADDR:
7613 gen_helper_dmfc0_lladdr(arg, cpu_env);
7614 register_name = "LLAddr";
7615 break;
7616 case CP0_REG17__MAAR:
7617 CP0_CHECK(ctx->mrp);
7618 gen_helper_dmfc0_maar(arg, cpu_env);
7619 register_name = "MAAR";
7620 break;
7621 case CP0_REG17__MAARI:
7622 CP0_CHECK(ctx->mrp);
7623 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
7624 register_name = "MAARI";
7625 break;
7626 default:
7627 goto cp0_unimplemented;
7628 }
7629 break;
7630 case CP0_REGISTER_18:
7631 switch (sel) {
7632 case CP0_REG18__WATCHLO0:
7633 case CP0_REG18__WATCHLO1:
7634 case CP0_REG18__WATCHLO2:
7635 case CP0_REG18__WATCHLO3:
7636 case CP0_REG18__WATCHLO4:
7637 case CP0_REG18__WATCHLO5:
7638 case CP0_REG18__WATCHLO6:
7639 case CP0_REG18__WATCHLO7:
7640 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
7641 gen_helper_1e0i(dmfc0_watchlo, arg, sel);
7642 register_name = "WatchLo";
7643 break;
7644 default:
7645 goto cp0_unimplemented;
7646 }
7647 break;
7648 case CP0_REGISTER_19:
7649 switch (sel) {
7650 case CP0_REG19__WATCHHI0:
7651 case CP0_REG19__WATCHHI1:
7652 case CP0_REG19__WATCHHI2:
7653 case CP0_REG19__WATCHHI3:
7654 case CP0_REG19__WATCHHI4:
7655 case CP0_REG19__WATCHHI5:
7656 case CP0_REG19__WATCHHI6:
7657 case CP0_REG19__WATCHHI7:
7658 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
7659 gen_helper_1e0i(dmfc0_watchhi, arg, sel);
7660 register_name = "WatchHi";
7661 break;
7662 default:
7663 goto cp0_unimplemented;
7664 }
7665 break;
7666 case CP0_REGISTER_20:
7667 switch (sel) {
7668 case CP0_REG20__XCONTEXT:
7669 check_insn(ctx, ISA_MIPS3);
7670 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
7671 register_name = "XContext";
7672 break;
7673 default:
7674 goto cp0_unimplemented;
7675 }
7676 break;
7677 case CP0_REGISTER_21:
7678 /* Officially reserved, but sel 0 is used for R1x000 framemask */
7679 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
7680 switch (sel) {
7681 case 0:
7682 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
7683 register_name = "Framemask";
7684 break;
7685 default:
7686 goto cp0_unimplemented;
7687 }
7688 break;
7689 case CP0_REGISTER_22:
7690 tcg_gen_movi_tl(arg, 0); /* unimplemented */
7691 register_name = "'Diagnostic"; /* implementation dependent */
7692 break;
7693 case CP0_REGISTER_23:
7694 switch (sel) {
7695 case CP0_REG23__DEBUG:
7696 gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
7697 register_name = "Debug";
7698 break;
7699 case CP0_REG23__TRACECONTROL:
7700 /* PDtrace support */
7701 /* gen_helper_dmfc0_tracecontrol(arg, cpu_env); */
7702 register_name = "TraceControl";
7703 goto cp0_unimplemented;
7704 case CP0_REG23__TRACECONTROL2:
7705 /* PDtrace support */
7706 /* gen_helper_dmfc0_tracecontrol2(arg, cpu_env); */
7707 register_name = "TraceControl2";
7708 goto cp0_unimplemented;
7709 case CP0_REG23__USERTRACEDATA1:
7710 /* PDtrace support */
7711 /* gen_helper_dmfc0_usertracedata1(arg, cpu_env);*/
7712 register_name = "UserTraceData1";
7713 goto cp0_unimplemented;
7714 case CP0_REG23__TRACEIBPC:
7715 /* PDtrace support */
7716 /* gen_helper_dmfc0_traceibpc(arg, cpu_env); */
7717 register_name = "TraceIBPC";
7718 goto cp0_unimplemented;
7719 case CP0_REG23__TRACEDBPC:
7720 /* PDtrace support */
7721 /* gen_helper_dmfc0_tracedbpc(arg, cpu_env); */
7722 register_name = "TraceDBPC";
7723 goto cp0_unimplemented;
7724 default:
7725 goto cp0_unimplemented;
7726 }
7727 break;
7728 case CP0_REGISTER_24:
7729 switch (sel) {
7730 case CP0_REG24__DEPC:
7731 /* EJTAG support */
7732 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
7733 register_name = "DEPC";
7734 break;
7735 default:
7736 goto cp0_unimplemented;
7737 }
7738 break;
7739 case CP0_REGISTER_25:
7740 switch (sel) {
7741 case CP0_REG25__PERFCTL0:
7742 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
7743 register_name = "Performance0";
7744 break;
7745 case CP0_REG25__PERFCNT0:
7746 /* gen_helper_dmfc0_performance1(arg); */
7747 register_name = "Performance1";
7748 goto cp0_unimplemented;
7749 case CP0_REG25__PERFCTL1:
7750 /* gen_helper_dmfc0_performance2(arg); */
7751 register_name = "Performance2";
7752 goto cp0_unimplemented;
7753 case CP0_REG25__PERFCNT1:
7754 /* gen_helper_dmfc0_performance3(arg); */
7755 register_name = "Performance3";
7756 goto cp0_unimplemented;
7757 case CP0_REG25__PERFCTL2:
7758 /* gen_helper_dmfc0_performance4(arg); */
7759 register_name = "Performance4";
7760 goto cp0_unimplemented;
7761 case CP0_REG25__PERFCNT2:
7762 /* gen_helper_dmfc0_performance5(arg); */
7763 register_name = "Performance5";
7764 goto cp0_unimplemented;
7765 case CP0_REG25__PERFCTL3:
7766 /* gen_helper_dmfc0_performance6(arg); */
7767 register_name = "Performance6";
7768 goto cp0_unimplemented;
7769 case CP0_REG25__PERFCNT3:
7770 /* gen_helper_dmfc0_performance7(arg); */
7771 register_name = "Performance7";
7772 goto cp0_unimplemented;
7773 default:
7774 goto cp0_unimplemented;
7775 }
7776 break;
7777 case CP0_REGISTER_26:
7778 switch (sel) {
7779 case CP0_REG26__ERRCTL:
7780 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
7781 register_name = "ErrCtl";
7782 break;
7783 default:
7784 goto cp0_unimplemented;
7785 }
7786 break;
7787 case CP0_REGISTER_27:
7788 switch (sel) {
7789 /* ignored */
7790 case CP0_REG27__CACHERR:
7791 tcg_gen_movi_tl(arg, 0); /* unimplemented */
7792 register_name = "CacheErr";
7793 break;
7794 default:
7795 goto cp0_unimplemented;
7796 }
7797 break;
7798 case CP0_REGISTER_28:
7799 switch (sel) {
7800 case CP0_REG28__TAGLO:
7801 case CP0_REG28__TAGLO1:
7802 case CP0_REG28__TAGLO2:
7803 case CP0_REG28__TAGLO3:
7804 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
7805 register_name = "TagLo";
7806 break;
7807 case CP0_REG28__DATALO:
7808 case CP0_REG28__DATALO1:
7809 case CP0_REG28__DATALO2:
7810 case CP0_REG28__DATALO3:
7811 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
7812 register_name = "DataLo";
7813 break;
7814 default:
7815 goto cp0_unimplemented;
7816 }
7817 break;
7818 case CP0_REGISTER_29:
7819 switch (sel) {
7820 case CP0_REG29__TAGHI:
7821 case CP0_REG29__TAGHI1:
7822 case CP0_REG29__TAGHI2:
7823 case CP0_REG29__TAGHI3:
7824 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
7825 register_name = "TagHi";
7826 break;
7827 case CP0_REG29__DATAHI:
7828 case CP0_REG29__DATAHI1:
7829 case CP0_REG29__DATAHI2:
7830 case CP0_REG29__DATAHI3:
7831 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
7832 register_name = "DataHi";
7833 break;
7834 default:
7835 goto cp0_unimplemented;
7836 }
7837 break;
7838 case CP0_REGISTER_30:
7839 switch (sel) {
7840 case CP0_REG30__ERROREPC:
7841 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
7842 register_name = "ErrorEPC";
7843 break;
7844 default:
7845 goto cp0_unimplemented;
7846 }
7847 break;
7848 case CP0_REGISTER_31:
7849 switch (sel) {
7850 case CP0_REG31__DESAVE:
7851 /* EJTAG support */
7852 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
7853 register_name = "DESAVE";
7854 break;
7855 case CP0_REG31__KSCRATCH1:
7856 case CP0_REG31__KSCRATCH2:
7857 case CP0_REG31__KSCRATCH3:
7858 case CP0_REG31__KSCRATCH4:
7859 case CP0_REG31__KSCRATCH5:
7860 case CP0_REG31__KSCRATCH6:
7861 CP0_CHECK(ctx->kscrexist & (1 << sel));
7862 tcg_gen_ld_tl(arg, cpu_env,
7863 offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
7864 register_name = "KScratch";
7865 break;
7866 default:
7867 goto cp0_unimplemented;
7868 }
7869 break;
7870 default:
7871 goto cp0_unimplemented;
7872 }
7873 trace_mips_translate_c0("dmfc0", register_name, reg, sel);
7874 return;
7875
7876 cp0_unimplemented:
7877 qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n",
7878 register_name, reg, sel);
7879 gen_mfc0_unimplemented(ctx, arg);
7880 }
7881
7882 static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
7883 {
7884 const char *register_name = "invalid";
7885
7886 if (sel != 0) {
7887 check_insn(ctx, ISA_MIPS_R1);
7888 }
7889
7890 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
7891 gen_io_start();
7892 }
7893
7894 switch (reg) {
7895 case CP0_REGISTER_00:
7896 switch (sel) {
7897 case CP0_REG00__INDEX:
7898 gen_helper_mtc0_index(cpu_env, arg);
7899 register_name = "Index";
7900 break;
7901 case CP0_REG00__MVPCONTROL:
7902 CP0_CHECK(ctx->insn_flags & ASE_MT);
7903 gen_helper_mtc0_mvpcontrol(cpu_env, arg);
7904 register_name = "MVPControl";
7905 break;
7906 case CP0_REG00__MVPCONF0:
7907 CP0_CHECK(ctx->insn_flags & ASE_MT);
7908 /* ignored */
7909 register_name = "MVPConf0";
7910 break;
7911 case CP0_REG00__MVPCONF1:
7912 CP0_CHECK(ctx->insn_flags & ASE_MT);
7913 /* ignored */
7914 register_name = "MVPConf1";
7915 break;
7916 case CP0_REG00__VPCONTROL:
7917 CP0_CHECK(ctx->vp);
7918 /* ignored */
7919 register_name = "VPControl";
7920 break;
7921 default:
7922 goto cp0_unimplemented;
7923 }
7924 break;
7925 case CP0_REGISTER_01:
7926 switch (sel) {
7927 case CP0_REG01__RANDOM:
7928 /* ignored */
7929 register_name = "Random";
7930 break;
7931 case CP0_REG01__VPECONTROL:
7932 CP0_CHECK(ctx->insn_flags & ASE_MT);
7933 gen_helper_mtc0_vpecontrol(cpu_env, arg);
7934 register_name = "VPEControl";
7935 break;
7936 case CP0_REG01__VPECONF0:
7937 CP0_CHECK(ctx->insn_flags & ASE_MT);
7938 gen_helper_mtc0_vpeconf0(cpu_env, arg);
7939 register_name = "VPEConf0";
7940 break;
7941 case CP0_REG01__VPECONF1:
7942 CP0_CHECK(ctx->insn_flags & ASE_MT);
7943 gen_helper_mtc0_vpeconf1(cpu_env, arg);
7944 register_name = "VPEConf1";
7945 break;
7946 case CP0_REG01__YQMASK:
7947 CP0_CHECK(ctx->insn_flags & ASE_MT);
7948 gen_helper_mtc0_yqmask(cpu_env, arg);
7949 register_name = "YQMask";
7950 break;
7951 case CP0_REG01__VPESCHEDULE:
7952 CP0_CHECK(ctx->insn_flags & ASE_MT);
7953 tcg_gen_st_tl(arg, cpu_env,
7954 offsetof(CPUMIPSState, CP0_VPESchedule));
7955 register_name = "VPESchedule";
7956 break;
7957 case CP0_REG01__VPESCHEFBACK:
7958 CP0_CHECK(ctx->insn_flags & ASE_MT);
7959 tcg_gen_st_tl(arg, cpu_env,
7960 offsetof(CPUMIPSState, CP0_VPEScheFBack));
7961 register_name = "VPEScheFBack";
7962 break;
7963 case CP0_REG01__VPEOPT:
7964 CP0_CHECK(ctx->insn_flags & ASE_MT);
7965 gen_helper_mtc0_vpeopt(cpu_env, arg);
7966 register_name = "VPEOpt";
7967 break;
7968 default:
7969 goto cp0_unimplemented;
7970 }
7971 break;
7972 case CP0_REGISTER_02:
7973 switch (sel) {
7974 case CP0_REG02__ENTRYLO0:
7975 gen_helper_dmtc0_entrylo0(cpu_env, arg);
7976 register_name = "EntryLo0";
7977 break;
7978 case CP0_REG02__TCSTATUS:
7979 CP0_CHECK(ctx->insn_flags & ASE_MT);
7980 gen_helper_mtc0_tcstatus(cpu_env, arg);
7981 register_name = "TCStatus";
7982 break;
7983 case CP0_REG02__TCBIND:
7984 CP0_CHECK(ctx->insn_flags & ASE_MT);
7985 gen_helper_mtc0_tcbind(cpu_env, arg);
7986 register_name = "TCBind";
7987 break;
7988 case CP0_REG02__TCRESTART:
7989 CP0_CHECK(ctx->insn_flags & ASE_MT);
7990 gen_helper_mtc0_tcrestart(cpu_env, arg);
7991 register_name = "TCRestart";
7992 break;
7993 case CP0_REG02__TCHALT:
7994 CP0_CHECK(ctx->insn_flags & ASE_MT);
7995 gen_helper_mtc0_tchalt(cpu_env, arg);
7996 register_name = "TCHalt";
7997 break;
7998 case CP0_REG02__TCCONTEXT:
7999 CP0_CHECK(ctx->insn_flags & ASE_MT);
8000 gen_helper_mtc0_tccontext(cpu_env, arg);
8001 register_name = "TCContext";
8002 break;
8003 case CP0_REG02__TCSCHEDULE:
8004 CP0_CHECK(ctx->insn_flags & ASE_MT);
8005 gen_helper_mtc0_tcschedule(cpu_env, arg);
8006 register_name = "TCSchedule";
8007 break;
8008 case CP0_REG02__TCSCHEFBACK:
8009 CP0_CHECK(ctx->insn_flags & ASE_MT);
8010 gen_helper_mtc0_tcschefback(cpu_env, arg);
8011 register_name = "TCScheFBack";
8012 break;
8013 default:
8014 goto cp0_unimplemented;
8015 }
8016 break;
8017 case CP0_REGISTER_03:
8018 switch (sel) {
8019 case CP0_REG03__ENTRYLO1:
8020 gen_helper_dmtc0_entrylo1(cpu_env, arg);
8021 register_name = "EntryLo1";
8022 break;
8023 case CP0_REG03__GLOBALNUM:
8024 CP0_CHECK(ctx->vp);
8025 /* ignored */
8026 register_name = "GlobalNumber";
8027 break;
8028 default:
8029 goto cp0_unimplemented;
8030 }
8031 break;
8032 case CP0_REGISTER_04:
8033 switch (sel) {
8034 case CP0_REG04__CONTEXT:
8035 gen_helper_mtc0_context(cpu_env, arg);
8036 register_name = "Context";
8037 break;
8038 case CP0_REG04__CONTEXTCONFIG:
8039 /* SmartMIPS ASE */
8040 /* gen_helper_dmtc0_contextconfig(arg); */
8041 register_name = "ContextConfig";
8042 goto cp0_unimplemented;
8043 case CP0_REG04__USERLOCAL:
8044 CP0_CHECK(ctx->ulri);
8045 tcg_gen_st_tl(arg, cpu_env,
8046 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
8047 register_name = "UserLocal";
8048 break;
8049 case CP0_REG04__MMID:
8050 CP0_CHECK(ctx->mi);
8051 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID));
8052 register_name = "MMID";
8053 break;
8054 default:
8055 goto cp0_unimplemented;
8056 }
8057 break;
8058 case CP0_REGISTER_05:
8059 switch (sel) {
8060 case CP0_REG05__PAGEMASK:
8061 gen_helper_mtc0_pagemask(cpu_env, arg);
8062 register_name = "PageMask";
8063 break;
8064 case CP0_REG05__PAGEGRAIN:
8065 check_insn(ctx, ISA_MIPS_R2);
8066 gen_helper_mtc0_pagegrain(cpu_env, arg);
8067 register_name = "PageGrain";
8068 break;
8069 case CP0_REG05__SEGCTL0:
8070 CP0_CHECK(ctx->sc);
8071 gen_helper_mtc0_segctl0(cpu_env, arg);
8072 register_name = "SegCtl0";
8073 break;
8074 case CP0_REG05__SEGCTL1:
8075 CP0_CHECK(ctx->sc);
8076 gen_helper_mtc0_segctl1(cpu_env, arg);
8077 register_name = "SegCtl1";
8078 break;
8079 case CP0_REG05__SEGCTL2:
8080 CP0_CHECK(ctx->sc);
8081 gen_helper_mtc0_segctl2(cpu_env, arg);
8082 register_name = "SegCtl2";
8083 break;
8084 case CP0_REG05__PWBASE:
8085 check_pw(ctx);
8086 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
8087 register_name = "PWBase";
8088 break;
8089 case CP0_REG05__PWFIELD:
8090 check_pw(ctx);
8091 gen_helper_mtc0_pwfield(cpu_env, arg);
8092 register_name = "PWField";
8093 break;
8094 case CP0_REG05__PWSIZE:
8095 check_pw(ctx);
8096 gen_helper_mtc0_pwsize(cpu_env, arg);
8097 register_name = "PWSize";
8098 break;
8099 default:
8100 goto cp0_unimplemented;
8101 }
8102 break;
8103 case CP0_REGISTER_06:
8104 switch (sel) {
8105 case CP0_REG06__WIRED:
8106 gen_helper_mtc0_wired(cpu_env, arg);
8107 register_name = "Wired";
8108 break;
8109 case CP0_REG06__SRSCONF0:
8110 check_insn(ctx, ISA_MIPS_R2);
8111 gen_helper_mtc0_srsconf0(cpu_env, arg);
8112 register_name = "SRSConf0";
8113 break;
8114 case CP0_REG06__SRSCONF1:
8115 check_insn(ctx, ISA_MIPS_R2);
8116 gen_helper_mtc0_srsconf1(cpu_env, arg);
8117 register_name = "SRSConf1";
8118 break;
8119 case CP0_REG06__SRSCONF2:
8120 check_insn(ctx, ISA_MIPS_R2);
8121 gen_helper_mtc0_srsconf2(cpu_env, arg);
8122 register_name = "SRSConf2";
8123 break;
8124 case CP0_REG06__SRSCONF3:
8125 check_insn(ctx, ISA_MIPS_R2);
8126 gen_helper_mtc0_srsconf3(cpu_env, arg);
8127 register_name = "SRSConf3";
8128 break;
8129 case CP0_REG06__SRSCONF4:
8130 check_insn(ctx, ISA_MIPS_R2);
8131 gen_helper_mtc0_srsconf4(cpu_env, arg);
8132 register_name = "SRSConf4";
8133 break;
8134 case CP0_REG06__PWCTL:
8135 check_pw(ctx);
8136 gen_helper_mtc0_pwctl(cpu_env, arg);
8137 register_name = "PWCtl";
8138 break;
8139 default:
8140 goto cp0_unimplemented;
8141 }
8142 break;
8143 case CP0_REGISTER_07:
8144 switch (sel) {
8145 case CP0_REG07__HWRENA:
8146 check_insn(ctx, ISA_MIPS_R2);
8147 gen_helper_mtc0_hwrena(cpu_env, arg);
8148 ctx->base.is_jmp = DISAS_STOP;
8149 register_name = "HWREna";
8150 break;
8151 default:
8152 goto cp0_unimplemented;
8153 }
8154 break;
8155 case CP0_REGISTER_08:
8156 switch (sel) {
8157 case CP0_REG08__BADVADDR:
8158 /* ignored */
8159 register_name = "BadVAddr";
8160 break;
8161 case CP0_REG08__BADINSTR:
8162 /* ignored */
8163 register_name = "BadInstr";
8164 break;
8165 case CP0_REG08__BADINSTRP:
8166 /* ignored */
8167 register_name = "BadInstrP";
8168 break;
8169 case CP0_REG08__BADINSTRX:
8170 /* ignored */
8171 register_name = "BadInstrX";
8172 break;
8173 default:
8174 goto cp0_unimplemented;
8175 }
8176 break;
8177 case CP0_REGISTER_09:
8178 switch (sel) {
8179 case CP0_REG09__COUNT:
8180 gen_helper_mtc0_count(cpu_env, arg);
8181 register_name = "Count";
8182 break;
8183 case CP0_REG09__SAARI:
8184 CP0_CHECK(ctx->saar);
8185 gen_helper_mtc0_saari(cpu_env, arg);
8186 register_name = "SAARI";
8187 break;
8188 case CP0_REG09__SAAR:
8189 CP0_CHECK(ctx->saar);
8190 gen_helper_mtc0_saar(cpu_env, arg);
8191 register_name = "SAAR";
8192 break;
8193 default:
8194 goto cp0_unimplemented;
8195 }
8196 /* Stop translation as we may have switched the execution mode */
8197 ctx->base.is_jmp = DISAS_STOP;
8198 break;
8199 case CP0_REGISTER_10:
8200 switch (sel) {
8201 case CP0_REG10__ENTRYHI:
8202 gen_helper_mtc0_entryhi(cpu_env, arg);
8203 register_name = "EntryHi";
8204 break;
8205 default:
8206 goto cp0_unimplemented;
8207 }
8208 break;
8209 case CP0_REGISTER_11:
8210 switch (sel) {
8211 case CP0_REG11__COMPARE:
8212 gen_helper_mtc0_compare(cpu_env, arg);
8213 register_name = "Compare";
8214 break;
8215 /* 6,7 are implementation dependent */
8216 default:
8217 goto cp0_unimplemented;
8218 }
8219 /* Stop translation as we may have switched the execution mode */
8220 ctx->base.is_jmp = DISAS_STOP;
8221 break;
8222 case CP0_REGISTER_12:
8223 switch (sel) {
8224 case CP0_REG12__STATUS:
8225 save_cpu_state(ctx, 1);
8226 gen_helper_mtc0_status(cpu_env, arg);
8227 /* DISAS_STOP isn't good enough here, hflags may have changed. */
8228 gen_save_pc(ctx->base.pc_next + 4);
8229 ctx->base.is_jmp = DISAS_EXIT;
8230 register_name = "Status";
8231 break;
8232 case CP0_REG12__INTCTL:
8233 check_insn(ctx, ISA_MIPS_R2);
8234 gen_helper_mtc0_intctl(cpu_env, arg);
8235 /* Stop translation as we may have switched the execution mode */
8236 ctx->base.is_jmp = DISAS_STOP;
8237 register_name = "IntCtl";
8238 break;
8239 case CP0_REG12__SRSCTL:
8240 check_insn(ctx, ISA_MIPS_R2);
8241 gen_helper_mtc0_srsctl(cpu_env, arg);
8242 /* Stop translation as we may have switched the execution mode */
8243 ctx->base.is_jmp = DISAS_STOP;
8244 register_name = "SRSCtl";
8245 break;
8246 case CP0_REG12__SRSMAP:
8247 check_insn(ctx, ISA_MIPS_R2);
8248 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
8249 /* Stop translation as we may have switched the execution mode */
8250 ctx->base.is_jmp = DISAS_STOP;
8251 register_name = "SRSMap";
8252 break;
8253 default:
8254 goto cp0_unimplemented;
8255 }
8256 break;
8257 case CP0_REGISTER_13:
8258 switch (sel) {
8259 case CP0_REG13__CAUSE:
8260 save_cpu_state(ctx, 1);
8261 gen_helper_mtc0_cause(cpu_env, arg);
8262 /*
8263 * Stop translation as we may have triggered an interrupt.
8264 * DISAS_STOP isn't sufficient, we need to ensure we break out of
8265 * translated code to check for pending interrupts.
8266 */
8267 gen_save_pc(ctx->base.pc_next + 4);
8268 ctx->base.is_jmp = DISAS_EXIT;
8269 register_name = "Cause";
8270 break;
8271 default:
8272 goto cp0_unimplemented;
8273 }
8274 break;
8275 case CP0_REGISTER_14:
8276 switch (sel) {
8277 case CP0_REG14__EPC:
8278 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
8279 register_name = "EPC";
8280 break;
8281 default:
8282 goto cp0_unimplemented;
8283 }
8284 break;
8285 case CP0_REGISTER_15:
8286 switch (sel) {
8287 case CP0_REG15__PRID:
8288 /* ignored */
8289 register_name = "PRid";
8290 break;
8291 case CP0_REG15__EBASE:
8292 check_insn(ctx, ISA_MIPS_R2);
8293 gen_helper_mtc0_ebase(cpu_env, arg);
8294 register_name = "EBase";
8295 break;
8296 default:
8297 goto cp0_unimplemented;
8298 }
8299 break;
8300 case CP0_REGISTER_16:
8301 switch (sel) {
8302 case CP0_REG16__CONFIG:
8303 gen_helper_mtc0_config0(cpu_env, arg);
8304 register_name = "Config";
8305 /* Stop translation as we may have switched the execution mode */
8306 ctx->base.is_jmp = DISAS_STOP;
8307 break;
8308 case CP0_REG16__CONFIG1:
8309 /* ignored, read only */
8310 register_name = "Config1";
8311 break;
8312 case CP0_REG16__CONFIG2:
8313 gen_helper_mtc0_config2(cpu_env, arg);
8314 register_name = "Config2";
8315 /* Stop translation as we may have switched the execution mode */
8316 ctx->base.is_jmp = DISAS_STOP;
8317 break;
8318 case CP0_REG16__CONFIG3:
8319 gen_helper_mtc0_config3(cpu_env, arg);
8320 register_name = "Config3";
8321 /* Stop translation as we may have switched the execution mode */
8322 ctx->base.is_jmp = DISAS_STOP;
8323 break;
8324 case CP0_REG16__CONFIG4:
8325 /* currently ignored */
8326 register_name = "Config4";
8327 break;
8328 case CP0_REG16__CONFIG5:
8329 gen_helper_mtc0_config5(cpu_env, arg);
8330 register_name = "Config5";
8331 /* Stop translation as we may have switched the execution mode */
8332 ctx->base.is_jmp = DISAS_STOP;
8333 break;
8334 /* 6,7 are implementation dependent */
8335 default:
8336 register_name = "Invalid config selector";
8337 goto cp0_unimplemented;
8338 }
8339 break;
8340 case CP0_REGISTER_17:
8341 switch (sel) {
8342 case CP0_REG17__LLADDR:
8343 gen_helper_mtc0_lladdr(cpu_env, arg);
8344 register_name = "LLAddr";
8345 break;
8346 case CP0_REG17__MAAR:
8347 CP0_CHECK(ctx->mrp);
8348 gen_helper_mtc0_maar(cpu_env, arg);
8349 register_name = "MAAR";
8350 break;
8351 case CP0_REG17__MAARI:
8352 CP0_CHECK(ctx->mrp);
8353 gen_helper_mtc0_maari(cpu_env, arg);
8354 register_name = "MAARI";
8355 break;
8356 default:
8357 goto cp0_unimplemented;
8358 }
8359 break;
8360 case CP0_REGISTER_18:
8361 switch (sel) {
8362 case CP0_REG18__WATCHLO0:
8363 case CP0_REG18__WATCHLO1:
8364 case CP0_REG18__WATCHLO2:
8365 case CP0_REG18__WATCHLO3:
8366 case CP0_REG18__WATCHLO4:
8367 case CP0_REG18__WATCHLO5:
8368 case CP0_REG18__WATCHLO6:
8369 case CP0_REG18__WATCHLO7:
8370 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
8371 gen_helper_0e1i(mtc0_watchlo, arg, sel);
8372 register_name = "WatchLo";
8373 break;
8374 default:
8375 goto cp0_unimplemented;
8376 }
8377 break;
8378 case CP0_REGISTER_19:
8379 switch (sel) {
8380 case CP0_REG19__WATCHHI0:
8381 case CP0_REG19__WATCHHI1:
8382 case CP0_REG19__WATCHHI2:
8383 case CP0_REG19__WATCHHI3:
8384 case CP0_REG19__WATCHHI4:
8385 case CP0_REG19__WATCHHI5:
8386 case CP0_REG19__WATCHHI6:
8387 case CP0_REG19__WATCHHI7:
8388 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
8389 gen_helper_0e1i(mtc0_watchhi, arg, sel);
8390 register_name = "WatchHi";
8391 break;
8392 default:
8393 goto cp0_unimplemented;
8394 }
8395 break;
8396 case CP0_REGISTER_20:
8397 switch (sel) {
8398 case CP0_REG20__XCONTEXT:
8399 check_insn(ctx, ISA_MIPS3);
8400 gen_helper_mtc0_xcontext(cpu_env, arg);
8401 register_name = "XContext";
8402 break;
8403 default:
8404 goto cp0_unimplemented;
8405 }
8406 break;
8407 case CP0_REGISTER_21:
8408 /* Officially reserved, but sel 0 is used for R1x000 framemask */
8409 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
8410 switch (sel) {
8411 case 0:
8412 gen_helper_mtc0_framemask(cpu_env, arg);
8413 register_name = "Framemask";
8414 break;
8415 default:
8416 goto cp0_unimplemented;
8417 }
8418 break;
8419 case CP0_REGISTER_22:
8420 /* ignored */
8421 register_name = "Diagnostic"; /* implementation dependent */
8422 break;
8423 case CP0_REGISTER_23:
8424 switch (sel) {
8425 case CP0_REG23__DEBUG:
8426 gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
8427 /* DISAS_STOP isn't good enough here, hflags may have changed. */
8428 gen_save_pc(ctx->base.pc_next + 4);
8429 ctx->base.is_jmp = DISAS_EXIT;
8430 register_name = "Debug";
8431 break;
8432 case CP0_REG23__TRACECONTROL:
8433 /* PDtrace support */
8434 /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
8435 /* Stop translation as we may have switched the execution mode */
8436 ctx->base.is_jmp = DISAS_STOP;
8437 register_name = "TraceControl";
8438 goto cp0_unimplemented;
8439 case CP0_REG23__TRACECONTROL2:
8440 /* PDtrace support */
8441 /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
8442 /* Stop translation as we may have switched the execution mode */
8443 ctx->base.is_jmp = DISAS_STOP;
8444 register_name = "TraceControl2";
8445 goto cp0_unimplemented;
8446 case CP0_REG23__USERTRACEDATA1:
8447 /* PDtrace support */
8448 /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
8449 /* Stop translation as we may have switched the execution mode */
8450 ctx->base.is_jmp = DISAS_STOP;
8451 register_name = "UserTraceData1";
8452 goto cp0_unimplemented;
8453 case CP0_REG23__TRACEIBPC:
8454 /* PDtrace support */
8455 /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
8456 /* Stop translation as we may have switched the execution mode */
8457 ctx->base.is_jmp = DISAS_STOP;
8458 register_name = "TraceIBPC";
8459 goto cp0_unimplemented;
8460 case CP0_REG23__TRACEDBPC:
8461 /* PDtrace support */
8462 /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
8463 /* Stop translation as we may have switched the execution mode */
8464 ctx->base.is_jmp = DISAS_STOP;
8465 register_name = "TraceDBPC";
8466 goto cp0_unimplemented;
8467 default:
8468 goto cp0_unimplemented;
8469 }
8470 break;
8471 case CP0_REGISTER_24:
8472 switch (sel) {
8473 case CP0_REG24__DEPC:
8474 /* EJTAG support */
8475 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
8476 register_name = "DEPC";
8477 break;
8478 default:
8479 goto cp0_unimplemented;
8480 }
8481 break;
8482 case CP0_REGISTER_25:
8483 switch (sel) {
8484 case CP0_REG25__PERFCTL0:
8485 gen_helper_mtc0_performance0(cpu_env, arg);
8486 register_name = "Performance0";
8487 break;
8488 case CP0_REG25__PERFCNT0:
8489 /* gen_helper_mtc0_performance1(cpu_env, arg); */
8490 register_name = "Performance1";
8491 goto cp0_unimplemented;
8492 case CP0_REG25__PERFCTL1:
8493 /* gen_helper_mtc0_performance2(cpu_env, arg); */
8494 register_name = "Performance2";
8495 goto cp0_unimplemented;
8496 case CP0_REG25__PERFCNT1:
8497 /* gen_helper_mtc0_performance3(cpu_env, arg); */
8498 register_name = "Performance3";
8499 goto cp0_unimplemented;
8500 case CP0_REG25__PERFCTL2:
8501 /* gen_helper_mtc0_performance4(cpu_env, arg); */
8502 register_name = "Performance4";
8503 goto cp0_unimplemented;
8504 case CP0_REG25__PERFCNT2:
8505 /* gen_helper_mtc0_performance5(cpu_env, arg); */
8506 register_name = "Performance5";
8507 goto cp0_unimplemented;
8508 case CP0_REG25__PERFCTL3:
8509 /* gen_helper_mtc0_performance6(cpu_env, arg); */
8510 register_name = "Performance6";
8511 goto cp0_unimplemented;
8512 case CP0_REG25__PERFCNT3:
8513 /* gen_helper_mtc0_performance7(cpu_env, arg); */
8514 register_name = "Performance7";
8515 goto cp0_unimplemented;
8516 default:
8517 goto cp0_unimplemented;
8518 }
8519 break;
8520 case CP0_REGISTER_26:
8521 switch (sel) {
8522 case CP0_REG26__ERRCTL:
8523 gen_helper_mtc0_errctl(cpu_env, arg);
8524 ctx->base.is_jmp = DISAS_STOP;
8525 register_name = "ErrCtl";
8526 break;
8527 default:
8528 goto cp0_unimplemented;
8529 }
8530 break;
8531 case CP0_REGISTER_27:
8532 switch (sel) {
8533 case CP0_REG27__CACHERR:
8534 /* ignored */
8535 register_name = "CacheErr";
8536 break;
8537 default:
8538 goto cp0_unimplemented;
8539 }
8540 break;
8541 case CP0_REGISTER_28:
8542 switch (sel) {
8543 case CP0_REG28__TAGLO:
8544 case CP0_REG28__TAGLO1:
8545 case CP0_REG28__TAGLO2:
8546 case CP0_REG28__TAGLO3:
8547 gen_helper_mtc0_taglo(cpu_env, arg);
8548 register_name = "TagLo";
8549 break;
8550 case CP0_REG28__DATALO:
8551 case CP0_REG28__DATALO1:
8552 case CP0_REG28__DATALO2:
8553 case CP0_REG28__DATALO3:
8554 gen_helper_mtc0_datalo(cpu_env, arg);
8555 register_name = "DataLo";
8556 break;
8557 default:
8558 goto cp0_unimplemented;
8559 }
8560 break;
8561 case CP0_REGISTER_29:
8562 switch (sel) {
8563 case CP0_REG29__TAGHI:
8564 case CP0_REG29__TAGHI1:
8565 case CP0_REG29__TAGHI2:
8566 case CP0_REG29__TAGHI3:
8567 gen_helper_mtc0_taghi(cpu_env, arg);
8568 register_name = "TagHi";
8569 break;
8570 case CP0_REG29__DATAHI:
8571 case CP0_REG29__DATAHI1:
8572 case CP0_REG29__DATAHI2:
8573 case CP0_REG29__DATAHI3:
8574 gen_helper_mtc0_datahi(cpu_env, arg);
8575 register_name = "DataHi";
8576 break;
8577 default:
8578 register_name = "invalid sel";
8579 goto cp0_unimplemented;
8580 }
8581 break;
8582 case CP0_REGISTER_30:
8583 switch (sel) {
8584 case CP0_REG30__ERROREPC:
8585 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
8586 register_name = "ErrorEPC";
8587 break;
8588 default:
8589 goto cp0_unimplemented;
8590 }
8591 break;
8592 case CP0_REGISTER_31:
8593 switch (sel) {
8594 case CP0_REG31__DESAVE:
8595 /* EJTAG support */
8596 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
8597 register_name = "DESAVE";
8598 break;
8599 case CP0_REG31__KSCRATCH1:
8600 case CP0_REG31__KSCRATCH2:
8601 case CP0_REG31__KSCRATCH3:
8602 case CP0_REG31__KSCRATCH4:
8603 case CP0_REG31__KSCRATCH5:
8604 case CP0_REG31__KSCRATCH6:
8605 CP0_CHECK(ctx->kscrexist & (1 << sel));
8606 tcg_gen_st_tl(arg, cpu_env,
8607 offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
8608 register_name = "KScratch";
8609 break;
8610 default:
8611 goto cp0_unimplemented;
8612 }
8613 break;
8614 default:
8615 goto cp0_unimplemented;
8616 }
8617 trace_mips_translate_c0("dmtc0", register_name, reg, sel);
8618
8619 /* For simplicity assume that all writes can cause interrupts. */
8620 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
8621 /*
8622 * DISAS_STOP isn't sufficient, we need to ensure we break out of
8623 * translated code to check for pending interrupts.
8624 */
8625 gen_save_pc(ctx->base.pc_next + 4);
8626 ctx->base.is_jmp = DISAS_EXIT;
8627 }
8628 return;
8629
8630 cp0_unimplemented:
8631 qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n",
8632 register_name, reg, sel);
8633 }
8634 #endif /* TARGET_MIPS64 */
8635
8636 static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
8637 int u, int sel, int h)
8638 {
8639 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
8640 TCGv t0 = tcg_temp_local_new();
8641
8642 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
8643 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
8644 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
8645 tcg_gen_movi_tl(t0, -1);
8646 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
8647 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
8648 tcg_gen_movi_tl(t0, -1);
8649 } else if (u == 0) {
8650 switch (rt) {
8651 case 1:
8652 switch (sel) {
8653 case 1:
8654 gen_helper_mftc0_vpecontrol(t0, cpu_env);
8655 break;
8656 case 2:
8657 gen_helper_mftc0_vpeconf0(t0, cpu_env);
8658 break;
8659 default:
8660 goto die;
8661 break;
8662 }
8663 break;
8664 case 2:
8665 switch (sel) {
8666 case 1:
8667 gen_helper_mftc0_tcstatus(t0, cpu_env);
8668 break;
8669 case 2:
8670 gen_helper_mftc0_tcbind(t0, cpu_env);
8671 break;
8672 case 3:
8673 gen_helper_mftc0_tcrestart(t0, cpu_env);
8674 break;
8675 case 4:
8676 gen_helper_mftc0_tchalt(t0, cpu_env);
8677 break;
8678 case 5:
8679 gen_helper_mftc0_tccontext(t0, cpu_env);
8680 break;
8681 case 6:
8682 gen_helper_mftc0_tcschedule(t0, cpu_env);
8683 break;
8684 case 7:
8685 gen_helper_mftc0_tcschefback(t0, cpu_env);
8686 break;
8687 default:
8688 gen_mfc0(ctx, t0, rt, sel);
8689 break;
8690 }
8691 break;
8692 case 10:
8693 switch (sel) {
8694 case 0:
8695 gen_helper_mftc0_entryhi(t0, cpu_env);
8696 break;
8697 default:
8698 gen_mfc0(ctx, t0, rt, sel);
8699 break;
8700 }
8701 break;
8702 case 12:
8703 switch (sel) {
8704 case 0:
8705 gen_helper_mftc0_status(t0, cpu_env);
8706 break;
8707 default:
8708 gen_mfc0(ctx, t0, rt, sel);
8709 break;
8710 }
8711 break;
8712 case 13:
8713 switch (sel) {
8714 case 0:
8715 gen_helper_mftc0_cause(t0, cpu_env);
8716 break;
8717 default:
8718 goto die;
8719 break;
8720 }
8721 break;
8722 case 14:
8723 switch (sel) {
8724 case 0:
8725 gen_helper_mftc0_epc(t0, cpu_env);
8726 break;
8727 default:
8728 goto die;
8729 break;
8730 }
8731 break;
8732 case 15:
8733 switch (sel) {
8734 case 1:
8735 gen_helper_mftc0_ebase(t0, cpu_env);
8736 break;
8737 default:
8738 goto die;
8739 break;
8740 }
8741 break;
8742 case 16:
8743 switch (sel) {
8744 case 0:
8745 case 1:
8746 case 2:
8747 case 3:
8748 case 4:
8749 case 5:
8750 case 6:
8751 case 7:
8752 gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel));
8753 break;
8754 default:
8755 goto die;
8756 break;
8757 }
8758 break;
8759 case 23:
8760 switch (sel) {
8761 case 0:
8762 gen_helper_mftc0_debug(t0, cpu_env);
8763 break;
8764 default:
8765 gen_mfc0(ctx, t0, rt, sel);
8766 break;
8767 }
8768 break;
8769 default:
8770 gen_mfc0(ctx, t0, rt, sel);
8771 }
8772 } else {
8773 switch (sel) {
8774 /* GPR registers. */
8775 case 0:
8776 gen_helper_1e0i(mftgpr, t0, rt);
8777 break;
8778 /* Auxiliary CPU registers */
8779 case 1:
8780 switch (rt) {
8781 case 0:
8782 gen_helper_1e0i(mftlo, t0, 0);
8783 break;
8784 case 1:
8785 gen_helper_1e0i(mfthi, t0, 0);
8786 break;
8787 case 2:
8788 gen_helper_1e0i(mftacx, t0, 0);
8789 break;
8790 case 4:
8791 gen_helper_1e0i(mftlo, t0, 1);
8792 break;
8793 case 5:
8794 gen_helper_1e0i(mfthi, t0, 1);
8795 break;
8796 case 6:
8797 gen_helper_1e0i(mftacx, t0, 1);
8798 break;
8799 case 8:
8800 gen_helper_1e0i(mftlo, t0, 2);
8801 break;
8802 case 9:
8803 gen_helper_1e0i(mfthi, t0, 2);
8804 break;
8805 case 10:
8806 gen_helper_1e0i(mftacx, t0, 2);
8807 break;
8808 case 12:
8809 gen_helper_1e0i(mftlo, t0, 3);
8810 break;
8811 case 13:
8812 gen_helper_1e0i(mfthi, t0, 3);
8813 break;
8814 case 14:
8815 gen_helper_1e0i(mftacx, t0, 3);
8816 break;
8817 case 16:
8818 gen_helper_mftdsp(t0, cpu_env);
8819 break;
8820 default:
8821 goto die;
8822 }
8823 break;
8824 /* Floating point (COP1). */
8825 case 2:
8826 /* XXX: For now we support only a single FPU context. */
8827 if (h == 0) {
8828 TCGv_i32 fp0 = tcg_temp_new_i32();
8829
8830 gen_load_fpr32(ctx, fp0, rt);
8831 tcg_gen_ext_i32_tl(t0, fp0);
8832 tcg_temp_free_i32(fp0);
8833 } else {
8834 TCGv_i32 fp0 = tcg_temp_new_i32();
8835
8836 gen_load_fpr32h(ctx, fp0, rt);
8837 tcg_gen_ext_i32_tl(t0, fp0);
8838 tcg_temp_free_i32(fp0);
8839 }
8840 break;
8841 case 3:
8842 /* XXX: For now we support only a single FPU context. */
8843 gen_helper_1e0i(cfc1, t0, rt);
8844 break;
8845 /* COP2: Not implemented. */
8846 case 4:
8847 case 5:
8848 /* fall through */
8849 default:
8850 goto die;
8851 }
8852 }
8853 trace_mips_translate_tr("mftr", rt, u, sel, h);
8854 gen_store_gpr(t0, rd);
8855 tcg_temp_free(t0);
8856 return;
8857
8858 die:
8859 tcg_temp_free(t0);
8860 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
8861 gen_reserved_instruction(ctx);
8862 }
8863
8864 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
8865 int u, int sel, int h)
8866 {
8867 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
8868 TCGv t0 = tcg_temp_local_new();
8869
8870 gen_load_gpr(t0, rt);
8871 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
8872 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
8873 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
8874 /* NOP */
8875 ;
8876 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
8877 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
8878 /* NOP */
8879 ;
8880 } else if (u == 0) {
8881 switch (rd) {
8882 case 1:
8883 switch (sel) {
8884 case 1:
8885 gen_helper_mttc0_vpecontrol(cpu_env, t0);
8886 break;
8887 case 2:
8888 gen_helper_mttc0_vpeconf0(cpu_env, t0);
8889 break;
8890 default:
8891 goto die;
8892 break;
8893 }
8894 break;
8895 case 2:
8896 switch (sel) {
8897 case 1:
8898 gen_helper_mttc0_tcstatus(cpu_env, t0);
8899 break;
8900 case 2:
8901 gen_helper_mttc0_tcbind(cpu_env, t0);
8902 break;
8903 case 3:
8904 gen_helper_mttc0_tcrestart(cpu_env, t0);
8905 break;
8906 case 4:
8907 gen_helper_mttc0_tchalt(cpu_env, t0);
8908 break;
8909 case 5:
8910 gen_helper_mttc0_tccontext(cpu_env, t0);
8911 break;
8912 case 6:
8913 gen_helper_mttc0_tcschedule(cpu_env, t0);
8914 break;
8915 case 7:
8916 gen_helper_mttc0_tcschefback(cpu_env, t0);
8917 break;
8918 default:
8919 gen_mtc0(ctx, t0, rd, sel);
8920 break;
8921 }
8922 break;
8923 case 10:
8924 switch (sel) {
8925 case 0:
8926 gen_helper_mttc0_entryhi(cpu_env, t0);
8927 break;
8928 default:
8929 gen_mtc0(ctx, t0, rd, sel);
8930 break;
8931 }
8932 break;
8933 case 12:
8934 switch (sel) {
8935 case 0:
8936 gen_helper_mttc0_status(cpu_env, t0);
8937 break;
8938 default:
8939 gen_mtc0(ctx, t0, rd, sel);
8940 break;
8941 }
8942 break;
8943 case 13:
8944 switch (sel) {
8945 case 0:
8946 gen_helper_mttc0_cause(cpu_env, t0);
8947 break;
8948 default:
8949 goto die;
8950 break;
8951 }
8952 break;
8953 case 15:
8954 switch (sel) {
8955 case 1:
8956 gen_helper_mttc0_ebase(cpu_env, t0);
8957 break;
8958 default:
8959 goto die;
8960 break;
8961 }
8962 break;
8963 case 23:
8964 switch (sel) {
8965 case 0:
8966 gen_helper_mttc0_debug(cpu_env, t0);
8967 break;
8968 default:
8969 gen_mtc0(ctx, t0, rd, sel);
8970 break;
8971 }
8972 break;
8973 default:
8974 gen_mtc0(ctx, t0, rd, sel);
8975 }
8976 } else {
8977 switch (sel) {
8978 /* GPR registers. */
8979 case 0:
8980 gen_helper_0e1i(mttgpr, t0, rd);
8981 break;
8982 /* Auxiliary CPU registers */
8983 case 1:
8984 switch (rd) {
8985 case 0:
8986 gen_helper_0e1i(mttlo, t0, 0);
8987 break;
8988 case 1:
8989 gen_helper_0e1i(mtthi, t0, 0);
8990 break;
8991 case 2:
8992 gen_helper_0e1i(mttacx, t0, 0);
8993 break;
8994 case 4:
8995 gen_helper_0e1i(mttlo, t0, 1);
8996 break;
8997 case 5:
8998 gen_helper_0e1i(mtthi, t0, 1);
8999 break;
9000 case 6:
9001 gen_helper_0e1i(mttacx, t0, 1);
9002 break;
9003 case 8:
9004 gen_helper_0e1i(mttlo, t0, 2);
9005 break;
9006 case 9:
9007 gen_helper_0e1i(mtthi, t0, 2);
9008 break;
9009 case 10:
9010 gen_helper_0e1i(mttacx, t0, 2);
9011 break;
9012 case 12:
9013 gen_helper_0e1i(mttlo, t0, 3);
9014 break;
9015 case 13:
9016 gen_helper_0e1i(mtthi, t0, 3);
9017 break;
9018 case 14:
9019 gen_helper_0e1i(mttacx, t0, 3);
9020 break;
9021 case 16:
9022 gen_helper_mttdsp(cpu_env, t0);
9023 break;
9024 default:
9025 goto die;
9026 }
9027 break;
9028 /* Floating point (COP1). */
9029 case 2:
9030 /* XXX: For now we support only a single FPU context. */
9031 if (h == 0) {
9032 TCGv_i32 fp0 = tcg_temp_new_i32();
9033
9034 tcg_gen_trunc_tl_i32(fp0, t0);
9035 gen_store_fpr32(ctx, fp0, rd);
9036 tcg_temp_free_i32(fp0);
9037 } else {
9038 TCGv_i32 fp0 = tcg_temp_new_i32();
9039
9040 tcg_gen_trunc_tl_i32(fp0, t0);
9041 gen_store_fpr32h(ctx, fp0, rd);
9042 tcg_temp_free_i32(fp0);
9043 }
9044 break;
9045 case 3:
9046 /* XXX: For now we support only a single FPU context. */
9047 gen_helper_0e2i(ctc1, t0, tcg_constant_i32(rd), rt);
9048 /* Stop translation as we may have changed hflags */
9049 ctx->base.is_jmp = DISAS_STOP;
9050 break;
9051 /* COP2: Not implemented. */
9052 case 4:
9053 case 5:
9054 /* fall through */
9055 default:
9056 goto die;
9057 }
9058 }
9059 trace_mips_translate_tr("mttr", rd, u, sel, h);
9060 tcg_temp_free(t0);
9061 return;
9062
9063 die:
9064 tcg_temp_free(t0);
9065 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
9066 gen_reserved_instruction(ctx);
9067 }
9068
9069 static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
9070 int rt, int rd)
9071 {
9072 const char *opn = "ldst";
9073
9074 check_cp0_enabled(ctx);
9075 switch (opc) {
9076 case OPC_MFC0:
9077 if (rt == 0) {
9078 /* Treat as NOP. */
9079 return;
9080 }
9081 gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
9082 opn = "mfc0";
9083 break;
9084 case OPC_MTC0:
9085 {
9086 TCGv t0 = tcg_temp_new();
9087
9088 gen_load_gpr(t0, rt);
9089 gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7);
9090 tcg_temp_free(t0);
9091 }
9092 opn = "mtc0";
9093 break;
9094 #if defined(TARGET_MIPS64)
9095 case OPC_DMFC0:
9096 check_insn(ctx, ISA_MIPS3);
9097 if (rt == 0) {
9098 /* Treat as NOP. */
9099 return;
9100 }
9101 gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
9102 opn = "dmfc0";
9103 break;
9104 case OPC_DMTC0:
9105 check_insn(ctx, ISA_MIPS3);
9106 {
9107 TCGv t0 = tcg_temp_new();
9108
9109 gen_load_gpr(t0, rt);
9110 gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7);
9111 tcg_temp_free(t0);
9112 }
9113 opn = "dmtc0";
9114 break;
9115 #endif
9116 case OPC_MFHC0:
9117 check_mvh(ctx);
9118 if (rt == 0) {
9119 /* Treat as NOP. */
9120 return;
9121 }
9122 gen_mfhc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
9123 opn = "mfhc0";
9124 break;
9125 case OPC_MTHC0:
9126 check_mvh(ctx);
9127 {
9128 TCGv t0 = tcg_temp_new();
9129 gen_load_gpr(t0, rt);
9130 gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7);
9131 tcg_temp_free(t0);
9132 }
9133 opn = "mthc0";
9134 break;
9135 case OPC_MFTR:
9136 check_cp0_enabled(ctx);
9137 if (rd == 0) {
9138 /* Treat as NOP. */
9139 return;
9140 }
9141 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1,
9142 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
9143 opn = "mftr";
9144 break;
9145 case OPC_MTTR:
9146 check_cp0_enabled(ctx);
9147 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
9148 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
9149 opn = "mttr";
9150 break;
9151 case OPC_TLBWI:
9152 opn = "tlbwi";
9153 if (!env->tlb->helper_tlbwi) {
9154 goto die;
9155 }
9156 gen_helper_tlbwi(cpu_env);
9157 break;
9158 case OPC_TLBINV:
9159 opn = "tlbinv";
9160 if (ctx->ie >= 2) {
9161 if (!env->tlb->helper_tlbinv) {
9162 goto die;
9163 }
9164 gen_helper_tlbinv(cpu_env);
9165 } /* treat as nop if TLBINV not supported */
9166 break;
9167 case OPC_TLBINVF:
9168 opn = "tlbinvf";
9169 if (ctx->ie >= 2) {
9170 if (!env->tlb->helper_tlbinvf) {
9171 goto die;
9172 }
9173 gen_helper_tlbinvf(cpu_env);
9174 } /* treat as nop if TLBINV not supported */
9175 break;
9176 case OPC_TLBWR:
9177 opn = "tlbwr";
9178 if (!env->tlb->helper_tlbwr) {
9179 goto die;
9180 }
9181 gen_helper_tlbwr(cpu_env);
9182 break;
9183 case OPC_TLBP:
9184 opn = "tlbp";
9185 if (!env->tlb->helper_tlbp) {
9186 goto die;
9187 }
9188 gen_helper_tlbp(cpu_env);
9189 break;
9190 case OPC_TLBR:
9191 opn = "tlbr";
9192 if (!env->tlb->helper_tlbr) {
9193 goto die;
9194 }
9195 gen_helper_tlbr(cpu_env);
9196 break;
9197 case OPC_ERET: /* OPC_ERETNC */
9198 if ((ctx->insn_flags & ISA_MIPS_R6) &&
9199 (ctx->hflags & MIPS_HFLAG_BMASK)) {
9200 goto die;
9201 } else {
9202 int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6;
9203 if (ctx->opcode & (1 << bit_shift)) {
9204 /* OPC_ERETNC */
9205 opn = "eretnc";
9206 check_insn(ctx, ISA_MIPS_R5);
9207 gen_helper_eretnc(cpu_env);
9208 } else {
9209 /* OPC_ERET */
9210 opn = "eret";
9211 check_insn(ctx, ISA_MIPS2);
9212 gen_helper_eret(cpu_env);
9213 }
9214 ctx->base.is_jmp = DISAS_EXIT;
9215 }
9216 break;
9217 case OPC_DERET:
9218 opn = "deret";
9219 check_insn(ctx, ISA_MIPS_R1);
9220 if ((ctx->insn_flags & ISA_MIPS_R6) &&
9221 (ctx->hflags & MIPS_HFLAG_BMASK)) {
9222 goto die;
9223 }
9224 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
9225 MIPS_INVAL(opn);
9226 gen_reserved_instruction(ctx);
9227 } else {
9228 gen_helper_deret(cpu_env);
9229 ctx->base.is_jmp = DISAS_EXIT;
9230 }
9231 break;
9232 case OPC_WAIT:
9233 opn = "wait";
9234 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
9235 if ((ctx->insn_flags & ISA_MIPS_R6) &&
9236 (ctx->hflags & MIPS_HFLAG_BMASK)) {
9237 goto die;
9238 }
9239 /* If we get an exception, we want to restart at next instruction */
9240 ctx->base.pc_next += 4;
9241 save_cpu_state(ctx, 1);
9242 ctx->base.pc_next -= 4;
9243 gen_helper_wait(cpu_env);
9244 ctx->base.is_jmp = DISAS_NORETURN;
9245 break;
9246 default:
9247 die:
9248 MIPS_INVAL(opn);
9249 gen_reserved_instruction(ctx);
9250 return;
9251 }
9252 (void)opn; /* avoid a compiler warning */
9253 }
9254 #endif /* !CONFIG_USER_ONLY */
9255
9256 /* CP1 Branches (before delay slot) */
9257 static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
9258 int32_t cc, int32_t offset)
9259 {
9260 target_ulong btarget;
9261 TCGv_i32 t0 = tcg_temp_new_i32();
9262
9263 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) {
9264 gen_reserved_instruction(ctx);
9265 goto out;
9266 }
9267
9268 if (cc != 0) {
9269 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
9270 }
9271
9272 btarget = ctx->base.pc_next + 4 + offset;
9273
9274 switch (op) {
9275 case OPC_BC1F:
9276 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9277 tcg_gen_not_i32(t0, t0);
9278 tcg_gen_andi_i32(t0, t0, 1);
9279 tcg_gen_extu_i32_tl(bcond, t0);
9280 goto not_likely;
9281 case OPC_BC1FL:
9282 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9283 tcg_gen_not_i32(t0, t0);
9284 tcg_gen_andi_i32(t0, t0, 1);
9285 tcg_gen_extu_i32_tl(bcond, t0);
9286 goto likely;
9287 case OPC_BC1T:
9288 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9289 tcg_gen_andi_i32(t0, t0, 1);
9290 tcg_gen_extu_i32_tl(bcond, t0);
9291 goto not_likely;
9292 case OPC_BC1TL:
9293 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9294 tcg_gen_andi_i32(t0, t0, 1);
9295 tcg_gen_extu_i32_tl(bcond, t0);
9296 likely:
9297 ctx->hflags |= MIPS_HFLAG_BL;
9298 break;
9299 case OPC_BC1FANY2:
9300 {
9301 TCGv_i32 t1 = tcg_temp_new_i32();
9302 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9303 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
9304 tcg_gen_nand_i32(t0, t0, t1);
9305 tcg_temp_free_i32(t1);
9306 tcg_gen_andi_i32(t0, t0, 1);
9307 tcg_gen_extu_i32_tl(bcond, t0);
9308 }
9309 goto not_likely;
9310 case OPC_BC1TANY2:
9311 {
9312 TCGv_i32 t1 = tcg_temp_new_i32();
9313 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9314 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
9315 tcg_gen_or_i32(t0, t0, t1);
9316 tcg_temp_free_i32(t1);
9317 tcg_gen_andi_i32(t0, t0, 1);
9318 tcg_gen_extu_i32_tl(bcond, t0);
9319 }
9320 goto not_likely;
9321 case OPC_BC1FANY4:
9322 {
9323 TCGv_i32 t1 = tcg_temp_new_i32();
9324 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9325 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
9326 tcg_gen_and_i32(t0, t0, t1);
9327 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2));
9328 tcg_gen_and_i32(t0, t0, t1);
9329 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3));
9330 tcg_gen_nand_i32(t0, t0, t1);
9331 tcg_temp_free_i32(t1);
9332 tcg_gen_andi_i32(t0, t0, 1);
9333 tcg_gen_extu_i32_tl(bcond, t0);
9334 }
9335 goto not_likely;
9336 case OPC_BC1TANY4:
9337 {
9338 TCGv_i32 t1 = tcg_temp_new_i32();
9339 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
9340 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
9341 tcg_gen_or_i32(t0, t0, t1);
9342 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2));
9343 tcg_gen_or_i32(t0, t0, t1);
9344 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3));
9345 tcg_gen_or_i32(t0, t0, t1);
9346 tcg_temp_free_i32(t1);
9347 tcg_gen_andi_i32(t0, t0, 1);
9348 tcg_gen_extu_i32_tl(bcond, t0);
9349 }
9350 not_likely:
9351 ctx->hflags |= MIPS_HFLAG_BC;
9352 break;
9353 default:
9354 MIPS_INVAL("cp1 cond branch");
9355 gen_reserved_instruction(ctx);
9356 goto out;
9357 }
9358 ctx->btarget = btarget;
9359 ctx->hflags |= MIPS_HFLAG_BDS32;
9360 out:
9361 tcg_temp_free_i32(t0);
9362 }
9363
9364 /* R6 CP1 Branches */
9365 static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
9366 int32_t ft, int32_t offset,
9367 int delayslot_size)
9368 {
9369 target_ulong btarget;
9370 TCGv_i64 t0 = tcg_temp_new_i64();
9371
9372 if (ctx->hflags & MIPS_HFLAG_BMASK) {
9373 #ifdef MIPS_DEBUG_DISAS
9374 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
9375 "\n", ctx->base.pc_next);
9376 #endif
9377 gen_reserved_instruction(ctx);
9378 goto out;
9379 }
9380
9381 gen_load_fpr64(ctx, t0, ft);
9382 tcg_gen_andi_i64(t0, t0, 1);
9383
9384 btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
9385
9386 switch (op) {
9387 case OPC_BC1EQZ:
9388 tcg_gen_xori_i64(t0, t0, 1);
9389 ctx->hflags |= MIPS_HFLAG_BC;
9390 break;
9391 case OPC_BC1NEZ:
9392 /* t0 already set */
9393 ctx->hflags |= MIPS_HFLAG_BC;
9394 break;
9395 default:
9396 MIPS_INVAL("cp1 cond branch");
9397 gen_reserved_instruction(ctx);
9398 goto out;
9399 }
9400
9401 tcg_gen_trunc_i64_tl(bcond, t0);
9402
9403 ctx->btarget = btarget;
9404
9405 switch (delayslot_size) {
9406 case 2:
9407 ctx->hflags |= MIPS_HFLAG_BDS16;
9408 break;
9409 case 4:
9410 ctx->hflags |= MIPS_HFLAG_BDS32;
9411 break;
9412 }
9413
9414 out:
9415 tcg_temp_free_i64(t0);
9416 }
9417
9418 /* Coprocessor 1 (FPU) */
9419
9420 #define FOP(func, fmt) (((fmt) << 21) | (func))
9421
9422 enum fopcode {
9423 OPC_ADD_S = FOP(0, FMT_S),
9424 OPC_SUB_S = FOP(1, FMT_S),
9425 OPC_MUL_S = FOP(2, FMT_S),
9426 OPC_DIV_S = FOP(3, FMT_S),
9427 OPC_SQRT_S = FOP(4, FMT_S),
9428 OPC_ABS_S = FOP(5, FMT_S),
9429 OPC_MOV_S = FOP(6, FMT_S),
9430 OPC_NEG_S = FOP(7, FMT_S),
9431 OPC_ROUND_L_S = FOP(8, FMT_S),
9432 OPC_TRUNC_L_S = FOP(9, FMT_S),
9433 OPC_CEIL_L_S = FOP(10, FMT_S),
9434 OPC_FLOOR_L_S = FOP(11, FMT_S),
9435 OPC_ROUND_W_S = FOP(12, FMT_S),
9436 OPC_TRUNC_W_S = FOP(13, FMT_S),
9437 OPC_CEIL_W_S = FOP(14, FMT_S),
9438 OPC_FLOOR_W_S = FOP(15, FMT_S),
9439 OPC_SEL_S = FOP(16, FMT_S),
9440 OPC_MOVCF_S = FOP(17, FMT_S),
9441 OPC_MOVZ_S = FOP(18, FMT_S),
9442 OPC_MOVN_S = FOP(19, FMT_S),
9443 OPC_SELEQZ_S = FOP(20, FMT_S),
9444 OPC_RECIP_S = FOP(21, FMT_S),
9445 OPC_RSQRT_S = FOP(22, FMT_S),
9446 OPC_SELNEZ_S = FOP(23, FMT_S),
9447 OPC_MADDF_S = FOP(24, FMT_S),
9448 OPC_MSUBF_S = FOP(25, FMT_S),
9449 OPC_RINT_S = FOP(26, FMT_S),
9450 OPC_CLASS_S = FOP(27, FMT_S),
9451 OPC_MIN_S = FOP(28, FMT_S),
9452 OPC_RECIP2_S = FOP(28, FMT_S),
9453 OPC_MINA_S = FOP(29, FMT_S),
9454 OPC_RECIP1_S = FOP(29, FMT_S),
9455 OPC_MAX_S = FOP(30, FMT_S),
9456 OPC_RSQRT1_S = FOP(30, FMT_S),
9457 OPC_MAXA_S = FOP(31, FMT_S),
9458 OPC_RSQRT2_S = FOP(31, FMT_S),
9459 OPC_CVT_D_S = FOP(33, FMT_S),
9460 OPC_CVT_W_S = FOP(36, FMT_S),
9461 OPC_CVT_L_S = FOP(37, FMT_S),
9462 OPC_CVT_PS_S = FOP(38, FMT_S),
9463 OPC_CMP_F_S = FOP(48, FMT_S),
9464 OPC_CMP_UN_S = FOP(49, FMT_S),
9465 OPC_CMP_EQ_S = FOP(50, FMT_S),
9466 OPC_CMP_UEQ_S = FOP(51, FMT_S),
9467 OPC_CMP_OLT_S = FOP(52, FMT_S),
9468 OPC_CMP_ULT_S = FOP(53, FMT_S),
9469 OPC_CMP_OLE_S = FOP(54, FMT_S),
9470 OPC_CMP_ULE_S = FOP(55, FMT_S),
9471 OPC_CMP_SF_S = FOP(56, FMT_S),
9472 OPC_CMP_NGLE_S = FOP(57, FMT_S),
9473 OPC_CMP_SEQ_S = FOP(58, FMT_S),
9474 OPC_CMP_NGL_S = FOP(59, FMT_S),
9475 OPC_CMP_LT_S = FOP(60, FMT_S),
9476 OPC_CMP_NGE_S = FOP(61, FMT_S),
9477 OPC_CMP_LE_S = FOP(62, FMT_S),
9478 OPC_CMP_NGT_S = FOP(63, FMT_S),
9479
9480 OPC_ADD_D = FOP(0, FMT_D),
9481 OPC_SUB_D = FOP(1, FMT_D),
9482 OPC_MUL_D = FOP(2, FMT_D),
9483 OPC_DIV_D = FOP(3, FMT_D),
9484 OPC_SQRT_D = FOP(4, FMT_D),
9485 OPC_ABS_D = FOP(5, FMT_D),
9486 OPC_MOV_D = FOP(6, FMT_D),
9487 OPC_NEG_D = FOP(7, FMT_D),
9488 OPC_ROUND_L_D = FOP(8, FMT_D),
9489 OPC_TRUNC_L_D = FOP(9, FMT_D),
9490 OPC_CEIL_L_D = FOP(10, FMT_D),
9491 OPC_FLOOR_L_D = FOP(11, FMT_D),
9492 OPC_ROUND_W_D = FOP(12, FMT_D),
9493 OPC_TRUNC_W_D = FOP(13, FMT_D),
9494 OPC_CEIL_W_D = FOP(14, FMT_D),
9495 OPC_FLOOR_W_D = FOP(15, FMT_D),
9496 OPC_SEL_D = FOP(16, FMT_D),
9497 OPC_MOVCF_D = FOP(17, FMT_D),
9498 OPC_MOVZ_D = FOP(18, FMT_D),
9499 OPC_MOVN_D = FOP(19, FMT_D),
9500 OPC_SELEQZ_D = FOP(20, FMT_D),
9501 OPC_RECIP_D = FOP(21, FMT_D),
9502 OPC_RSQRT_D = FOP(22, FMT_D),
9503 OPC_SELNEZ_D = FOP(23, FMT_D),
9504 OPC_MADDF_D = FOP(24, FMT_D),
9505 OPC_MSUBF_D = FOP(25, FMT_D),
9506 OPC_RINT_D = FOP(26, FMT_D),
9507 OPC_CLASS_D = FOP(27, FMT_D),
9508 OPC_MIN_D = FOP(28, FMT_D),
9509 OPC_RECIP2_D = FOP(28, FMT_D),
9510 OPC_MINA_D = FOP(29, FMT_D),
9511 OPC_RECIP1_D = FOP(29, FMT_D),
9512 OPC_MAX_D = FOP(30, FMT_D),
9513 OPC_RSQRT1_D = FOP(30, FMT_D),
9514 OPC_MAXA_D = FOP(31, FMT_D),
9515 OPC_RSQRT2_D = FOP(31, FMT_D),
9516 OPC_CVT_S_D = FOP(32, FMT_D),
9517 OPC_CVT_W_D = FOP(36, FMT_D),
9518 OPC_CVT_L_D = FOP(37, FMT_D),
9519 OPC_CMP_F_D = FOP(48, FMT_D),
9520 OPC_CMP_UN_D = FOP(49, FMT_D),
9521 OPC_CMP_EQ_D = FOP(50, FMT_D),
9522 OPC_CMP_UEQ_D = FOP(51, FMT_D),
9523 OPC_CMP_OLT_D = FOP(52, FMT_D),
9524 OPC_CMP_ULT_D = FOP(53, FMT_D),
9525 OPC_CMP_OLE_D = FOP(54, FMT_D),
9526 OPC_CMP_ULE_D = FOP(55, FMT_D),
9527 OPC_CMP_SF_D = FOP(56, FMT_D),
9528 OPC_CMP_NGLE_D = FOP(57, FMT_D),
9529 OPC_CMP_SEQ_D = FOP(58, FMT_D),
9530 OPC_CMP_NGL_D = FOP(59, FMT_D),
9531 OPC_CMP_LT_D = FOP(60, FMT_D),
9532 OPC_CMP_NGE_D = FOP(61, FMT_D),
9533 OPC_CMP_LE_D = FOP(62, FMT_D),
9534 OPC_CMP_NGT_D = FOP(63, FMT_D),
9535
9536 OPC_CVT_S_W = FOP(32, FMT_W),
9537 OPC_CVT_D_W = FOP(33, FMT_W),
9538 OPC_CVT_S_L = FOP(32, FMT_L),
9539 OPC_CVT_D_L = FOP(33, FMT_L),
9540 OPC_CVT_PS_PW = FOP(38, FMT_W),
9541
9542 OPC_ADD_PS = FOP(0, FMT_PS),
9543 OPC_SUB_PS = FOP(1, FMT_PS),
9544 OPC_MUL_PS = FOP(2, FMT_PS),
9545 OPC_DIV_PS = FOP(3, FMT_PS),
9546 OPC_ABS_PS = FOP(5, FMT_PS),
9547 OPC_MOV_PS = FOP(6, FMT_PS),
9548 OPC_NEG_PS = FOP(7, FMT_PS),
9549 OPC_MOVCF_PS = FOP(17, FMT_PS),
9550 OPC_MOVZ_PS = FOP(18, FMT_PS),
9551 OPC_MOVN_PS = FOP(19, FMT_PS),
9552 OPC_ADDR_PS = FOP(24, FMT_PS),
9553 OPC_MULR_PS = FOP(26, FMT_PS),
9554 OPC_RECIP2_PS = FOP(28, FMT_PS),
9555 OPC_RECIP1_PS = FOP(29, FMT_PS),
9556 OPC_RSQRT1_PS = FOP(30, FMT_PS),
9557 OPC_RSQRT2_PS = FOP(31, FMT_PS),
9558
9559 OPC_CVT_S_PU = FOP(32, FMT_PS),
9560 OPC_CVT_PW_PS = FOP(36, FMT_PS),
9561 OPC_CVT_S_PL = FOP(40, FMT_PS),
9562 OPC_PLL_PS = FOP(44, FMT_PS),
9563 OPC_PLU_PS = FOP(45, FMT_PS),
9564 OPC_PUL_PS = FOP(46, FMT_PS),
9565 OPC_PUU_PS = FOP(47, FMT_PS),
9566 OPC_CMP_F_PS = FOP(48, FMT_PS),
9567 OPC_CMP_UN_PS = FOP(49, FMT_PS),
9568 OPC_CMP_EQ_PS = FOP(50, FMT_PS),
9569 OPC_CMP_UEQ_PS = FOP(51, FMT_PS),
9570 OPC_CMP_OLT_PS = FOP(52, FMT_PS),
9571 OPC_CMP_ULT_PS = FOP(53, FMT_PS),
9572 OPC_CMP_OLE_PS = FOP(54, FMT_PS),
9573 OPC_CMP_ULE_PS = FOP(55, FMT_PS),
9574 OPC_CMP_SF_PS = FOP(56, FMT_PS),
9575 OPC_CMP_NGLE_PS = FOP(57, FMT_PS),
9576 OPC_CMP_SEQ_PS = FOP(58, FMT_PS),
9577 OPC_CMP_NGL_PS = FOP(59, FMT_PS),
9578 OPC_CMP_LT_PS = FOP(60, FMT_PS),
9579 OPC_CMP_NGE_PS = FOP(61, FMT_PS),
9580 OPC_CMP_LE_PS = FOP(62, FMT_PS),
9581 OPC_CMP_NGT_PS = FOP(63, FMT_PS),
9582 };
9583
9584 enum r6_f_cmp_op {
9585 R6_OPC_CMP_AF_S = FOP(0, FMT_W),
9586 R6_OPC_CMP_UN_S = FOP(1, FMT_W),
9587 R6_OPC_CMP_EQ_S = FOP(2, FMT_W),
9588 R6_OPC_CMP_UEQ_S = FOP(3, FMT_W),
9589 R6_OPC_CMP_LT_S = FOP(4, FMT_W),
9590 R6_OPC_CMP_ULT_S = FOP(5, FMT_W),
9591 R6_OPC_CMP_LE_S = FOP(6, FMT_W),
9592 R6_OPC_CMP_ULE_S = FOP(7, FMT_W),
9593 R6_OPC_CMP_SAF_S = FOP(8, FMT_W),
9594 R6_OPC_CMP_SUN_S = FOP(9, FMT_W),
9595 R6_OPC_CMP_SEQ_S = FOP(10, FMT_W),
9596 R6_OPC_CMP_SEUQ_S = FOP(11, FMT_W),
9597 R6_OPC_CMP_SLT_S = FOP(12, FMT_W),
9598 R6_OPC_CMP_SULT_S = FOP(13, FMT_W),
9599 R6_OPC_CMP_SLE_S = FOP(14, FMT_W),
9600 R6_OPC_CMP_SULE_S = FOP(15, FMT_W),
9601 R6_OPC_CMP_OR_S = FOP(17, FMT_W),
9602 R6_OPC_CMP_UNE_S = FOP(18, FMT_W),
9603 R6_OPC_CMP_NE_S = FOP(19, FMT_W),
9604 R6_OPC_CMP_SOR_S = FOP(25, FMT_W),
9605 R6_OPC_CMP_SUNE_S = FOP(26, FMT_W),
9606 R6_OPC_CMP_SNE_S = FOP(27, FMT_W),
9607
9608 R6_OPC_CMP_AF_D = FOP(0, FMT_L),
9609 R6_OPC_CMP_UN_D = FOP(1, FMT_L),
9610 R6_OPC_CMP_EQ_D = FOP(2, FMT_L),
9611 R6_OPC_CMP_UEQ_D = FOP(3, FMT_L),
9612 R6_OPC_CMP_LT_D = FOP(4, FMT_L),
9613 R6_OPC_CMP_ULT_D = FOP(5, FMT_L),
9614 R6_OPC_CMP_LE_D = FOP(6, FMT_L),
9615 R6_OPC_CMP_ULE_D = FOP(7, FMT_L),
9616 R6_OPC_CMP_SAF_D = FOP(8, FMT_L),
9617 R6_OPC_CMP_SUN_D = FOP(9, FMT_L),
9618 R6_OPC_CMP_SEQ_D = FOP(10, FMT_L),
9619 R6_OPC_CMP_SEUQ_D = FOP(11, FMT_L),
9620 R6_OPC_CMP_SLT_D = FOP(12, FMT_L),
9621 R6_OPC_CMP_SULT_D = FOP(13, FMT_L),
9622 R6_OPC_CMP_SLE_D = FOP(14, FMT_L),
9623 R6_OPC_CMP_SULE_D = FOP(15, FMT_L),
9624 R6_OPC_CMP_OR_D = FOP(17, FMT_L),
9625 R6_OPC_CMP_UNE_D = FOP(18, FMT_L),
9626 R6_OPC_CMP_NE_D = FOP(19, FMT_L),
9627 R6_OPC_CMP_SOR_D = FOP(25, FMT_L),
9628 R6_OPC_CMP_SUNE_D = FOP(26, FMT_L),
9629 R6_OPC_CMP_SNE_D = FOP(27, FMT_L),
9630 };
9631
9632 static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs)
9633 {
9634 TCGv t0 = tcg_temp_new();
9635
9636 switch (opc) {
9637 case OPC_MFC1:
9638 {
9639 TCGv_i32 fp0 = tcg_temp_new_i32();
9640
9641 gen_load_fpr32(ctx, fp0, fs);
9642 tcg_gen_ext_i32_tl(t0, fp0);
9643 tcg_temp_free_i32(fp0);
9644 }
9645 gen_store_gpr(t0, rt);
9646 break;
9647 case OPC_MTC1:
9648 gen_load_gpr(t0, rt);
9649 {
9650 TCGv_i32 fp0 = tcg_temp_new_i32();
9651
9652 tcg_gen_trunc_tl_i32(fp0, t0);
9653 gen_store_fpr32(ctx, fp0, fs);
9654 tcg_temp_free_i32(fp0);
9655 }
9656 break;
9657 case OPC_CFC1:
9658 gen_helper_1e0i(cfc1, t0, fs);
9659 gen_store_gpr(t0, rt);
9660 break;
9661 case OPC_CTC1:
9662 gen_load_gpr(t0, rt);
9663 save_cpu_state(ctx, 0);
9664 gen_helper_0e2i(ctc1, t0, tcg_constant_i32(fs), rt);
9665 /* Stop translation as we may have changed hflags */
9666 ctx->base.is_jmp = DISAS_STOP;
9667 break;
9668 #if defined(TARGET_MIPS64)
9669 case OPC_DMFC1:
9670 gen_load_fpr64(ctx, t0, fs);
9671 gen_store_gpr(t0, rt);
9672 break;
9673 case OPC_DMTC1:
9674 gen_load_gpr(t0, rt);
9675 gen_store_fpr64(ctx, t0, fs);
9676 break;
9677 #endif
9678 case OPC_MFHC1:
9679 {
9680 TCGv_i32 fp0 = tcg_temp_new_i32();
9681
9682 gen_load_fpr32h(ctx, fp0, fs);
9683 tcg_gen_ext_i32_tl(t0, fp0);
9684 tcg_temp_free_i32(fp0);
9685 }
9686 gen_store_gpr(t0, rt);
9687 break;
9688 case OPC_MTHC1:
9689 gen_load_gpr(t0, rt);
9690 {
9691 TCGv_i32 fp0 = tcg_temp_new_i32();
9692
9693 tcg_gen_trunc_tl_i32(fp0, t0);
9694 gen_store_fpr32h(ctx, fp0, fs);
9695 tcg_temp_free_i32(fp0);
9696 }
9697 break;
9698 default:
9699 MIPS_INVAL("cp1 move");
9700 gen_reserved_instruction(ctx);
9701 goto out;
9702 }
9703
9704 out:
9705 tcg_temp_free(t0);
9706 }
9707
9708 static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf)
9709 {
9710 TCGLabel *l1;
9711 TCGCond cond;
9712 TCGv_i32 t0;
9713
9714 if (rd == 0) {
9715 /* Treat as NOP. */
9716 return;
9717 }
9718
9719 if (tf) {
9720 cond = TCG_COND_EQ;
9721 } else {
9722 cond = TCG_COND_NE;
9723 }
9724
9725 l1 = gen_new_label();
9726 t0 = tcg_temp_new_i32();
9727 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
9728 tcg_gen_brcondi_i32(cond, t0, 0, l1);
9729 tcg_temp_free_i32(t0);
9730 gen_load_gpr(cpu_gpr[rd], rs);
9731 gen_set_label(l1);
9732 }
9733
9734 static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,
9735 int tf)
9736 {
9737 int cond;
9738 TCGv_i32 t0 = tcg_temp_new_i32();
9739 TCGLabel *l1 = gen_new_label();
9740
9741 if (tf) {
9742 cond = TCG_COND_EQ;
9743 } else {
9744 cond = TCG_COND_NE;
9745 }
9746
9747 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
9748 tcg_gen_brcondi_i32(cond, t0, 0, l1);
9749 gen_load_fpr32(ctx, t0, fs);
9750 gen_store_fpr32(ctx, t0, fd);
9751 gen_set_label(l1);
9752 tcg_temp_free_i32(t0);
9753 }
9754
9755 static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc,
9756 int tf)
9757 {
9758 int cond;
9759 TCGv_i32 t0 = tcg_temp_new_i32();
9760 TCGv_i64 fp0;
9761 TCGLabel *l1 = gen_new_label();
9762
9763 if (tf) {
9764 cond = TCG_COND_EQ;
9765 } else {
9766 cond = TCG_COND_NE;
9767 }
9768
9769 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
9770 tcg_gen_brcondi_i32(cond, t0, 0, l1);
9771 tcg_temp_free_i32(t0);
9772 fp0 = tcg_temp_new_i64();
9773 gen_load_fpr64(ctx, fp0, fs);
9774 gen_store_fpr64(ctx, fp0, fd);
9775 tcg_temp_free_i64(fp0);
9776 gen_set_label(l1);
9777 }
9778
9779 static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
9780 int cc, int tf)
9781 {
9782 int cond;
9783 TCGv_i32 t0 = tcg_temp_new_i32();
9784 TCGLabel *l1 = gen_new_label();
9785 TCGLabel *l2 = gen_new_label();
9786
9787 if (tf) {
9788 cond = TCG_COND_EQ;
9789 } else {
9790 cond = TCG_COND_NE;
9791 }
9792
9793 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
9794 tcg_gen_brcondi_i32(cond, t0, 0, l1);
9795 gen_load_fpr32(ctx, t0, fs);
9796 gen_store_fpr32(ctx, t0, fd);
9797 gen_set_label(l1);
9798
9799 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc + 1));
9800 tcg_gen_brcondi_i32(cond, t0, 0, l2);
9801 gen_load_fpr32h(ctx, t0, fs);
9802 gen_store_fpr32h(ctx, t0, fd);
9803 tcg_temp_free_i32(t0);
9804 gen_set_label(l2);
9805 }
9806
9807 static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
9808 int fs)
9809 {
9810 TCGv_i32 t1 = tcg_const_i32(0);
9811 TCGv_i32 fp0 = tcg_temp_new_i32();
9812 TCGv_i32 fp1 = tcg_temp_new_i32();
9813 TCGv_i32 fp2 = tcg_temp_new_i32();
9814 gen_load_fpr32(ctx, fp0, fd);
9815 gen_load_fpr32(ctx, fp1, ft);
9816 gen_load_fpr32(ctx, fp2, fs);
9817
9818 switch (op1) {
9819 case OPC_SEL_S:
9820 tcg_gen_andi_i32(fp0, fp0, 1);
9821 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp0, t1, fp1, fp2);
9822 break;
9823 case OPC_SELEQZ_S:
9824 tcg_gen_andi_i32(fp1, fp1, 1);
9825 tcg_gen_movcond_i32(TCG_COND_EQ, fp0, fp1, t1, fp2, t1);
9826 break;
9827 case OPC_SELNEZ_S:
9828 tcg_gen_andi_i32(fp1, fp1, 1);
9829 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp1, t1, fp2, t1);
9830 break;
9831 default:
9832 MIPS_INVAL("gen_sel_s");
9833 gen_reserved_instruction(ctx);
9834 break;
9835 }
9836
9837 gen_store_fpr32(ctx, fp0, fd);
9838 tcg_temp_free_i32(fp2);
9839 tcg_temp_free_i32(fp1);
9840 tcg_temp_free_i32(fp0);
9841 tcg_temp_free_i32(t1);
9842 }
9843
9844 static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
9845 int fs)
9846 {
9847 TCGv_i64 t1 = tcg_const_i64(0);
9848 TCGv_i64 fp0 = tcg_temp_new_i64();
9849 TCGv_i64 fp1 = tcg_temp_new_i64();
9850 TCGv_i64 fp2 = tcg_temp_new_i64();
9851 gen_load_fpr64(ctx, fp0, fd);
9852 gen_load_fpr64(ctx, fp1, ft);
9853 gen_load_fpr64(ctx, fp2, fs);
9854
9855 switch (op1) {
9856 case OPC_SEL_D:
9857 tcg_gen_andi_i64(fp0, fp0, 1);
9858 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp0, t1, fp1, fp2);
9859 break;
9860 case OPC_SELEQZ_D:
9861 tcg_gen_andi_i64(fp1, fp1, 1);
9862 tcg_gen_movcond_i64(TCG_COND_EQ, fp0, fp1, t1, fp2, t1);
9863 break;
9864 case OPC_SELNEZ_D:
9865 tcg_gen_andi_i64(fp1, fp1, 1);
9866 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp1, t1, fp2, t1);
9867 break;
9868 default:
9869 MIPS_INVAL("gen_sel_d");
9870 gen_reserved_instruction(ctx);
9871 break;
9872 }
9873
9874 gen_store_fpr64(ctx, fp0, fd);
9875 tcg_temp_free_i64(fp2);
9876 tcg_temp_free_i64(fp1);
9877 tcg_temp_free_i64(fp0);
9878 tcg_temp_free_i64(t1);
9879 }
9880
9881 static void gen_farith(DisasContext *ctx, enum fopcode op1,
9882 int ft, int fs, int fd, int cc)
9883 {
9884 uint32_t func = ctx->opcode & 0x3f;
9885 switch (op1) {
9886 case OPC_ADD_S:
9887 {
9888 TCGv_i32 fp0 = tcg_temp_new_i32();
9889 TCGv_i32 fp1 = tcg_temp_new_i32();
9890
9891 gen_load_fpr32(ctx, fp0, fs);
9892 gen_load_fpr32(ctx, fp1, ft);
9893 gen_helper_float_add_s(fp0, cpu_env, fp0, fp1);
9894 tcg_temp_free_i32(fp1);
9895 gen_store_fpr32(ctx, fp0, fd);
9896 tcg_temp_free_i32(fp0);
9897 }
9898 break;
9899 case OPC_SUB_S:
9900 {
9901 TCGv_i32 fp0 = tcg_temp_new_i32();
9902 TCGv_i32 fp1 = tcg_temp_new_i32();
9903
9904 gen_load_fpr32(ctx, fp0, fs);
9905 gen_load_fpr32(ctx, fp1, ft);
9906 gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1);
9907 tcg_temp_free_i32(fp1);
9908 gen_store_fpr32(ctx, fp0, fd);
9909 tcg_temp_free_i32(fp0);
9910 }
9911 break;
9912 case OPC_MUL_S:
9913 {
9914 TCGv_i32 fp0 = tcg_temp_new_i32();
9915 TCGv_i32 fp1 = tcg_temp_new_i32();
9916
9917 gen_load_fpr32(ctx, fp0, fs);
9918 gen_load_fpr32(ctx, fp1, ft);
9919 gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1);
9920 tcg_temp_free_i32(fp1);
9921 gen_store_fpr32(ctx, fp0, fd);
9922 tcg_temp_free_i32(fp0);
9923 }
9924 break;
9925 case OPC_DIV_S:
9926 {
9927 TCGv_i32 fp0 = tcg_temp_new_i32();
9928 TCGv_i32 fp1 = tcg_temp_new_i32();
9929
9930 gen_load_fpr32(ctx, fp0, fs);
9931 gen_load_fpr32(ctx, fp1, ft);
9932 gen_helper_float_div_s(fp0, cpu_env, fp0, fp1);
9933 tcg_temp_free_i32(fp1);
9934 gen_store_fpr32(ctx, fp0, fd);
9935 tcg_temp_free_i32(fp0);
9936 }
9937 break;
9938 case OPC_SQRT_S:
9939 {
9940 TCGv_i32 fp0 = tcg_temp_new_i32();
9941
9942 gen_load_fpr32(ctx, fp0, fs);
9943 gen_helper_float_sqrt_s(fp0, cpu_env, fp0);
9944 gen_store_fpr32(ctx, fp0, fd);
9945 tcg_temp_free_i32(fp0);
9946 }
9947 break;
9948 case OPC_ABS_S:
9949 {
9950 TCGv_i32 fp0 = tcg_temp_new_i32();
9951
9952 gen_load_fpr32(ctx, fp0, fs);
9953 if (ctx->abs2008) {
9954 tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL);
9955 } else {
9956 gen_helper_float_abs_s(fp0, fp0);
9957 }
9958 gen_store_fpr32(ctx, fp0, fd);
9959 tcg_temp_free_i32(fp0);
9960 }
9961 break;
9962 case OPC_MOV_S:
9963 {
9964 TCGv_i32 fp0 = tcg_temp_new_i32();
9965
9966 gen_load_fpr32(ctx, fp0, fs);
9967 gen_store_fpr32(ctx, fp0, fd);
9968 tcg_temp_free_i32(fp0);
9969 }
9970 break;
9971 case OPC_NEG_S:
9972 {
9973 TCGv_i32 fp0 = tcg_temp_new_i32();
9974
9975 gen_load_fpr32(ctx, fp0, fs);
9976 if (ctx->abs2008) {
9977 tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
9978 } else {
9979 gen_helper_float_chs_s(fp0, fp0);
9980 }
9981 gen_store_fpr32(ctx, fp0, fd);
9982 tcg_temp_free_i32(fp0);
9983 }
9984 break;
9985 case OPC_ROUND_L_S:
9986 check_cp1_64bitmode(ctx);
9987 {
9988 TCGv_i32 fp32 = tcg_temp_new_i32();
9989 TCGv_i64 fp64 = tcg_temp_new_i64();
9990
9991 gen_load_fpr32(ctx, fp32, fs);
9992 if (ctx->nan2008) {
9993 gen_helper_float_round_2008_l_s(fp64, cpu_env, fp32);
9994 } else {
9995 gen_helper_float_round_l_s(fp64, cpu_env, fp32);
9996 }
9997 tcg_temp_free_i32(fp32);
9998 gen_store_fpr64(ctx, fp64, fd);
9999 tcg_temp_free_i64(fp64);
10000 }
10001 break;
10002 case OPC_TRUNC_L_S:
10003 check_cp1_64bitmode(ctx);
10004 {
10005 TCGv_i32 fp32 = tcg_temp_new_i32();
10006 TCGv_i64 fp64 = tcg_temp_new_i64();
10007
10008 gen_load_fpr32(ctx, fp32, fs);
10009 if (ctx->nan2008) {
10010 gen_helper_float_trunc_2008_l_s(fp64, cpu_env, fp32);
10011 } else {
10012 gen_helper_float_trunc_l_s(fp64, cpu_env, fp32);
10013 }
10014 tcg_temp_free_i32(fp32);
10015 gen_store_fpr64(ctx, fp64, fd);
10016 tcg_temp_free_i64(fp64);
10017 }
10018 break;
10019 case OPC_CEIL_L_S:
10020 check_cp1_64bitmode(ctx);
10021 {
10022 TCGv_i32 fp32 = tcg_temp_new_i32();
10023 TCGv_i64 fp64 = tcg_temp_new_i64();
10024
10025 gen_load_fpr32(ctx, fp32, fs);
10026 if (ctx->nan2008) {
10027 gen_helper_float_ceil_2008_l_s(fp64, cpu_env, fp32);
10028 } else {
10029 gen_helper_float_ceil_l_s(fp64, cpu_env, fp32);
10030 }
10031 tcg_temp_free_i32(fp32);
10032 gen_store_fpr64(ctx, fp64, fd);
10033 tcg_temp_free_i64(fp64);
10034 }
10035 break;
10036 case OPC_FLOOR_L_S:
10037 check_cp1_64bitmode(ctx);
10038 {
10039 TCGv_i32 fp32 = tcg_temp_new_i32();
10040 TCGv_i64 fp64 = tcg_temp_new_i64();
10041
10042 gen_load_fpr32(ctx, fp32, fs);
10043 if (ctx->nan2008) {
10044 gen_helper_float_floor_2008_l_s(fp64, cpu_env, fp32);
10045 } else {
10046 gen_helper_float_floor_l_s(fp64, cpu_env, fp32);
10047 }
10048 tcg_temp_free_i32(fp32);
10049 gen_store_fpr64(ctx, fp64, fd);
10050 tcg_temp_free_i64(fp64);
10051 }
10052 break;
10053 case OPC_ROUND_W_S:
10054 {
10055 TCGv_i32 fp0 = tcg_temp_new_i32();
10056
10057 gen_load_fpr32(ctx, fp0, fs);
10058 if (ctx->nan2008) {
10059 gen_helper_float_round_2008_w_s(fp0, cpu_env, fp0);
10060 } else {
10061 gen_helper_float_round_w_s(fp0, cpu_env, fp0);
10062 }
10063 gen_store_fpr32(ctx, fp0, fd);
10064 tcg_temp_free_i32(fp0);
10065 }
10066 break;
10067 case OPC_TRUNC_W_S:
10068 {
10069 TCGv_i32 fp0 = tcg_temp_new_i32();
10070
10071 gen_load_fpr32(ctx, fp0, fs);
10072 if (ctx->nan2008) {
10073 gen_helper_float_trunc_2008_w_s(fp0, cpu_env, fp0);
10074 } else {
10075 gen_helper_float_trunc_w_s(fp0, cpu_env, fp0);
10076 }
10077 gen_store_fpr32(ctx, fp0, fd);
10078 tcg_temp_free_i32(fp0);
10079 }
10080 break;
10081 case OPC_CEIL_W_S:
10082 {
10083 TCGv_i32 fp0 = tcg_temp_new_i32();
10084
10085 gen_load_fpr32(ctx, fp0, fs);
10086 if (ctx->nan2008) {
10087 gen_helper_float_ceil_2008_w_s(fp0, cpu_env, fp0);
10088 } else {
10089 gen_helper_float_ceil_w_s(fp0, cpu_env, fp0);
10090 }
10091 gen_store_fpr32(ctx, fp0, fd);
10092 tcg_temp_free_i32(fp0);
10093 }
10094 break;
10095 case OPC_FLOOR_W_S:
10096 {
10097 TCGv_i32 fp0 = tcg_temp_new_i32();
10098
10099 gen_load_fpr32(ctx, fp0, fs);
10100 if (ctx->nan2008) {
10101 gen_helper_float_floor_2008_w_s(fp0, cpu_env, fp0);
10102 } else {
10103 gen_helper_float_floor_w_s(fp0, cpu_env, fp0);
10104 }
10105 gen_store_fpr32(ctx, fp0, fd);
10106 tcg_temp_free_i32(fp0);
10107 }
10108 break;
10109 case OPC_SEL_S:
10110 check_insn(ctx, ISA_MIPS_R6);
10111 gen_sel_s(ctx, op1, fd, ft, fs);
10112 break;
10113 case OPC_SELEQZ_S:
10114 check_insn(ctx, ISA_MIPS_R6);
10115 gen_sel_s(ctx, op1, fd, ft, fs);
10116 break;
10117 case OPC_SELNEZ_S:
10118 check_insn(ctx, ISA_MIPS_R6);
10119 gen_sel_s(ctx, op1, fd, ft, fs);
10120 break;
10121 case OPC_MOVCF_S:
10122 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10123 gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
10124 break;
10125 case OPC_MOVZ_S:
10126 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10127 {
10128 TCGLabel *l1 = gen_new_label();
10129 TCGv_i32 fp0;
10130
10131 if (ft != 0) {
10132 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
10133 }
10134 fp0 = tcg_temp_new_i32();
10135 gen_load_fpr32(ctx, fp0, fs);
10136 gen_store_fpr32(ctx, fp0, fd);
10137 tcg_temp_free_i32(fp0);
10138 gen_set_label(l1);
10139 }
10140 break;
10141 case OPC_MOVN_S:
10142 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10143 {
10144 TCGLabel *l1 = gen_new_label();
10145 TCGv_i32 fp0;
10146
10147 if (ft != 0) {
10148 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
10149 fp0 = tcg_temp_new_i32();
10150 gen_load_fpr32(ctx, fp0, fs);
10151 gen_store_fpr32(ctx, fp0, fd);
10152 tcg_temp_free_i32(fp0);
10153 gen_set_label(l1);
10154 }
10155 }
10156 break;
10157 case OPC_RECIP_S:
10158 {
10159 TCGv_i32 fp0 = tcg_temp_new_i32();
10160
10161 gen_load_fpr32(ctx, fp0, fs);
10162 gen_helper_float_recip_s(fp0, cpu_env, fp0);
10163 gen_store_fpr32(ctx, fp0, fd);
10164 tcg_temp_free_i32(fp0);
10165 }
10166 break;
10167 case OPC_RSQRT_S:
10168 {
10169 TCGv_i32 fp0 = tcg_temp_new_i32();
10170
10171 gen_load_fpr32(ctx, fp0, fs);
10172 gen_helper_float_rsqrt_s(fp0, cpu_env, fp0);
10173 gen_store_fpr32(ctx, fp0, fd);
10174 tcg_temp_free_i32(fp0);
10175 }
10176 break;
10177 case OPC_MADDF_S:
10178 check_insn(ctx, ISA_MIPS_R6);
10179 {
10180 TCGv_i32 fp0 = tcg_temp_new_i32();
10181 TCGv_i32 fp1 = tcg_temp_new_i32();
10182 TCGv_i32 fp2 = tcg_temp_new_i32();
10183 gen_load_fpr32(ctx, fp0, fs);
10184 gen_load_fpr32(ctx, fp1, ft);
10185 gen_load_fpr32(ctx, fp2, fd);
10186 gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2);
10187 gen_store_fpr32(ctx, fp2, fd);
10188 tcg_temp_free_i32(fp2);
10189 tcg_temp_free_i32(fp1);
10190 tcg_temp_free_i32(fp0);
10191 }
10192 break;
10193 case OPC_MSUBF_S:
10194 check_insn(ctx, ISA_MIPS_R6);
10195 {
10196 TCGv_i32 fp0 = tcg_temp_new_i32();
10197 TCGv_i32 fp1 = tcg_temp_new_i32();
10198 TCGv_i32 fp2 = tcg_temp_new_i32();
10199 gen_load_fpr32(ctx, fp0, fs);
10200 gen_load_fpr32(ctx, fp1, ft);
10201 gen_load_fpr32(ctx, fp2, fd);
10202 gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2);
10203 gen_store_fpr32(ctx, fp2, fd);
10204 tcg_temp_free_i32(fp2);
10205 tcg_temp_free_i32(fp1);
10206 tcg_temp_free_i32(fp0);
10207 }
10208 break;
10209 case OPC_RINT_S:
10210 check_insn(ctx, ISA_MIPS_R6);
10211 {
10212 TCGv_i32 fp0 = tcg_temp_new_i32();
10213 gen_load_fpr32(ctx, fp0, fs);
10214 gen_helper_float_rint_s(fp0, cpu_env, fp0);
10215 gen_store_fpr32(ctx, fp0, fd);
10216 tcg_temp_free_i32(fp0);
10217 }
10218 break;
10219 case OPC_CLASS_S:
10220 check_insn(ctx, ISA_MIPS_R6);
10221 {
10222 TCGv_i32 fp0 = tcg_temp_new_i32();
10223 gen_load_fpr32(ctx, fp0, fs);
10224 gen_helper_float_class_s(fp0, cpu_env, fp0);
10225 gen_store_fpr32(ctx, fp0, fd);
10226 tcg_temp_free_i32(fp0);
10227 }
10228 break;
10229 case OPC_MIN_S: /* OPC_RECIP2_S */
10230 if (ctx->insn_flags & ISA_MIPS_R6) {
10231 /* OPC_MIN_S */
10232 TCGv_i32 fp0 = tcg_temp_new_i32();
10233 TCGv_i32 fp1 = tcg_temp_new_i32();
10234 TCGv_i32 fp2 = tcg_temp_new_i32();
10235 gen_load_fpr32(ctx, fp0, fs);
10236 gen_load_fpr32(ctx, fp1, ft);
10237 gen_helper_float_min_s(fp2, cpu_env, fp0, fp1);
10238 gen_store_fpr32(ctx, fp2, fd);
10239 tcg_temp_free_i32(fp2);
10240 tcg_temp_free_i32(fp1);
10241 tcg_temp_free_i32(fp0);
10242 } else {
10243 /* OPC_RECIP2_S */
10244 check_cp1_64bitmode(ctx);
10245 {
10246 TCGv_i32 fp0 = tcg_temp_new_i32();
10247 TCGv_i32 fp1 = tcg_temp_new_i32();
10248
10249 gen_load_fpr32(ctx, fp0, fs);
10250 gen_load_fpr32(ctx, fp1, ft);
10251 gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1);
10252 tcg_temp_free_i32(fp1);
10253 gen_store_fpr32(ctx, fp0, fd);
10254 tcg_temp_free_i32(fp0);
10255 }
10256 }
10257 break;
10258 case OPC_MINA_S: /* OPC_RECIP1_S */
10259 if (ctx->insn_flags & ISA_MIPS_R6) {
10260 /* OPC_MINA_S */
10261 TCGv_i32 fp0 = tcg_temp_new_i32();
10262 TCGv_i32 fp1 = tcg_temp_new_i32();
10263 TCGv_i32 fp2 = tcg_temp_new_i32();
10264 gen_load_fpr32(ctx, fp0, fs);
10265 gen_load_fpr32(ctx, fp1, ft);
10266 gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1);
10267 gen_store_fpr32(ctx, fp2, fd);
10268 tcg_temp_free_i32(fp2);
10269 tcg_temp_free_i32(fp1);
10270 tcg_temp_free_i32(fp0);
10271 } else {
10272 /* OPC_RECIP1_S */
10273 check_cp1_64bitmode(ctx);
10274 {
10275 TCGv_i32 fp0 = tcg_temp_new_i32();
10276
10277 gen_load_fpr32(ctx, fp0, fs);
10278 gen_helper_float_recip1_s(fp0, cpu_env, fp0);
10279 gen_store_fpr32(ctx, fp0, fd);
10280 tcg_temp_free_i32(fp0);
10281 }
10282 }
10283 break;
10284 case OPC_MAX_S: /* OPC_RSQRT1_S */
10285 if (ctx->insn_flags & ISA_MIPS_R6) {
10286 /* OPC_MAX_S */
10287 TCGv_i32 fp0 = tcg_temp_new_i32();
10288 TCGv_i32 fp1 = tcg_temp_new_i32();
10289 gen_load_fpr32(ctx, fp0, fs);
10290 gen_load_fpr32(ctx, fp1, ft);
10291 gen_helper_float_max_s(fp1, cpu_env, fp0, fp1);
10292 gen_store_fpr32(ctx, fp1, fd);
10293 tcg_temp_free_i32(fp1);
10294 tcg_temp_free_i32(fp0);
10295 } else {
10296 /* OPC_RSQRT1_S */
10297 check_cp1_64bitmode(ctx);
10298 {
10299 TCGv_i32 fp0 = tcg_temp_new_i32();
10300
10301 gen_load_fpr32(ctx, fp0, fs);
10302 gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0);
10303 gen_store_fpr32(ctx, fp0, fd);
10304 tcg_temp_free_i32(fp0);
10305 }
10306 }
10307 break;
10308 case OPC_MAXA_S: /* OPC_RSQRT2_S */
10309 if (ctx->insn_flags & ISA_MIPS_R6) {
10310 /* OPC_MAXA_S */
10311 TCGv_i32 fp0 = tcg_temp_new_i32();
10312 TCGv_i32 fp1 = tcg_temp_new_i32();
10313 gen_load_fpr32(ctx, fp0, fs);
10314 gen_load_fpr32(ctx, fp1, ft);
10315 gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1);
10316 gen_store_fpr32(ctx, fp1, fd);
10317 tcg_temp_free_i32(fp1);
10318 tcg_temp_free_i32(fp0);
10319 } else {
10320 /* OPC_RSQRT2_S */
10321 check_cp1_64bitmode(ctx);
10322 {
10323 TCGv_i32 fp0 = tcg_temp_new_i32();
10324 TCGv_i32 fp1 = tcg_temp_new_i32();
10325
10326 gen_load_fpr32(ctx, fp0, fs);
10327 gen_load_fpr32(ctx, fp1, ft);
10328 gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1);
10329 tcg_temp_free_i32(fp1);
10330 gen_store_fpr32(ctx, fp0, fd);
10331 tcg_temp_free_i32(fp0);
10332 }
10333 }
10334 break;
10335 case OPC_CVT_D_S:
10336 check_cp1_registers(ctx, fd);
10337 {
10338 TCGv_i32 fp32 = tcg_temp_new_i32();
10339 TCGv_i64 fp64 = tcg_temp_new_i64();
10340
10341 gen_load_fpr32(ctx, fp32, fs);
10342 gen_helper_float_cvtd_s(fp64, cpu_env, fp32);
10343 tcg_temp_free_i32(fp32);
10344 gen_store_fpr64(ctx, fp64, fd);
10345 tcg_temp_free_i64(fp64);
10346 }
10347 break;
10348 case OPC_CVT_W_S:
10349 {
10350 TCGv_i32 fp0 = tcg_temp_new_i32();
10351
10352 gen_load_fpr32(ctx, fp0, fs);
10353 if (ctx->nan2008) {
10354 gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0);
10355 } else {
10356 gen_helper_float_cvt_w_s(fp0, cpu_env, fp0);
10357 }
10358 gen_store_fpr32(ctx, fp0, fd);
10359 tcg_temp_free_i32(fp0);
10360 }
10361 break;
10362 case OPC_CVT_L_S:
10363 check_cp1_64bitmode(ctx);
10364 {
10365 TCGv_i32 fp32 = tcg_temp_new_i32();
10366 TCGv_i64 fp64 = tcg_temp_new_i64();
10367
10368 gen_load_fpr32(ctx, fp32, fs);
10369 if (ctx->nan2008) {
10370 gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32);
10371 } else {
10372 gen_helper_float_cvt_l_s(fp64, cpu_env, fp32);
10373 }
10374 tcg_temp_free_i32(fp32);
10375 gen_store_fpr64(ctx, fp64, fd);
10376 tcg_temp_free_i64(fp64);
10377 }
10378 break;
10379 case OPC_CVT_PS_S:
10380 check_ps(ctx);
10381 {
10382 TCGv_i64 fp64 = tcg_temp_new_i64();
10383 TCGv_i32 fp32_0 = tcg_temp_new_i32();
10384 TCGv_i32 fp32_1 = tcg_temp_new_i32();
10385
10386 gen_load_fpr32(ctx, fp32_0, fs);
10387 gen_load_fpr32(ctx, fp32_1, ft);
10388 tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0);
10389 tcg_temp_free_i32(fp32_1);
10390 tcg_temp_free_i32(fp32_0);
10391 gen_store_fpr64(ctx, fp64, fd);
10392 tcg_temp_free_i64(fp64);
10393 }
10394 break;
10395 case OPC_CMP_F_S:
10396 case OPC_CMP_UN_S:
10397 case OPC_CMP_EQ_S:
10398 case OPC_CMP_UEQ_S:
10399 case OPC_CMP_OLT_S:
10400 case OPC_CMP_ULT_S:
10401 case OPC_CMP_OLE_S:
10402 case OPC_CMP_ULE_S:
10403 case OPC_CMP_SF_S:
10404 case OPC_CMP_NGLE_S:
10405 case OPC_CMP_SEQ_S:
10406 case OPC_CMP_NGL_S:
10407 case OPC_CMP_LT_S:
10408 case OPC_CMP_NGE_S:
10409 case OPC_CMP_LE_S:
10410 case OPC_CMP_NGT_S:
10411 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10412 if (ctx->opcode & (1 << 6)) {
10413 gen_cmpabs_s(ctx, func - 48, ft, fs, cc);
10414 } else {
10415 gen_cmp_s(ctx, func - 48, ft, fs, cc);
10416 }
10417 break;
10418 case OPC_ADD_D:
10419 check_cp1_registers(ctx, fs | ft | fd);
10420 {
10421 TCGv_i64 fp0 = tcg_temp_new_i64();
10422 TCGv_i64 fp1 = tcg_temp_new_i64();
10423
10424 gen_load_fpr64(ctx, fp0, fs);
10425 gen_load_fpr64(ctx, fp1, ft);
10426 gen_helper_float_add_d(fp0, cpu_env, fp0, fp1);
10427 tcg_temp_free_i64(fp1);
10428 gen_store_fpr64(ctx, fp0, fd);
10429 tcg_temp_free_i64(fp0);
10430 }
10431 break;
10432 case OPC_SUB_D:
10433 check_cp1_registers(ctx, fs | ft | fd);
10434 {
10435 TCGv_i64 fp0 = tcg_temp_new_i64();
10436 TCGv_i64 fp1 = tcg_temp_new_i64();
10437
10438 gen_load_fpr64(ctx, fp0, fs);
10439 gen_load_fpr64(ctx, fp1, ft);
10440 gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1);
10441 tcg_temp_free_i64(fp1);
10442 gen_store_fpr64(ctx, fp0, fd);
10443 tcg_temp_free_i64(fp0);
10444 }
10445 break;
10446 case OPC_MUL_D:
10447 check_cp1_registers(ctx, fs | ft | fd);
10448 {
10449 TCGv_i64 fp0 = tcg_temp_new_i64();
10450 TCGv_i64 fp1 = tcg_temp_new_i64();
10451
10452 gen_load_fpr64(ctx, fp0, fs);
10453 gen_load_fpr64(ctx, fp1, ft);
10454 gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1);
10455 tcg_temp_free_i64(fp1);
10456 gen_store_fpr64(ctx, fp0, fd);
10457 tcg_temp_free_i64(fp0);
10458 }
10459 break;
10460 case OPC_DIV_D:
10461 check_cp1_registers(ctx, fs | ft | fd);
10462 {
10463 TCGv_i64 fp0 = tcg_temp_new_i64();
10464 TCGv_i64 fp1 = tcg_temp_new_i64();
10465
10466 gen_load_fpr64(ctx, fp0, fs);
10467 gen_load_fpr64(ctx, fp1, ft);
10468 gen_helper_float_div_d(fp0, cpu_env, fp0, fp1);
10469 tcg_temp_free_i64(fp1);
10470 gen_store_fpr64(ctx, fp0, fd);
10471 tcg_temp_free_i64(fp0);
10472 }
10473 break;
10474 case OPC_SQRT_D:
10475 check_cp1_registers(ctx, fs | fd);
10476 {
10477 TCGv_i64 fp0 = tcg_temp_new_i64();
10478
10479 gen_load_fpr64(ctx, fp0, fs);
10480 gen_helper_float_sqrt_d(fp0, cpu_env, fp0);
10481 gen_store_fpr64(ctx, fp0, fd);
10482 tcg_temp_free_i64(fp0);
10483 }
10484 break;
10485 case OPC_ABS_D:
10486 check_cp1_registers(ctx, fs | fd);
10487 {
10488 TCGv_i64 fp0 = tcg_temp_new_i64();
10489
10490 gen_load_fpr64(ctx, fp0, fs);
10491 if (ctx->abs2008) {
10492 tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL);
10493 } else {
10494 gen_helper_float_abs_d(fp0, fp0);
10495 }
10496 gen_store_fpr64(ctx, fp0, fd);
10497 tcg_temp_free_i64(fp0);
10498 }
10499 break;
10500 case OPC_MOV_D:
10501 check_cp1_registers(ctx, fs | fd);
10502 {
10503 TCGv_i64 fp0 = tcg_temp_new_i64();
10504
10505 gen_load_fpr64(ctx, fp0, fs);
10506 gen_store_fpr64(ctx, fp0, fd);
10507 tcg_temp_free_i64(fp0);
10508 }
10509 break;
10510 case OPC_NEG_D:
10511 check_cp1_registers(ctx, fs | fd);
10512 {
10513 TCGv_i64 fp0 = tcg_temp_new_i64();
10514
10515 gen_load_fpr64(ctx, fp0, fs);
10516 if (ctx->abs2008) {
10517 tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
10518 } else {
10519 gen_helper_float_chs_d(fp0, fp0);
10520 }
10521 gen_store_fpr64(ctx, fp0, fd);
10522 tcg_temp_free_i64(fp0);
10523 }
10524 break;
10525 case OPC_ROUND_L_D:
10526 check_cp1_64bitmode(ctx);
10527 {
10528 TCGv_i64 fp0 = tcg_temp_new_i64();
10529
10530 gen_load_fpr64(ctx, fp0, fs);
10531 if (ctx->nan2008) {
10532 gen_helper_float_round_2008_l_d(fp0, cpu_env, fp0);
10533 } else {
10534 gen_helper_float_round_l_d(fp0, cpu_env, fp0);
10535 }
10536 gen_store_fpr64(ctx, fp0, fd);
10537 tcg_temp_free_i64(fp0);
10538 }
10539 break;
10540 case OPC_TRUNC_L_D:
10541 check_cp1_64bitmode(ctx);
10542 {
10543 TCGv_i64 fp0 = tcg_temp_new_i64();
10544
10545 gen_load_fpr64(ctx, fp0, fs);
10546 if (ctx->nan2008) {
10547 gen_helper_float_trunc_2008_l_d(fp0, cpu_env, fp0);
10548 } else {
10549 gen_helper_float_trunc_l_d(fp0, cpu_env, fp0);
10550 }
10551 gen_store_fpr64(ctx, fp0, fd);
10552 tcg_temp_free_i64(fp0);
10553 }
10554 break;
10555 case OPC_CEIL_L_D:
10556 check_cp1_64bitmode(ctx);
10557 {
10558 TCGv_i64 fp0 = tcg_temp_new_i64();
10559
10560 gen_load_fpr64(ctx, fp0, fs);
10561 if (ctx->nan2008) {
10562 gen_helper_float_ceil_2008_l_d(fp0, cpu_env, fp0);
10563 } else {
10564 gen_helper_float_ceil_l_d(fp0, cpu_env, fp0);
10565 }
10566 gen_store_fpr64(ctx, fp0, fd);
10567 tcg_temp_free_i64(fp0);
10568 }
10569 break;
10570 case OPC_FLOOR_L_D:
10571 check_cp1_64bitmode(ctx);
10572 {
10573 TCGv_i64 fp0 = tcg_temp_new_i64();
10574
10575 gen_load_fpr64(ctx, fp0, fs);
10576 if (ctx->nan2008) {
10577 gen_helper_float_floor_2008_l_d(fp0, cpu_env, fp0);
10578 } else {
10579 gen_helper_float_floor_l_d(fp0, cpu_env, fp0);
10580 }
10581 gen_store_fpr64(ctx, fp0, fd);
10582 tcg_temp_free_i64(fp0);
10583 }
10584 break;
10585 case OPC_ROUND_W_D:
10586 check_cp1_registers(ctx, fs);
10587 {
10588 TCGv_i32 fp32 = tcg_temp_new_i32();
10589 TCGv_i64 fp64 = tcg_temp_new_i64();
10590
10591 gen_load_fpr64(ctx, fp64, fs);
10592 if (ctx->nan2008) {
10593 gen_helper_float_round_2008_w_d(fp32, cpu_env, fp64);
10594 } else {
10595 gen_helper_float_round_w_d(fp32, cpu_env, fp64);
10596 }
10597 tcg_temp_free_i64(fp64);
10598 gen_store_fpr32(ctx, fp32, fd);
10599 tcg_temp_free_i32(fp32);
10600 }
10601 break;
10602 case OPC_TRUNC_W_D:
10603 check_cp1_registers(ctx, fs);
10604 {
10605 TCGv_i32 fp32 = tcg_temp_new_i32();
10606 TCGv_i64 fp64 = tcg_temp_new_i64();
10607
10608 gen_load_fpr64(ctx, fp64, fs);
10609 if (ctx->nan2008) {
10610 gen_helper_float_trunc_2008_w_d(fp32, cpu_env, fp64);
10611 } else {
10612 gen_helper_float_trunc_w_d(fp32, cpu_env, fp64);
10613 }
10614 tcg_temp_free_i64(fp64);
10615 gen_store_fpr32(ctx, fp32, fd);
10616 tcg_temp_free_i32(fp32);
10617 }
10618 break;
10619 case OPC_CEIL_W_D:
10620 check_cp1_registers(ctx, fs);
10621 {
10622 TCGv_i32 fp32 = tcg_temp_new_i32();
10623 TCGv_i64 fp64 = tcg_temp_new_i64();
10624
10625 gen_load_fpr64(ctx, fp64, fs);
10626 if (ctx->nan2008) {
10627 gen_helper_float_ceil_2008_w_d(fp32, cpu_env, fp64);
10628 } else {
10629 gen_helper_float_ceil_w_d(fp32, cpu_env, fp64);
10630 }
10631 tcg_temp_free_i64(fp64);
10632 gen_store_fpr32(ctx, fp32, fd);
10633 tcg_temp_free_i32(fp32);
10634 }
10635 break;
10636 case OPC_FLOOR_W_D:
10637 check_cp1_registers(ctx, fs);
10638 {
10639 TCGv_i32 fp32 = tcg_temp_new_i32();
10640 TCGv_i64 fp64 = tcg_temp_new_i64();
10641
10642 gen_load_fpr64(ctx, fp64, fs);
10643 if (ctx->nan2008) {
10644 gen_helper_float_floor_2008_w_d(fp32, cpu_env, fp64);
10645 } else {
10646 gen_helper_float_floor_w_d(fp32, cpu_env, fp64);
10647 }
10648 tcg_temp_free_i64(fp64);
10649 gen_store_fpr32(ctx, fp32, fd);
10650 tcg_temp_free_i32(fp32);
10651 }
10652 break;
10653 case OPC_SEL_D:
10654 check_insn(ctx, ISA_MIPS_R6);
10655 gen_sel_d(ctx, op1, fd, ft, fs);
10656 break;
10657 case OPC_SELEQZ_D:
10658 check_insn(ctx, ISA_MIPS_R6);
10659 gen_sel_d(ctx, op1, fd, ft, fs);
10660 break;
10661 case OPC_SELNEZ_D:
10662 check_insn(ctx, ISA_MIPS_R6);
10663 gen_sel_d(ctx, op1, fd, ft, fs);
10664 break;
10665 case OPC_MOVCF_D:
10666 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10667 gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
10668 break;
10669 case OPC_MOVZ_D:
10670 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10671 {
10672 TCGLabel *l1 = gen_new_label();
10673 TCGv_i64 fp0;
10674
10675 if (ft != 0) {
10676 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
10677 }
10678 fp0 = tcg_temp_new_i64();
10679 gen_load_fpr64(ctx, fp0, fs);
10680 gen_store_fpr64(ctx, fp0, fd);
10681 tcg_temp_free_i64(fp0);
10682 gen_set_label(l1);
10683 }
10684 break;
10685 case OPC_MOVN_D:
10686 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10687 {
10688 TCGLabel *l1 = gen_new_label();
10689 TCGv_i64 fp0;
10690
10691 if (ft != 0) {
10692 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
10693 fp0 = tcg_temp_new_i64();
10694 gen_load_fpr64(ctx, fp0, fs);
10695 gen_store_fpr64(ctx, fp0, fd);
10696 tcg_temp_free_i64(fp0);
10697 gen_set_label(l1);
10698 }
10699 }
10700 break;
10701 case OPC_RECIP_D:
10702 check_cp1_registers(ctx, fs | fd);
10703 {
10704 TCGv_i64 fp0 = tcg_temp_new_i64();
10705
10706 gen_load_fpr64(ctx, fp0, fs);
10707 gen_helper_float_recip_d(fp0, cpu_env, fp0);
10708 gen_store_fpr64(ctx, fp0, fd);
10709 tcg_temp_free_i64(fp0);
10710 }
10711 break;
10712 case OPC_RSQRT_D:
10713 check_cp1_registers(ctx, fs | fd);
10714 {
10715 TCGv_i64 fp0 = tcg_temp_new_i64();
10716
10717 gen_load_fpr64(ctx, fp0, fs);
10718 gen_helper_float_rsqrt_d(fp0, cpu_env, fp0);
10719 gen_store_fpr64(ctx, fp0, fd);
10720 tcg_temp_free_i64(fp0);
10721 }
10722 break;
10723 case OPC_MADDF_D:
10724 check_insn(ctx, ISA_MIPS_R6);
10725 {
10726 TCGv_i64 fp0 = tcg_temp_new_i64();
10727 TCGv_i64 fp1 = tcg_temp_new_i64();
10728 TCGv_i64 fp2 = tcg_temp_new_i64();
10729 gen_load_fpr64(ctx, fp0, fs);
10730 gen_load_fpr64(ctx, fp1, ft);
10731 gen_load_fpr64(ctx, fp2, fd);
10732 gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2);
10733 gen_store_fpr64(ctx, fp2, fd);
10734 tcg_temp_free_i64(fp2);
10735 tcg_temp_free_i64(fp1);
10736 tcg_temp_free_i64(fp0);
10737 }
10738 break;
10739 case OPC_MSUBF_D:
10740 check_insn(ctx, ISA_MIPS_R6);
10741 {
10742 TCGv_i64 fp0 = tcg_temp_new_i64();
10743 TCGv_i64 fp1 = tcg_temp_new_i64();
10744 TCGv_i64 fp2 = tcg_temp_new_i64();
10745 gen_load_fpr64(ctx, fp0, fs);
10746 gen_load_fpr64(ctx, fp1, ft);
10747 gen_load_fpr64(ctx, fp2, fd);
10748 gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2);
10749 gen_store_fpr64(ctx, fp2, fd);
10750 tcg_temp_free_i64(fp2);
10751 tcg_temp_free_i64(fp1);
10752 tcg_temp_free_i64(fp0);
10753 }
10754 break;
10755 case OPC_RINT_D:
10756 check_insn(ctx, ISA_MIPS_R6);
10757 {
10758 TCGv_i64 fp0 = tcg_temp_new_i64();
10759 gen_load_fpr64(ctx, fp0, fs);
10760 gen_helper_float_rint_d(fp0, cpu_env, fp0);
10761 gen_store_fpr64(ctx, fp0, fd);
10762 tcg_temp_free_i64(fp0);
10763 }
10764 break;
10765 case OPC_CLASS_D:
10766 check_insn(ctx, ISA_MIPS_R6);
10767 {
10768 TCGv_i64 fp0 = tcg_temp_new_i64();
10769 gen_load_fpr64(ctx, fp0, fs);
10770 gen_helper_float_class_d(fp0, cpu_env, fp0);
10771 gen_store_fpr64(ctx, fp0, fd);
10772 tcg_temp_free_i64(fp0);
10773 }
10774 break;
10775 case OPC_MIN_D: /* OPC_RECIP2_D */
10776 if (ctx->insn_flags & ISA_MIPS_R6) {
10777 /* OPC_MIN_D */
10778 TCGv_i64 fp0 = tcg_temp_new_i64();
10779 TCGv_i64 fp1 = tcg_temp_new_i64();
10780 gen_load_fpr64(ctx, fp0, fs);
10781 gen_load_fpr64(ctx, fp1, ft);
10782 gen_helper_float_min_d(fp1, cpu_env, fp0, fp1);
10783 gen_store_fpr64(ctx, fp1, fd);
10784 tcg_temp_free_i64(fp1);
10785 tcg_temp_free_i64(fp0);
10786 } else {
10787 /* OPC_RECIP2_D */
10788 check_cp1_64bitmode(ctx);
10789 {
10790 TCGv_i64 fp0 = tcg_temp_new_i64();
10791 TCGv_i64 fp1 = tcg_temp_new_i64();
10792
10793 gen_load_fpr64(ctx, fp0, fs);
10794 gen_load_fpr64(ctx, fp1, ft);
10795 gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1);
10796 tcg_temp_free_i64(fp1);
10797 gen_store_fpr64(ctx, fp0, fd);
10798 tcg_temp_free_i64(fp0);
10799 }
10800 }
10801 break;
10802 case OPC_MINA_D: /* OPC_RECIP1_D */
10803 if (ctx->insn_flags & ISA_MIPS_R6) {
10804 /* OPC_MINA_D */
10805 TCGv_i64 fp0 = tcg_temp_new_i64();
10806 TCGv_i64 fp1 = tcg_temp_new_i64();
10807 gen_load_fpr64(ctx, fp0, fs);
10808 gen_load_fpr64(ctx, fp1, ft);
10809 gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1);
10810 gen_store_fpr64(ctx, fp1, fd);
10811 tcg_temp_free_i64(fp1);
10812 tcg_temp_free_i64(fp0);
10813 } else {
10814 /* OPC_RECIP1_D */
10815 check_cp1_64bitmode(ctx);
10816 {
10817 TCGv_i64 fp0 = tcg_temp_new_i64();
10818
10819 gen_load_fpr64(ctx, fp0, fs);
10820 gen_helper_float_recip1_d(fp0, cpu_env, fp0);
10821 gen_store_fpr64(ctx, fp0, fd);
10822 tcg_temp_free_i64(fp0);
10823 }
10824 }
10825 break;
10826 case OPC_MAX_D: /* OPC_RSQRT1_D */
10827 if (ctx->insn_flags & ISA_MIPS_R6) {
10828 /* OPC_MAX_D */
10829 TCGv_i64 fp0 = tcg_temp_new_i64();
10830 TCGv_i64 fp1 = tcg_temp_new_i64();
10831 gen_load_fpr64(ctx, fp0, fs);
10832 gen_load_fpr64(ctx, fp1, ft);
10833 gen_helper_float_max_d(fp1, cpu_env, fp0, fp1);
10834 gen_store_fpr64(ctx, fp1, fd);
10835 tcg_temp_free_i64(fp1);
10836 tcg_temp_free_i64(fp0);
10837 } else {
10838 /* OPC_RSQRT1_D */
10839 check_cp1_64bitmode(ctx);
10840 {
10841 TCGv_i64 fp0 = tcg_temp_new_i64();
10842
10843 gen_load_fpr64(ctx, fp0, fs);
10844 gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0);
10845 gen_store_fpr64(ctx, fp0, fd);
10846 tcg_temp_free_i64(fp0);
10847 }
10848 }
10849 break;
10850 case OPC_MAXA_D: /* OPC_RSQRT2_D */
10851 if (ctx->insn_flags & ISA_MIPS_R6) {
10852 /* OPC_MAXA_D */
10853 TCGv_i64 fp0 = tcg_temp_new_i64();
10854 TCGv_i64 fp1 = tcg_temp_new_i64();
10855 gen_load_fpr64(ctx, fp0, fs);
10856 gen_load_fpr64(ctx, fp1, ft);
10857 gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1);
10858 gen_store_fpr64(ctx, fp1, fd);
10859 tcg_temp_free_i64(fp1);
10860 tcg_temp_free_i64(fp0);
10861 } else {
10862 /* OPC_RSQRT2_D */
10863 check_cp1_64bitmode(ctx);
10864 {
10865 TCGv_i64 fp0 = tcg_temp_new_i64();
10866 TCGv_i64 fp1 = tcg_temp_new_i64();
10867
10868 gen_load_fpr64(ctx, fp0, fs);
10869 gen_load_fpr64(ctx, fp1, ft);
10870 gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1);
10871 tcg_temp_free_i64(fp1);
10872 gen_store_fpr64(ctx, fp0, fd);
10873 tcg_temp_free_i64(fp0);
10874 }
10875 }
10876 break;
10877 case OPC_CMP_F_D:
10878 case OPC_CMP_UN_D:
10879 case OPC_CMP_EQ_D:
10880 case OPC_CMP_UEQ_D:
10881 case OPC_CMP_OLT_D:
10882 case OPC_CMP_ULT_D:
10883 case OPC_CMP_OLE_D:
10884 case OPC_CMP_ULE_D:
10885 case OPC_CMP_SF_D:
10886 case OPC_CMP_NGLE_D:
10887 case OPC_CMP_SEQ_D:
10888 case OPC_CMP_NGL_D:
10889 case OPC_CMP_LT_D:
10890 case OPC_CMP_NGE_D:
10891 case OPC_CMP_LE_D:
10892 case OPC_CMP_NGT_D:
10893 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10894 if (ctx->opcode & (1 << 6)) {
10895 gen_cmpabs_d(ctx, func - 48, ft, fs, cc);
10896 } else {
10897 gen_cmp_d(ctx, func - 48, ft, fs, cc);
10898 }
10899 break;
10900 case OPC_CVT_S_D:
10901 check_cp1_registers(ctx, fs);
10902 {
10903 TCGv_i32 fp32 = tcg_temp_new_i32();
10904 TCGv_i64 fp64 = tcg_temp_new_i64();
10905
10906 gen_load_fpr64(ctx, fp64, fs);
10907 gen_helper_float_cvts_d(fp32, cpu_env, fp64);
10908 tcg_temp_free_i64(fp64);
10909 gen_store_fpr32(ctx, fp32, fd);
10910 tcg_temp_free_i32(fp32);
10911 }
10912 break;
10913 case OPC_CVT_W_D:
10914 check_cp1_registers(ctx, fs);
10915 {
10916 TCGv_i32 fp32 = tcg_temp_new_i32();
10917 TCGv_i64 fp64 = tcg_temp_new_i64();
10918
10919 gen_load_fpr64(ctx, fp64, fs);
10920 if (ctx->nan2008) {
10921 gen_helper_float_cvt_2008_w_d(fp32, cpu_env, fp64);
10922 } else {
10923 gen_helper_float_cvt_w_d(fp32, cpu_env, fp64);
10924 }
10925 tcg_temp_free_i64(fp64);
10926 gen_store_fpr32(ctx, fp32, fd);
10927 tcg_temp_free_i32(fp32);
10928 }
10929 break;
10930 case OPC_CVT_L_D:
10931 check_cp1_64bitmode(ctx);
10932 {
10933 TCGv_i64 fp0 = tcg_temp_new_i64();
10934
10935 gen_load_fpr64(ctx, fp0, fs);
10936 if (ctx->nan2008) {
10937 gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0);
10938 } else {
10939 gen_helper_float_cvt_l_d(fp0, cpu_env, fp0);
10940 }
10941 gen_store_fpr64(ctx, fp0, fd);
10942 tcg_temp_free_i64(fp0);
10943 }
10944 break;
10945 case OPC_CVT_S_W:
10946 {
10947 TCGv_i32 fp0 = tcg_temp_new_i32();
10948
10949 gen_load_fpr32(ctx, fp0, fs);
10950 gen_helper_float_cvts_w(fp0, cpu_env, fp0);
10951 gen_store_fpr32(ctx, fp0, fd);
10952 tcg_temp_free_i32(fp0);
10953 }
10954 break;
10955 case OPC_CVT_D_W:
10956 check_cp1_registers(ctx, fd);
10957 {
10958 TCGv_i32 fp32 = tcg_temp_new_i32();
10959 TCGv_i64 fp64 = tcg_temp_new_i64();
10960
10961 gen_load_fpr32(ctx, fp32, fs);
10962 gen_helper_float_cvtd_w(fp64, cpu_env, fp32);
10963 tcg_temp_free_i32(fp32);
10964 gen_store_fpr64(ctx, fp64, fd);
10965 tcg_temp_free_i64(fp64);
10966 }
10967 break;
10968 case OPC_CVT_S_L:
10969 check_cp1_64bitmode(ctx);
10970 {
10971 TCGv_i32 fp32 = tcg_temp_new_i32();
10972 TCGv_i64 fp64 = tcg_temp_new_i64();
10973
10974 gen_load_fpr64(ctx, fp64, fs);
10975 gen_helper_float_cvts_l(fp32, cpu_env, fp64);
10976 tcg_temp_free_i64(fp64);
10977 gen_store_fpr32(ctx, fp32, fd);
10978 tcg_temp_free_i32(fp32);
10979 }
10980 break;
10981 case OPC_CVT_D_L:
10982 check_cp1_64bitmode(ctx);
10983 {
10984 TCGv_i64 fp0 = tcg_temp_new_i64();
10985
10986 gen_load_fpr64(ctx, fp0, fs);
10987 gen_helper_float_cvtd_l(fp0, cpu_env, fp0);
10988 gen_store_fpr64(ctx, fp0, fd);
10989 tcg_temp_free_i64(fp0);
10990 }
10991 break;
10992 case OPC_CVT_PS_PW:
10993 check_ps(ctx);
10994 {
10995 TCGv_i64 fp0 = tcg_temp_new_i64();
10996
10997 gen_load_fpr64(ctx, fp0, fs);
10998 gen_helper_float_cvtps_pw(fp0, cpu_env, fp0);
10999 gen_store_fpr64(ctx, fp0, fd);
11000 tcg_temp_free_i64(fp0);
11001 }
11002 break;
11003 case OPC_ADD_PS:
11004 check_ps(ctx);
11005 {
11006 TCGv_i64 fp0 = tcg_temp_new_i64();
11007 TCGv_i64 fp1 = tcg_temp_new_i64();
11008
11009 gen_load_fpr64(ctx, fp0, fs);
11010 gen_load_fpr64(ctx, fp1, ft);
11011 gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1);
11012 tcg_temp_free_i64(fp1);
11013 gen_store_fpr64(ctx, fp0, fd);
11014 tcg_temp_free_i64(fp0);
11015 }
11016 break;
11017 case OPC_SUB_PS:
11018 check_ps(ctx);
11019 {
11020 TCGv_i64 fp0 = tcg_temp_new_i64();
11021 TCGv_i64 fp1 = tcg_temp_new_i64();
11022
11023 gen_load_fpr64(ctx, fp0, fs);
11024 gen_load_fpr64(ctx, fp1, ft);
11025 gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1);
11026 tcg_temp_free_i64(fp1);
11027 gen_store_fpr64(ctx, fp0, fd);
11028 tcg_temp_free_i64(fp0);
11029 }
11030 break;
11031 case OPC_MUL_PS:
11032 check_ps(ctx);
11033 {
11034 TCGv_i64 fp0 = tcg_temp_new_i64();
11035 TCGv_i64 fp1 = tcg_temp_new_i64();
11036
11037 gen_load_fpr64(ctx, fp0, fs);
11038 gen_load_fpr64(ctx, fp1, ft);
11039 gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1);
11040 tcg_temp_free_i64(fp1);
11041 gen_store_fpr64(ctx, fp0, fd);
11042 tcg_temp_free_i64(fp0);
11043 }
11044 break;
11045 case OPC_ABS_PS:
11046 check_ps(ctx);
11047 {
11048 TCGv_i64 fp0 = tcg_temp_new_i64();
11049
11050 gen_load_fpr64(ctx, fp0, fs);
11051 gen_helper_float_abs_ps(fp0, fp0);
11052 gen_store_fpr64(ctx, fp0, fd);
11053 tcg_temp_free_i64(fp0);
11054 }
11055 break;
11056 case OPC_MOV_PS:
11057 check_ps(ctx);
11058 {
11059 TCGv_i64 fp0 = tcg_temp_new_i64();
11060
11061 gen_load_fpr64(ctx, fp0, fs);
11062 gen_store_fpr64(ctx, fp0, fd);
11063 tcg_temp_free_i64(fp0);
11064 }
11065 break;
11066 case OPC_NEG_PS:
11067 check_ps(ctx);
11068 {
11069 TCGv_i64 fp0 = tcg_temp_new_i64();
11070
11071 gen_load_fpr64(ctx, fp0, fs);
11072 gen_helper_float_chs_ps(fp0, fp0);
11073 gen_store_fpr64(ctx, fp0, fd);
11074 tcg_temp_free_i64(fp0);
11075 }
11076 break;
11077 case OPC_MOVCF_PS:
11078 check_ps(ctx);
11079 gen_movcf_ps(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
11080 break;
11081 case OPC_MOVZ_PS:
11082 check_ps(ctx);
11083 {
11084 TCGLabel *l1 = gen_new_label();
11085 TCGv_i64 fp0;
11086
11087 if (ft != 0) {
11088 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
11089 }
11090 fp0 = tcg_temp_new_i64();
11091 gen_load_fpr64(ctx, fp0, fs);
11092 gen_store_fpr64(ctx, fp0, fd);
11093 tcg_temp_free_i64(fp0);
11094 gen_set_label(l1);
11095 }
11096 break;
11097 case OPC_MOVN_PS:
11098 check_ps(ctx);
11099 {
11100 TCGLabel *l1 = gen_new_label();
11101 TCGv_i64 fp0;
11102
11103 if (ft != 0) {
11104 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
11105 fp0 = tcg_temp_new_i64();
11106 gen_load_fpr64(ctx, fp0, fs);
11107 gen_store_fpr64(ctx, fp0, fd);
11108 tcg_temp_free_i64(fp0);
11109 gen_set_label(l1);
11110 }
11111 }
11112 break;
11113 case OPC_ADDR_PS:
11114 check_ps(ctx);
11115 {
11116 TCGv_i64 fp0 = tcg_temp_new_i64();
11117 TCGv_i64 fp1 = tcg_temp_new_i64();
11118
11119 gen_load_fpr64(ctx, fp0, ft);
11120 gen_load_fpr64(ctx, fp1, fs);
11121 gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1);
11122 tcg_temp_free_i64(fp1);
11123 gen_store_fpr64(ctx, fp0, fd);
11124 tcg_temp_free_i64(fp0);
11125 }
11126 break;
11127 case OPC_MULR_PS:
11128 check_ps(ctx);
11129 {
11130 TCGv_i64 fp0 = tcg_temp_new_i64();
11131 TCGv_i64 fp1 = tcg_temp_new_i64();
11132
11133 gen_load_fpr64(ctx, fp0, ft);
11134 gen_load_fpr64(ctx, fp1, fs);
11135 gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1);
11136 tcg_temp_free_i64(fp1);
11137 gen_store_fpr64(ctx, fp0, fd);
11138 tcg_temp_free_i64(fp0);
11139 }
11140 break;
11141 case OPC_RECIP2_PS:
11142 check_ps(ctx);
11143 {
11144 TCGv_i64 fp0 = tcg_temp_new_i64();
11145 TCGv_i64 fp1 = tcg_temp_new_i64();
11146
11147 gen_load_fpr64(ctx, fp0, fs);
11148 gen_load_fpr64(ctx, fp1, ft);
11149 gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1);
11150 tcg_temp_free_i64(fp1);
11151 gen_store_fpr64(ctx, fp0, fd);
11152 tcg_temp_free_i64(fp0);
11153 }
11154 break;
11155 case OPC_RECIP1_PS:
11156 check_ps(ctx);
11157 {
11158 TCGv_i64 fp0 = tcg_temp_new_i64();
11159
11160 gen_load_fpr64(ctx, fp0, fs);
11161 gen_helper_float_recip1_ps(fp0, cpu_env, fp0);
11162 gen_store_fpr64(ctx, fp0, fd);
11163 tcg_temp_free_i64(fp0);
11164 }
11165 break;
11166 case OPC_RSQRT1_PS:
11167 check_ps(ctx);
11168 {
11169 TCGv_i64 fp0 = tcg_temp_new_i64();
11170
11171 gen_load_fpr64(ctx, fp0, fs);
11172 gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0);
11173 gen_store_fpr64(ctx, fp0, fd);
11174 tcg_temp_free_i64(fp0);
11175 }
11176 break;
11177 case OPC_RSQRT2_PS:
11178 check_ps(ctx);
11179 {
11180 TCGv_i64 fp0 = tcg_temp_new_i64();
11181 TCGv_i64 fp1 = tcg_temp_new_i64();
11182
11183 gen_load_fpr64(ctx, fp0, fs);
11184 gen_load_fpr64(ctx, fp1, ft);
11185 gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1);
11186 tcg_temp_free_i64(fp1);
11187 gen_store_fpr64(ctx, fp0, fd);
11188 tcg_temp_free_i64(fp0);
11189 }
11190 break;
11191 case OPC_CVT_S_PU:
11192 check_cp1_64bitmode(ctx);
11193 {
11194 TCGv_i32 fp0 = tcg_temp_new_i32();
11195
11196 gen_load_fpr32h(ctx, fp0, fs);
11197 gen_helper_float_cvts_pu(fp0, cpu_env, fp0);
11198 gen_store_fpr32(ctx, fp0, fd);
11199 tcg_temp_free_i32(fp0);
11200 }
11201 break;
11202 case OPC_CVT_PW_PS:
11203 check_ps(ctx);
11204 {
11205 TCGv_i64 fp0 = tcg_temp_new_i64();
11206
11207 gen_load_fpr64(ctx, fp0, fs);
11208 gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0);
11209 gen_store_fpr64(ctx, fp0, fd);
11210 tcg_temp_free_i64(fp0);
11211 }
11212 break;
11213 case OPC_CVT_S_PL:
11214 check_cp1_64bitmode(ctx);
11215 {
11216 TCGv_i32 fp0 = tcg_temp_new_i32();
11217
11218 gen_load_fpr32(ctx, fp0, fs);
11219 gen_helper_float_cvts_pl(fp0, cpu_env, fp0);
11220 gen_store_fpr32(ctx, fp0, fd);
11221 tcg_temp_free_i32(fp0);
11222 }
11223 break;
11224 case OPC_PLL_PS:
11225 check_ps(ctx);
11226 {
11227 TCGv_i32 fp0 = tcg_temp_new_i32();
11228 TCGv_i32 fp1 = tcg_temp_new_i32();
11229
11230 gen_load_fpr32(ctx, fp0, fs);
11231 gen_load_fpr32(ctx, fp1, ft);
11232 gen_store_fpr32h(ctx, fp0, fd);
11233 gen_store_fpr32(ctx, fp1, fd);
11234 tcg_temp_free_i32(fp0);
11235 tcg_temp_free_i32(fp1);
11236 }
11237 break;
11238 case OPC_PLU_PS:
11239 check_ps(ctx);
11240 {
11241 TCGv_i32 fp0 = tcg_temp_new_i32();
11242 TCGv_i32 fp1 = tcg_temp_new_i32();
11243
11244 gen_load_fpr32(ctx, fp0, fs);
11245 gen_load_fpr32h(ctx, fp1, ft);
11246 gen_store_fpr32(ctx, fp1, fd);
11247 gen_store_fpr32h(ctx, fp0, fd);
11248 tcg_temp_free_i32(fp0);
11249 tcg_temp_free_i32(fp1);
11250 }
11251 break;
11252 case OPC_PUL_PS:
11253 check_ps(ctx);
11254 {
11255 TCGv_i32 fp0 = tcg_temp_new_i32();
11256 TCGv_i32 fp1 = tcg_temp_new_i32();
11257
11258 gen_load_fpr32h(ctx, fp0, fs);
11259 gen_load_fpr32(ctx, fp1, ft);
11260 gen_store_fpr32(ctx, fp1, fd);
11261 gen_store_fpr32h(ctx, fp0, fd);
11262 tcg_temp_free_i32(fp0);
11263 tcg_temp_free_i32(fp1);
11264 }
11265 break;
11266 case OPC_PUU_PS:
11267 check_ps(ctx);
11268 {
11269 TCGv_i32 fp0 = tcg_temp_new_i32();
11270 TCGv_i32 fp1 = tcg_temp_new_i32();
11271
11272 gen_load_fpr32h(ctx, fp0, fs);
11273 gen_load_fpr32h(ctx, fp1, ft);
11274 gen_store_fpr32(ctx, fp1, fd);
11275 gen_store_fpr32h(ctx, fp0, fd);
11276 tcg_temp_free_i32(fp0);
11277 tcg_temp_free_i32(fp1);
11278 }
11279 break;
11280 case OPC_CMP_F_PS:
11281 case OPC_CMP_UN_PS:
11282 case OPC_CMP_EQ_PS:
11283 case OPC_CMP_UEQ_PS:
11284 case OPC_CMP_OLT_PS:
11285 case OPC_CMP_ULT_PS:
11286 case OPC_CMP_OLE_PS:
11287 case OPC_CMP_ULE_PS:
11288 case OPC_CMP_SF_PS:
11289 case OPC_CMP_NGLE_PS:
11290 case OPC_CMP_SEQ_PS:
11291 case OPC_CMP_NGL_PS:
11292 case OPC_CMP_LT_PS:
11293 case OPC_CMP_NGE_PS:
11294 case OPC_CMP_LE_PS:
11295 case OPC_CMP_NGT_PS:
11296 if (ctx->opcode & (1 << 6)) {
11297 gen_cmpabs_ps(ctx, func - 48, ft, fs, cc);
11298 } else {
11299 gen_cmp_ps(ctx, func - 48, ft, fs, cc);
11300 }
11301 break;
11302 default:
11303 MIPS_INVAL("farith");
11304 gen_reserved_instruction(ctx);
11305 return;
11306 }
11307 }
11308
11309 /* Coprocessor 3 (FPU) */
11310 static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
11311 int fd, int fs, int base, int index)
11312 {
11313 TCGv t0 = tcg_temp_new();
11314
11315 if (base == 0) {
11316 gen_load_gpr(t0, index);
11317 } else if (index == 0) {
11318 gen_load_gpr(t0, base);
11319 } else {
11320 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
11321 }
11322 /*
11323 * Don't do NOP if destination is zero: we must perform the actual
11324 * memory access.
11325 */
11326 switch (opc) {
11327 case OPC_LWXC1:
11328 check_cop1x(ctx);
11329 {
11330 TCGv_i32 fp0 = tcg_temp_new_i32();
11331
11332 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
11333 tcg_gen_trunc_tl_i32(fp0, t0);
11334 gen_store_fpr32(ctx, fp0, fd);
11335 tcg_temp_free_i32(fp0);
11336 }
11337 break;
11338 case OPC_LDXC1:
11339 check_cop1x(ctx);
11340 check_cp1_registers(ctx, fd);
11341 {
11342 TCGv_i64 fp0 = tcg_temp_new_i64();
11343 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
11344 gen_store_fpr64(ctx, fp0, fd);
11345 tcg_temp_free_i64(fp0);
11346 }
11347 break;
11348 case OPC_LUXC1:
11349 check_cp1_64bitmode(ctx);
11350 tcg_gen_andi_tl(t0, t0, ~0x7);
11351 {
11352 TCGv_i64 fp0 = tcg_temp_new_i64();
11353
11354 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
11355 gen_store_fpr64(ctx, fp0, fd);
11356 tcg_temp_free_i64(fp0);
11357 }
11358 break;
11359 case OPC_SWXC1:
11360 check_cop1x(ctx);
11361 {
11362 TCGv_i32 fp0 = tcg_temp_new_i32();
11363 gen_load_fpr32(ctx, fp0, fs);
11364 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL);
11365 tcg_temp_free_i32(fp0);
11366 }
11367 break;
11368 case OPC_SDXC1:
11369 check_cop1x(ctx);
11370 check_cp1_registers(ctx, fs);
11371 {
11372 TCGv_i64 fp0 = tcg_temp_new_i64();
11373 gen_load_fpr64(ctx, fp0, fs);
11374 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
11375 tcg_temp_free_i64(fp0);
11376 }
11377 break;
11378 case OPC_SUXC1:
11379 check_cp1_64bitmode(ctx);
11380 tcg_gen_andi_tl(t0, t0, ~0x7);
11381 {
11382 TCGv_i64 fp0 = tcg_temp_new_i64();
11383 gen_load_fpr64(ctx, fp0, fs);
11384 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
11385 tcg_temp_free_i64(fp0);
11386 }
11387 break;
11388 }
11389 tcg_temp_free(t0);
11390 }
11391
11392 static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
11393 int fd, int fr, int fs, int ft)
11394 {
11395 switch (opc) {
11396 case OPC_ALNV_PS:
11397 check_ps(ctx);
11398 {
11399 TCGv t0 = tcg_temp_local_new();
11400 TCGv_i32 fp = tcg_temp_new_i32();
11401 TCGv_i32 fph = tcg_temp_new_i32();
11402 TCGLabel *l1 = gen_new_label();
11403 TCGLabel *l2 = gen_new_label();
11404
11405 gen_load_gpr(t0, fr);
11406 tcg_gen_andi_tl(t0, t0, 0x7);
11407
11408 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
11409 gen_load_fpr32(ctx, fp, fs);
11410 gen_load_fpr32h(ctx, fph, fs);
11411 gen_store_fpr32(ctx, fp, fd);
11412 gen_store_fpr32h(ctx, fph, fd);
11413 tcg_gen_br(l2);
11414 gen_set_label(l1);
11415 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
11416 tcg_temp_free(t0);
11417 if (cpu_is_bigendian(ctx)) {
11418 gen_load_fpr32(ctx, fp, fs);
11419 gen_load_fpr32h(ctx, fph, ft);
11420 gen_store_fpr32h(ctx, fp, fd);
11421 gen_store_fpr32(ctx, fph, fd);
11422 } else {
11423 gen_load_fpr32h(ctx, fph, fs);
11424 gen_load_fpr32(ctx, fp, ft);
11425 gen_store_fpr32(ctx, fph, fd);
11426 gen_store_fpr32h(ctx, fp, fd);
11427 }
11428 gen_set_label(l2);
11429 tcg_temp_free_i32(fp);
11430 tcg_temp_free_i32(fph);
11431 }
11432 break;
11433 case OPC_MADD_S:
11434 check_cop1x(ctx);
11435 {
11436 TCGv_i32 fp0 = tcg_temp_new_i32();
11437 TCGv_i32 fp1 = tcg_temp_new_i32();
11438 TCGv_i32 fp2 = tcg_temp_new_i32();
11439
11440 gen_load_fpr32(ctx, fp0, fs);
11441 gen_load_fpr32(ctx, fp1, ft);
11442 gen_load_fpr32(ctx, fp2, fr);
11443 gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2);
11444 tcg_temp_free_i32(fp0);
11445 tcg_temp_free_i32(fp1);
11446 gen_store_fpr32(ctx, fp2, fd);
11447 tcg_temp_free_i32(fp2);
11448 }
11449 break;
11450 case OPC_MADD_D:
11451 check_cop1x(ctx);
11452 check_cp1_registers(ctx, fd | fs | ft | fr);
11453 {
11454 TCGv_i64 fp0 = tcg_temp_new_i64();
11455 TCGv_i64 fp1 = tcg_temp_new_i64();
11456 TCGv_i64 fp2 = tcg_temp_new_i64();
11457
11458 gen_load_fpr64(ctx, fp0, fs);
11459 gen_load_fpr64(ctx, fp1, ft);
11460 gen_load_fpr64(ctx, fp2, fr);
11461 gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2);
11462 tcg_temp_free_i64(fp0);
11463 tcg_temp_free_i64(fp1);
11464 gen_store_fpr64(ctx, fp2, fd);
11465 tcg_temp_free_i64(fp2);
11466 }
11467 break;
11468 case OPC_MADD_PS:
11469 check_ps(ctx);
11470 {
11471 TCGv_i64 fp0 = tcg_temp_new_i64();
11472 TCGv_i64 fp1 = tcg_temp_new_i64();
11473 TCGv_i64 fp2 = tcg_temp_new_i64();
11474
11475 gen_load_fpr64(ctx, fp0, fs);
11476 gen_load_fpr64(ctx, fp1, ft);
11477 gen_load_fpr64(ctx, fp2, fr);
11478 gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2);
11479 tcg_temp_free_i64(fp0);
11480 tcg_temp_free_i64(fp1);
11481 gen_store_fpr64(ctx, fp2, fd);
11482 tcg_temp_free_i64(fp2);
11483 }
11484 break;
11485 case OPC_MSUB_S:
11486 check_cop1x(ctx);
11487 {
11488 TCGv_i32 fp0 = tcg_temp_new_i32();
11489 TCGv_i32 fp1 = tcg_temp_new_i32();
11490 TCGv_i32 fp2 = tcg_temp_new_i32();
11491
11492 gen_load_fpr32(ctx, fp0, fs);
11493 gen_load_fpr32(ctx, fp1, ft);
11494 gen_load_fpr32(ctx, fp2, fr);
11495 gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2);
11496 tcg_temp_free_i32(fp0);
11497 tcg_temp_free_i32(fp1);
11498 gen_store_fpr32(ctx, fp2, fd);
11499 tcg_temp_free_i32(fp2);
11500 }
11501 break;
11502 case OPC_MSUB_D:
11503 check_cop1x(ctx);
11504 check_cp1_registers(ctx, fd | fs | ft | fr);
11505 {
11506 TCGv_i64 fp0 = tcg_temp_new_i64();
11507 TCGv_i64 fp1 = tcg_temp_new_i64();
11508 TCGv_i64 fp2 = tcg_temp_new_i64();
11509
11510 gen_load_fpr64(ctx, fp0, fs);
11511 gen_load_fpr64(ctx, fp1, ft);
11512 gen_load_fpr64(ctx, fp2, fr);
11513 gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2);
11514 tcg_temp_free_i64(fp0);
11515 tcg_temp_free_i64(fp1);
11516 gen_store_fpr64(ctx, fp2, fd);
11517 tcg_temp_free_i64(fp2);
11518 }
11519 break;
11520 case OPC_MSUB_PS:
11521 check_ps(ctx);
11522 {
11523 TCGv_i64 fp0 = tcg_temp_new_i64();
11524 TCGv_i64 fp1 = tcg_temp_new_i64();
11525 TCGv_i64 fp2 = tcg_temp_new_i64();
11526
11527 gen_load_fpr64(ctx, fp0, fs);
11528 gen_load_fpr64(ctx, fp1, ft);
11529 gen_load_fpr64(ctx, fp2, fr);
11530 gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2);
11531 tcg_temp_free_i64(fp0);
11532 tcg_temp_free_i64(fp1);
11533 gen_store_fpr64(ctx, fp2, fd);
11534 tcg_temp_free_i64(fp2);
11535 }
11536 break;
11537 case OPC_NMADD_S:
11538 check_cop1x(ctx);
11539 {
11540 TCGv_i32 fp0 = tcg_temp_new_i32();
11541 TCGv_i32 fp1 = tcg_temp_new_i32();
11542 TCGv_i32 fp2 = tcg_temp_new_i32();
11543
11544 gen_load_fpr32(ctx, fp0, fs);
11545 gen_load_fpr32(ctx, fp1, ft);
11546 gen_load_fpr32(ctx, fp2, fr);
11547 gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2);
11548 tcg_temp_free_i32(fp0);
11549 tcg_temp_free_i32(fp1);
11550 gen_store_fpr32(ctx, fp2, fd);
11551 tcg_temp_free_i32(fp2);
11552 }
11553 break;
11554 case OPC_NMADD_D:
11555 check_cop1x(ctx);
11556 check_cp1_registers(ctx, fd | fs | ft | fr);
11557 {
11558 TCGv_i64 fp0 = tcg_temp_new_i64();
11559 TCGv_i64 fp1 = tcg_temp_new_i64();
11560 TCGv_i64 fp2 = tcg_temp_new_i64();
11561
11562 gen_load_fpr64(ctx, fp0, fs);
11563 gen_load_fpr64(ctx, fp1, ft);
11564 gen_load_fpr64(ctx, fp2, fr);
11565 gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2);
11566 tcg_temp_free_i64(fp0);
11567 tcg_temp_free_i64(fp1);
11568 gen_store_fpr64(ctx, fp2, fd);
11569 tcg_temp_free_i64(fp2);
11570 }
11571 break;
11572 case OPC_NMADD_PS:
11573 check_ps(ctx);
11574 {
11575 TCGv_i64 fp0 = tcg_temp_new_i64();
11576 TCGv_i64 fp1 = tcg_temp_new_i64();
11577 TCGv_i64 fp2 = tcg_temp_new_i64();
11578
11579 gen_load_fpr64(ctx, fp0, fs);
11580 gen_load_fpr64(ctx, fp1, ft);
11581 gen_load_fpr64(ctx, fp2, fr);
11582 gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2);
11583 tcg_temp_free_i64(fp0);
11584 tcg_temp_free_i64(fp1);
11585 gen_store_fpr64(ctx, fp2, fd);
11586 tcg_temp_free_i64(fp2);
11587 }
11588 break;
11589 case OPC_NMSUB_S:
11590 check_cop1x(ctx);
11591 {
11592 TCGv_i32 fp0 = tcg_temp_new_i32();
11593 TCGv_i32 fp1 = tcg_temp_new_i32();
11594 TCGv_i32 fp2 = tcg_temp_new_i32();
11595
11596 gen_load_fpr32(ctx, fp0, fs);
11597 gen_load_fpr32(ctx, fp1, ft);
11598 gen_load_fpr32(ctx, fp2, fr);
11599 gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2);
11600 tcg_temp_free_i32(fp0);
11601 tcg_temp_free_i32(fp1);
11602 gen_store_fpr32(ctx, fp2, fd);
11603 tcg_temp_free_i32(fp2);
11604 }
11605 break;
11606 case OPC_NMSUB_D:
11607 check_cop1x(ctx);
11608 check_cp1_registers(ctx, fd | fs | ft | fr);
11609 {
11610 TCGv_i64 fp0 = tcg_temp_new_i64();
11611 TCGv_i64 fp1 = tcg_temp_new_i64();
11612 TCGv_i64 fp2 = tcg_temp_new_i64();
11613
11614 gen_load_fpr64(ctx, fp0, fs);
11615 gen_load_fpr64(ctx, fp1, ft);
11616 gen_load_fpr64(ctx, fp2, fr);
11617 gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2);
11618 tcg_temp_free_i64(fp0);
11619 tcg_temp_free_i64(fp1);
11620 gen_store_fpr64(ctx, fp2, fd);
11621 tcg_temp_free_i64(fp2);
11622 }
11623 break;
11624 case OPC_NMSUB_PS:
11625 check_ps(ctx);
11626 {
11627 TCGv_i64 fp0 = tcg_temp_new_i64();
11628 TCGv_i64 fp1 = tcg_temp_new_i64();
11629 TCGv_i64 fp2 = tcg_temp_new_i64();
11630
11631 gen_load_fpr64(ctx, fp0, fs);
11632 gen_load_fpr64(ctx, fp1, ft);
11633 gen_load_fpr64(ctx, fp2, fr);
11634 gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2);
11635 tcg_temp_free_i64(fp0);
11636 tcg_temp_free_i64(fp1);
11637 gen_store_fpr64(ctx, fp2, fd);
11638 tcg_temp_free_i64(fp2);
11639 }
11640 break;
11641 default:
11642 MIPS_INVAL("flt3_arith");
11643 gen_reserved_instruction(ctx);
11644 return;
11645 }
11646 }
11647
11648 void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
11649 {
11650 TCGv t0;
11651
11652 #if !defined(CONFIG_USER_ONLY)
11653 /*
11654 * The Linux kernel will emulate rdhwr if it's not supported natively.
11655 * Therefore only check the ISA in system mode.
11656 */
11657 check_insn(ctx, ISA_MIPS_R2);
11658 #endif
11659 t0 = tcg_temp_new();
11660
11661 switch (rd) {
11662 case 0:
11663 gen_helper_rdhwr_cpunum(t0, cpu_env);
11664 gen_store_gpr(t0, rt);
11665 break;
11666 case 1:
11667 gen_helper_rdhwr_synci_step(t0, cpu_env);
11668 gen_store_gpr(t0, rt);
11669 break;
11670 case 2:
11671 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
11672 gen_io_start();
11673 }
11674 gen_helper_rdhwr_cc(t0, cpu_env);
11675 gen_store_gpr(t0, rt);
11676 /*
11677 * Break the TB to be able to take timer interrupts immediately
11678 * after reading count. DISAS_STOP isn't sufficient, we need to ensure
11679 * we break completely out of translated code.
11680 */
11681 gen_save_pc(ctx->base.pc_next + 4);
11682 ctx->base.is_jmp = DISAS_EXIT;
11683 break;
11684 case 3:
11685 gen_helper_rdhwr_ccres(t0, cpu_env);
11686 gen_store_gpr(t0, rt);
11687 break;
11688 case 4:
11689 check_insn(ctx, ISA_MIPS_R6);
11690 if (sel != 0) {
11691 /*
11692 * Performance counter registers are not implemented other than
11693 * control register 0.
11694 */
11695 generate_exception(ctx, EXCP_RI);
11696 }
11697 gen_helper_rdhwr_performance(t0, cpu_env);
11698 gen_store_gpr(t0, rt);
11699 break;
11700 case 5:
11701 check_insn(ctx, ISA_MIPS_R6);
11702 gen_helper_rdhwr_xnp(t0, cpu_env);
11703 gen_store_gpr(t0, rt);
11704 break;
11705 case 29:
11706 #if defined(CONFIG_USER_ONLY)
11707 tcg_gen_ld_tl(t0, cpu_env,
11708 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
11709 gen_store_gpr(t0, rt);
11710 break;
11711 #else
11712 if ((ctx->hflags & MIPS_HFLAG_CP0) ||
11713 (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) {
11714 tcg_gen_ld_tl(t0, cpu_env,
11715 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
11716 gen_store_gpr(t0, rt);
11717 } else {
11718 gen_reserved_instruction(ctx);
11719 }
11720 break;
11721 #endif
11722 default: /* Invalid */
11723 MIPS_INVAL("rdhwr");
11724 gen_reserved_instruction(ctx);
11725 break;
11726 }
11727 tcg_temp_free(t0);
11728 }
11729
11730 static inline void clear_branch_hflags(DisasContext *ctx)
11731 {
11732 ctx->hflags &= ~MIPS_HFLAG_BMASK;
11733 if (ctx->base.is_jmp == DISAS_NEXT) {
11734 save_cpu_state(ctx, 0);
11735 } else {
11736 /*
11737 * It is not safe to save ctx->hflags as hflags may be changed
11738 * in execution time by the instruction in delay / forbidden slot.
11739 */
11740 tcg_gen_andi_i32(hflags, hflags, ~MIPS_HFLAG_BMASK);
11741 }
11742 }
11743
11744 static void gen_branch(DisasContext *ctx, int insn_bytes)
11745 {
11746 if (ctx->hflags & MIPS_HFLAG_BMASK) {
11747 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK;
11748 /* Branches completion */
11749 clear_branch_hflags(ctx);
11750 ctx->base.is_jmp = DISAS_NORETURN;
11751 /* FIXME: Need to clear can_do_io. */
11752 switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) {
11753 case MIPS_HFLAG_FBNSLOT:
11754 gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes);
11755 break;
11756 case MIPS_HFLAG_B:
11757 /* unconditional branch */
11758 if (proc_hflags & MIPS_HFLAG_BX) {
11759 tcg_gen_xori_i32(hflags, hflags, MIPS_HFLAG_M16);
11760 }
11761 gen_goto_tb(ctx, 0, ctx->btarget);
11762 break;
11763 case MIPS_HFLAG_BL:
11764 /* blikely taken case */
11765 gen_goto_tb(ctx, 0, ctx->btarget);
11766 break;
11767 case MIPS_HFLAG_BC:
11768 /* Conditional branch */
11769 {
11770 TCGLabel *l1 = gen_new_label();
11771
11772 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
11773 gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes);
11774 gen_set_label(l1);
11775 gen_goto_tb(ctx, 0, ctx->btarget);
11776 }
11777 break;
11778 case MIPS_HFLAG_BR:
11779 /* unconditional branch to register */
11780 if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) {
11781 TCGv t0 = tcg_temp_new();
11782 TCGv_i32 t1 = tcg_temp_new_i32();
11783
11784 tcg_gen_andi_tl(t0, btarget, 0x1);
11785 tcg_gen_trunc_tl_i32(t1, t0);
11786 tcg_temp_free(t0);
11787 tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16);
11788 tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT);
11789 tcg_gen_or_i32(hflags, hflags, t1);
11790 tcg_temp_free_i32(t1);
11791
11792 tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1);
11793 } else {
11794 tcg_gen_mov_tl(cpu_PC, btarget);
11795 }
11796 tcg_gen_lookup_and_goto_ptr();
11797 break;
11798 default:
11799 LOG_DISAS("unknown branch 0x%x\n", proc_hflags);
11800 gen_reserved_instruction(ctx);
11801 }
11802 }
11803 }
11804
11805 /* Compact Branches */
11806 static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
11807 int rs, int rt, int32_t offset)
11808 {
11809 int bcond_compute = 0;
11810 TCGv t0 = tcg_temp_new();
11811 TCGv t1 = tcg_temp_new();
11812 int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0;
11813
11814 if (ctx->hflags & MIPS_HFLAG_BMASK) {
11815 #ifdef MIPS_DEBUG_DISAS
11816 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
11817 "\n", ctx->base.pc_next);
11818 #endif
11819 gen_reserved_instruction(ctx);
11820 goto out;
11821 }
11822
11823 /* Load needed operands and calculate btarget */
11824 switch (opc) {
11825 /* compact branch */
11826 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
11827 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
11828 gen_load_gpr(t0, rs);
11829 gen_load_gpr(t1, rt);
11830 bcond_compute = 1;
11831 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
11832 if (rs <= rt && rs == 0) {
11833 /* OPC_BEQZALC, OPC_BNEZALC */
11834 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
11835 }
11836 break;
11837 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
11838 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
11839 gen_load_gpr(t0, rs);
11840 gen_load_gpr(t1, rt);
11841 bcond_compute = 1;
11842 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
11843 break;
11844 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
11845 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
11846 if (rs == 0 || rs == rt) {
11847 /* OPC_BLEZALC, OPC_BGEZALC */
11848 /* OPC_BGTZALC, OPC_BLTZALC */
11849 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
11850 }
11851 gen_load_gpr(t0, rs);
11852 gen_load_gpr(t1, rt);
11853 bcond_compute = 1;
11854 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
11855 break;
11856 case OPC_BC:
11857 case OPC_BALC:
11858 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
11859 break;
11860 case OPC_BEQZC:
11861 case OPC_BNEZC:
11862 if (rs != 0) {
11863 /* OPC_BEQZC, OPC_BNEZC */
11864 gen_load_gpr(t0, rs);
11865 bcond_compute = 1;
11866 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
11867 } else {
11868 /* OPC_JIC, OPC_JIALC */
11869 TCGv tbase = tcg_temp_new();
11870 TCGv toffset = tcg_constant_tl(offset);
11871
11872 gen_load_gpr(tbase, rt);
11873 gen_op_addr_add(ctx, btarget, tbase, toffset);
11874 tcg_temp_free(tbase);
11875 }
11876 break;
11877 default:
11878 MIPS_INVAL("Compact branch/jump");
11879 gen_reserved_instruction(ctx);
11880 goto out;
11881 }
11882
11883 if (bcond_compute == 0) {
11884 /* Unconditional compact branch */
11885 switch (opc) {
11886 case OPC_JIALC:
11887 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
11888 /* Fallthrough */
11889 case OPC_JIC:
11890 ctx->hflags |= MIPS_HFLAG_BR;
11891 break;
11892 case OPC_BALC:
11893 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
11894 /* Fallthrough */
11895 case OPC_BC:
11896 ctx->hflags |= MIPS_HFLAG_B;
11897 break;
11898 default:
11899 MIPS_INVAL("Compact branch/jump");
11900 gen_reserved_instruction(ctx);
11901 goto out;
11902 }
11903
11904 /* Generating branch here as compact branches don't have delay slot */
11905 gen_branch(ctx, 4);
11906 } else {
11907 /* Conditional compact branch */
11908 TCGLabel *fs = gen_new_label();
11909 save_cpu_state(ctx, 0);
11910
11911 switch (opc) {
11912 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
11913 if (rs == 0 && rt != 0) {
11914 /* OPC_BLEZALC */
11915 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
11916 } else if (rs != 0 && rt != 0 && rs == rt) {
11917 /* OPC_BGEZALC */
11918 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
11919 } else {
11920 /* OPC_BGEUC */
11921 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs);
11922 }
11923 break;
11924 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
11925 if (rs == 0 && rt != 0) {
11926 /* OPC_BGTZALC */
11927 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
11928 } else if (rs != 0 && rt != 0 && rs == rt) {
11929 /* OPC_BLTZALC */
11930 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
11931 } else {
11932 /* OPC_BLTUC */
11933 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs);
11934 }
11935 break;
11936 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
11937 if (rs == 0 && rt != 0) {
11938 /* OPC_BLEZC */
11939 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
11940 } else if (rs != 0 && rt != 0 && rs == rt) {
11941 /* OPC_BGEZC */
11942 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
11943 } else {
11944 /* OPC_BGEC */
11945 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
11946 }
11947 break;
11948 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
11949 if (rs == 0 && rt != 0) {
11950 /* OPC_BGTZC */
11951 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
11952 } else if (rs != 0 && rt != 0 && rs == rt) {
11953 /* OPC_BLTZC */
11954 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
11955 } else {
11956 /* OPC_BLTC */
11957 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs);
11958 }
11959 break;
11960 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
11961 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
11962 if (rs >= rt) {
11963 /* OPC_BOVC, OPC_BNVC */
11964 TCGv t2 = tcg_temp_new();
11965 TCGv t3 = tcg_temp_new();
11966 TCGv t4 = tcg_temp_new();
11967 TCGv input_overflow = tcg_temp_new();
11968
11969 gen_load_gpr(t0, rs);
11970 gen_load_gpr(t1, rt);
11971 tcg_gen_ext32s_tl(t2, t0);
11972 tcg_gen_setcond_tl(TCG_COND_NE, input_overflow, t2, t0);
11973 tcg_gen_ext32s_tl(t3, t1);
11974 tcg_gen_setcond_tl(TCG_COND_NE, t4, t3, t1);
11975 tcg_gen_or_tl(input_overflow, input_overflow, t4);
11976
11977 tcg_gen_add_tl(t4, t2, t3);
11978 tcg_gen_ext32s_tl(t4, t4);
11979 tcg_gen_xor_tl(t2, t2, t3);
11980 tcg_gen_xor_tl(t3, t4, t3);
11981 tcg_gen_andc_tl(t2, t3, t2);
11982 tcg_gen_setcondi_tl(TCG_COND_LT, t4, t2, 0);
11983 tcg_gen_or_tl(t4, t4, input_overflow);
11984 if (opc == OPC_BOVC) {
11985 /* OPC_BOVC */
11986 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t4, 0, fs);
11987 } else {
11988 /* OPC_BNVC */
11989 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs);
11990 }
11991 tcg_temp_free(input_overflow);
11992 tcg_temp_free(t4);
11993 tcg_temp_free(t3);
11994 tcg_temp_free(t2);
11995 } else if (rs < rt && rs == 0) {
11996 /* OPC_BEQZALC, OPC_BNEZALC */
11997 if (opc == OPC_BEQZALC) {
11998 /* OPC_BEQZALC */
11999 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t1, 0, fs);
12000 } else {
12001 /* OPC_BNEZALC */
12002 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t1, 0, fs);
12003 }
12004 } else {
12005 /* OPC_BEQC, OPC_BNEC */
12006 if (opc == OPC_BEQC) {
12007 /* OPC_BEQC */
12008 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs);
12009 } else {
12010 /* OPC_BNEC */
12011 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs);
12012 }
12013 }
12014 break;
12015 case OPC_BEQZC:
12016 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs);
12017 break;
12018 case OPC_BNEZC:
12019 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t0, 0, fs);
12020 break;
12021 default:
12022 MIPS_INVAL("Compact conditional branch/jump");
12023 gen_reserved_instruction(ctx);
12024 goto out;
12025 }
12026
12027 /* Generating branch here as compact branches don't have delay slot */
12028 gen_goto_tb(ctx, 1, ctx->btarget);
12029 gen_set_label(fs);
12030
12031 ctx->hflags |= MIPS_HFLAG_FBNSLOT;
12032 }
12033
12034 out:
12035 tcg_temp_free(t0);
12036 tcg_temp_free(t1);
12037 }
12038
12039 void gen_addiupc(DisasContext *ctx, int rx, int imm,
12040 int is_64_bit, int extended)
12041 {
12042 TCGv t0;
12043
12044 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
12045 gen_reserved_instruction(ctx);
12046 return;
12047 }
12048
12049 t0 = tcg_temp_new();
12050
12051 tcg_gen_movi_tl(t0, pc_relative_pc(ctx));
12052 tcg_gen_addi_tl(cpu_gpr[rx], t0, imm);
12053 if (!is_64_bit) {
12054 tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
12055 }
12056
12057 tcg_temp_free(t0);
12058 }
12059
12060 static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
12061 int16_t offset)
12062 {
12063 TCGv_i32 t0 = tcg_const_i32(op);
12064 TCGv t1 = tcg_temp_new();
12065 gen_base_offset_addr(ctx, t1, base, offset);
12066 gen_helper_cache(cpu_env, t1, t0);
12067 tcg_temp_free(t1);
12068 tcg_temp_free_i32(t0);
12069 }
12070
12071 static inline bool is_uhi(int sdbbp_code)
12072 {
12073 #ifdef CONFIG_USER_ONLY
12074 return false;
12075 #else
12076 return semihosting_enabled() && sdbbp_code == 1;
12077 #endif
12078 }
12079
12080 #ifdef CONFIG_USER_ONLY
12081 /* The above should dead-code away any calls to this..*/
12082 static inline void gen_helper_do_semihosting(void *env)
12083 {
12084 g_assert_not_reached();
12085 }
12086 #endif
12087
12088 void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
12089 {
12090 TCGv t0 = tcg_temp_new();
12091 TCGv t1 = tcg_temp_new();
12092
12093 gen_load_gpr(t0, base);
12094
12095 if (index != 0) {
12096 gen_load_gpr(t1, index);
12097 tcg_gen_shli_tl(t1, t1, 2);
12098 gen_op_addr_add(ctx, t0, t1, t0);
12099 }
12100
12101 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
12102 gen_store_gpr(t1, rd);
12103
12104 tcg_temp_free(t0);
12105 tcg_temp_free(t1);
12106 }
12107
12108 static void gen_sync(int stype)
12109 {
12110 TCGBar tcg_mo = TCG_BAR_SC;
12111
12112 switch (stype) {
12113 case 0x4: /* SYNC_WMB */
12114 tcg_mo |= TCG_MO_ST_ST;
12115 break;
12116 case 0x10: /* SYNC_MB */
12117 tcg_mo |= TCG_MO_ALL;
12118 break;
12119 case 0x11: /* SYNC_ACQUIRE */
12120 tcg_mo |= TCG_MO_LD_LD | TCG_MO_LD_ST;
12121 break;
12122 case 0x12: /* SYNC_RELEASE */
12123 tcg_mo |= TCG_MO_ST_ST | TCG_MO_LD_ST;
12124 break;
12125 case 0x13: /* SYNC_RMB */
12126 tcg_mo |= TCG_MO_LD_LD;
12127 break;
12128 default:
12129 tcg_mo |= TCG_MO_ALL;
12130 break;
12131 }
12132
12133 tcg_gen_mb(tcg_mo);
12134 }
12135
12136 /* ISA extensions (ASEs) */
12137
12138 /* MIPS16 extension to MIPS32 */
12139 #include "mips16e_translate.c.inc"
12140
12141 /* microMIPS extension to MIPS32/MIPS64 */
12142
12143 /*
12144 * Values for microMIPS fmt field. Variable-width, depending on which
12145 * formats the instruction supports.
12146 */
12147 enum {
12148 FMT_SD_S = 0,
12149 FMT_SD_D = 1,
12150
12151 FMT_SDPS_S = 0,
12152 FMT_SDPS_D = 1,
12153 FMT_SDPS_PS = 2,
12154
12155 FMT_SWL_S = 0,
12156 FMT_SWL_W = 1,
12157 FMT_SWL_L = 2,
12158
12159 FMT_DWL_D = 0,
12160 FMT_DWL_W = 1,
12161 FMT_DWL_L = 2
12162 };
12163
12164 #include "micromips_translate.c.inc"
12165
12166 #include "nanomips_translate.c.inc"
12167
12168 /* MIPSDSP functions. */
12169 static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc,
12170 int rd, int base, int offset)
12171 {
12172 TCGv t0;
12173
12174 check_dsp(ctx);
12175 t0 = tcg_temp_new();
12176
12177 if (base == 0) {
12178 gen_load_gpr(t0, offset);
12179 } else if (offset == 0) {
12180 gen_load_gpr(t0, base);
12181 } else {
12182 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]);
12183 }
12184
12185 switch (opc) {
12186 case OPC_LBUX:
12187 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
12188 gen_store_gpr(t0, rd);
12189 break;
12190 case OPC_LHX:
12191 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW);
12192 gen_store_gpr(t0, rd);
12193 break;
12194 case OPC_LWX:
12195 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
12196 gen_store_gpr(t0, rd);
12197 break;
12198 #if defined(TARGET_MIPS64)
12199 case OPC_LDX:
12200 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ);
12201 gen_store_gpr(t0, rd);
12202 break;
12203 #endif
12204 }
12205 tcg_temp_free(t0);
12206 }
12207
12208 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
12209 int ret, int v1, int v2)
12210 {
12211 TCGv v1_t;
12212 TCGv v2_t;
12213
12214 if (ret == 0) {
12215 /* Treat as NOP. */
12216 return;
12217 }
12218
12219 v1_t = tcg_temp_new();
12220 v2_t = tcg_temp_new();
12221
12222 gen_load_gpr(v1_t, v1);
12223 gen_load_gpr(v2_t, v2);
12224
12225 switch (op1) {
12226 /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
12227 case OPC_MULT_G_2E:
12228 check_dsp_r2(ctx);
12229 switch (op2) {
12230 case OPC_ADDUH_QB:
12231 gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t);
12232 break;
12233 case OPC_ADDUH_R_QB:
12234 gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t);
12235 break;
12236 case OPC_ADDQH_PH:
12237 gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t);
12238 break;
12239 case OPC_ADDQH_R_PH:
12240 gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
12241 break;
12242 case OPC_ADDQH_W:
12243 gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t);
12244 break;
12245 case OPC_ADDQH_R_W:
12246 gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t);
12247 break;
12248 case OPC_SUBUH_QB:
12249 gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t);
12250 break;
12251 case OPC_SUBUH_R_QB:
12252 gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t);
12253 break;
12254 case OPC_SUBQH_PH:
12255 gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t);
12256 break;
12257 case OPC_SUBQH_R_PH:
12258 gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
12259 break;
12260 case OPC_SUBQH_W:
12261 gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t);
12262 break;
12263 case OPC_SUBQH_R_W:
12264 gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t);
12265 break;
12266 }
12267 break;
12268 case OPC_ABSQ_S_PH_DSP:
12269 switch (op2) {
12270 case OPC_ABSQ_S_QB:
12271 check_dsp_r2(ctx);
12272 gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env);
12273 break;
12274 case OPC_ABSQ_S_PH:
12275 check_dsp(ctx);
12276 gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, cpu_env);
12277 break;
12278 case OPC_ABSQ_S_W:
12279 check_dsp(ctx);
12280 gen_helper_absq_s_w(cpu_gpr[ret], v2_t, cpu_env);
12281 break;
12282 case OPC_PRECEQ_W_PHL:
12283 check_dsp(ctx);
12284 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFF0000);
12285 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
12286 break;
12287 case OPC_PRECEQ_W_PHR:
12288 check_dsp(ctx);
12289 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0x0000FFFF);
12290 tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 16);
12291 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
12292 break;
12293 case OPC_PRECEQU_PH_QBL:
12294 check_dsp(ctx);
12295 gen_helper_precequ_ph_qbl(cpu_gpr[ret], v2_t);
12296 break;
12297 case OPC_PRECEQU_PH_QBR:
12298 check_dsp(ctx);
12299 gen_helper_precequ_ph_qbr(cpu_gpr[ret], v2_t);
12300 break;
12301 case OPC_PRECEQU_PH_QBLA:
12302 check_dsp(ctx);
12303 gen_helper_precequ_ph_qbla(cpu_gpr[ret], v2_t);
12304 break;
12305 case OPC_PRECEQU_PH_QBRA:
12306 check_dsp(ctx);
12307 gen_helper_precequ_ph_qbra(cpu_gpr[ret], v2_t);
12308 break;
12309 case OPC_PRECEU_PH_QBL:
12310 check_dsp(ctx);
12311 gen_helper_preceu_ph_qbl(cpu_gpr[ret], v2_t);
12312 break;
12313 case OPC_PRECEU_PH_QBR:
12314 check_dsp(ctx);
12315 gen_helper_preceu_ph_qbr(cpu_gpr[ret], v2_t);
12316 break;
12317 case OPC_PRECEU_PH_QBLA:
12318 check_dsp(ctx);
12319 gen_helper_preceu_ph_qbla(cpu_gpr[ret], v2_t);
12320 break;
12321 case OPC_PRECEU_PH_QBRA:
12322 check_dsp(ctx);
12323 gen_helper_preceu_ph_qbra(cpu_gpr[ret], v2_t);
12324 break;
12325 }
12326 break;
12327 case OPC_ADDU_QB_DSP:
12328 switch (op2) {
12329 case OPC_ADDQ_PH:
12330 check_dsp(ctx);
12331 gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12332 break;
12333 case OPC_ADDQ_S_PH:
12334 check_dsp(ctx);
12335 gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12336 break;
12337 case OPC_ADDQ_S_W:
12338 check_dsp(ctx);
12339 gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12340 break;
12341 case OPC_ADDU_QB:
12342 check_dsp(ctx);
12343 gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12344 break;
12345 case OPC_ADDU_S_QB:
12346 check_dsp(ctx);
12347 gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12348 break;
12349 case OPC_ADDU_PH:
12350 check_dsp_r2(ctx);
12351 gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12352 break;
12353 case OPC_ADDU_S_PH:
12354 check_dsp_r2(ctx);
12355 gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12356 break;
12357 case OPC_SUBQ_PH:
12358 check_dsp(ctx);
12359 gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12360 break;
12361 case OPC_SUBQ_S_PH:
12362 check_dsp(ctx);
12363 gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12364 break;
12365 case OPC_SUBQ_S_W:
12366 check_dsp(ctx);
12367 gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12368 break;
12369 case OPC_SUBU_QB:
12370 check_dsp(ctx);
12371 gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12372 break;
12373 case OPC_SUBU_S_QB:
12374 check_dsp(ctx);
12375 gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12376 break;
12377 case OPC_SUBU_PH:
12378 check_dsp_r2(ctx);
12379 gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12380 break;
12381 case OPC_SUBU_S_PH:
12382 check_dsp_r2(ctx);
12383 gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12384 break;
12385 case OPC_ADDSC:
12386 check_dsp(ctx);
12387 gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12388 break;
12389 case OPC_ADDWC:
12390 check_dsp(ctx);
12391 gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12392 break;
12393 case OPC_MODSUB:
12394 check_dsp(ctx);
12395 gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t);
12396 break;
12397 case OPC_RADDU_W_QB:
12398 check_dsp(ctx);
12399 gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t);
12400 break;
12401 }
12402 break;
12403 case OPC_CMPU_EQ_QB_DSP:
12404 switch (op2) {
12405 case OPC_PRECR_QB_PH:
12406 check_dsp_r2(ctx);
12407 gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t);
12408 break;
12409 case OPC_PRECRQ_QB_PH:
12410 check_dsp(ctx);
12411 gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t);
12412 break;
12413 case OPC_PRECR_SRA_PH_W:
12414 check_dsp_r2(ctx);
12415 {
12416 TCGv_i32 sa_t = tcg_const_i32(v2);
12417 gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t,
12418 cpu_gpr[ret]);
12419 tcg_temp_free_i32(sa_t);
12420 break;
12421 }
12422 case OPC_PRECR_SRA_R_PH_W:
12423 check_dsp_r2(ctx);
12424 {
12425 TCGv_i32 sa_t = tcg_const_i32(v2);
12426 gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t,
12427 cpu_gpr[ret]);
12428 tcg_temp_free_i32(sa_t);
12429 break;
12430 }
12431 case OPC_PRECRQ_PH_W:
12432 check_dsp(ctx);
12433 gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t);
12434 break;
12435 case OPC_PRECRQ_RS_PH_W:
12436 check_dsp(ctx);
12437 gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12438 break;
12439 case OPC_PRECRQU_S_QB_PH:
12440 check_dsp(ctx);
12441 gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12442 break;
12443 }
12444 break;
12445 #ifdef TARGET_MIPS64
12446 case OPC_ABSQ_S_QH_DSP:
12447 switch (op2) {
12448 case OPC_PRECEQ_L_PWL:
12449 check_dsp(ctx);
12450 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFFFFFF00000000ull);
12451 break;
12452 case OPC_PRECEQ_L_PWR:
12453 check_dsp(ctx);
12454 tcg_gen_shli_tl(cpu_gpr[ret], v2_t, 32);
12455 break;
12456 case OPC_PRECEQ_PW_QHL:
12457 check_dsp(ctx);
12458 gen_helper_preceq_pw_qhl(cpu_gpr[ret], v2_t);
12459 break;
12460 case OPC_PRECEQ_PW_QHR:
12461 check_dsp(ctx);
12462 gen_helper_preceq_pw_qhr(cpu_gpr[ret], v2_t);
12463 break;
12464 case OPC_PRECEQ_PW_QHLA:
12465 check_dsp(ctx);
12466 gen_helper_preceq_pw_qhla(cpu_gpr[ret], v2_t);
12467 break;
12468 case OPC_PRECEQ_PW_QHRA:
12469 check_dsp(ctx);
12470 gen_helper_preceq_pw_qhra(cpu_gpr[ret], v2_t);
12471 break;
12472 case OPC_PRECEQU_QH_OBL:
12473 check_dsp(ctx);
12474 gen_helper_precequ_qh_obl(cpu_gpr[ret], v2_t);
12475 break;
12476 case OPC_PRECEQU_QH_OBR:
12477 check_dsp(ctx);
12478 gen_helper_precequ_qh_obr(cpu_gpr[ret], v2_t);
12479 break;
12480 case OPC_PRECEQU_QH_OBLA:
12481 check_dsp(ctx);
12482 gen_helper_precequ_qh_obla(cpu_gpr[ret], v2_t);
12483 break;
12484 case OPC_PRECEQU_QH_OBRA:
12485 check_dsp(ctx);
12486 gen_helper_precequ_qh_obra(cpu_gpr[ret], v2_t);
12487 break;
12488 case OPC_PRECEU_QH_OBL:
12489 check_dsp(ctx);
12490 gen_helper_preceu_qh_obl(cpu_gpr[ret], v2_t);
12491 break;
12492 case OPC_PRECEU_QH_OBR:
12493 check_dsp(ctx);
12494 gen_helper_preceu_qh_obr(cpu_gpr[ret], v2_t);
12495 break;
12496 case OPC_PRECEU_QH_OBLA:
12497 check_dsp(ctx);
12498 gen_helper_preceu_qh_obla(cpu_gpr[ret], v2_t);
12499 break;
12500 case OPC_PRECEU_QH_OBRA:
12501 check_dsp(ctx);
12502 gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t);
12503 break;
12504 case OPC_ABSQ_S_OB:
12505 check_dsp_r2(ctx);
12506 gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env);
12507 break;
12508 case OPC_ABSQ_S_PW:
12509 check_dsp(ctx);
12510 gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, cpu_env);
12511 break;
12512 case OPC_ABSQ_S_QH:
12513 check_dsp(ctx);
12514 gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, cpu_env);
12515 break;
12516 }
12517 break;
12518 case OPC_ADDU_OB_DSP:
12519 switch (op2) {
12520 case OPC_RADDU_L_OB:
12521 check_dsp(ctx);
12522 gen_helper_raddu_l_ob(cpu_gpr[ret], v1_t);
12523 break;
12524 case OPC_SUBQ_PW:
12525 check_dsp(ctx);
12526 gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12527 break;
12528 case OPC_SUBQ_S_PW:
12529 check_dsp(ctx);
12530 gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12531 break;
12532 case OPC_SUBQ_QH:
12533 check_dsp(ctx);
12534 gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12535 break;
12536 case OPC_SUBQ_S_QH:
12537 check_dsp(ctx);
12538 gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12539 break;
12540 case OPC_SUBU_OB:
12541 check_dsp(ctx);
12542 gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12543 break;
12544 case OPC_SUBU_S_OB:
12545 check_dsp(ctx);
12546 gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12547 break;
12548 case OPC_SUBU_QH:
12549 check_dsp_r2(ctx);
12550 gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12551 break;
12552 case OPC_SUBU_S_QH:
12553 check_dsp_r2(ctx);
12554 gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12555 break;
12556 case OPC_SUBUH_OB:
12557 check_dsp_r2(ctx);
12558 gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t);
12559 break;
12560 case OPC_SUBUH_R_OB:
12561 check_dsp_r2(ctx);
12562 gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t);
12563 break;
12564 case OPC_ADDQ_PW:
12565 check_dsp(ctx);
12566 gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12567 break;
12568 case OPC_ADDQ_S_PW:
12569 check_dsp(ctx);
12570 gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12571 break;
12572 case OPC_ADDQ_QH:
12573 check_dsp(ctx);
12574 gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12575 break;
12576 case OPC_ADDQ_S_QH:
12577 check_dsp(ctx);
12578 gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12579 break;
12580 case OPC_ADDU_OB:
12581 check_dsp(ctx);
12582 gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12583 break;
12584 case OPC_ADDU_S_OB:
12585 check_dsp(ctx);
12586 gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12587 break;
12588 case OPC_ADDU_QH:
12589 check_dsp_r2(ctx);
12590 gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12591 break;
12592 case OPC_ADDU_S_QH:
12593 check_dsp_r2(ctx);
12594 gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12595 break;
12596 case OPC_ADDUH_OB:
12597 check_dsp_r2(ctx);
12598 gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t);
12599 break;
12600 case OPC_ADDUH_R_OB:
12601 check_dsp_r2(ctx);
12602 gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t);
12603 break;
12604 }
12605 break;
12606 case OPC_CMPU_EQ_OB_DSP:
12607 switch (op2) {
12608 case OPC_PRECR_OB_QH:
12609 check_dsp_r2(ctx);
12610 gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t);
12611 break;
12612 case OPC_PRECR_SRA_QH_PW:
12613 check_dsp_r2(ctx);
12614 {
12615 TCGv_i32 ret_t = tcg_const_i32(ret);
12616 gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t);
12617 tcg_temp_free_i32(ret_t);
12618 break;
12619 }
12620 case OPC_PRECR_SRA_R_QH_PW:
12621 check_dsp_r2(ctx);
12622 {
12623 TCGv_i32 sa_v = tcg_const_i32(ret);
12624 gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v);
12625 tcg_temp_free_i32(sa_v);
12626 break;
12627 }
12628 case OPC_PRECRQ_OB_QH:
12629 check_dsp(ctx);
12630 gen_helper_precrq_ob_qh(cpu_gpr[ret], v1_t, v2_t);
12631 break;
12632 case OPC_PRECRQ_PW_L:
12633 check_dsp(ctx);
12634 gen_helper_precrq_pw_l(cpu_gpr[ret], v1_t, v2_t);
12635 break;
12636 case OPC_PRECRQ_QH_PW:
12637 check_dsp(ctx);
12638 gen_helper_precrq_qh_pw(cpu_gpr[ret], v1_t, v2_t);
12639 break;
12640 case OPC_PRECRQ_RS_QH_PW:
12641 check_dsp(ctx);
12642 gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12643 break;
12644 case OPC_PRECRQU_S_OB_QH:
12645 check_dsp(ctx);
12646 gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12647 break;
12648 }
12649 break;
12650 #endif
12651 }
12652
12653 tcg_temp_free(v1_t);
12654 tcg_temp_free(v2_t);
12655 }
12656
12657 static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
12658 int ret, int v1, int v2)
12659 {
12660 uint32_t op2;
12661 TCGv t0;
12662 TCGv v1_t;
12663 TCGv v2_t;
12664
12665 if (ret == 0) {
12666 /* Treat as NOP. */
12667 return;
12668 }
12669
12670 t0 = tcg_temp_new();
12671 v1_t = tcg_temp_new();
12672 v2_t = tcg_temp_new();
12673
12674 tcg_gen_movi_tl(t0, v1);
12675 gen_load_gpr(v1_t, v1);
12676 gen_load_gpr(v2_t, v2);
12677
12678 switch (opc) {
12679 case OPC_SHLL_QB_DSP:
12680 {
12681 op2 = MASK_SHLL_QB(ctx->opcode);
12682 switch (op2) {
12683 case OPC_SHLL_QB:
12684 check_dsp(ctx);
12685 gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, cpu_env);
12686 break;
12687 case OPC_SHLLV_QB:
12688 check_dsp(ctx);
12689 gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12690 break;
12691 case OPC_SHLL_PH:
12692 check_dsp(ctx);
12693 gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
12694 break;
12695 case OPC_SHLLV_PH:
12696 check_dsp(ctx);
12697 gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12698 break;
12699 case OPC_SHLL_S_PH:
12700 check_dsp(ctx);
12701 gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
12702 break;
12703 case OPC_SHLLV_S_PH:
12704 check_dsp(ctx);
12705 gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12706 break;
12707 case OPC_SHLL_S_W:
12708 check_dsp(ctx);
12709 gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, cpu_env);
12710 break;
12711 case OPC_SHLLV_S_W:
12712 check_dsp(ctx);
12713 gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12714 break;
12715 case OPC_SHRL_QB:
12716 check_dsp(ctx);
12717 gen_helper_shrl_qb(cpu_gpr[ret], t0, v2_t);
12718 break;
12719 case OPC_SHRLV_QB:
12720 check_dsp(ctx);
12721 gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t);
12722 break;
12723 case OPC_SHRL_PH:
12724 check_dsp_r2(ctx);
12725 gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t);
12726 break;
12727 case OPC_SHRLV_PH:
12728 check_dsp_r2(ctx);
12729 gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t);
12730 break;
12731 case OPC_SHRA_QB:
12732 check_dsp_r2(ctx);
12733 gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t);
12734 break;
12735 case OPC_SHRA_R_QB:
12736 check_dsp_r2(ctx);
12737 gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t);
12738 break;
12739 case OPC_SHRAV_QB:
12740 check_dsp_r2(ctx);
12741 gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t);
12742 break;
12743 case OPC_SHRAV_R_QB:
12744 check_dsp_r2(ctx);
12745 gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t);
12746 break;
12747 case OPC_SHRA_PH:
12748 check_dsp(ctx);
12749 gen_helper_shra_ph(cpu_gpr[ret], t0, v2_t);
12750 break;
12751 case OPC_SHRA_R_PH:
12752 check_dsp(ctx);
12753 gen_helper_shra_r_ph(cpu_gpr[ret], t0, v2_t);
12754 break;
12755 case OPC_SHRAV_PH:
12756 check_dsp(ctx);
12757 gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t);
12758 break;
12759 case OPC_SHRAV_R_PH:
12760 check_dsp(ctx);
12761 gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t);
12762 break;
12763 case OPC_SHRA_R_W:
12764 check_dsp(ctx);
12765 gen_helper_shra_r_w(cpu_gpr[ret], t0, v2_t);
12766 break;
12767 case OPC_SHRAV_R_W:
12768 check_dsp(ctx);
12769 gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t);
12770 break;
12771 default: /* Invalid */
12772 MIPS_INVAL("MASK SHLL.QB");
12773 gen_reserved_instruction(ctx);
12774 break;
12775 }
12776 break;
12777 }
12778 #ifdef TARGET_MIPS64
12779 case OPC_SHLL_OB_DSP:
12780 op2 = MASK_SHLL_OB(ctx->opcode);
12781 switch (op2) {
12782 case OPC_SHLL_PW:
12783 check_dsp(ctx);
12784 gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
12785 break;
12786 case OPC_SHLLV_PW:
12787 check_dsp(ctx);
12788 gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
12789 break;
12790 case OPC_SHLL_S_PW:
12791 check_dsp(ctx);
12792 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
12793 break;
12794 case OPC_SHLLV_S_PW:
12795 check_dsp(ctx);
12796 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
12797 break;
12798 case OPC_SHLL_OB:
12799 check_dsp(ctx);
12800 gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, cpu_env);
12801 break;
12802 case OPC_SHLLV_OB:
12803 check_dsp(ctx);
12804 gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, cpu_env);
12805 break;
12806 case OPC_SHLL_QH:
12807 check_dsp(ctx);
12808 gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
12809 break;
12810 case OPC_SHLLV_QH:
12811 check_dsp(ctx);
12812 gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
12813 break;
12814 case OPC_SHLL_S_QH:
12815 check_dsp(ctx);
12816 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
12817 break;
12818 case OPC_SHLLV_S_QH:
12819 check_dsp(ctx);
12820 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
12821 break;
12822 case OPC_SHRA_OB:
12823 check_dsp_r2(ctx);
12824 gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0);
12825 break;
12826 case OPC_SHRAV_OB:
12827 check_dsp_r2(ctx);
12828 gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t);
12829 break;
12830 case OPC_SHRA_R_OB:
12831 check_dsp_r2(ctx);
12832 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0);
12833 break;
12834 case OPC_SHRAV_R_OB:
12835 check_dsp_r2(ctx);
12836 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t);
12837 break;
12838 case OPC_SHRA_PW:
12839 check_dsp(ctx);
12840 gen_helper_shra_pw(cpu_gpr[ret], v2_t, t0);
12841 break;
12842 case OPC_SHRAV_PW:
12843 check_dsp(ctx);
12844 gen_helper_shra_pw(cpu_gpr[ret], v2_t, v1_t);
12845 break;
12846 case OPC_SHRA_R_PW:
12847 check_dsp(ctx);
12848 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, t0);
12849 break;
12850 case OPC_SHRAV_R_PW:
12851 check_dsp(ctx);
12852 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, v1_t);
12853 break;
12854 case OPC_SHRA_QH:
12855 check_dsp(ctx);
12856 gen_helper_shra_qh(cpu_gpr[ret], v2_t, t0);
12857 break;
12858 case OPC_SHRAV_QH:
12859 check_dsp(ctx);
12860 gen_helper_shra_qh(cpu_gpr[ret], v2_t, v1_t);
12861 break;
12862 case OPC_SHRA_R_QH:
12863 check_dsp(ctx);
12864 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, t0);
12865 break;
12866 case OPC_SHRAV_R_QH:
12867 check_dsp(ctx);
12868 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, v1_t);
12869 break;
12870 case OPC_SHRL_OB:
12871 check_dsp(ctx);
12872 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, t0);
12873 break;
12874 case OPC_SHRLV_OB:
12875 check_dsp(ctx);
12876 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t);
12877 break;
12878 case OPC_SHRL_QH:
12879 check_dsp_r2(ctx);
12880 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0);
12881 break;
12882 case OPC_SHRLV_QH:
12883 check_dsp_r2(ctx);
12884 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t);
12885 break;
12886 default: /* Invalid */
12887 MIPS_INVAL("MASK SHLL.OB");
12888 gen_reserved_instruction(ctx);
12889 break;
12890 }
12891 break;
12892 #endif
12893 }
12894
12895 tcg_temp_free(t0);
12896 tcg_temp_free(v1_t);
12897 tcg_temp_free(v2_t);
12898 }
12899
12900 static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
12901 int ret, int v1, int v2, int check_ret)
12902 {
12903 TCGv_i32 t0;
12904 TCGv v1_t;
12905 TCGv v2_t;
12906
12907 if ((ret == 0) && (check_ret == 1)) {
12908 /* Treat as NOP. */
12909 return;
12910 }
12911
12912 t0 = tcg_temp_new_i32();
12913 v1_t = tcg_temp_new();
12914 v2_t = tcg_temp_new();
12915
12916 tcg_gen_movi_i32(t0, ret);
12917 gen_load_gpr(v1_t, v1);
12918 gen_load_gpr(v2_t, v2);
12919
12920 switch (op1) {
12921 /*
12922 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
12923 * the same mask and op1.
12924 */
12925 case OPC_MULT_G_2E:
12926 check_dsp_r2(ctx);
12927 switch (op2) {
12928 case OPC_MUL_PH:
12929 gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12930 break;
12931 case OPC_MUL_S_PH:
12932 gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12933 break;
12934 case OPC_MULQ_S_W:
12935 gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12936 break;
12937 case OPC_MULQ_RS_W:
12938 gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
12939 break;
12940 }
12941 break;
12942 case OPC_DPA_W_PH_DSP:
12943 switch (op2) {
12944 case OPC_DPAU_H_QBL:
12945 check_dsp(ctx);
12946 gen_helper_dpau_h_qbl(t0, v1_t, v2_t, cpu_env);
12947 break;
12948 case OPC_DPAU_H_QBR:
12949 check_dsp(ctx);
12950 gen_helper_dpau_h_qbr(t0, v1_t, v2_t, cpu_env);
12951 break;
12952 case OPC_DPSU_H_QBL:
12953 check_dsp(ctx);
12954 gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, cpu_env);
12955 break;
12956 case OPC_DPSU_H_QBR:
12957 check_dsp(ctx);
12958 gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, cpu_env);
12959 break;
12960 case OPC_DPA_W_PH:
12961 check_dsp_r2(ctx);
12962 gen_helper_dpa_w_ph(t0, v1_t, v2_t, cpu_env);
12963 break;
12964 case OPC_DPAX_W_PH:
12965 check_dsp_r2(ctx);
12966 gen_helper_dpax_w_ph(t0, v1_t, v2_t, cpu_env);
12967 break;
12968 case OPC_DPAQ_S_W_PH:
12969 check_dsp(ctx);
12970 gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
12971 break;
12972 case OPC_DPAQX_S_W_PH:
12973 check_dsp_r2(ctx);
12974 gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
12975 break;
12976 case OPC_DPAQX_SA_W_PH:
12977 check_dsp_r2(ctx);
12978 gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
12979 break;
12980 case OPC_DPS_W_PH:
12981 check_dsp_r2(ctx);
12982 gen_helper_dps_w_ph(t0, v1_t, v2_t, cpu_env);
12983 break;
12984 case OPC_DPSX_W_PH:
12985 check_dsp_r2(ctx);
12986 gen_helper_dpsx_w_ph(t0, v1_t, v2_t, cpu_env);
12987 break;
12988 case OPC_DPSQ_S_W_PH:
12989 check_dsp(ctx);
12990 gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, cpu_env);
12991 break;
12992 case OPC_DPSQX_S_W_PH:
12993 check_dsp_r2(ctx);
12994 gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
12995 break;
12996 case OPC_DPSQX_SA_W_PH:
12997 check_dsp_r2(ctx);
12998 gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
12999 break;
13000 case OPC_MULSAQ_S_W_PH:
13001 check_dsp(ctx);
13002 gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
13003 break;
13004 case OPC_DPAQ_SA_L_W:
13005 check_dsp(ctx);
13006 gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, cpu_env);
13007 break;
13008 case OPC_DPSQ_SA_L_W:
13009 check_dsp(ctx);
13010 gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, cpu_env);
13011 break;
13012 case OPC_MAQ_S_W_PHL:
13013 check_dsp(ctx);
13014 gen_helper_maq_s_w_phl(t0, v1_t, v2_t, cpu_env);
13015 break;
13016 case OPC_MAQ_S_W_PHR:
13017 check_dsp(ctx);
13018 gen_helper_maq_s_w_phr(t0, v1_t, v2_t, cpu_env);
13019 break;
13020 case OPC_MAQ_SA_W_PHL:
13021 check_dsp(ctx);
13022 gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, cpu_env);
13023 break;
13024 case OPC_MAQ_SA_W_PHR:
13025 check_dsp(ctx);
13026 gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, cpu_env);
13027 break;
13028 case OPC_MULSA_W_PH:
13029 check_dsp_r2(ctx);
13030 gen_helper_mulsa_w_ph(t0, v1_t, v2_t, cpu_env);
13031 break;
13032 }
13033 break;
13034 #ifdef TARGET_MIPS64
13035 case OPC_DPAQ_W_QH_DSP:
13036 {
13037 int ac = ret & 0x03;
13038 tcg_gen_movi_i32(t0, ac);
13039
13040 switch (op2) {
13041 case OPC_DMADD:
13042 check_dsp(ctx);
13043 gen_helper_dmadd(v1_t, v2_t, t0, cpu_env);
13044 break;
13045 case OPC_DMADDU:
13046 check_dsp(ctx);
13047 gen_helper_dmaddu(v1_t, v2_t, t0, cpu_env);
13048 break;
13049 case OPC_DMSUB:
13050 check_dsp(ctx);
13051 gen_helper_dmsub(v1_t, v2_t, t0, cpu_env);
13052 break;
13053 case OPC_DMSUBU:
13054 check_dsp(ctx);
13055 gen_helper_dmsubu(v1_t, v2_t, t0, cpu_env);
13056 break;
13057 case OPC_DPA_W_QH:
13058 check_dsp_r2(ctx);
13059 gen_helper_dpa_w_qh(v1_t, v2_t, t0, cpu_env);
13060 break;
13061 case OPC_DPAQ_S_W_QH:
13062 check_dsp(ctx);
13063 gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, cpu_env);
13064 break;
13065 case OPC_DPAQ_SA_L_PW:
13066 check_dsp(ctx);
13067 gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, cpu_env);
13068 break;
13069 case OPC_DPAU_H_OBL:
13070 check_dsp(ctx);
13071 gen_helper_dpau_h_obl(v1_t, v2_t, t0, cpu_env);
13072 break;
13073 case OPC_DPAU_H_OBR:
13074 check_dsp(ctx);
13075 gen_helper_dpau_h_obr(v1_t, v2_t, t0, cpu_env);
13076 break;
13077 case OPC_DPS_W_QH:
13078 check_dsp_r2(ctx);
13079 gen_helper_dps_w_qh(v1_t, v2_t, t0, cpu_env);
13080 break;
13081 case OPC_DPSQ_S_W_QH:
13082 check_dsp(ctx);
13083 gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, cpu_env);
13084 break;
13085 case OPC_DPSQ_SA_L_PW:
13086 check_dsp(ctx);
13087 gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, cpu_env);
13088 break;
13089 case OPC_DPSU_H_OBL:
13090 check_dsp(ctx);
13091 gen_helper_dpsu_h_obl(v1_t, v2_t, t0, cpu_env);
13092 break;
13093 case OPC_DPSU_H_OBR:
13094 check_dsp(ctx);
13095 gen_helper_dpsu_h_obr(v1_t, v2_t, t0, cpu_env);
13096 break;
13097 case OPC_MAQ_S_L_PWL:
13098 check_dsp(ctx);
13099 gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, cpu_env);
13100 break;
13101 case OPC_MAQ_S_L_PWR:
13102 check_dsp(ctx);
13103 gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, cpu_env);
13104 break;
13105 case OPC_MAQ_S_W_QHLL:
13106 check_dsp(ctx);
13107 gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, cpu_env);
13108 break;
13109 case OPC_MAQ_SA_W_QHLL:
13110 check_dsp(ctx);
13111 gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, cpu_env);
13112 break;
13113 case OPC_MAQ_S_W_QHLR:
13114 check_dsp(ctx);
13115 gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, cpu_env);
13116 break;
13117 case OPC_MAQ_SA_W_QHLR:
13118 check_dsp(ctx);
13119 gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, cpu_env);
13120 break;
13121 case OPC_MAQ_S_W_QHRL:
13122 check_dsp(ctx);
13123 gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, cpu_env);
13124 break;
13125 case OPC_MAQ_SA_W_QHRL:
13126 check_dsp(ctx);
13127 gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, cpu_env);
13128 break;
13129 case OPC_MAQ_S_W_QHRR:
13130 check_dsp(ctx);
13131 gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, cpu_env);
13132 break;
13133 case OPC_MAQ_SA_W_QHRR:
13134 check_dsp(ctx);
13135 gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, cpu_env);
13136 break;
13137 case OPC_MULSAQ_S_L_PW:
13138 check_dsp(ctx);
13139 gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, cpu_env);
13140 break;
13141 case OPC_MULSAQ_S_W_QH:
13142 check_dsp(ctx);
13143 gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, cpu_env);
13144 break;
13145 }
13146 }
13147 break;
13148 #endif
13149 case OPC_ADDU_QB_DSP:
13150 switch (op2) {
13151 case OPC_MULEU_S_PH_QBL:
13152 check_dsp(ctx);
13153 gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13154 break;
13155 case OPC_MULEU_S_PH_QBR:
13156 check_dsp(ctx);
13157 gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13158 break;
13159 case OPC_MULQ_RS_PH:
13160 check_dsp(ctx);
13161 gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13162 break;
13163 case OPC_MULEQ_S_W_PHL:
13164 check_dsp(ctx);
13165 gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13166 break;
13167 case OPC_MULEQ_S_W_PHR:
13168 check_dsp(ctx);
13169 gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13170 break;
13171 case OPC_MULQ_S_PH:
13172 check_dsp_r2(ctx);
13173 gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13174 break;
13175 }
13176 break;
13177 #ifdef TARGET_MIPS64
13178 case OPC_ADDU_OB_DSP:
13179 switch (op2) {
13180 case OPC_MULEQ_S_PW_QHL:
13181 check_dsp(ctx);
13182 gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13183 break;
13184 case OPC_MULEQ_S_PW_QHR:
13185 check_dsp(ctx);
13186 gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13187 break;
13188 case OPC_MULEU_S_QH_OBL:
13189 check_dsp(ctx);
13190 gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13191 break;
13192 case OPC_MULEU_S_QH_OBR:
13193 check_dsp(ctx);
13194 gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13195 break;
13196 case OPC_MULQ_RS_QH:
13197 check_dsp(ctx);
13198 gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13199 break;
13200 }
13201 break;
13202 #endif
13203 }
13204
13205 tcg_temp_free_i32(t0);
13206 tcg_temp_free(v1_t);
13207 tcg_temp_free(v2_t);
13208 }
13209
13210 static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
13211 int ret, int val)
13212 {
13213 int16_t imm;
13214 TCGv t0;
13215 TCGv val_t;
13216
13217 if (ret == 0) {
13218 /* Treat as NOP. */
13219 return;
13220 }
13221
13222 t0 = tcg_temp_new();
13223 val_t = tcg_temp_new();
13224 gen_load_gpr(val_t, val);
13225
13226 switch (op1) {
13227 case OPC_ABSQ_S_PH_DSP:
13228 switch (op2) {
13229 case OPC_BITREV:
13230 check_dsp(ctx);
13231 gen_helper_bitrev(cpu_gpr[ret], val_t);
13232 break;
13233 case OPC_REPL_QB:
13234 check_dsp(ctx);
13235 {
13236 target_long result;
13237 imm = (ctx->opcode >> 16) & 0xFF;
13238 result = (uint32_t)imm << 24 |
13239 (uint32_t)imm << 16 |
13240 (uint32_t)imm << 8 |
13241 (uint32_t)imm;
13242 result = (int32_t)result;
13243 tcg_gen_movi_tl(cpu_gpr[ret], result);
13244 }
13245 break;
13246 case OPC_REPLV_QB:
13247 check_dsp(ctx);
13248 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
13249 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
13250 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
13251 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
13252 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
13253 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
13254 break;
13255 case OPC_REPL_PH:
13256 check_dsp(ctx);
13257 {
13258 imm = (ctx->opcode >> 16) & 0x03FF;
13259 imm = (int16_t)(imm << 6) >> 6;
13260 tcg_gen_movi_tl(cpu_gpr[ret], \
13261 (target_long)((int32_t)imm << 16 | \
13262 (uint16_t)imm));
13263 }
13264 break;
13265 case OPC_REPLV_PH:
13266 check_dsp(ctx);
13267 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
13268 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
13269 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
13270 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
13271 break;
13272 }
13273 break;
13274 #ifdef TARGET_MIPS64
13275 case OPC_ABSQ_S_QH_DSP:
13276 switch (op2) {
13277 case OPC_REPL_OB:
13278 check_dsp(ctx);
13279 {
13280 target_long temp;
13281
13282 imm = (ctx->opcode >> 16) & 0xFF;
13283 temp = ((uint64_t)imm << 8) | (uint64_t)imm;
13284 temp = (temp << 16) | temp;
13285 temp = (temp << 32) | temp;
13286 tcg_gen_movi_tl(cpu_gpr[ret], temp);
13287 break;
13288 }
13289 case OPC_REPL_PW:
13290 check_dsp(ctx);
13291 {
13292 target_long temp;
13293
13294 imm = (ctx->opcode >> 16) & 0x03FF;
13295 imm = (int16_t)(imm << 6) >> 6;
13296 temp = ((target_long)imm << 32) \
13297 | ((target_long)imm & 0xFFFFFFFF);
13298 tcg_gen_movi_tl(cpu_gpr[ret], temp);
13299 break;
13300 }
13301 case OPC_REPL_QH:
13302 check_dsp(ctx);
13303 {
13304 target_long temp;
13305
13306 imm = (ctx->opcode >> 16) & 0x03FF;
13307 imm = (int16_t)(imm << 6) >> 6;
13308
13309 temp = ((uint64_t)(uint16_t)imm << 48) |
13310 ((uint64_t)(uint16_t)imm << 32) |
13311 ((uint64_t)(uint16_t)imm << 16) |
13312 (uint64_t)(uint16_t)imm;
13313 tcg_gen_movi_tl(cpu_gpr[ret], temp);
13314 break;
13315 }
13316 case OPC_REPLV_OB:
13317 check_dsp(ctx);
13318 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
13319 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
13320 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
13321 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
13322 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
13323 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
13324 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
13325 break;
13326 case OPC_REPLV_PW:
13327 check_dsp(ctx);
13328 tcg_gen_ext32u_i64(cpu_gpr[ret], val_t);
13329 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
13330 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
13331 break;
13332 case OPC_REPLV_QH:
13333 check_dsp(ctx);
13334 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
13335 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
13336 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
13337 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
13338 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
13339 break;
13340 }
13341 break;
13342 #endif
13343 }
13344 tcg_temp_free(t0);
13345 tcg_temp_free(val_t);
13346 }
13347
13348 static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
13349 uint32_t op1, uint32_t op2,
13350 int ret, int v1, int v2, int check_ret)
13351 {
13352 TCGv t1;
13353 TCGv v1_t;
13354 TCGv v2_t;
13355
13356 if ((ret == 0) && (check_ret == 1)) {
13357 /* Treat as NOP. */
13358 return;
13359 }
13360
13361 t1 = tcg_temp_new();
13362 v1_t = tcg_temp_new();
13363 v2_t = tcg_temp_new();
13364
13365 gen_load_gpr(v1_t, v1);
13366 gen_load_gpr(v2_t, v2);
13367
13368 switch (op1) {
13369 case OPC_CMPU_EQ_QB_DSP:
13370 switch (op2) {
13371 case OPC_CMPU_EQ_QB:
13372 check_dsp(ctx);
13373 gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env);
13374 break;
13375 case OPC_CMPU_LT_QB:
13376 check_dsp(ctx);
13377 gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env);
13378 break;
13379 case OPC_CMPU_LE_QB:
13380 check_dsp(ctx);
13381 gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env);
13382 break;
13383 case OPC_CMPGU_EQ_QB:
13384 check_dsp(ctx);
13385 gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t);
13386 break;
13387 case OPC_CMPGU_LT_QB:
13388 check_dsp(ctx);
13389 gen_helper_cmpgu_lt_qb(cpu_gpr[ret], v1_t, v2_t);
13390 break;
13391 case OPC_CMPGU_LE_QB:
13392 check_dsp(ctx);
13393 gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t);
13394 break;
13395 case OPC_CMPGDU_EQ_QB:
13396 check_dsp_r2(ctx);
13397 gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t);
13398 tcg_gen_mov_tl(cpu_gpr[ret], t1);
13399 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
13400 tcg_gen_shli_tl(t1, t1, 24);
13401 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
13402 break;
13403 case OPC_CMPGDU_LT_QB:
13404 check_dsp_r2(ctx);
13405 gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t);
13406 tcg_gen_mov_tl(cpu_gpr[ret], t1);
13407 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
13408 tcg_gen_shli_tl(t1, t1, 24);
13409 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
13410 break;
13411 case OPC_CMPGDU_LE_QB:
13412 check_dsp_r2(ctx);
13413 gen_helper_cmpgu_le_qb(t1, v1_t, v2_t);
13414 tcg_gen_mov_tl(cpu_gpr[ret], t1);
13415 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
13416 tcg_gen_shli_tl(t1, t1, 24);
13417 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
13418 break;
13419 case OPC_CMP_EQ_PH:
13420 check_dsp(ctx);
13421 gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env);
13422 break;
13423 case OPC_CMP_LT_PH:
13424 check_dsp(ctx);
13425 gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env);
13426 break;
13427 case OPC_CMP_LE_PH:
13428 check_dsp(ctx);
13429 gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env);
13430 break;
13431 case OPC_PICK_QB:
13432 check_dsp(ctx);
13433 gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13434 break;
13435 case OPC_PICK_PH:
13436 check_dsp(ctx);
13437 gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13438 break;
13439 case OPC_PACKRL_PH:
13440 check_dsp(ctx);
13441 gen_helper_packrl_ph(cpu_gpr[ret], v1_t, v2_t);
13442 break;
13443 }
13444 break;
13445 #ifdef TARGET_MIPS64
13446 case OPC_CMPU_EQ_OB_DSP:
13447 switch (op2) {
13448 case OPC_CMP_EQ_PW:
13449 check_dsp(ctx);
13450 gen_helper_cmp_eq_pw(v1_t, v2_t, cpu_env);
13451 break;
13452 case OPC_CMP_LT_PW:
13453 check_dsp(ctx);
13454 gen_helper_cmp_lt_pw(v1_t, v2_t, cpu_env);
13455 break;
13456 case OPC_CMP_LE_PW:
13457 check_dsp(ctx);
13458 gen_helper_cmp_le_pw(v1_t, v2_t, cpu_env);
13459 break;
13460 case OPC_CMP_EQ_QH:
13461 check_dsp(ctx);
13462 gen_helper_cmp_eq_qh(v1_t, v2_t, cpu_env);
13463 break;
13464 case OPC_CMP_LT_QH:
13465 check_dsp(ctx);
13466 gen_helper_cmp_lt_qh(v1_t, v2_t, cpu_env);
13467 break;
13468 case OPC_CMP_LE_QH:
13469 check_dsp(ctx);
13470 gen_helper_cmp_le_qh(v1_t, v2_t, cpu_env);
13471 break;
13472 case OPC_CMPGDU_EQ_OB:
13473 check_dsp_r2(ctx);
13474 gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13475 break;
13476 case OPC_CMPGDU_LT_OB:
13477 check_dsp_r2(ctx);
13478 gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13479 break;
13480 case OPC_CMPGDU_LE_OB:
13481 check_dsp_r2(ctx);
13482 gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13483 break;
13484 case OPC_CMPGU_EQ_OB:
13485 check_dsp(ctx);
13486 gen_helper_cmpgu_eq_ob(cpu_gpr[ret], v1_t, v2_t);
13487 break;
13488 case OPC_CMPGU_LT_OB:
13489 check_dsp(ctx);
13490 gen_helper_cmpgu_lt_ob(cpu_gpr[ret], v1_t, v2_t);
13491 break;
13492 case OPC_CMPGU_LE_OB:
13493 check_dsp(ctx);
13494 gen_helper_cmpgu_le_ob(cpu_gpr[ret], v1_t, v2_t);
13495 break;
13496 case OPC_CMPU_EQ_OB:
13497 check_dsp(ctx);
13498 gen_helper_cmpu_eq_ob(v1_t, v2_t, cpu_env);
13499 break;
13500 case OPC_CMPU_LT_OB:
13501 check_dsp(ctx);
13502 gen_helper_cmpu_lt_ob(v1_t, v2_t, cpu_env);
13503 break;
13504 case OPC_CMPU_LE_OB:
13505 check_dsp(ctx);
13506 gen_helper_cmpu_le_ob(v1_t, v2_t, cpu_env);
13507 break;
13508 case OPC_PACKRL_PW:
13509 check_dsp(ctx);
13510 gen_helper_packrl_pw(cpu_gpr[ret], v1_t, v2_t);
13511 break;
13512 case OPC_PICK_OB:
13513 check_dsp(ctx);
13514 gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13515 break;
13516 case OPC_PICK_PW:
13517 check_dsp(ctx);
13518 gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13519 break;
13520 case OPC_PICK_QH:
13521 check_dsp(ctx);
13522 gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
13523 break;
13524 }
13525 break;
13526 #endif
13527 }
13528
13529 tcg_temp_free(t1);
13530 tcg_temp_free(v1_t);
13531 tcg_temp_free(v2_t);
13532 }
13533
13534 static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
13535 uint32_t op1, int rt, int rs, int sa)
13536 {
13537 TCGv t0;
13538
13539 check_dsp_r2(ctx);
13540
13541 if (rt == 0) {
13542 /* Treat as NOP. */
13543 return;
13544 }
13545
13546 t0 = tcg_temp_new();
13547 gen_load_gpr(t0, rs);
13548
13549 switch (op1) {
13550 case OPC_APPEND_DSP:
13551 switch (MASK_APPEND(ctx->opcode)) {
13552 case OPC_APPEND:
13553 if (sa != 0) {
13554 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa);
13555 }
13556 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
13557 break;
13558 case OPC_PREPEND:
13559 if (sa != 0) {
13560 tcg_gen_ext32u_tl(cpu_gpr[rt], cpu_gpr[rt]);
13561 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa);
13562 tcg_gen_shli_tl(t0, t0, 32 - sa);
13563 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
13564 }
13565 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
13566 break;
13567 case OPC_BALIGN:
13568 sa &= 3;
13569 if (sa != 0 && sa != 2) {
13570 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa);
13571 tcg_gen_ext32u_tl(t0, t0);
13572 tcg_gen_shri_tl(t0, t0, 8 * (4 - sa));
13573 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
13574 }
13575 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
13576 break;
13577 default: /* Invalid */
13578 MIPS_INVAL("MASK APPEND");
13579 gen_reserved_instruction(ctx);
13580 break;
13581 }
13582 break;
13583 #ifdef TARGET_MIPS64
13584 case OPC_DAPPEND_DSP:
13585 switch (MASK_DAPPEND(ctx->opcode)) {
13586 case OPC_DAPPEND:
13587 if (sa != 0) {
13588 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa);
13589 }
13590 break;
13591 case OPC_PREPENDD:
13592 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], 0x20 | sa);
13593 tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa));
13594 tcg_gen_or_tl(cpu_gpr[rt], t0, t0);
13595 break;
13596 case OPC_PREPENDW:
13597 if (sa != 0) {
13598 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa);
13599 tcg_gen_shli_tl(t0, t0, 64 - sa);
13600 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
13601 }
13602 break;
13603 case OPC_DBALIGN:
13604 sa &= 7;
13605 if (sa != 0 && sa != 2 && sa != 4) {
13606 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa);
13607 tcg_gen_shri_tl(t0, t0, 8 * (8 - sa));
13608 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
13609 }
13610 break;
13611 default: /* Invalid */
13612 MIPS_INVAL("MASK DAPPEND");
13613 gen_reserved_instruction(ctx);
13614 break;
13615 }
13616 break;
13617 #endif
13618 }
13619 tcg_temp_free(t0);
13620 }
13621
13622 static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
13623 int ret, int v1, int v2, int check_ret)
13624
13625 {
13626 TCGv t0;
13627 TCGv t1;
13628 TCGv v1_t;
13629 int16_t imm;
13630
13631 if ((ret == 0) && (check_ret == 1)) {
13632 /* Treat as NOP. */
13633 return;
13634 }
13635
13636 t0 = tcg_temp_new();
13637 t1 = tcg_temp_new();
13638 v1_t = tcg_temp_new();
13639
13640 gen_load_gpr(v1_t, v1);
13641
13642 switch (op1) {
13643 case OPC_EXTR_W_DSP:
13644 check_dsp(ctx);
13645 switch (op2) {
13646 case OPC_EXTR_W:
13647 tcg_gen_movi_tl(t0, v2);
13648 tcg_gen_movi_tl(t1, v1);
13649 gen_helper_extr_w(cpu_gpr[ret], t0, t1, cpu_env);
13650 break;
13651 case OPC_EXTR_R_W:
13652 tcg_gen_movi_tl(t0, v2);
13653 tcg_gen_movi_tl(t1, v1);
13654 gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
13655 break;
13656 case OPC_EXTR_RS_W:
13657 tcg_gen_movi_tl(t0, v2);
13658 tcg_gen_movi_tl(t1, v1);
13659 gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
13660 break;
13661 case OPC_EXTR_S_H:
13662 tcg_gen_movi_tl(t0, v2);
13663 tcg_gen_movi_tl(t1, v1);
13664 gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
13665 break;
13666 case OPC_EXTRV_S_H:
13667 tcg_gen_movi_tl(t0, v2);
13668 gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
13669 break;
13670 case OPC_EXTRV_W:
13671 tcg_gen_movi_tl(t0, v2);
13672 gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
13673 break;
13674 case OPC_EXTRV_R_W:
13675 tcg_gen_movi_tl(t0, v2);
13676 gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
13677 break;
13678 case OPC_EXTRV_RS_W:
13679 tcg_gen_movi_tl(t0, v2);
13680 gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
13681 break;
13682 case OPC_EXTP:
13683 tcg_gen_movi_tl(t0, v2);
13684 tcg_gen_movi_tl(t1, v1);
13685 gen_helper_extp(cpu_gpr[ret], t0, t1, cpu_env);
13686 break;
13687 case OPC_EXTPV:
13688 tcg_gen_movi_tl(t0, v2);
13689 gen_helper_extp(cpu_gpr[ret], t0, v1_t, cpu_env);
13690 break;
13691 case OPC_EXTPDP:
13692 tcg_gen_movi_tl(t0, v2);
13693 tcg_gen_movi_tl(t1, v1);
13694 gen_helper_extpdp(cpu_gpr[ret], t0, t1, cpu_env);
13695 break;
13696 case OPC_EXTPDPV:
13697 tcg_gen_movi_tl(t0, v2);
13698 gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
13699 break;
13700 case OPC_SHILO:
13701 imm = (ctx->opcode >> 20) & 0x3F;
13702 tcg_gen_movi_tl(t0, ret);
13703 tcg_gen_movi_tl(t1, imm);
13704 gen_helper_shilo(t0, t1, cpu_env);
13705 break;
13706 case OPC_SHILOV:
13707 tcg_gen_movi_tl(t0, ret);
13708 gen_helper_shilo(t0, v1_t, cpu_env);
13709 break;
13710 case OPC_MTHLIP:
13711 tcg_gen_movi_tl(t0, ret);
13712 gen_helper_mthlip(t0, v1_t, cpu_env);
13713 break;
13714 case OPC_WRDSP:
13715 imm = (ctx->opcode >> 11) & 0x3FF;
13716 tcg_gen_movi_tl(t0, imm);
13717 gen_helper_wrdsp(v1_t, t0, cpu_env);
13718 break;
13719 case OPC_RDDSP:
13720 imm = (ctx->opcode >> 16) & 0x03FF;
13721 tcg_gen_movi_tl(t0, imm);
13722 gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env);
13723 break;
13724 }
13725 break;
13726 #ifdef TARGET_MIPS64
13727 case OPC_DEXTR_W_DSP:
13728 check_dsp(ctx);
13729 switch (op2) {
13730 case OPC_DMTHLIP:
13731 tcg_gen_movi_tl(t0, ret);
13732 gen_helper_dmthlip(v1_t, t0, cpu_env);
13733 break;
13734 case OPC_DSHILO:
13735 {
13736 int shift = (ctx->opcode >> 19) & 0x7F;
13737 int ac = (ctx->opcode >> 11) & 0x03;
13738 tcg_gen_movi_tl(t0, shift);
13739 tcg_gen_movi_tl(t1, ac);
13740 gen_helper_dshilo(t0, t1, cpu_env);
13741 break;
13742 }
13743 case OPC_DSHILOV:
13744 {
13745 int ac = (ctx->opcode >> 11) & 0x03;
13746 tcg_gen_movi_tl(t0, ac);
13747 gen_helper_dshilo(v1_t, t0, cpu_env);
13748 break;
13749 }
13750 case OPC_DEXTP:
13751 tcg_gen_movi_tl(t0, v2);
13752 tcg_gen_movi_tl(t1, v1);
13753
13754 gen_helper_dextp(cpu_gpr[ret], t0, t1, cpu_env);
13755 break;
13756 case OPC_DEXTPV:
13757 tcg_gen_movi_tl(t0, v2);
13758 gen_helper_dextp(cpu_gpr[ret], t0, v1_t, cpu_env);
13759 break;
13760 case OPC_DEXTPDP:
13761 tcg_gen_movi_tl(t0, v2);
13762 tcg_gen_movi_tl(t1, v1);
13763 gen_helper_dextpdp(cpu_gpr[ret], t0, t1, cpu_env);
13764 break;
13765 case OPC_DEXTPDPV:
13766 tcg_gen_movi_tl(t0, v2);
13767 gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
13768 break;
13769 case OPC_DEXTR_L:
13770 tcg_gen_movi_tl(t0, v2);
13771 tcg_gen_movi_tl(t1, v1);
13772 gen_helper_dextr_l(cpu_gpr[ret], t0, t1, cpu_env);
13773 break;
13774 case OPC_DEXTR_R_L:
13775 tcg_gen_movi_tl(t0, v2);
13776 tcg_gen_movi_tl(t1, v1);
13777 gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, cpu_env);
13778 break;
13779 case OPC_DEXTR_RS_L:
13780 tcg_gen_movi_tl(t0, v2);
13781 tcg_gen_movi_tl(t1, v1);
13782 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, cpu_env);
13783 break;
13784 case OPC_DEXTR_W:
13785 tcg_gen_movi_tl(t0, v2);
13786 tcg_gen_movi_tl(t1, v1);
13787 gen_helper_dextr_w(cpu_gpr[ret], t0, t1, cpu_env);
13788 break;
13789 case OPC_DEXTR_R_W:
13790 tcg_gen_movi_tl(t0, v2);
13791 tcg_gen_movi_tl(t1, v1);
13792 gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
13793 break;
13794 case OPC_DEXTR_RS_W:
13795 tcg_gen_movi_tl(t0, v2);
13796 tcg_gen_movi_tl(t1, v1);
13797 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
13798 break;
13799 case OPC_DEXTR_S_H:
13800 tcg_gen_movi_tl(t0, v2);
13801 tcg_gen_movi_tl(t1, v1);
13802 gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
13803 break;
13804 case OPC_DEXTRV_S_H:
13805 tcg_gen_movi_tl(t0, v2);
13806 gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
13807 break;
13808 case OPC_DEXTRV_L:
13809 tcg_gen_movi_tl(t0, v2);
13810 gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, cpu_env);
13811 break;
13812 case OPC_DEXTRV_R_L:
13813 tcg_gen_movi_tl(t0, v2);
13814 gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, cpu_env);
13815 break;
13816 case OPC_DEXTRV_RS_L:
13817 tcg_gen_movi_tl(t0, v2);
13818 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, cpu_env);
13819 break;
13820 case OPC_DEXTRV_W:
13821 tcg_gen_movi_tl(t0, v2);
13822 gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
13823 break;
13824 case OPC_DEXTRV_R_W:
13825 tcg_gen_movi_tl(t0, v2);
13826 gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
13827 break;
13828 case OPC_DEXTRV_RS_W:
13829 tcg_gen_movi_tl(t0, v2);
13830 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
13831 break;
13832 }
13833 break;
13834 #endif
13835 }
13836
13837 tcg_temp_free(t0);
13838 tcg_temp_free(t1);
13839 tcg_temp_free(v1_t);
13840 }
13841
13842 /* End MIPSDSP functions. */
13843
13844 static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
13845 {
13846 int rs, rt, rd, sa;
13847 uint32_t op1, op2;
13848
13849 rs = (ctx->opcode >> 21) & 0x1f;
13850 rt = (ctx->opcode >> 16) & 0x1f;
13851 rd = (ctx->opcode >> 11) & 0x1f;
13852 sa = (ctx->opcode >> 6) & 0x1f;
13853
13854 op1 = MASK_SPECIAL(ctx->opcode);
13855 switch (op1) {
13856 case OPC_MULT:
13857 case OPC_MULTU:
13858 case OPC_DIV:
13859 case OPC_DIVU:
13860 op2 = MASK_R6_MULDIV(ctx->opcode);
13861 switch (op2) {
13862 case R6_OPC_MUL:
13863 case R6_OPC_MUH:
13864 case R6_OPC_MULU:
13865 case R6_OPC_MUHU:
13866 case R6_OPC_DIV:
13867 case R6_OPC_MOD:
13868 case R6_OPC_DIVU:
13869 case R6_OPC_MODU:
13870 gen_r6_muldiv(ctx, op2, rd, rs, rt);
13871 break;
13872 default:
13873 MIPS_INVAL("special_r6 muldiv");
13874 gen_reserved_instruction(ctx);
13875 break;
13876 }
13877 break;
13878 case OPC_SELEQZ:
13879 case OPC_SELNEZ:
13880 gen_cond_move(ctx, op1, rd, rs, rt);
13881 break;
13882 case R6_OPC_CLO:
13883 case R6_OPC_CLZ:
13884 if (rt == 0 && sa == 1) {
13885 /*
13886 * Major opcode and function field is shared with preR6 MFHI/MTHI.
13887 * We need additionally to check other fields.
13888 */
13889 gen_cl(ctx, op1, rd, rs);
13890 } else {
13891 gen_reserved_instruction(ctx);
13892 }
13893 break;
13894 case R6_OPC_SDBBP:
13895 if (is_uhi(extract32(ctx->opcode, 6, 20))) {
13896 gen_helper_do_semihosting(cpu_env);
13897 } else {
13898 if (ctx->hflags & MIPS_HFLAG_SBRI) {
13899 gen_reserved_instruction(ctx);
13900 } else {
13901 generate_exception_end(ctx, EXCP_DBp);
13902 }
13903 }
13904 break;
13905 #if defined(TARGET_MIPS64)
13906 case R6_OPC_DCLO:
13907 case R6_OPC_DCLZ:
13908 if (rt == 0 && sa == 1) {
13909 /*
13910 * Major opcode and function field is shared with preR6 MFHI/MTHI.
13911 * We need additionally to check other fields.
13912 */
13913 check_mips_64(ctx);
13914 gen_cl(ctx, op1, rd, rs);
13915 } else {
13916 gen_reserved_instruction(ctx);
13917 }
13918 break;
13919 case OPC_DMULT:
13920 case OPC_DMULTU:
13921 case OPC_DDIV:
13922 case OPC_DDIVU:
13923
13924 op2 = MASK_R6_MULDIV(ctx->opcode);
13925 switch (op2) {
13926 case R6_OPC_DMUL:
13927 case R6_OPC_DMUH:
13928 case R6_OPC_DMULU:
13929 case R6_OPC_DMUHU:
13930 case R6_OPC_DDIV:
13931 case R6_OPC_DMOD:
13932 case R6_OPC_DDIVU:
13933 case R6_OPC_DMODU:
13934 check_mips_64(ctx);
13935 gen_r6_muldiv(ctx, op2, rd, rs, rt);
13936 break;
13937 default:
13938 MIPS_INVAL("special_r6 muldiv");
13939 gen_reserved_instruction(ctx);
13940 break;
13941 }
13942 break;
13943 #endif
13944 default: /* Invalid */
13945 MIPS_INVAL("special_r6");
13946 gen_reserved_instruction(ctx);
13947 break;
13948 }
13949 }
13950
13951 static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx)
13952 {
13953 int rs = extract32(ctx->opcode, 21, 5);
13954 int rt = extract32(ctx->opcode, 16, 5);
13955 int rd = extract32(ctx->opcode, 11, 5);
13956 uint32_t op1 = MASK_SPECIAL(ctx->opcode);
13957
13958 switch (op1) {
13959 case OPC_MOVN: /* Conditional move */
13960 case OPC_MOVZ:
13961 gen_cond_move(ctx, op1, rd, rs, rt);
13962 break;
13963 case OPC_MFHI: /* Move from HI/LO */
13964 case OPC_MFLO:
13965 gen_HILO(ctx, op1, 0, rd);
13966 break;
13967 case OPC_MTHI:
13968 case OPC_MTLO: /* Move to HI/LO */
13969 gen_HILO(ctx, op1, 0, rs);
13970 break;
13971 case OPC_MULT:
13972 case OPC_MULTU:
13973 gen_mul_txx9(ctx, op1, rd, rs, rt);
13974 break;
13975 case OPC_DIV:
13976 case OPC_DIVU:
13977 gen_muldiv(ctx, op1, 0, rs, rt);
13978 break;
13979 #if defined(TARGET_MIPS64)
13980 case OPC_DMULT:
13981 case OPC_DMULTU:
13982 case OPC_DDIV:
13983 case OPC_DDIVU:
13984 check_insn_opc_user_only(ctx, INSN_R5900);
13985 gen_muldiv(ctx, op1, 0, rs, rt);
13986 break;
13987 #endif
13988 case OPC_JR:
13989 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4);
13990 break;
13991 default: /* Invalid */
13992 MIPS_INVAL("special_tx79");
13993 gen_reserved_instruction(ctx);
13994 break;
13995 }
13996 }
13997
13998 static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
13999 {
14000 int rs, rt, rd;
14001 uint32_t op1;
14002
14003 rs = (ctx->opcode >> 21) & 0x1f;
14004 rt = (ctx->opcode >> 16) & 0x1f;
14005 rd = (ctx->opcode >> 11) & 0x1f;
14006
14007 op1 = MASK_SPECIAL(ctx->opcode);
14008 switch (op1) {
14009 case OPC_MOVN: /* Conditional move */
14010 case OPC_MOVZ:
14011 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 |
14012 INSN_LOONGSON2E | INSN_LOONGSON2F);
14013 gen_cond_move(ctx, op1, rd, rs, rt);
14014 break;
14015 case OPC_MFHI: /* Move from HI/LO */
14016 case OPC_MFLO:
14017 gen_HILO(ctx, op1, rs & 3, rd);
14018 break;
14019 case OPC_MTHI:
14020 case OPC_MTLO: /* Move to HI/LO */
14021 gen_HILO(ctx, op1, rd & 3, rs);
14022 break;
14023 case OPC_MOVCI:
14024 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
14025 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
14026 check_cp1_enabled(ctx);
14027 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
14028 (ctx->opcode >> 16) & 1);
14029 } else {
14030 generate_exception_err(ctx, EXCP_CpU, 1);
14031 }
14032 break;
14033 case OPC_MULT:
14034 case OPC_MULTU:
14035 gen_muldiv(ctx, op1, rd & 3, rs, rt);
14036 break;
14037 case OPC_DIV:
14038 case OPC_DIVU:
14039 gen_muldiv(ctx, op1, 0, rs, rt);
14040 break;
14041 #if defined(TARGET_MIPS64)
14042 case OPC_DMULT:
14043 case OPC_DMULTU:
14044 case OPC_DDIV:
14045 case OPC_DDIVU:
14046 check_insn(ctx, ISA_MIPS3);
14047 check_mips_64(ctx);
14048 gen_muldiv(ctx, op1, 0, rs, rt);
14049 break;
14050 #endif
14051 case OPC_JR:
14052 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4);
14053 break;
14054 case OPC_SPIM:
14055 #ifdef MIPS_STRICT_STANDARD
14056 MIPS_INVAL("SPIM");
14057 gen_reserved_instruction(ctx);
14058 #else
14059 /* Implemented as RI exception for now. */
14060 MIPS_INVAL("spim (unofficial)");
14061 gen_reserved_instruction(ctx);
14062 #endif
14063 break;
14064 default: /* Invalid */
14065 MIPS_INVAL("special_legacy");
14066 gen_reserved_instruction(ctx);
14067 break;
14068 }
14069 }
14070
14071 static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
14072 {
14073 int rs, rt, rd, sa;
14074 uint32_t op1;
14075
14076 rs = (ctx->opcode >> 21) & 0x1f;
14077 rt = (ctx->opcode >> 16) & 0x1f;
14078 rd = (ctx->opcode >> 11) & 0x1f;
14079 sa = (ctx->opcode >> 6) & 0x1f;
14080
14081 op1 = MASK_SPECIAL(ctx->opcode);
14082 switch (op1) {
14083 case OPC_SLL: /* Shift with immediate */
14084 if (sa == 5 && rd == 0 &&
14085 rs == 0 && rt == 0) { /* PAUSE */
14086 if ((ctx->insn_flags & ISA_MIPS_R6) &&
14087 (ctx->hflags & MIPS_HFLAG_BMASK)) {
14088 gen_reserved_instruction(ctx);
14089 break;
14090 }
14091 }
14092 /* Fallthrough */
14093 case OPC_SRA:
14094 gen_shift_imm(ctx, op1, rd, rt, sa);
14095 break;
14096 case OPC_SRL:
14097 switch ((ctx->opcode >> 21) & 0x1f) {
14098 case 1:
14099 /* rotr is decoded as srl on non-R2 CPUs */
14100 if (ctx->insn_flags & ISA_MIPS_R2) {
14101 op1 = OPC_ROTR;
14102 }
14103 /* Fallthrough */
14104 case 0:
14105 gen_shift_imm(ctx, op1, rd, rt, sa);
14106 break;
14107 default:
14108 gen_reserved_instruction(ctx);
14109 break;
14110 }
14111 break;
14112 case OPC_ADD:
14113 case OPC_ADDU:
14114 case OPC_SUB:
14115 case OPC_SUBU:
14116 gen_arith(ctx, op1, rd, rs, rt);
14117 break;
14118 case OPC_SLLV: /* Shifts */
14119 case OPC_SRAV:
14120 gen_shift(ctx, op1, rd, rs, rt);
14121 break;
14122 case OPC_SRLV:
14123 switch ((ctx->opcode >> 6) & 0x1f) {
14124 case 1:
14125 /* rotrv is decoded as srlv on non-R2 CPUs */
14126 if (ctx->insn_flags & ISA_MIPS_R2) {
14127 op1 = OPC_ROTRV;
14128 }
14129 /* Fallthrough */
14130 case 0:
14131 gen_shift(ctx, op1, rd, rs, rt);
14132 break;
14133 default:
14134 gen_reserved_instruction(ctx);
14135 break;
14136 }
14137 break;
14138 case OPC_SLT: /* Set on less than */
14139 case OPC_SLTU:
14140 gen_slt(ctx, op1, rd, rs, rt);
14141 break;
14142 case OPC_AND: /* Logic*/
14143 case OPC_OR:
14144 case OPC_NOR:
14145 case OPC_XOR:
14146 gen_logic(ctx, op1, rd, rs, rt);
14147 break;
14148 case OPC_JALR:
14149 gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
14150 break;
14151 case OPC_TGE: /* Traps */
14152 case OPC_TGEU:
14153 case OPC_TLT:
14154 case OPC_TLTU:
14155 case OPC_TEQ:
14156 case OPC_TNE:
14157 check_insn(ctx, ISA_MIPS2);
14158 gen_trap(ctx, op1, rs, rt, -1);
14159 break;
14160 case OPC_PMON:
14161 /* Pmon entry point, also R4010 selsl */
14162 #ifdef MIPS_STRICT_STANDARD
14163 MIPS_INVAL("PMON / selsl");
14164 gen_reserved_instruction(ctx);
14165 #else
14166 gen_helper_pmon(cpu_env, tcg_constant_i32(sa));
14167 #endif
14168 break;
14169 case OPC_SYSCALL:
14170 generate_exception_end(ctx, EXCP_SYSCALL);
14171 break;
14172 case OPC_BREAK:
14173 generate_exception_break(ctx, extract32(ctx->opcode, 6, 20));
14174 break;
14175 case OPC_SYNC:
14176 check_insn(ctx, ISA_MIPS2);
14177 gen_sync(extract32(ctx->opcode, 6, 5));
14178 break;
14179
14180 #if defined(TARGET_MIPS64)
14181 /* MIPS64 specific opcodes */
14182 case OPC_DSLL:
14183 case OPC_DSRA:
14184 case OPC_DSLL32:
14185 case OPC_DSRA32:
14186 check_insn(ctx, ISA_MIPS3);
14187 check_mips_64(ctx);
14188 gen_shift_imm(ctx, op1, rd, rt, sa);
14189 break;
14190 case OPC_DSRL:
14191 switch ((ctx->opcode >> 21) & 0x1f) {
14192 case 1:
14193 /* drotr is decoded as dsrl on non-R2 CPUs */
14194 if (ctx->insn_flags & ISA_MIPS_R2) {
14195 op1 = OPC_DROTR;
14196 }
14197 /* Fallthrough */
14198 case 0:
14199 check_insn(ctx, ISA_MIPS3);
14200 check_mips_64(ctx);
14201 gen_shift_imm(ctx, op1, rd, rt, sa);
14202 break;
14203 default:
14204 gen_reserved_instruction(ctx);
14205 break;
14206 }
14207 break;
14208 case OPC_DSRL32:
14209 switch ((ctx->opcode >> 21) & 0x1f) {
14210 case 1:
14211 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
14212 if (ctx->insn_flags & ISA_MIPS_R2) {
14213 op1 = OPC_DROTR32;
14214 }
14215 /* Fallthrough */
14216 case 0:
14217 check_insn(ctx, ISA_MIPS3);
14218 check_mips_64(ctx);
14219 gen_shift_imm(ctx, op1, rd, rt, sa);
14220 break;
14221 default:
14222 gen_reserved_instruction(ctx);
14223 break;
14224 }
14225 break;
14226 case OPC_DADD:
14227 case OPC_DADDU:
14228 case OPC_DSUB:
14229 case OPC_DSUBU:
14230 check_insn(ctx, ISA_MIPS3);
14231 check_mips_64(ctx);
14232 gen_arith(ctx, op1, rd, rs, rt);
14233 break;
14234 case OPC_DSLLV:
14235 case OPC_DSRAV:
14236 check_insn(ctx, ISA_MIPS3);
14237 check_mips_64(ctx);
14238 gen_shift(ctx, op1, rd, rs, rt);
14239 break;
14240 case OPC_DSRLV:
14241 switch ((ctx->opcode >> 6) & 0x1f) {
14242 case 1:
14243 /* drotrv is decoded as dsrlv on non-R2 CPUs */
14244 if (ctx->insn_flags & ISA_MIPS_R2) {
14245 op1 = OPC_DROTRV;
14246 }
14247 /* Fallthrough */
14248 case 0:
14249 check_insn(ctx, ISA_MIPS3);
14250 check_mips_64(ctx);
14251 gen_shift(ctx, op1, rd, rs, rt);
14252 break;
14253 default:
14254 gen_reserved_instruction(ctx);
14255 break;
14256 }
14257 break;
14258 #endif
14259 default:
14260 if (ctx->insn_flags & ISA_MIPS_R6) {
14261 decode_opc_special_r6(env, ctx);
14262 } else if (ctx->insn_flags & INSN_R5900) {
14263 decode_opc_special_tx79(env, ctx);
14264 } else {
14265 decode_opc_special_legacy(env, ctx);
14266 }
14267 }
14268 }
14269
14270
14271 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
14272 {
14273 int rs, rt, rd;
14274 uint32_t op1;
14275
14276 rs = (ctx->opcode >> 21) & 0x1f;
14277 rt = (ctx->opcode >> 16) & 0x1f;
14278 rd = (ctx->opcode >> 11) & 0x1f;
14279
14280 op1 = MASK_SPECIAL2(ctx->opcode);
14281 switch (op1) {
14282 case OPC_MADD: /* Multiply and add/sub */
14283 case OPC_MADDU:
14284 case OPC_MSUB:
14285 case OPC_MSUBU:
14286 check_insn(ctx, ISA_MIPS_R1);
14287 gen_muldiv(ctx, op1, rd & 3, rs, rt);
14288 break;
14289 case OPC_MUL:
14290 gen_arith(ctx, op1, rd, rs, rt);
14291 break;
14292 case OPC_DIV_G_2F:
14293 case OPC_DIVU_G_2F:
14294 case OPC_MULT_G_2F:
14295 case OPC_MULTU_G_2F:
14296 case OPC_MOD_G_2F:
14297 case OPC_MODU_G_2F:
14298 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
14299 gen_loongson_integer(ctx, op1, rd, rs, rt);
14300 break;
14301 case OPC_CLO:
14302 case OPC_CLZ:
14303 check_insn(ctx, ISA_MIPS_R1);
14304 gen_cl(ctx, op1, rd, rs);
14305 break;
14306 case OPC_SDBBP:
14307 if (is_uhi(extract32(ctx->opcode, 6, 20))) {
14308 gen_helper_do_semihosting(cpu_env);
14309 } else {
14310 /*
14311 * XXX: not clear which exception should be raised
14312 * when in debug mode...
14313 */
14314 check_insn(ctx, ISA_MIPS_R1);
14315 generate_exception_end(ctx, EXCP_DBp);
14316 }
14317 break;
14318 #if defined(TARGET_MIPS64)
14319 case OPC_DCLO:
14320 case OPC_DCLZ:
14321 check_insn(ctx, ISA_MIPS_R1);
14322 check_mips_64(ctx);
14323 gen_cl(ctx, op1, rd, rs);
14324 break;
14325 case OPC_DMULT_G_2F:
14326 case OPC_DMULTU_G_2F:
14327 case OPC_DDIV_G_2F:
14328 case OPC_DDIVU_G_2F:
14329 case OPC_DMOD_G_2F:
14330 case OPC_DMODU_G_2F:
14331 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
14332 gen_loongson_integer(ctx, op1, rd, rs, rt);
14333 break;
14334 #endif
14335 default: /* Invalid */
14336 MIPS_INVAL("special2_legacy");
14337 gen_reserved_instruction(ctx);
14338 break;
14339 }
14340 }
14341
14342 static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
14343 {
14344 int rs, rt, rd, sa;
14345 uint32_t op1, op2;
14346 int16_t imm;
14347
14348 rs = (ctx->opcode >> 21) & 0x1f;
14349 rt = (ctx->opcode >> 16) & 0x1f;
14350 rd = (ctx->opcode >> 11) & 0x1f;
14351 sa = (ctx->opcode >> 6) & 0x1f;
14352 imm = (int16_t)ctx->opcode >> 7;
14353
14354 op1 = MASK_SPECIAL3(ctx->opcode);
14355 switch (op1) {
14356 case R6_OPC_PREF:
14357 if (rt >= 24) {
14358 /* hint codes 24-31 are reserved and signal RI */
14359 gen_reserved_instruction(ctx);
14360 }
14361 /* Treat as NOP. */
14362 break;
14363 case R6_OPC_CACHE:
14364 check_cp0_enabled(ctx);
14365 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
14366 gen_cache_operation(ctx, rt, rs, imm);
14367 }
14368 break;
14369 case R6_OPC_SC:
14370 gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
14371 break;
14372 case R6_OPC_LL:
14373 gen_ld(ctx, op1, rt, rs, imm);
14374 break;
14375 case OPC_BSHFL:
14376 {
14377 if (rd == 0) {
14378 /* Treat as NOP. */
14379 break;
14380 }
14381 op2 = MASK_BSHFL(ctx->opcode);
14382 switch (op2) {
14383 case OPC_ALIGN:
14384 case OPC_ALIGN_1:
14385 case OPC_ALIGN_2:
14386 case OPC_ALIGN_3:
14387 gen_align(ctx, 32, rd, rs, rt, sa & 3);
14388 break;
14389 case OPC_BITSWAP:
14390 gen_bitswap(ctx, op2, rd, rt);
14391 break;
14392 }
14393 }
14394 break;
14395 #ifndef CONFIG_USER_ONLY
14396 case OPC_GINV:
14397 if (unlikely(ctx->gi <= 1)) {
14398 gen_reserved_instruction(ctx);
14399 }
14400 check_cp0_enabled(ctx);
14401 switch ((ctx->opcode >> 6) & 3) {
14402 case 0: /* GINVI */
14403 /* Treat as NOP. */
14404 break;
14405 case 2: /* GINVT */
14406 gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2));
14407 break;
14408 default:
14409 gen_reserved_instruction(ctx);
14410 break;
14411 }
14412 break;
14413 #endif
14414 #if defined(TARGET_MIPS64)
14415 case R6_OPC_SCD:
14416 gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false);
14417 break;
14418 case R6_OPC_LLD:
14419 gen_ld(ctx, op1, rt, rs, imm);
14420 break;
14421 case OPC_DBSHFL:
14422 check_mips_64(ctx);
14423 {
14424 if (rd == 0) {
14425 /* Treat as NOP. */
14426 break;
14427 }
14428 op2 = MASK_DBSHFL(ctx->opcode);
14429 switch (op2) {
14430 case OPC_DALIGN:
14431 case OPC_DALIGN_1:
14432 case OPC_DALIGN_2:
14433 case OPC_DALIGN_3:
14434 case OPC_DALIGN_4:
14435 case OPC_DALIGN_5:
14436 case OPC_DALIGN_6:
14437 case OPC_DALIGN_7:
14438 gen_align(ctx, 64, rd, rs, rt, sa & 7);
14439 break;
14440 case OPC_DBITSWAP:
14441 gen_bitswap(ctx, op2, rd, rt);
14442 break;
14443 }
14444
14445 }
14446 break;
14447 #endif
14448 default: /* Invalid */
14449 MIPS_INVAL("special3_r6");
14450 gen_reserved_instruction(ctx);
14451 break;
14452 }
14453 }
14454
14455 static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
14456 {
14457 int rs, rt, rd;
14458 uint32_t op1, op2;
14459
14460 rs = (ctx->opcode >> 21) & 0x1f;
14461 rt = (ctx->opcode >> 16) & 0x1f;
14462 rd = (ctx->opcode >> 11) & 0x1f;
14463
14464 op1 = MASK_SPECIAL3(ctx->opcode);
14465 switch (op1) {
14466 case OPC_DIV_G_2E:
14467 case OPC_DIVU_G_2E:
14468 case OPC_MOD_G_2E:
14469 case OPC_MODU_G_2E:
14470 case OPC_MULT_G_2E:
14471 case OPC_MULTU_G_2E:
14472 /*
14473 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
14474 * the same mask and op1.
14475 */
14476 if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) {
14477 op2 = MASK_ADDUH_QB(ctx->opcode);
14478 switch (op2) {
14479 case OPC_ADDUH_QB:
14480 case OPC_ADDUH_R_QB:
14481 case OPC_ADDQH_PH:
14482 case OPC_ADDQH_R_PH:
14483 case OPC_ADDQH_W:
14484 case OPC_ADDQH_R_W:
14485 case OPC_SUBUH_QB:
14486 case OPC_SUBUH_R_QB:
14487 case OPC_SUBQH_PH:
14488 case OPC_SUBQH_R_PH:
14489 case OPC_SUBQH_W:
14490 case OPC_SUBQH_R_W:
14491 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
14492 break;
14493 case OPC_MUL_PH:
14494 case OPC_MUL_S_PH:
14495 case OPC_MULQ_S_W:
14496 case OPC_MULQ_RS_W:
14497 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
14498 break;
14499 default:
14500 MIPS_INVAL("MASK ADDUH.QB");
14501 gen_reserved_instruction(ctx);
14502 break;
14503 }
14504 } else if (ctx->insn_flags & INSN_LOONGSON2E) {
14505 gen_loongson_integer(ctx, op1, rd, rs, rt);
14506 } else {
14507 gen_reserved_instruction(ctx);
14508 }
14509 break;
14510 case OPC_LX_DSP:
14511 op2 = MASK_LX(ctx->opcode);
14512 switch (op2) {
14513 #if defined(TARGET_MIPS64)
14514 case OPC_LDX:
14515 #endif
14516 case OPC_LBUX:
14517 case OPC_LHX:
14518 case OPC_LWX:
14519 gen_mipsdsp_ld(ctx, op2, rd, rs, rt);
14520 break;
14521 default: /* Invalid */
14522 MIPS_INVAL("MASK LX");
14523 gen_reserved_instruction(ctx);
14524 break;
14525 }
14526 break;
14527 case OPC_ABSQ_S_PH_DSP:
14528 op2 = MASK_ABSQ_S_PH(ctx->opcode);
14529 switch (op2) {
14530 case OPC_ABSQ_S_QB:
14531 case OPC_ABSQ_S_PH:
14532 case OPC_ABSQ_S_W:
14533 case OPC_PRECEQ_W_PHL:
14534 case OPC_PRECEQ_W_PHR:
14535 case OPC_PRECEQU_PH_QBL:
14536 case OPC_PRECEQU_PH_QBR:
14537 case OPC_PRECEQU_PH_QBLA:
14538 case OPC_PRECEQU_PH_QBRA:
14539 case OPC_PRECEU_PH_QBL:
14540 case OPC_PRECEU_PH_QBR:
14541 case OPC_PRECEU_PH_QBLA:
14542 case OPC_PRECEU_PH_QBRA:
14543 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
14544 break;
14545 case OPC_BITREV:
14546 case OPC_REPL_QB:
14547 case OPC_REPLV_QB:
14548 case OPC_REPL_PH:
14549 case OPC_REPLV_PH:
14550 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt);
14551 break;
14552 default:
14553 MIPS_INVAL("MASK ABSQ_S.PH");
14554 gen_reserved_instruction(ctx);
14555 break;
14556 }
14557 break;
14558 case OPC_ADDU_QB_DSP:
14559 op2 = MASK_ADDU_QB(ctx->opcode);
14560 switch (op2) {
14561 case OPC_ADDQ_PH:
14562 case OPC_ADDQ_S_PH:
14563 case OPC_ADDQ_S_W:
14564 case OPC_ADDU_QB:
14565 case OPC_ADDU_S_QB:
14566 case OPC_ADDU_PH:
14567 case OPC_ADDU_S_PH:
14568 case OPC_SUBQ_PH:
14569 case OPC_SUBQ_S_PH:
14570 case OPC_SUBQ_S_W:
14571 case OPC_SUBU_QB:
14572 case OPC_SUBU_S_QB:
14573 case OPC_SUBU_PH:
14574 case OPC_SUBU_S_PH:
14575 case OPC_ADDSC:
14576 case OPC_ADDWC:
14577 case OPC_MODSUB:
14578 case OPC_RADDU_W_QB:
14579 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
14580 break;
14581 case OPC_MULEU_S_PH_QBL:
14582 case OPC_MULEU_S_PH_QBR:
14583 case OPC_MULQ_RS_PH:
14584 case OPC_MULEQ_S_W_PHL:
14585 case OPC_MULEQ_S_W_PHR:
14586 case OPC_MULQ_S_PH:
14587 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
14588 break;
14589 default: /* Invalid */
14590 MIPS_INVAL("MASK ADDU.QB");
14591 gen_reserved_instruction(ctx);
14592 break;
14593
14594 }
14595 break;
14596 case OPC_CMPU_EQ_QB_DSP:
14597 op2 = MASK_CMPU_EQ_QB(ctx->opcode);
14598 switch (op2) {
14599 case OPC_PRECR_SRA_PH_W:
14600 case OPC_PRECR_SRA_R_PH_W:
14601 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd);
14602 break;
14603 case OPC_PRECR_QB_PH:
14604 case OPC_PRECRQ_QB_PH:
14605 case OPC_PRECRQ_PH_W:
14606 case OPC_PRECRQ_RS_PH_W:
14607 case OPC_PRECRQU_S_QB_PH:
14608 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
14609 break;
14610 case OPC_CMPU_EQ_QB:
14611 case OPC_CMPU_LT_QB:
14612 case OPC_CMPU_LE_QB:
14613 case OPC_CMP_EQ_PH:
14614 case OPC_CMP_LT_PH:
14615 case OPC_CMP_LE_PH:
14616 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0);
14617 break;
14618 case OPC_CMPGU_EQ_QB:
14619 case OPC_CMPGU_LT_QB:
14620 case OPC_CMPGU_LE_QB:
14621 case OPC_CMPGDU_EQ_QB:
14622 case OPC_CMPGDU_LT_QB:
14623 case OPC_CMPGDU_LE_QB:
14624 case OPC_PICK_QB:
14625 case OPC_PICK_PH:
14626 case OPC_PACKRL_PH:
14627 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1);
14628 break;
14629 default: /* Invalid */
14630 MIPS_INVAL("MASK CMPU.EQ.QB");
14631 gen_reserved_instruction(ctx);
14632 break;
14633 }
14634 break;
14635 case OPC_SHLL_QB_DSP:
14636 gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
14637 break;
14638 case OPC_DPA_W_PH_DSP:
14639 op2 = MASK_DPA_W_PH(ctx->opcode);
14640 switch (op2) {
14641 case OPC_DPAU_H_QBL:
14642 case OPC_DPAU_H_QBR:
14643 case OPC_DPSU_H_QBL:
14644 case OPC_DPSU_H_QBR:
14645 case OPC_DPA_W_PH:
14646 case OPC_DPAX_W_PH:
14647 case OPC_DPAQ_S_W_PH:
14648 case OPC_DPAQX_S_W_PH:
14649 case OPC_DPAQX_SA_W_PH:
14650 case OPC_DPS_W_PH:
14651 case OPC_DPSX_W_PH:
14652 case OPC_DPSQ_S_W_PH:
14653 case OPC_DPSQX_S_W_PH:
14654 case OPC_DPSQX_SA_W_PH:
14655 case OPC_MULSAQ_S_W_PH:
14656 case OPC_DPAQ_SA_L_W:
14657 case OPC_DPSQ_SA_L_W:
14658 case OPC_MAQ_S_W_PHL:
14659 case OPC_MAQ_S_W_PHR:
14660 case OPC_MAQ_SA_W_PHL:
14661 case OPC_MAQ_SA_W_PHR:
14662 case OPC_MULSA_W_PH:
14663 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
14664 break;
14665 default: /* Invalid */
14666 MIPS_INVAL("MASK DPAW.PH");
14667 gen_reserved_instruction(ctx);
14668 break;
14669 }
14670 break;
14671 case OPC_INSV_DSP:
14672 op2 = MASK_INSV(ctx->opcode);
14673 switch (op2) {
14674 case OPC_INSV:
14675 check_dsp(ctx);
14676 {
14677 TCGv t0, t1;
14678
14679 if (rt == 0) {
14680 break;
14681 }
14682
14683 t0 = tcg_temp_new();
14684 t1 = tcg_temp_new();
14685
14686 gen_load_gpr(t0, rt);
14687 gen_load_gpr(t1, rs);
14688
14689 gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0);
14690
14691 tcg_temp_free(t0);
14692 tcg_temp_free(t1);
14693 break;
14694 }
14695 default: /* Invalid */
14696 MIPS_INVAL("MASK INSV");
14697 gen_reserved_instruction(ctx);
14698 break;
14699 }
14700 break;
14701 case OPC_APPEND_DSP:
14702 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd);
14703 break;
14704 case OPC_EXTR_W_DSP:
14705 op2 = MASK_EXTR_W(ctx->opcode);
14706 switch (op2) {
14707 case OPC_EXTR_W:
14708 case OPC_EXTR_R_W:
14709 case OPC_EXTR_RS_W:
14710 case OPC_EXTR_S_H:
14711 case OPC_EXTRV_S_H:
14712 case OPC_EXTRV_W:
14713 case OPC_EXTRV_R_W:
14714 case OPC_EXTRV_RS_W:
14715 case OPC_EXTP:
14716 case OPC_EXTPV:
14717 case OPC_EXTPDP:
14718 case OPC_EXTPDPV:
14719 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1);
14720 break;
14721 case OPC_RDDSP:
14722 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 1);
14723 break;
14724 case OPC_SHILO:
14725 case OPC_SHILOV:
14726 case OPC_MTHLIP:
14727 case OPC_WRDSP:
14728 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0);
14729 break;
14730 default: /* Invalid */
14731 MIPS_INVAL("MASK EXTR.W");
14732 gen_reserved_instruction(ctx);
14733 break;
14734 }
14735 break;
14736 #if defined(TARGET_MIPS64)
14737 case OPC_DDIV_G_2E:
14738 case OPC_DDIVU_G_2E:
14739 case OPC_DMULT_G_2E:
14740 case OPC_DMULTU_G_2E:
14741 case OPC_DMOD_G_2E:
14742 case OPC_DMODU_G_2E:
14743 check_insn(ctx, INSN_LOONGSON2E);
14744 gen_loongson_integer(ctx, op1, rd, rs, rt);
14745 break;
14746 case OPC_ABSQ_S_QH_DSP:
14747 op2 = MASK_ABSQ_S_QH(ctx->opcode);
14748 switch (op2) {
14749 case OPC_PRECEQ_L_PWL:
14750 case OPC_PRECEQ_L_PWR:
14751 case OPC_PRECEQ_PW_QHL:
14752 case OPC_PRECEQ_PW_QHR:
14753 case OPC_PRECEQ_PW_QHLA:
14754 case OPC_PRECEQ_PW_QHRA:
14755 case OPC_PRECEQU_QH_OBL:
14756 case OPC_PRECEQU_QH_OBR:
14757 case OPC_PRECEQU_QH_OBLA:
14758 case OPC_PRECEQU_QH_OBRA:
14759 case OPC_PRECEU_QH_OBL:
14760 case OPC_PRECEU_QH_OBR:
14761 case OPC_PRECEU_QH_OBLA:
14762 case OPC_PRECEU_QH_OBRA:
14763 case OPC_ABSQ_S_OB:
14764 case OPC_ABSQ_S_PW:
14765 case OPC_ABSQ_S_QH:
14766 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
14767 break;
14768 case OPC_REPL_OB:
14769 case OPC_REPL_PW:
14770 case OPC_REPL_QH:
14771 case OPC_REPLV_OB:
14772 case OPC_REPLV_PW:
14773 case OPC_REPLV_QH:
14774 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt);
14775 break;
14776 default: /* Invalid */
14777 MIPS_INVAL("MASK ABSQ_S.QH");
14778 gen_reserved_instruction(ctx);
14779 break;
14780 }
14781 break;
14782 case OPC_ADDU_OB_DSP:
14783 op2 = MASK_ADDU_OB(ctx->opcode);
14784 switch (op2) {
14785 case OPC_RADDU_L_OB:
14786 case OPC_SUBQ_PW:
14787 case OPC_SUBQ_S_PW:
14788 case OPC_SUBQ_QH:
14789 case OPC_SUBQ_S_QH:
14790 case OPC_SUBU_OB:
14791 case OPC_SUBU_S_OB:
14792 case OPC_SUBU_QH:
14793 case OPC_SUBU_S_QH:
14794 case OPC_SUBUH_OB:
14795 case OPC_SUBUH_R_OB:
14796 case OPC_ADDQ_PW:
14797 case OPC_ADDQ_S_PW:
14798 case OPC_ADDQ_QH:
14799 case OPC_ADDQ_S_QH:
14800 case OPC_ADDU_OB:
14801 case OPC_ADDU_S_OB:
14802 case OPC_ADDU_QH:
14803 case OPC_ADDU_S_QH:
14804 case OPC_ADDUH_OB:
14805 case OPC_ADDUH_R_OB:
14806 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
14807 break;
14808 case OPC_MULEQ_S_PW_QHL:
14809 case OPC_MULEQ_S_PW_QHR:
14810 case OPC_MULEU_S_QH_OBL:
14811 case OPC_MULEU_S_QH_OBR:
14812 case OPC_MULQ_RS_QH:
14813 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
14814 break;
14815 default: /* Invalid */
14816 MIPS_INVAL("MASK ADDU.OB");
14817 gen_reserved_instruction(ctx);
14818 break;
14819 }
14820 break;
14821 case OPC_CMPU_EQ_OB_DSP:
14822 op2 = MASK_CMPU_EQ_OB(ctx->opcode);
14823 switch (op2) {
14824 case OPC_PRECR_SRA_QH_PW:
14825 case OPC_PRECR_SRA_R_QH_PW:
14826 /* Return value is rt. */
14827 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd);
14828 break;
14829 case OPC_PRECR_OB_QH:
14830 case OPC_PRECRQ_OB_QH:
14831 case OPC_PRECRQ_PW_L:
14832 case OPC_PRECRQ_QH_PW:
14833 case OPC_PRECRQ_RS_QH_PW:
14834 case OPC_PRECRQU_S_OB_QH:
14835 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
14836 break;
14837 case OPC_CMPU_EQ_OB:
14838 case OPC_CMPU_LT_OB:
14839 case OPC_CMPU_LE_OB:
14840 case OPC_CMP_EQ_QH:
14841 case OPC_CMP_LT_QH:
14842 case OPC_CMP_LE_QH:
14843 case OPC_CMP_EQ_PW:
14844 case OPC_CMP_LT_PW:
14845 case OPC_CMP_LE_PW:
14846 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0);
14847 break;
14848 case OPC_CMPGDU_EQ_OB:
14849 case OPC_CMPGDU_LT_OB:
14850 case OPC_CMPGDU_LE_OB:
14851 case OPC_CMPGU_EQ_OB:
14852 case OPC_CMPGU_LT_OB:
14853 case OPC_CMPGU_LE_OB:
14854 case OPC_PACKRL_PW:
14855 case OPC_PICK_OB:
14856 case OPC_PICK_PW:
14857 case OPC_PICK_QH:
14858 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1);
14859 break;
14860 default: /* Invalid */
14861 MIPS_INVAL("MASK CMPU_EQ.OB");
14862 gen_reserved_instruction(ctx);
14863 break;
14864 }
14865 break;
14866 case OPC_DAPPEND_DSP:
14867 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd);
14868 break;
14869 case OPC_DEXTR_W_DSP:
14870 op2 = MASK_DEXTR_W(ctx->opcode);
14871 switch (op2) {
14872 case OPC_DEXTP:
14873 case OPC_DEXTPDP:
14874 case OPC_DEXTPDPV:
14875 case OPC_DEXTPV:
14876 case OPC_DEXTR_L:
14877 case OPC_DEXTR_R_L:
14878 case OPC_DEXTR_RS_L:
14879 case OPC_DEXTR_W:
14880 case OPC_DEXTR_R_W:
14881 case OPC_DEXTR_RS_W:
14882 case OPC_DEXTR_S_H:
14883 case OPC_DEXTRV_L:
14884 case OPC_DEXTRV_R_L:
14885 case OPC_DEXTRV_RS_L:
14886 case OPC_DEXTRV_S_H:
14887 case OPC_DEXTRV_W:
14888 case OPC_DEXTRV_R_W:
14889 case OPC_DEXTRV_RS_W:
14890 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1);
14891 break;
14892 case OPC_DMTHLIP:
14893 case OPC_DSHILO:
14894 case OPC_DSHILOV:
14895 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0);
14896 break;
14897 default: /* Invalid */
14898 MIPS_INVAL("MASK EXTR.W");
14899 gen_reserved_instruction(ctx);
14900 break;
14901 }
14902 break;
14903 case OPC_DPAQ_W_QH_DSP:
14904 op2 = MASK_DPAQ_W_QH(ctx->opcode);
14905 switch (op2) {
14906 case OPC_DPAU_H_OBL:
14907 case OPC_DPAU_H_OBR:
14908 case OPC_DPSU_H_OBL:
14909 case OPC_DPSU_H_OBR:
14910 case OPC_DPA_W_QH:
14911 case OPC_DPAQ_S_W_QH:
14912 case OPC_DPS_W_QH:
14913 case OPC_DPSQ_S_W_QH:
14914 case OPC_MULSAQ_S_W_QH:
14915 case OPC_DPAQ_SA_L_PW:
14916 case OPC_DPSQ_SA_L_PW:
14917 case OPC_MULSAQ_S_L_PW:
14918 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
14919 break;
14920 case OPC_MAQ_S_W_QHLL:
14921 case OPC_MAQ_S_W_QHLR:
14922 case OPC_MAQ_S_W_QHRL:
14923 case OPC_MAQ_S_W_QHRR:
14924 case OPC_MAQ_SA_W_QHLL:
14925 case OPC_MAQ_SA_W_QHLR:
14926 case OPC_MAQ_SA_W_QHRL:
14927 case OPC_MAQ_SA_W_QHRR:
14928 case OPC_MAQ_S_L_PWL:
14929 case OPC_MAQ_S_L_PWR:
14930 case OPC_DMADD:
14931 case OPC_DMADDU:
14932 case OPC_DMSUB:
14933 case OPC_DMSUBU:
14934 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
14935 break;
14936 default: /* Invalid */
14937 MIPS_INVAL("MASK DPAQ.W.QH");
14938 gen_reserved_instruction(ctx);
14939 break;
14940 }
14941 break;
14942 case OPC_DINSV_DSP:
14943 op2 = MASK_INSV(ctx->opcode);
14944 switch (op2) {
14945 case OPC_DINSV:
14946 {
14947 TCGv t0, t1;
14948
14949 check_dsp(ctx);
14950
14951 if (rt == 0) {
14952 break;
14953 }
14954
14955 t0 = tcg_temp_new();
14956 t1 = tcg_temp_new();
14957
14958 gen_load_gpr(t0, rt);
14959 gen_load_gpr(t1, rs);
14960
14961 gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0);
14962
14963 tcg_temp_free(t0);
14964 tcg_temp_free(t1);
14965 break;
14966 }
14967 default: /* Invalid */
14968 MIPS_INVAL("MASK DINSV");
14969 gen_reserved_instruction(ctx);
14970 break;
14971 }
14972 break;
14973 case OPC_SHLL_OB_DSP:
14974 gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
14975 break;
14976 #endif
14977 default: /* Invalid */
14978 MIPS_INVAL("special3_legacy");
14979 gen_reserved_instruction(ctx);
14980 break;
14981 }
14982 }
14983
14984
14985 #if defined(TARGET_MIPS64)
14986
14987 static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
14988 {
14989 uint32_t opc = MASK_MMI(ctx->opcode);
14990 int rs = extract32(ctx->opcode, 21, 5);
14991 int rt = extract32(ctx->opcode, 16, 5);
14992 int rd = extract32(ctx->opcode, 11, 5);
14993
14994 switch (opc) {
14995 case MMI_OPC_MULT1:
14996 case MMI_OPC_MULTU1:
14997 case MMI_OPC_MADD:
14998 case MMI_OPC_MADDU:
14999 case MMI_OPC_MADD1:
15000 case MMI_OPC_MADDU1:
15001 gen_mul_txx9(ctx, opc, rd, rs, rt);
15002 break;
15003 case MMI_OPC_DIV1:
15004 case MMI_OPC_DIVU1:
15005 gen_div1_tx79(ctx, opc, rs, rt);
15006 break;
15007 default:
15008 MIPS_INVAL("TX79 MMI class");
15009 gen_reserved_instruction(ctx);
15010 break;
15011 }
15012 }
15013
15014 static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
15015 {
15016 gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */
15017 }
15018
15019 /*
15020 * The TX79-specific instruction Store Quadword
15021 *
15022 * +--------+-------+-------+------------------------+
15023 * | 011111 | base | rt | offset | SQ
15024 * +--------+-------+-------+------------------------+
15025 * 6 5 5 16
15026 *
15027 * has the same opcode as the Read Hardware Register instruction
15028 *
15029 * +--------+-------+-------+-------+-------+--------+
15030 * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR
15031 * +--------+-------+-------+-------+-------+--------+
15032 * 6 5 5 5 5 6
15033 *
15034 * that is required, trapped and emulated by the Linux kernel. However, all
15035 * RDHWR encodings yield address error exceptions on the TX79 since the SQ
15036 * offset is odd. Therefore all valid SQ instructions can execute normally.
15037 * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
15038 * between SQ and RDHWR, as the Linux kernel does.
15039 */
15040 static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
15041 {
15042 int base = extract32(ctx->opcode, 21, 5);
15043 int rt = extract32(ctx->opcode, 16, 5);
15044 int offset = extract32(ctx->opcode, 0, 16);
15045
15046 #ifdef CONFIG_USER_ONLY
15047 uint32_t op1 = MASK_SPECIAL3(ctx->opcode);
15048 uint32_t op2 = extract32(ctx->opcode, 6, 5);
15049
15050 if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) {
15051 int rd = extract32(ctx->opcode, 11, 5);
15052
15053 gen_rdhwr(ctx, rt, rd, 0);
15054 return;
15055 }
15056 #endif
15057
15058 gen_mmi_sq(ctx, base, rt, offset);
15059 }
15060
15061 #endif
15062
15063 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
15064 {
15065 int rs, rt, rd, sa;
15066 uint32_t op1, op2;
15067 int16_t imm;
15068
15069 rs = (ctx->opcode >> 21) & 0x1f;
15070 rt = (ctx->opcode >> 16) & 0x1f;
15071 rd = (ctx->opcode >> 11) & 0x1f;
15072 sa = (ctx->opcode >> 6) & 0x1f;
15073 imm = sextract32(ctx->opcode, 7, 9);
15074
15075 op1 = MASK_SPECIAL3(ctx->opcode);
15076
15077 /*
15078 * EVA loads and stores overlap Loongson 2E instructions decoded by
15079 * decode_opc_special3_legacy(), so be careful to allow their decoding when
15080 * EVA is absent.
15081 */
15082 if (ctx->eva) {
15083 switch (op1) {
15084 case OPC_LWLE:
15085 case OPC_LWRE:
15086 case OPC_LBUE:
15087 case OPC_LHUE:
15088 case OPC_LBE:
15089 case OPC_LHE:
15090 case OPC_LLE:
15091 case OPC_LWE:
15092 check_cp0_enabled(ctx);
15093 gen_ld(ctx, op1, rt, rs, imm);
15094 return;
15095 case OPC_SWLE:
15096 case OPC_SWRE:
15097 case OPC_SBE:
15098 case OPC_SHE:
15099 case OPC_SWE:
15100 check_cp0_enabled(ctx);
15101 gen_st(ctx, op1, rt, rs, imm);
15102 return;
15103 case OPC_SCE:
15104 check_cp0_enabled(ctx);
15105 gen_st_cond(ctx, rt, rs, imm, MO_TESL, true);
15106 return;
15107 case OPC_CACHEE:
15108 check_eva(ctx);
15109 check_cp0_enabled(ctx);
15110 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
15111 gen_cache_operation(ctx, rt, rs, imm);
15112 }
15113 return;
15114 case OPC_PREFE:
15115 check_cp0_enabled(ctx);
15116 /* Treat as NOP. */
15117 return;
15118 }
15119 }
15120
15121 switch (op1) {
15122 case OPC_EXT:
15123 case OPC_INS:
15124 check_insn(ctx, ISA_MIPS_R2);
15125 gen_bitops(ctx, op1, rt, rs, sa, rd);
15126 break;
15127 case OPC_BSHFL:
15128 op2 = MASK_BSHFL(ctx->opcode);
15129 switch (op2) {
15130 case OPC_ALIGN:
15131 case OPC_ALIGN_1:
15132 case OPC_ALIGN_2:
15133 case OPC_ALIGN_3:
15134 case OPC_BITSWAP:
15135 check_insn(ctx, ISA_MIPS_R6);
15136 decode_opc_special3_r6(env, ctx);
15137 break;
15138 default:
15139 check_insn(ctx, ISA_MIPS_R2);
15140 gen_bshfl(ctx, op2, rt, rd);
15141 break;
15142 }
15143 break;
15144 #if defined(TARGET_MIPS64)
15145 case OPC_DEXTM:
15146 case OPC_DEXTU:
15147 case OPC_DEXT:
15148 case OPC_DINSM:
15149 case OPC_DINSU:
15150 case OPC_DINS:
15151 check_insn(ctx, ISA_MIPS_R2);
15152 check_mips_64(ctx);
15153 gen_bitops(ctx, op1, rt, rs, sa, rd);
15154 break;
15155 case OPC_DBSHFL:
15156 op2 = MASK_DBSHFL(ctx->opcode);
15157 switch (op2) {
15158 case OPC_DALIGN:
15159 case OPC_DALIGN_1:
15160 case OPC_DALIGN_2:
15161 case OPC_DALIGN_3:
15162 case OPC_DALIGN_4:
15163 case OPC_DALIGN_5:
15164 case OPC_DALIGN_6:
15165 case OPC_DALIGN_7:
15166 case OPC_DBITSWAP:
15167 check_insn(ctx, ISA_MIPS_R6);
15168 decode_opc_special3_r6(env, ctx);
15169 break;
15170 default:
15171 check_insn(ctx, ISA_MIPS_R2);
15172 check_mips_64(ctx);
15173 op2 = MASK_DBSHFL(ctx->opcode);
15174 gen_bshfl(ctx, op2, rt, rd);
15175 break;
15176 }
15177 break;
15178 #endif
15179 case OPC_RDHWR:
15180 gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3));
15181 break;
15182 case OPC_FORK:
15183 check_mt(ctx);
15184 {
15185 TCGv t0 = tcg_temp_new();
15186 TCGv t1 = tcg_temp_new();
15187
15188 gen_load_gpr(t0, rt);
15189 gen_load_gpr(t1, rs);
15190 gen_helper_fork(t0, t1);
15191 tcg_temp_free(t0);
15192 tcg_temp_free(t1);
15193 }
15194 break;
15195 case OPC_YIELD:
15196 check_mt(ctx);
15197 {
15198 TCGv t0 = tcg_temp_new();
15199
15200 gen_load_gpr(t0, rs);
15201 gen_helper_yield(t0, cpu_env, t0);
15202 gen_store_gpr(t0, rd);
15203 tcg_temp_free(t0);
15204 }
15205 break;
15206 default:
15207 if (ctx->insn_flags & ISA_MIPS_R6) {
15208 decode_opc_special3_r6(env, ctx);
15209 } else {
15210 decode_opc_special3_legacy(env, ctx);
15211 }
15212 }
15213 }
15214
15215 static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
15216 {
15217 int32_t offset;
15218 int rs, rt, rd, sa;
15219 uint32_t op, op1;
15220 int16_t imm;
15221
15222 op = MASK_OP_MAJOR(ctx->opcode);
15223 rs = (ctx->opcode >> 21) & 0x1f;
15224 rt = (ctx->opcode >> 16) & 0x1f;
15225 rd = (ctx->opcode >> 11) & 0x1f;
15226 sa = (ctx->opcode >> 6) & 0x1f;
15227 imm = (int16_t)ctx->opcode;
15228 switch (op) {
15229 case OPC_SPECIAL:
15230 decode_opc_special(env, ctx);
15231 break;
15232 case OPC_SPECIAL2:
15233 #if defined(TARGET_MIPS64)
15234 if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
15235 decode_mmi(env, ctx);
15236 break;
15237 }
15238 #endif
15239 if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) {
15240 if (MASK_SPECIAL2(ctx->opcode) == OPC_MUL) {
15241 gen_arith(ctx, OPC_MUL, rd, rs, rt);
15242 } else {
15243 decode_ase_mxu(ctx, ctx->opcode);
15244 }
15245 break;
15246 }
15247 decode_opc_special2_legacy(env, ctx);
15248 break;
15249 case OPC_SPECIAL3:
15250 #if defined(TARGET_MIPS64)
15251 if (ctx->insn_flags & INSN_R5900) {
15252 decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */
15253 } else {
15254 decode_opc_special3(env, ctx);
15255 }
15256 #else
15257 decode_opc_special3(env, ctx);
15258 #endif
15259 break;
15260 case OPC_REGIMM:
15261 op1 = MASK_REGIMM(ctx->opcode);
15262 switch (op1) {
15263 case OPC_BLTZL: /* REGIMM branches */
15264 case OPC_BGEZL:
15265 case OPC_BLTZALL:
15266 case OPC_BGEZALL:
15267 check_insn(ctx, ISA_MIPS2);
15268 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15269 /* Fallthrough */
15270 case OPC_BLTZ:
15271 case OPC_BGEZ:
15272 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
15273 break;
15274 case OPC_BLTZAL:
15275 case OPC_BGEZAL:
15276 if (ctx->insn_flags & ISA_MIPS_R6) {
15277 if (rs == 0) {
15278 /* OPC_NAL, OPC_BAL */
15279 gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4);
15280 } else {
15281 gen_reserved_instruction(ctx);
15282 }
15283 } else {
15284 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
15285 }
15286 break;
15287 case OPC_TGEI: /* REGIMM traps */
15288 case OPC_TGEIU:
15289 case OPC_TLTI:
15290 case OPC_TLTIU:
15291 case OPC_TEQI:
15292
15293 case OPC_TNEI:
15294 check_insn(ctx, ISA_MIPS2);
15295 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15296 gen_trap(ctx, op1, rs, -1, imm);
15297 break;
15298 case OPC_SIGRIE:
15299 check_insn(ctx, ISA_MIPS_R6);
15300 gen_reserved_instruction(ctx);
15301 break;
15302 case OPC_SYNCI:
15303 check_insn(ctx, ISA_MIPS_R2);
15304 /*
15305 * Break the TB to be able to sync copied instructions
15306 * immediately.
15307 */
15308 ctx->base.is_jmp = DISAS_STOP;
15309 break;
15310 case OPC_BPOSGE32: /* MIPS DSP branch */
15311 #if defined(TARGET_MIPS64)
15312 case OPC_BPOSGE64:
15313 #endif
15314 check_dsp(ctx);
15315 gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4);
15316 break;
15317 #if defined(TARGET_MIPS64)
15318 case OPC_DAHI:
15319 check_insn(ctx, ISA_MIPS_R6);
15320 check_mips_64(ctx);
15321 if (rs != 0) {
15322 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32);
15323 }
15324 break;
15325 case OPC_DATI:
15326 check_insn(ctx, ISA_MIPS_R6);
15327 check_mips_64(ctx);
15328 if (rs != 0) {
15329 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48);
15330 }
15331 break;
15332 #endif
15333 default: /* Invalid */
15334 MIPS_INVAL("regimm");
15335 gen_reserved_instruction(ctx);
15336 break;
15337 }
15338 break;
15339 case OPC_CP0:
15340 check_cp0_enabled(ctx);
15341 op1 = MASK_CP0(ctx->opcode);
15342 switch (op1) {
15343 case OPC_MFC0:
15344 case OPC_MTC0:
15345 case OPC_MFTR:
15346 case OPC_MTTR:
15347 case OPC_MFHC0:
15348 case OPC_MTHC0:
15349 #if defined(TARGET_MIPS64)
15350 case OPC_DMFC0:
15351 case OPC_DMTC0:
15352 #endif
15353 #ifndef CONFIG_USER_ONLY
15354 gen_cp0(env, ctx, op1, rt, rd);
15355 #endif /* !CONFIG_USER_ONLY */
15356 break;
15357 case OPC_C0:
15358 case OPC_C0_1:
15359 case OPC_C0_2:
15360 case OPC_C0_3:
15361 case OPC_C0_4:
15362 case OPC_C0_5:
15363 case OPC_C0_6:
15364 case OPC_C0_7:
15365 case OPC_C0_8:
15366 case OPC_C0_9:
15367 case OPC_C0_A:
15368 case OPC_C0_B:
15369 case OPC_C0_C:
15370 case OPC_C0_D:
15371 case OPC_C0_E:
15372 case OPC_C0_F:
15373 #ifndef CONFIG_USER_ONLY
15374 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
15375 #endif /* !CONFIG_USER_ONLY */
15376 break;
15377 case OPC_MFMC0:
15378 #ifndef CONFIG_USER_ONLY
15379 {
15380 uint32_t op2;
15381 TCGv t0 = tcg_temp_new();
15382
15383 op2 = MASK_MFMC0(ctx->opcode);
15384 switch (op2) {
15385 case OPC_DMT:
15386 check_cp0_mt(ctx);
15387 gen_helper_dmt(t0);
15388 gen_store_gpr(t0, rt);
15389 break;
15390 case OPC_EMT:
15391 check_cp0_mt(ctx);
15392 gen_helper_emt(t0);
15393 gen_store_gpr(t0, rt);
15394 break;
15395 case OPC_DVPE:
15396 check_cp0_mt(ctx);
15397 gen_helper_dvpe(t0, cpu_env);
15398 gen_store_gpr(t0, rt);
15399 break;
15400 case OPC_EVPE:
15401 check_cp0_mt(ctx);
15402 gen_helper_evpe(t0, cpu_env);
15403 gen_store_gpr(t0, rt);
15404 break;
15405 case OPC_DVP:
15406 check_insn(ctx, ISA_MIPS_R6);
15407 if (ctx->vp) {
15408 gen_helper_dvp(t0, cpu_env);
15409 gen_store_gpr(t0, rt);
15410 }
15411 break;
15412 case OPC_EVP:
15413 check_insn(ctx, ISA_MIPS_R6);
15414 if (ctx->vp) {
15415 gen_helper_evp(t0, cpu_env);
15416 gen_store_gpr(t0, rt);
15417 }
15418 break;
15419 case OPC_DI:
15420 check_insn(ctx, ISA_MIPS_R2);
15421 save_cpu_state(ctx, 1);
15422 gen_helper_di(t0, cpu_env);
15423 gen_store_gpr(t0, rt);
15424 /*
15425 * Stop translation as we may have switched
15426 * the execution mode.
15427 */
15428 ctx->base.is_jmp = DISAS_STOP;
15429 break;
15430 case OPC_EI:
15431 check_insn(ctx, ISA_MIPS_R2);
15432 save_cpu_state(ctx, 1);
15433 gen_helper_ei(t0, cpu_env);
15434 gen_store_gpr(t0, rt);
15435 /*
15436 * DISAS_STOP isn't sufficient, we need to ensure we break
15437 * out of translated code to check for pending interrupts.
15438 */
15439 gen_save_pc(ctx->base.pc_next + 4);
15440 ctx->base.is_jmp = DISAS_EXIT;
15441 break;
15442 default: /* Invalid */
15443 MIPS_INVAL("mfmc0");
15444 gen_reserved_instruction(ctx);
15445 break;
15446 }
15447 tcg_temp_free(t0);
15448 }
15449 #endif /* !CONFIG_USER_ONLY */
15450 break;
15451 case OPC_RDPGPR:
15452 check_insn(ctx, ISA_MIPS_R2);
15453 gen_load_srsgpr(rt, rd);
15454 break;
15455 case OPC_WRPGPR:
15456 check_insn(ctx, ISA_MIPS_R2);
15457 gen_store_srsgpr(rt, rd);
15458 break;
15459 default:
15460 MIPS_INVAL("cp0");
15461 gen_reserved_instruction(ctx);
15462 break;
15463 }
15464 break;
15465 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */
15466 if (ctx->insn_flags & ISA_MIPS_R6) {
15467 /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */
15468 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
15469 } else {
15470 /* OPC_ADDI */
15471 /* Arithmetic with immediate opcode */
15472 gen_arith_imm(ctx, op, rt, rs, imm);
15473 }
15474 break;
15475 case OPC_ADDIU:
15476 gen_arith_imm(ctx, op, rt, rs, imm);
15477 break;
15478 case OPC_SLTI: /* Set on less than with immediate opcode */
15479 case OPC_SLTIU:
15480 gen_slt_imm(ctx, op, rt, rs, imm);
15481 break;
15482 case OPC_ANDI: /* Arithmetic with immediate opcode */
15483 case OPC_LUI: /* OPC_AUI */
15484 case OPC_ORI:
15485 case OPC_XORI:
15486 gen_logic_imm(ctx, op, rt, rs, imm);
15487 break;
15488 case OPC_J: /* Jump */
15489 case OPC_JAL:
15490 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
15491 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
15492 break;
15493 /* Branch */
15494 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
15495 if (ctx->insn_flags & ISA_MIPS_R6) {
15496 if (rt == 0) {
15497 gen_reserved_instruction(ctx);
15498 break;
15499 }
15500 /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
15501 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
15502 } else {
15503 /* OPC_BLEZL */
15504 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
15505 }
15506 break;
15507 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
15508 if (ctx->insn_flags & ISA_MIPS_R6) {
15509 if (rt == 0) {
15510 gen_reserved_instruction(ctx);
15511 break;
15512 }
15513 /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
15514 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
15515 } else {
15516 /* OPC_BGTZL */
15517 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
15518 }
15519 break;
15520 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */
15521 if (rt == 0) {
15522 /* OPC_BLEZ */
15523 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
15524 } else {
15525 check_insn(ctx, ISA_MIPS_R6);
15526 /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */
15527 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
15528 }
15529 break;
15530 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */
15531 if (rt == 0) {
15532 /* OPC_BGTZ */
15533 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
15534 } else {
15535 check_insn(ctx, ISA_MIPS_R6);
15536 /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */
15537 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
15538 }
15539 break;
15540 case OPC_BEQL:
15541 case OPC_BNEL:
15542 check_insn(ctx, ISA_MIPS2);
15543 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15544 /* Fallthrough */
15545 case OPC_BEQ:
15546 case OPC_BNE:
15547 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
15548 break;
15549 case OPC_LL: /* Load and stores */
15550 check_insn(ctx, ISA_MIPS2);
15551 if (ctx->insn_flags & INSN_R5900) {
15552 check_insn_opc_user_only(ctx, INSN_R5900);
15553 }
15554 /* Fallthrough */
15555 case OPC_LWL:
15556 case OPC_LWR:
15557 case OPC_LB:
15558 case OPC_LH:
15559 case OPC_LW:
15560 case OPC_LWPC:
15561 case OPC_LBU:
15562 case OPC_LHU:
15563 gen_ld(ctx, op, rt, rs, imm);
15564 break;
15565 case OPC_SWL:
15566 case OPC_SWR:
15567 case OPC_SB:
15568 case OPC_SH:
15569 case OPC_SW:
15570 gen_st(ctx, op, rt, rs, imm);
15571 break;
15572 case OPC_SC:
15573 check_insn(ctx, ISA_MIPS2);
15574 if (ctx->insn_flags & INSN_R5900) {
15575 check_insn_opc_user_only(ctx, INSN_R5900);
15576 }
15577 gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
15578 break;
15579 case OPC_CACHE:
15580 check_cp0_enabled(ctx);
15581 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
15582 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
15583 gen_cache_operation(ctx, rt, rs, imm);
15584 }
15585 /* Treat as NOP. */
15586 break;
15587 case OPC_PREF:
15588 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_R5900);
15589 /* Treat as NOP. */
15590 break;
15591
15592 /* Floating point (COP1). */
15593 case OPC_LWC1:
15594 case OPC_LDC1:
15595 case OPC_SWC1:
15596 case OPC_SDC1:
15597 gen_cop1_ldst(ctx, op, rt, rs, imm);
15598 break;
15599
15600 case OPC_CP1:
15601 op1 = MASK_CP1(ctx->opcode);
15602
15603 switch (op1) {
15604 case OPC_MFHC1:
15605 case OPC_MTHC1:
15606 check_cp1_enabled(ctx);
15607 check_insn(ctx, ISA_MIPS_R2);
15608 /* fall through */
15609 case OPC_MFC1:
15610 case OPC_CFC1:
15611 case OPC_MTC1:
15612 case OPC_CTC1:
15613 check_cp1_enabled(ctx);
15614 gen_cp1(ctx, op1, rt, rd);
15615 break;
15616 #if defined(TARGET_MIPS64)
15617 case OPC_DMFC1:
15618 case OPC_DMTC1:
15619 check_cp1_enabled(ctx);
15620 check_insn(ctx, ISA_MIPS3);
15621 check_mips_64(ctx);
15622 gen_cp1(ctx, op1, rt, rd);
15623 break;
15624 #endif
15625 case OPC_BC1EQZ: /* OPC_BC1ANY2 */
15626 check_cp1_enabled(ctx);
15627 if (ctx->insn_flags & ISA_MIPS_R6) {
15628 /* OPC_BC1EQZ */
15629 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
15630 rt, imm << 2, 4);
15631 } else {
15632 /* OPC_BC1ANY2 */
15633 check_cop1x(ctx);
15634 check_insn(ctx, ASE_MIPS3D);
15635 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
15636 (rt >> 2) & 0x7, imm << 2);
15637 }
15638 break;
15639 case OPC_BC1NEZ:
15640 check_cp1_enabled(ctx);
15641 check_insn(ctx, ISA_MIPS_R6);
15642 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
15643 rt, imm << 2, 4);
15644 break;
15645 case OPC_BC1ANY4:
15646 check_cp1_enabled(ctx);
15647 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15648 check_cop1x(ctx);
15649 check_insn(ctx, ASE_MIPS3D);
15650 /* fall through */
15651 case OPC_BC1:
15652 check_cp1_enabled(ctx);
15653 check_insn_opc_removed(ctx, ISA_MIPS_R6);
15654 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
15655 (rt >> 2) & 0x7, imm << 2);
15656 break;
15657 case OPC_PS_FMT:
15658 check_ps(ctx);
15659 /* fall through */
15660 case OPC_S_FMT:
15661 case OPC_D_FMT:
15662 check_cp1_enabled(ctx);
15663 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
15664 (imm >> 8) & 0x7);
15665 break;
15666 case OPC_W_FMT:
15667 case OPC_L_FMT:
15668 {
15669 int r6_op = ctx->opcode & FOP(0x3f, 0x1f);
15670 check_cp1_enabled(ctx);
15671 if (ctx->insn_flags & ISA_MIPS_R6) {
15672 switch (r6_op) {
15673 case R6_OPC_CMP_AF_S:
15674 case R6_OPC_CMP_UN_S:
15675 case R6_OPC_CMP_EQ_S:
15676 case R6_OPC_CMP_UEQ_S:
15677 case R6_OPC_CMP_LT_S:
15678 case R6_OPC_CMP_ULT_S:
15679 case R6_OPC_CMP_LE_S:
15680 case R6_OPC_CMP_ULE_S:
15681 case R6_OPC_CMP_SAF_S:
15682 case R6_OPC_CMP_SUN_S:
15683 case R6_OPC_CMP_SEQ_S:
15684 case R6_OPC_CMP_SEUQ_S:
15685 case R6_OPC_CMP_SLT_S:
15686 case R6_OPC_CMP_SULT_S:
15687 case R6_OPC_CMP_SLE_S:
15688 case R6_OPC_CMP_SULE_S:
15689 case R6_OPC_CMP_OR_S:
15690 case R6_OPC_CMP_UNE_S:
15691 case R6_OPC_CMP_NE_S:
15692 case R6_OPC_CMP_SOR_S:
15693 case R6_OPC_CMP_SUNE_S:
15694 case R6_OPC_CMP_SNE_S:
15695 gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa);
15696 break;
15697 case R6_OPC_CMP_AF_D:
15698 case R6_OPC_CMP_UN_D:
15699 case R6_OPC_CMP_EQ_D:
15700 case R6_OPC_CMP_UEQ_D:
15701 case R6_OPC_CMP_LT_D:
15702 case R6_OPC_CMP_ULT_D:
15703 case R6_OPC_CMP_LE_D:
15704 case R6_OPC_CMP_ULE_D:
15705 case R6_OPC_CMP_SAF_D:
15706 case R6_OPC_CMP_SUN_D:
15707 case R6_OPC_CMP_SEQ_D:
15708 case R6_OPC_CMP_SEUQ_D:
15709 case R6_OPC_CMP_SLT_D:
15710 case R6_OPC_CMP_SULT_D:
15711 case R6_OPC_CMP_SLE_D:
15712 case R6_OPC_CMP_SULE_D:
15713 case R6_OPC_CMP_OR_D:
15714 case R6_OPC_CMP_UNE_D:
15715 case R6_OPC_CMP_NE_D:
15716 case R6_OPC_CMP_SOR_D:
15717 case R6_OPC_CMP_SUNE_D:
15718 case R6_OPC_CMP_SNE_D:
15719 gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa);
15720 break;
15721 default:
15722 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f),
15723 rt, rd, sa, (imm >> 8) & 0x7);
15724
15725 break;
15726 }
15727 } else {
15728 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
15729 (imm >> 8) & 0x7);
15730 }
15731 break;
15732 }
15733 default:
15734 MIPS_INVAL("cp1");
15735 gen_reserved_instruction(ctx);
15736 break;
15737 }
15738 break;
15739
15740 /* Compact branches [R6] and COP2 [non-R6] */
15741 case OPC_BC: /* OPC_LWC2 */
15742 case OPC_BALC: /* OPC_SWC2 */
15743 if (ctx->insn_flags & ISA_MIPS_R6) {
15744 /* OPC_BC, OPC_BALC */
15745 gen_compute_compact_branch(ctx, op, 0, 0,
15746 sextract32(ctx->opcode << 2, 0, 28));
15747 } else if (ctx->insn_flags & ASE_LEXT) {
15748 gen_loongson_lswc2(ctx, rt, rs, rd);
15749 } else {
15750 /* OPC_LWC2, OPC_SWC2 */
15751 /* COP2: Not implemented. */
15752 generate_exception_err(ctx, EXCP_CpU, 2);
15753 }
15754 break;
15755 case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */
15756 case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */
15757 if (ctx->insn_flags & ISA_MIPS_R6) {
15758 if (rs != 0) {
15759 /* OPC_BEQZC, OPC_BNEZC */
15760 gen_compute_compact_branch(ctx, op, rs, 0,
15761 sextract32(ctx->opcode << 2, 0, 23));
15762 } else {
15763 /* OPC_JIC, OPC_JIALC */
15764 gen_compute_compact_branch(ctx, op, 0, rt, imm);
15765 }
15766 } else if (ctx->insn_flags & ASE_LEXT) {
15767 gen_loongson_lsdc2(ctx, rt, rs, rd);
15768 } else {
15769 /* OPC_LWC2, OPC_SWC2 */
15770 /* COP2: Not implemented. */
15771 generate_exception_err(ctx, EXCP_CpU, 2);
15772 }
15773 break;
15774 case OPC_CP2:
15775 check_insn(ctx, ASE_LMMI);
15776 /* Note that these instructions use different fields. */
15777 gen_loongson_multimedia(ctx, sa, rd, rt);
15778 break;
15779
15780 case OPC_CP3:
15781 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
15782 check_cp1_enabled(ctx);
15783 op1 = MASK_CP3(ctx->opcode);
15784 switch (op1) {
15785 case OPC_LUXC1:
15786 case OPC_SUXC1:
15787 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
15788 /* Fallthrough */
15789 case OPC_LWXC1:
15790 case OPC_LDXC1:
15791 case OPC_SWXC1:
15792 case OPC_SDXC1:
15793 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
15794 gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
15795 break;
15796 case OPC_PREFX:
15797 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
15798 /* Treat as NOP. */
15799 break;
15800 case OPC_ALNV_PS:
15801 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
15802 /* Fallthrough */
15803 case OPC_MADD_S:
15804 case OPC_MADD_D:
15805 case OPC_MADD_PS:
15806 case OPC_MSUB_S:
15807 case OPC_MSUB_D:
15808 case OPC_MSUB_PS:
15809 case OPC_NMADD_S:
15810 case OPC_NMADD_D:
15811 case OPC_NMADD_PS:
15812 case OPC_NMSUB_S:
15813 case OPC_NMSUB_D:
15814 case OPC_NMSUB_PS:
15815 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
15816 gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
15817 break;
15818 default:
15819 MIPS_INVAL("cp3");
15820 gen_reserved_instruction(ctx);
15821 break;
15822 }
15823 } else {
15824 generate_exception_err(ctx, EXCP_CpU, 1);
15825 }
15826 break;
15827
15828 #if defined(TARGET_MIPS64)
15829 /* MIPS64 opcodes */
15830 case OPC_LLD:
15831 if (ctx->insn_flags & INSN_R5900) {
15832 check_insn_opc_user_only(ctx, INSN_R5900);
15833 }
15834 /* fall through */
15835 case OPC_LDL:
15836 case OPC_LDR:
15837 case OPC_LWU:
15838 case OPC_LD:
15839 check_insn(ctx, ISA_MIPS3);
15840 check_mips_64(ctx);
15841 gen_ld(ctx, op, rt, rs, imm);
15842 break;
15843 case OPC_SDL:
15844 case OPC_SDR:
15845 case OPC_SD:
15846 check_insn(ctx, ISA_MIPS3);
15847 check_mips_64(ctx);
15848 gen_st(ctx, op, rt, rs, imm);
15849 break;
15850 case OPC_SCD:
15851 check_insn(ctx, ISA_MIPS3);
15852 if (ctx->insn_flags & INSN_R5900) {
15853 check_insn_opc_user_only(ctx, INSN_R5900);
15854 }
15855 check_mips_64(ctx);
15856 gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false);
15857 break;
15858 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
15859 if (ctx->insn_flags & ISA_MIPS_R6) {
15860 /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
15861 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
15862 } else {
15863 /* OPC_DADDI */
15864 check_insn(ctx, ISA_MIPS3);
15865 check_mips_64(ctx);
15866 gen_arith_imm(ctx, op, rt, rs, imm);
15867 }
15868 break;
15869 case OPC_DADDIU:
15870 check_insn(ctx, ISA_MIPS3);
15871 check_mips_64(ctx);
15872 gen_arith_imm(ctx, op, rt, rs, imm);
15873 break;
15874 #else
15875 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
15876 if (ctx->insn_flags & ISA_MIPS_R6) {
15877 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
15878 } else {
15879 MIPS_INVAL("major opcode");
15880 gen_reserved_instruction(ctx);
15881 }
15882 break;
15883 #endif
15884 case OPC_DAUI: /* OPC_JALX */
15885 if (ctx->insn_flags & ISA_MIPS_R6) {
15886 #if defined(TARGET_MIPS64)
15887 /* OPC_DAUI */
15888 check_mips_64(ctx);
15889 if (rs == 0) {
15890 generate_exception(ctx, EXCP_RI);
15891 } else if (rt != 0) {
15892 TCGv t0 = tcg_temp_new();
15893 gen_load_gpr(t0, rs);
15894 tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);
15895 tcg_temp_free(t0);
15896 }
15897 #else
15898 gen_reserved_instruction(ctx);
15899 MIPS_INVAL("major opcode");
15900 #endif
15901 } else {
15902 /* OPC_JALX */
15903 check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS);
15904 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
15905 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
15906 }
15907 break;
15908 case OPC_MDMX:
15909 /* MDMX: Not implemented. */
15910 break;
15911 case OPC_PCREL:
15912 check_insn(ctx, ISA_MIPS_R6);
15913 gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs);
15914 break;
15915 default: /* Invalid */
15916 MIPS_INVAL("major opcode");
15917 return false;
15918 }
15919 return true;
15920 }
15921
15922 static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
15923 {
15924 /* make sure instructions are on a word boundary */
15925 if (ctx->base.pc_next & 0x3) {
15926 env->CP0_BadVAddr = ctx->base.pc_next;
15927 generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
15928 return;
15929 }
15930
15931 /* Handle blikely not taken case */
15932 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
15933 TCGLabel *l1 = gen_new_label();
15934
15935 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
15936 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
15937 gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
15938 gen_set_label(l1);
15939 }
15940
15941 /* Transition to the auto-generated decoder. */
15942
15943 /* Vendor specific extensions */
15944 if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) {
15945 return;
15946 }
15947 if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) {
15948 return;
15949 }
15950
15951 /* ISA extensions */
15952 if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
15953 return;
15954 }
15955
15956 /* ISA (from latest to oldest) */
15957 if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) {
15958 return;
15959 }
15960
15961 if (decode_opc_legacy(env, ctx)) {
15962 return;
15963 }
15964
15965 gen_reserved_instruction(ctx);
15966 }
15967
15968 static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
15969 {
15970 DisasContext *ctx = container_of(dcbase, DisasContext, base);
15971 CPUMIPSState *env = cs->env_ptr;
15972
15973 ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
15974 ctx->saved_pc = -1;
15975 ctx->insn_flags = env->insn_flags;
15976 ctx->CP0_Config0 = env->CP0_Config0;
15977 ctx->CP0_Config1 = env->CP0_Config1;
15978 ctx->CP0_Config2 = env->CP0_Config2;
15979 ctx->CP0_Config3 = env->CP0_Config3;
15980 ctx->CP0_Config5 = env->CP0_Config5;
15981 ctx->btarget = 0;
15982 ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
15983 ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
15984 ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
15985 ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
15986 ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
15987 ctx->PAMask = env->PAMask;
15988 ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
15989 ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1;
15990 ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1;
15991 ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift;
15992 ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
15993 /* Restore delay slot state from the tb context. */
15994 ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */
15995 ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
15996 ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
15997 (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
15998 ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
15999 ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
16000 ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
16001 ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
16002 ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1;
16003 ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3;
16004 restore_cpu_state(env, ctx);
16005 #ifdef CONFIG_USER_ONLY
16006 ctx->mem_idx = MIPS_HFLAG_UM;
16007 #else
16008 ctx->mem_idx = hflags_mmu_index(ctx->hflags);
16009 #endif
16010 ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
16011 INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
16012
16013 /*
16014 * Execute a branch and its delay slot as a single instruction.
16015 * This is what GDB expects and is consistent with what the
16016 * hardware does (e.g. if a delay slot instruction faults, the
16017 * reported PC is the PC of the branch).
16018 */
16019 if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) {
16020 ctx->base.max_insns = 2;
16021 }
16022
16023 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
16024 ctx->hflags);
16025 }
16026
16027 static void mips_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
16028 {
16029 }
16030
16031 static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
16032 {
16033 DisasContext *ctx = container_of(dcbase, DisasContext, base);
16034
16035 tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK,
16036 ctx->btarget);
16037 }
16038
16039 static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
16040 {
16041 CPUMIPSState *env = cs->env_ptr;
16042 DisasContext *ctx = container_of(dcbase, DisasContext, base);
16043 int insn_bytes;
16044 int is_slot;
16045
16046 is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
16047 if (ctx->insn_flags & ISA_NANOMIPS32) {
16048 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
16049 insn_bytes = decode_isa_nanomips(env, ctx);
16050 } else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
16051 ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
16052 insn_bytes = 4;
16053 decode_opc(env, ctx);
16054 } else if (ctx->insn_flags & ASE_MICROMIPS) {
16055 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
16056 insn_bytes = decode_isa_micromips(env, ctx);
16057 } else if (ctx->insn_flags & ASE_MIPS16) {
16058 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
16059 insn_bytes = decode_ase_mips16e(env, ctx);
16060 } else {
16061 gen_reserved_instruction(ctx);
16062 g_assert(ctx->base.is_jmp == DISAS_NORETURN);
16063 return;
16064 }
16065
16066 if (ctx->hflags & MIPS_HFLAG_BMASK) {
16067 if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
16068 MIPS_HFLAG_FBNSLOT))) {
16069 /*
16070 * Force to generate branch as there is neither delay nor
16071 * forbidden slot.
16072 */
16073 is_slot = 1;
16074 }
16075 if ((ctx->hflags & MIPS_HFLAG_M16) &&
16076 (ctx->hflags & MIPS_HFLAG_FBNSLOT)) {
16077 /*
16078 * Force to generate branch as microMIPS R6 doesn't restrict
16079 * branches in the forbidden slot.
16080 */
16081 is_slot = 1;
16082 }
16083 }
16084 if (is_slot) {
16085 gen_branch(ctx, insn_bytes);
16086 }
16087 ctx->base.pc_next += insn_bytes;
16088
16089 if (ctx->base.is_jmp != DISAS_NEXT) {
16090 return;
16091 }
16092
16093 /*
16094 * End the TB on (most) page crossings.
16095 * See mips_tr_init_disas_context about single-stepping a branch
16096 * together with its delay slot.
16097 */
16098 if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE
16099 && !ctx->base.singlestep_enabled) {
16100 ctx->base.is_jmp = DISAS_TOO_MANY;
16101 }
16102 }
16103
16104 static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
16105 {
16106 DisasContext *ctx = container_of(dcbase, DisasContext, base);
16107
16108 switch (ctx->base.is_jmp) {
16109 case DISAS_STOP:
16110 gen_save_pc(ctx->base.pc_next);
16111 tcg_gen_lookup_and_goto_ptr();
16112 break;
16113 case DISAS_NEXT:
16114 case DISAS_TOO_MANY:
16115 save_cpu_state(ctx, 0);
16116 gen_goto_tb(ctx, 0, ctx->base.pc_next);
16117 break;
16118 case DISAS_EXIT:
16119 tcg_gen_exit_tb(NULL, 0);
16120 break;
16121 case DISAS_NORETURN:
16122 break;
16123 default:
16124 g_assert_not_reached();
16125 }
16126 }
16127
16128 static void mips_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
16129 {
16130 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
16131 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
16132 }
16133
16134 static const TranslatorOps mips_tr_ops = {
16135 .init_disas_context = mips_tr_init_disas_context,
16136 .tb_start = mips_tr_tb_start,
16137 .insn_start = mips_tr_insn_start,
16138 .translate_insn = mips_tr_translate_insn,
16139 .tb_stop = mips_tr_tb_stop,
16140 .disas_log = mips_tr_disas_log,
16141 };
16142
16143 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
16144 {
16145 DisasContext ctx;
16146
16147 translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
16148 }
16149
16150 void mips_tcg_init(void)
16151 {
16152 int i;
16153
16154 cpu_gpr[0] = NULL;
16155 for (i = 1; i < 32; i++)
16156 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
16157 offsetof(CPUMIPSState,
16158 active_tc.gpr[i]),
16159 regnames[i]);
16160 #if defined(TARGET_MIPS64)
16161 cpu_gpr_hi[0] = NULL;
16162
16163 for (unsigned i = 1; i < 32; i++) {
16164 g_autofree char *rname = g_strdup_printf("%s[hi]", regnames[i]);
16165
16166 cpu_gpr_hi[i] = tcg_global_mem_new_i64(cpu_env,
16167 offsetof(CPUMIPSState,
16168 active_tc.gpr_hi[i]),
16169 rname);
16170 }
16171 #endif /* !TARGET_MIPS64 */
16172 for (i = 0; i < 32; i++) {
16173 int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
16174
16175 fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
16176 }
16177 msa_translate_init();
16178 cpu_PC = tcg_global_mem_new(cpu_env,
16179 offsetof(CPUMIPSState, active_tc.PC), "PC");
16180 for (i = 0; i < MIPS_DSP_ACC; i++) {
16181 cpu_HI[i] = tcg_global_mem_new(cpu_env,
16182 offsetof(CPUMIPSState, active_tc.HI[i]),
16183 regnames_HI[i]);
16184 cpu_LO[i] = tcg_global_mem_new(cpu_env,
16185 offsetof(CPUMIPSState, active_tc.LO[i]),
16186 regnames_LO[i]);
16187 }
16188 cpu_dspctrl = tcg_global_mem_new(cpu_env,
16189 offsetof(CPUMIPSState,
16190 active_tc.DSPControl),
16191 "DSPControl");
16192 bcond = tcg_global_mem_new(cpu_env,
16193 offsetof(CPUMIPSState, bcond), "bcond");
16194 btarget = tcg_global_mem_new(cpu_env,
16195 offsetof(CPUMIPSState, btarget), "btarget");
16196 hflags = tcg_global_mem_new_i32(cpu_env,
16197 offsetof(CPUMIPSState, hflags), "hflags");
16198
16199 fpu_fcr0 = tcg_global_mem_new_i32(cpu_env,
16200 offsetof(CPUMIPSState, active_fpu.fcr0),
16201 "fcr0");
16202 fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
16203 offsetof(CPUMIPSState, active_fpu.fcr31),
16204 "fcr31");
16205 cpu_lladdr = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, lladdr),
16206 "lladdr");
16207 cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
16208 "llval");
16209
16210 if (TARGET_LONG_BITS == 32) {
16211 mxu_translate_init();
16212 }
16213 }
16214
16215 void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,
16216 target_ulong *data)
16217 {
16218 env->active_tc.PC = data[0];
16219 env->hflags &= ~MIPS_HFLAG_BMASK;
16220 env->hflags |= data[1];
16221 switch (env->hflags & MIPS_HFLAG_BMASK_BASE) {
16222 case MIPS_HFLAG_BR:
16223 break;
16224 case MIPS_HFLAG_BC:
16225 case MIPS_HFLAG_BL:
16226 case MIPS_HFLAG_B:
16227 env->btarget = data[2];
16228 break;
16229 }
16230 }
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