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[mirror_qemu.git] / target / mips / translate.c
1 /*
2 * MIPS32 emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "cpu.h"
26 #include "disas/disas.h"
27 #include "exec/exec-all.h"
28 #include "tcg-op.h"
29 #include "exec/cpu_ldst.h"
30
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
33 #include "sysemu/kvm.h"
34 #include "exec/semihost.h"
35
36 #include "trace-tcg.h"
37 #include "exec/log.h"
38
39 #define MIPS_DEBUG_DISAS 0
40
41 /* MIPS major opcodes */
42 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
43
44 enum {
45 /* indirect opcode tables */
46 OPC_SPECIAL = (0x00 << 26),
47 OPC_REGIMM = (0x01 << 26),
48 OPC_CP0 = (0x10 << 26),
49 OPC_CP1 = (0x11 << 26),
50 OPC_CP2 = (0x12 << 26),
51 OPC_CP3 = (0x13 << 26),
52 OPC_SPECIAL2 = (0x1C << 26),
53 OPC_SPECIAL3 = (0x1F << 26),
54 /* arithmetic with immediate */
55 OPC_ADDI = (0x08 << 26),
56 OPC_ADDIU = (0x09 << 26),
57 OPC_SLTI = (0x0A << 26),
58 OPC_SLTIU = (0x0B << 26),
59 /* logic with immediate */
60 OPC_ANDI = (0x0C << 26),
61 OPC_ORI = (0x0D << 26),
62 OPC_XORI = (0x0E << 26),
63 OPC_LUI = (0x0F << 26),
64 /* arithmetic with immediate */
65 OPC_DADDI = (0x18 << 26),
66 OPC_DADDIU = (0x19 << 26),
67 /* Jump and branches */
68 OPC_J = (0x02 << 26),
69 OPC_JAL = (0x03 << 26),
70 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
71 OPC_BEQL = (0x14 << 26),
72 OPC_BNE = (0x05 << 26),
73 OPC_BNEL = (0x15 << 26),
74 OPC_BLEZ = (0x06 << 26),
75 OPC_BLEZL = (0x16 << 26),
76 OPC_BGTZ = (0x07 << 26),
77 OPC_BGTZL = (0x17 << 26),
78 OPC_JALX = (0x1D << 26),
79 OPC_DAUI = (0x1D << 26),
80 /* Load and stores */
81 OPC_LDL = (0x1A << 26),
82 OPC_LDR = (0x1B << 26),
83 OPC_LB = (0x20 << 26),
84 OPC_LH = (0x21 << 26),
85 OPC_LWL = (0x22 << 26),
86 OPC_LW = (0x23 << 26),
87 OPC_LWPC = OPC_LW | 0x5,
88 OPC_LBU = (0x24 << 26),
89 OPC_LHU = (0x25 << 26),
90 OPC_LWR = (0x26 << 26),
91 OPC_LWU = (0x27 << 26),
92 OPC_SB = (0x28 << 26),
93 OPC_SH = (0x29 << 26),
94 OPC_SWL = (0x2A << 26),
95 OPC_SW = (0x2B << 26),
96 OPC_SDL = (0x2C << 26),
97 OPC_SDR = (0x2D << 26),
98 OPC_SWR = (0x2E << 26),
99 OPC_LL = (0x30 << 26),
100 OPC_LLD = (0x34 << 26),
101 OPC_LD = (0x37 << 26),
102 OPC_LDPC = OPC_LD | 0x5,
103 OPC_SC = (0x38 << 26),
104 OPC_SCD = (0x3C << 26),
105 OPC_SD = (0x3F << 26),
106 /* Floating point load/store */
107 OPC_LWC1 = (0x31 << 26),
108 OPC_LWC2 = (0x32 << 26),
109 OPC_LDC1 = (0x35 << 26),
110 OPC_LDC2 = (0x36 << 26),
111 OPC_SWC1 = (0x39 << 26),
112 OPC_SWC2 = (0x3A << 26),
113 OPC_SDC1 = (0x3D << 26),
114 OPC_SDC2 = (0x3E << 26),
115 /* Compact Branches */
116 OPC_BLEZALC = (0x06 << 26),
117 OPC_BGEZALC = (0x06 << 26),
118 OPC_BGEUC = (0x06 << 26),
119 OPC_BGTZALC = (0x07 << 26),
120 OPC_BLTZALC = (0x07 << 26),
121 OPC_BLTUC = (0x07 << 26),
122 OPC_BOVC = (0x08 << 26),
123 OPC_BEQZALC = (0x08 << 26),
124 OPC_BEQC = (0x08 << 26),
125 OPC_BLEZC = (0x16 << 26),
126 OPC_BGEZC = (0x16 << 26),
127 OPC_BGEC = (0x16 << 26),
128 OPC_BGTZC = (0x17 << 26),
129 OPC_BLTZC = (0x17 << 26),
130 OPC_BLTC = (0x17 << 26),
131 OPC_BNVC = (0x18 << 26),
132 OPC_BNEZALC = (0x18 << 26),
133 OPC_BNEC = (0x18 << 26),
134 OPC_BC = (0x32 << 26),
135 OPC_BEQZC = (0x36 << 26),
136 OPC_JIC = (0x36 << 26),
137 OPC_BALC = (0x3A << 26),
138 OPC_BNEZC = (0x3E << 26),
139 OPC_JIALC = (0x3E << 26),
140 /* MDMX ASE specific */
141 OPC_MDMX = (0x1E << 26),
142 /* MSA ASE, same as MDMX */
143 OPC_MSA = OPC_MDMX,
144 /* Cache and prefetch */
145 OPC_CACHE = (0x2F << 26),
146 OPC_PREF = (0x33 << 26),
147 /* PC-relative address computation / loads */
148 OPC_PCREL = (0x3B << 26),
149 };
150
151 /* PC-relative address computation / loads */
152 #define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19)))
153 #define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16)))
154 enum {
155 /* Instructions determined by bits 19 and 20 */
156 OPC_ADDIUPC = OPC_PCREL | (0 << 19),
157 R6_OPC_LWPC = OPC_PCREL | (1 << 19),
158 OPC_LWUPC = OPC_PCREL | (2 << 19),
159
160 /* Instructions determined by bits 16 ... 20 */
161 OPC_AUIPC = OPC_PCREL | (0x1e << 16),
162 OPC_ALUIPC = OPC_PCREL | (0x1f << 16),
163
164 /* Other */
165 R6_OPC_LDPC = OPC_PCREL | (6 << 18),
166 };
167
168 /* MIPS special opcodes */
169 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
170
171 enum {
172 /* Shifts */
173 OPC_SLL = 0x00 | OPC_SPECIAL,
174 /* NOP is SLL r0, r0, 0 */
175 /* SSNOP is SLL r0, r0, 1 */
176 /* EHB is SLL r0, r0, 3 */
177 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
178 OPC_ROTR = OPC_SRL | (1 << 21),
179 OPC_SRA = 0x03 | OPC_SPECIAL,
180 OPC_SLLV = 0x04 | OPC_SPECIAL,
181 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */
182 OPC_ROTRV = OPC_SRLV | (1 << 6),
183 OPC_SRAV = 0x07 | OPC_SPECIAL,
184 OPC_DSLLV = 0x14 | OPC_SPECIAL,
185 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
186 OPC_DROTRV = OPC_DSRLV | (1 << 6),
187 OPC_DSRAV = 0x17 | OPC_SPECIAL,
188 OPC_DSLL = 0x38 | OPC_SPECIAL,
189 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
190 OPC_DROTR = OPC_DSRL | (1 << 21),
191 OPC_DSRA = 0x3B | OPC_SPECIAL,
192 OPC_DSLL32 = 0x3C | OPC_SPECIAL,
193 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */
194 OPC_DROTR32 = OPC_DSRL32 | (1 << 21),
195 OPC_DSRA32 = 0x3F | OPC_SPECIAL,
196 /* Multiplication / division */
197 OPC_MULT = 0x18 | OPC_SPECIAL,
198 OPC_MULTU = 0x19 | OPC_SPECIAL,
199 OPC_DIV = 0x1A | OPC_SPECIAL,
200 OPC_DIVU = 0x1B | OPC_SPECIAL,
201 OPC_DMULT = 0x1C | OPC_SPECIAL,
202 OPC_DMULTU = 0x1D | OPC_SPECIAL,
203 OPC_DDIV = 0x1E | OPC_SPECIAL,
204 OPC_DDIVU = 0x1F | OPC_SPECIAL,
205
206 /* 2 registers arithmetic / logic */
207 OPC_ADD = 0x20 | OPC_SPECIAL,
208 OPC_ADDU = 0x21 | OPC_SPECIAL,
209 OPC_SUB = 0x22 | OPC_SPECIAL,
210 OPC_SUBU = 0x23 | OPC_SPECIAL,
211 OPC_AND = 0x24 | OPC_SPECIAL,
212 OPC_OR = 0x25 | OPC_SPECIAL,
213 OPC_XOR = 0x26 | OPC_SPECIAL,
214 OPC_NOR = 0x27 | OPC_SPECIAL,
215 OPC_SLT = 0x2A | OPC_SPECIAL,
216 OPC_SLTU = 0x2B | OPC_SPECIAL,
217 OPC_DADD = 0x2C | OPC_SPECIAL,
218 OPC_DADDU = 0x2D | OPC_SPECIAL,
219 OPC_DSUB = 0x2E | OPC_SPECIAL,
220 OPC_DSUBU = 0x2F | OPC_SPECIAL,
221 /* Jumps */
222 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */
223 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
224 /* Traps */
225 OPC_TGE = 0x30 | OPC_SPECIAL,
226 OPC_TGEU = 0x31 | OPC_SPECIAL,
227 OPC_TLT = 0x32 | OPC_SPECIAL,
228 OPC_TLTU = 0x33 | OPC_SPECIAL,
229 OPC_TEQ = 0x34 | OPC_SPECIAL,
230 OPC_TNE = 0x36 | OPC_SPECIAL,
231 /* HI / LO registers load & stores */
232 OPC_MFHI = 0x10 | OPC_SPECIAL,
233 OPC_MTHI = 0x11 | OPC_SPECIAL,
234 OPC_MFLO = 0x12 | OPC_SPECIAL,
235 OPC_MTLO = 0x13 | OPC_SPECIAL,
236 /* Conditional moves */
237 OPC_MOVZ = 0x0A | OPC_SPECIAL,
238 OPC_MOVN = 0x0B | OPC_SPECIAL,
239
240 OPC_SELEQZ = 0x35 | OPC_SPECIAL,
241 OPC_SELNEZ = 0x37 | OPC_SPECIAL,
242
243 OPC_MOVCI = 0x01 | OPC_SPECIAL,
244
245 /* Special */
246 OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */
247 OPC_SYSCALL = 0x0C | OPC_SPECIAL,
248 OPC_BREAK = 0x0D | OPC_SPECIAL,
249 OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */
250 OPC_SYNC = 0x0F | OPC_SPECIAL,
251
252 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
253 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
254 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
255 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
256 };
257
258 /* R6 Multiply and Divide instructions have the same Opcode
259 and function field as legacy OPC_MULT[U]/OPC_DIV[U] */
260 #define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff)))
261
262 enum {
263 R6_OPC_MUL = OPC_MULT | (2 << 6),
264 R6_OPC_MUH = OPC_MULT | (3 << 6),
265 R6_OPC_MULU = OPC_MULTU | (2 << 6),
266 R6_OPC_MUHU = OPC_MULTU | (3 << 6),
267 R6_OPC_DIV = OPC_DIV | (2 << 6),
268 R6_OPC_MOD = OPC_DIV | (3 << 6),
269 R6_OPC_DIVU = OPC_DIVU | (2 << 6),
270 R6_OPC_MODU = OPC_DIVU | (3 << 6),
271
272 R6_OPC_DMUL = OPC_DMULT | (2 << 6),
273 R6_OPC_DMUH = OPC_DMULT | (3 << 6),
274 R6_OPC_DMULU = OPC_DMULTU | (2 << 6),
275 R6_OPC_DMUHU = OPC_DMULTU | (3 << 6),
276 R6_OPC_DDIV = OPC_DDIV | (2 << 6),
277 R6_OPC_DMOD = OPC_DDIV | (3 << 6),
278 R6_OPC_DDIVU = OPC_DDIVU | (2 << 6),
279 R6_OPC_DMODU = OPC_DDIVU | (3 << 6),
280
281 R6_OPC_CLZ = 0x10 | OPC_SPECIAL,
282 R6_OPC_CLO = 0x11 | OPC_SPECIAL,
283 R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
284 R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
285 R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
286
287 OPC_LSA = 0x05 | OPC_SPECIAL,
288 OPC_DLSA = 0x15 | OPC_SPECIAL,
289 };
290
291 /* Multiplication variants of the vr54xx. */
292 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
293
294 enum {
295 OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
296 OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
297 OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
298 OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
299 OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
300 OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
301 OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
302 OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
303 OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
304 OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
305 OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
306 OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
307 OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
308 OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
309 };
310
311 /* REGIMM (rt field) opcodes */
312 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
313
314 enum {
315 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
316 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM,
317 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM,
318 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM,
319 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM,
320 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM,
321 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM,
322 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM,
323 OPC_TGEI = (0x08 << 16) | OPC_REGIMM,
324 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM,
325 OPC_TLTI = (0x0A << 16) | OPC_REGIMM,
326 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
327 OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
328 OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
329 OPC_SIGRIE = (0x17 << 16) | OPC_REGIMM,
330 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
331
332 OPC_DAHI = (0x06 << 16) | OPC_REGIMM,
333 OPC_DATI = (0x1e << 16) | OPC_REGIMM,
334 };
335
336 /* Special2 opcodes */
337 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
338
339 enum {
340 /* Multiply & xxx operations */
341 OPC_MADD = 0x00 | OPC_SPECIAL2,
342 OPC_MADDU = 0x01 | OPC_SPECIAL2,
343 OPC_MUL = 0x02 | OPC_SPECIAL2,
344 OPC_MSUB = 0x04 | OPC_SPECIAL2,
345 OPC_MSUBU = 0x05 | OPC_SPECIAL2,
346 /* Loongson 2F */
347 OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2,
348 OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
349 OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
350 OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
351 OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2,
352 OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2,
353 OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
354 OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
355 OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
356 OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2,
357 OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
358 OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2,
359 /* Misc */
360 OPC_CLZ = 0x20 | OPC_SPECIAL2,
361 OPC_CLO = 0x21 | OPC_SPECIAL2,
362 OPC_DCLZ = 0x24 | OPC_SPECIAL2,
363 OPC_DCLO = 0x25 | OPC_SPECIAL2,
364 /* Special */
365 OPC_SDBBP = 0x3F | OPC_SPECIAL2,
366 };
367
368 /* Special3 opcodes */
369 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
370
371 enum {
372 OPC_EXT = 0x00 | OPC_SPECIAL3,
373 OPC_DEXTM = 0x01 | OPC_SPECIAL3,
374 OPC_DEXTU = 0x02 | OPC_SPECIAL3,
375 OPC_DEXT = 0x03 | OPC_SPECIAL3,
376 OPC_INS = 0x04 | OPC_SPECIAL3,
377 OPC_DINSM = 0x05 | OPC_SPECIAL3,
378 OPC_DINSU = 0x06 | OPC_SPECIAL3,
379 OPC_DINS = 0x07 | OPC_SPECIAL3,
380 OPC_FORK = 0x08 | OPC_SPECIAL3,
381 OPC_YIELD = 0x09 | OPC_SPECIAL3,
382 OPC_BSHFL = 0x20 | OPC_SPECIAL3,
383 OPC_DBSHFL = 0x24 | OPC_SPECIAL3,
384 OPC_RDHWR = 0x3B | OPC_SPECIAL3,
385
386 /* Loongson 2E */
387 OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3,
388 OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
389 OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3,
390 OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
391 OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
392 OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
393 OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3,
394 OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3,
395 OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
396 OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
397 OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
398 OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3,
399
400 /* MIPS DSP Load */
401 OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
402 /* MIPS DSP Arithmetic */
403 OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3,
404 OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3,
405 OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3,
406 OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3,
407 /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
408 /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
409 OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
410 OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3,
411 /* MIPS DSP GPR-Based Shift Sub-class */
412 OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3,
413 OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3,
414 /* MIPS DSP Multiply Sub-class insns */
415 /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */
416 /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */
417 OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3,
418 OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3,
419 /* DSP Bit/Manipulation Sub-class */
420 OPC_INSV_DSP = 0x0C | OPC_SPECIAL3,
421 OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3,
422 /* MIPS DSP Append Sub-class */
423 OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3,
424 OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3,
425 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
426 OPC_EXTR_W_DSP = 0x38 | OPC_SPECIAL3,
427 OPC_DEXTR_W_DSP = 0x3C | OPC_SPECIAL3,
428
429 /* R6 */
430 R6_OPC_PREF = 0x35 | OPC_SPECIAL3,
431 R6_OPC_CACHE = 0x25 | OPC_SPECIAL3,
432 R6_OPC_LL = 0x36 | OPC_SPECIAL3,
433 R6_OPC_SC = 0x26 | OPC_SPECIAL3,
434 R6_OPC_LLD = 0x37 | OPC_SPECIAL3,
435 R6_OPC_SCD = 0x27 | OPC_SPECIAL3,
436 };
437
438 /* BSHFL opcodes */
439 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
440
441 enum {
442 OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
443 OPC_SEB = (0x10 << 6) | OPC_BSHFL,
444 OPC_SEH = (0x18 << 6) | OPC_BSHFL,
445 OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp */
446 OPC_ALIGN_END = (0x0B << 6) | OPC_BSHFL, /* 010.00 to 010.11 */
447 OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 00000 */
448 };
449
450 /* DBSHFL opcodes */
451 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
452
453 enum {
454 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
455 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
456 OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp */
457 OPC_DALIGN_END = (0x0F << 6) | OPC_DBSHFL, /* 01.000 to 01.111 */
458 OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 00000 */
459 };
460
461 /* MIPS DSP REGIMM opcodes */
462 enum {
463 OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM,
464 OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM,
465 };
466
467 #define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
468 /* MIPS DSP Load */
469 enum {
470 OPC_LBUX = (0x06 << 6) | OPC_LX_DSP,
471 OPC_LHX = (0x04 << 6) | OPC_LX_DSP,
472 OPC_LWX = (0x00 << 6) | OPC_LX_DSP,
473 OPC_LDX = (0x08 << 6) | OPC_LX_DSP,
474 };
475
476 #define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
477 enum {
478 /* MIPS DSP Arithmetic Sub-class */
479 OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP,
480 OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP,
481 OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP,
482 OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP,
483 OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP,
484 OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP,
485 OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP,
486 OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP,
487 OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP,
488 OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP,
489 OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP,
490 OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP,
491 OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP,
492 OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP,
493 OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP,
494 OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP,
495 OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP,
496 OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP,
497 /* MIPS DSP Multiply Sub-class insns */
498 OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP,
499 OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP,
500 OPC_MULQ_RS_PH = (0x1F << 6) | OPC_ADDU_QB_DSP,
501 OPC_MULEQ_S_W_PHL = (0x1C << 6) | OPC_ADDU_QB_DSP,
502 OPC_MULEQ_S_W_PHR = (0x1D << 6) | OPC_ADDU_QB_DSP,
503 OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP,
504 };
505
506 #define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
507 #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
508 enum {
509 /* MIPS DSP Arithmetic Sub-class */
510 OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP,
511 OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP,
512 OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP,
513 OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP,
514 OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP,
515 OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP,
516 OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP,
517 OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP,
518 OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP,
519 OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP,
520 OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP,
521 OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP,
522 /* MIPS DSP Multiply Sub-class insns */
523 OPC_MUL_PH = (0x0C << 6) | OPC_ADDUH_QB_DSP,
524 OPC_MUL_S_PH = (0x0E << 6) | OPC_ADDUH_QB_DSP,
525 OPC_MULQ_S_W = (0x16 << 6) | OPC_ADDUH_QB_DSP,
526 OPC_MULQ_RS_W = (0x17 << 6) | OPC_ADDUH_QB_DSP,
527 };
528
529 #define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
530 enum {
531 /* MIPS DSP Arithmetic Sub-class */
532 OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP,
533 OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP,
534 OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP,
535 OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP,
536 OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP,
537 OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP,
538 OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP,
539 OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP,
540 OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP,
541 OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP,
542 OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP,
543 OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP,
544 OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP,
545 /* DSP Bit/Manipulation Sub-class */
546 OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP,
547 OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP,
548 OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP,
549 OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP,
550 OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP,
551 };
552
553 #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
554 enum {
555 /* MIPS DSP Arithmetic Sub-class */
556 OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP,
557 OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP,
558 OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP,
559 OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP,
560 OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP,
561 OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP,
562 OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP,
563 /* DSP Compare-Pick Sub-class */
564 OPC_CMPU_EQ_QB = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP,
565 OPC_CMPU_LT_QB = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP,
566 OPC_CMPU_LE_QB = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP,
567 OPC_CMPGU_EQ_QB = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP,
568 OPC_CMPGU_LT_QB = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP,
569 OPC_CMPGU_LE_QB = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP,
570 OPC_CMPGDU_EQ_QB = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP,
571 OPC_CMPGDU_LT_QB = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP,
572 OPC_CMPGDU_LE_QB = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP,
573 OPC_CMP_EQ_PH = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP,
574 OPC_CMP_LT_PH = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP,
575 OPC_CMP_LE_PH = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP,
576 OPC_PICK_QB = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP,
577 OPC_PICK_PH = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP,
578 OPC_PACKRL_PH = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP,
579 };
580
581 #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
582 enum {
583 /* MIPS DSP GPR-Based Shift Sub-class */
584 OPC_SHLL_QB = (0x00 << 6) | OPC_SHLL_QB_DSP,
585 OPC_SHLLV_QB = (0x02 << 6) | OPC_SHLL_QB_DSP,
586 OPC_SHLL_PH = (0x08 << 6) | OPC_SHLL_QB_DSP,
587 OPC_SHLLV_PH = (0x0A << 6) | OPC_SHLL_QB_DSP,
588 OPC_SHLL_S_PH = (0x0C << 6) | OPC_SHLL_QB_DSP,
589 OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP,
590 OPC_SHLL_S_W = (0x14 << 6) | OPC_SHLL_QB_DSP,
591 OPC_SHLLV_S_W = (0x16 << 6) | OPC_SHLL_QB_DSP,
592 OPC_SHRL_QB = (0x01 << 6) | OPC_SHLL_QB_DSP,
593 OPC_SHRLV_QB = (0x03 << 6) | OPC_SHLL_QB_DSP,
594 OPC_SHRL_PH = (0x19 << 6) | OPC_SHLL_QB_DSP,
595 OPC_SHRLV_PH = (0x1B << 6) | OPC_SHLL_QB_DSP,
596 OPC_SHRA_QB = (0x04 << 6) | OPC_SHLL_QB_DSP,
597 OPC_SHRA_R_QB = (0x05 << 6) | OPC_SHLL_QB_DSP,
598 OPC_SHRAV_QB = (0x06 << 6) | OPC_SHLL_QB_DSP,
599 OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP,
600 OPC_SHRA_PH = (0x09 << 6) | OPC_SHLL_QB_DSP,
601 OPC_SHRAV_PH = (0x0B << 6) | OPC_SHLL_QB_DSP,
602 OPC_SHRA_R_PH = (0x0D << 6) | OPC_SHLL_QB_DSP,
603 OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP,
604 OPC_SHRA_R_W = (0x15 << 6) | OPC_SHLL_QB_DSP,
605 OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP,
606 };
607
608 #define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
609 enum {
610 /* MIPS DSP Multiply Sub-class insns */
611 OPC_DPAU_H_QBL = (0x03 << 6) | OPC_DPA_W_PH_DSP,
612 OPC_DPAU_H_QBR = (0x07 << 6) | OPC_DPA_W_PH_DSP,
613 OPC_DPSU_H_QBL = (0x0B << 6) | OPC_DPA_W_PH_DSP,
614 OPC_DPSU_H_QBR = (0x0F << 6) | OPC_DPA_W_PH_DSP,
615 OPC_DPA_W_PH = (0x00 << 6) | OPC_DPA_W_PH_DSP,
616 OPC_DPAX_W_PH = (0x08 << 6) | OPC_DPA_W_PH_DSP,
617 OPC_DPAQ_S_W_PH = (0x04 << 6) | OPC_DPA_W_PH_DSP,
618 OPC_DPAQX_S_W_PH = (0x18 << 6) | OPC_DPA_W_PH_DSP,
619 OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP,
620 OPC_DPS_W_PH = (0x01 << 6) | OPC_DPA_W_PH_DSP,
621 OPC_DPSX_W_PH = (0x09 << 6) | OPC_DPA_W_PH_DSP,
622 OPC_DPSQ_S_W_PH = (0x05 << 6) | OPC_DPA_W_PH_DSP,
623 OPC_DPSQX_S_W_PH = (0x19 << 6) | OPC_DPA_W_PH_DSP,
624 OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP,
625 OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP,
626 OPC_DPAQ_SA_L_W = (0x0C << 6) | OPC_DPA_W_PH_DSP,
627 OPC_DPSQ_SA_L_W = (0x0D << 6) | OPC_DPA_W_PH_DSP,
628 OPC_MAQ_S_W_PHL = (0x14 << 6) | OPC_DPA_W_PH_DSP,
629 OPC_MAQ_S_W_PHR = (0x16 << 6) | OPC_DPA_W_PH_DSP,
630 OPC_MAQ_SA_W_PHL = (0x10 << 6) | OPC_DPA_W_PH_DSP,
631 OPC_MAQ_SA_W_PHR = (0x12 << 6) | OPC_DPA_W_PH_DSP,
632 OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP,
633 };
634
635 #define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
636 enum {
637 /* DSP Bit/Manipulation Sub-class */
638 OPC_INSV = (0x00 << 6) | OPC_INSV_DSP,
639 };
640
641 #define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
642 enum {
643 /* MIPS DSP Append Sub-class */
644 OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP,
645 OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP,
646 OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP,
647 };
648
649 #define MASK_EXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
650 enum {
651 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
652 OPC_EXTR_W = (0x00 << 6) | OPC_EXTR_W_DSP,
653 OPC_EXTR_R_W = (0x04 << 6) | OPC_EXTR_W_DSP,
654 OPC_EXTR_RS_W = (0x06 << 6) | OPC_EXTR_W_DSP,
655 OPC_EXTR_S_H = (0x0E << 6) | OPC_EXTR_W_DSP,
656 OPC_EXTRV_S_H = (0x0F << 6) | OPC_EXTR_W_DSP,
657 OPC_EXTRV_W = (0x01 << 6) | OPC_EXTR_W_DSP,
658 OPC_EXTRV_R_W = (0x05 << 6) | OPC_EXTR_W_DSP,
659 OPC_EXTRV_RS_W = (0x07 << 6) | OPC_EXTR_W_DSP,
660 OPC_EXTP = (0x02 << 6) | OPC_EXTR_W_DSP,
661 OPC_EXTPV = (0x03 << 6) | OPC_EXTR_W_DSP,
662 OPC_EXTPDP = (0x0A << 6) | OPC_EXTR_W_DSP,
663 OPC_EXTPDPV = (0x0B << 6) | OPC_EXTR_W_DSP,
664 OPC_SHILO = (0x1A << 6) | OPC_EXTR_W_DSP,
665 OPC_SHILOV = (0x1B << 6) | OPC_EXTR_W_DSP,
666 OPC_MTHLIP = (0x1F << 6) | OPC_EXTR_W_DSP,
667 OPC_WRDSP = (0x13 << 6) | OPC_EXTR_W_DSP,
668 OPC_RDDSP = (0x12 << 6) | OPC_EXTR_W_DSP,
669 };
670
671 #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
672 enum {
673 /* MIPS DSP Arithmetic Sub-class */
674 OPC_PRECEQ_L_PWL = (0x14 << 6) | OPC_ABSQ_S_QH_DSP,
675 OPC_PRECEQ_L_PWR = (0x15 << 6) | OPC_ABSQ_S_QH_DSP,
676 OPC_PRECEQ_PW_QHL = (0x0C << 6) | OPC_ABSQ_S_QH_DSP,
677 OPC_PRECEQ_PW_QHR = (0x0D << 6) | OPC_ABSQ_S_QH_DSP,
678 OPC_PRECEQ_PW_QHLA = (0x0E << 6) | OPC_ABSQ_S_QH_DSP,
679 OPC_PRECEQ_PW_QHRA = (0x0F << 6) | OPC_ABSQ_S_QH_DSP,
680 OPC_PRECEQU_QH_OBL = (0x04 << 6) | OPC_ABSQ_S_QH_DSP,
681 OPC_PRECEQU_QH_OBR = (0x05 << 6) | OPC_ABSQ_S_QH_DSP,
682 OPC_PRECEQU_QH_OBLA = (0x06 << 6) | OPC_ABSQ_S_QH_DSP,
683 OPC_PRECEQU_QH_OBRA = (0x07 << 6) | OPC_ABSQ_S_QH_DSP,
684 OPC_PRECEU_QH_OBL = (0x1C << 6) | OPC_ABSQ_S_QH_DSP,
685 OPC_PRECEU_QH_OBR = (0x1D << 6) | OPC_ABSQ_S_QH_DSP,
686 OPC_PRECEU_QH_OBLA = (0x1E << 6) | OPC_ABSQ_S_QH_DSP,
687 OPC_PRECEU_QH_OBRA = (0x1F << 6) | OPC_ABSQ_S_QH_DSP,
688 OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP,
689 OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP,
690 OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP,
691 /* DSP Bit/Manipulation Sub-class */
692 OPC_REPL_OB = (0x02 << 6) | OPC_ABSQ_S_QH_DSP,
693 OPC_REPL_PW = (0x12 << 6) | OPC_ABSQ_S_QH_DSP,
694 OPC_REPL_QH = (0x0A << 6) | OPC_ABSQ_S_QH_DSP,
695 OPC_REPLV_OB = (0x03 << 6) | OPC_ABSQ_S_QH_DSP,
696 OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP,
697 OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP,
698 };
699
700 #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
701 enum {
702 /* MIPS DSP Multiply Sub-class insns */
703 OPC_MULEQ_S_PW_QHL = (0x1C << 6) | OPC_ADDU_OB_DSP,
704 OPC_MULEQ_S_PW_QHR = (0x1D << 6) | OPC_ADDU_OB_DSP,
705 OPC_MULEU_S_QH_OBL = (0x06 << 6) | OPC_ADDU_OB_DSP,
706 OPC_MULEU_S_QH_OBR = (0x07 << 6) | OPC_ADDU_OB_DSP,
707 OPC_MULQ_RS_QH = (0x1F << 6) | OPC_ADDU_OB_DSP,
708 /* MIPS DSP Arithmetic Sub-class */
709 OPC_RADDU_L_OB = (0x14 << 6) | OPC_ADDU_OB_DSP,
710 OPC_SUBQ_PW = (0x13 << 6) | OPC_ADDU_OB_DSP,
711 OPC_SUBQ_S_PW = (0x17 << 6) | OPC_ADDU_OB_DSP,
712 OPC_SUBQ_QH = (0x0B << 6) | OPC_ADDU_OB_DSP,
713 OPC_SUBQ_S_QH = (0x0F << 6) | OPC_ADDU_OB_DSP,
714 OPC_SUBU_OB = (0x01 << 6) | OPC_ADDU_OB_DSP,
715 OPC_SUBU_S_OB = (0x05 << 6) | OPC_ADDU_OB_DSP,
716 OPC_SUBU_QH = (0x09 << 6) | OPC_ADDU_OB_DSP,
717 OPC_SUBU_S_QH = (0x0D << 6) | OPC_ADDU_OB_DSP,
718 OPC_SUBUH_OB = (0x19 << 6) | OPC_ADDU_OB_DSP,
719 OPC_SUBUH_R_OB = (0x1B << 6) | OPC_ADDU_OB_DSP,
720 OPC_ADDQ_PW = (0x12 << 6) | OPC_ADDU_OB_DSP,
721 OPC_ADDQ_S_PW = (0x16 << 6) | OPC_ADDU_OB_DSP,
722 OPC_ADDQ_QH = (0x0A << 6) | OPC_ADDU_OB_DSP,
723 OPC_ADDQ_S_QH = (0x0E << 6) | OPC_ADDU_OB_DSP,
724 OPC_ADDU_OB = (0x00 << 6) | OPC_ADDU_OB_DSP,
725 OPC_ADDU_S_OB = (0x04 << 6) | OPC_ADDU_OB_DSP,
726 OPC_ADDU_QH = (0x08 << 6) | OPC_ADDU_OB_DSP,
727 OPC_ADDU_S_QH = (0x0C << 6) | OPC_ADDU_OB_DSP,
728 OPC_ADDUH_OB = (0x18 << 6) | OPC_ADDU_OB_DSP,
729 OPC_ADDUH_R_OB = (0x1A << 6) | OPC_ADDU_OB_DSP,
730 };
731
732 #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
733 enum {
734 /* DSP Compare-Pick Sub-class */
735 OPC_CMP_EQ_PW = (0x10 << 6) | OPC_CMPU_EQ_OB_DSP,
736 OPC_CMP_LT_PW = (0x11 << 6) | OPC_CMPU_EQ_OB_DSP,
737 OPC_CMP_LE_PW = (0x12 << 6) | OPC_CMPU_EQ_OB_DSP,
738 OPC_CMP_EQ_QH = (0x08 << 6) | OPC_CMPU_EQ_OB_DSP,
739 OPC_CMP_LT_QH = (0x09 << 6) | OPC_CMPU_EQ_OB_DSP,
740 OPC_CMP_LE_QH = (0x0A << 6) | OPC_CMPU_EQ_OB_DSP,
741 OPC_CMPGDU_EQ_OB = (0x18 << 6) | OPC_CMPU_EQ_OB_DSP,
742 OPC_CMPGDU_LT_OB = (0x19 << 6) | OPC_CMPU_EQ_OB_DSP,
743 OPC_CMPGDU_LE_OB = (0x1A << 6) | OPC_CMPU_EQ_OB_DSP,
744 OPC_CMPGU_EQ_OB = (0x04 << 6) | OPC_CMPU_EQ_OB_DSP,
745 OPC_CMPGU_LT_OB = (0x05 << 6) | OPC_CMPU_EQ_OB_DSP,
746 OPC_CMPGU_LE_OB = (0x06 << 6) | OPC_CMPU_EQ_OB_DSP,
747 OPC_CMPU_EQ_OB = (0x00 << 6) | OPC_CMPU_EQ_OB_DSP,
748 OPC_CMPU_LT_OB = (0x01 << 6) | OPC_CMPU_EQ_OB_DSP,
749 OPC_CMPU_LE_OB = (0x02 << 6) | OPC_CMPU_EQ_OB_DSP,
750 OPC_PACKRL_PW = (0x0E << 6) | OPC_CMPU_EQ_OB_DSP,
751 OPC_PICK_OB = (0x03 << 6) | OPC_CMPU_EQ_OB_DSP,
752 OPC_PICK_PW = (0x13 << 6) | OPC_CMPU_EQ_OB_DSP,
753 OPC_PICK_QH = (0x0B << 6) | OPC_CMPU_EQ_OB_DSP,
754 /* MIPS DSP Arithmetic Sub-class */
755 OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP,
756 OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP,
757 OPC_PRECR_SRA_R_QH_PW = (0x1F << 6) | OPC_CMPU_EQ_OB_DSP,
758 OPC_PRECRQ_OB_QH = (0x0C << 6) | OPC_CMPU_EQ_OB_DSP,
759 OPC_PRECRQ_PW_L = (0x1C << 6) | OPC_CMPU_EQ_OB_DSP,
760 OPC_PRECRQ_QH_PW = (0x14 << 6) | OPC_CMPU_EQ_OB_DSP,
761 OPC_PRECRQ_RS_QH_PW = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP,
762 OPC_PRECRQU_S_OB_QH = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP,
763 };
764
765 #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
766 enum {
767 /* DSP Append Sub-class */
768 OPC_DAPPEND = (0x00 << 6) | OPC_DAPPEND_DSP,
769 OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP,
770 OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP,
771 OPC_DBALIGN = (0x10 << 6) | OPC_DAPPEND_DSP,
772 };
773
774 #define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
775 enum {
776 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
777 OPC_DMTHLIP = (0x1F << 6) | OPC_DEXTR_W_DSP,
778 OPC_DSHILO = (0x1A << 6) | OPC_DEXTR_W_DSP,
779 OPC_DEXTP = (0x02 << 6) | OPC_DEXTR_W_DSP,
780 OPC_DEXTPDP = (0x0A << 6) | OPC_DEXTR_W_DSP,
781 OPC_DEXTPDPV = (0x0B << 6) | OPC_DEXTR_W_DSP,
782 OPC_DEXTPV = (0x03 << 6) | OPC_DEXTR_W_DSP,
783 OPC_DEXTR_L = (0x10 << 6) | OPC_DEXTR_W_DSP,
784 OPC_DEXTR_R_L = (0x14 << 6) | OPC_DEXTR_W_DSP,
785 OPC_DEXTR_RS_L = (0x16 << 6) | OPC_DEXTR_W_DSP,
786 OPC_DEXTR_W = (0x00 << 6) | OPC_DEXTR_W_DSP,
787 OPC_DEXTR_R_W = (0x04 << 6) | OPC_DEXTR_W_DSP,
788 OPC_DEXTR_RS_W = (0x06 << 6) | OPC_DEXTR_W_DSP,
789 OPC_DEXTR_S_H = (0x0E << 6) | OPC_DEXTR_W_DSP,
790 OPC_DEXTRV_L = (0x11 << 6) | OPC_DEXTR_W_DSP,
791 OPC_DEXTRV_R_L = (0x15 << 6) | OPC_DEXTR_W_DSP,
792 OPC_DEXTRV_RS_L = (0x17 << 6) | OPC_DEXTR_W_DSP,
793 OPC_DEXTRV_S_H = (0x0F << 6) | OPC_DEXTR_W_DSP,
794 OPC_DEXTRV_W = (0x01 << 6) | OPC_DEXTR_W_DSP,
795 OPC_DEXTRV_R_W = (0x05 << 6) | OPC_DEXTR_W_DSP,
796 OPC_DEXTRV_RS_W = (0x07 << 6) | OPC_DEXTR_W_DSP,
797 OPC_DSHILOV = (0x1B << 6) | OPC_DEXTR_W_DSP,
798 };
799
800 #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
801 enum {
802 /* DSP Bit/Manipulation Sub-class */
803 OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP,
804 };
805
806 #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
807 enum {
808 /* MIPS DSP Multiply Sub-class insns */
809 OPC_DMADD = (0x19 << 6) | OPC_DPAQ_W_QH_DSP,
810 OPC_DMADDU = (0x1D << 6) | OPC_DPAQ_W_QH_DSP,
811 OPC_DMSUB = (0x1B << 6) | OPC_DPAQ_W_QH_DSP,
812 OPC_DMSUBU = (0x1F << 6) | OPC_DPAQ_W_QH_DSP,
813 OPC_DPA_W_QH = (0x00 << 6) | OPC_DPAQ_W_QH_DSP,
814 OPC_DPAQ_S_W_QH = (0x04 << 6) | OPC_DPAQ_W_QH_DSP,
815 OPC_DPAQ_SA_L_PW = (0x0C << 6) | OPC_DPAQ_W_QH_DSP,
816 OPC_DPAU_H_OBL = (0x03 << 6) | OPC_DPAQ_W_QH_DSP,
817 OPC_DPAU_H_OBR = (0x07 << 6) | OPC_DPAQ_W_QH_DSP,
818 OPC_DPS_W_QH = (0x01 << 6) | OPC_DPAQ_W_QH_DSP,
819 OPC_DPSQ_S_W_QH = (0x05 << 6) | OPC_DPAQ_W_QH_DSP,
820 OPC_DPSQ_SA_L_PW = (0x0D << 6) | OPC_DPAQ_W_QH_DSP,
821 OPC_DPSU_H_OBL = (0x0B << 6) | OPC_DPAQ_W_QH_DSP,
822 OPC_DPSU_H_OBR = (0x0F << 6) | OPC_DPAQ_W_QH_DSP,
823 OPC_MAQ_S_L_PWL = (0x1C << 6) | OPC_DPAQ_W_QH_DSP,
824 OPC_MAQ_S_L_PWR = (0x1E << 6) | OPC_DPAQ_W_QH_DSP,
825 OPC_MAQ_S_W_QHLL = (0x14 << 6) | OPC_DPAQ_W_QH_DSP,
826 OPC_MAQ_SA_W_QHLL = (0x10 << 6) | OPC_DPAQ_W_QH_DSP,
827 OPC_MAQ_S_W_QHLR = (0x15 << 6) | OPC_DPAQ_W_QH_DSP,
828 OPC_MAQ_SA_W_QHLR = (0x11 << 6) | OPC_DPAQ_W_QH_DSP,
829 OPC_MAQ_S_W_QHRL = (0x16 << 6) | OPC_DPAQ_W_QH_DSP,
830 OPC_MAQ_SA_W_QHRL = (0x12 << 6) | OPC_DPAQ_W_QH_DSP,
831 OPC_MAQ_S_W_QHRR = (0x17 << 6) | OPC_DPAQ_W_QH_DSP,
832 OPC_MAQ_SA_W_QHRR = (0x13 << 6) | OPC_DPAQ_W_QH_DSP,
833 OPC_MULSAQ_S_L_PW = (0x0E << 6) | OPC_DPAQ_W_QH_DSP,
834 OPC_MULSAQ_S_W_QH = (0x06 << 6) | OPC_DPAQ_W_QH_DSP,
835 };
836
837 #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
838 enum {
839 /* MIPS DSP GPR-Based Shift Sub-class */
840 OPC_SHLL_PW = (0x10 << 6) | OPC_SHLL_OB_DSP,
841 OPC_SHLL_S_PW = (0x14 << 6) | OPC_SHLL_OB_DSP,
842 OPC_SHLLV_OB = (0x02 << 6) | OPC_SHLL_OB_DSP,
843 OPC_SHLLV_PW = (0x12 << 6) | OPC_SHLL_OB_DSP,
844 OPC_SHLLV_S_PW = (0x16 << 6) | OPC_SHLL_OB_DSP,
845 OPC_SHLLV_QH = (0x0A << 6) | OPC_SHLL_OB_DSP,
846 OPC_SHLLV_S_QH = (0x0E << 6) | OPC_SHLL_OB_DSP,
847 OPC_SHRA_PW = (0x11 << 6) | OPC_SHLL_OB_DSP,
848 OPC_SHRA_R_PW = (0x15 << 6) | OPC_SHLL_OB_DSP,
849 OPC_SHRAV_OB = (0x06 << 6) | OPC_SHLL_OB_DSP,
850 OPC_SHRAV_R_OB = (0x07 << 6) | OPC_SHLL_OB_DSP,
851 OPC_SHRAV_PW = (0x13 << 6) | OPC_SHLL_OB_DSP,
852 OPC_SHRAV_R_PW = (0x17 << 6) | OPC_SHLL_OB_DSP,
853 OPC_SHRAV_QH = (0x0B << 6) | OPC_SHLL_OB_DSP,
854 OPC_SHRAV_R_QH = (0x0F << 6) | OPC_SHLL_OB_DSP,
855 OPC_SHRLV_OB = (0x03 << 6) | OPC_SHLL_OB_DSP,
856 OPC_SHRLV_QH = (0x1B << 6) | OPC_SHLL_OB_DSP,
857 OPC_SHLL_OB = (0x00 << 6) | OPC_SHLL_OB_DSP,
858 OPC_SHLL_QH = (0x08 << 6) | OPC_SHLL_OB_DSP,
859 OPC_SHLL_S_QH = (0x0C << 6) | OPC_SHLL_OB_DSP,
860 OPC_SHRA_OB = (0x04 << 6) | OPC_SHLL_OB_DSP,
861 OPC_SHRA_R_OB = (0x05 << 6) | OPC_SHLL_OB_DSP,
862 OPC_SHRA_QH = (0x09 << 6) | OPC_SHLL_OB_DSP,
863 OPC_SHRA_R_QH = (0x0D << 6) | OPC_SHLL_OB_DSP,
864 OPC_SHRL_OB = (0x01 << 6) | OPC_SHLL_OB_DSP,
865 OPC_SHRL_QH = (0x19 << 6) | OPC_SHLL_OB_DSP,
866 };
867
868 /* Coprocessor 0 (rs field) */
869 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
870
871 enum {
872 OPC_MFC0 = (0x00 << 21) | OPC_CP0,
873 OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
874 OPC_MFHC0 = (0x02 << 21) | OPC_CP0,
875 OPC_MTC0 = (0x04 << 21) | OPC_CP0,
876 OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
877 OPC_MTHC0 = (0x06 << 21) | OPC_CP0,
878 OPC_MFTR = (0x08 << 21) | OPC_CP0,
879 OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
880 OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
881 OPC_MTTR = (0x0C << 21) | OPC_CP0,
882 OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
883 OPC_C0 = (0x10 << 21) | OPC_CP0,
884 OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,
885 OPC_C0_LAST = (0x1F << 21) | OPC_CP0,
886 };
887
888 /* MFMC0 opcodes */
889 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
890
891 enum {
892 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
893 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
894 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0,
895 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0,
896 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
897 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
898 OPC_DVP = 0x04 | (0 << 3) | (1 << 5) | (0 << 11) | OPC_MFMC0,
899 OPC_EVP = 0x04 | (0 << 3) | (0 << 5) | (0 << 11) | OPC_MFMC0,
900 };
901
902 /* Coprocessor 0 (with rs == C0) */
903 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
904
905 enum {
906 OPC_TLBR = 0x01 | OPC_C0,
907 OPC_TLBWI = 0x02 | OPC_C0,
908 OPC_TLBINV = 0x03 | OPC_C0,
909 OPC_TLBINVF = 0x04 | OPC_C0,
910 OPC_TLBWR = 0x06 | OPC_C0,
911 OPC_TLBP = 0x08 | OPC_C0,
912 OPC_RFE = 0x10 | OPC_C0,
913 OPC_ERET = 0x18 | OPC_C0,
914 OPC_DERET = 0x1F | OPC_C0,
915 OPC_WAIT = 0x20 | OPC_C0,
916 };
917
918 /* Coprocessor 1 (rs field) */
919 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
920
921 /* Values for the fmt field in FP instructions */
922 enum {
923 /* 0 - 15 are reserved */
924 FMT_S = 16, /* single fp */
925 FMT_D = 17, /* double fp */
926 FMT_E = 18, /* extended fp */
927 FMT_Q = 19, /* quad fp */
928 FMT_W = 20, /* 32-bit fixed */
929 FMT_L = 21, /* 64-bit fixed */
930 FMT_PS = 22, /* paired single fp */
931 /* 23 - 31 are reserved */
932 };
933
934 enum {
935 OPC_MFC1 = (0x00 << 21) | OPC_CP1,
936 OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
937 OPC_CFC1 = (0x02 << 21) | OPC_CP1,
938 OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
939 OPC_MTC1 = (0x04 << 21) | OPC_CP1,
940 OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
941 OPC_CTC1 = (0x06 << 21) | OPC_CP1,
942 OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
943 OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
944 OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
945 OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
946 OPC_BZ_V = (0x0B << 21) | OPC_CP1,
947 OPC_BNZ_V = (0x0F << 21) | OPC_CP1,
948 OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
949 OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
950 OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
951 OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1,
952 OPC_W_FMT = (FMT_W << 21) | OPC_CP1,
953 OPC_L_FMT = (FMT_L << 21) | OPC_CP1,
954 OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
955 OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
956 OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
957 OPC_BZ_B = (0x18 << 21) | OPC_CP1,
958 OPC_BZ_H = (0x19 << 21) | OPC_CP1,
959 OPC_BZ_W = (0x1A << 21) | OPC_CP1,
960 OPC_BZ_D = (0x1B << 21) | OPC_CP1,
961 OPC_BNZ_B = (0x1C << 21) | OPC_CP1,
962 OPC_BNZ_H = (0x1D << 21) | OPC_CP1,
963 OPC_BNZ_W = (0x1E << 21) | OPC_CP1,
964 OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
965 };
966
967 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
968 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
969
970 enum {
971 OPC_BC1F = (0x00 << 16) | OPC_BC1,
972 OPC_BC1T = (0x01 << 16) | OPC_BC1,
973 OPC_BC1FL = (0x02 << 16) | OPC_BC1,
974 OPC_BC1TL = (0x03 << 16) | OPC_BC1,
975 };
976
977 enum {
978 OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2,
979 OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2,
980 };
981
982 enum {
983 OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4,
984 OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
985 };
986
987 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
988
989 enum {
990 OPC_MFC2 = (0x00 << 21) | OPC_CP2,
991 OPC_DMFC2 = (0x01 << 21) | OPC_CP2,
992 OPC_CFC2 = (0x02 << 21) | OPC_CP2,
993 OPC_MFHC2 = (0x03 << 21) | OPC_CP2,
994 OPC_MTC2 = (0x04 << 21) | OPC_CP2,
995 OPC_DMTC2 = (0x05 << 21) | OPC_CP2,
996 OPC_CTC2 = (0x06 << 21) | OPC_CP2,
997 OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
998 OPC_BC2 = (0x08 << 21) | OPC_CP2,
999 OPC_BC2EQZ = (0x09 << 21) | OPC_CP2,
1000 OPC_BC2NEZ = (0x0D << 21) | OPC_CP2,
1001 };
1002
1003 #define MASK_LMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
1004
1005 enum {
1006 OPC_PADDSH = (24 << 21) | (0x00) | OPC_CP2,
1007 OPC_PADDUSH = (25 << 21) | (0x00) | OPC_CP2,
1008 OPC_PADDH = (26 << 21) | (0x00) | OPC_CP2,
1009 OPC_PADDW = (27 << 21) | (0x00) | OPC_CP2,
1010 OPC_PADDSB = (28 << 21) | (0x00) | OPC_CP2,
1011 OPC_PADDUSB = (29 << 21) | (0x00) | OPC_CP2,
1012 OPC_PADDB = (30 << 21) | (0x00) | OPC_CP2,
1013 OPC_PADDD = (31 << 21) | (0x00) | OPC_CP2,
1014
1015 OPC_PSUBSH = (24 << 21) | (0x01) | OPC_CP2,
1016 OPC_PSUBUSH = (25 << 21) | (0x01) | OPC_CP2,
1017 OPC_PSUBH = (26 << 21) | (0x01) | OPC_CP2,
1018 OPC_PSUBW = (27 << 21) | (0x01) | OPC_CP2,
1019 OPC_PSUBSB = (28 << 21) | (0x01) | OPC_CP2,
1020 OPC_PSUBUSB = (29 << 21) | (0x01) | OPC_CP2,
1021 OPC_PSUBB = (30 << 21) | (0x01) | OPC_CP2,
1022 OPC_PSUBD = (31 << 21) | (0x01) | OPC_CP2,
1023
1024 OPC_PSHUFH = (24 << 21) | (0x02) | OPC_CP2,
1025 OPC_PACKSSWH = (25 << 21) | (0x02) | OPC_CP2,
1026 OPC_PACKSSHB = (26 << 21) | (0x02) | OPC_CP2,
1027 OPC_PACKUSHB = (27 << 21) | (0x02) | OPC_CP2,
1028 OPC_XOR_CP2 = (28 << 21) | (0x02) | OPC_CP2,
1029 OPC_NOR_CP2 = (29 << 21) | (0x02) | OPC_CP2,
1030 OPC_AND_CP2 = (30 << 21) | (0x02) | OPC_CP2,
1031 OPC_PANDN = (31 << 21) | (0x02) | OPC_CP2,
1032
1033 OPC_PUNPCKLHW = (24 << 21) | (0x03) | OPC_CP2,
1034 OPC_PUNPCKHHW = (25 << 21) | (0x03) | OPC_CP2,
1035 OPC_PUNPCKLBH = (26 << 21) | (0x03) | OPC_CP2,
1036 OPC_PUNPCKHBH = (27 << 21) | (0x03) | OPC_CP2,
1037 OPC_PINSRH_0 = (28 << 21) | (0x03) | OPC_CP2,
1038 OPC_PINSRH_1 = (29 << 21) | (0x03) | OPC_CP2,
1039 OPC_PINSRH_2 = (30 << 21) | (0x03) | OPC_CP2,
1040 OPC_PINSRH_3 = (31 << 21) | (0x03) | OPC_CP2,
1041
1042 OPC_PAVGH = (24 << 21) | (0x08) | OPC_CP2,
1043 OPC_PAVGB = (25 << 21) | (0x08) | OPC_CP2,
1044 OPC_PMAXSH = (26 << 21) | (0x08) | OPC_CP2,
1045 OPC_PMINSH = (27 << 21) | (0x08) | OPC_CP2,
1046 OPC_PMAXUB = (28 << 21) | (0x08) | OPC_CP2,
1047 OPC_PMINUB = (29 << 21) | (0x08) | OPC_CP2,
1048
1049 OPC_PCMPEQW = (24 << 21) | (0x09) | OPC_CP2,
1050 OPC_PCMPGTW = (25 << 21) | (0x09) | OPC_CP2,
1051 OPC_PCMPEQH = (26 << 21) | (0x09) | OPC_CP2,
1052 OPC_PCMPGTH = (27 << 21) | (0x09) | OPC_CP2,
1053 OPC_PCMPEQB = (28 << 21) | (0x09) | OPC_CP2,
1054 OPC_PCMPGTB = (29 << 21) | (0x09) | OPC_CP2,
1055
1056 OPC_PSLLW = (24 << 21) | (0x0A) | OPC_CP2,
1057 OPC_PSLLH = (25 << 21) | (0x0A) | OPC_CP2,
1058 OPC_PMULLH = (26 << 21) | (0x0A) | OPC_CP2,
1059 OPC_PMULHH = (27 << 21) | (0x0A) | OPC_CP2,
1060 OPC_PMULUW = (28 << 21) | (0x0A) | OPC_CP2,
1061 OPC_PMULHUH = (29 << 21) | (0x0A) | OPC_CP2,
1062
1063 OPC_PSRLW = (24 << 21) | (0x0B) | OPC_CP2,
1064 OPC_PSRLH = (25 << 21) | (0x0B) | OPC_CP2,
1065 OPC_PSRAW = (26 << 21) | (0x0B) | OPC_CP2,
1066 OPC_PSRAH = (27 << 21) | (0x0B) | OPC_CP2,
1067 OPC_PUNPCKLWD = (28 << 21) | (0x0B) | OPC_CP2,
1068 OPC_PUNPCKHWD = (29 << 21) | (0x0B) | OPC_CP2,
1069
1070 OPC_ADDU_CP2 = (24 << 21) | (0x0C) | OPC_CP2,
1071 OPC_OR_CP2 = (25 << 21) | (0x0C) | OPC_CP2,
1072 OPC_ADD_CP2 = (26 << 21) | (0x0C) | OPC_CP2,
1073 OPC_DADD_CP2 = (27 << 21) | (0x0C) | OPC_CP2,
1074 OPC_SEQU_CP2 = (28 << 21) | (0x0C) | OPC_CP2,
1075 OPC_SEQ_CP2 = (29 << 21) | (0x0C) | OPC_CP2,
1076
1077 OPC_SUBU_CP2 = (24 << 21) | (0x0D) | OPC_CP2,
1078 OPC_PASUBUB = (25 << 21) | (0x0D) | OPC_CP2,
1079 OPC_SUB_CP2 = (26 << 21) | (0x0D) | OPC_CP2,
1080 OPC_DSUB_CP2 = (27 << 21) | (0x0D) | OPC_CP2,
1081 OPC_SLTU_CP2 = (28 << 21) | (0x0D) | OPC_CP2,
1082 OPC_SLT_CP2 = (29 << 21) | (0x0D) | OPC_CP2,
1083
1084 OPC_SLL_CP2 = (24 << 21) | (0x0E) | OPC_CP2,
1085 OPC_DSLL_CP2 = (25 << 21) | (0x0E) | OPC_CP2,
1086 OPC_PEXTRH = (26 << 21) | (0x0E) | OPC_CP2,
1087 OPC_PMADDHW = (27 << 21) | (0x0E) | OPC_CP2,
1088 OPC_SLEU_CP2 = (28 << 21) | (0x0E) | OPC_CP2,
1089 OPC_SLE_CP2 = (29 << 21) | (0x0E) | OPC_CP2,
1090
1091 OPC_SRL_CP2 = (24 << 21) | (0x0F) | OPC_CP2,
1092 OPC_DSRL_CP2 = (25 << 21) | (0x0F) | OPC_CP2,
1093 OPC_SRA_CP2 = (26 << 21) | (0x0F) | OPC_CP2,
1094 OPC_DSRA_CP2 = (27 << 21) | (0x0F) | OPC_CP2,
1095 OPC_BIADD = (28 << 21) | (0x0F) | OPC_CP2,
1096 OPC_PMOVMSKB = (29 << 21) | (0x0F) | OPC_CP2,
1097 };
1098
1099
1100 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
1101
1102 enum {
1103 OPC_LWXC1 = 0x00 | OPC_CP3,
1104 OPC_LDXC1 = 0x01 | OPC_CP3,
1105 OPC_LUXC1 = 0x05 | OPC_CP3,
1106 OPC_SWXC1 = 0x08 | OPC_CP3,
1107 OPC_SDXC1 = 0x09 | OPC_CP3,
1108 OPC_SUXC1 = 0x0D | OPC_CP3,
1109 OPC_PREFX = 0x0F | OPC_CP3,
1110 OPC_ALNV_PS = 0x1E | OPC_CP3,
1111 OPC_MADD_S = 0x20 | OPC_CP3,
1112 OPC_MADD_D = 0x21 | OPC_CP3,
1113 OPC_MADD_PS = 0x26 | OPC_CP3,
1114 OPC_MSUB_S = 0x28 | OPC_CP3,
1115 OPC_MSUB_D = 0x29 | OPC_CP3,
1116 OPC_MSUB_PS = 0x2E | OPC_CP3,
1117 OPC_NMADD_S = 0x30 | OPC_CP3,
1118 OPC_NMADD_D = 0x31 | OPC_CP3,
1119 OPC_NMADD_PS= 0x36 | OPC_CP3,
1120 OPC_NMSUB_S = 0x38 | OPC_CP3,
1121 OPC_NMSUB_D = 0x39 | OPC_CP3,
1122 OPC_NMSUB_PS= 0x3E | OPC_CP3,
1123 };
1124
1125 /* MSA Opcodes */
1126 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
1127 enum {
1128 OPC_MSA_I8_00 = 0x00 | OPC_MSA,
1129 OPC_MSA_I8_01 = 0x01 | OPC_MSA,
1130 OPC_MSA_I8_02 = 0x02 | OPC_MSA,
1131 OPC_MSA_I5_06 = 0x06 | OPC_MSA,
1132 OPC_MSA_I5_07 = 0x07 | OPC_MSA,
1133 OPC_MSA_BIT_09 = 0x09 | OPC_MSA,
1134 OPC_MSA_BIT_0A = 0x0A | OPC_MSA,
1135 OPC_MSA_3R_0D = 0x0D | OPC_MSA,
1136 OPC_MSA_3R_0E = 0x0E | OPC_MSA,
1137 OPC_MSA_3R_0F = 0x0F | OPC_MSA,
1138 OPC_MSA_3R_10 = 0x10 | OPC_MSA,
1139 OPC_MSA_3R_11 = 0x11 | OPC_MSA,
1140 OPC_MSA_3R_12 = 0x12 | OPC_MSA,
1141 OPC_MSA_3R_13 = 0x13 | OPC_MSA,
1142 OPC_MSA_3R_14 = 0x14 | OPC_MSA,
1143 OPC_MSA_3R_15 = 0x15 | OPC_MSA,
1144 OPC_MSA_ELM = 0x19 | OPC_MSA,
1145 OPC_MSA_3RF_1A = 0x1A | OPC_MSA,
1146 OPC_MSA_3RF_1B = 0x1B | OPC_MSA,
1147 OPC_MSA_3RF_1C = 0x1C | OPC_MSA,
1148 OPC_MSA_VEC = 0x1E | OPC_MSA,
1149
1150 /* MI10 instruction */
1151 OPC_LD_B = (0x20) | OPC_MSA,
1152 OPC_LD_H = (0x21) | OPC_MSA,
1153 OPC_LD_W = (0x22) | OPC_MSA,
1154 OPC_LD_D = (0x23) | OPC_MSA,
1155 OPC_ST_B = (0x24) | OPC_MSA,
1156 OPC_ST_H = (0x25) | OPC_MSA,
1157 OPC_ST_W = (0x26) | OPC_MSA,
1158 OPC_ST_D = (0x27) | OPC_MSA,
1159 };
1160
1161 enum {
1162 /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
1163 OPC_ADDVI_df = (0x0 << 23) | OPC_MSA_I5_06,
1164 OPC_CEQI_df = (0x0 << 23) | OPC_MSA_I5_07,
1165 OPC_SUBVI_df = (0x1 << 23) | OPC_MSA_I5_06,
1166 OPC_MAXI_S_df = (0x2 << 23) | OPC_MSA_I5_06,
1167 OPC_CLTI_S_df = (0x2 << 23) | OPC_MSA_I5_07,
1168 OPC_MAXI_U_df = (0x3 << 23) | OPC_MSA_I5_06,
1169 OPC_CLTI_U_df = (0x3 << 23) | OPC_MSA_I5_07,
1170 OPC_MINI_S_df = (0x4 << 23) | OPC_MSA_I5_06,
1171 OPC_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07,
1172 OPC_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06,
1173 OPC_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07,
1174 OPC_LDI_df = (0x6 << 23) | OPC_MSA_I5_07,
1175
1176 /* I8 instruction */
1177 OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
1178 OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
1179 OPC_SHF_B = (0x0 << 24) | OPC_MSA_I8_02,
1180 OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00,
1181 OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01,
1182 OPC_SHF_H = (0x1 << 24) | OPC_MSA_I8_02,
1183 OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00,
1184 OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
1185 OPC_SHF_W = (0x2 << 24) | OPC_MSA_I8_02,
1186 OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00,
1187
1188 /* VEC/2R/2RF instruction */
1189 OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC,
1190 OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC,
1191 OPC_NOR_V = (0x02 << 21) | OPC_MSA_VEC,
1192 OPC_XOR_V = (0x03 << 21) | OPC_MSA_VEC,
1193 OPC_BMNZ_V = (0x04 << 21) | OPC_MSA_VEC,
1194 OPC_BMZ_V = (0x05 << 21) | OPC_MSA_VEC,
1195 OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC,
1196
1197 OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
1198 OPC_MSA_2RF = (0x19 << 21) | OPC_MSA_VEC,
1199
1200 /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
1201 OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
1202 OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
1203 OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
1204 OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
1205
1206 /* 2RF instruction df(bit 16) = _w, _d */
1207 OPC_FCLASS_df = (0x00 << 17) | OPC_MSA_2RF,
1208 OPC_FTRUNC_S_df = (0x01 << 17) | OPC_MSA_2RF,
1209 OPC_FTRUNC_U_df = (0x02 << 17) | OPC_MSA_2RF,
1210 OPC_FSQRT_df = (0x03 << 17) | OPC_MSA_2RF,
1211 OPC_FRSQRT_df = (0x04 << 17) | OPC_MSA_2RF,
1212 OPC_FRCP_df = (0x05 << 17) | OPC_MSA_2RF,
1213 OPC_FRINT_df = (0x06 << 17) | OPC_MSA_2RF,
1214 OPC_FLOG2_df = (0x07 << 17) | OPC_MSA_2RF,
1215 OPC_FEXUPL_df = (0x08 << 17) | OPC_MSA_2RF,
1216 OPC_FEXUPR_df = (0x09 << 17) | OPC_MSA_2RF,
1217 OPC_FFQL_df = (0x0A << 17) | OPC_MSA_2RF,
1218 OPC_FFQR_df = (0x0B << 17) | OPC_MSA_2RF,
1219 OPC_FTINT_S_df = (0x0C << 17) | OPC_MSA_2RF,
1220 OPC_FTINT_U_df = (0x0D << 17) | OPC_MSA_2RF,
1221 OPC_FFINT_S_df = (0x0E << 17) | OPC_MSA_2RF,
1222 OPC_FFINT_U_df = (0x0F << 17) | OPC_MSA_2RF,
1223
1224 /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
1225 OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
1226 OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
1227 OPC_CEQ_df = (0x0 << 23) | OPC_MSA_3R_0F,
1228 OPC_ADD_A_df = (0x0 << 23) | OPC_MSA_3R_10,
1229 OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
1230 OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
1231 OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13,
1232 OPC_SLD_df = (0x0 << 23) | OPC_MSA_3R_14,
1233 OPC_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15,
1234 OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
1235 OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
1236 OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
1237 OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
1238 OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
1239 OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13,
1240 OPC_SPLAT_df = (0x1 << 23) | OPC_MSA_3R_14,
1241 OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
1242 OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
1243 OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
1244 OPC_CLT_S_df = (0x2 << 23) | OPC_MSA_3R_0F,
1245 OPC_ADDS_S_df = (0x2 << 23) | OPC_MSA_3R_10,
1246 OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
1247 OPC_MSUBV_df = (0x2 << 23) | OPC_MSA_3R_12,
1248 OPC_DPADD_S_df = (0x2 << 23) | OPC_MSA_3R_13,
1249 OPC_PCKEV_df = (0x2 << 23) | OPC_MSA_3R_14,
1250 OPC_SRLR_df = (0x2 << 23) | OPC_MSA_3R_15,
1251 OPC_BCLR_df = (0x3 << 23) | OPC_MSA_3R_0D,
1252 OPC_MAX_U_df = (0x3 << 23) | OPC_MSA_3R_0E,
1253 OPC_CLT_U_df = (0x3 << 23) | OPC_MSA_3R_0F,
1254 OPC_ADDS_U_df = (0x3 << 23) | OPC_MSA_3R_10,
1255 OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
1256 OPC_DPADD_U_df = (0x3 << 23) | OPC_MSA_3R_13,
1257 OPC_PCKOD_df = (0x3 << 23) | OPC_MSA_3R_14,
1258 OPC_BSET_df = (0x4 << 23) | OPC_MSA_3R_0D,
1259 OPC_MIN_S_df = (0x4 << 23) | OPC_MSA_3R_0E,
1260 OPC_CLE_S_df = (0x4 << 23) | OPC_MSA_3R_0F,
1261 OPC_AVE_S_df = (0x4 << 23) | OPC_MSA_3R_10,
1262 OPC_ASUB_S_df = (0x4 << 23) | OPC_MSA_3R_11,
1263 OPC_DIV_S_df = (0x4 << 23) | OPC_MSA_3R_12,
1264 OPC_DPSUB_S_df = (0x4 << 23) | OPC_MSA_3R_13,
1265 OPC_ILVL_df = (0x4 << 23) | OPC_MSA_3R_14,
1266 OPC_HADD_S_df = (0x4 << 23) | OPC_MSA_3R_15,
1267 OPC_BNEG_df = (0x5 << 23) | OPC_MSA_3R_0D,
1268 OPC_MIN_U_df = (0x5 << 23) | OPC_MSA_3R_0E,
1269 OPC_CLE_U_df = (0x5 << 23) | OPC_MSA_3R_0F,
1270 OPC_AVE_U_df = (0x5 << 23) | OPC_MSA_3R_10,
1271 OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
1272 OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
1273 OPC_DPSUB_U_df = (0x5 << 23) | OPC_MSA_3R_13,
1274 OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
1275 OPC_HADD_U_df = (0x5 << 23) | OPC_MSA_3R_15,
1276 OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D,
1277 OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
1278 OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
1279 OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
1280 OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
1281 OPC_HSUB_S_df = (0x6 << 23) | OPC_MSA_3R_15,
1282 OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D,
1283 OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
1284 OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
1285 OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
1286 OPC_ILVOD_df = (0x7 << 23) | OPC_MSA_3R_14,
1287 OPC_HSUB_U_df = (0x7 << 23) | OPC_MSA_3R_15,
1288
1289 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
1290 OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1291 OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
1292 OPC_SPLATI_df = (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1293 OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
1294 OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1295 OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
1296 OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1297 OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1298 OPC_INSVE_df = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1299
1300 /* 3RF instruction _df(bit 21) = _w, _d */
1301 OPC_FCAF_df = (0x0 << 22) | OPC_MSA_3RF_1A,
1302 OPC_FADD_df = (0x0 << 22) | OPC_MSA_3RF_1B,
1303 OPC_FCUN_df = (0x1 << 22) | OPC_MSA_3RF_1A,
1304 OPC_FSUB_df = (0x1 << 22) | OPC_MSA_3RF_1B,
1305 OPC_FCOR_df = (0x1 << 22) | OPC_MSA_3RF_1C,
1306 OPC_FCEQ_df = (0x2 << 22) | OPC_MSA_3RF_1A,
1307 OPC_FMUL_df = (0x2 << 22) | OPC_MSA_3RF_1B,
1308 OPC_FCUNE_df = (0x2 << 22) | OPC_MSA_3RF_1C,
1309 OPC_FCUEQ_df = (0x3 << 22) | OPC_MSA_3RF_1A,
1310 OPC_FDIV_df = (0x3 << 22) | OPC_MSA_3RF_1B,
1311 OPC_FCNE_df = (0x3 << 22) | OPC_MSA_3RF_1C,
1312 OPC_FCLT_df = (0x4 << 22) | OPC_MSA_3RF_1A,
1313 OPC_FMADD_df = (0x4 << 22) | OPC_MSA_3RF_1B,
1314 OPC_MUL_Q_df = (0x4 << 22) | OPC_MSA_3RF_1C,
1315 OPC_FCULT_df = (0x5 << 22) | OPC_MSA_3RF_1A,
1316 OPC_FMSUB_df = (0x5 << 22) | OPC_MSA_3RF_1B,
1317 OPC_MADD_Q_df = (0x5 << 22) | OPC_MSA_3RF_1C,
1318 OPC_FCLE_df = (0x6 << 22) | OPC_MSA_3RF_1A,
1319 OPC_MSUB_Q_df = (0x6 << 22) | OPC_MSA_3RF_1C,
1320 OPC_FCULE_df = (0x7 << 22) | OPC_MSA_3RF_1A,
1321 OPC_FEXP2_df = (0x7 << 22) | OPC_MSA_3RF_1B,
1322 OPC_FSAF_df = (0x8 << 22) | OPC_MSA_3RF_1A,
1323 OPC_FEXDO_df = (0x8 << 22) | OPC_MSA_3RF_1B,
1324 OPC_FSUN_df = (0x9 << 22) | OPC_MSA_3RF_1A,
1325 OPC_FSOR_df = (0x9 << 22) | OPC_MSA_3RF_1C,
1326 OPC_FSEQ_df = (0xA << 22) | OPC_MSA_3RF_1A,
1327 OPC_FTQ_df = (0xA << 22) | OPC_MSA_3RF_1B,
1328 OPC_FSUNE_df = (0xA << 22) | OPC_MSA_3RF_1C,
1329 OPC_FSUEQ_df = (0xB << 22) | OPC_MSA_3RF_1A,
1330 OPC_FSNE_df = (0xB << 22) | OPC_MSA_3RF_1C,
1331 OPC_FSLT_df = (0xC << 22) | OPC_MSA_3RF_1A,
1332 OPC_FMIN_df = (0xC << 22) | OPC_MSA_3RF_1B,
1333 OPC_MULR_Q_df = (0xC << 22) | OPC_MSA_3RF_1C,
1334 OPC_FSULT_df = (0xD << 22) | OPC_MSA_3RF_1A,
1335 OPC_FMIN_A_df = (0xD << 22) | OPC_MSA_3RF_1B,
1336 OPC_MADDR_Q_df = (0xD << 22) | OPC_MSA_3RF_1C,
1337 OPC_FSLE_df = (0xE << 22) | OPC_MSA_3RF_1A,
1338 OPC_FMAX_df = (0xE << 22) | OPC_MSA_3RF_1B,
1339 OPC_MSUBR_Q_df = (0xE << 22) | OPC_MSA_3RF_1C,
1340 OPC_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A,
1341 OPC_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B,
1342
1343 /* BIT instruction df(bits 22..16) = _B _H _W _D */
1344 OPC_SLLI_df = (0x0 << 23) | OPC_MSA_BIT_09,
1345 OPC_SAT_S_df = (0x0 << 23) | OPC_MSA_BIT_0A,
1346 OPC_SRAI_df = (0x1 << 23) | OPC_MSA_BIT_09,
1347 OPC_SAT_U_df = (0x1 << 23) | OPC_MSA_BIT_0A,
1348 OPC_SRLI_df = (0x2 << 23) | OPC_MSA_BIT_09,
1349 OPC_SRARI_df = (0x2 << 23) | OPC_MSA_BIT_0A,
1350 OPC_BCLRI_df = (0x3 << 23) | OPC_MSA_BIT_09,
1351 OPC_SRLRI_df = (0x3 << 23) | OPC_MSA_BIT_0A,
1352 OPC_BSETI_df = (0x4 << 23) | OPC_MSA_BIT_09,
1353 OPC_BNEGI_df = (0x5 << 23) | OPC_MSA_BIT_09,
1354 OPC_BINSLI_df = (0x6 << 23) | OPC_MSA_BIT_09,
1355 OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
1356 };
1357
1358 /* global register indices */
1359 static TCGv_env cpu_env;
1360 static TCGv cpu_gpr[32], cpu_PC;
1361 static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
1362 static TCGv cpu_dspctrl, btarget, bcond;
1363 static TCGv_i32 hflags;
1364 static TCGv_i32 fpu_fcr0, fpu_fcr31;
1365 static TCGv_i64 fpu_f64[32];
1366 static TCGv_i64 msa_wr_d[64];
1367
1368 #include "exec/gen-icount.h"
1369
1370 #define gen_helper_0e0i(name, arg) do { \
1371 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
1372 gen_helper_##name(cpu_env, helper_tmp); \
1373 tcg_temp_free_i32(helper_tmp); \
1374 } while(0)
1375
1376 #define gen_helper_0e1i(name, arg1, arg2) do { \
1377 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
1378 gen_helper_##name(cpu_env, arg1, helper_tmp); \
1379 tcg_temp_free_i32(helper_tmp); \
1380 } while(0)
1381
1382 #define gen_helper_1e0i(name, ret, arg1) do { \
1383 TCGv_i32 helper_tmp = tcg_const_i32(arg1); \
1384 gen_helper_##name(ret, cpu_env, helper_tmp); \
1385 tcg_temp_free_i32(helper_tmp); \
1386 } while(0)
1387
1388 #define gen_helper_1e1i(name, ret, arg1, arg2) do { \
1389 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
1390 gen_helper_##name(ret, cpu_env, arg1, helper_tmp); \
1391 tcg_temp_free_i32(helper_tmp); \
1392 } while(0)
1393
1394 #define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
1395 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
1396 gen_helper_##name(cpu_env, arg1, arg2, helper_tmp); \
1397 tcg_temp_free_i32(helper_tmp); \
1398 } while(0)
1399
1400 #define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do { \
1401 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
1402 gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp); \
1403 tcg_temp_free_i32(helper_tmp); \
1404 } while(0)
1405
1406 #define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do { \
1407 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
1408 gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp); \
1409 tcg_temp_free_i32(helper_tmp); \
1410 } while(0)
1411
1412 typedef struct DisasContext {
1413 struct TranslationBlock *tb;
1414 target_ulong pc, saved_pc;
1415 uint32_t opcode;
1416 int singlestep_enabled;
1417 int insn_flags;
1418 int32_t CP0_Config1;
1419 /* Routine used to access memory */
1420 int mem_idx;
1421 TCGMemOp default_tcg_memop_mask;
1422 uint32_t hflags, saved_hflags;
1423 int bstate;
1424 target_ulong btarget;
1425 bool ulri;
1426 int kscrexist;
1427 bool rxi;
1428 int ie;
1429 bool bi;
1430 bool bp;
1431 uint64_t PAMask;
1432 bool mvh;
1433 int CP0_LLAddr_shift;
1434 bool ps;
1435 bool vp;
1436 bool cmgcr;
1437 bool mrp;
1438 bool nan2008;
1439 bool abs2008;
1440 } DisasContext;
1441
1442 enum {
1443 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
1444 * exception condition */
1445 BS_STOP = 1, /* We want to stop translation for any reason */
1446 BS_BRANCH = 2, /* We reached a branch condition */
1447 BS_EXCP = 3, /* We reached an exception condition */
1448 };
1449
1450 static const char * const regnames[] = {
1451 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1452 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
1453 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1454 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
1455 };
1456
1457 static const char * const regnames_HI[] = {
1458 "HI0", "HI1", "HI2", "HI3",
1459 };
1460
1461 static const char * const regnames_LO[] = {
1462 "LO0", "LO1", "LO2", "LO3",
1463 };
1464
1465 static const char * const fregnames[] = {
1466 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1467 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1468 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1469 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1470 };
1471
1472 static const char * const msaregnames[] = {
1473 "w0.d0", "w0.d1", "w1.d0", "w1.d1",
1474 "w2.d0", "w2.d1", "w3.d0", "w3.d1",
1475 "w4.d0", "w4.d1", "w5.d0", "w5.d1",
1476 "w6.d0", "w6.d1", "w7.d0", "w7.d1",
1477 "w8.d0", "w8.d1", "w9.d0", "w9.d1",
1478 "w10.d0", "w10.d1", "w11.d0", "w11.d1",
1479 "w12.d0", "w12.d1", "w13.d0", "w13.d1",
1480 "w14.d0", "w14.d1", "w15.d0", "w15.d1",
1481 "w16.d0", "w16.d1", "w17.d0", "w17.d1",
1482 "w18.d0", "w18.d1", "w19.d0", "w19.d1",
1483 "w20.d0", "w20.d1", "w21.d0", "w21.d1",
1484 "w22.d0", "w22.d1", "w23.d0", "w23.d1",
1485 "w24.d0", "w24.d1", "w25.d0", "w25.d1",
1486 "w26.d0", "w26.d1", "w27.d0", "w27.d1",
1487 "w28.d0", "w28.d1", "w29.d0", "w29.d1",
1488 "w30.d0", "w30.d1", "w31.d0", "w31.d1",
1489 };
1490
1491 #define LOG_DISAS(...) \
1492 do { \
1493 if (MIPS_DEBUG_DISAS) { \
1494 qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
1495 } \
1496 } while (0)
1497
1498 #define MIPS_INVAL(op) \
1499 do { \
1500 if (MIPS_DEBUG_DISAS) { \
1501 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
1502 TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
1503 ctx->pc, ctx->opcode, op, ctx->opcode >> 26, \
1504 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
1505 } \
1506 } while (0)
1507
1508 /* General purpose registers moves. */
1509 static inline void gen_load_gpr (TCGv t, int reg)
1510 {
1511 if (reg == 0)
1512 tcg_gen_movi_tl(t, 0);
1513 else
1514 tcg_gen_mov_tl(t, cpu_gpr[reg]);
1515 }
1516
1517 static inline void gen_store_gpr (TCGv t, int reg)
1518 {
1519 if (reg != 0)
1520 tcg_gen_mov_tl(cpu_gpr[reg], t);
1521 }
1522
1523 /* Moves to/from shadow registers. */
1524 static inline void gen_load_srsgpr (int from, int to)
1525 {
1526 TCGv t0 = tcg_temp_new();
1527
1528 if (from == 0)
1529 tcg_gen_movi_tl(t0, 0);
1530 else {
1531 TCGv_i32 t2 = tcg_temp_new_i32();
1532 TCGv_ptr addr = tcg_temp_new_ptr();
1533
1534 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
1535 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
1536 tcg_gen_andi_i32(t2, t2, 0xf);
1537 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
1538 tcg_gen_ext_i32_ptr(addr, t2);
1539 tcg_gen_add_ptr(addr, cpu_env, addr);
1540
1541 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
1542 tcg_temp_free_ptr(addr);
1543 tcg_temp_free_i32(t2);
1544 }
1545 gen_store_gpr(t0, to);
1546 tcg_temp_free(t0);
1547 }
1548
1549 static inline void gen_store_srsgpr (int from, int to)
1550 {
1551 if (to != 0) {
1552 TCGv t0 = tcg_temp_new();
1553 TCGv_i32 t2 = tcg_temp_new_i32();
1554 TCGv_ptr addr = tcg_temp_new_ptr();
1555
1556 gen_load_gpr(t0, from);
1557 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
1558 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
1559 tcg_gen_andi_i32(t2, t2, 0xf);
1560 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
1561 tcg_gen_ext_i32_ptr(addr, t2);
1562 tcg_gen_add_ptr(addr, cpu_env, addr);
1563
1564 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
1565 tcg_temp_free_ptr(addr);
1566 tcg_temp_free_i32(t2);
1567 tcg_temp_free(t0);
1568 }
1569 }
1570
1571 /* Tests */
1572 static inline void gen_save_pc(target_ulong pc)
1573 {
1574 tcg_gen_movi_tl(cpu_PC, pc);
1575 }
1576
1577 static inline void save_cpu_state(DisasContext *ctx, int do_save_pc)
1578 {
1579 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
1580 if (do_save_pc && ctx->pc != ctx->saved_pc) {
1581 gen_save_pc(ctx->pc);
1582 ctx->saved_pc = ctx->pc;
1583 }
1584 if (ctx->hflags != ctx->saved_hflags) {
1585 tcg_gen_movi_i32(hflags, ctx->hflags);
1586 ctx->saved_hflags = ctx->hflags;
1587 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
1588 case MIPS_HFLAG_BR:
1589 break;
1590 case MIPS_HFLAG_BC:
1591 case MIPS_HFLAG_BL:
1592 case MIPS_HFLAG_B:
1593 tcg_gen_movi_tl(btarget, ctx->btarget);
1594 break;
1595 }
1596 }
1597 }
1598
1599 static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
1600 {
1601 ctx->saved_hflags = ctx->hflags;
1602 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
1603 case MIPS_HFLAG_BR:
1604 break;
1605 case MIPS_HFLAG_BC:
1606 case MIPS_HFLAG_BL:
1607 case MIPS_HFLAG_B:
1608 ctx->btarget = env->btarget;
1609 break;
1610 }
1611 }
1612
1613 static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
1614 {
1615 TCGv_i32 texcp = tcg_const_i32(excp);
1616 TCGv_i32 terr = tcg_const_i32(err);
1617 save_cpu_state(ctx, 1);
1618 gen_helper_raise_exception_err(cpu_env, texcp, terr);
1619 tcg_temp_free_i32(terr);
1620 tcg_temp_free_i32(texcp);
1621 ctx->bstate = BS_EXCP;
1622 }
1623
1624 static inline void generate_exception(DisasContext *ctx, int excp)
1625 {
1626 gen_helper_0e0i(raise_exception, excp);
1627 }
1628
1629 static inline void generate_exception_end(DisasContext *ctx, int excp)
1630 {
1631 generate_exception_err(ctx, excp, 0);
1632 }
1633
1634 /* Floating point register moves. */
1635 static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
1636 {
1637 if (ctx->hflags & MIPS_HFLAG_FRE) {
1638 generate_exception(ctx, EXCP_RI);
1639 }
1640 tcg_gen_extrl_i64_i32(t, fpu_f64[reg]);
1641 }
1642
1643 static void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
1644 {
1645 TCGv_i64 t64;
1646 if (ctx->hflags & MIPS_HFLAG_FRE) {
1647 generate_exception(ctx, EXCP_RI);
1648 }
1649 t64 = tcg_temp_new_i64();
1650 tcg_gen_extu_i32_i64(t64, t);
1651 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32);
1652 tcg_temp_free_i64(t64);
1653 }
1654
1655 static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
1656 {
1657 if (ctx->hflags & MIPS_HFLAG_F64) {
1658 tcg_gen_extrh_i64_i32(t, fpu_f64[reg]);
1659 } else {
1660 gen_load_fpr32(ctx, t, reg | 1);
1661 }
1662 }
1663
1664 static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
1665 {
1666 if (ctx->hflags & MIPS_HFLAG_F64) {
1667 TCGv_i64 t64 = tcg_temp_new_i64();
1668 tcg_gen_extu_i32_i64(t64, t);
1669 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32);
1670 tcg_temp_free_i64(t64);
1671 } else {
1672 gen_store_fpr32(ctx, t, reg | 1);
1673 }
1674 }
1675
1676 static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
1677 {
1678 if (ctx->hflags & MIPS_HFLAG_F64) {
1679 tcg_gen_mov_i64(t, fpu_f64[reg]);
1680 } else {
1681 tcg_gen_concat32_i64(t, fpu_f64[reg & ~1], fpu_f64[reg | 1]);
1682 }
1683 }
1684
1685 static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
1686 {
1687 if (ctx->hflags & MIPS_HFLAG_F64) {
1688 tcg_gen_mov_i64(fpu_f64[reg], t);
1689 } else {
1690 TCGv_i64 t0;
1691 tcg_gen_deposit_i64(fpu_f64[reg & ~1], fpu_f64[reg & ~1], t, 0, 32);
1692 t0 = tcg_temp_new_i64();
1693 tcg_gen_shri_i64(t0, t, 32);
1694 tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32);
1695 tcg_temp_free_i64(t0);
1696 }
1697 }
1698
1699 static inline int get_fp_bit (int cc)
1700 {
1701 if (cc)
1702 return 24 + cc;
1703 else
1704 return 23;
1705 }
1706
1707 /* Addresses computation */
1708 static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
1709 {
1710 tcg_gen_add_tl(ret, arg0, arg1);
1711
1712 #if defined(TARGET_MIPS64)
1713 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1714 tcg_gen_ext32s_i64(ret, ret);
1715 }
1716 #endif
1717 }
1718
1719 /* Addresses computation (translation time) */
1720 static target_long addr_add(DisasContext *ctx, target_long base,
1721 target_long offset)
1722 {
1723 target_long sum = base + offset;
1724
1725 #if defined(TARGET_MIPS64)
1726 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1727 sum = (int32_t)sum;
1728 }
1729 #endif
1730 return sum;
1731 }
1732
1733 /* Sign-extract the low 32-bits to a target_long. */
1734 static inline void gen_move_low32(TCGv ret, TCGv_i64 arg)
1735 {
1736 #if defined(TARGET_MIPS64)
1737 tcg_gen_ext32s_i64(ret, arg);
1738 #else
1739 tcg_gen_extrl_i64_i32(ret, arg);
1740 #endif
1741 }
1742
1743 /* Sign-extract the high 32-bits to a target_long. */
1744 static inline void gen_move_high32(TCGv ret, TCGv_i64 arg)
1745 {
1746 #if defined(TARGET_MIPS64)
1747 tcg_gen_sari_i64(ret, arg, 32);
1748 #else
1749 tcg_gen_extrh_i64_i32(ret, arg);
1750 #endif
1751 }
1752
1753 static inline void check_cp0_enabled(DisasContext *ctx)
1754 {
1755 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
1756 generate_exception_err(ctx, EXCP_CpU, 0);
1757 }
1758
1759 static inline void check_cp1_enabled(DisasContext *ctx)
1760 {
1761 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
1762 generate_exception_err(ctx, EXCP_CpU, 1);
1763 }
1764
1765 /* Verify that the processor is running with COP1X instructions enabled.
1766 This is associated with the nabla symbol in the MIPS32 and MIPS64
1767 opcode tables. */
1768
1769 static inline void check_cop1x(DisasContext *ctx)
1770 {
1771 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
1772 generate_exception_end(ctx, EXCP_RI);
1773 }
1774
1775 /* Verify that the processor is running with 64-bit floating-point
1776 operations enabled. */
1777
1778 static inline void check_cp1_64bitmode(DisasContext *ctx)
1779 {
1780 if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
1781 generate_exception_end(ctx, EXCP_RI);
1782 }
1783
1784 /*
1785 * Verify if floating point register is valid; an operation is not defined
1786 * if bit 0 of any register specification is set and the FR bit in the
1787 * Status register equals zero, since the register numbers specify an
1788 * even-odd pair of adjacent coprocessor general registers. When the FR bit
1789 * in the Status register equals one, both even and odd register numbers
1790 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
1791 *
1792 * Multiple 64 bit wide registers can be checked by calling
1793 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
1794 */
1795 static inline void check_cp1_registers(DisasContext *ctx, int regs)
1796 {
1797 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
1798 generate_exception_end(ctx, EXCP_RI);
1799 }
1800
1801 /* Verify that the processor is running with DSP instructions enabled.
1802 This is enabled by CP0 Status register MX(24) bit.
1803 */
1804
1805 static inline void check_dsp(DisasContext *ctx)
1806 {
1807 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) {
1808 if (ctx->insn_flags & ASE_DSP) {
1809 generate_exception_end(ctx, EXCP_DSPDIS);
1810 } else {
1811 generate_exception_end(ctx, EXCP_RI);
1812 }
1813 }
1814 }
1815
1816 static inline void check_dspr2(DisasContext *ctx)
1817 {
1818 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) {
1819 if (ctx->insn_flags & ASE_DSP) {
1820 generate_exception_end(ctx, EXCP_DSPDIS);
1821 } else {
1822 generate_exception_end(ctx, EXCP_RI);
1823 }
1824 }
1825 }
1826
1827 /* This code generates a "reserved instruction" exception if the
1828 CPU does not support the instruction set corresponding to flags. */
1829 static inline void check_insn(DisasContext *ctx, int flags)
1830 {
1831 if (unlikely(!(ctx->insn_flags & flags))) {
1832 generate_exception_end(ctx, EXCP_RI);
1833 }
1834 }
1835
1836 /* This code generates a "reserved instruction" exception if the
1837 CPU has corresponding flag set which indicates that the instruction
1838 has been removed. */
1839 static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
1840 {
1841 if (unlikely(ctx->insn_flags & flags)) {
1842 generate_exception_end(ctx, EXCP_RI);
1843 }
1844 }
1845
1846 /* This code generates a "reserved instruction" exception if the
1847 CPU does not support 64-bit paired-single (PS) floating point data type */
1848 static inline void check_ps(DisasContext *ctx)
1849 {
1850 if (unlikely(!ctx->ps)) {
1851 generate_exception(ctx, EXCP_RI);
1852 }
1853 check_cp1_64bitmode(ctx);
1854 }
1855
1856 #ifdef TARGET_MIPS64
1857 /* This code generates a "reserved instruction" exception if 64-bit
1858 instructions are not enabled. */
1859 static inline void check_mips_64(DisasContext *ctx)
1860 {
1861 if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
1862 generate_exception_end(ctx, EXCP_RI);
1863 }
1864 #endif
1865
1866 #ifndef CONFIG_USER_ONLY
1867 static inline void check_mvh(DisasContext *ctx)
1868 {
1869 if (unlikely(!ctx->mvh)) {
1870 generate_exception(ctx, EXCP_RI);
1871 }
1872 }
1873 #endif
1874
1875 /* Define small wrappers for gen_load_fpr* so that we have a uniform
1876 calling interface for 32 and 64-bit FPRs. No sense in changing
1877 all callers for gen_load_fpr32 when we need the CTX parameter for
1878 this one use. */
1879 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y)
1880 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
1881 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \
1882 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
1883 int ft, int fs, int cc) \
1884 { \
1885 TCGv_i##bits fp0 = tcg_temp_new_i##bits (); \
1886 TCGv_i##bits fp1 = tcg_temp_new_i##bits (); \
1887 switch (ifmt) { \
1888 case FMT_PS: \
1889 check_ps(ctx); \
1890 break; \
1891 case FMT_D: \
1892 if (abs) { \
1893 check_cop1x(ctx); \
1894 } \
1895 check_cp1_registers(ctx, fs | ft); \
1896 break; \
1897 case FMT_S: \
1898 if (abs) { \
1899 check_cop1x(ctx); \
1900 } \
1901 break; \
1902 } \
1903 gen_ldcmp_fpr##bits (ctx, fp0, fs); \
1904 gen_ldcmp_fpr##bits (ctx, fp1, ft); \
1905 switch (n) { \
1906 case 0: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\
1907 case 1: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\
1908 case 2: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\
1909 case 3: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\
1910 case 4: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\
1911 case 5: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\
1912 case 6: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\
1913 case 7: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\
1914 case 8: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\
1915 case 9: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\
1916 case 10: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\
1917 case 11: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\
1918 case 12: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\
1919 case 13: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\
1920 case 14: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\
1921 case 15: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\
1922 default: abort(); \
1923 } \
1924 tcg_temp_free_i##bits (fp0); \
1925 tcg_temp_free_i##bits (fp1); \
1926 }
1927
1928 FOP_CONDS(, 0, d, FMT_D, 64)
1929 FOP_CONDS(abs, 1, d, FMT_D, 64)
1930 FOP_CONDS(, 0, s, FMT_S, 32)
1931 FOP_CONDS(abs, 1, s, FMT_S, 32)
1932 FOP_CONDS(, 0, ps, FMT_PS, 64)
1933 FOP_CONDS(abs, 1, ps, FMT_PS, 64)
1934 #undef FOP_CONDS
1935
1936 #define FOP_CONDNS(fmt, ifmt, bits, STORE) \
1937 static inline void gen_r6_cmp_ ## fmt(DisasContext * ctx, int n, \
1938 int ft, int fs, int fd) \
1939 { \
1940 TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \
1941 TCGv_i ## bits fp1 = tcg_temp_new_i ## bits(); \
1942 if (ifmt == FMT_D) { \
1943 check_cp1_registers(ctx, fs | ft | fd); \
1944 } \
1945 gen_ldcmp_fpr ## bits(ctx, fp0, fs); \
1946 gen_ldcmp_fpr ## bits(ctx, fp1, ft); \
1947 switch (n) { \
1948 case 0: \
1949 gen_helper_r6_cmp_ ## fmt ## _af(fp0, cpu_env, fp0, fp1); \
1950 break; \
1951 case 1: \
1952 gen_helper_r6_cmp_ ## fmt ## _un(fp0, cpu_env, fp0, fp1); \
1953 break; \
1954 case 2: \
1955 gen_helper_r6_cmp_ ## fmt ## _eq(fp0, cpu_env, fp0, fp1); \
1956 break; \
1957 case 3: \
1958 gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, cpu_env, fp0, fp1); \
1959 break; \
1960 case 4: \
1961 gen_helper_r6_cmp_ ## fmt ## _lt(fp0, cpu_env, fp0, fp1); \
1962 break; \
1963 case 5: \
1964 gen_helper_r6_cmp_ ## fmt ## _ult(fp0, cpu_env, fp0, fp1); \
1965 break; \
1966 case 6: \
1967 gen_helper_r6_cmp_ ## fmt ## _le(fp0, cpu_env, fp0, fp1); \
1968 break; \
1969 case 7: \
1970 gen_helper_r6_cmp_ ## fmt ## _ule(fp0, cpu_env, fp0, fp1); \
1971 break; \
1972 case 8: \
1973 gen_helper_r6_cmp_ ## fmt ## _saf(fp0, cpu_env, fp0, fp1); \
1974 break; \
1975 case 9: \
1976 gen_helper_r6_cmp_ ## fmt ## _sun(fp0, cpu_env, fp0, fp1); \
1977 break; \
1978 case 10: \
1979 gen_helper_r6_cmp_ ## fmt ## _seq(fp0, cpu_env, fp0, fp1); \
1980 break; \
1981 case 11: \
1982 gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, cpu_env, fp0, fp1); \
1983 break; \
1984 case 12: \
1985 gen_helper_r6_cmp_ ## fmt ## _slt(fp0, cpu_env, fp0, fp1); \
1986 break; \
1987 case 13: \
1988 gen_helper_r6_cmp_ ## fmt ## _sult(fp0, cpu_env, fp0, fp1); \
1989 break; \
1990 case 14: \
1991 gen_helper_r6_cmp_ ## fmt ## _sle(fp0, cpu_env, fp0, fp1); \
1992 break; \
1993 case 15: \
1994 gen_helper_r6_cmp_ ## fmt ## _sule(fp0, cpu_env, fp0, fp1); \
1995 break; \
1996 case 17: \
1997 gen_helper_r6_cmp_ ## fmt ## _or(fp0, cpu_env, fp0, fp1); \
1998 break; \
1999 case 18: \
2000 gen_helper_r6_cmp_ ## fmt ## _une(fp0, cpu_env, fp0, fp1); \
2001 break; \
2002 case 19: \
2003 gen_helper_r6_cmp_ ## fmt ## _ne(fp0, cpu_env, fp0, fp1); \
2004 break; \
2005 case 25: \
2006 gen_helper_r6_cmp_ ## fmt ## _sor(fp0, cpu_env, fp0, fp1); \
2007 break; \
2008 case 26: \
2009 gen_helper_r6_cmp_ ## fmt ## _sune(fp0, cpu_env, fp0, fp1); \
2010 break; \
2011 case 27: \
2012 gen_helper_r6_cmp_ ## fmt ## _sne(fp0, cpu_env, fp0, fp1); \
2013 break; \
2014 default: \
2015 abort(); \
2016 } \
2017 STORE; \
2018 tcg_temp_free_i ## bits (fp0); \
2019 tcg_temp_free_i ## bits (fp1); \
2020 }
2021
2022 FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd))
2023 FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
2024 #undef FOP_CONDNS
2025 #undef gen_ldcmp_fpr32
2026 #undef gen_ldcmp_fpr64
2027
2028 /* load/store instructions. */
2029 #ifdef CONFIG_USER_ONLY
2030 #define OP_LD_ATOMIC(insn,fname) \
2031 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
2032 { \
2033 TCGv t0 = tcg_temp_new(); \
2034 tcg_gen_mov_tl(t0, arg1); \
2035 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
2036 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
2037 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
2038 tcg_temp_free(t0); \
2039 }
2040 #else
2041 #define OP_LD_ATOMIC(insn,fname) \
2042 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
2043 { \
2044 gen_helper_1e1i(insn, ret, arg1, ctx->mem_idx); \
2045 }
2046 #endif
2047 OP_LD_ATOMIC(ll,ld32s);
2048 #if defined(TARGET_MIPS64)
2049 OP_LD_ATOMIC(lld,ld64);
2050 #endif
2051 #undef OP_LD_ATOMIC
2052
2053 #ifdef CONFIG_USER_ONLY
2054 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
2055 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
2056 { \
2057 TCGv t0 = tcg_temp_new(); \
2058 TCGLabel *l1 = gen_new_label(); \
2059 TCGLabel *l2 = gen_new_label(); \
2060 \
2061 tcg_gen_andi_tl(t0, arg2, almask); \
2062 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
2063 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); \
2064 generate_exception(ctx, EXCP_AdES); \
2065 gen_set_label(l1); \
2066 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
2067 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
2068 tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
2069 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); \
2070 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUMIPSState, llnewval)); \
2071 generate_exception_end(ctx, EXCP_SC); \
2072 gen_set_label(l2); \
2073 tcg_gen_movi_tl(t0, 0); \
2074 gen_store_gpr(t0, rt); \
2075 tcg_temp_free(t0); \
2076 }
2077 #else
2078 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
2079 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
2080 { \
2081 TCGv t0 = tcg_temp_new(); \
2082 gen_helper_1e2i(insn, t0, arg1, arg2, ctx->mem_idx); \
2083 gen_store_gpr(t0, rt); \
2084 tcg_temp_free(t0); \
2085 }
2086 #endif
2087 OP_ST_ATOMIC(sc,st32,ld32s,0x3);
2088 #if defined(TARGET_MIPS64)
2089 OP_ST_ATOMIC(scd,st64,ld64,0x7);
2090 #endif
2091 #undef OP_ST_ATOMIC
2092
2093 static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
2094 int base, int16_t offset)
2095 {
2096 if (base == 0) {
2097 tcg_gen_movi_tl(addr, offset);
2098 } else if (offset == 0) {
2099 gen_load_gpr(addr, base);
2100 } else {
2101 tcg_gen_movi_tl(addr, offset);
2102 gen_op_addr_add(ctx, addr, cpu_gpr[base], addr);
2103 }
2104 }
2105
2106 static target_ulong pc_relative_pc (DisasContext *ctx)
2107 {
2108 target_ulong pc = ctx->pc;
2109
2110 if (ctx->hflags & MIPS_HFLAG_BMASK) {
2111 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4;
2112
2113 pc -= branch_bytes;
2114 }
2115
2116 pc &= ~(target_ulong)3;
2117 return pc;
2118 }
2119
2120 /* Load */
2121 static void gen_ld(DisasContext *ctx, uint32_t opc,
2122 int rt, int base, int16_t offset)
2123 {
2124 TCGv t0, t1, t2;
2125
2126 if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
2127 /* Loongson CPU uses a load to zero register for prefetch.
2128 We emulate it as a NOP. On other CPU we must perform the
2129 actual memory access. */
2130 return;
2131 }
2132
2133 t0 = tcg_temp_new();
2134 gen_base_offset_addr(ctx, t0, base, offset);
2135
2136 switch (opc) {
2137 #if defined(TARGET_MIPS64)
2138 case OPC_LWU:
2139 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL |
2140 ctx->default_tcg_memop_mask);
2141 gen_store_gpr(t0, rt);
2142 break;
2143 case OPC_LD:
2144 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
2145 ctx->default_tcg_memop_mask);
2146 gen_store_gpr(t0, rt);
2147 break;
2148 case OPC_LLD:
2149 case R6_OPC_LLD:
2150 op_ld_lld(t0, t0, ctx);
2151 gen_store_gpr(t0, rt);
2152 break;
2153 case OPC_LDL:
2154 t1 = tcg_temp_new();
2155 /* Do a byte access to possibly trigger a page
2156 fault with the unaligned address. */
2157 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
2158 tcg_gen_andi_tl(t1, t0, 7);
2159 #ifndef TARGET_WORDS_BIGENDIAN
2160 tcg_gen_xori_tl(t1, t1, 7);
2161 #endif
2162 tcg_gen_shli_tl(t1, t1, 3);
2163 tcg_gen_andi_tl(t0, t0, ~7);
2164 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
2165 tcg_gen_shl_tl(t0, t0, t1);
2166 t2 = tcg_const_tl(-1);
2167 tcg_gen_shl_tl(t2, t2, t1);
2168 gen_load_gpr(t1, rt);
2169 tcg_gen_andc_tl(t1, t1, t2);
2170 tcg_temp_free(t2);
2171 tcg_gen_or_tl(t0, t0, t1);
2172 tcg_temp_free(t1);
2173 gen_store_gpr(t0, rt);
2174 break;
2175 case OPC_LDR:
2176 t1 = tcg_temp_new();
2177 /* Do a byte access to possibly trigger a page
2178 fault with the unaligned address. */
2179 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
2180 tcg_gen_andi_tl(t1, t0, 7);
2181 #ifdef TARGET_WORDS_BIGENDIAN
2182 tcg_gen_xori_tl(t1, t1, 7);
2183 #endif
2184 tcg_gen_shli_tl(t1, t1, 3);
2185 tcg_gen_andi_tl(t0, t0, ~7);
2186 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
2187 tcg_gen_shr_tl(t0, t0, t1);
2188 tcg_gen_xori_tl(t1, t1, 63);
2189 t2 = tcg_const_tl(0xfffffffffffffffeull);
2190 tcg_gen_shl_tl(t2, t2, t1);
2191 gen_load_gpr(t1, rt);
2192 tcg_gen_and_tl(t1, t1, t2);
2193 tcg_temp_free(t2);
2194 tcg_gen_or_tl(t0, t0, t1);
2195 tcg_temp_free(t1);
2196 gen_store_gpr(t0, rt);
2197 break;
2198 case OPC_LDPC:
2199 t1 = tcg_const_tl(pc_relative_pc(ctx));
2200 gen_op_addr_add(ctx, t0, t0, t1);
2201 tcg_temp_free(t1);
2202 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
2203 gen_store_gpr(t0, rt);
2204 break;
2205 #endif
2206 case OPC_LWPC:
2207 t1 = tcg_const_tl(pc_relative_pc(ctx));
2208 gen_op_addr_add(ctx, t0, t0, t1);
2209 tcg_temp_free(t1);
2210 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
2211 gen_store_gpr(t0, rt);
2212 break;
2213 case OPC_LW:
2214 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
2215 ctx->default_tcg_memop_mask);
2216 gen_store_gpr(t0, rt);
2217 break;
2218 case OPC_LH:
2219 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
2220 ctx->default_tcg_memop_mask);
2221 gen_store_gpr(t0, rt);
2222 break;
2223 case OPC_LHU:
2224 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUW |
2225 ctx->default_tcg_memop_mask);
2226 gen_store_gpr(t0, rt);
2227 break;
2228 case OPC_LB:
2229 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
2230 gen_store_gpr(t0, rt);
2231 break;
2232 case OPC_LBU:
2233 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
2234 gen_store_gpr(t0, rt);
2235 break;
2236 case OPC_LWL:
2237 t1 = tcg_temp_new();
2238 /* Do a byte access to possibly trigger a page
2239 fault with the unaligned address. */
2240 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
2241 tcg_gen_andi_tl(t1, t0, 3);
2242 #ifndef TARGET_WORDS_BIGENDIAN
2243 tcg_gen_xori_tl(t1, t1, 3);
2244 #endif
2245 tcg_gen_shli_tl(t1, t1, 3);
2246 tcg_gen_andi_tl(t0, t0, ~3);
2247 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
2248 tcg_gen_shl_tl(t0, t0, t1);
2249 t2 = tcg_const_tl(-1);
2250 tcg_gen_shl_tl(t2, t2, t1);
2251 gen_load_gpr(t1, rt);
2252 tcg_gen_andc_tl(t1, t1, t2);
2253 tcg_temp_free(t2);
2254 tcg_gen_or_tl(t0, t0, t1);
2255 tcg_temp_free(t1);
2256 tcg_gen_ext32s_tl(t0, t0);
2257 gen_store_gpr(t0, rt);
2258 break;
2259 case OPC_LWR:
2260 t1 = tcg_temp_new();
2261 /* Do a byte access to possibly trigger a page
2262 fault with the unaligned address. */
2263 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
2264 tcg_gen_andi_tl(t1, t0, 3);
2265 #ifdef TARGET_WORDS_BIGENDIAN
2266 tcg_gen_xori_tl(t1, t1, 3);
2267 #endif
2268 tcg_gen_shli_tl(t1, t1, 3);
2269 tcg_gen_andi_tl(t0, t0, ~3);
2270 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
2271 tcg_gen_shr_tl(t0, t0, t1);
2272 tcg_gen_xori_tl(t1, t1, 31);
2273 t2 = tcg_const_tl(0xfffffffeull);
2274 tcg_gen_shl_tl(t2, t2, t1);
2275 gen_load_gpr(t1, rt);
2276 tcg_gen_and_tl(t1, t1, t2);
2277 tcg_temp_free(t2);
2278 tcg_gen_or_tl(t0, t0, t1);
2279 tcg_temp_free(t1);
2280 tcg_gen_ext32s_tl(t0, t0);
2281 gen_store_gpr(t0, rt);
2282 break;
2283 case OPC_LL:
2284 case R6_OPC_LL:
2285 op_ld_ll(t0, t0, ctx);
2286 gen_store_gpr(t0, rt);
2287 break;
2288 }
2289 tcg_temp_free(t0);
2290 }
2291
2292 /* Store */
2293 static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
2294 int base, int16_t offset)
2295 {
2296 TCGv t0 = tcg_temp_new();
2297 TCGv t1 = tcg_temp_new();
2298
2299 gen_base_offset_addr(ctx, t0, base, offset);
2300 gen_load_gpr(t1, rt);
2301 switch (opc) {
2302 #if defined(TARGET_MIPS64)
2303 case OPC_SD:
2304 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
2305 ctx->default_tcg_memop_mask);
2306 break;
2307 case OPC_SDL:
2308 gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx);
2309 break;
2310 case OPC_SDR:
2311 gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx);
2312 break;
2313 #endif
2314 case OPC_SW:
2315 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
2316 ctx->default_tcg_memop_mask);
2317 break;
2318 case OPC_SH:
2319 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
2320 ctx->default_tcg_memop_mask);
2321 break;
2322 case OPC_SB:
2323 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_8);
2324 break;
2325 case OPC_SWL:
2326 gen_helper_0e2i(swl, t1, t0, ctx->mem_idx);
2327 break;
2328 case OPC_SWR:
2329 gen_helper_0e2i(swr, t1, t0, ctx->mem_idx);
2330 break;
2331 }
2332 tcg_temp_free(t0);
2333 tcg_temp_free(t1);
2334 }
2335
2336
2337 /* Store conditional */
2338 static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
2339 int base, int16_t offset)
2340 {
2341 TCGv t0, t1;
2342
2343 #ifdef CONFIG_USER_ONLY
2344 t0 = tcg_temp_local_new();
2345 t1 = tcg_temp_local_new();
2346 #else
2347 t0 = tcg_temp_new();
2348 t1 = tcg_temp_new();
2349 #endif
2350 gen_base_offset_addr(ctx, t0, base, offset);
2351 gen_load_gpr(t1, rt);
2352 switch (opc) {
2353 #if defined(TARGET_MIPS64)
2354 case OPC_SCD:
2355 case R6_OPC_SCD:
2356 op_st_scd(t1, t0, rt, ctx);
2357 break;
2358 #endif
2359 case OPC_SC:
2360 case R6_OPC_SC:
2361 op_st_sc(t1, t0, rt, ctx);
2362 break;
2363 }
2364 tcg_temp_free(t1);
2365 tcg_temp_free(t0);
2366 }
2367
2368 /* Load and store */
2369 static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
2370 int base, int16_t offset)
2371 {
2372 TCGv t0 = tcg_temp_new();
2373
2374 gen_base_offset_addr(ctx, t0, base, offset);
2375 /* Don't do NOP if destination is zero: we must perform the actual
2376 memory access. */
2377 switch (opc) {
2378 case OPC_LWC1:
2379 {
2380 TCGv_i32 fp0 = tcg_temp_new_i32();
2381 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
2382 ctx->default_tcg_memop_mask);
2383 gen_store_fpr32(ctx, fp0, ft);
2384 tcg_temp_free_i32(fp0);
2385 }
2386 break;
2387 case OPC_SWC1:
2388 {
2389 TCGv_i32 fp0 = tcg_temp_new_i32();
2390 gen_load_fpr32(ctx, fp0, ft);
2391 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
2392 ctx->default_tcg_memop_mask);
2393 tcg_temp_free_i32(fp0);
2394 }
2395 break;
2396 case OPC_LDC1:
2397 {
2398 TCGv_i64 fp0 = tcg_temp_new_i64();
2399 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
2400 ctx->default_tcg_memop_mask);
2401 gen_store_fpr64(ctx, fp0, ft);
2402 tcg_temp_free_i64(fp0);
2403 }
2404 break;
2405 case OPC_SDC1:
2406 {
2407 TCGv_i64 fp0 = tcg_temp_new_i64();
2408 gen_load_fpr64(ctx, fp0, ft);
2409 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
2410 ctx->default_tcg_memop_mask);
2411 tcg_temp_free_i64(fp0);
2412 }
2413 break;
2414 default:
2415 MIPS_INVAL("flt_ldst");
2416 generate_exception_end(ctx, EXCP_RI);
2417 goto out;
2418 }
2419 out:
2420 tcg_temp_free(t0);
2421 }
2422
2423 static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
2424 int rs, int16_t imm)
2425 {
2426 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
2427 check_cp1_enabled(ctx);
2428 switch (op) {
2429 case OPC_LDC1:
2430 case OPC_SDC1:
2431 check_insn(ctx, ISA_MIPS2);
2432 /* Fallthrough */
2433 default:
2434 gen_flt_ldst(ctx, op, rt, rs, imm);
2435 }
2436 } else {
2437 generate_exception_err(ctx, EXCP_CpU, 1);
2438 }
2439 }
2440
2441 /* Arithmetic with immediate operand */
2442 static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
2443 int rt, int rs, int16_t imm)
2444 {
2445 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
2446
2447 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
2448 /* If no destination, treat it as a NOP.
2449 For addi, we must generate the overflow exception when needed. */
2450 return;
2451 }
2452 switch (opc) {
2453 case OPC_ADDI:
2454 {
2455 TCGv t0 = tcg_temp_local_new();
2456 TCGv t1 = tcg_temp_new();
2457 TCGv t2 = tcg_temp_new();
2458 TCGLabel *l1 = gen_new_label();
2459
2460 gen_load_gpr(t1, rs);
2461 tcg_gen_addi_tl(t0, t1, uimm);
2462 tcg_gen_ext32s_tl(t0, t0);
2463
2464 tcg_gen_xori_tl(t1, t1, ~uimm);
2465 tcg_gen_xori_tl(t2, t0, uimm);
2466 tcg_gen_and_tl(t1, t1, t2);
2467 tcg_temp_free(t2);
2468 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2469 tcg_temp_free(t1);
2470 /* operands of same sign, result different sign */
2471 generate_exception(ctx, EXCP_OVERFLOW);
2472 gen_set_label(l1);
2473 tcg_gen_ext32s_tl(t0, t0);
2474 gen_store_gpr(t0, rt);
2475 tcg_temp_free(t0);
2476 }
2477 break;
2478 case OPC_ADDIU:
2479 if (rs != 0) {
2480 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2481 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
2482 } else {
2483 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2484 }
2485 break;
2486 #if defined(TARGET_MIPS64)
2487 case OPC_DADDI:
2488 {
2489 TCGv t0 = tcg_temp_local_new();
2490 TCGv t1 = tcg_temp_new();
2491 TCGv t2 = tcg_temp_new();
2492 TCGLabel *l1 = gen_new_label();
2493
2494 gen_load_gpr(t1, rs);
2495 tcg_gen_addi_tl(t0, t1, uimm);
2496
2497 tcg_gen_xori_tl(t1, t1, ~uimm);
2498 tcg_gen_xori_tl(t2, t0, uimm);
2499 tcg_gen_and_tl(t1, t1, t2);
2500 tcg_temp_free(t2);
2501 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2502 tcg_temp_free(t1);
2503 /* operands of same sign, result different sign */
2504 generate_exception(ctx, EXCP_OVERFLOW);
2505 gen_set_label(l1);
2506 gen_store_gpr(t0, rt);
2507 tcg_temp_free(t0);
2508 }
2509 break;
2510 case OPC_DADDIU:
2511 if (rs != 0) {
2512 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2513 } else {
2514 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2515 }
2516 break;
2517 #endif
2518 }
2519 }
2520
2521 /* Logic with immediate operand */
2522 static void gen_logic_imm(DisasContext *ctx, uint32_t opc,
2523 int rt, int rs, int16_t imm)
2524 {
2525 target_ulong uimm;
2526
2527 if (rt == 0) {
2528 /* If no destination, treat it as a NOP. */
2529 return;
2530 }
2531 uimm = (uint16_t)imm;
2532 switch (opc) {
2533 case OPC_ANDI:
2534 if (likely(rs != 0))
2535 tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2536 else
2537 tcg_gen_movi_tl(cpu_gpr[rt], 0);
2538 break;
2539 case OPC_ORI:
2540 if (rs != 0)
2541 tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2542 else
2543 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2544 break;
2545 case OPC_XORI:
2546 if (likely(rs != 0))
2547 tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2548 else
2549 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2550 break;
2551 case OPC_LUI:
2552 if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) {
2553 /* OPC_AUI */
2554 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16);
2555 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
2556 } else {
2557 tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
2558 }
2559 break;
2560
2561 default:
2562 break;
2563 }
2564 }
2565
2566 /* Set on less than with immediate operand */
2567 static void gen_slt_imm(DisasContext *ctx, uint32_t opc,
2568 int rt, int rs, int16_t imm)
2569 {
2570 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
2571 TCGv t0;
2572
2573 if (rt == 0) {
2574 /* If no destination, treat it as a NOP. */
2575 return;
2576 }
2577 t0 = tcg_temp_new();
2578 gen_load_gpr(t0, rs);
2579 switch (opc) {
2580 case OPC_SLTI:
2581 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm);
2582 break;
2583 case OPC_SLTIU:
2584 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm);
2585 break;
2586 }
2587 tcg_temp_free(t0);
2588 }
2589
2590 /* Shifts with immediate operand */
2591 static void gen_shift_imm(DisasContext *ctx, uint32_t opc,
2592 int rt, int rs, int16_t imm)
2593 {
2594 target_ulong uimm = ((uint16_t)imm) & 0x1f;
2595 TCGv t0;
2596
2597 if (rt == 0) {
2598 /* If no destination, treat it as a NOP. */
2599 return;
2600 }
2601
2602 t0 = tcg_temp_new();
2603 gen_load_gpr(t0, rs);
2604 switch (opc) {
2605 case OPC_SLL:
2606 tcg_gen_shli_tl(t0, t0, uimm);
2607 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2608 break;
2609 case OPC_SRA:
2610 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
2611 break;
2612 case OPC_SRL:
2613 if (uimm != 0) {
2614 tcg_gen_ext32u_tl(t0, t0);
2615 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
2616 } else {
2617 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2618 }
2619 break;
2620 case OPC_ROTR:
2621 if (uimm != 0) {
2622 TCGv_i32 t1 = tcg_temp_new_i32();
2623
2624 tcg_gen_trunc_tl_i32(t1, t0);
2625 tcg_gen_rotri_i32(t1, t1, uimm);
2626 tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
2627 tcg_temp_free_i32(t1);
2628 } else {
2629 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2630 }
2631 break;
2632 #if defined(TARGET_MIPS64)
2633 case OPC_DSLL:
2634 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm);
2635 break;
2636 case OPC_DSRA:
2637 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
2638 break;
2639 case OPC_DSRL:
2640 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
2641 break;
2642 case OPC_DROTR:
2643 if (uimm != 0) {
2644 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
2645 } else {
2646 tcg_gen_mov_tl(cpu_gpr[rt], t0);
2647 }
2648 break;
2649 case OPC_DSLL32:
2650 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32);
2651 break;
2652 case OPC_DSRA32:
2653 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32);
2654 break;
2655 case OPC_DSRL32:
2656 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
2657 break;
2658 case OPC_DROTR32:
2659 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32);
2660 break;
2661 #endif
2662 }
2663 tcg_temp_free(t0);
2664 }
2665
2666 /* Arithmetic */
2667 static void gen_arith(DisasContext *ctx, uint32_t opc,
2668 int rd, int rs, int rt)
2669 {
2670 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
2671 && opc != OPC_DADD && opc != OPC_DSUB) {
2672 /* If no destination, treat it as a NOP.
2673 For add & sub, we must generate the overflow exception when needed. */
2674 return;
2675 }
2676
2677 switch (opc) {
2678 case OPC_ADD:
2679 {
2680 TCGv t0 = tcg_temp_local_new();
2681 TCGv t1 = tcg_temp_new();
2682 TCGv t2 = tcg_temp_new();
2683 TCGLabel *l1 = gen_new_label();
2684
2685 gen_load_gpr(t1, rs);
2686 gen_load_gpr(t2, rt);
2687 tcg_gen_add_tl(t0, t1, t2);
2688 tcg_gen_ext32s_tl(t0, t0);
2689 tcg_gen_xor_tl(t1, t1, t2);
2690 tcg_gen_xor_tl(t2, t0, t2);
2691 tcg_gen_andc_tl(t1, t2, t1);
2692 tcg_temp_free(t2);
2693 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2694 tcg_temp_free(t1);
2695 /* operands of same sign, result different sign */
2696 generate_exception(ctx, EXCP_OVERFLOW);
2697 gen_set_label(l1);
2698 gen_store_gpr(t0, rd);
2699 tcg_temp_free(t0);
2700 }
2701 break;
2702 case OPC_ADDU:
2703 if (rs != 0 && rt != 0) {
2704 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2705 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2706 } else if (rs == 0 && rt != 0) {
2707 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2708 } else if (rs != 0 && rt == 0) {
2709 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2710 } else {
2711 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2712 }
2713 break;
2714 case OPC_SUB:
2715 {
2716 TCGv t0 = tcg_temp_local_new();
2717 TCGv t1 = tcg_temp_new();
2718 TCGv t2 = tcg_temp_new();
2719 TCGLabel *l1 = gen_new_label();
2720
2721 gen_load_gpr(t1, rs);
2722 gen_load_gpr(t2, rt);
2723 tcg_gen_sub_tl(t0, t1, t2);
2724 tcg_gen_ext32s_tl(t0, t0);
2725 tcg_gen_xor_tl(t2, t1, t2);
2726 tcg_gen_xor_tl(t1, t0, t1);
2727 tcg_gen_and_tl(t1, t1, t2);
2728 tcg_temp_free(t2);
2729 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2730 tcg_temp_free(t1);
2731 /* operands of different sign, first operand and result different sign */
2732 generate_exception(ctx, EXCP_OVERFLOW);
2733 gen_set_label(l1);
2734 gen_store_gpr(t0, rd);
2735 tcg_temp_free(t0);
2736 }
2737 break;
2738 case OPC_SUBU:
2739 if (rs != 0 && rt != 0) {
2740 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2741 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2742 } else if (rs == 0 && rt != 0) {
2743 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
2744 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2745 } else if (rs != 0 && rt == 0) {
2746 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2747 } else {
2748 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2749 }
2750 break;
2751 #if defined(TARGET_MIPS64)
2752 case OPC_DADD:
2753 {
2754 TCGv t0 = tcg_temp_local_new();
2755 TCGv t1 = tcg_temp_new();
2756 TCGv t2 = tcg_temp_new();
2757 TCGLabel *l1 = gen_new_label();
2758
2759 gen_load_gpr(t1, rs);
2760 gen_load_gpr(t2, rt);
2761 tcg_gen_add_tl(t0, t1, t2);
2762 tcg_gen_xor_tl(t1, t1, t2);
2763 tcg_gen_xor_tl(t2, t0, t2);
2764 tcg_gen_andc_tl(t1, t2, t1);
2765 tcg_temp_free(t2);
2766 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2767 tcg_temp_free(t1);
2768 /* operands of same sign, result different sign */
2769 generate_exception(ctx, EXCP_OVERFLOW);
2770 gen_set_label(l1);
2771 gen_store_gpr(t0, rd);
2772 tcg_temp_free(t0);
2773 }
2774 break;
2775 case OPC_DADDU:
2776 if (rs != 0 && rt != 0) {
2777 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2778 } else if (rs == 0 && rt != 0) {
2779 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2780 } else if (rs != 0 && rt == 0) {
2781 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2782 } else {
2783 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2784 }
2785 break;
2786 case OPC_DSUB:
2787 {
2788 TCGv t0 = tcg_temp_local_new();
2789 TCGv t1 = tcg_temp_new();
2790 TCGv t2 = tcg_temp_new();
2791 TCGLabel *l1 = gen_new_label();
2792
2793 gen_load_gpr(t1, rs);
2794 gen_load_gpr(t2, rt);
2795 tcg_gen_sub_tl(t0, t1, t2);
2796 tcg_gen_xor_tl(t2, t1, t2);
2797 tcg_gen_xor_tl(t1, t0, t1);
2798 tcg_gen_and_tl(t1, t1, t2);
2799 tcg_temp_free(t2);
2800 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2801 tcg_temp_free(t1);
2802 /* operands of different sign, first operand and result different sign */
2803 generate_exception(ctx, EXCP_OVERFLOW);
2804 gen_set_label(l1);
2805 gen_store_gpr(t0, rd);
2806 tcg_temp_free(t0);
2807 }
2808 break;
2809 case OPC_DSUBU:
2810 if (rs != 0 && rt != 0) {
2811 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2812 } else if (rs == 0 && rt != 0) {
2813 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
2814 } else if (rs != 0 && rt == 0) {
2815 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2816 } else {
2817 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2818 }
2819 break;
2820 #endif
2821 case OPC_MUL:
2822 if (likely(rs != 0 && rt != 0)) {
2823 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2824 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2825 } else {
2826 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2827 }
2828 break;
2829 }
2830 }
2831
2832 /* Conditional move */
2833 static void gen_cond_move(DisasContext *ctx, uint32_t opc,
2834 int rd, int rs, int rt)
2835 {
2836 TCGv t0, t1, t2;
2837
2838 if (rd == 0) {
2839 /* If no destination, treat it as a NOP. */
2840 return;
2841 }
2842
2843 t0 = tcg_temp_new();
2844 gen_load_gpr(t0, rt);
2845 t1 = tcg_const_tl(0);
2846 t2 = tcg_temp_new();
2847 gen_load_gpr(t2, rs);
2848 switch (opc) {
2849 case OPC_MOVN:
2850 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
2851 break;
2852 case OPC_MOVZ:
2853 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
2854 break;
2855 case OPC_SELNEZ:
2856 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1);
2857 break;
2858 case OPC_SELEQZ:
2859 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1);
2860 break;
2861 }
2862 tcg_temp_free(t2);
2863 tcg_temp_free(t1);
2864 tcg_temp_free(t0);
2865 }
2866
2867 /* Logic */
2868 static void gen_logic(DisasContext *ctx, uint32_t opc,
2869 int rd, int rs, int rt)
2870 {
2871 if (rd == 0) {
2872 /* If no destination, treat it as a NOP. */
2873 return;
2874 }
2875
2876 switch (opc) {
2877 case OPC_AND:
2878 if (likely(rs != 0 && rt != 0)) {
2879 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2880 } else {
2881 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2882 }
2883 break;
2884 case OPC_NOR:
2885 if (rs != 0 && rt != 0) {
2886 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2887 } else if (rs == 0 && rt != 0) {
2888 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]);
2889 } else if (rs != 0 && rt == 0) {
2890 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]);
2891 } else {
2892 tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0));
2893 }
2894 break;
2895 case OPC_OR:
2896 if (likely(rs != 0 && rt != 0)) {
2897 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2898 } else if (rs == 0 && rt != 0) {
2899 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2900 } else if (rs != 0 && rt == 0) {
2901 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2902 } else {
2903 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2904 }
2905 break;
2906 case OPC_XOR:
2907 if (likely(rs != 0 && rt != 0)) {
2908 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2909 } else if (rs == 0 && rt != 0) {
2910 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2911 } else if (rs != 0 && rt == 0) {
2912 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2913 } else {
2914 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2915 }
2916 break;
2917 }
2918 }
2919
2920 /* Set on lower than */
2921 static void gen_slt(DisasContext *ctx, uint32_t opc,
2922 int rd, int rs, int rt)
2923 {
2924 TCGv t0, t1;
2925
2926 if (rd == 0) {
2927 /* If no destination, treat it as a NOP. */
2928 return;
2929 }
2930
2931 t0 = tcg_temp_new();
2932 t1 = tcg_temp_new();
2933 gen_load_gpr(t0, rs);
2934 gen_load_gpr(t1, rt);
2935 switch (opc) {
2936 case OPC_SLT:
2937 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1);
2938 break;
2939 case OPC_SLTU:
2940 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1);
2941 break;
2942 }
2943 tcg_temp_free(t0);
2944 tcg_temp_free(t1);
2945 }
2946
2947 /* Shifts */
2948 static void gen_shift(DisasContext *ctx, uint32_t opc,
2949 int rd, int rs, int rt)
2950 {
2951 TCGv t0, t1;
2952
2953 if (rd == 0) {
2954 /* If no destination, treat it as a NOP.
2955 For add & sub, we must generate the overflow exception when needed. */
2956 return;
2957 }
2958
2959 t0 = tcg_temp_new();
2960 t1 = tcg_temp_new();
2961 gen_load_gpr(t0, rs);
2962 gen_load_gpr(t1, rt);
2963 switch (opc) {
2964 case OPC_SLLV:
2965 tcg_gen_andi_tl(t0, t0, 0x1f);
2966 tcg_gen_shl_tl(t0, t1, t0);
2967 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
2968 break;
2969 case OPC_SRAV:
2970 tcg_gen_andi_tl(t0, t0, 0x1f);
2971 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
2972 break;
2973 case OPC_SRLV:
2974 tcg_gen_ext32u_tl(t1, t1);
2975 tcg_gen_andi_tl(t0, t0, 0x1f);
2976 tcg_gen_shr_tl(t0, t1, t0);
2977 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
2978 break;
2979 case OPC_ROTRV:
2980 {
2981 TCGv_i32 t2 = tcg_temp_new_i32();
2982 TCGv_i32 t3 = tcg_temp_new_i32();
2983
2984 tcg_gen_trunc_tl_i32(t2, t0);
2985 tcg_gen_trunc_tl_i32(t3, t1);
2986 tcg_gen_andi_i32(t2, t2, 0x1f);
2987 tcg_gen_rotr_i32(t2, t3, t2);
2988 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
2989 tcg_temp_free_i32(t2);
2990 tcg_temp_free_i32(t3);
2991 }
2992 break;
2993 #if defined(TARGET_MIPS64)
2994 case OPC_DSLLV:
2995 tcg_gen_andi_tl(t0, t0, 0x3f);
2996 tcg_gen_shl_tl(cpu_gpr[rd], t1, t0);
2997 break;
2998 case OPC_DSRAV:
2999 tcg_gen_andi_tl(t0, t0, 0x3f);
3000 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
3001 break;
3002 case OPC_DSRLV:
3003 tcg_gen_andi_tl(t0, t0, 0x3f);
3004 tcg_gen_shr_tl(cpu_gpr[rd], t1, t0);
3005 break;
3006 case OPC_DROTRV:
3007 tcg_gen_andi_tl(t0, t0, 0x3f);
3008 tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0);
3009 break;
3010 #endif
3011 }
3012 tcg_temp_free(t0);
3013 tcg_temp_free(t1);
3014 }
3015
3016 /* Arithmetic on HI/LO registers */
3017 static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
3018 {
3019 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
3020 /* Treat as NOP. */
3021 return;
3022 }
3023
3024 if (acc != 0) {
3025 check_dsp(ctx);
3026 }
3027
3028 switch (opc) {
3029 case OPC_MFHI:
3030 #if defined(TARGET_MIPS64)
3031 if (acc != 0) {
3032 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]);
3033 } else
3034 #endif
3035 {
3036 tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]);
3037 }
3038 break;
3039 case OPC_MFLO:
3040 #if defined(TARGET_MIPS64)
3041 if (acc != 0) {
3042 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]);
3043 } else
3044 #endif
3045 {
3046 tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]);
3047 }
3048 break;
3049 case OPC_MTHI:
3050 if (reg != 0) {
3051 #if defined(TARGET_MIPS64)
3052 if (acc != 0) {
3053 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]);
3054 } else
3055 #endif
3056 {
3057 tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]);
3058 }
3059 } else {
3060 tcg_gen_movi_tl(cpu_HI[acc], 0);
3061 }
3062 break;
3063 case OPC_MTLO:
3064 if (reg != 0) {
3065 #if defined(TARGET_MIPS64)
3066 if (acc != 0) {
3067 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]);
3068 } else
3069 #endif
3070 {
3071 tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]);
3072 }
3073 } else {
3074 tcg_gen_movi_tl(cpu_LO[acc], 0);
3075 }
3076 break;
3077 }
3078 }
3079
3080 static inline void gen_r6_ld(target_long addr, int reg, int memidx,
3081 TCGMemOp memop)
3082 {
3083 TCGv t0 = tcg_const_tl(addr);
3084 tcg_gen_qemu_ld_tl(t0, t0, memidx, memop);
3085 gen_store_gpr(t0, reg);
3086 tcg_temp_free(t0);
3087 }
3088
3089 static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
3090 int rs)
3091 {
3092 target_long offset;
3093 target_long addr;
3094
3095 switch (MASK_OPC_PCREL_TOP2BITS(opc)) {
3096 case OPC_ADDIUPC:
3097 if (rs != 0) {
3098 offset = sextract32(ctx->opcode << 2, 0, 21);
3099 addr = addr_add(ctx, pc, offset);
3100 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3101 }
3102 break;
3103 case R6_OPC_LWPC:
3104 offset = sextract32(ctx->opcode << 2, 0, 21);
3105 addr = addr_add(ctx, pc, offset);
3106 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL);
3107 break;
3108 #if defined(TARGET_MIPS64)
3109 case OPC_LWUPC:
3110 check_mips_64(ctx);
3111 offset = sextract32(ctx->opcode << 2, 0, 21);
3112 addr = addr_add(ctx, pc, offset);
3113 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL);
3114 break;
3115 #endif
3116 default:
3117 switch (MASK_OPC_PCREL_TOP5BITS(opc)) {
3118 case OPC_AUIPC:
3119 if (rs != 0) {
3120 offset = sextract32(ctx->opcode, 0, 16) << 16;
3121 addr = addr_add(ctx, pc, offset);
3122 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3123 }
3124 break;
3125 case OPC_ALUIPC:
3126 if (rs != 0) {
3127 offset = sextract32(ctx->opcode, 0, 16) << 16;
3128 addr = ~0xFFFF & addr_add(ctx, pc, offset);
3129 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3130 }
3131 break;
3132 #if defined(TARGET_MIPS64)
3133 case R6_OPC_LDPC: /* bits 16 and 17 are part of immediate */
3134 case R6_OPC_LDPC + (1 << 16):
3135 case R6_OPC_LDPC + (2 << 16):
3136 case R6_OPC_LDPC + (3 << 16):
3137 check_mips_64(ctx);
3138 offset = sextract32(ctx->opcode << 3, 0, 21);
3139 addr = addr_add(ctx, (pc & ~0x7), offset);
3140 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEQ);
3141 break;
3142 #endif
3143 default:
3144 MIPS_INVAL("OPC_PCREL");
3145 generate_exception_end(ctx, EXCP_RI);
3146 break;
3147 }
3148 break;
3149 }
3150 }
3151
3152 static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
3153 {
3154 TCGv t0, t1;
3155
3156 if (rd == 0) {
3157 /* Treat as NOP. */
3158 return;
3159 }
3160
3161 t0 = tcg_temp_new();
3162 t1 = tcg_temp_new();
3163
3164 gen_load_gpr(t0, rs);
3165 gen_load_gpr(t1, rt);
3166
3167 switch (opc) {
3168 case R6_OPC_DIV:
3169 {
3170 TCGv t2 = tcg_temp_new();
3171 TCGv t3 = tcg_temp_new();
3172 tcg_gen_ext32s_tl(t0, t0);
3173 tcg_gen_ext32s_tl(t1, t1);
3174 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3175 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3176 tcg_gen_and_tl(t2, t2, t3);
3177 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3178 tcg_gen_or_tl(t2, t2, t3);
3179 tcg_gen_movi_tl(t3, 0);
3180 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3181 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3182 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3183 tcg_temp_free(t3);
3184 tcg_temp_free(t2);
3185 }
3186 break;
3187 case R6_OPC_MOD:
3188 {
3189 TCGv t2 = tcg_temp_new();
3190 TCGv t3 = tcg_temp_new();
3191 tcg_gen_ext32s_tl(t0, t0);
3192 tcg_gen_ext32s_tl(t1, t1);
3193 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3194 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3195 tcg_gen_and_tl(t2, t2, t3);
3196 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3197 tcg_gen_or_tl(t2, t2, t3);
3198 tcg_gen_movi_tl(t3, 0);
3199 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3200 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3201 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3202 tcg_temp_free(t3);
3203 tcg_temp_free(t2);
3204 }
3205 break;
3206 case R6_OPC_DIVU:
3207 {
3208 TCGv t2 = tcg_const_tl(0);
3209 TCGv t3 = tcg_const_tl(1);
3210 tcg_gen_ext32u_tl(t0, t0);
3211 tcg_gen_ext32u_tl(t1, t1);
3212 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3213 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3214 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3215 tcg_temp_free(t3);
3216 tcg_temp_free(t2);
3217 }
3218 break;
3219 case R6_OPC_MODU:
3220 {
3221 TCGv t2 = tcg_const_tl(0);
3222 TCGv t3 = tcg_const_tl(1);
3223 tcg_gen_ext32u_tl(t0, t0);
3224 tcg_gen_ext32u_tl(t1, t1);
3225 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3226 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3227 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3228 tcg_temp_free(t3);
3229 tcg_temp_free(t2);
3230 }
3231 break;
3232 case R6_OPC_MUL:
3233 {
3234 TCGv_i32 t2 = tcg_temp_new_i32();
3235 TCGv_i32 t3 = tcg_temp_new_i32();
3236 tcg_gen_trunc_tl_i32(t2, t0);
3237 tcg_gen_trunc_tl_i32(t3, t1);
3238 tcg_gen_mul_i32(t2, t2, t3);
3239 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3240 tcg_temp_free_i32(t2);
3241 tcg_temp_free_i32(t3);
3242 }
3243 break;
3244 case R6_OPC_MUH:
3245 {
3246 TCGv_i32 t2 = tcg_temp_new_i32();
3247 TCGv_i32 t3 = tcg_temp_new_i32();
3248 tcg_gen_trunc_tl_i32(t2, t0);
3249 tcg_gen_trunc_tl_i32(t3, t1);
3250 tcg_gen_muls2_i32(t2, t3, t2, t3);
3251 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
3252 tcg_temp_free_i32(t2);
3253 tcg_temp_free_i32(t3);
3254 }
3255 break;
3256 case R6_OPC_MULU:
3257 {
3258 TCGv_i32 t2 = tcg_temp_new_i32();
3259 TCGv_i32 t3 = tcg_temp_new_i32();
3260 tcg_gen_trunc_tl_i32(t2, t0);
3261 tcg_gen_trunc_tl_i32(t3, t1);
3262 tcg_gen_mul_i32(t2, t2, t3);
3263 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3264 tcg_temp_free_i32(t2);
3265 tcg_temp_free_i32(t3);
3266 }
3267 break;
3268 case R6_OPC_MUHU:
3269 {
3270 TCGv_i32 t2 = tcg_temp_new_i32();
3271 TCGv_i32 t3 = tcg_temp_new_i32();
3272 tcg_gen_trunc_tl_i32(t2, t0);
3273 tcg_gen_trunc_tl_i32(t3, t1);
3274 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3275 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
3276 tcg_temp_free_i32(t2);
3277 tcg_temp_free_i32(t3);
3278 }
3279 break;
3280 #if defined(TARGET_MIPS64)
3281 case R6_OPC_DDIV:
3282 {
3283 TCGv t2 = tcg_temp_new();
3284 TCGv t3 = tcg_temp_new();
3285 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3286 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3287 tcg_gen_and_tl(t2, t2, t3);
3288 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3289 tcg_gen_or_tl(t2, t2, t3);
3290 tcg_gen_movi_tl(t3, 0);
3291 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3292 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3293 tcg_temp_free(t3);
3294 tcg_temp_free(t2);
3295 }
3296 break;
3297 case R6_OPC_DMOD:
3298 {
3299 TCGv t2 = tcg_temp_new();
3300 TCGv t3 = tcg_temp_new();
3301 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3302 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3303 tcg_gen_and_tl(t2, t2, t3);
3304 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3305 tcg_gen_or_tl(t2, t2, t3);
3306 tcg_gen_movi_tl(t3, 0);
3307 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3308 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3309 tcg_temp_free(t3);
3310 tcg_temp_free(t2);
3311 }
3312 break;
3313 case R6_OPC_DDIVU:
3314 {
3315 TCGv t2 = tcg_const_tl(0);
3316 TCGv t3 = tcg_const_tl(1);
3317 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3318 tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
3319 tcg_temp_free(t3);
3320 tcg_temp_free(t2);
3321 }
3322 break;
3323 case R6_OPC_DMODU:
3324 {
3325 TCGv t2 = tcg_const_tl(0);
3326 TCGv t3 = tcg_const_tl(1);
3327 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3328 tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
3329 tcg_temp_free(t3);
3330 tcg_temp_free(t2);
3331 }
3332 break;
3333 case R6_OPC_DMUL:
3334 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
3335 break;
3336 case R6_OPC_DMUH:
3337 {
3338 TCGv t2 = tcg_temp_new();
3339 tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1);
3340 tcg_temp_free(t2);
3341 }
3342 break;
3343 case R6_OPC_DMULU:
3344 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
3345 break;
3346 case R6_OPC_DMUHU:
3347 {
3348 TCGv t2 = tcg_temp_new();
3349 tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1);
3350 tcg_temp_free(t2);
3351 }
3352 break;
3353 #endif
3354 default:
3355 MIPS_INVAL("r6 mul/div");
3356 generate_exception_end(ctx, EXCP_RI);
3357 goto out;
3358 }
3359 out:
3360 tcg_temp_free(t0);
3361 tcg_temp_free(t1);
3362 }
3363
3364 static void gen_muldiv(DisasContext *ctx, uint32_t opc,
3365 int acc, int rs, int rt)
3366 {
3367 TCGv t0, t1;
3368
3369 t0 = tcg_temp_new();
3370 t1 = tcg_temp_new();
3371
3372 gen_load_gpr(t0, rs);
3373 gen_load_gpr(t1, rt);
3374
3375 if (acc != 0) {
3376 check_dsp(ctx);
3377 }
3378
3379 switch (opc) {
3380 case OPC_DIV:
3381 {
3382 TCGv t2 = tcg_temp_new();
3383 TCGv t3 = tcg_temp_new();
3384 tcg_gen_ext32s_tl(t0, t0);
3385 tcg_gen_ext32s_tl(t1, t1);
3386 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3387 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3388 tcg_gen_and_tl(t2, t2, t3);
3389 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3390 tcg_gen_or_tl(t2, t2, t3);
3391 tcg_gen_movi_tl(t3, 0);
3392 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3393 tcg_gen_div_tl(cpu_LO[acc], t0, t1);
3394 tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
3395 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
3396 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
3397 tcg_temp_free(t3);
3398 tcg_temp_free(t2);
3399 }
3400 break;
3401 case OPC_DIVU:
3402 {
3403 TCGv t2 = tcg_const_tl(0);
3404 TCGv t3 = tcg_const_tl(1);
3405 tcg_gen_ext32u_tl(t0, t0);
3406 tcg_gen_ext32u_tl(t1, t1);
3407 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3408 tcg_gen_divu_tl(cpu_LO[acc], t0, t1);
3409 tcg_gen_remu_tl(cpu_HI[acc], t0, t1);
3410 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
3411 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
3412 tcg_temp_free(t3);
3413 tcg_temp_free(t2);
3414 }
3415 break;
3416 case OPC_MULT:
3417 {
3418 TCGv_i32 t2 = tcg_temp_new_i32();
3419 TCGv_i32 t3 = tcg_temp_new_i32();
3420 tcg_gen_trunc_tl_i32(t2, t0);
3421 tcg_gen_trunc_tl_i32(t3, t1);
3422 tcg_gen_muls2_i32(t2, t3, t2, t3);
3423 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3424 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3425 tcg_temp_free_i32(t2);
3426 tcg_temp_free_i32(t3);
3427 }
3428 break;
3429 case OPC_MULTU:
3430 {
3431 TCGv_i32 t2 = tcg_temp_new_i32();
3432 TCGv_i32 t3 = tcg_temp_new_i32();
3433 tcg_gen_trunc_tl_i32(t2, t0);
3434 tcg_gen_trunc_tl_i32(t3, t1);
3435 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3436 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3437 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3438 tcg_temp_free_i32(t2);
3439 tcg_temp_free_i32(t3);
3440 }
3441 break;
3442 #if defined(TARGET_MIPS64)
3443 case OPC_DDIV:
3444 {
3445 TCGv t2 = tcg_temp_new();
3446 TCGv t3 = tcg_temp_new();
3447 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3448 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3449 tcg_gen_and_tl(t2, t2, t3);
3450 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3451 tcg_gen_or_tl(t2, t2, t3);
3452 tcg_gen_movi_tl(t3, 0);
3453 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3454 tcg_gen_div_tl(cpu_LO[acc], t0, t1);
3455 tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
3456 tcg_temp_free(t3);
3457 tcg_temp_free(t2);
3458 }
3459 break;
3460 case OPC_DDIVU:
3461 {
3462 TCGv t2 = tcg_const_tl(0);
3463 TCGv t3 = tcg_const_tl(1);
3464 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3465 tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
3466 tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
3467 tcg_temp_free(t3);
3468 tcg_temp_free(t2);
3469 }
3470 break;
3471 case OPC_DMULT:
3472 tcg_gen_muls2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1);
3473 break;
3474 case OPC_DMULTU:
3475 tcg_gen_mulu2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1);
3476 break;
3477 #endif
3478 case OPC_MADD:
3479 {
3480 TCGv_i64 t2 = tcg_temp_new_i64();
3481 TCGv_i64 t3 = tcg_temp_new_i64();
3482
3483 tcg_gen_ext_tl_i64(t2, t0);
3484 tcg_gen_ext_tl_i64(t3, t1);
3485 tcg_gen_mul_i64(t2, t2, t3);
3486 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3487 tcg_gen_add_i64(t2, t2, t3);
3488 tcg_temp_free_i64(t3);
3489 gen_move_low32(cpu_LO[acc], t2);
3490 gen_move_high32(cpu_HI[acc], t2);
3491 tcg_temp_free_i64(t2);
3492 }
3493 break;
3494 case OPC_MADDU:
3495 {
3496 TCGv_i64 t2 = tcg_temp_new_i64();
3497 TCGv_i64 t3 = tcg_temp_new_i64();
3498
3499 tcg_gen_ext32u_tl(t0, t0);
3500 tcg_gen_ext32u_tl(t1, t1);
3501 tcg_gen_extu_tl_i64(t2, t0);
3502 tcg_gen_extu_tl_i64(t3, t1);
3503 tcg_gen_mul_i64(t2, t2, t3);
3504 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3505 tcg_gen_add_i64(t2, t2, t3);
3506 tcg_temp_free_i64(t3);
3507 gen_move_low32(cpu_LO[acc], t2);
3508 gen_move_high32(cpu_HI[acc], t2);
3509 tcg_temp_free_i64(t2);
3510 }
3511 break;
3512 case OPC_MSUB:
3513 {
3514 TCGv_i64 t2 = tcg_temp_new_i64();
3515 TCGv_i64 t3 = tcg_temp_new_i64();
3516
3517 tcg_gen_ext_tl_i64(t2, t0);
3518 tcg_gen_ext_tl_i64(t3, t1);
3519 tcg_gen_mul_i64(t2, t2, t3);
3520 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3521 tcg_gen_sub_i64(t2, t3, t2);
3522 tcg_temp_free_i64(t3);
3523 gen_move_low32(cpu_LO[acc], t2);
3524 gen_move_high32(cpu_HI[acc], t2);
3525 tcg_temp_free_i64(t2);
3526 }
3527 break;
3528 case OPC_MSUBU:
3529 {
3530 TCGv_i64 t2 = tcg_temp_new_i64();
3531 TCGv_i64 t3 = tcg_temp_new_i64();
3532
3533 tcg_gen_ext32u_tl(t0, t0);
3534 tcg_gen_ext32u_tl(t1, t1);
3535 tcg_gen_extu_tl_i64(t2, t0);
3536 tcg_gen_extu_tl_i64(t3, t1);
3537 tcg_gen_mul_i64(t2, t2, t3);
3538 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3539 tcg_gen_sub_i64(t2, t3, t2);
3540 tcg_temp_free_i64(t3);
3541 gen_move_low32(cpu_LO[acc], t2);
3542 gen_move_high32(cpu_HI[acc], t2);
3543 tcg_temp_free_i64(t2);
3544 }
3545 break;
3546 default:
3547 MIPS_INVAL("mul/div");
3548 generate_exception_end(ctx, EXCP_RI);
3549 goto out;
3550 }
3551 out:
3552 tcg_temp_free(t0);
3553 tcg_temp_free(t1);
3554 }
3555
3556 static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
3557 int rd, int rs, int rt)
3558 {
3559 TCGv t0 = tcg_temp_new();
3560 TCGv t1 = tcg_temp_new();
3561
3562 gen_load_gpr(t0, rs);
3563 gen_load_gpr(t1, rt);
3564
3565 switch (opc) {
3566 case OPC_VR54XX_MULS:
3567 gen_helper_muls(t0, cpu_env, t0, t1);
3568 break;
3569 case OPC_VR54XX_MULSU:
3570 gen_helper_mulsu(t0, cpu_env, t0, t1);
3571 break;
3572 case OPC_VR54XX_MACC:
3573 gen_helper_macc(t0, cpu_env, t0, t1);
3574 break;
3575 case OPC_VR54XX_MACCU:
3576 gen_helper_maccu(t0, cpu_env, t0, t1);
3577 break;
3578 case OPC_VR54XX_MSAC:
3579 gen_helper_msac(t0, cpu_env, t0, t1);
3580 break;
3581 case OPC_VR54XX_MSACU:
3582 gen_helper_msacu(t0, cpu_env, t0, t1);
3583 break;
3584 case OPC_VR54XX_MULHI:
3585 gen_helper_mulhi(t0, cpu_env, t0, t1);
3586 break;
3587 case OPC_VR54XX_MULHIU:
3588 gen_helper_mulhiu(t0, cpu_env, t0, t1);
3589 break;
3590 case OPC_VR54XX_MULSHI:
3591 gen_helper_mulshi(t0, cpu_env, t0, t1);
3592 break;
3593 case OPC_VR54XX_MULSHIU:
3594 gen_helper_mulshiu(t0, cpu_env, t0, t1);
3595 break;
3596 case OPC_VR54XX_MACCHI:
3597 gen_helper_macchi(t0, cpu_env, t0, t1);
3598 break;
3599 case OPC_VR54XX_MACCHIU:
3600 gen_helper_macchiu(t0, cpu_env, t0, t1);
3601 break;
3602 case OPC_VR54XX_MSACHI:
3603 gen_helper_msachi(t0, cpu_env, t0, t1);
3604 break;
3605 case OPC_VR54XX_MSACHIU:
3606 gen_helper_msachiu(t0, cpu_env, t0, t1);
3607 break;
3608 default:
3609 MIPS_INVAL("mul vr54xx");
3610 generate_exception_end(ctx, EXCP_RI);
3611 goto out;
3612 }
3613 gen_store_gpr(t0, rd);
3614
3615 out:
3616 tcg_temp_free(t0);
3617 tcg_temp_free(t1);
3618 }
3619
3620 static void gen_cl (DisasContext *ctx, uint32_t opc,
3621 int rd, int rs)
3622 {
3623 TCGv t0;
3624
3625 if (rd == 0) {
3626 /* Treat as NOP. */
3627 return;
3628 }
3629 t0 = cpu_gpr[rd];
3630 gen_load_gpr(t0, rs);
3631
3632 switch (opc) {
3633 case OPC_CLO:
3634 case R6_OPC_CLO:
3635 #if defined(TARGET_MIPS64)
3636 case OPC_DCLO:
3637 case R6_OPC_DCLO:
3638 #endif
3639 tcg_gen_not_tl(t0, t0);
3640 break;
3641 }
3642
3643 switch (opc) {
3644 case OPC_CLO:
3645 case R6_OPC_CLO:
3646 case OPC_CLZ:
3647 case R6_OPC_CLZ:
3648 tcg_gen_ext32u_tl(t0, t0);
3649 tcg_gen_clzi_tl(t0, t0, TARGET_LONG_BITS);
3650 tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32);
3651 break;
3652 #if defined(TARGET_MIPS64)
3653 case OPC_DCLO:
3654 case R6_OPC_DCLO:
3655 case OPC_DCLZ:
3656 case R6_OPC_DCLZ:
3657 tcg_gen_clzi_i64(t0, t0, 64);
3658 break;
3659 #endif
3660 }
3661 }
3662
3663 /* Godson integer instructions */
3664 static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
3665 int rd, int rs, int rt)
3666 {
3667 TCGv t0, t1;
3668
3669 if (rd == 0) {
3670 /* Treat as NOP. */
3671 return;
3672 }
3673
3674 switch (opc) {
3675 case OPC_MULT_G_2E:
3676 case OPC_MULT_G_2F:
3677 case OPC_MULTU_G_2E:
3678 case OPC_MULTU_G_2F:
3679 #if defined(TARGET_MIPS64)
3680 case OPC_DMULT_G_2E:
3681 case OPC_DMULT_G_2F:
3682 case OPC_DMULTU_G_2E:
3683 case OPC_DMULTU_G_2F:
3684 #endif
3685 t0 = tcg_temp_new();
3686 t1 = tcg_temp_new();
3687 break;
3688 default:
3689 t0 = tcg_temp_local_new();
3690 t1 = tcg_temp_local_new();
3691 break;
3692 }
3693
3694 gen_load_gpr(t0, rs);
3695 gen_load_gpr(t1, rt);
3696
3697 switch (opc) {
3698 case OPC_MULT_G_2E:
3699 case OPC_MULT_G_2F:
3700 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3701 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3702 break;
3703 case OPC_MULTU_G_2E:
3704 case OPC_MULTU_G_2F:
3705 tcg_gen_ext32u_tl(t0, t0);
3706 tcg_gen_ext32u_tl(t1, t1);
3707 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3708 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3709 break;
3710 case OPC_DIV_G_2E:
3711 case OPC_DIV_G_2F:
3712 {
3713 TCGLabel *l1 = gen_new_label();
3714 TCGLabel *l2 = gen_new_label();
3715 TCGLabel *l3 = gen_new_label();
3716 tcg_gen_ext32s_tl(t0, t0);
3717 tcg_gen_ext32s_tl(t1, t1);
3718 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3719 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3720 tcg_gen_br(l3);
3721 gen_set_label(l1);
3722 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
3723 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
3724 tcg_gen_mov_tl(cpu_gpr[rd], t0);
3725 tcg_gen_br(l3);
3726 gen_set_label(l2);
3727 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3728 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3729 gen_set_label(l3);
3730 }
3731 break;
3732 case OPC_DIVU_G_2E:
3733 case OPC_DIVU_G_2F:
3734 {
3735 TCGLabel *l1 = gen_new_label();
3736 TCGLabel *l2 = gen_new_label();
3737 tcg_gen_ext32u_tl(t0, t0);
3738 tcg_gen_ext32u_tl(t1, t1);
3739 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3740 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3741 tcg_gen_br(l2);
3742 gen_set_label(l1);
3743 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3744 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3745 gen_set_label(l2);
3746 }
3747 break;
3748 case OPC_MOD_G_2E:
3749 case OPC_MOD_G_2F:
3750 {
3751 TCGLabel *l1 = gen_new_label();
3752 TCGLabel *l2 = gen_new_label();
3753 TCGLabel *l3 = gen_new_label();
3754 tcg_gen_ext32u_tl(t0, t0);
3755 tcg_gen_ext32u_tl(t1, t1);
3756 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
3757 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
3758 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
3759 gen_set_label(l1);
3760 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3761 tcg_gen_br(l3);
3762 gen_set_label(l2);
3763 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3764 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3765 gen_set_label(l3);
3766 }
3767 break;
3768 case OPC_MODU_G_2E:
3769 case OPC_MODU_G_2F:
3770 {
3771 TCGLabel *l1 = gen_new_label();
3772 TCGLabel *l2 = gen_new_label();
3773 tcg_gen_ext32u_tl(t0, t0);
3774 tcg_gen_ext32u_tl(t1, t1);
3775 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3776 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3777 tcg_gen_br(l2);
3778 gen_set_label(l1);
3779 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3780 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3781 gen_set_label(l2);
3782 }
3783 break;
3784 #if defined(TARGET_MIPS64)
3785 case OPC_DMULT_G_2E:
3786 case OPC_DMULT_G_2F:
3787 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3788 break;
3789 case OPC_DMULTU_G_2E:
3790 case OPC_DMULTU_G_2F:
3791 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3792 break;
3793 case OPC_DDIV_G_2E:
3794 case OPC_DDIV_G_2F:
3795 {
3796 TCGLabel *l1 = gen_new_label();
3797 TCGLabel *l2 = gen_new_label();
3798 TCGLabel *l3 = gen_new_label();
3799 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3800 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3801 tcg_gen_br(l3);
3802 gen_set_label(l1);
3803 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
3804 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
3805 tcg_gen_mov_tl(cpu_gpr[rd], t0);
3806 tcg_gen_br(l3);
3807 gen_set_label(l2);
3808 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3809 gen_set_label(l3);
3810 }
3811 break;
3812 case OPC_DDIVU_G_2E:
3813 case OPC_DDIVU_G_2F:
3814 {
3815 TCGLabel *l1 = gen_new_label();
3816 TCGLabel *l2 = gen_new_label();
3817 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3818 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3819 tcg_gen_br(l2);
3820 gen_set_label(l1);
3821 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3822 gen_set_label(l2);
3823 }
3824 break;
3825 case OPC_DMOD_G_2E:
3826 case OPC_DMOD_G_2F:
3827 {
3828 TCGLabel *l1 = gen_new_label();
3829 TCGLabel *l2 = gen_new_label();
3830 TCGLabel *l3 = gen_new_label();
3831 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
3832 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
3833 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
3834 gen_set_label(l1);
3835 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3836 tcg_gen_br(l3);
3837 gen_set_label(l2);
3838 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3839 gen_set_label(l3);
3840 }
3841 break;
3842 case OPC_DMODU_G_2E:
3843 case OPC_DMODU_G_2F:
3844 {
3845 TCGLabel *l1 = gen_new_label();
3846 TCGLabel *l2 = gen_new_label();
3847 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3848 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3849 tcg_gen_br(l2);
3850 gen_set_label(l1);
3851 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3852 gen_set_label(l2);
3853 }
3854 break;
3855 #endif
3856 }
3857
3858 tcg_temp_free(t0);
3859 tcg_temp_free(t1);
3860 }
3861
3862 /* Loongson multimedia instructions */
3863 static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
3864 {
3865 uint32_t opc, shift_max;
3866 TCGv_i64 t0, t1;
3867
3868 opc = MASK_LMI(ctx->opcode);
3869 switch (opc) {
3870 case OPC_ADD_CP2:
3871 case OPC_SUB_CP2:
3872 case OPC_DADD_CP2:
3873 case OPC_DSUB_CP2:
3874 t0 = tcg_temp_local_new_i64();
3875 t1 = tcg_temp_local_new_i64();
3876 break;
3877 default:
3878 t0 = tcg_temp_new_i64();
3879 t1 = tcg_temp_new_i64();
3880 break;
3881 }
3882
3883 check_cp1_enabled(ctx);
3884 gen_load_fpr64(ctx, t0, rs);
3885 gen_load_fpr64(ctx, t1, rt);
3886
3887 #define LMI_HELPER(UP, LO) \
3888 case OPC_##UP: gen_helper_##LO(t0, t0, t1); break
3889 #define LMI_HELPER_1(UP, LO) \
3890 case OPC_##UP: gen_helper_##LO(t0, t0); break
3891 #define LMI_DIRECT(UP, LO, OP) \
3892 case OPC_##UP: tcg_gen_##OP##_i64(t0, t0, t1); break
3893
3894 switch (opc) {
3895 LMI_HELPER(PADDSH, paddsh);
3896 LMI_HELPER(PADDUSH, paddush);
3897 LMI_HELPER(PADDH, paddh);
3898 LMI_HELPER(PADDW, paddw);
3899 LMI_HELPER(PADDSB, paddsb);
3900 LMI_HELPER(PADDUSB, paddusb);
3901 LMI_HELPER(PADDB, paddb);
3902
3903 LMI_HELPER(PSUBSH, psubsh);
3904 LMI_HELPER(PSUBUSH, psubush);
3905 LMI_HELPER(PSUBH, psubh);
3906 LMI_HELPER(PSUBW, psubw);
3907 LMI_HELPER(PSUBSB, psubsb);
3908 LMI_HELPER(PSUBUSB, psubusb);
3909 LMI_HELPER(PSUBB, psubb);
3910
3911 LMI_HELPER(PSHUFH, pshufh);
3912 LMI_HELPER(PACKSSWH, packsswh);
3913 LMI_HELPER(PACKSSHB, packsshb);
3914 LMI_HELPER(PACKUSHB, packushb);
3915
3916 LMI_HELPER(PUNPCKLHW, punpcklhw);
3917 LMI_HELPER(PUNPCKHHW, punpckhhw);
3918 LMI_HELPER(PUNPCKLBH, punpcklbh);
3919 LMI_HELPER(PUNPCKHBH, punpckhbh);
3920 LMI_HELPER(PUNPCKLWD, punpcklwd);
3921 LMI_HELPER(PUNPCKHWD, punpckhwd);
3922
3923 LMI_HELPER(PAVGH, pavgh);
3924 LMI_HELPER(PAVGB, pavgb);
3925 LMI_HELPER(PMAXSH, pmaxsh);
3926 LMI_HELPER(PMINSH, pminsh);
3927 LMI_HELPER(PMAXUB, pmaxub);
3928 LMI_HELPER(PMINUB, pminub);
3929
3930 LMI_HELPER(PCMPEQW, pcmpeqw);
3931 LMI_HELPER(PCMPGTW, pcmpgtw);
3932 LMI_HELPER(PCMPEQH, pcmpeqh);
3933 LMI_HELPER(PCMPGTH, pcmpgth);
3934 LMI_HELPER(PCMPEQB, pcmpeqb);
3935 LMI_HELPER(PCMPGTB, pcmpgtb);
3936
3937 LMI_HELPER(PSLLW, psllw);
3938 LMI_HELPER(PSLLH, psllh);
3939 LMI_HELPER(PSRLW, psrlw);
3940 LMI_HELPER(PSRLH, psrlh);
3941 LMI_HELPER(PSRAW, psraw);
3942 LMI_HELPER(PSRAH, psrah);
3943
3944 LMI_HELPER(PMULLH, pmullh);
3945 LMI_HELPER(PMULHH, pmulhh);
3946 LMI_HELPER(PMULHUH, pmulhuh);
3947 LMI_HELPER(PMADDHW, pmaddhw);
3948
3949 LMI_HELPER(PASUBUB, pasubub);
3950 LMI_HELPER_1(BIADD, biadd);
3951 LMI_HELPER_1(PMOVMSKB, pmovmskb);
3952
3953 LMI_DIRECT(PADDD, paddd, add);
3954 LMI_DIRECT(PSUBD, psubd, sub);
3955 LMI_DIRECT(XOR_CP2, xor, xor);
3956 LMI_DIRECT(NOR_CP2, nor, nor);
3957 LMI_DIRECT(AND_CP2, and, and);
3958 LMI_DIRECT(OR_CP2, or, or);
3959
3960 case OPC_PANDN:
3961 tcg_gen_andc_i64(t0, t1, t0);
3962 break;
3963
3964 case OPC_PINSRH_0:
3965 tcg_gen_deposit_i64(t0, t0, t1, 0, 16);
3966 break;
3967 case OPC_PINSRH_1:
3968 tcg_gen_deposit_i64(t0, t0, t1, 16, 16);
3969 break;
3970 case OPC_PINSRH_2:
3971 tcg_gen_deposit_i64(t0, t0, t1, 32, 16);
3972 break;
3973 case OPC_PINSRH_3:
3974 tcg_gen_deposit_i64(t0, t0, t1, 48, 16);
3975 break;
3976
3977 case OPC_PEXTRH:
3978 tcg_gen_andi_i64(t1, t1, 3);
3979 tcg_gen_shli_i64(t1, t1, 4);
3980 tcg_gen_shr_i64(t0, t0, t1);
3981 tcg_gen_ext16u_i64(t0, t0);
3982 break;
3983
3984 case OPC_ADDU_CP2:
3985 tcg_gen_add_i64(t0, t0, t1);
3986 tcg_gen_ext32s_i64(t0, t0);
3987 break;
3988 case OPC_SUBU_CP2:
3989 tcg_gen_sub_i64(t0, t0, t1);
3990 tcg_gen_ext32s_i64(t0, t0);
3991 break;
3992
3993 case OPC_SLL_CP2:
3994 shift_max = 32;
3995 goto do_shift;
3996 case OPC_SRL_CP2:
3997 shift_max = 32;
3998 goto do_shift;
3999 case OPC_SRA_CP2:
4000 shift_max = 32;
4001 goto do_shift;
4002 case OPC_DSLL_CP2:
4003 shift_max = 64;
4004 goto do_shift;
4005 case OPC_DSRL_CP2:
4006 shift_max = 64;
4007 goto do_shift;
4008 case OPC_DSRA_CP2:
4009 shift_max = 64;
4010 goto do_shift;
4011 do_shift:
4012 /* Make sure shift count isn't TCG undefined behaviour. */
4013 tcg_gen_andi_i64(t1, t1, shift_max - 1);
4014
4015 switch (opc) {
4016 case OPC_SLL_CP2:
4017 case OPC_DSLL_CP2:
4018 tcg_gen_shl_i64(t0, t0, t1);
4019 break;
4020 case OPC_SRA_CP2:
4021 case OPC_DSRA_CP2:
4022 /* Since SRA is UndefinedResult without sign-extended inputs,
4023 we can treat SRA and DSRA the same. */
4024 tcg_gen_sar_i64(t0, t0, t1);
4025 break;
4026 case OPC_SRL_CP2:
4027 /* We want to shift in zeros for SRL; zero-extend first. */
4028 tcg_gen_ext32u_i64(t0, t0);
4029 /* FALLTHRU */
4030 case OPC_DSRL_CP2:
4031 tcg_gen_shr_i64(t0, t0, t1);
4032 break;
4033 }
4034
4035 if (shift_max == 32) {
4036 tcg_gen_ext32s_i64(t0, t0);
4037 }
4038
4039 /* Shifts larger than MAX produce zero. */
4040 tcg_gen_setcondi_i64(TCG_COND_LTU, t1, t1, shift_max);
4041 tcg_gen_neg_i64(t1, t1);
4042 tcg_gen_and_i64(t0, t0, t1);
4043 break;
4044
4045 case OPC_ADD_CP2:
4046 case OPC_DADD_CP2:
4047 {
4048 TCGv_i64 t2 = tcg_temp_new_i64();
4049 TCGLabel *lab = gen_new_label();
4050
4051 tcg_gen_mov_i64(t2, t0);
4052 tcg_gen_add_i64(t0, t1, t2);
4053 if (opc == OPC_ADD_CP2) {
4054 tcg_gen_ext32s_i64(t0, t0);
4055 }
4056 tcg_gen_xor_i64(t1, t1, t2);
4057 tcg_gen_xor_i64(t2, t2, t0);
4058 tcg_gen_andc_i64(t1, t2, t1);
4059 tcg_temp_free_i64(t2);
4060 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
4061 generate_exception(ctx, EXCP_OVERFLOW);
4062 gen_set_label(lab);
4063 break;
4064 }
4065
4066 case OPC_SUB_CP2:
4067 case OPC_DSUB_CP2:
4068 {
4069 TCGv_i64 t2 = tcg_temp_new_i64();
4070 TCGLabel *lab = gen_new_label();
4071
4072 tcg_gen_mov_i64(t2, t0);
4073 tcg_gen_sub_i64(t0, t1, t2);
4074 if (opc == OPC_SUB_CP2) {
4075 tcg_gen_ext32s_i64(t0, t0);
4076 }
4077 tcg_gen_xor_i64(t1, t1, t2);
4078 tcg_gen_xor_i64(t2, t2, t0);
4079 tcg_gen_and_i64(t1, t1, t2);
4080 tcg_temp_free_i64(t2);
4081 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
4082 generate_exception(ctx, EXCP_OVERFLOW);
4083 gen_set_label(lab);
4084 break;
4085 }
4086
4087 case OPC_PMULUW:
4088 tcg_gen_ext32u_i64(t0, t0);
4089 tcg_gen_ext32u_i64(t1, t1);
4090 tcg_gen_mul_i64(t0, t0, t1);
4091 break;
4092
4093 case OPC_SEQU_CP2:
4094 case OPC_SEQ_CP2:
4095 case OPC_SLTU_CP2:
4096 case OPC_SLT_CP2:
4097 case OPC_SLEU_CP2:
4098 case OPC_SLE_CP2:
4099 /* ??? Document is unclear: Set FCC[CC]. Does that mean the
4100 FD field is the CC field? */
4101 default:
4102 MIPS_INVAL("loongson_cp2");
4103 generate_exception_end(ctx, EXCP_RI);
4104 return;
4105 }
4106
4107 #undef LMI_HELPER
4108 #undef LMI_DIRECT
4109
4110 gen_store_fpr64(ctx, t0, rd);
4111
4112 tcg_temp_free_i64(t0);
4113 tcg_temp_free_i64(t1);
4114 }
4115
4116 /* Traps */
4117 static void gen_trap (DisasContext *ctx, uint32_t opc,
4118 int rs, int rt, int16_t imm)
4119 {
4120 int cond;
4121 TCGv t0 = tcg_temp_new();
4122 TCGv t1 = tcg_temp_new();
4123
4124 cond = 0;
4125 /* Load needed operands */
4126 switch (opc) {
4127 case OPC_TEQ:
4128 case OPC_TGE:
4129 case OPC_TGEU:
4130 case OPC_TLT:
4131 case OPC_TLTU:
4132 case OPC_TNE:
4133 /* Compare two registers */
4134 if (rs != rt) {
4135 gen_load_gpr(t0, rs);
4136 gen_load_gpr(t1, rt);
4137 cond = 1;
4138 }
4139 break;
4140 case OPC_TEQI:
4141 case OPC_TGEI:
4142 case OPC_TGEIU:
4143 case OPC_TLTI:
4144 case OPC_TLTIU:
4145 case OPC_TNEI:
4146 /* Compare register to immediate */
4147 if (rs != 0 || imm != 0) {
4148 gen_load_gpr(t0, rs);
4149 tcg_gen_movi_tl(t1, (int32_t)imm);
4150 cond = 1;
4151 }
4152 break;
4153 }
4154 if (cond == 0) {
4155 switch (opc) {
4156 case OPC_TEQ: /* rs == rs */
4157 case OPC_TEQI: /* r0 == 0 */
4158 case OPC_TGE: /* rs >= rs */
4159 case OPC_TGEI: /* r0 >= 0 */
4160 case OPC_TGEU: /* rs >= rs unsigned */
4161 case OPC_TGEIU: /* r0 >= 0 unsigned */
4162 /* Always trap */
4163 generate_exception_end(ctx, EXCP_TRAP);
4164 break;
4165 case OPC_TLT: /* rs < rs */
4166 case OPC_TLTI: /* r0 < 0 */
4167 case OPC_TLTU: /* rs < rs unsigned */
4168 case OPC_TLTIU: /* r0 < 0 unsigned */
4169 case OPC_TNE: /* rs != rs */
4170 case OPC_TNEI: /* r0 != 0 */
4171 /* Never trap: treat as NOP. */
4172 break;
4173 }
4174 } else {
4175 TCGLabel *l1 = gen_new_label();
4176
4177 switch (opc) {
4178 case OPC_TEQ:
4179 case OPC_TEQI:
4180 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1);
4181 break;
4182 case OPC_TGE:
4183 case OPC_TGEI:
4184 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
4185 break;
4186 case OPC_TGEU:
4187 case OPC_TGEIU:
4188 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
4189 break;
4190 case OPC_TLT:
4191 case OPC_TLTI:
4192 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4193 break;
4194 case OPC_TLTU:
4195 case OPC_TLTIU:
4196 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
4197 break;
4198 case OPC_TNE:
4199 case OPC_TNEI:
4200 tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1);
4201 break;
4202 }
4203 generate_exception(ctx, EXCP_TRAP);
4204 gen_set_label(l1);
4205 }
4206 tcg_temp_free(t0);
4207 tcg_temp_free(t1);
4208 }
4209
4210 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
4211 {
4212 if (unlikely(ctx->singlestep_enabled)) {
4213 return false;
4214 }
4215
4216 #ifndef CONFIG_USER_ONLY
4217 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
4218 #else
4219 return true;
4220 #endif
4221 }
4222
4223 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4224 {
4225 if (use_goto_tb(ctx, dest)) {
4226 tcg_gen_goto_tb(n);
4227 gen_save_pc(dest);
4228 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
4229 } else {
4230 gen_save_pc(dest);
4231 if (ctx->singlestep_enabled) {
4232 save_cpu_state(ctx, 0);
4233 gen_helper_raise_exception_debug(cpu_env);
4234 }
4235 tcg_gen_exit_tb(0);
4236 }
4237 }
4238
4239 /* Branches (before delay slot) */
4240 static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
4241 int insn_bytes,
4242 int rs, int rt, int32_t offset,
4243 int delayslot_size)
4244 {
4245 target_ulong btgt = -1;
4246 int blink = 0;
4247 int bcond_compute = 0;
4248 TCGv t0 = tcg_temp_new();
4249 TCGv t1 = tcg_temp_new();
4250
4251 if (ctx->hflags & MIPS_HFLAG_BMASK) {
4252 #ifdef MIPS_DEBUG_DISAS
4253 LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
4254 TARGET_FMT_lx "\n", ctx->pc);
4255 #endif
4256 generate_exception_end(ctx, EXCP_RI);
4257 goto out;
4258 }
4259
4260 /* Load needed operands */
4261 switch (opc) {
4262 case OPC_BEQ:
4263 case OPC_BEQL:
4264 case OPC_BNE:
4265 case OPC_BNEL:
4266 /* Compare two registers */
4267 if (rs != rt) {
4268 gen_load_gpr(t0, rs);
4269 gen_load_gpr(t1, rt);
4270 bcond_compute = 1;
4271 }
4272 btgt = ctx->pc + insn_bytes + offset;
4273 break;
4274 case OPC_BGEZ:
4275 case OPC_BGEZAL:
4276 case OPC_BGEZALL:
4277 case OPC_BGEZL:
4278 case OPC_BGTZ:
4279 case OPC_BGTZL:
4280 case OPC_BLEZ:
4281 case OPC_BLEZL:
4282 case OPC_BLTZ:
4283 case OPC_BLTZAL:
4284 case OPC_BLTZALL:
4285 case OPC_BLTZL:
4286 /* Compare to zero */
4287 if (rs != 0) {
4288 gen_load_gpr(t0, rs);
4289 bcond_compute = 1;
4290 }
4291 btgt = ctx->pc + insn_bytes + offset;
4292 break;
4293 case OPC_BPOSGE32:
4294 #if defined(TARGET_MIPS64)
4295 case OPC_BPOSGE64:
4296 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
4297 #else
4298 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
4299 #endif
4300 bcond_compute = 1;
4301 btgt = ctx->pc + insn_bytes + offset;
4302 break;
4303 case OPC_J:
4304 case OPC_JAL:
4305 case OPC_JALX:
4306 /* Jump to immediate */
4307 btgt = ((ctx->pc + insn_bytes) & (int32_t)0xF0000000) | (uint32_t)offset;
4308 break;
4309 case OPC_JR:
4310 case OPC_JALR:
4311 /* Jump to register */
4312 if (offset != 0 && offset != 16) {
4313 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
4314 others are reserved. */
4315 MIPS_INVAL("jump hint");
4316 generate_exception_end(ctx, EXCP_RI);
4317 goto out;
4318 }
4319 gen_load_gpr(btarget, rs);
4320 break;
4321 default:
4322 MIPS_INVAL("branch/jump");
4323 generate_exception_end(ctx, EXCP_RI);
4324 goto out;
4325 }
4326 if (bcond_compute == 0) {
4327 /* No condition to be computed */
4328 switch (opc) {
4329 case OPC_BEQ: /* rx == rx */
4330 case OPC_BEQL: /* rx == rx likely */
4331 case OPC_BGEZ: /* 0 >= 0 */
4332 case OPC_BGEZL: /* 0 >= 0 likely */
4333 case OPC_BLEZ: /* 0 <= 0 */
4334 case OPC_BLEZL: /* 0 <= 0 likely */
4335 /* Always take */
4336 ctx->hflags |= MIPS_HFLAG_B;
4337 break;
4338 case OPC_BGEZAL: /* 0 >= 0 */
4339 case OPC_BGEZALL: /* 0 >= 0 likely */
4340 /* Always take and link */
4341 blink = 31;
4342 ctx->hflags |= MIPS_HFLAG_B;
4343 break;
4344 case OPC_BNE: /* rx != rx */
4345 case OPC_BGTZ: /* 0 > 0 */
4346 case OPC_BLTZ: /* 0 < 0 */
4347 /* Treat as NOP. */
4348 goto out;
4349 case OPC_BLTZAL: /* 0 < 0 */
4350 /* Handle as an unconditional branch to get correct delay
4351 slot checking. */
4352 blink = 31;
4353 btgt = ctx->pc + insn_bytes + delayslot_size;
4354 ctx->hflags |= MIPS_HFLAG_B;
4355 break;
4356 case OPC_BLTZALL: /* 0 < 0 likely */
4357 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8);
4358 /* Skip the instruction in the delay slot */
4359 ctx->pc += 4;
4360 goto out;
4361 case OPC_BNEL: /* rx != rx likely */
4362 case OPC_BGTZL: /* 0 > 0 likely */
4363 case OPC_BLTZL: /* 0 < 0 likely */
4364 /* Skip the instruction in the delay slot */
4365 ctx->pc += 4;
4366 goto out;
4367 case OPC_J:
4368 ctx->hflags |= MIPS_HFLAG_B;
4369 break;
4370 case OPC_JALX:
4371 ctx->hflags |= MIPS_HFLAG_BX;
4372 /* Fallthrough */
4373 case OPC_JAL:
4374 blink = 31;
4375 ctx->hflags |= MIPS_HFLAG_B;
4376 break;
4377 case OPC_JR:
4378 ctx->hflags |= MIPS_HFLAG_BR;
4379 break;
4380 case OPC_JALR:
4381 blink = rt;
4382 ctx->hflags |= MIPS_HFLAG_BR;
4383 break;
4384 default:
4385 MIPS_INVAL("branch/jump");
4386 generate_exception_end(ctx, EXCP_RI);
4387 goto out;
4388 }
4389 } else {
4390 switch (opc) {
4391 case OPC_BEQ:
4392 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
4393 goto not_likely;
4394 case OPC_BEQL:
4395 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
4396 goto likely;
4397 case OPC_BNE:
4398 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
4399 goto not_likely;
4400 case OPC_BNEL:
4401 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
4402 goto likely;
4403 case OPC_BGEZ:
4404 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
4405 goto not_likely;
4406 case OPC_BGEZL:
4407 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
4408 goto likely;
4409 case OPC_BGEZAL:
4410 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
4411 blink = 31;
4412 goto not_likely;
4413 case OPC_BGEZALL:
4414 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
4415 blink = 31;
4416 goto likely;
4417 case OPC_BGTZ:
4418 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
4419 goto not_likely;
4420 case OPC_BGTZL:
4421 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
4422 goto likely;
4423 case OPC_BLEZ:
4424 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
4425 goto not_likely;
4426 case OPC_BLEZL:
4427 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
4428 goto likely;
4429 case OPC_BLTZ:
4430 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
4431 goto not_likely;
4432 case OPC_BLTZL:
4433 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
4434 goto likely;
4435 case OPC_BPOSGE32:
4436 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
4437 goto not_likely;
4438 #if defined(TARGET_MIPS64)
4439 case OPC_BPOSGE64:
4440 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64);
4441 goto not_likely;
4442 #endif
4443 case OPC_BLTZAL:
4444 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
4445 blink = 31;
4446 not_likely:
4447 ctx->hflags |= MIPS_HFLAG_BC;
4448 break;
4449 case OPC_BLTZALL:
4450 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
4451 blink = 31;
4452 likely:
4453 ctx->hflags |= MIPS_HFLAG_BL;
4454 break;
4455 default:
4456 MIPS_INVAL("conditional branch/jump");
4457 generate_exception_end(ctx, EXCP_RI);
4458 goto out;
4459 }
4460 }
4461
4462 ctx->btarget = btgt;
4463
4464 switch (delayslot_size) {
4465 case 2:
4466 ctx->hflags |= MIPS_HFLAG_BDS16;
4467 break;
4468 case 4:
4469 ctx->hflags |= MIPS_HFLAG_BDS32;
4470 break;
4471 }
4472
4473 if (blink > 0) {
4474 int post_delay = insn_bytes + delayslot_size;
4475 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
4476
4477 tcg_gen_movi_tl(cpu_gpr[blink], ctx->pc + post_delay + lowbit);
4478 }
4479
4480 out:
4481 if (insn_bytes == 2)
4482 ctx->hflags |= MIPS_HFLAG_B16;
4483 tcg_temp_free(t0);
4484 tcg_temp_free(t1);
4485 }
4486
4487 /* special3 bitfield operations */
4488 static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
4489 int rs, int lsb, int msb)
4490 {
4491 TCGv t0 = tcg_temp_new();
4492 TCGv t1 = tcg_temp_new();
4493
4494 gen_load_gpr(t1, rs);
4495 switch (opc) {
4496 case OPC_EXT:
4497 if (lsb + msb > 31) {
4498 goto fail;
4499 }
4500 if (msb != 31) {
4501 tcg_gen_extract_tl(t0, t1, lsb, msb + 1);
4502 } else {
4503 /* The two checks together imply that lsb == 0,
4504 so this is a simple sign-extension. */
4505 tcg_gen_ext32s_tl(t0, t1);
4506 }
4507 break;
4508 #if defined(TARGET_MIPS64)
4509 case OPC_DEXTU:
4510 lsb += 32;
4511 goto do_dext;
4512 case OPC_DEXTM:
4513 msb += 32;
4514 goto do_dext;
4515 case OPC_DEXT:
4516 do_dext:
4517 if (lsb + msb > 63) {
4518 goto fail;
4519 }
4520 tcg_gen_extract_tl(t0, t1, lsb, msb + 1);
4521 break;
4522 #endif
4523 case OPC_INS:
4524 if (lsb > msb) {
4525 goto fail;
4526 }
4527 gen_load_gpr(t0, rt);
4528 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
4529 tcg_gen_ext32s_tl(t0, t0);
4530 break;
4531 #if defined(TARGET_MIPS64)
4532 case OPC_DINSU:
4533 lsb += 32;
4534 /* FALLTHRU */
4535 case OPC_DINSM:
4536 msb += 32;
4537 /* FALLTHRU */
4538 case OPC_DINS:
4539 if (lsb > msb) {
4540 goto fail;
4541 }
4542 gen_load_gpr(t0, rt);
4543 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
4544 break;
4545 #endif
4546 default:
4547 fail:
4548 MIPS_INVAL("bitops");
4549 generate_exception_end(ctx, EXCP_RI);
4550 tcg_temp_free(t0);
4551 tcg_temp_free(t1);
4552 return;
4553 }
4554 gen_store_gpr(t0, rt);
4555 tcg_temp_free(t0);
4556 tcg_temp_free(t1);
4557 }
4558
4559 static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
4560 {
4561 TCGv t0;
4562
4563 if (rd == 0) {
4564 /* If no destination, treat it as a NOP. */
4565 return;
4566 }
4567
4568 t0 = tcg_temp_new();
4569 gen_load_gpr(t0, rt);
4570 switch (op2) {
4571 case OPC_WSBH:
4572 {
4573 TCGv t1 = tcg_temp_new();
4574
4575 tcg_gen_shri_tl(t1, t0, 8);
4576 tcg_gen_andi_tl(t1, t1, 0x00FF00FF);
4577 tcg_gen_shli_tl(t0, t0, 8);
4578 tcg_gen_andi_tl(t0, t0, ~0x00FF00FF);
4579 tcg_gen_or_tl(t0, t0, t1);
4580 tcg_temp_free(t1);
4581 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
4582 }
4583 break;
4584 case OPC_SEB:
4585 tcg_gen_ext8s_tl(cpu_gpr[rd], t0);
4586 break;
4587 case OPC_SEH:
4588 tcg_gen_ext16s_tl(cpu_gpr[rd], t0);
4589 break;
4590 #if defined(TARGET_MIPS64)
4591 case OPC_DSBH:
4592 {
4593 TCGv t1 = tcg_temp_new();
4594
4595 tcg_gen_shri_tl(t1, t0, 8);
4596 tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL);
4597 tcg_gen_shli_tl(t0, t0, 8);
4598 tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL);
4599 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
4600 tcg_temp_free(t1);
4601 }
4602 break;
4603 case OPC_DSHD:
4604 {
4605 TCGv t1 = tcg_temp_new();
4606
4607 tcg_gen_shri_tl(t1, t0, 16);
4608 tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL);
4609 tcg_gen_shli_tl(t0, t0, 16);
4610 tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL);
4611 tcg_gen_or_tl(t0, t0, t1);
4612 tcg_gen_shri_tl(t1, t0, 32);
4613 tcg_gen_shli_tl(t0, t0, 32);
4614 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
4615 tcg_temp_free(t1);
4616 }
4617 break;
4618 #endif
4619 default:
4620 MIPS_INVAL("bsfhl");
4621 generate_exception_end(ctx, EXCP_RI);
4622 tcg_temp_free(t0);
4623 return;
4624 }
4625 tcg_temp_free(t0);
4626 }
4627
4628 static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt,
4629 int imm2)
4630 {
4631 TCGv t0;
4632 TCGv t1;
4633 if (rd == 0) {
4634 /* Treat as NOP. */
4635 return;
4636 }
4637 t0 = tcg_temp_new();
4638 t1 = tcg_temp_new();
4639 gen_load_gpr(t0, rs);
4640 gen_load_gpr(t1, rt);
4641 tcg_gen_shli_tl(t0, t0, imm2 + 1);
4642 tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
4643 if (opc == OPC_LSA) {
4644 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4645 }
4646
4647 tcg_temp_free(t1);
4648 tcg_temp_free(t0);
4649
4650 return;
4651 }
4652
4653 static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
4654 int bp)
4655 {
4656 TCGv t0;
4657 if (rd == 0) {
4658 /* Treat as NOP. */
4659 return;
4660 }
4661 t0 = tcg_temp_new();
4662 gen_load_gpr(t0, rt);
4663 if (bp == 0) {
4664 switch (opc) {
4665 case OPC_ALIGN:
4666 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
4667 break;
4668 #if defined(TARGET_MIPS64)
4669 case OPC_DALIGN:
4670 tcg_gen_mov_tl(cpu_gpr[rd], t0);
4671 break;
4672 #endif
4673 }
4674 } else {
4675 TCGv t1 = tcg_temp_new();
4676 gen_load_gpr(t1, rs);
4677 switch (opc) {
4678 case OPC_ALIGN:
4679 {
4680 TCGv_i64 t2 = tcg_temp_new_i64();
4681 tcg_gen_concat_tl_i64(t2, t1, t0);
4682 tcg_gen_shri_i64(t2, t2, 8 * (4 - bp));
4683 gen_move_low32(cpu_gpr[rd], t2);
4684 tcg_temp_free_i64(t2);
4685 }
4686 break;
4687 #if defined(TARGET_MIPS64)
4688 case OPC_DALIGN:
4689 tcg_gen_shli_tl(t0, t0, 8 * bp);
4690 tcg_gen_shri_tl(t1, t1, 8 * (8 - bp));
4691 tcg_gen_or_tl(cpu_gpr[rd], t1, t0);
4692 break;
4693 #endif
4694 }
4695 tcg_temp_free(t1);
4696 }
4697
4698 tcg_temp_free(t0);
4699 }
4700
4701 static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt)
4702 {
4703 TCGv t0;
4704 if (rd == 0) {
4705 /* Treat as NOP. */
4706 return;
4707 }
4708 t0 = tcg_temp_new();
4709 gen_load_gpr(t0, rt);
4710 switch (opc) {
4711 case OPC_BITSWAP:
4712 gen_helper_bitswap(cpu_gpr[rd], t0);
4713 break;
4714 #if defined(TARGET_MIPS64)
4715 case OPC_DBITSWAP:
4716 gen_helper_dbitswap(cpu_gpr[rd], t0);
4717 break;
4718 #endif
4719 }
4720 tcg_temp_free(t0);
4721 }
4722
4723 #ifndef CONFIG_USER_ONLY
4724 /* CP0 (MMU and control) */
4725 static inline void gen_mthc0_entrylo(TCGv arg, target_ulong off)
4726 {
4727 TCGv_i64 t0 = tcg_temp_new_i64();
4728 TCGv_i64 t1 = tcg_temp_new_i64();
4729
4730 tcg_gen_ext_tl_i64(t0, arg);
4731 tcg_gen_ld_i64(t1, cpu_env, off);
4732 #if defined(TARGET_MIPS64)
4733 tcg_gen_deposit_i64(t1, t1, t0, 30, 32);
4734 #else
4735 tcg_gen_concat32_i64(t1, t1, t0);
4736 #endif
4737 tcg_gen_st_i64(t1, cpu_env, off);
4738 tcg_temp_free_i64(t1);
4739 tcg_temp_free_i64(t0);
4740 }
4741
4742 static inline void gen_mthc0_store64(TCGv arg, target_ulong off)
4743 {
4744 TCGv_i64 t0 = tcg_temp_new_i64();
4745 TCGv_i64 t1 = tcg_temp_new_i64();
4746
4747 tcg_gen_ext_tl_i64(t0, arg);
4748 tcg_gen_ld_i64(t1, cpu_env, off);
4749 tcg_gen_concat32_i64(t1, t1, t0);
4750 tcg_gen_st_i64(t1, cpu_env, off);
4751 tcg_temp_free_i64(t1);
4752 tcg_temp_free_i64(t0);
4753 }
4754
4755 static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off)
4756 {
4757 TCGv_i64 t0 = tcg_temp_new_i64();
4758
4759 tcg_gen_ld_i64(t0, cpu_env, off);
4760 #if defined(TARGET_MIPS64)
4761 tcg_gen_shri_i64(t0, t0, 30);
4762 #else
4763 tcg_gen_shri_i64(t0, t0, 32);
4764 #endif
4765 gen_move_low32(arg, t0);
4766 tcg_temp_free_i64(t0);
4767 }
4768
4769 static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift)
4770 {
4771 TCGv_i64 t0 = tcg_temp_new_i64();
4772
4773 tcg_gen_ld_i64(t0, cpu_env, off);
4774 tcg_gen_shri_i64(t0, t0, 32 + shift);
4775 gen_move_low32(arg, t0);
4776 tcg_temp_free_i64(t0);
4777 }
4778
4779 static inline void gen_mfc0_load32 (TCGv arg, target_ulong off)
4780 {
4781 TCGv_i32 t0 = tcg_temp_new_i32();
4782
4783 tcg_gen_ld_i32(t0, cpu_env, off);
4784 tcg_gen_ext_i32_tl(arg, t0);
4785 tcg_temp_free_i32(t0);
4786 }
4787
4788 static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
4789 {
4790 tcg_gen_ld_tl(arg, cpu_env, off);
4791 tcg_gen_ext32s_tl(arg, arg);
4792 }
4793
4794 static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
4795 {
4796 TCGv_i32 t0 = tcg_temp_new_i32();
4797
4798 tcg_gen_trunc_tl_i32(t0, arg);
4799 tcg_gen_st_i32(t0, cpu_env, off);
4800 tcg_temp_free_i32(t0);
4801 }
4802
4803 #define CP0_CHECK(c) \
4804 do { \
4805 if (!(c)) { \
4806 goto cp0_unimplemented; \
4807 } \
4808 } while (0)
4809
4810 static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
4811 {
4812 const char *rn = "invalid";
4813
4814 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
4815
4816 switch (reg) {
4817 case 2:
4818 switch (sel) {
4819 case 0:
4820 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
4821 rn = "EntryLo0";
4822 break;
4823 default:
4824 goto cp0_unimplemented;
4825 }
4826 break;
4827 case 3:
4828 switch (sel) {
4829 case 0:
4830 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
4831 rn = "EntryLo1";
4832 break;
4833 default:
4834 goto cp0_unimplemented;
4835 }
4836 break;
4837 case 17:
4838 switch (sel) {
4839 case 0:
4840 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, lladdr),
4841 ctx->CP0_LLAddr_shift);
4842 rn = "LLAddr";
4843 break;
4844 case 1:
4845 CP0_CHECK(ctx->mrp);
4846 gen_helper_mfhc0_maar(arg, cpu_env);
4847 rn = "MAAR";
4848 break;
4849 default:
4850 goto cp0_unimplemented;
4851 }
4852 break;
4853 case 28:
4854 switch (sel) {
4855 case 0:
4856 case 2:
4857 case 4:
4858 case 6:
4859 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_TagLo), 0);
4860 rn = "TagLo";
4861 break;
4862 default:
4863 goto cp0_unimplemented;
4864 }
4865 break;
4866 default:
4867 goto cp0_unimplemented;
4868 }
4869
4870 (void)rn; /* avoid a compiler warning */
4871 LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
4872 return;
4873
4874 cp0_unimplemented:
4875 qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
4876 tcg_gen_movi_tl(arg, 0);
4877 }
4878
4879 static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
4880 {
4881 const char *rn = "invalid";
4882 uint64_t mask = ctx->PAMask >> 36;
4883
4884 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
4885
4886 switch (reg) {
4887 case 2:
4888 switch (sel) {
4889 case 0:
4890 tcg_gen_andi_tl(arg, arg, mask);
4891 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
4892 rn = "EntryLo0";
4893 break;
4894 default:
4895 goto cp0_unimplemented;
4896 }
4897 break;
4898 case 3:
4899 switch (sel) {
4900 case 0:
4901 tcg_gen_andi_tl(arg, arg, mask);
4902 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
4903 rn = "EntryLo1";
4904 break;
4905 default:
4906 goto cp0_unimplemented;
4907 }
4908 break;
4909 case 17:
4910 switch (sel) {
4911 case 0:
4912 /* LLAddr is read-only (the only exception is bit 0 if LLB is
4913 supported); the CP0_LLAddr_rw_bitmask does not seem to be
4914 relevant for modern MIPS cores supporting MTHC0, therefore
4915 treating MTHC0 to LLAddr as NOP. */
4916 rn = "LLAddr";
4917 break;
4918 case 1:
4919 CP0_CHECK(ctx->mrp);
4920 gen_helper_mthc0_maar(cpu_env, arg);
4921 rn = "MAAR";
4922 break;
4923 default:
4924 goto cp0_unimplemented;
4925 }
4926 break;
4927 case 28:
4928 switch (sel) {
4929 case 0:
4930 case 2:
4931 case 4:
4932 case 6:
4933 tcg_gen_andi_tl(arg, arg, mask);
4934 gen_mthc0_store64(arg, offsetof(CPUMIPSState, CP0_TagLo));
4935 rn = "TagLo";
4936 break;
4937 default:
4938 goto cp0_unimplemented;
4939 }
4940 break;
4941 default:
4942 goto cp0_unimplemented;
4943 }
4944
4945 (void)rn; /* avoid a compiler warning */
4946 cp0_unimplemented:
4947 qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
4948 }
4949
4950 static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
4951 {
4952 if (ctx->insn_flags & ISA_MIPS32R6) {
4953 tcg_gen_movi_tl(arg, 0);
4954 } else {
4955 tcg_gen_movi_tl(arg, ~0);
4956 }
4957 }
4958
4959 static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
4960 {
4961 const char *rn = "invalid";
4962
4963 if (sel != 0)
4964 check_insn(ctx, ISA_MIPS32);
4965
4966 switch (reg) {
4967 case 0:
4968 switch (sel) {
4969 case 0:
4970 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
4971 rn = "Index";
4972 break;
4973 case 1:
4974 CP0_CHECK(ctx->insn_flags & ASE_MT);
4975 gen_helper_mfc0_mvpcontrol(arg, cpu_env);
4976 rn = "MVPControl";
4977 break;
4978 case 2:
4979 CP0_CHECK(ctx->insn_flags & ASE_MT);
4980 gen_helper_mfc0_mvpconf0(arg, cpu_env);
4981 rn = "MVPConf0";
4982 break;
4983 case 3:
4984 CP0_CHECK(ctx->insn_flags & ASE_MT);
4985 gen_helper_mfc0_mvpconf1(arg, cpu_env);
4986 rn = "MVPConf1";
4987 break;
4988 case 4:
4989 CP0_CHECK(ctx->vp);
4990 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
4991 rn = "VPControl";
4992 break;
4993 default:
4994 goto cp0_unimplemented;
4995 }
4996 break;
4997 case 1:
4998 switch (sel) {
4999 case 0:
5000 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
5001 gen_helper_mfc0_random(arg, cpu_env);
5002 rn = "Random";
5003 break;
5004 case 1:
5005 CP0_CHECK(ctx->insn_flags & ASE_MT);
5006 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
5007 rn = "VPEControl";
5008 break;
5009 case 2:
5010 CP0_CHECK(ctx->insn_flags & ASE_MT);
5011 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
5012 rn = "VPEConf0";
5013 break;
5014 case 3:
5015 CP0_CHECK(ctx->insn_flags & ASE_MT);
5016 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
5017 rn = "VPEConf1";
5018 break;
5019 case 4:
5020 CP0_CHECK(ctx->insn_flags & ASE_MT);
5021 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
5022 rn = "YQMask";
5023 break;
5024 case 5:
5025 CP0_CHECK(ctx->insn_flags & ASE_MT);
5026 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
5027 rn = "VPESchedule";
5028 break;
5029 case 6:
5030 CP0_CHECK(ctx->insn_flags & ASE_MT);
5031 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
5032 rn = "VPEScheFBack";
5033 break;
5034 case 7:
5035 CP0_CHECK(ctx->insn_flags & ASE_MT);
5036 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
5037 rn = "VPEOpt";
5038 break;
5039 default:
5040 goto cp0_unimplemented;
5041 }
5042 break;
5043 case 2:
5044 switch (sel) {
5045 case 0:
5046 {
5047 TCGv_i64 tmp = tcg_temp_new_i64();
5048 tcg_gen_ld_i64(tmp, cpu_env,
5049 offsetof(CPUMIPSState, CP0_EntryLo0));
5050 #if defined(TARGET_MIPS64)
5051 if (ctx->rxi) {
5052 /* Move RI/XI fields to bits 31:30 */
5053 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI);
5054 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2);
5055 }
5056 #endif
5057 gen_move_low32(arg, tmp);
5058 tcg_temp_free_i64(tmp);
5059 }
5060 rn = "EntryLo0";
5061 break;
5062 case 1:
5063 CP0_CHECK(ctx->insn_flags & ASE_MT);
5064 gen_helper_mfc0_tcstatus(arg, cpu_env);
5065 rn = "TCStatus";
5066 break;
5067 case 2:
5068 CP0_CHECK(ctx->insn_flags & ASE_MT);
5069 gen_helper_mfc0_tcbind(arg, cpu_env);
5070 rn = "TCBind";
5071 break;
5072 case 3:
5073 CP0_CHECK(ctx->insn_flags & ASE_MT);
5074 gen_helper_mfc0_tcrestart(arg, cpu_env);
5075 rn = "TCRestart";
5076 break;
5077 case 4:
5078 CP0_CHECK(ctx->insn_flags & ASE_MT);
5079 gen_helper_mfc0_tchalt(arg, cpu_env);
5080 rn = "TCHalt";
5081 break;
5082 case 5:
5083 CP0_CHECK(ctx->insn_flags & ASE_MT);
5084 gen_helper_mfc0_tccontext(arg, cpu_env);
5085 rn = "TCContext";
5086 break;
5087 case 6:
5088 CP0_CHECK(ctx->insn_flags & ASE_MT);
5089 gen_helper_mfc0_tcschedule(arg, cpu_env);
5090 rn = "TCSchedule";
5091 break;
5092 case 7:
5093 CP0_CHECK(ctx->insn_flags & ASE_MT);
5094 gen_helper_mfc0_tcschefback(arg, cpu_env);
5095 rn = "TCScheFBack";
5096 break;
5097 default:
5098 goto cp0_unimplemented;
5099 }
5100 break;
5101 case 3:
5102 switch (sel) {
5103 case 0:
5104 {
5105 TCGv_i64 tmp = tcg_temp_new_i64();
5106 tcg_gen_ld_i64(tmp, cpu_env,
5107 offsetof(CPUMIPSState, CP0_EntryLo1));
5108 #if defined(TARGET_MIPS64)
5109 if (ctx->rxi) {
5110 /* Move RI/XI fields to bits 31:30 */
5111 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI);
5112 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2);
5113 }
5114 #endif
5115 gen_move_low32(arg, tmp);
5116 tcg_temp_free_i64(tmp);
5117 }
5118 rn = "EntryLo1";
5119 break;
5120 case 1:
5121 CP0_CHECK(ctx->vp);
5122 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
5123 rn = "GlobalNumber";
5124 break;
5125 default:
5126 goto cp0_unimplemented;
5127 }
5128 break;
5129 case 4:
5130 switch (sel) {
5131 case 0:
5132 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
5133 tcg_gen_ext32s_tl(arg, arg);
5134 rn = "Context";
5135 break;
5136 case 1:
5137 // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
5138 rn = "ContextConfig";
5139 goto cp0_unimplemented;
5140 case 2:
5141 CP0_CHECK(ctx->ulri);
5142 tcg_gen_ld32s_tl(arg, cpu_env,
5143 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
5144 rn = "UserLocal";
5145 break;
5146 default:
5147 goto cp0_unimplemented;
5148 }
5149 break;
5150 case 5:
5151 switch (sel) {
5152 case 0:
5153 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
5154 rn = "PageMask";
5155 break;
5156 case 1:
5157 check_insn(ctx, ISA_MIPS32R2);
5158 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
5159 rn = "PageGrain";
5160 break;
5161 default:
5162 goto cp0_unimplemented;
5163 }
5164 break;
5165 case 6:
5166 switch (sel) {
5167 case 0:
5168 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
5169 rn = "Wired";
5170 break;
5171 case 1:
5172 check_insn(ctx, ISA_MIPS32R2);
5173 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
5174 rn = "SRSConf0";
5175 break;
5176 case 2:
5177 check_insn(ctx, ISA_MIPS32R2);
5178 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
5179 rn = "SRSConf1";
5180 break;
5181 case 3:
5182 check_insn(ctx, ISA_MIPS32R2);
5183 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
5184 rn = "SRSConf2";
5185 break;
5186 case 4:
5187 check_insn(ctx, ISA_MIPS32R2);
5188 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
5189 rn = "SRSConf3";
5190 break;
5191 case 5:
5192 check_insn(ctx, ISA_MIPS32R2);
5193 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
5194 rn = "SRSConf4";
5195 break;
5196 default:
5197 goto cp0_unimplemented;
5198 }
5199 break;
5200 case 7:
5201 switch (sel) {
5202 case 0:
5203 check_insn(ctx, ISA_MIPS32R2);
5204 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
5205 rn = "HWREna";
5206 break;
5207 default:
5208 goto cp0_unimplemented;
5209 }
5210 break;
5211 case 8:
5212 switch (sel) {
5213 case 0:
5214 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
5215 tcg_gen_ext32s_tl(arg, arg);
5216 rn = "BadVAddr";
5217 break;
5218 case 1:
5219 CP0_CHECK(ctx->bi);
5220 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
5221 rn = "BadInstr";
5222 break;
5223 case 2:
5224 CP0_CHECK(ctx->bp);
5225 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
5226 rn = "BadInstrP";
5227 break;
5228 default:
5229 goto cp0_unimplemented;
5230 }
5231 break;
5232 case 9:
5233 switch (sel) {
5234 case 0:
5235 /* Mark as an IO operation because we read the time. */
5236 if (ctx->tb->cflags & CF_USE_ICOUNT) {
5237 gen_io_start();
5238 }
5239 gen_helper_mfc0_count(arg, cpu_env);
5240 if (ctx->tb->cflags & CF_USE_ICOUNT) {
5241 gen_io_end();
5242 }
5243 /* Break the TB to be able to take timer interrupts immediately
5244 after reading count. */
5245 ctx->bstate = BS_STOP;
5246 rn = "Count";
5247 break;
5248 /* 6,7 are implementation dependent */
5249 default:
5250 goto cp0_unimplemented;
5251 }
5252 break;
5253 case 10:
5254 switch (sel) {
5255 case 0:
5256 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
5257 tcg_gen_ext32s_tl(arg, arg);
5258 rn = "EntryHi";
5259 break;
5260 default:
5261 goto cp0_unimplemented;
5262 }
5263 break;
5264 case 11:
5265 switch (sel) {
5266 case 0:
5267 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
5268 rn = "Compare";
5269 break;
5270 /* 6,7 are implementation dependent */
5271 default:
5272 goto cp0_unimplemented;
5273 }
5274 break;
5275 case 12:
5276 switch (sel) {
5277 case 0:
5278 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
5279 rn = "Status";
5280 break;
5281 case 1:
5282 check_insn(ctx, ISA_MIPS32R2);
5283 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
5284 rn = "IntCtl";
5285 break;
5286 case 2:
5287 check_insn(ctx, ISA_MIPS32R2);
5288 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
5289 rn = "SRSCtl";
5290 break;
5291 case 3:
5292 check_insn(ctx, ISA_MIPS32R2);
5293 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
5294 rn = "SRSMap";
5295 break;
5296 default:
5297 goto cp0_unimplemented;
5298 }
5299 break;
5300 case 13:
5301 switch (sel) {
5302 case 0:
5303 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
5304 rn = "Cause";
5305 break;
5306 default:
5307 goto cp0_unimplemented;
5308 }
5309 break;
5310 case 14:
5311 switch (sel) {
5312 case 0:
5313 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
5314 tcg_gen_ext32s_tl(arg, arg);
5315 rn = "EPC";
5316 break;
5317 default:
5318 goto cp0_unimplemented;
5319 }
5320 break;
5321 case 15:
5322 switch (sel) {
5323 case 0:
5324 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
5325 rn = "PRid";
5326 break;
5327 case 1:
5328 check_insn(ctx, ISA_MIPS32R2);
5329 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase));
5330 rn = "EBase";
5331 break;
5332 case 3:
5333 check_insn(ctx, ISA_MIPS32R2);
5334 CP0_CHECK(ctx->cmgcr);
5335 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
5336 tcg_gen_ext32s_tl(arg, arg);
5337 rn = "CMGCRBase";
5338 break;
5339 default:
5340 goto cp0_unimplemented;
5341 }
5342 break;
5343 case 16:
5344 switch (sel) {
5345 case 0:
5346 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
5347 rn = "Config";
5348 break;
5349 case 1:
5350 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
5351 rn = "Config1";
5352 break;
5353 case 2:
5354 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
5355 rn = "Config2";
5356 break;
5357 case 3:
5358 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
5359 rn = "Config3";
5360 break;
5361 case 4:
5362 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
5363 rn = "Config4";
5364 break;
5365 case 5:
5366 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
5367 rn = "Config5";
5368 break;
5369 /* 6,7 are implementation dependent */
5370 case 6:
5371 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
5372 rn = "Config6";
5373 break;
5374 case 7:
5375 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
5376 rn = "Config7";
5377 break;
5378 default:
5379 goto cp0_unimplemented;
5380 }
5381 break;
5382 case 17:
5383 switch (sel) {
5384 case 0:
5385 gen_helper_mfc0_lladdr(arg, cpu_env);
5386 rn = "LLAddr";
5387 break;
5388 case 1:
5389 CP0_CHECK(ctx->mrp);
5390 gen_helper_mfc0_maar(arg, cpu_env);
5391 rn = "MAAR";
5392 break;
5393 case 2:
5394 CP0_CHECK(ctx->mrp);
5395 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
5396 rn = "MAARI";
5397 break;
5398 default:
5399 goto cp0_unimplemented;
5400 }
5401 break;
5402 case 18:
5403 switch (sel) {
5404 case 0 ... 7:
5405 gen_helper_1e0i(mfc0_watchlo, arg, sel);
5406 rn = "WatchLo";
5407 break;
5408 default:
5409 goto cp0_unimplemented;
5410 }
5411 break;
5412 case 19:
5413 switch (sel) {
5414 case 0 ...7:
5415 gen_helper_1e0i(mfc0_watchhi, arg, sel);
5416 rn = "WatchHi";
5417 break;
5418 default:
5419 goto cp0_unimplemented;
5420 }
5421 break;
5422 case 20:
5423 switch (sel) {
5424 case 0:
5425 #if defined(TARGET_MIPS64)
5426 check_insn(ctx, ISA_MIPS3);
5427 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
5428 tcg_gen_ext32s_tl(arg, arg);
5429 rn = "XContext";
5430 break;
5431 #endif
5432 default:
5433 goto cp0_unimplemented;
5434 }
5435 break;
5436 case 21:
5437 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5438 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
5439 switch (sel) {
5440 case 0:
5441 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
5442 rn = "Framemask";
5443 break;
5444 default:
5445 goto cp0_unimplemented;
5446 }
5447 break;
5448 case 22:
5449 tcg_gen_movi_tl(arg, 0); /* unimplemented */
5450 rn = "'Diagnostic"; /* implementation dependent */
5451 break;
5452 case 23:
5453 switch (sel) {
5454 case 0:
5455 gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
5456 rn = "Debug";
5457 break;
5458 case 1:
5459 // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
5460 rn = "TraceControl";
5461 // break;
5462 case 2:
5463 // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
5464 rn = "TraceControl2";
5465 // break;
5466 case 3:
5467 // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
5468 rn = "UserTraceData";
5469 // break;
5470 case 4:
5471 // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
5472 rn = "TraceBPC";
5473 // break;
5474 default:
5475 goto cp0_unimplemented;
5476 }
5477 break;
5478 case 24:
5479 switch (sel) {
5480 case 0:
5481 /* EJTAG support */
5482 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
5483 tcg_gen_ext32s_tl(arg, arg);
5484 rn = "DEPC";
5485 break;
5486 default:
5487 goto cp0_unimplemented;
5488 }
5489 break;
5490 case 25:
5491 switch (sel) {
5492 case 0:
5493 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
5494 rn = "Performance0";
5495 break;
5496 case 1:
5497 // gen_helper_mfc0_performance1(arg);
5498 rn = "Performance1";
5499 // break;
5500 case 2:
5501 // gen_helper_mfc0_performance2(arg);
5502 rn = "Performance2";
5503 // break;
5504 case 3:
5505 // gen_helper_mfc0_performance3(arg);
5506 rn = "Performance3";
5507 // break;
5508 case 4:
5509 // gen_helper_mfc0_performance4(arg);
5510 rn = "Performance4";
5511 // break;
5512 case 5:
5513 // gen_helper_mfc0_performance5(arg);
5514 rn = "Performance5";
5515 // break;
5516 case 6:
5517 // gen_helper_mfc0_performance6(arg);
5518 rn = "Performance6";
5519 // break;
5520 case 7:
5521 // gen_helper_mfc0_performance7(arg);
5522 rn = "Performance7";
5523 // break;
5524 default:
5525 goto cp0_unimplemented;
5526 }
5527 break;
5528 case 26:
5529 switch (sel) {
5530 case 0:
5531 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
5532 rn = "ErrCtl";
5533 break;
5534 default:
5535 goto cp0_unimplemented;
5536 }
5537 break;
5538 case 27:
5539 switch (sel) {
5540 case 0 ... 3:
5541 tcg_gen_movi_tl(arg, 0); /* unimplemented */
5542 rn = "CacheErr";
5543 break;
5544 default:
5545 goto cp0_unimplemented;
5546 }
5547 break;
5548 case 28:
5549 switch (sel) {
5550 case 0:
5551 case 2:
5552 case 4:
5553 case 6:
5554 {
5555 TCGv_i64 tmp = tcg_temp_new_i64();
5556 tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
5557 gen_move_low32(arg, tmp);
5558 tcg_temp_free_i64(tmp);
5559 }
5560 rn = "TagLo";
5561 break;
5562 case 1:
5563 case 3:
5564 case 5:
5565 case 7:
5566 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
5567 rn = "DataLo";
5568 break;
5569 default:
5570 goto cp0_unimplemented;
5571 }
5572 break;
5573 case 29:
5574 switch (sel) {
5575 case 0:
5576 case 2:
5577 case 4:
5578 case 6:
5579 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
5580 rn = "TagHi";
5581 break;
5582 case 1:
5583 case 3:
5584 case 5:
5585 case 7:
5586 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
5587 rn = "DataHi";
5588 break;
5589 default:
5590 goto cp0_unimplemented;
5591 }
5592 break;
5593 case 30:
5594 switch (sel) {
5595 case 0:
5596 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
5597 tcg_gen_ext32s_tl(arg, arg);
5598 rn = "ErrorEPC";
5599 break;
5600 default:
5601 goto cp0_unimplemented;
5602 }
5603 break;
5604 case 31:
5605 switch (sel) {
5606 case 0:
5607 /* EJTAG support */
5608 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
5609 rn = "DESAVE";
5610 break;
5611 case 2 ... 7:
5612 CP0_CHECK(ctx->kscrexist & (1 << sel));
5613 tcg_gen_ld_tl(arg, cpu_env,
5614 offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
5615 tcg_gen_ext32s_tl(arg, arg);
5616 rn = "KScratch";
5617 break;
5618 default:
5619 goto cp0_unimplemented;
5620 }
5621 break;
5622 default:
5623 goto cp0_unimplemented;
5624 }
5625 (void)rn; /* avoid a compiler warning */
5626 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
5627 return;
5628
5629 cp0_unimplemented:
5630 qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
5631 gen_mfc0_unimplemented(ctx, arg);
5632 }
5633
5634 static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
5635 {
5636 const char *rn = "invalid";
5637
5638 if (sel != 0)
5639 check_insn(ctx, ISA_MIPS32);
5640
5641 if (ctx->tb->cflags & CF_USE_ICOUNT) {
5642 gen_io_start();
5643 }
5644
5645 switch (reg) {
5646 case 0:
5647 switch (sel) {
5648 case 0:
5649 gen_helper_mtc0_index(cpu_env, arg);
5650 rn = "Index";
5651 break;
5652 case 1:
5653 CP0_CHECK(ctx->insn_flags & ASE_MT);
5654 gen_helper_mtc0_mvpcontrol(cpu_env, arg);
5655 rn = "MVPControl";
5656 break;
5657 case 2:
5658 CP0_CHECK(ctx->insn_flags & ASE_MT);
5659 /* ignored */
5660 rn = "MVPConf0";
5661 break;
5662 case 3:
5663 CP0_CHECK(ctx->insn_flags & ASE_MT);
5664 /* ignored */
5665 rn = "MVPConf1";
5666 break;
5667 case 4:
5668 CP0_CHECK(ctx->vp);
5669 /* ignored */
5670 rn = "VPControl";
5671 break;
5672 default:
5673 goto cp0_unimplemented;
5674 }
5675 break;
5676 case 1:
5677 switch (sel) {
5678 case 0:
5679 /* ignored */
5680 rn = "Random";
5681 break;
5682 case 1:
5683 CP0_CHECK(ctx->insn_flags & ASE_MT);
5684 gen_helper_mtc0_vpecontrol(cpu_env, arg);
5685 rn = "VPEControl";
5686 break;
5687 case 2:
5688 CP0_CHECK(ctx->insn_flags & ASE_MT);
5689 gen_helper_mtc0_vpeconf0(cpu_env, arg);
5690 rn = "VPEConf0";
5691 break;
5692 case 3:
5693 CP0_CHECK(ctx->insn_flags & ASE_MT);
5694 gen_helper_mtc0_vpeconf1(cpu_env, arg);
5695 rn = "VPEConf1";
5696 break;
5697 case 4:
5698 CP0_CHECK(ctx->insn_flags & ASE_MT);
5699 gen_helper_mtc0_yqmask(cpu_env, arg);
5700 rn = "YQMask";
5701 break;
5702 case 5:
5703 CP0_CHECK(ctx->insn_flags & ASE_MT);
5704 tcg_gen_st_tl(arg, cpu_env,
5705 offsetof(CPUMIPSState, CP0_VPESchedule));
5706 rn = "VPESchedule";
5707 break;
5708 case 6:
5709 CP0_CHECK(ctx->insn_flags & ASE_MT);
5710 tcg_gen_st_tl(arg, cpu_env,
5711 offsetof(CPUMIPSState, CP0_VPEScheFBack));
5712 rn = "VPEScheFBack";
5713 break;
5714 case 7:
5715 CP0_CHECK(ctx->insn_flags & ASE_MT);
5716 gen_helper_mtc0_vpeopt(cpu_env, arg);
5717 rn = "VPEOpt";
5718 break;
5719 default:
5720 goto cp0_unimplemented;
5721 }
5722 break;
5723 case 2:
5724 switch (sel) {
5725 case 0:
5726 gen_helper_mtc0_entrylo0(cpu_env, arg);
5727 rn = "EntryLo0";
5728 break;
5729 case 1:
5730 CP0_CHECK(ctx->insn_flags & ASE_MT);
5731 gen_helper_mtc0_tcstatus(cpu_env, arg);
5732 rn = "TCStatus";
5733 break;
5734 case 2:
5735 CP0_CHECK(ctx->insn_flags & ASE_MT);
5736 gen_helper_mtc0_tcbind(cpu_env, arg);
5737 rn = "TCBind";
5738 break;
5739 case 3:
5740 CP0_CHECK(ctx->insn_flags & ASE_MT);
5741 gen_helper_mtc0_tcrestart(cpu_env, arg);
5742 rn = "TCRestart";
5743 break;
5744 case 4:
5745 CP0_CHECK(ctx->insn_flags & ASE_MT);
5746 gen_helper_mtc0_tchalt(cpu_env, arg);
5747 rn = "TCHalt";
5748 break;
5749 case 5:
5750 CP0_CHECK(ctx->insn_flags & ASE_MT);
5751 gen_helper_mtc0_tccontext(cpu_env, arg);
5752 rn = "TCContext";
5753 break;
5754 case 6:
5755 CP0_CHECK(ctx->insn_flags & ASE_MT);
5756 gen_helper_mtc0_tcschedule(cpu_env, arg);
5757 rn = "TCSchedule";
5758 break;
5759 case 7:
5760 CP0_CHECK(ctx->insn_flags & ASE_MT);
5761 gen_helper_mtc0_tcschefback(cpu_env, arg);
5762 rn = "TCScheFBack";
5763 break;
5764 default:
5765 goto cp0_unimplemented;
5766 }
5767 break;
5768 case 3:
5769 switch (sel) {
5770 case 0:
5771 gen_helper_mtc0_entrylo1(cpu_env, arg);
5772 rn = "EntryLo1";
5773 break;
5774 case 1:
5775 CP0_CHECK(ctx->vp);
5776 /* ignored */
5777 rn = "GlobalNumber";
5778 break;
5779 default:
5780 goto cp0_unimplemented;
5781 }
5782 break;
5783 case 4:
5784 switch (sel) {
5785 case 0:
5786 gen_helper_mtc0_context(cpu_env, arg);
5787 rn = "Context";
5788 break;
5789 case 1:
5790 // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
5791 rn = "ContextConfig";
5792 goto cp0_unimplemented;
5793 case 2:
5794 CP0_CHECK(ctx->ulri);
5795 tcg_gen_st_tl(arg, cpu_env,
5796 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
5797 rn = "UserLocal";
5798 break;
5799 default:
5800 goto cp0_unimplemented;
5801 }
5802 break;
5803 case 5:
5804 switch (sel) {
5805 case 0:
5806 gen_helper_mtc0_pagemask(cpu_env, arg);
5807 rn = "PageMask";
5808 break;
5809 case 1:
5810 check_insn(ctx, ISA_MIPS32R2);
5811 gen_helper_mtc0_pagegrain(cpu_env, arg);
5812 rn = "PageGrain";
5813 ctx->bstate = BS_STOP;
5814 break;
5815 default:
5816 goto cp0_unimplemented;
5817 }
5818 break;
5819 case 6:
5820 switch (sel) {
5821 case 0:
5822 gen_helper_mtc0_wired(cpu_env, arg);
5823 rn = "Wired";
5824 break;
5825 case 1:
5826 check_insn(ctx, ISA_MIPS32R2);
5827 gen_helper_mtc0_srsconf0(cpu_env, arg);
5828 rn = "SRSConf0";
5829 break;
5830 case 2:
5831 check_insn(ctx, ISA_MIPS32R2);
5832 gen_helper_mtc0_srsconf1(cpu_env, arg);
5833 rn = "SRSConf1";
5834 break;
5835 case 3:
5836 check_insn(ctx, ISA_MIPS32R2);
5837 gen_helper_mtc0_srsconf2(cpu_env, arg);
5838 rn = "SRSConf2";
5839 break;
5840 case 4:
5841 check_insn(ctx, ISA_MIPS32R2);
5842 gen_helper_mtc0_srsconf3(cpu_env, arg);
5843 rn = "SRSConf3";
5844 break;
5845 case 5:
5846 check_insn(ctx, ISA_MIPS32R2);
5847 gen_helper_mtc0_srsconf4(cpu_env, arg);
5848 rn = "SRSConf4";
5849 break;
5850 default:
5851 goto cp0_unimplemented;
5852 }
5853 break;
5854 case 7:
5855 switch (sel) {
5856 case 0:
5857 check_insn(ctx, ISA_MIPS32R2);
5858 gen_helper_mtc0_hwrena(cpu_env, arg);
5859 ctx->bstate = BS_STOP;
5860 rn = "HWREna";
5861 break;
5862 default:
5863 goto cp0_unimplemented;
5864 }
5865 break;
5866 case 8:
5867 switch (sel) {
5868 case 0:
5869 /* ignored */
5870 rn = "BadVAddr";
5871 break;
5872 case 1:
5873 /* ignored */
5874 rn = "BadInstr";
5875 break;
5876 case 2:
5877 /* ignored */
5878 rn = "BadInstrP";
5879 break;
5880 default:
5881 goto cp0_unimplemented;
5882 }
5883 break;
5884 case 9:
5885 switch (sel) {
5886 case 0:
5887 gen_helper_mtc0_count(cpu_env, arg);
5888 rn = "Count";
5889 break;
5890 /* 6,7 are implementation dependent */
5891 default:
5892 goto cp0_unimplemented;
5893 }
5894 break;
5895 case 10:
5896 switch (sel) {
5897 case 0:
5898 gen_helper_mtc0_entryhi(cpu_env, arg);
5899 rn = "EntryHi";
5900 break;
5901 default:
5902 goto cp0_unimplemented;
5903 }
5904 break;
5905 case 11:
5906 switch (sel) {
5907 case 0:
5908 gen_helper_mtc0_compare(cpu_env, arg);
5909 rn = "Compare";
5910 break;
5911 /* 6,7 are implementation dependent */
5912 default:
5913 goto cp0_unimplemented;
5914 }
5915 break;
5916 case 12:
5917 switch (sel) {
5918 case 0:
5919 save_cpu_state(ctx, 1);
5920 gen_helper_mtc0_status(cpu_env, arg);
5921 /* BS_STOP isn't good enough here, hflags may have changed. */
5922 gen_save_pc(ctx->pc + 4);
5923 ctx->bstate = BS_EXCP;
5924 rn = "Status";
5925 break;
5926 case 1:
5927 check_insn(ctx, ISA_MIPS32R2);
5928 gen_helper_mtc0_intctl(cpu_env, arg);
5929 /* Stop translation as we may have switched the execution mode */
5930 ctx->bstate = BS_STOP;
5931 rn = "IntCtl";
5932 break;
5933 case 2:
5934 check_insn(ctx, ISA_MIPS32R2);
5935 gen_helper_mtc0_srsctl(cpu_env, arg);
5936 /* Stop translation as we may have switched the execution mode */
5937 ctx->bstate = BS_STOP;
5938 rn = "SRSCtl";
5939 break;
5940 case 3:
5941 check_insn(ctx, ISA_MIPS32R2);
5942 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
5943 /* Stop translation as we may have switched the execution mode */
5944 ctx->bstate = BS_STOP;
5945 rn = "SRSMap";
5946 break;
5947 default:
5948 goto cp0_unimplemented;
5949 }
5950 break;
5951 case 13:
5952 switch (sel) {
5953 case 0:
5954 save_cpu_state(ctx, 1);
5955 gen_helper_mtc0_cause(cpu_env, arg);
5956 rn = "Cause";
5957 break;
5958 default:
5959 goto cp0_unimplemented;
5960 }
5961 break;
5962 case 14:
5963 switch (sel) {
5964 case 0:
5965 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
5966 rn = "EPC";
5967 break;
5968 default:
5969 goto cp0_unimplemented;
5970 }
5971 break;
5972 case 15:
5973 switch (sel) {
5974 case 0:
5975 /* ignored */
5976 rn = "PRid";
5977 break;
5978 case 1:
5979 check_insn(ctx, ISA_MIPS32R2);
5980 gen_helper_mtc0_ebase(cpu_env, arg);
5981 rn = "EBase";
5982 break;
5983 default:
5984 goto cp0_unimplemented;
5985 }
5986 break;
5987 case 16:
5988 switch (sel) {
5989 case 0:
5990 gen_helper_mtc0_config0(cpu_env, arg);
5991 rn = "Config";
5992 /* Stop translation as we may have switched the execution mode */
5993 ctx->bstate = BS_STOP;
5994 break;
5995 case 1:
5996 /* ignored, read only */
5997 rn = "Config1";
5998 break;
5999 case 2:
6000 gen_helper_mtc0_config2(cpu_env, arg);
6001 rn = "Config2";
6002 /* Stop translation as we may have switched the execution mode */
6003 ctx->bstate = BS_STOP;
6004 break;
6005 case 3:
6006 gen_helper_mtc0_config3(cpu_env, arg);
6007 rn = "Config3";
6008 /* Stop translation as we may have switched the execution mode */
6009 ctx->bstate = BS_STOP;
6010 break;
6011 case 4:
6012 gen_helper_mtc0_config4(cpu_env, arg);
6013 rn = "Config4";
6014 ctx->bstate = BS_STOP;
6015 break;
6016 case 5:
6017 gen_helper_mtc0_config5(cpu_env, arg);
6018 rn = "Config5";
6019 /* Stop translation as we may have switched the execution mode */
6020 ctx->bstate = BS_STOP;
6021 break;
6022 /* 6,7 are implementation dependent */
6023 case 6:
6024 /* ignored */
6025 rn = "Config6";
6026 break;
6027 case 7:
6028 /* ignored */
6029 rn = "Config7";
6030 break;
6031 default:
6032 rn = "Invalid config selector";
6033 goto cp0_unimplemented;
6034 }
6035 break;
6036 case 17:
6037 switch (sel) {
6038 case 0:
6039 gen_helper_mtc0_lladdr(cpu_env, arg);
6040 rn = "LLAddr";
6041 break;
6042 case 1:
6043 CP0_CHECK(ctx->mrp);
6044 gen_helper_mtc0_maar(cpu_env, arg);
6045 rn = "MAAR";
6046 break;
6047 case 2:
6048 CP0_CHECK(ctx->mrp);
6049 gen_helper_mtc0_maari(cpu_env, arg);
6050 rn = "MAARI";
6051 break;
6052 default:
6053 goto cp0_unimplemented;
6054 }
6055 break;
6056 case 18:
6057 switch (sel) {
6058 case 0 ... 7:
6059 gen_helper_0e1i(mtc0_watchlo, arg, sel);
6060 rn = "WatchLo";
6061 break;
6062 default:
6063 goto cp0_unimplemented;
6064 }
6065 break;
6066 case 19:
6067 switch (sel) {
6068 case 0 ... 7:
6069 gen_helper_0e1i(mtc0_watchhi, arg, sel);
6070 rn = "WatchHi";
6071 break;
6072 default:
6073 goto cp0_unimplemented;
6074 }
6075 break;
6076 case 20:
6077 switch (sel) {
6078 case 0:
6079 #if defined(TARGET_MIPS64)
6080 check_insn(ctx, ISA_MIPS3);
6081 gen_helper_mtc0_xcontext(cpu_env, arg);
6082 rn = "XContext";
6083 break;
6084 #endif
6085 default:
6086 goto cp0_unimplemented;
6087 }
6088 break;
6089 case 21:
6090 /* Officially reserved, but sel 0 is used for R1x000 framemask */
6091 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
6092 switch (sel) {
6093 case 0:
6094 gen_helper_mtc0_framemask(cpu_env, arg);
6095 rn = "Framemask";
6096 break;
6097 default:
6098 goto cp0_unimplemented;
6099 }
6100 break;
6101 case 22:
6102 /* ignored */
6103 rn = "Diagnostic"; /* implementation dependent */
6104 break;
6105 case 23:
6106 switch (sel) {
6107 case 0:
6108 gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
6109 /* BS_STOP isn't good enough here, hflags may have changed. */
6110 gen_save_pc(ctx->pc + 4);
6111 ctx->bstate = BS_EXCP;
6112 rn = "Debug";
6113 break;
6114 case 1:
6115 // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
6116 rn = "TraceControl";
6117 /* Stop translation as we may have switched the execution mode */
6118 ctx->bstate = BS_STOP;
6119 // break;
6120 case 2:
6121 // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
6122 rn = "TraceControl2";
6123 /* Stop translation as we may have switched the execution mode */
6124 ctx->bstate = BS_STOP;
6125 // break;
6126 case 3:
6127 /* Stop translation as we may have switched the execution mode */
6128 ctx->bstate = BS_STOP;
6129 // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
6130 rn = "UserTraceData";
6131 /* Stop translation as we may have switched the execution mode */
6132 ctx->bstate = BS_STOP;
6133 // break;
6134 case 4:
6135 // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
6136 /* Stop translation as we may have switched the execution mode */
6137 ctx->bstate = BS_STOP;
6138 rn = "TraceBPC";
6139 // break;
6140 default:
6141 goto cp0_unimplemented;
6142 }
6143 break;
6144 case 24:
6145 switch (sel) {
6146 case 0:
6147 /* EJTAG support */
6148 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
6149 rn = "DEPC";
6150 break;
6151 default:
6152 goto cp0_unimplemented;
6153 }
6154 break;
6155 case 25:
6156 switch (sel) {
6157 case 0:
6158 gen_helper_mtc0_performance0(cpu_env, arg);
6159 rn = "Performance0";
6160 break;
6161 case 1:
6162 // gen_helper_mtc0_performance1(arg);
6163 rn = "Performance1";
6164 // break;
6165 case 2:
6166 // gen_helper_mtc0_performance2(arg);
6167 rn = "Performance2";
6168 // break;
6169 case 3:
6170 // gen_helper_mtc0_performance3(arg);
6171 rn = "Performance3";
6172 // break;
6173 case 4:
6174 // gen_helper_mtc0_performance4(arg);
6175 rn = "Performance4";
6176 // break;
6177 case 5:
6178 // gen_helper_mtc0_performance5(arg);
6179 rn = "Performance5";
6180 // break;
6181 case 6:
6182 // gen_helper_mtc0_performance6(arg);
6183 rn = "Performance6";
6184 // break;
6185 case 7:
6186 // gen_helper_mtc0_performance7(arg);
6187 rn = "Performance7";
6188 // break;
6189 default:
6190 goto cp0_unimplemented;
6191 }
6192 break;
6193 case 26:
6194 switch (sel) {
6195 case 0:
6196 gen_helper_mtc0_errctl(cpu_env, arg);
6197 ctx->bstate = BS_STOP;
6198 rn = "ErrCtl";
6199 break;
6200 default:
6201 goto cp0_unimplemented;
6202 }
6203 break;
6204 case 27:
6205 switch (sel) {
6206 case 0 ... 3:
6207 /* ignored */
6208 rn = "CacheErr";
6209 break;
6210 default:
6211 goto cp0_unimplemented;
6212 }
6213 break;
6214 case 28:
6215 switch (sel) {
6216 case 0:
6217 case 2:
6218 case 4:
6219 case 6:
6220 gen_helper_mtc0_taglo(cpu_env, arg);
6221 rn = "TagLo";
6222 break;
6223 case 1:
6224 case 3:
6225 case 5:
6226 case 7:
6227 gen_helper_mtc0_datalo(cpu_env, arg);
6228 rn = "DataLo";
6229 break;
6230 default:
6231 goto cp0_unimplemented;
6232 }
6233 break;
6234 case 29:
6235 switch (sel) {
6236 case 0:
6237 case 2:
6238 case 4:
6239 case 6:
6240 gen_helper_mtc0_taghi(cpu_env, arg);
6241 rn = "TagHi";
6242 break;
6243 case 1:
6244 case 3:
6245 case 5:
6246 case 7:
6247 gen_helper_mtc0_datahi(cpu_env, arg);
6248 rn = "DataHi";
6249 break;
6250 default:
6251 rn = "invalid sel";
6252 goto cp0_unimplemented;
6253 }
6254 break;
6255 case 30:
6256 switch (sel) {
6257 case 0:
6258 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
6259 rn = "ErrorEPC";
6260 break;
6261 default:
6262 goto cp0_unimplemented;
6263 }
6264 break;
6265 case 31:
6266 switch (sel) {
6267 case 0:
6268 /* EJTAG support */
6269 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
6270 rn = "DESAVE";
6271 break;
6272 case 2 ... 7:
6273 CP0_CHECK(ctx->kscrexist & (1 << sel));
6274 tcg_gen_st_tl(arg, cpu_env,
6275 offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
6276 rn = "KScratch";
6277 break;
6278 default:
6279 goto cp0_unimplemented;
6280 }
6281 /* Stop translation as we may have switched the execution mode */
6282 ctx->bstate = BS_STOP;
6283 break;
6284 default:
6285 goto cp0_unimplemented;
6286 }
6287 (void)rn; /* avoid a compiler warning */
6288 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
6289 /* For simplicity assume that all writes can cause interrupts. */
6290 if (ctx->tb->cflags & CF_USE_ICOUNT) {
6291 gen_io_end();
6292 ctx->bstate = BS_STOP;
6293 }
6294 return;
6295
6296 cp0_unimplemented:
6297 qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
6298 }
6299
6300 #if defined(TARGET_MIPS64)
6301 static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
6302 {
6303 const char *rn = "invalid";
6304
6305 if (sel != 0)
6306 check_insn(ctx, ISA_MIPS64);
6307
6308 switch (reg) {
6309 case 0:
6310 switch (sel) {
6311 case 0:
6312 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
6313 rn = "Index";
6314 break;
6315 case 1:
6316 CP0_CHECK(ctx->insn_flags & ASE_MT);
6317 gen_helper_mfc0_mvpcontrol(arg, cpu_env);
6318 rn = "MVPControl";
6319 break;
6320 case 2:
6321 CP0_CHECK(ctx->insn_flags & ASE_MT);
6322 gen_helper_mfc0_mvpconf0(arg, cpu_env);
6323 rn = "MVPConf0";
6324 break;
6325 case 3:
6326 CP0_CHECK(ctx->insn_flags & ASE_MT);
6327 gen_helper_mfc0_mvpconf1(arg, cpu_env);
6328 rn = "MVPConf1";
6329 break;
6330 case 4:
6331 CP0_CHECK(ctx->vp);
6332 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
6333 rn = "VPControl";
6334 break;
6335 default:
6336 goto cp0_unimplemented;
6337 }
6338 break;
6339 case 1:
6340 switch (sel) {
6341 case 0:
6342 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
6343 gen_helper_mfc0_random(arg, cpu_env);
6344 rn = "Random";
6345 break;
6346 case 1:
6347 CP0_CHECK(ctx->insn_flags & ASE_MT);
6348 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
6349 rn = "VPEControl";
6350 break;
6351 case 2:
6352 CP0_CHECK(ctx->insn_flags & ASE_MT);
6353 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
6354 rn = "VPEConf0";
6355 break;
6356 case 3:
6357 CP0_CHECK(ctx->insn_flags & ASE_MT);
6358 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
6359 rn = "VPEConf1";
6360 break;
6361 case 4:
6362 CP0_CHECK(ctx->insn_flags & ASE_MT);
6363 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
6364 rn = "YQMask";
6365 break;
6366 case 5:
6367 CP0_CHECK(ctx->insn_flags & ASE_MT);
6368 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
6369 rn = "VPESchedule";
6370 break;
6371 case 6:
6372 CP0_CHECK(ctx->insn_flags & ASE_MT);
6373 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
6374 rn = "VPEScheFBack";
6375 break;
6376 case 7:
6377 CP0_CHECK(ctx->insn_flags & ASE_MT);
6378 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
6379 rn = "VPEOpt";
6380 break;
6381 default:
6382 goto cp0_unimplemented;
6383 }
6384 break;
6385 case 2:
6386 switch (sel) {
6387 case 0:
6388 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
6389 rn = "EntryLo0";
6390 break;
6391 case 1:
6392 CP0_CHECK(ctx->insn_flags & ASE_MT);
6393 gen_helper_mfc0_tcstatus(arg, cpu_env);
6394 rn = "TCStatus";
6395 break;
6396 case 2:
6397 CP0_CHECK(ctx->insn_flags & ASE_MT);
6398 gen_helper_mfc0_tcbind(arg, cpu_env);
6399 rn = "TCBind";
6400 break;
6401 case 3:
6402 CP0_CHECK(ctx->insn_flags & ASE_MT);
6403 gen_helper_dmfc0_tcrestart(arg, cpu_env);
6404 rn = "TCRestart";
6405 break;
6406 case 4:
6407 CP0_CHECK(ctx->insn_flags & ASE_MT);
6408 gen_helper_dmfc0_tchalt(arg, cpu_env);
6409 rn = "TCHalt";
6410 break;
6411 case 5:
6412 CP0_CHECK(ctx->insn_flags & ASE_MT);
6413 gen_helper_dmfc0_tccontext(arg, cpu_env);
6414 rn = "TCContext";
6415 break;
6416 case 6:
6417 CP0_CHECK(ctx->insn_flags & ASE_MT);
6418 gen_helper_dmfc0_tcschedule(arg, cpu_env);
6419 rn = "TCSchedule";
6420 break;
6421 case 7:
6422 CP0_CHECK(ctx->insn_flags & ASE_MT);
6423 gen_helper_dmfc0_tcschefback(arg, cpu_env);
6424 rn = "TCScheFBack";
6425 break;
6426 default:
6427 goto cp0_unimplemented;
6428 }
6429 break;
6430 case 3:
6431 switch (sel) {
6432 case 0:
6433 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
6434 rn = "EntryLo1";
6435 break;
6436 case 1:
6437 CP0_CHECK(ctx->vp);
6438 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
6439 rn = "GlobalNumber";
6440 break;
6441 default:
6442 goto cp0_unimplemented;
6443 }
6444 break;
6445 case 4:
6446 switch (sel) {
6447 case 0:
6448 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
6449 rn = "Context";
6450 break;
6451 case 1:
6452 // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
6453 rn = "ContextConfig";
6454 goto cp0_unimplemented;
6455 case 2:
6456 CP0_CHECK(ctx->ulri);
6457 tcg_gen_ld_tl(arg, cpu_env,
6458 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
6459 rn = "UserLocal";
6460 break;
6461 default:
6462 goto cp0_unimplemented;
6463 }
6464 break;
6465 case 5:
6466 switch (sel) {
6467 case 0:
6468 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
6469 rn = "PageMask";
6470 break;
6471 case 1:
6472 check_insn(ctx, ISA_MIPS32R2);
6473 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
6474 rn = "PageGrain";
6475 break;
6476 default:
6477 goto cp0_unimplemented;
6478 }
6479 break;
6480 case 6:
6481 switch (sel) {
6482 case 0:
6483 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
6484 rn = "Wired";
6485 break;
6486 case 1:
6487 check_insn(ctx, ISA_MIPS32R2);
6488 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
6489 rn = "SRSConf0";
6490 break;
6491 case 2:
6492 check_insn(ctx, ISA_MIPS32R2);
6493 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
6494 rn = "SRSConf1";
6495 break;
6496 case 3:
6497 check_insn(ctx, ISA_MIPS32R2);
6498 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
6499 rn = "SRSConf2";
6500 break;
6501 case 4:
6502 check_insn(ctx, ISA_MIPS32R2);
6503 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
6504 rn = "SRSConf3";
6505 break;
6506 case 5:
6507 check_insn(ctx, ISA_MIPS32R2);
6508 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
6509 rn = "SRSConf4";
6510 break;
6511 default:
6512 goto cp0_unimplemented;
6513 }
6514 break;
6515 case 7:
6516 switch (sel) {
6517 case 0:
6518 check_insn(ctx, ISA_MIPS32R2);
6519 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
6520 rn = "HWREna";
6521 break;
6522 default:
6523 goto cp0_unimplemented;
6524 }
6525 break;
6526 case 8:
6527 switch (sel) {
6528 case 0:
6529 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
6530 rn = "BadVAddr";
6531 break;
6532 case 1:
6533 CP0_CHECK(ctx->bi);
6534 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
6535 rn = "BadInstr";
6536 break;
6537 case 2:
6538 CP0_CHECK(ctx->bp);
6539 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
6540 rn = "BadInstrP";
6541 break;
6542 default:
6543 goto cp0_unimplemented;
6544 }
6545 break;
6546 case 9:
6547 switch (sel) {
6548 case 0:
6549 /* Mark as an IO operation because we read the time. */
6550 if (ctx->tb->cflags & CF_USE_ICOUNT) {
6551 gen_io_start();
6552 }
6553 gen_helper_mfc0_count(arg, cpu_env);
6554 if (ctx->tb->cflags & CF_USE_ICOUNT) {
6555 gen_io_end();
6556 }
6557 /* Break the TB to be able to take timer interrupts immediately
6558 after reading count. */
6559 ctx->bstate = BS_STOP;
6560 rn = "Count";
6561 break;
6562 /* 6,7 are implementation dependent */
6563 default:
6564 goto cp0_unimplemented;
6565 }
6566 break;
6567 case 10:
6568 switch (sel) {
6569 case 0:
6570 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
6571 rn = "EntryHi";
6572 break;
6573 default:
6574 goto cp0_unimplemented;
6575 }
6576 break;
6577 case 11:
6578 switch (sel) {
6579 case 0:
6580 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
6581 rn = "Compare";
6582 break;
6583 /* 6,7 are implementation dependent */
6584 default:
6585 goto cp0_unimplemented;
6586 }
6587 break;
6588 case 12:
6589 switch (sel) {
6590 case 0:
6591 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
6592 rn = "Status";
6593 break;
6594 case 1:
6595 check_insn(ctx, ISA_MIPS32R2);
6596 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
6597 rn = "IntCtl";
6598 break;
6599 case 2:
6600 check_insn(ctx, ISA_MIPS32R2);
6601 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
6602 rn = "SRSCtl";
6603 break;
6604 case 3:
6605 check_insn(ctx, ISA_MIPS32R2);
6606 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
6607 rn = "SRSMap";
6608 break;
6609 default:
6610 goto cp0_unimplemented;
6611 }
6612 break;
6613 case 13:
6614 switch (sel) {
6615 case 0:
6616 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
6617 rn = "Cause";
6618 break;
6619 default:
6620 goto cp0_unimplemented;
6621 }
6622 break;
6623 case 14:
6624 switch (sel) {
6625 case 0:
6626 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
6627 rn = "EPC";
6628 break;
6629 default:
6630 goto cp0_unimplemented;
6631 }
6632 break;
6633 case 15:
6634 switch (sel) {
6635 case 0:
6636 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
6637 rn = "PRid";
6638 break;
6639 case 1:
6640 check_insn(ctx, ISA_MIPS32R2);
6641 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase));
6642 rn = "EBase";
6643 break;
6644 case 3:
6645 check_insn(ctx, ISA_MIPS32R2);
6646 CP0_CHECK(ctx->cmgcr);
6647 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
6648 rn = "CMGCRBase";
6649 break;
6650 default:
6651 goto cp0_unimplemented;
6652 }
6653 break;
6654 case 16:
6655 switch (sel) {
6656 case 0:
6657 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
6658 rn = "Config";
6659 break;
6660 case 1:
6661 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
6662 rn = "Config1";
6663 break;
6664 case 2:
6665 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
6666 rn = "Config2";
6667 break;
6668 case 3:
6669 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
6670 rn = "Config3";
6671 break;
6672 case 4:
6673 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
6674 rn = "Config4";
6675 break;
6676 case 5:
6677 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
6678 rn = "Config5";
6679 break;
6680 /* 6,7 are implementation dependent */
6681 case 6:
6682 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
6683 rn = "Config6";
6684 break;
6685 case 7:
6686 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
6687 rn = "Config7";
6688 break;
6689 default:
6690 goto cp0_unimplemented;
6691 }
6692 break;
6693 case 17:
6694 switch (sel) {
6695 case 0:
6696 gen_helper_dmfc0_lladdr(arg, cpu_env);
6697 rn = "LLAddr";
6698 break;
6699 case 1:
6700 CP0_CHECK(ctx->mrp);
6701 gen_helper_dmfc0_maar(arg, cpu_env);
6702 rn = "MAAR";
6703 break;
6704 case 2:
6705 CP0_CHECK(ctx->mrp);
6706 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
6707 rn = "MAARI";
6708 break;
6709 default:
6710 goto cp0_unimplemented;
6711 }
6712 break;
6713 case 18:
6714 switch (sel) {
6715 case 0 ... 7:
6716 gen_helper_1e0i(dmfc0_watchlo, arg, sel);
6717 rn = "WatchLo";
6718 break;
6719 default:
6720 goto cp0_unimplemented;
6721 }
6722 break;
6723 case 19:
6724 switch (sel) {
6725 case 0 ... 7:
6726 gen_helper_1e0i(mfc0_watchhi, arg, sel);
6727 rn = "WatchHi";
6728 break;
6729 default:
6730 goto cp0_unimplemented;
6731 }
6732 break;
6733 case 20:
6734 switch (sel) {
6735 case 0:
6736 check_insn(ctx, ISA_MIPS3);
6737 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
6738 rn = "XContext";
6739 break;
6740 default:
6741 goto cp0_unimplemented;
6742 }
6743 break;
6744 case 21:
6745 /* Officially reserved, but sel 0 is used for R1x000 framemask */
6746 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
6747 switch (sel) {
6748 case 0:
6749 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
6750 rn = "Framemask";
6751 break;
6752 default:
6753 goto cp0_unimplemented;
6754 }
6755 break;
6756 case 22:
6757 tcg_gen_movi_tl(arg, 0); /* unimplemented */
6758 rn = "'Diagnostic"; /* implementation dependent */
6759 break;
6760 case 23:
6761 switch (sel) {
6762 case 0:
6763 gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
6764 rn = "Debug";
6765 break;
6766 case 1:
6767 // gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace support */
6768 rn = "TraceControl";
6769 // break;
6770 case 2:
6771 // gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace support */
6772 rn = "TraceControl2";
6773 // break;
6774 case 3:
6775 // gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace support */
6776 rn = "UserTraceData";
6777 // break;
6778 case 4:
6779 // gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support */
6780 rn = "TraceBPC";
6781 // break;
6782 default:
6783 goto cp0_unimplemented;
6784 }
6785 break;
6786 case 24:
6787 switch (sel) {
6788 case 0:
6789 /* EJTAG support */
6790 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
6791 rn = "DEPC";
6792 break;
6793 default:
6794 goto cp0_unimplemented;
6795 }
6796 break;
6797 case 25:
6798 switch (sel) {
6799 case 0:
6800 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
6801 rn = "Performance0";
6802 break;
6803 case 1:
6804 // gen_helper_dmfc0_performance1(arg);
6805 rn = "Performance1";
6806 // break;
6807 case 2:
6808 // gen_helper_dmfc0_performance2(arg);
6809 rn = "Performance2";
6810 // break;
6811 case 3:
6812 // gen_helper_dmfc0_performance3(arg);
6813 rn = "Performance3";
6814 // break;
6815 case 4:
6816 // gen_helper_dmfc0_performance4(arg);
6817 rn = "Performance4";
6818 // break;
6819 case 5:
6820 // gen_helper_dmfc0_performance5(arg);
6821 rn = "Performance5";
6822 // break;
6823 case 6:
6824 // gen_helper_dmfc0_performance6(arg);
6825 rn = "Performance6";
6826 // break;
6827 case 7:
6828 // gen_helper_dmfc0_performance7(arg);
6829 rn = "Performance7";
6830 // break;
6831 default:
6832 goto cp0_unimplemented;
6833 }
6834 break;
6835 case 26:
6836 switch (sel) {
6837 case 0:
6838 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
6839 rn = "ErrCtl";
6840 break;
6841 default:
6842 goto cp0_unimplemented;
6843 }
6844 break;
6845 case 27:
6846 switch (sel) {
6847 /* ignored */
6848 case 0 ... 3:
6849 tcg_gen_movi_tl(arg, 0); /* unimplemented */
6850 rn = "CacheErr";
6851 break;
6852 default:
6853 goto cp0_unimplemented;
6854 }
6855 break;
6856 case 28:
6857 switch (sel) {
6858 case 0:
6859 case 2:
6860 case 4:
6861 case 6:
6862 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
6863 rn = "TagLo";
6864 break;
6865 case 1:
6866 case 3:
6867 case 5:
6868 case 7:
6869 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
6870 rn = "DataLo";
6871 break;
6872 default:
6873 goto cp0_unimplemented;
6874 }
6875 break;
6876 case 29:
6877 switch (sel) {
6878 case 0:
6879 case 2:
6880 case 4:
6881 case 6:
6882 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
6883 rn = "TagHi";
6884 break;
6885 case 1:
6886 case 3:
6887 case 5:
6888 case 7:
6889 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
6890 rn = "DataHi";
6891 break;
6892 default:
6893 goto cp0_unimplemented;
6894 }
6895 break;
6896 case 30:
6897 switch (sel) {
6898 case 0:
6899 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
6900 rn = "ErrorEPC";
6901 break;
6902 default:
6903 goto cp0_unimplemented;
6904 }
6905 break;
6906 case 31:
6907 switch (sel) {
6908 case 0:
6909 /* EJTAG support */
6910 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
6911 rn = "DESAVE";
6912 break;
6913 case 2 ... 7:
6914 CP0_CHECK(ctx->kscrexist & (1 << sel));
6915 tcg_gen_ld_tl(arg, cpu_env,
6916 offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
6917 rn = "KScratch";
6918 break;
6919 default:
6920 goto cp0_unimplemented;
6921 }
6922 break;
6923 default:
6924 goto cp0_unimplemented;
6925 }
6926 (void)rn; /* avoid a compiler warning */
6927 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
6928 return;
6929
6930 cp0_unimplemented:
6931 qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
6932 gen_mfc0_unimplemented(ctx, arg);
6933 }
6934
6935 static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
6936 {
6937 const char *rn = "invalid";
6938
6939 if (sel != 0)
6940 check_insn(ctx, ISA_MIPS64);
6941
6942 if (ctx->tb->cflags & CF_USE_ICOUNT) {
6943 gen_io_start();
6944 }
6945
6946 switch (reg) {
6947 case 0:
6948 switch (sel) {
6949 case 0:
6950 gen_helper_mtc0_index(cpu_env, arg);
6951 rn = "Index";
6952 break;
6953 case 1:
6954 CP0_CHECK(ctx->insn_flags & ASE_MT);
6955 gen_helper_mtc0_mvpcontrol(cpu_env, arg);
6956 rn = "MVPControl";
6957 break;
6958 case 2:
6959 CP0_CHECK(ctx->insn_flags & ASE_MT);
6960 /* ignored */
6961 rn = "MVPConf0";
6962 break;
6963 case 3:
6964 CP0_CHECK(ctx->insn_flags & ASE_MT);
6965 /* ignored */
6966 rn = "MVPConf1";
6967 break;
6968 case 4:
6969 CP0_CHECK(ctx->vp);
6970 /* ignored */
6971 rn = "VPControl";
6972 break;
6973 default:
6974 goto cp0_unimplemented;
6975 }
6976 break;
6977 case 1:
6978 switch (sel) {
6979 case 0:
6980 /* ignored */
6981 rn = "Random";
6982 break;
6983 case 1:
6984 CP0_CHECK(ctx->insn_flags & ASE_MT);
6985 gen_helper_mtc0_vpecontrol(cpu_env, arg);
6986 rn = "VPEControl";
6987 break;
6988 case 2:
6989 CP0_CHECK(ctx->insn_flags & ASE_MT);
6990 gen_helper_mtc0_vpeconf0(cpu_env, arg);
6991 rn = "VPEConf0";
6992 break;
6993 case 3:
6994 CP0_CHECK(ctx->insn_flags & ASE_MT);
6995 gen_helper_mtc0_vpeconf1(cpu_env, arg);
6996 rn = "VPEConf1";
6997 break;
6998 case 4:
6999 CP0_CHECK(ctx->insn_flags & ASE_MT);
7000 gen_helper_mtc0_yqmask(cpu_env, arg);
7001 rn = "YQMask";
7002 break;
7003 case 5:
7004 CP0_CHECK(ctx->insn_flags & ASE_MT);
7005 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
7006 rn = "VPESchedule";
7007 break;
7008 case 6:
7009 CP0_CHECK(ctx->insn_flags & ASE_MT);
7010 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
7011 rn = "VPEScheFBack";
7012 break;
7013 case 7:
7014 CP0_CHECK(ctx->insn_flags & ASE_MT);
7015 gen_helper_mtc0_vpeopt(cpu_env, arg);
7016 rn = "VPEOpt";
7017 break;
7018 default:
7019 goto cp0_unimplemented;
7020 }
7021 break;
7022 case 2:
7023 switch (sel) {
7024 case 0:
7025 gen_helper_dmtc0_entrylo0(cpu_env, arg);
7026 rn = "EntryLo0";
7027 break;
7028 case 1:
7029 CP0_CHECK(ctx->insn_flags & ASE_MT);
7030 gen_helper_mtc0_tcstatus(cpu_env, arg);
7031 rn = "TCStatus";
7032 break;
7033 case 2:
7034 CP0_CHECK(ctx->insn_flags & ASE_MT);
7035 gen_helper_mtc0_tcbind(cpu_env, arg);
7036 rn = "TCBind";
7037 break;
7038 case 3:
7039 CP0_CHECK(ctx->insn_flags & ASE_MT);
7040 gen_helper_mtc0_tcrestart(cpu_env, arg);
7041 rn = "TCRestart";
7042 break;
7043 case 4:
7044 CP0_CHECK(ctx->insn_flags & ASE_MT);
7045 gen_helper_mtc0_tchalt(cpu_env, arg);
7046 rn = "TCHalt";
7047 break;
7048 case 5:
7049 CP0_CHECK(ctx->insn_flags & ASE_MT);
7050 gen_helper_mtc0_tccontext(cpu_env, arg);
7051 rn = "TCContext";
7052 break;
7053 case 6:
7054 CP0_CHECK(ctx->insn_flags & ASE_MT);
7055 gen_helper_mtc0_tcschedule(cpu_env, arg);
7056 rn = "TCSchedule";
7057 break;
7058 case 7:
7059 CP0_CHECK(ctx->insn_flags & ASE_MT);
7060 gen_helper_mtc0_tcschefback(cpu_env, arg);
7061 rn = "TCScheFBack";
7062 break;
7063 default:
7064 goto cp0_unimplemented;
7065 }
7066 break;
7067 case 3:
7068 switch (sel) {
7069 case 0:
7070 gen_helper_dmtc0_entrylo1(cpu_env, arg);
7071 rn = "EntryLo1";
7072 break;
7073 case 1:
7074 CP0_CHECK(ctx->vp);
7075 /* ignored */
7076 rn = "GlobalNumber";
7077 break;
7078 default:
7079 goto cp0_unimplemented;
7080 }
7081 break;
7082 case 4:
7083 switch (sel) {
7084 case 0:
7085 gen_helper_mtc0_context(cpu_env, arg);
7086 rn = "Context";
7087 break;
7088 case 1:
7089 // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
7090 rn = "ContextConfig";
7091 goto cp0_unimplemented;
7092 case 2:
7093 CP0_CHECK(ctx->ulri);
7094 tcg_gen_st_tl(arg, cpu_env,
7095 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
7096 rn = "UserLocal";
7097 break;
7098 default:
7099 goto cp0_unimplemented;
7100 }
7101 break;
7102 case 5:
7103 switch (sel) {
7104 case 0:
7105 gen_helper_mtc0_pagemask(cpu_env, arg);
7106 rn = "PageMask";
7107 break;
7108 case 1:
7109 check_insn(ctx, ISA_MIPS32R2);
7110 gen_helper_mtc0_pagegrain(cpu_env, arg);
7111 rn = "PageGrain";
7112 break;
7113 default:
7114 goto cp0_unimplemented;
7115 }
7116 break;
7117 case 6:
7118 switch (sel) {
7119 case 0:
7120 gen_helper_mtc0_wired(cpu_env, arg);
7121 rn = "Wired";
7122 break;
7123 case 1:
7124 check_insn(ctx, ISA_MIPS32R2);
7125 gen_helper_mtc0_srsconf0(cpu_env, arg);
7126 rn = "SRSConf0";
7127 break;
7128 case 2:
7129 check_insn(ctx, ISA_MIPS32R2);
7130 gen_helper_mtc0_srsconf1(cpu_env, arg);
7131 rn = "SRSConf1";
7132 break;
7133 case 3:
7134 check_insn(ctx, ISA_MIPS32R2);
7135 gen_helper_mtc0_srsconf2(cpu_env, arg);
7136 rn = "SRSConf2";
7137 break;
7138 case 4:
7139 check_insn(ctx, ISA_MIPS32R2);
7140 gen_helper_mtc0_srsconf3(cpu_env, arg);
7141 rn = "SRSConf3";
7142 break;
7143 case 5:
7144 check_insn(ctx, ISA_MIPS32R2);
7145 gen_helper_mtc0_srsconf4(cpu_env, arg);
7146 rn = "SRSConf4";
7147 break;
7148 default:
7149 goto cp0_unimplemented;
7150 }
7151 break;
7152 case 7:
7153 switch (sel) {
7154 case 0:
7155 check_insn(ctx, ISA_MIPS32R2);
7156 gen_helper_mtc0_hwrena(cpu_env, arg);
7157 ctx->bstate = BS_STOP;
7158 rn = "HWREna";
7159 break;
7160 default:
7161 goto cp0_unimplemented;
7162 }
7163 break;
7164 case 8:
7165 switch (sel) {
7166 case 0:
7167 /* ignored */
7168 rn = "BadVAddr";
7169 break;
7170 case 1:
7171 /* ignored */
7172 rn = "BadInstr";
7173 break;
7174 case 2:
7175 /* ignored */
7176 rn = "BadInstrP";
7177 break;
7178 default:
7179 goto cp0_unimplemented;
7180 }
7181 break;
7182 case 9:
7183 switch (sel) {
7184 case 0:
7185 gen_helper_mtc0_count(cpu_env, arg);
7186 rn = "Count";
7187 break;
7188 /* 6,7 are implementation dependent */
7189 default:
7190 goto cp0_unimplemented;
7191 }
7192 /* Stop translation as we may have switched the execution mode */
7193 ctx->bstate = BS_STOP;
7194 break;
7195 case 10:
7196 switch (sel) {
7197 case 0:
7198 gen_helper_mtc0_entryhi(cpu_env, arg);
7199 rn = "EntryHi";
7200 break;
7201 default:
7202 goto cp0_unimplemented;
7203 }
7204 break;
7205 case 11:
7206 switch (sel) {
7207 case 0:
7208 gen_helper_mtc0_compare(cpu_env, arg);
7209 rn = "Compare";
7210 break;
7211 /* 6,7 are implementation dependent */
7212 default:
7213 goto cp0_unimplemented;
7214 }
7215 /* Stop translation as we may have switched the execution mode */
7216 ctx->bstate = BS_STOP;
7217 break;
7218 case 12:
7219 switch (sel) {
7220 case 0:
7221 save_cpu_state(ctx, 1);
7222 gen_helper_mtc0_status(cpu_env, arg);
7223 /* BS_STOP isn't good enough here, hflags may have changed. */
7224 gen_save_pc(ctx->pc + 4);
7225 ctx->bstate = BS_EXCP;
7226 rn = "Status";
7227 break;
7228 case 1:
7229 check_insn(ctx, ISA_MIPS32R2);
7230 gen_helper_mtc0_intctl(cpu_env, arg);
7231 /* Stop translation as we may have switched the execution mode */
7232 ctx->bstate = BS_STOP;
7233 rn = "IntCtl";
7234 break;
7235 case 2:
7236 check_insn(ctx, ISA_MIPS32R2);
7237 gen_helper_mtc0_srsctl(cpu_env, arg);
7238 /* Stop translation as we may have switched the execution mode */
7239 ctx->bstate = BS_STOP;
7240 rn = "SRSCtl";
7241 break;
7242 case 3:
7243 check_insn(ctx, ISA_MIPS32R2);
7244 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
7245 /* Stop translation as we may have switched the execution mode */
7246 ctx->bstate = BS_STOP;
7247 rn = "SRSMap";
7248 break;
7249 default:
7250 goto cp0_unimplemented;
7251 }
7252 break;
7253 case 13:
7254 switch (sel) {
7255 case 0:
7256 save_cpu_state(ctx, 1);
7257 /* Mark as an IO operation because we may trigger a software
7258 interrupt. */
7259 if (ctx->tb->cflags & CF_USE_ICOUNT) {
7260 gen_io_start();
7261 }
7262 gen_helper_mtc0_cause(cpu_env, arg);
7263 if (ctx->tb->cflags & CF_USE_ICOUNT) {
7264 gen_io_end();
7265 }
7266 /* Stop translation as we may have triggered an intetrupt */
7267 ctx->bstate = BS_STOP;
7268 rn = "Cause";
7269 break;
7270 default:
7271 goto cp0_unimplemented;
7272 }
7273 break;
7274 case 14:
7275 switch (sel) {
7276 case 0:
7277 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
7278 rn = "EPC";
7279 break;
7280 default:
7281 goto cp0_unimplemented;
7282 }
7283 break;
7284 case 15:
7285 switch (sel) {
7286 case 0:
7287 /* ignored */
7288 rn = "PRid";
7289 break;
7290 case 1:
7291 check_insn(ctx, ISA_MIPS32R2);
7292 gen_helper_mtc0_ebase(cpu_env, arg);
7293 rn = "EBase";
7294 break;
7295 default:
7296 goto cp0_unimplemented;
7297 }
7298 break;
7299 case 16:
7300 switch (sel) {
7301 case 0:
7302 gen_helper_mtc0_config0(cpu_env, arg);
7303 rn = "Config";
7304 /* Stop translation as we may have switched the execution mode */
7305 ctx->bstate = BS_STOP;
7306 break;
7307 case 1:
7308 /* ignored, read only */
7309 rn = "Config1";
7310 break;
7311 case 2:
7312 gen_helper_mtc0_config2(cpu_env, arg);
7313 rn = "Config2";
7314 /* Stop translation as we may have switched the execution mode */
7315 ctx->bstate = BS_STOP;
7316 break;
7317 case 3:
7318 gen_helper_mtc0_config3(cpu_env, arg);
7319 rn = "Config3";
7320 /* Stop translation as we may have switched the execution mode */
7321 ctx->bstate = BS_STOP;
7322 break;
7323 case 4:
7324 /* currently ignored */
7325 rn = "Config4";
7326 break;
7327 case 5:
7328 gen_helper_mtc0_config5(cpu_env, arg);
7329 rn = "Config5";
7330 /* Stop translation as we may have switched the execution mode */
7331 ctx->bstate = BS_STOP;
7332 break;
7333 /* 6,7 are implementation dependent */
7334 default:
7335 rn = "Invalid config selector";
7336 goto cp0_unimplemented;
7337 }
7338 break;
7339 case 17:
7340 switch (sel) {
7341 case 0:
7342 gen_helper_mtc0_lladdr(cpu_env, arg);
7343 rn = "LLAddr";
7344 break;
7345 case 1:
7346 CP0_CHECK(ctx->mrp);
7347 gen_helper_mtc0_maar(cpu_env, arg);
7348 rn = "MAAR";
7349 break;
7350 case 2:
7351 CP0_CHECK(ctx->mrp);
7352 gen_helper_mtc0_maari(cpu_env, arg);
7353 rn = "MAARI";
7354 break;
7355 default:
7356 goto cp0_unimplemented;
7357 }
7358 break;
7359 case 18:
7360 switch (sel) {
7361 case 0 ... 7:
7362 gen_helper_0e1i(mtc0_watchlo, arg, sel);
7363 rn = "WatchLo";
7364 break;
7365 default:
7366 goto cp0_unimplemented;
7367 }
7368 break;
7369 case 19:
7370 switch (sel) {
7371 case 0 ... 7:
7372 gen_helper_0e1i(mtc0_watchhi, arg, sel);
7373 rn = "WatchHi";
7374 break;
7375 default:
7376 goto cp0_unimplemented;
7377 }
7378 break;
7379 case 20:
7380 switch (sel) {
7381 case 0:
7382 check_insn(ctx, ISA_MIPS3);
7383 gen_helper_mtc0_xcontext(cpu_env, arg);
7384 rn = "XContext";
7385 break;
7386 default:
7387 goto cp0_unimplemented;
7388 }
7389 break;
7390 case 21:
7391 /* Officially reserved, but sel 0 is used for R1x000 framemask */
7392 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
7393 switch (sel) {
7394 case 0:
7395 gen_helper_mtc0_framemask(cpu_env, arg);
7396 rn = "Framemask";
7397 break;
7398 default:
7399 goto cp0_unimplemented;
7400 }
7401 break;
7402 case 22:
7403 /* ignored */
7404 rn = "Diagnostic"; /* implementation dependent */
7405 break;
7406 case 23:
7407 switch (sel) {
7408 case 0:
7409 gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
7410 /* BS_STOP isn't good enough here, hflags may have changed. */
7411 gen_save_pc(ctx->pc + 4);
7412 ctx->bstate = BS_EXCP;
7413 rn = "Debug";
7414 break;
7415 case 1:
7416 // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
7417 /* Stop translation as we may have switched the execution mode */
7418 ctx->bstate = BS_STOP;
7419 rn = "TraceControl";
7420 // break;
7421 case 2:
7422 // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
7423 /* Stop translation as we may have switched the execution mode */
7424 ctx->bstate = BS_STOP;
7425 rn = "TraceControl2";
7426 // break;
7427 case 3:
7428 // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
7429 /* Stop translation as we may have switched the execution mode */
7430 ctx->bstate = BS_STOP;
7431 rn = "UserTraceData";
7432 // break;
7433 case 4:
7434 // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
7435 /* Stop translation as we may have switched the execution mode */
7436 ctx->bstate = BS_STOP;
7437 rn = "TraceBPC";
7438 // break;
7439 default:
7440 goto cp0_unimplemented;
7441 }
7442 break;
7443 case 24:
7444 switch (sel) {
7445 case 0:
7446 /* EJTAG support */
7447 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
7448 rn = "DEPC";
7449 break;
7450 default:
7451 goto cp0_unimplemented;
7452 }
7453 break;
7454 case 25:
7455 switch (sel) {
7456 case 0:
7457 gen_helper_mtc0_performance0(cpu_env, arg);
7458 rn = "Performance0";
7459 break;
7460 case 1:
7461 // gen_helper_mtc0_performance1(cpu_env, arg);
7462 rn = "Performance1";
7463 // break;
7464 case 2:
7465 // gen_helper_mtc0_performance2(cpu_env, arg);
7466 rn = "Performance2";
7467 // break;
7468 case 3:
7469 // gen_helper_mtc0_performance3(cpu_env, arg);
7470 rn = "Performance3";
7471 // break;
7472 case 4:
7473 // gen_helper_mtc0_performance4(cpu_env, arg);
7474 rn = "Performance4";
7475 // break;
7476 case 5:
7477 // gen_helper_mtc0_performance5(cpu_env, arg);
7478 rn = "Performance5";
7479 // break;
7480 case 6:
7481 // gen_helper_mtc0_performance6(cpu_env, arg);
7482 rn = "Performance6";
7483 // break;
7484 case 7:
7485 // gen_helper_mtc0_performance7(cpu_env, arg);
7486 rn = "Performance7";
7487 // break;
7488 default:
7489 goto cp0_unimplemented;
7490 }
7491 break;
7492 case 26:
7493 switch (sel) {
7494 case 0:
7495 gen_helper_mtc0_errctl(cpu_env, arg);
7496 ctx->bstate = BS_STOP;
7497 rn = "ErrCtl";
7498 break;
7499 default:
7500 goto cp0_unimplemented;
7501 }
7502 break;
7503 case 27:
7504 switch (sel) {
7505 case 0 ... 3:
7506 /* ignored */
7507 rn = "CacheErr";
7508 break;
7509 default:
7510 goto cp0_unimplemented;
7511 }
7512 break;
7513 case 28:
7514 switch (sel) {
7515 case 0:
7516 case 2:
7517 case 4:
7518 case 6:
7519 gen_helper_mtc0_taglo(cpu_env, arg);
7520 rn = "TagLo";
7521 break;
7522 case 1:
7523 case 3:
7524 case 5:
7525 case 7:
7526 gen_helper_mtc0_datalo(cpu_env, arg);
7527 rn = "DataLo";
7528 break;
7529 default:
7530 goto cp0_unimplemented;
7531 }
7532 break;
7533 case 29:
7534 switch (sel) {
7535 case 0:
7536 case 2:
7537 case 4:
7538 case 6:
7539 gen_helper_mtc0_taghi(cpu_env, arg);
7540 rn = "TagHi";
7541 break;
7542 case 1:
7543 case 3:
7544 case 5:
7545 case 7:
7546 gen_helper_mtc0_datahi(cpu_env, arg);
7547 rn = "DataHi";
7548 break;
7549 default:
7550 rn = "invalid sel";
7551 goto cp0_unimplemented;
7552 }
7553 break;
7554 case 30:
7555 switch (sel) {
7556 case 0:
7557 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
7558 rn = "ErrorEPC";
7559 break;
7560 default:
7561 goto cp0_unimplemented;
7562 }
7563 break;
7564 case 31:
7565 switch (sel) {
7566 case 0:
7567 /* EJTAG support */
7568 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
7569 rn = "DESAVE";
7570 break;
7571 case 2 ... 7:
7572 CP0_CHECK(ctx->kscrexist & (1 << sel));
7573 tcg_gen_st_tl(arg, cpu_env,
7574 offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
7575 rn = "KScratch";
7576 break;
7577 default:
7578 goto cp0_unimplemented;
7579 }
7580 /* Stop translation as we may have switched the execution mode */
7581 ctx->bstate = BS_STOP;
7582 break;
7583 default:
7584 goto cp0_unimplemented;
7585 }
7586 (void)rn; /* avoid a compiler warning */
7587 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
7588 /* For simplicity assume that all writes can cause interrupts. */
7589 if (ctx->tb->cflags & CF_USE_ICOUNT) {
7590 gen_io_end();
7591 ctx->bstate = BS_STOP;
7592 }
7593 return;
7594
7595 cp0_unimplemented:
7596 qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
7597 }
7598 #endif /* TARGET_MIPS64 */
7599
7600 static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
7601 int u, int sel, int h)
7602 {
7603 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
7604 TCGv t0 = tcg_temp_local_new();
7605
7606 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
7607 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
7608 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
7609 tcg_gen_movi_tl(t0, -1);
7610 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
7611 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
7612 tcg_gen_movi_tl(t0, -1);
7613 else if (u == 0) {
7614 switch (rt) {
7615 case 1:
7616 switch (sel) {
7617 case 1:
7618 gen_helper_mftc0_vpecontrol(t0, cpu_env);
7619 break;
7620 case 2:
7621 gen_helper_mftc0_vpeconf0(t0, cpu_env);
7622 break;
7623 default:
7624 goto die;
7625 break;
7626 }
7627 break;
7628 case 2:
7629 switch (sel) {
7630 case 1:
7631 gen_helper_mftc0_tcstatus(t0, cpu_env);
7632 break;
7633 case 2:
7634 gen_helper_mftc0_tcbind(t0, cpu_env);
7635 break;
7636 case 3:
7637 gen_helper_mftc0_tcrestart(t0, cpu_env);
7638 break;
7639 case 4:
7640 gen_helper_mftc0_tchalt(t0, cpu_env);
7641 break;
7642 case 5:
7643 gen_helper_mftc0_tccontext(t0, cpu_env);
7644 break;
7645 case 6:
7646 gen_helper_mftc0_tcschedule(t0, cpu_env);
7647 break;
7648 case 7:
7649 gen_helper_mftc0_tcschefback(t0, cpu_env);
7650 break;
7651 default:
7652 gen_mfc0(ctx, t0, rt, sel);
7653 break;
7654 }
7655 break;
7656 case 10:
7657 switch (sel) {
7658 case 0:
7659 gen_helper_mftc0_entryhi(t0, cpu_env);
7660 break;
7661 default:
7662 gen_mfc0(ctx, t0, rt, sel);
7663 break;
7664 }
7665 case 12:
7666 switch (sel) {
7667 case 0:
7668 gen_helper_mftc0_status(t0, cpu_env);
7669 break;
7670 default:
7671 gen_mfc0(ctx, t0, rt, sel);
7672 break;
7673 }
7674 case 13:
7675 switch (sel) {
7676 case 0:
7677 gen_helper_mftc0_cause(t0, cpu_env);
7678 break;
7679 default:
7680 goto die;
7681 break;
7682 }
7683 break;
7684 case 14:
7685 switch (sel) {
7686 case 0:
7687 gen_helper_mftc0_epc(t0, cpu_env);
7688 break;
7689 default:
7690 goto die;
7691 break;
7692 }
7693 break;
7694 case 15:
7695 switch (sel) {
7696 case 1:
7697 gen_helper_mftc0_ebase(t0, cpu_env);
7698 break;
7699 default:
7700 goto die;
7701 break;
7702 }
7703 break;
7704 case 16:
7705 switch (sel) {
7706 case 0 ... 7:
7707 gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel));
7708 break;
7709 default:
7710 goto die;
7711 break;
7712 }
7713 break;
7714 case 23:
7715 switch (sel) {
7716 case 0:
7717 gen_helper_mftc0_debug(t0, cpu_env);
7718 break;
7719 default:
7720 gen_mfc0(ctx, t0, rt, sel);
7721 break;
7722 }
7723 break;
7724 default:
7725 gen_mfc0(ctx, t0, rt, sel);
7726 }
7727 } else switch (sel) {
7728 /* GPR registers. */
7729 case 0:
7730 gen_helper_1e0i(mftgpr, t0, rt);
7731 break;
7732 /* Auxiliary CPU registers */
7733 case 1:
7734 switch (rt) {
7735 case 0:
7736 gen_helper_1e0i(mftlo, t0, 0);
7737 break;
7738 case 1:
7739 gen_helper_1e0i(mfthi, t0, 0);
7740 break;
7741 case 2:
7742 gen_helper_1e0i(mftacx, t0, 0);
7743 break;
7744 case 4:
7745 gen_helper_1e0i(mftlo, t0, 1);
7746 break;
7747 case 5:
7748 gen_helper_1e0i(mfthi, t0, 1);
7749 break;
7750 case 6:
7751 gen_helper_1e0i(mftacx, t0, 1);
7752 break;
7753 case 8:
7754 gen_helper_1e0i(mftlo, t0, 2);
7755 break;
7756 case 9:
7757 gen_helper_1e0i(mfthi, t0, 2);
7758 break;
7759 case 10:
7760 gen_helper_1e0i(mftacx, t0, 2);
7761 break;
7762 case 12:
7763 gen_helper_1e0i(mftlo, t0, 3);
7764 break;
7765 case 13:
7766 gen_helper_1e0i(mfthi, t0, 3);
7767 break;
7768 case 14:
7769 gen_helper_1e0i(mftacx, t0, 3);
7770 break;
7771 case 16:
7772 gen_helper_mftdsp(t0, cpu_env);
7773 break;
7774 default:
7775 goto die;
7776 }
7777 break;
7778 /* Floating point (COP1). */
7779 case 2:
7780 /* XXX: For now we support only a single FPU context. */
7781 if (h == 0) {
7782 TCGv_i32 fp0 = tcg_temp_new_i32();
7783
7784 gen_load_fpr32(ctx, fp0, rt);
7785 tcg_gen_ext_i32_tl(t0, fp0);
7786 tcg_temp_free_i32(fp0);
7787 } else {
7788 TCGv_i32 fp0 = tcg_temp_new_i32();
7789
7790 gen_load_fpr32h(ctx, fp0, rt);
7791 tcg_gen_ext_i32_tl(t0, fp0);
7792 tcg_temp_free_i32(fp0);
7793 }
7794 break;
7795 case 3:
7796 /* XXX: For now we support only a single FPU context. */
7797 gen_helper_1e0i(cfc1, t0, rt);
7798 break;
7799 /* COP2: Not implemented. */
7800 case 4:
7801 case 5:
7802 /* fall through */
7803 default:
7804 goto die;
7805 }
7806 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
7807 gen_store_gpr(t0, rd);
7808 tcg_temp_free(t0);
7809 return;
7810
7811 die:
7812 tcg_temp_free(t0);
7813 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
7814 generate_exception_end(ctx, EXCP_RI);
7815 }
7816
7817 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
7818 int u, int sel, int h)
7819 {
7820 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
7821 TCGv t0 = tcg_temp_local_new();
7822
7823 gen_load_gpr(t0, rt);
7824 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
7825 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
7826 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
7827 /* NOP */ ;
7828 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
7829 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
7830 /* NOP */ ;
7831 else if (u == 0) {
7832 switch (rd) {
7833 case 1:
7834 switch (sel) {
7835 case 1:
7836 gen_helper_mttc0_vpecontrol(cpu_env, t0);
7837 break;
7838 case 2:
7839 gen_helper_mttc0_vpeconf0(cpu_env, t0);
7840 break;
7841 default:
7842 goto die;
7843 break;
7844 }
7845 break;
7846 case 2:
7847 switch (sel) {
7848 case 1:
7849 gen_helper_mttc0_tcstatus(cpu_env, t0);
7850 break;
7851 case 2:
7852 gen_helper_mttc0_tcbind(cpu_env, t0);
7853 break;
7854 case 3:
7855 gen_helper_mttc0_tcrestart(cpu_env, t0);
7856 break;
7857 case 4:
7858 gen_helper_mttc0_tchalt(cpu_env, t0);
7859 break;
7860 case 5:
7861 gen_helper_mttc0_tccontext(cpu_env, t0);
7862 break;
7863 case 6:
7864 gen_helper_mttc0_tcschedule(cpu_env, t0);
7865 break;
7866 case 7:
7867 gen_helper_mttc0_tcschefback(cpu_env, t0);
7868 break;
7869 default:
7870 gen_mtc0(ctx, t0, rd, sel);
7871 break;
7872 }
7873 break;
7874 case 10:
7875 switch (sel) {
7876 case 0:
7877 gen_helper_mttc0_entryhi(cpu_env, t0);
7878 break;
7879 default:
7880 gen_mtc0(ctx, t0, rd, sel);
7881 break;
7882 }
7883 case 12:
7884 switch (sel) {
7885 case 0:
7886 gen_helper_mttc0_status(cpu_env, t0);
7887 break;
7888 default:
7889 gen_mtc0(ctx, t0, rd, sel);
7890 break;
7891 }
7892 case 13:
7893 switch (sel) {
7894 case 0:
7895 gen_helper_mttc0_cause(cpu_env, t0);
7896 break;
7897 default:
7898 goto die;
7899 break;
7900 }
7901 break;
7902 case 15:
7903 switch (sel) {
7904 case 1:
7905 gen_helper_mttc0_ebase(cpu_env, t0);
7906 break;
7907 default:
7908 goto die;
7909 break;
7910 }
7911 break;
7912 case 23:
7913 switch (sel) {
7914 case 0:
7915 gen_helper_mttc0_debug(cpu_env, t0);
7916 break;
7917 default:
7918 gen_mtc0(ctx, t0, rd, sel);
7919 break;
7920 }
7921 break;
7922 default:
7923 gen_mtc0(ctx, t0, rd, sel);
7924 }
7925 } else switch (sel) {
7926 /* GPR registers. */
7927 case 0:
7928 gen_helper_0e1i(mttgpr, t0, rd);
7929 break;
7930 /* Auxiliary CPU registers */
7931 case 1:
7932 switch (rd) {
7933 case 0:
7934 gen_helper_0e1i(mttlo, t0, 0);
7935 break;
7936 case 1:
7937 gen_helper_0e1i(mtthi, t0, 0);
7938 break;
7939 case 2:
7940 gen_helper_0e1i(mttacx, t0, 0);
7941 break;
7942 case 4:
7943 gen_helper_0e1i(mttlo, t0, 1);
7944 break;
7945 case 5:
7946 gen_helper_0e1i(mtthi, t0, 1);
7947 break;
7948 case 6:
7949 gen_helper_0e1i(mttacx, t0, 1);
7950 break;
7951 case 8:
7952 gen_helper_0e1i(mttlo, t0, 2);
7953 break;
7954 case 9:
7955 gen_helper_0e1i(mtthi, t0, 2);
7956 break;
7957 case 10:
7958 gen_helper_0e1i(mttacx, t0, 2);
7959 break;
7960 case 12:
7961 gen_helper_0e1i(mttlo, t0, 3);
7962 break;
7963 case 13:
7964 gen_helper_0e1i(mtthi, t0, 3);
7965 break;
7966 case 14:
7967 gen_helper_0e1i(mttacx, t0, 3);
7968 break;
7969 case 16:
7970 gen_helper_mttdsp(cpu_env, t0);
7971 break;
7972 default:
7973 goto die;
7974 }
7975 break;
7976 /* Floating point (COP1). */
7977 case 2:
7978 /* XXX: For now we support only a single FPU context. */
7979 if (h == 0) {
7980 TCGv_i32 fp0 = tcg_temp_new_i32();
7981
7982 tcg_gen_trunc_tl_i32(fp0, t0);
7983 gen_store_fpr32(ctx, fp0, rd);
7984 tcg_temp_free_i32(fp0);
7985 } else {
7986 TCGv_i32 fp0 = tcg_temp_new_i32();
7987
7988 tcg_gen_trunc_tl_i32(fp0, t0);
7989 gen_store_fpr32h(ctx, fp0, rd);
7990 tcg_temp_free_i32(fp0);
7991 }
7992 break;
7993 case 3:
7994 /* XXX: For now we support only a single FPU context. */
7995 {
7996 TCGv_i32 fs_tmp = tcg_const_i32(rd);
7997
7998 gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
7999 tcg_temp_free_i32(fs_tmp);
8000 }
8001 /* Stop translation as we may have changed hflags */
8002 ctx->bstate = BS_STOP;
8003 break;
8004 /* COP2: Not implemented. */
8005 case 4:
8006 case 5:
8007 /* fall through */
8008 default:
8009 goto die;
8010 }
8011 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
8012 tcg_temp_free(t0);
8013 return;
8014
8015 die:
8016 tcg_temp_free(t0);
8017 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
8018 generate_exception_end(ctx, EXCP_RI);
8019 }
8020
8021 static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
8022 {
8023 const char *opn = "ldst";
8024
8025 check_cp0_enabled(ctx);
8026 switch (opc) {
8027 case OPC_MFC0:
8028 if (rt == 0) {
8029 /* Treat as NOP. */
8030 return;
8031 }
8032 gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
8033 opn = "mfc0";
8034 break;
8035 case OPC_MTC0:
8036 {
8037 TCGv t0 = tcg_temp_new();
8038
8039 gen_load_gpr(t0, rt);
8040 gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7);
8041 tcg_temp_free(t0);
8042 }
8043 opn = "mtc0";
8044 break;
8045 #if defined(TARGET_MIPS64)
8046 case OPC_DMFC0:
8047 check_insn(ctx, ISA_MIPS3);
8048 if (rt == 0) {
8049 /* Treat as NOP. */
8050 return;
8051 }
8052 gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
8053 opn = "dmfc0";
8054 break;
8055 case OPC_DMTC0:
8056 check_insn(ctx, ISA_MIPS3);
8057 {
8058 TCGv t0 = tcg_temp_new();
8059
8060 gen_load_gpr(t0, rt);
8061 gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7);
8062 tcg_temp_free(t0);
8063 }
8064 opn = "dmtc0";
8065 break;
8066 #endif
8067 case OPC_MFHC0:
8068 check_mvh(ctx);
8069 if (rt == 0) {
8070 /* Treat as NOP. */
8071 return;
8072 }
8073 gen_mfhc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
8074 opn = "mfhc0";
8075 break;
8076 case OPC_MTHC0:
8077 check_mvh(ctx);
8078 {
8079 TCGv t0 = tcg_temp_new();
8080 gen_load_gpr(t0, rt);
8081 gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7);
8082 tcg_temp_free(t0);
8083 }
8084 opn = "mthc0";
8085 break;
8086 case OPC_MFTR:
8087 check_insn(ctx, ASE_MT);
8088 if (rd == 0) {
8089 /* Treat as NOP. */
8090 return;
8091 }
8092 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1,
8093 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
8094 opn = "mftr";
8095 break;
8096 case OPC_MTTR:
8097 check_insn(ctx, ASE_MT);
8098 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
8099 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
8100 opn = "mttr";
8101 break;
8102 case OPC_TLBWI:
8103 opn = "tlbwi";
8104 if (!env->tlb->helper_tlbwi)
8105 goto die;
8106 gen_helper_tlbwi(cpu_env);
8107 break;
8108 case OPC_TLBINV:
8109 opn = "tlbinv";
8110 if (ctx->ie >= 2) {
8111 if (!env->tlb->helper_tlbinv) {
8112 goto die;
8113 }
8114 gen_helper_tlbinv(cpu_env);
8115 } /* treat as nop if TLBINV not supported */
8116 break;
8117 case OPC_TLBINVF:
8118 opn = "tlbinvf";
8119 if (ctx->ie >= 2) {
8120 if (!env->tlb->helper_tlbinvf) {
8121 goto die;
8122 }
8123 gen_helper_tlbinvf(cpu_env);
8124 } /* treat as nop if TLBINV not supported */
8125 break;
8126 case OPC_TLBWR:
8127 opn = "tlbwr";
8128 if (!env->tlb->helper_tlbwr)
8129 goto die;
8130 gen_helper_tlbwr(cpu_env);
8131 break;
8132 case OPC_TLBP:
8133 opn = "tlbp";
8134 if (!env->tlb->helper_tlbp)
8135 goto die;
8136 gen_helper_tlbp(cpu_env);
8137 break;
8138 case OPC_TLBR:
8139 opn = "tlbr";
8140 if (!env->tlb->helper_tlbr)
8141 goto die;
8142 gen_helper_tlbr(cpu_env);
8143 break;
8144 case OPC_ERET: /* OPC_ERETNC */
8145 if ((ctx->insn_flags & ISA_MIPS32R6) &&
8146 (ctx->hflags & MIPS_HFLAG_BMASK)) {
8147 goto die;
8148 } else {
8149 int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6;
8150 if (ctx->opcode & (1 << bit_shift)) {
8151 /* OPC_ERETNC */
8152 opn = "eretnc";
8153 check_insn(ctx, ISA_MIPS32R5);
8154 gen_helper_eretnc(cpu_env);
8155 } else {
8156 /* OPC_ERET */
8157 opn = "eret";
8158 check_insn(ctx, ISA_MIPS2);
8159 gen_helper_eret(cpu_env);
8160 }
8161 ctx->bstate = BS_EXCP;
8162 }
8163 break;
8164 case OPC_DERET:
8165 opn = "deret";
8166 check_insn(ctx, ISA_MIPS32);
8167 if ((ctx->insn_flags & ISA_MIPS32R6) &&
8168 (ctx->hflags & MIPS_HFLAG_BMASK)) {
8169 goto die;
8170 }
8171 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
8172 MIPS_INVAL(opn);
8173 generate_exception_end(ctx, EXCP_RI);
8174 } else {
8175 gen_helper_deret(cpu_env);
8176 ctx->bstate = BS_EXCP;
8177 }
8178 break;
8179 case OPC_WAIT:
8180 opn = "wait";
8181 check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
8182 if ((ctx->insn_flags & ISA_MIPS32R6) &&
8183 (ctx->hflags & MIPS_HFLAG_BMASK)) {
8184 goto die;
8185 }
8186 /* If we get an exception, we want to restart at next instruction */
8187 ctx->pc += 4;
8188 save_cpu_state(ctx, 1);
8189 ctx->pc -= 4;
8190 gen_helper_wait(cpu_env);
8191 ctx->bstate = BS_EXCP;
8192 break;
8193 default:
8194 die:
8195 MIPS_INVAL(opn);
8196 generate_exception_end(ctx, EXCP_RI);
8197 return;
8198 }
8199 (void)opn; /* avoid a compiler warning */
8200 }
8201 #endif /* !CONFIG_USER_ONLY */
8202
8203 /* CP1 Branches (before delay slot) */
8204 static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
8205 int32_t cc, int32_t offset)
8206 {
8207 target_ulong btarget;
8208 TCGv_i32 t0 = tcg_temp_new_i32();
8209
8210 if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) {
8211 generate_exception_end(ctx, EXCP_RI);
8212 goto out;
8213 }
8214
8215 if (cc != 0)
8216 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
8217
8218 btarget = ctx->pc + 4 + offset;
8219
8220 switch (op) {
8221 case OPC_BC1F:
8222 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8223 tcg_gen_not_i32(t0, t0);
8224 tcg_gen_andi_i32(t0, t0, 1);
8225 tcg_gen_extu_i32_tl(bcond, t0);
8226 goto not_likely;
8227 case OPC_BC1FL:
8228 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8229 tcg_gen_not_i32(t0, t0);
8230 tcg_gen_andi_i32(t0, t0, 1);
8231 tcg_gen_extu_i32_tl(bcond, t0);
8232 goto likely;
8233 case OPC_BC1T:
8234 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8235 tcg_gen_andi_i32(t0, t0, 1);
8236 tcg_gen_extu_i32_tl(bcond, t0);
8237 goto not_likely;
8238 case OPC_BC1TL:
8239 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8240 tcg_gen_andi_i32(t0, t0, 1);
8241 tcg_gen_extu_i32_tl(bcond, t0);
8242 likely:
8243 ctx->hflags |= MIPS_HFLAG_BL;
8244 break;
8245 case OPC_BC1FANY2:
8246 {
8247 TCGv_i32 t1 = tcg_temp_new_i32();
8248 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8249 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
8250 tcg_gen_nand_i32(t0, t0, t1);
8251 tcg_temp_free_i32(t1);
8252 tcg_gen_andi_i32(t0, t0, 1);
8253 tcg_gen_extu_i32_tl(bcond, t0);
8254 }
8255 goto not_likely;
8256 case OPC_BC1TANY2:
8257 {
8258 TCGv_i32 t1 = tcg_temp_new_i32();
8259 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8260 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
8261 tcg_gen_or_i32(t0, t0, t1);
8262 tcg_temp_free_i32(t1);
8263 tcg_gen_andi_i32(t0, t0, 1);
8264 tcg_gen_extu_i32_tl(bcond, t0);
8265 }
8266 goto not_likely;
8267 case OPC_BC1FANY4:
8268 {
8269 TCGv_i32 t1 = tcg_temp_new_i32();
8270 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8271 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
8272 tcg_gen_and_i32(t0, t0, t1);
8273 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
8274 tcg_gen_and_i32(t0, t0, t1);
8275 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
8276 tcg_gen_nand_i32(t0, t0, t1);
8277 tcg_temp_free_i32(t1);
8278 tcg_gen_andi_i32(t0, t0, 1);
8279 tcg_gen_extu_i32_tl(bcond, t0);
8280 }
8281 goto not_likely;
8282 case OPC_BC1TANY4:
8283 {
8284 TCGv_i32 t1 = tcg_temp_new_i32();
8285 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8286 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
8287 tcg_gen_or_i32(t0, t0, t1);
8288 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
8289 tcg_gen_or_i32(t0, t0, t1);
8290 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
8291 tcg_gen_or_i32(t0, t0, t1);
8292 tcg_temp_free_i32(t1);
8293 tcg_gen_andi_i32(t0, t0, 1);
8294 tcg_gen_extu_i32_tl(bcond, t0);
8295 }
8296 not_likely:
8297 ctx->hflags |= MIPS_HFLAG_BC;
8298 break;
8299 default:
8300 MIPS_INVAL("cp1 cond branch");
8301 generate_exception_end(ctx, EXCP_RI);
8302 goto out;
8303 }
8304 ctx->btarget = btarget;
8305 ctx->hflags |= MIPS_HFLAG_BDS32;
8306 out:
8307 tcg_temp_free_i32(t0);
8308 }
8309
8310 /* R6 CP1 Branches */
8311 static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
8312 int32_t ft, int32_t offset,
8313 int delayslot_size)
8314 {
8315 target_ulong btarget;
8316 TCGv_i64 t0 = tcg_temp_new_i64();
8317
8318 if (ctx->hflags & MIPS_HFLAG_BMASK) {
8319 #ifdef MIPS_DEBUG_DISAS
8320 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
8321 "\n", ctx->pc);
8322 #endif
8323 generate_exception_end(ctx, EXCP_RI);
8324 goto out;
8325 }
8326
8327 gen_load_fpr64(ctx, t0, ft);
8328 tcg_gen_andi_i64(t0, t0, 1);
8329
8330 btarget = addr_add(ctx, ctx->pc + 4, offset);
8331
8332 switch (op) {
8333 case OPC_BC1EQZ:
8334 tcg_gen_xori_i64(t0, t0, 1);
8335 ctx->hflags |= MIPS_HFLAG_BC;
8336 break;
8337 case OPC_BC1NEZ:
8338 /* t0 already set */
8339 ctx->hflags |= MIPS_HFLAG_BC;
8340 break;
8341 default:
8342 MIPS_INVAL("cp1 cond branch");
8343 generate_exception_end(ctx, EXCP_RI);
8344 goto out;
8345 }
8346
8347 tcg_gen_trunc_i64_tl(bcond, t0);
8348
8349 ctx->btarget = btarget;
8350
8351 switch (delayslot_size) {
8352 case 2:
8353 ctx->hflags |= MIPS_HFLAG_BDS16;
8354 break;
8355 case 4:
8356 ctx->hflags |= MIPS_HFLAG_BDS32;
8357 break;
8358 }
8359
8360 out:
8361 tcg_temp_free_i64(t0);
8362 }
8363
8364 /* Coprocessor 1 (FPU) */
8365
8366 #define FOP(func, fmt) (((fmt) << 21) | (func))
8367
8368 enum fopcode {
8369 OPC_ADD_S = FOP(0, FMT_S),
8370 OPC_SUB_S = FOP(1, FMT_S),
8371 OPC_MUL_S = FOP(2, FMT_S),
8372 OPC_DIV_S = FOP(3, FMT_S),
8373 OPC_SQRT_S = FOP(4, FMT_S),
8374 OPC_ABS_S = FOP(5, FMT_S),
8375 OPC_MOV_S = FOP(6, FMT_S),
8376 OPC_NEG_S = FOP(7, FMT_S),
8377 OPC_ROUND_L_S = FOP(8, FMT_S),
8378 OPC_TRUNC_L_S = FOP(9, FMT_S),
8379 OPC_CEIL_L_S = FOP(10, FMT_S),
8380 OPC_FLOOR_L_S = FOP(11, FMT_S),
8381 OPC_ROUND_W_S = FOP(12, FMT_S),
8382 OPC_TRUNC_W_S = FOP(13, FMT_S),
8383 OPC_CEIL_W_S = FOP(14, FMT_S),
8384 OPC_FLOOR_W_S = FOP(15, FMT_S),
8385 OPC_SEL_S = FOP(16, FMT_S),
8386 OPC_MOVCF_S = FOP(17, FMT_S),
8387 OPC_MOVZ_S = FOP(18, FMT_S),
8388 OPC_MOVN_S = FOP(19, FMT_S),
8389 OPC_SELEQZ_S = FOP(20, FMT_S),
8390 OPC_RECIP_S = FOP(21, FMT_S),
8391 OPC_RSQRT_S = FOP(22, FMT_S),
8392 OPC_SELNEZ_S = FOP(23, FMT_S),
8393 OPC_MADDF_S = FOP(24, FMT_S),
8394 OPC_MSUBF_S = FOP(25, FMT_S),
8395 OPC_RINT_S = FOP(26, FMT_S),
8396 OPC_CLASS_S = FOP(27, FMT_S),
8397 OPC_MIN_S = FOP(28, FMT_S),
8398 OPC_RECIP2_S = FOP(28, FMT_S),
8399 OPC_MINA_S = FOP(29, FMT_S),
8400 OPC_RECIP1_S = FOP(29, FMT_S),
8401 OPC_MAX_S = FOP(30, FMT_S),
8402 OPC_RSQRT1_S = FOP(30, FMT_S),
8403 OPC_MAXA_S = FOP(31, FMT_S),
8404 OPC_RSQRT2_S = FOP(31, FMT_S),
8405 OPC_CVT_D_S = FOP(33, FMT_S),
8406 OPC_CVT_W_S = FOP(36, FMT_S),
8407 OPC_CVT_L_S = FOP(37, FMT_S),
8408 OPC_CVT_PS_S = FOP(38, FMT_S),
8409 OPC_CMP_F_S = FOP (48, FMT_S),
8410 OPC_CMP_UN_S = FOP (49, FMT_S),
8411 OPC_CMP_EQ_S = FOP (50, FMT_S),
8412 OPC_CMP_UEQ_S = FOP (51, FMT_S),
8413 OPC_CMP_OLT_S = FOP (52, FMT_S),
8414 OPC_CMP_ULT_S = FOP (53, FMT_S),
8415 OPC_CMP_OLE_S = FOP (54, FMT_S),
8416 OPC_CMP_ULE_S = FOP (55, FMT_S),
8417 OPC_CMP_SF_S = FOP (56, FMT_S),
8418 OPC_CMP_NGLE_S = FOP (57, FMT_S),
8419 OPC_CMP_SEQ_S = FOP (58, FMT_S),
8420 OPC_CMP_NGL_S = FOP (59, FMT_S),
8421 OPC_CMP_LT_S = FOP (60, FMT_S),
8422 OPC_CMP_NGE_S = FOP (61, FMT_S),
8423 OPC_CMP_LE_S = FOP (62, FMT_S),
8424 OPC_CMP_NGT_S = FOP (63, FMT_S),
8425
8426 OPC_ADD_D = FOP(0, FMT_D),
8427 OPC_SUB_D = FOP(1, FMT_D),
8428 OPC_MUL_D = FOP(2, FMT_D),
8429 OPC_DIV_D = FOP(3, FMT_D),
8430 OPC_SQRT_D = FOP(4, FMT_D),
8431 OPC_ABS_D = FOP(5, FMT_D),
8432 OPC_MOV_D = FOP(6, FMT_D),
8433 OPC_NEG_D = FOP(7, FMT_D),
8434 OPC_ROUND_L_D = FOP(8, FMT_D),
8435 OPC_TRUNC_L_D = FOP(9, FMT_D),
8436 OPC_CEIL_L_D = FOP(10, FMT_D),
8437 OPC_FLOOR_L_D = FOP(11, FMT_D),
8438 OPC_ROUND_W_D = FOP(12, FMT_D),
8439 OPC_TRUNC_W_D = FOP(13, FMT_D),
8440 OPC_CEIL_W_D = FOP(14, FMT_D),
8441 OPC_FLOOR_W_D = FOP(15, FMT_D),
8442 OPC_SEL_D = FOP(16, FMT_D),
8443 OPC_MOVCF_D = FOP(17, FMT_D),
8444 OPC_MOVZ_D = FOP(18, FMT_D),
8445 OPC_MOVN_D = FOP(19, FMT_D),
8446 OPC_SELEQZ_D = FOP(20, FMT_D),
8447 OPC_RECIP_D = FOP(21, FMT_D),
8448 OPC_RSQRT_D = FOP(22, FMT_D),
8449 OPC_SELNEZ_D = FOP(23, FMT_D),
8450 OPC_MADDF_D = FOP(24, FMT_D),
8451 OPC_MSUBF_D = FOP(25, FMT_D),
8452 OPC_RINT_D = FOP(26, FMT_D),
8453 OPC_CLASS_D = FOP(27, FMT_D),
8454 OPC_MIN_D = FOP(28, FMT_D),
8455 OPC_RECIP2_D = FOP(28, FMT_D),
8456 OPC_MINA_D = FOP(29, FMT_D),
8457 OPC_RECIP1_D = FOP(29, FMT_D),
8458 OPC_MAX_D = FOP(30, FMT_D),
8459 OPC_RSQRT1_D = FOP(30, FMT_D),
8460 OPC_MAXA_D = FOP(31, FMT_D),
8461 OPC_RSQRT2_D = FOP(31, FMT_D),
8462 OPC_CVT_S_D = FOP(32, FMT_D),
8463 OPC_CVT_W_D = FOP(36, FMT_D),
8464 OPC_CVT_L_D = FOP(37, FMT_D),
8465 OPC_CMP_F_D = FOP (48, FMT_D),
8466 OPC_CMP_UN_D = FOP (49, FMT_D),
8467 OPC_CMP_EQ_D = FOP (50, FMT_D),
8468 OPC_CMP_UEQ_D = FOP (51, FMT_D),
8469 OPC_CMP_OLT_D = FOP (52, FMT_D),
8470 OPC_CMP_ULT_D = FOP (53, FMT_D),
8471 OPC_CMP_OLE_D = FOP (54, FMT_D),
8472 OPC_CMP_ULE_D = FOP (55, FMT_D),
8473 OPC_CMP_SF_D = FOP (56, FMT_D),
8474 OPC_CMP_NGLE_D = FOP (57, FMT_D),
8475 OPC_CMP_SEQ_D = FOP (58, FMT_D),
8476 OPC_CMP_NGL_D = FOP (59, FMT_D),
8477 OPC_CMP_LT_D = FOP (60, FMT_D),
8478 OPC_CMP_NGE_D = FOP (61, FMT_D),
8479 OPC_CMP_LE_D = FOP (62, FMT_D),
8480 OPC_CMP_NGT_D = FOP (63, FMT_D),
8481
8482 OPC_CVT_S_W = FOP(32, FMT_W),
8483 OPC_CVT_D_W = FOP(33, FMT_W),
8484 OPC_CVT_S_L = FOP(32, FMT_L),
8485 OPC_CVT_D_L = FOP(33, FMT_L),
8486 OPC_CVT_PS_PW = FOP(38, FMT_W),
8487
8488 OPC_ADD_PS = FOP(0, FMT_PS),
8489 OPC_SUB_PS = FOP(1, FMT_PS),
8490 OPC_MUL_PS = FOP(2, FMT_PS),
8491 OPC_DIV_PS = FOP(3, FMT_PS),
8492 OPC_ABS_PS = FOP(5, FMT_PS),
8493 OPC_MOV_PS = FOP(6, FMT_PS),
8494 OPC_NEG_PS = FOP(7, FMT_PS),
8495 OPC_MOVCF_PS = FOP(17, FMT_PS),
8496 OPC_MOVZ_PS = FOP(18, FMT_PS),
8497 OPC_MOVN_PS = FOP(19, FMT_PS),
8498 OPC_ADDR_PS = FOP(24, FMT_PS),
8499 OPC_MULR_PS = FOP(26, FMT_PS),
8500 OPC_RECIP2_PS = FOP(28, FMT_PS),
8501 OPC_RECIP1_PS = FOP(29, FMT_PS),
8502 OPC_RSQRT1_PS = FOP(30, FMT_PS),
8503 OPC_RSQRT2_PS = FOP(31, FMT_PS),
8504
8505 OPC_CVT_S_PU = FOP(32, FMT_PS),
8506 OPC_CVT_PW_PS = FOP(36, FMT_PS),
8507 OPC_CVT_S_PL = FOP(40, FMT_PS),
8508 OPC_PLL_PS = FOP(44, FMT_PS),
8509 OPC_PLU_PS = FOP(45, FMT_PS),
8510 OPC_PUL_PS = FOP(46, FMT_PS),
8511 OPC_PUU_PS = FOP(47, FMT_PS),
8512 OPC_CMP_F_PS = FOP (48, FMT_PS),
8513 OPC_CMP_UN_PS = FOP (49, FMT_PS),
8514 OPC_CMP_EQ_PS = FOP (50, FMT_PS),
8515 OPC_CMP_UEQ_PS = FOP (51, FMT_PS),
8516 OPC_CMP_OLT_PS = FOP (52, FMT_PS),
8517 OPC_CMP_ULT_PS = FOP (53, FMT_PS),
8518 OPC_CMP_OLE_PS = FOP (54, FMT_PS),
8519 OPC_CMP_ULE_PS = FOP (55, FMT_PS),
8520 OPC_CMP_SF_PS = FOP (56, FMT_PS),
8521 OPC_CMP_NGLE_PS = FOP (57, FMT_PS),
8522 OPC_CMP_SEQ_PS = FOP (58, FMT_PS),
8523 OPC_CMP_NGL_PS = FOP (59, FMT_PS),
8524 OPC_CMP_LT_PS = FOP (60, FMT_PS),
8525 OPC_CMP_NGE_PS = FOP (61, FMT_PS),
8526 OPC_CMP_LE_PS = FOP (62, FMT_PS),
8527 OPC_CMP_NGT_PS = FOP (63, FMT_PS),
8528 };
8529
8530 enum r6_f_cmp_op {
8531 R6_OPC_CMP_AF_S = FOP(0, FMT_W),
8532 R6_OPC_CMP_UN_S = FOP(1, FMT_W),
8533 R6_OPC_CMP_EQ_S = FOP(2, FMT_W),
8534 R6_OPC_CMP_UEQ_S = FOP(3, FMT_W),
8535 R6_OPC_CMP_LT_S = FOP(4, FMT_W),
8536 R6_OPC_CMP_ULT_S = FOP(5, FMT_W),
8537 R6_OPC_CMP_LE_S = FOP(6, FMT_W),
8538 R6_OPC_CMP_ULE_S = FOP(7, FMT_W),
8539 R6_OPC_CMP_SAF_S = FOP(8, FMT_W),
8540 R6_OPC_CMP_SUN_S = FOP(9, FMT_W),
8541 R6_OPC_CMP_SEQ_S = FOP(10, FMT_W),
8542 R6_OPC_CMP_SEUQ_S = FOP(11, FMT_W),
8543 R6_OPC_CMP_SLT_S = FOP(12, FMT_W),
8544 R6_OPC_CMP_SULT_S = FOP(13, FMT_W),
8545 R6_OPC_CMP_SLE_S = FOP(14, FMT_W),
8546 R6_OPC_CMP_SULE_S = FOP(15, FMT_W),
8547 R6_OPC_CMP_OR_S = FOP(17, FMT_W),
8548 R6_OPC_CMP_UNE_S = FOP(18, FMT_W),
8549 R6_OPC_CMP_NE_S = FOP(19, FMT_W),
8550 R6_OPC_CMP_SOR_S = FOP(25, FMT_W),
8551 R6_OPC_CMP_SUNE_S = FOP(26, FMT_W),
8552 R6_OPC_CMP_SNE_S = FOP(27, FMT_W),
8553
8554 R6_OPC_CMP_AF_D = FOP(0, FMT_L),
8555 R6_OPC_CMP_UN_D = FOP(1, FMT_L),
8556 R6_OPC_CMP_EQ_D = FOP(2, FMT_L),
8557 R6_OPC_CMP_UEQ_D = FOP(3, FMT_L),
8558 R6_OPC_CMP_LT_D = FOP(4, FMT_L),
8559 R6_OPC_CMP_ULT_D = FOP(5, FMT_L),
8560 R6_OPC_CMP_LE_D = FOP(6, FMT_L),
8561 R6_OPC_CMP_ULE_D = FOP(7, FMT_L),
8562 R6_OPC_CMP_SAF_D = FOP(8, FMT_L),
8563 R6_OPC_CMP_SUN_D = FOP(9, FMT_L),
8564 R6_OPC_CMP_SEQ_D = FOP(10, FMT_L),
8565 R6_OPC_CMP_SEUQ_D = FOP(11, FMT_L),
8566 R6_OPC_CMP_SLT_D = FOP(12, FMT_L),
8567 R6_OPC_CMP_SULT_D = FOP(13, FMT_L),
8568 R6_OPC_CMP_SLE_D = FOP(14, FMT_L),
8569 R6_OPC_CMP_SULE_D = FOP(15, FMT_L),
8570 R6_OPC_CMP_OR_D = FOP(17, FMT_L),
8571 R6_OPC_CMP_UNE_D = FOP(18, FMT_L),
8572 R6_OPC_CMP_NE_D = FOP(19, FMT_L),
8573 R6_OPC_CMP_SOR_D = FOP(25, FMT_L),
8574 R6_OPC_CMP_SUNE_D = FOP(26, FMT_L),
8575 R6_OPC_CMP_SNE_D = FOP(27, FMT_L),
8576 };
8577 static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
8578 {
8579 TCGv t0 = tcg_temp_new();
8580
8581 switch (opc) {
8582 case OPC_MFC1:
8583 {
8584 TCGv_i32 fp0 = tcg_temp_new_i32();
8585
8586 gen_load_fpr32(ctx, fp0, fs);
8587 tcg_gen_ext_i32_tl(t0, fp0);
8588 tcg_temp_free_i32(fp0);
8589 }
8590 gen_store_gpr(t0, rt);
8591 break;
8592 case OPC_MTC1:
8593 gen_load_gpr(t0, rt);
8594 {
8595 TCGv_i32 fp0 = tcg_temp_new_i32();
8596
8597 tcg_gen_trunc_tl_i32(fp0, t0);
8598 gen_store_fpr32(ctx, fp0, fs);
8599 tcg_temp_free_i32(fp0);
8600 }
8601 break;
8602 case OPC_CFC1:
8603 gen_helper_1e0i(cfc1, t0, fs);
8604 gen_store_gpr(t0, rt);
8605 break;
8606 case OPC_CTC1:
8607 gen_load_gpr(t0, rt);
8608 save_cpu_state(ctx, 0);
8609 {
8610 TCGv_i32 fs_tmp = tcg_const_i32(fs);
8611
8612 gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
8613 tcg_temp_free_i32(fs_tmp);
8614 }
8615 /* Stop translation as we may have changed hflags */
8616 ctx->bstate = BS_STOP;
8617 break;
8618 #if defined(TARGET_MIPS64)
8619 case OPC_DMFC1:
8620 gen_load_fpr64(ctx, t0, fs);
8621 gen_store_gpr(t0, rt);
8622 break;
8623 case OPC_DMTC1:
8624 gen_load_gpr(t0, rt);
8625 gen_store_fpr64(ctx, t0, fs);
8626 break;
8627 #endif
8628 case OPC_MFHC1:
8629 {
8630 TCGv_i32 fp0 = tcg_temp_new_i32();
8631
8632 gen_load_fpr32h(ctx, fp0, fs);
8633 tcg_gen_ext_i32_tl(t0, fp0);
8634 tcg_temp_free_i32(fp0);
8635 }
8636 gen_store_gpr(t0, rt);
8637 break;
8638 case OPC_MTHC1:
8639 gen_load_gpr(t0, rt);
8640 {
8641 TCGv_i32 fp0 = tcg_temp_new_i32();
8642
8643 tcg_gen_trunc_tl_i32(fp0, t0);
8644 gen_store_fpr32h(ctx, fp0, fs);
8645 tcg_temp_free_i32(fp0);
8646 }
8647 break;
8648 default:
8649 MIPS_INVAL("cp1 move");
8650 generate_exception_end(ctx, EXCP_RI);
8651 goto out;
8652 }
8653
8654 out:
8655 tcg_temp_free(t0);
8656 }
8657
8658 static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
8659 {
8660 TCGLabel *l1;
8661 TCGCond cond;
8662 TCGv_i32 t0;
8663
8664 if (rd == 0) {
8665 /* Treat as NOP. */
8666 return;
8667 }
8668
8669 if (tf)
8670 cond = TCG_COND_EQ;
8671 else
8672 cond = TCG_COND_NE;
8673
8674 l1 = gen_new_label();
8675 t0 = tcg_temp_new_i32();
8676 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
8677 tcg_gen_brcondi_i32(cond, t0, 0, l1);
8678 tcg_temp_free_i32(t0);
8679 if (rs == 0) {
8680 tcg_gen_movi_tl(cpu_gpr[rd], 0);
8681 } else {
8682 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
8683 }
8684 gen_set_label(l1);
8685 }
8686
8687 static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,
8688 int tf)
8689 {
8690 int cond;
8691 TCGv_i32 t0 = tcg_temp_new_i32();
8692 TCGLabel *l1 = gen_new_label();
8693
8694 if (tf)
8695 cond = TCG_COND_EQ;
8696 else
8697 cond = TCG_COND_NE;
8698
8699 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
8700 tcg_gen_brcondi_i32(cond, t0, 0, l1);
8701 gen_load_fpr32(ctx, t0, fs);
8702 gen_store_fpr32(ctx, t0, fd);
8703 gen_set_label(l1);
8704 tcg_temp_free_i32(t0);
8705 }
8706
8707 static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf)
8708 {
8709 int cond;
8710 TCGv_i32 t0 = tcg_temp_new_i32();
8711 TCGv_i64 fp0;
8712 TCGLabel *l1 = gen_new_label();
8713
8714 if (tf)
8715 cond = TCG_COND_EQ;
8716 else
8717 cond = TCG_COND_NE;
8718
8719 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
8720 tcg_gen_brcondi_i32(cond, t0, 0, l1);
8721 tcg_temp_free_i32(t0);
8722 fp0 = tcg_temp_new_i64();
8723 gen_load_fpr64(ctx, fp0, fs);
8724 gen_store_fpr64(ctx, fp0, fd);
8725 tcg_temp_free_i64(fp0);
8726 gen_set_label(l1);
8727 }
8728
8729 static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
8730 int cc, int tf)
8731 {
8732 int cond;
8733 TCGv_i32 t0 = tcg_temp_new_i32();
8734 TCGLabel *l1 = gen_new_label();
8735 TCGLabel *l2 = gen_new_label();
8736
8737 if (tf)
8738 cond = TCG_COND_EQ;
8739 else
8740 cond = TCG_COND_NE;
8741
8742 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
8743 tcg_gen_brcondi_i32(cond, t0, 0, l1);
8744 gen_load_fpr32(ctx, t0, fs);
8745 gen_store_fpr32(ctx, t0, fd);
8746 gen_set_label(l1);
8747
8748 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc+1));
8749 tcg_gen_brcondi_i32(cond, t0, 0, l2);
8750 gen_load_fpr32h(ctx, t0, fs);
8751 gen_store_fpr32h(ctx, t0, fd);
8752 tcg_temp_free_i32(t0);
8753 gen_set_label(l2);
8754 }
8755
8756 static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
8757 int fs)
8758 {
8759 TCGv_i32 t1 = tcg_const_i32(0);
8760 TCGv_i32 fp0 = tcg_temp_new_i32();
8761 TCGv_i32 fp1 = tcg_temp_new_i32();
8762 TCGv_i32 fp2 = tcg_temp_new_i32();
8763 gen_load_fpr32(ctx, fp0, fd);
8764 gen_load_fpr32(ctx, fp1, ft);
8765 gen_load_fpr32(ctx, fp2, fs);
8766
8767 switch (op1) {
8768 case OPC_SEL_S:
8769 tcg_gen_andi_i32(fp0, fp0, 1);
8770 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp0, t1, fp1, fp2);
8771 break;
8772 case OPC_SELEQZ_S:
8773 tcg_gen_andi_i32(fp1, fp1, 1);
8774 tcg_gen_movcond_i32(TCG_COND_EQ, fp0, fp1, t1, fp2, t1);
8775 break;
8776 case OPC_SELNEZ_S:
8777 tcg_gen_andi_i32(fp1, fp1, 1);
8778 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp1, t1, fp2, t1);
8779 break;
8780 default:
8781 MIPS_INVAL("gen_sel_s");
8782 generate_exception_end(ctx, EXCP_RI);
8783 break;
8784 }
8785
8786 gen_store_fpr32(ctx, fp0, fd);
8787 tcg_temp_free_i32(fp2);
8788 tcg_temp_free_i32(fp1);
8789 tcg_temp_free_i32(fp0);
8790 tcg_temp_free_i32(t1);
8791 }
8792
8793 static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
8794 int fs)
8795 {
8796 TCGv_i64 t1 = tcg_const_i64(0);
8797 TCGv_i64 fp0 = tcg_temp_new_i64();
8798 TCGv_i64 fp1 = tcg_temp_new_i64();
8799 TCGv_i64 fp2 = tcg_temp_new_i64();
8800 gen_load_fpr64(ctx, fp0, fd);
8801 gen_load_fpr64(ctx, fp1, ft);
8802 gen_load_fpr64(ctx, fp2, fs);
8803
8804 switch (op1) {
8805 case OPC_SEL_D:
8806 tcg_gen_andi_i64(fp0, fp0, 1);
8807 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp0, t1, fp1, fp2);
8808 break;
8809 case OPC_SELEQZ_D:
8810 tcg_gen_andi_i64(fp1, fp1, 1);
8811 tcg_gen_movcond_i64(TCG_COND_EQ, fp0, fp1, t1, fp2, t1);
8812 break;
8813 case OPC_SELNEZ_D:
8814 tcg_gen_andi_i64(fp1, fp1, 1);
8815 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp1, t1, fp2, t1);
8816 break;
8817 default:
8818 MIPS_INVAL("gen_sel_d");
8819 generate_exception_end(ctx, EXCP_RI);
8820 break;
8821 }
8822
8823 gen_store_fpr64(ctx, fp0, fd);
8824 tcg_temp_free_i64(fp2);
8825 tcg_temp_free_i64(fp1);
8826 tcg_temp_free_i64(fp0);
8827 tcg_temp_free_i64(t1);
8828 }
8829
8830 static void gen_farith (DisasContext *ctx, enum fopcode op1,
8831 int ft, int fs, int fd, int cc)
8832 {
8833 uint32_t func = ctx->opcode & 0x3f;
8834 switch (op1) {
8835 case OPC_ADD_S:
8836 {
8837 TCGv_i32 fp0 = tcg_temp_new_i32();
8838 TCGv_i32 fp1 = tcg_temp_new_i32();
8839
8840 gen_load_fpr32(ctx, fp0, fs);
8841 gen_load_fpr32(ctx, fp1, ft);
8842 gen_helper_float_add_s(fp0, cpu_env, fp0, fp1);
8843 tcg_temp_free_i32(fp1);
8844 gen_store_fpr32(ctx, fp0, fd);
8845 tcg_temp_free_i32(fp0);
8846 }
8847 break;
8848 case OPC_SUB_S:
8849 {
8850 TCGv_i32 fp0 = tcg_temp_new_i32();
8851 TCGv_i32 fp1 = tcg_temp_new_i32();
8852
8853 gen_load_fpr32(ctx, fp0, fs);
8854 gen_load_fpr32(ctx, fp1, ft);
8855 gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1);
8856 tcg_temp_free_i32(fp1);
8857 gen_store_fpr32(ctx, fp0, fd);
8858 tcg_temp_free_i32(fp0);
8859 }
8860 break;
8861 case OPC_MUL_S:
8862 {
8863 TCGv_i32 fp0 = tcg_temp_new_i32();
8864 TCGv_i32 fp1 = tcg_temp_new_i32();
8865
8866 gen_load_fpr32(ctx, fp0, fs);
8867 gen_load_fpr32(ctx, fp1, ft);
8868 gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1);
8869 tcg_temp_free_i32(fp1);
8870 gen_store_fpr32(ctx, fp0, fd);
8871 tcg_temp_free_i32(fp0);
8872 }
8873 break;
8874 case OPC_DIV_S:
8875 {
8876 TCGv_i32 fp0 = tcg_temp_new_i32();
8877 TCGv_i32 fp1 = tcg_temp_new_i32();
8878
8879 gen_load_fpr32(ctx, fp0, fs);
8880 gen_load_fpr32(ctx, fp1, ft);
8881 gen_helper_float_div_s(fp0, cpu_env, fp0, fp1);
8882 tcg_temp_free_i32(fp1);
8883 gen_store_fpr32(ctx, fp0, fd);
8884 tcg_temp_free_i32(fp0);
8885 }
8886 break;
8887 case OPC_SQRT_S:
8888 {
8889 TCGv_i32 fp0 = tcg_temp_new_i32();
8890
8891 gen_load_fpr32(ctx, fp0, fs);
8892 gen_helper_float_sqrt_s(fp0, cpu_env, fp0);
8893 gen_store_fpr32(ctx, fp0, fd);
8894 tcg_temp_free_i32(fp0);
8895 }
8896 break;
8897 case OPC_ABS_S:
8898 {
8899 TCGv_i32 fp0 = tcg_temp_new_i32();
8900
8901 gen_load_fpr32(ctx, fp0, fs);
8902 if (ctx->abs2008) {
8903 tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL);
8904 } else {
8905 gen_helper_float_abs_s(fp0, fp0);
8906 }
8907 gen_store_fpr32(ctx, fp0, fd);
8908 tcg_temp_free_i32(fp0);
8909 }
8910 break;
8911 case OPC_MOV_S:
8912 {
8913 TCGv_i32 fp0 = tcg_temp_new_i32();
8914
8915 gen_load_fpr32(ctx, fp0, fs);
8916 gen_store_fpr32(ctx, fp0, fd);
8917 tcg_temp_free_i32(fp0);
8918 }
8919 break;
8920 case OPC_NEG_S:
8921 {
8922 TCGv_i32 fp0 = tcg_temp_new_i32();
8923
8924 gen_load_fpr32(ctx, fp0, fs);
8925 if (ctx->abs2008) {
8926 tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
8927 } else {
8928 gen_helper_float_chs_s(fp0, fp0);
8929 }
8930 gen_store_fpr32(ctx, fp0, fd);
8931 tcg_temp_free_i32(fp0);
8932 }
8933 break;
8934 case OPC_ROUND_L_S:
8935 check_cp1_64bitmode(ctx);
8936 {
8937 TCGv_i32 fp32 = tcg_temp_new_i32();
8938 TCGv_i64 fp64 = tcg_temp_new_i64();
8939
8940 gen_load_fpr32(ctx, fp32, fs);
8941 if (ctx->nan2008) {
8942 gen_helper_float_round_2008_l_s(fp64, cpu_env, fp32);
8943 } else {
8944 gen_helper_float_round_l_s(fp64, cpu_env, fp32);
8945 }
8946 tcg_temp_free_i32(fp32);
8947 gen_store_fpr64(ctx, fp64, fd);
8948 tcg_temp_free_i64(fp64);
8949 }
8950 break;
8951 case OPC_TRUNC_L_S:
8952 check_cp1_64bitmode(ctx);
8953 {
8954 TCGv_i32 fp32 = tcg_temp_new_i32();
8955 TCGv_i64 fp64 = tcg_temp_new_i64();
8956
8957 gen_load_fpr32(ctx, fp32, fs);
8958 if (ctx->nan2008) {
8959 gen_helper_float_trunc_2008_l_s(fp64, cpu_env, fp32);
8960 } else {
8961 gen_helper_float_trunc_l_s(fp64, cpu_env, fp32);
8962 }
8963 tcg_temp_free_i32(fp32);
8964 gen_store_fpr64(ctx, fp64, fd);
8965 tcg_temp_free_i64(fp64);
8966 }
8967 break;
8968 case OPC_CEIL_L_S:
8969 check_cp1_64bitmode(ctx);
8970 {
8971 TCGv_i32 fp32 = tcg_temp_new_i32();
8972 TCGv_i64 fp64 = tcg_temp_new_i64();
8973
8974 gen_load_fpr32(ctx, fp32, fs);
8975 if (ctx->nan2008) {
8976 gen_helper_float_ceil_2008_l_s(fp64, cpu_env, fp32);
8977 } else {
8978 gen_helper_float_ceil_l_s(fp64, cpu_env, fp32);
8979 }
8980 tcg_temp_free_i32(fp32);
8981 gen_store_fpr64(ctx, fp64, fd);
8982 tcg_temp_free_i64(fp64);
8983 }
8984 break;
8985 case OPC_FLOOR_L_S:
8986 check_cp1_64bitmode(ctx);
8987 {
8988 TCGv_i32 fp32 = tcg_temp_new_i32();
8989 TCGv_i64 fp64 = tcg_temp_new_i64();
8990
8991 gen_load_fpr32(ctx, fp32, fs);
8992 if (ctx->nan2008) {
8993 gen_helper_float_floor_2008_l_s(fp64, cpu_env, fp32);
8994 } else {
8995 gen_helper_float_floor_l_s(fp64, cpu_env, fp32);
8996 }
8997 tcg_temp_free_i32(fp32);
8998 gen_store_fpr64(ctx, fp64, fd);
8999 tcg_temp_free_i64(fp64);
9000 }
9001 break;
9002 case OPC_ROUND_W_S:
9003 {
9004 TCGv_i32 fp0 = tcg_temp_new_i32();
9005
9006 gen_load_fpr32(ctx, fp0, fs);
9007 if (ctx->nan2008) {
9008 gen_helper_float_round_2008_w_s(fp0, cpu_env, fp0);
9009 } else {
9010 gen_helper_float_round_w_s(fp0, cpu_env, fp0);
9011 }
9012 gen_store_fpr32(ctx, fp0, fd);
9013 tcg_temp_free_i32(fp0);
9014 }
9015 break;
9016 case OPC_TRUNC_W_S:
9017 {
9018 TCGv_i32 fp0 = tcg_temp_new_i32();
9019
9020 gen_load_fpr32(ctx, fp0, fs);
9021 if (ctx->nan2008) {
9022 gen_helper_float_trunc_2008_w_s(fp0, cpu_env, fp0);
9023 } else {
9024 gen_helper_float_trunc_w_s(fp0, cpu_env, fp0);
9025 }
9026 gen_store_fpr32(ctx, fp0, fd);
9027 tcg_temp_free_i32(fp0);
9028 }
9029 break;
9030 case OPC_CEIL_W_S:
9031 {
9032 TCGv_i32 fp0 = tcg_temp_new_i32();
9033
9034 gen_load_fpr32(ctx, fp0, fs);
9035 if (ctx->nan2008) {
9036 gen_helper_float_ceil_2008_w_s(fp0, cpu_env, fp0);
9037 } else {
9038 gen_helper_float_ceil_w_s(fp0, cpu_env, fp0);
9039 }
9040 gen_store_fpr32(ctx, fp0, fd);
9041 tcg_temp_free_i32(fp0);
9042 }
9043 break;
9044 case OPC_FLOOR_W_S:
9045 {
9046 TCGv_i32 fp0 = tcg_temp_new_i32();
9047
9048 gen_load_fpr32(ctx, fp0, fs);
9049 if (ctx->nan2008) {
9050 gen_helper_float_floor_2008_w_s(fp0, cpu_env, fp0);
9051 } else {
9052 gen_helper_float_floor_w_s(fp0, cpu_env, fp0);
9053 }
9054 gen_store_fpr32(ctx, fp0, fd);
9055 tcg_temp_free_i32(fp0);
9056 }
9057 break;
9058 case OPC_SEL_S:
9059 check_insn(ctx, ISA_MIPS32R6);
9060 gen_sel_s(ctx, op1, fd, ft, fs);
9061 break;
9062 case OPC_SELEQZ_S:
9063 check_insn(ctx, ISA_MIPS32R6);
9064 gen_sel_s(ctx, op1, fd, ft, fs);
9065 break;
9066 case OPC_SELNEZ_S:
9067 check_insn(ctx, ISA_MIPS32R6);
9068 gen_sel_s(ctx, op1, fd, ft, fs);
9069 break;
9070 case OPC_MOVCF_S:
9071 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9072 gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
9073 break;
9074 case OPC_MOVZ_S:
9075 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9076 {
9077 TCGLabel *l1 = gen_new_label();
9078 TCGv_i32 fp0;
9079
9080 if (ft != 0) {
9081 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
9082 }
9083 fp0 = tcg_temp_new_i32();
9084 gen_load_fpr32(ctx, fp0, fs);
9085 gen_store_fpr32(ctx, fp0, fd);
9086 tcg_temp_free_i32(fp0);
9087 gen_set_label(l1);
9088 }
9089 break;
9090 case OPC_MOVN_S:
9091 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9092 {
9093 TCGLabel *l1 = gen_new_label();
9094 TCGv_i32 fp0;
9095
9096 if (ft != 0) {
9097 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
9098 fp0 = tcg_temp_new_i32();
9099 gen_load_fpr32(ctx, fp0, fs);
9100 gen_store_fpr32(ctx, fp0, fd);
9101 tcg_temp_free_i32(fp0);
9102 gen_set_label(l1);
9103 }
9104 }
9105 break;
9106 case OPC_RECIP_S:
9107 {
9108 TCGv_i32 fp0 = tcg_temp_new_i32();
9109
9110 gen_load_fpr32(ctx, fp0, fs);
9111 gen_helper_float_recip_s(fp0, cpu_env, fp0);
9112 gen_store_fpr32(ctx, fp0, fd);
9113 tcg_temp_free_i32(fp0);
9114 }
9115 break;
9116 case OPC_RSQRT_S:
9117 {
9118 TCGv_i32 fp0 = tcg_temp_new_i32();
9119
9120 gen_load_fpr32(ctx, fp0, fs);
9121 gen_helper_float_rsqrt_s(fp0, cpu_env, fp0);
9122 gen_store_fpr32(ctx, fp0, fd);
9123 tcg_temp_free_i32(fp0);
9124 }
9125 break;
9126 case OPC_MADDF_S:
9127 check_insn(ctx, ISA_MIPS32R6);
9128 {
9129 TCGv_i32 fp0 = tcg_temp_new_i32();
9130 TCGv_i32 fp1 = tcg_temp_new_i32();
9131 TCGv_i32 fp2 = tcg_temp_new_i32();
9132 gen_load_fpr32(ctx, fp0, fs);
9133 gen_load_fpr32(ctx, fp1, ft);
9134 gen_load_fpr32(ctx, fp2, fd);
9135 gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2);
9136 gen_store_fpr32(ctx, fp2, fd);
9137 tcg_temp_free_i32(fp2);
9138 tcg_temp_free_i32(fp1);
9139 tcg_temp_free_i32(fp0);
9140 }
9141 break;
9142 case OPC_MSUBF_S:
9143 check_insn(ctx, ISA_MIPS32R6);
9144 {
9145 TCGv_i32 fp0 = tcg_temp_new_i32();
9146 TCGv_i32 fp1 = tcg_temp_new_i32();
9147 TCGv_i32 fp2 = tcg_temp_new_i32();
9148 gen_load_fpr32(ctx, fp0, fs);
9149 gen_load_fpr32(ctx, fp1, ft);
9150 gen_load_fpr32(ctx, fp2, fd);
9151 gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2);
9152 gen_store_fpr32(ctx, fp2, fd);
9153 tcg_temp_free_i32(fp2);
9154 tcg_temp_free_i32(fp1);
9155 tcg_temp_free_i32(fp0);
9156 }
9157 break;
9158 case OPC_RINT_S:
9159 check_insn(ctx, ISA_MIPS32R6);
9160 {
9161 TCGv_i32 fp0 = tcg_temp_new_i32();
9162 gen_load_fpr32(ctx, fp0, fs);
9163 gen_helper_float_rint_s(fp0, cpu_env, fp0);
9164 gen_store_fpr32(ctx, fp0, fd);
9165 tcg_temp_free_i32(fp0);
9166 }
9167 break;
9168 case OPC_CLASS_S:
9169 check_insn(ctx, ISA_MIPS32R6);
9170 {
9171 TCGv_i32 fp0 = tcg_temp_new_i32();
9172 gen_load_fpr32(ctx, fp0, fs);
9173 gen_helper_float_class_s(fp0, cpu_env, fp0);
9174 gen_store_fpr32(ctx, fp0, fd);
9175 tcg_temp_free_i32(fp0);
9176 }
9177 break;
9178 case OPC_MIN_S: /* OPC_RECIP2_S */
9179 if (ctx->insn_flags & ISA_MIPS32R6) {
9180 /* OPC_MIN_S */
9181 TCGv_i32 fp0 = tcg_temp_new_i32();
9182 TCGv_i32 fp1 = tcg_temp_new_i32();
9183 TCGv_i32 fp2 = tcg_temp_new_i32();
9184 gen_load_fpr32(ctx, fp0, fs);
9185 gen_load_fpr32(ctx, fp1, ft);
9186 gen_helper_float_min_s(fp2, cpu_env, fp0, fp1);
9187 gen_store_fpr32(ctx, fp2, fd);
9188 tcg_temp_free_i32(fp2);
9189 tcg_temp_free_i32(fp1);
9190 tcg_temp_free_i32(fp0);
9191 } else {
9192 /* OPC_RECIP2_S */
9193 check_cp1_64bitmode(ctx);
9194 {
9195 TCGv_i32 fp0 = tcg_temp_new_i32();
9196 TCGv_i32 fp1 = tcg_temp_new_i32();
9197
9198 gen_load_fpr32(ctx, fp0, fs);
9199 gen_load_fpr32(ctx, fp1, ft);
9200 gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1);
9201 tcg_temp_free_i32(fp1);
9202 gen_store_fpr32(ctx, fp0, fd);
9203 tcg_temp_free_i32(fp0);
9204 }
9205 }
9206 break;
9207 case OPC_MINA_S: /* OPC_RECIP1_S */
9208 if (ctx->insn_flags & ISA_MIPS32R6) {
9209 /* OPC_MINA_S */
9210 TCGv_i32 fp0 = tcg_temp_new_i32();
9211 TCGv_i32 fp1 = tcg_temp_new_i32();
9212 TCGv_i32 fp2 = tcg_temp_new_i32();
9213 gen_load_fpr32(ctx, fp0, fs);
9214 gen_load_fpr32(ctx, fp1, ft);
9215 gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1);
9216 gen_store_fpr32(ctx, fp2, fd);
9217 tcg_temp_free_i32(fp2);
9218 tcg_temp_free_i32(fp1);
9219 tcg_temp_free_i32(fp0);
9220 } else {
9221 /* OPC_RECIP1_S */
9222 check_cp1_64bitmode(ctx);
9223 {
9224 TCGv_i32 fp0 = tcg_temp_new_i32();
9225
9226 gen_load_fpr32(ctx, fp0, fs);
9227 gen_helper_float_recip1_s(fp0, cpu_env, fp0);
9228 gen_store_fpr32(ctx, fp0, fd);
9229 tcg_temp_free_i32(fp0);
9230 }
9231 }
9232 break;
9233 case OPC_MAX_S: /* OPC_RSQRT1_S */
9234 if (ctx->insn_flags & ISA_MIPS32R6) {
9235 /* OPC_MAX_S */
9236 TCGv_i32 fp0 = tcg_temp_new_i32();
9237 TCGv_i32 fp1 = tcg_temp_new_i32();
9238 gen_load_fpr32(ctx, fp0, fs);
9239 gen_load_fpr32(ctx, fp1, ft);
9240 gen_helper_float_max_s(fp1, cpu_env, fp0, fp1);
9241 gen_store_fpr32(ctx, fp1, fd);
9242 tcg_temp_free_i32(fp1);
9243 tcg_temp_free_i32(fp0);
9244 } else {
9245 /* OPC_RSQRT1_S */
9246 check_cp1_64bitmode(ctx);
9247 {
9248 TCGv_i32 fp0 = tcg_temp_new_i32();
9249
9250 gen_load_fpr32(ctx, fp0, fs);
9251 gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0);
9252 gen_store_fpr32(ctx, fp0, fd);
9253 tcg_temp_free_i32(fp0);
9254 }
9255 }
9256 break;
9257 case OPC_MAXA_S: /* OPC_RSQRT2_S */
9258 if (ctx->insn_flags & ISA_MIPS32R6) {
9259 /* OPC_MAXA_S */
9260 TCGv_i32 fp0 = tcg_temp_new_i32();
9261 TCGv_i32 fp1 = tcg_temp_new_i32();
9262 gen_load_fpr32(ctx, fp0, fs);
9263 gen_load_fpr32(ctx, fp1, ft);
9264 gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1);
9265 gen_store_fpr32(ctx, fp1, fd);
9266 tcg_temp_free_i32(fp1);
9267 tcg_temp_free_i32(fp0);
9268 } else {
9269 /* OPC_RSQRT2_S */
9270 check_cp1_64bitmode(ctx);
9271 {
9272 TCGv_i32 fp0 = tcg_temp_new_i32();
9273 TCGv_i32 fp1 = tcg_temp_new_i32();
9274
9275 gen_load_fpr32(ctx, fp0, fs);
9276 gen_load_fpr32(ctx, fp1, ft);
9277 gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1);
9278 tcg_temp_free_i32(fp1);
9279 gen_store_fpr32(ctx, fp0, fd);
9280 tcg_temp_free_i32(fp0);
9281 }
9282 }
9283 break;
9284 case OPC_CVT_D_S:
9285 check_cp1_registers(ctx, fd);
9286 {
9287 TCGv_i32 fp32 = tcg_temp_new_i32();
9288 TCGv_i64 fp64 = tcg_temp_new_i64();
9289
9290 gen_load_fpr32(ctx, fp32, fs);
9291 gen_helper_float_cvtd_s(fp64, cpu_env, fp32);
9292 tcg_temp_free_i32(fp32);
9293 gen_store_fpr64(ctx, fp64, fd);
9294 tcg_temp_free_i64(fp64);
9295 }
9296 break;
9297 case OPC_CVT_W_S:
9298 {
9299 TCGv_i32 fp0 = tcg_temp_new_i32();
9300
9301 gen_load_fpr32(ctx, fp0, fs);
9302 if (ctx->nan2008) {
9303 gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0);
9304 } else {
9305 gen_helper_float_cvt_w_s(fp0, cpu_env, fp0);
9306 }
9307 gen_store_fpr32(ctx, fp0, fd);
9308 tcg_temp_free_i32(fp0);
9309 }
9310 break;
9311 case OPC_CVT_L_S:
9312 check_cp1_64bitmode(ctx);
9313 {
9314 TCGv_i32 fp32 = tcg_temp_new_i32();
9315 TCGv_i64 fp64 = tcg_temp_new_i64();
9316
9317 gen_load_fpr32(ctx, fp32, fs);
9318 if (ctx->nan2008) {
9319 gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32);
9320 } else {
9321 gen_helper_float_cvt_l_s(fp64, cpu_env, fp32);
9322 }
9323 tcg_temp_free_i32(fp32);
9324 gen_store_fpr64(ctx, fp64, fd);
9325 tcg_temp_free_i64(fp64);
9326 }
9327 break;
9328 case OPC_CVT_PS_S:
9329 check_ps(ctx);
9330 {
9331 TCGv_i64 fp64 = tcg_temp_new_i64();
9332 TCGv_i32 fp32_0 = tcg_temp_new_i32();
9333 TCGv_i32 fp32_1 = tcg_temp_new_i32();
9334
9335 gen_load_fpr32(ctx, fp32_0, fs);
9336 gen_load_fpr32(ctx, fp32_1, ft);
9337 tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0);
9338 tcg_temp_free_i32(fp32_1);
9339 tcg_temp_free_i32(fp32_0);
9340 gen_store_fpr64(ctx, fp64, fd);
9341 tcg_temp_free_i64(fp64);
9342 }
9343 break;
9344 case OPC_CMP_F_S:
9345 case OPC_CMP_UN_S:
9346 case OPC_CMP_EQ_S:
9347 case OPC_CMP_UEQ_S:
9348 case OPC_CMP_OLT_S:
9349 case OPC_CMP_ULT_S:
9350 case OPC_CMP_OLE_S:
9351 case OPC_CMP_ULE_S:
9352 case OPC_CMP_SF_S:
9353 case OPC_CMP_NGLE_S:
9354 case OPC_CMP_SEQ_S:
9355 case OPC_CMP_NGL_S:
9356 case OPC_CMP_LT_S:
9357 case OPC_CMP_NGE_S:
9358 case OPC_CMP_LE_S:
9359 case OPC_CMP_NGT_S:
9360 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9361 if (ctx->opcode & (1 << 6)) {
9362 gen_cmpabs_s(ctx, func-48, ft, fs, cc);
9363 } else {
9364 gen_cmp_s(ctx, func-48, ft, fs, cc);
9365 }
9366 break;
9367 case OPC_ADD_D:
9368 check_cp1_registers(ctx, fs | ft | fd);
9369 {
9370 TCGv_i64 fp0 = tcg_temp_new_i64();
9371 TCGv_i64 fp1 = tcg_temp_new_i64();
9372
9373 gen_load_fpr64(ctx, fp0, fs);
9374 gen_load_fpr64(ctx, fp1, ft);
9375 gen_helper_float_add_d(fp0, cpu_env, fp0, fp1);
9376 tcg_temp_free_i64(fp1);
9377 gen_store_fpr64(ctx, fp0, fd);
9378 tcg_temp_free_i64(fp0);
9379 }
9380 break;
9381 case OPC_SUB_D:
9382 check_cp1_registers(ctx, fs | ft | fd);
9383 {
9384 TCGv_i64 fp0 = tcg_temp_new_i64();
9385 TCGv_i64 fp1 = tcg_temp_new_i64();
9386
9387 gen_load_fpr64(ctx, fp0, fs);
9388 gen_load_fpr64(ctx, fp1, ft);
9389 gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1);
9390 tcg_temp_free_i64(fp1);
9391 gen_store_fpr64(ctx, fp0, fd);
9392 tcg_temp_free_i64(fp0);
9393 }
9394 break;
9395 case OPC_MUL_D:
9396 check_cp1_registers(ctx, fs | ft | fd);
9397 {
9398 TCGv_i64 fp0 = tcg_temp_new_i64();
9399 TCGv_i64 fp1 = tcg_temp_new_i64();
9400
9401 gen_load_fpr64(ctx, fp0, fs);
9402 gen_load_fpr64(ctx, fp1, ft);
9403 gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1);
9404 tcg_temp_free_i64(fp1);
9405 gen_store_fpr64(ctx, fp0, fd);
9406 tcg_temp_free_i64(fp0);
9407 }
9408 break;
9409 case OPC_DIV_D:
9410 check_cp1_registers(ctx, fs | ft | fd);
9411 {
9412 TCGv_i64 fp0 = tcg_temp_new_i64();
9413 TCGv_i64 fp1 = tcg_temp_new_i64();
9414
9415 gen_load_fpr64(ctx, fp0, fs);
9416 gen_load_fpr64(ctx, fp1, ft);
9417 gen_helper_float_div_d(fp0, cpu_env, fp0, fp1);
9418 tcg_temp_free_i64(fp1);
9419 gen_store_fpr64(ctx, fp0, fd);
9420 tcg_temp_free_i64(fp0);
9421 }
9422 break;
9423 case OPC_SQRT_D:
9424 check_cp1_registers(ctx, fs | fd);
9425 {
9426 TCGv_i64 fp0 = tcg_temp_new_i64();
9427
9428 gen_load_fpr64(ctx, fp0, fs);
9429 gen_helper_float_sqrt_d(fp0, cpu_env, fp0);
9430 gen_store_fpr64(ctx, fp0, fd);
9431 tcg_temp_free_i64(fp0);
9432 }
9433 break;
9434 case OPC_ABS_D:
9435 check_cp1_registers(ctx, fs | fd);
9436 {
9437 TCGv_i64 fp0 = tcg_temp_new_i64();
9438
9439 gen_load_fpr64(ctx, fp0, fs);
9440 if (ctx->abs2008) {
9441 tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL);
9442 } else {
9443 gen_helper_float_abs_d(fp0, fp0);
9444 }
9445 gen_store_fpr64(ctx, fp0, fd);
9446 tcg_temp_free_i64(fp0);
9447 }
9448 break;
9449 case OPC_MOV_D:
9450 check_cp1_registers(ctx, fs | fd);
9451 {
9452 TCGv_i64 fp0 = tcg_temp_new_i64();
9453
9454 gen_load_fpr64(ctx, fp0, fs);
9455 gen_store_fpr64(ctx, fp0, fd);
9456 tcg_temp_free_i64(fp0);
9457 }
9458 break;
9459 case OPC_NEG_D:
9460 check_cp1_registers(ctx, fs | fd);
9461 {
9462 TCGv_i64 fp0 = tcg_temp_new_i64();
9463
9464 gen_load_fpr64(ctx, fp0, fs);
9465 if (ctx->abs2008) {
9466 tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
9467 } else {
9468 gen_helper_float_chs_d(fp0, fp0);
9469 }
9470 gen_store_fpr64(ctx, fp0, fd);
9471 tcg_temp_free_i64(fp0);
9472 }
9473 break;
9474 case OPC_ROUND_L_D:
9475 check_cp1_64bitmode(ctx);
9476 {
9477 TCGv_i64 fp0 = tcg_temp_new_i64();
9478
9479 gen_load_fpr64(ctx, fp0, fs);
9480 if (ctx->nan2008) {
9481 gen_helper_float_round_2008_l_d(fp0, cpu_env, fp0);
9482 } else {
9483 gen_helper_float_round_l_d(fp0, cpu_env, fp0);
9484 }
9485 gen_store_fpr64(ctx, fp0, fd);
9486 tcg_temp_free_i64(fp0);
9487 }
9488 break;
9489 case OPC_TRUNC_L_D:
9490 check_cp1_64bitmode(ctx);
9491 {
9492 TCGv_i64 fp0 = tcg_temp_new_i64();
9493
9494 gen_load_fpr64(ctx, fp0, fs);
9495 if (ctx->nan2008) {
9496 gen_helper_float_trunc_2008_l_d(fp0, cpu_env, fp0);
9497 } else {
9498 gen_helper_float_trunc_l_d(fp0, cpu_env, fp0);
9499 }
9500 gen_store_fpr64(ctx, fp0, fd);
9501 tcg_temp_free_i64(fp0);
9502 }
9503 break;
9504 case OPC_CEIL_L_D:
9505 check_cp1_64bitmode(ctx);
9506 {
9507 TCGv_i64 fp0 = tcg_temp_new_i64();
9508
9509 gen_load_fpr64(ctx, fp0, fs);
9510 if (ctx->nan2008) {
9511 gen_helper_float_ceil_2008_l_d(fp0, cpu_env, fp0);
9512 } else {
9513 gen_helper_float_ceil_l_d(fp0, cpu_env, fp0);
9514 }
9515 gen_store_fpr64(ctx, fp0, fd);
9516 tcg_temp_free_i64(fp0);
9517 }
9518 break;
9519 case OPC_FLOOR_L_D:
9520 check_cp1_64bitmode(ctx);
9521 {
9522 TCGv_i64 fp0 = tcg_temp_new_i64();
9523
9524 gen_load_fpr64(ctx, fp0, fs);
9525 if (ctx->nan2008) {
9526 gen_helper_float_floor_2008_l_d(fp0, cpu_env, fp0);
9527 } else {
9528 gen_helper_float_floor_l_d(fp0, cpu_env, fp0);
9529 }
9530 gen_store_fpr64(ctx, fp0, fd);
9531 tcg_temp_free_i64(fp0);
9532 }
9533 break;
9534 case OPC_ROUND_W_D:
9535 check_cp1_registers(ctx, fs);
9536 {
9537 TCGv_i32 fp32 = tcg_temp_new_i32();
9538 TCGv_i64 fp64 = tcg_temp_new_i64();
9539
9540 gen_load_fpr64(ctx, fp64, fs);
9541 if (ctx->nan2008) {
9542 gen_helper_float_round_2008_w_d(fp32, cpu_env, fp64);
9543 } else {
9544 gen_helper_float_round_w_d(fp32, cpu_env, fp64);
9545 }
9546 tcg_temp_free_i64(fp64);
9547 gen_store_fpr32(ctx, fp32, fd);
9548 tcg_temp_free_i32(fp32);
9549 }
9550 break;
9551 case OPC_TRUNC_W_D:
9552 check_cp1_registers(ctx, fs);
9553 {
9554 TCGv_i32 fp32 = tcg_temp_new_i32();
9555 TCGv_i64 fp64 = tcg_temp_new_i64();
9556
9557 gen_load_fpr64(ctx, fp64, fs);
9558 if (ctx->nan2008) {
9559 gen_helper_float_trunc_2008_w_d(fp32, cpu_env, fp64);
9560 } else {
9561 gen_helper_float_trunc_w_d(fp32, cpu_env, fp64);
9562 }
9563 tcg_temp_free_i64(fp64);
9564 gen_store_fpr32(ctx, fp32, fd);
9565 tcg_temp_free_i32(fp32);
9566 }
9567 break;
9568 case OPC_CEIL_W_D:
9569 check_cp1_registers(ctx, fs);
9570 {
9571 TCGv_i32 fp32 = tcg_temp_new_i32();
9572 TCGv_i64 fp64 = tcg_temp_new_i64();
9573
9574 gen_load_fpr64(ctx, fp64, fs);
9575 if (ctx->nan2008) {
9576 gen_helper_float_ceil_2008_w_d(fp32, cpu_env, fp64);
9577 } else {
9578 gen_helper_float_ceil_w_d(fp32, cpu_env, fp64);
9579 }
9580 tcg_temp_free_i64(fp64);
9581 gen_store_fpr32(ctx, fp32, fd);
9582 tcg_temp_free_i32(fp32);
9583 }
9584 break;
9585 case OPC_FLOOR_W_D:
9586 check_cp1_registers(ctx, fs);
9587 {
9588 TCGv_i32 fp32 = tcg_temp_new_i32();
9589 TCGv_i64 fp64 = tcg_temp_new_i64();
9590
9591 gen_load_fpr64(ctx, fp64, fs);
9592 if (ctx->nan2008) {
9593 gen_helper_float_floor_2008_w_d(fp32, cpu_env, fp64);
9594 } else {
9595 gen_helper_float_floor_w_d(fp32, cpu_env, fp64);
9596 }
9597 tcg_temp_free_i64(fp64);
9598 gen_store_fpr32(ctx, fp32, fd);
9599 tcg_temp_free_i32(fp32);
9600 }
9601 break;
9602 case OPC_SEL_D:
9603 check_insn(ctx, ISA_MIPS32R6);
9604 gen_sel_d(ctx, op1, fd, ft, fs);
9605 break;
9606 case OPC_SELEQZ_D:
9607 check_insn(ctx, ISA_MIPS32R6);
9608 gen_sel_d(ctx, op1, fd, ft, fs);
9609 break;
9610 case OPC_SELNEZ_D:
9611 check_insn(ctx, ISA_MIPS32R6);
9612 gen_sel_d(ctx, op1, fd, ft, fs);
9613 break;
9614 case OPC_MOVCF_D:
9615 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9616 gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
9617 break;
9618 case OPC_MOVZ_D:
9619 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9620 {
9621 TCGLabel *l1 = gen_new_label();
9622 TCGv_i64 fp0;
9623
9624 if (ft != 0) {
9625 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
9626 }
9627 fp0 = tcg_temp_new_i64();
9628 gen_load_fpr64(ctx, fp0, fs);
9629 gen_store_fpr64(ctx, fp0, fd);
9630 tcg_temp_free_i64(fp0);
9631 gen_set_label(l1);
9632 }
9633 break;
9634 case OPC_MOVN_D:
9635 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9636 {
9637 TCGLabel *l1 = gen_new_label();
9638 TCGv_i64 fp0;
9639
9640 if (ft != 0) {
9641 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
9642 fp0 = tcg_temp_new_i64();
9643 gen_load_fpr64(ctx, fp0, fs);
9644 gen_store_fpr64(ctx, fp0, fd);
9645 tcg_temp_free_i64(fp0);
9646 gen_set_label(l1);
9647 }
9648 }
9649 break;
9650 case OPC_RECIP_D:
9651 check_cp1_registers(ctx, fs | fd);
9652 {
9653 TCGv_i64 fp0 = tcg_temp_new_i64();
9654
9655 gen_load_fpr64(ctx, fp0, fs);
9656 gen_helper_float_recip_d(fp0, cpu_env, fp0);
9657 gen_store_fpr64(ctx, fp0, fd);
9658 tcg_temp_free_i64(fp0);
9659 }
9660 break;
9661 case OPC_RSQRT_D:
9662 check_cp1_registers(ctx, fs | fd);
9663 {
9664 TCGv_i64 fp0 = tcg_temp_new_i64();
9665
9666 gen_load_fpr64(ctx, fp0, fs);
9667 gen_helper_float_rsqrt_d(fp0, cpu_env, fp0);
9668 gen_store_fpr64(ctx, fp0, fd);
9669 tcg_temp_free_i64(fp0);
9670 }
9671 break;
9672 case OPC_MADDF_D:
9673 check_insn(ctx, ISA_MIPS32R6);
9674 {
9675 TCGv_i64 fp0 = tcg_temp_new_i64();
9676 TCGv_i64 fp1 = tcg_temp_new_i64();
9677 TCGv_i64 fp2 = tcg_temp_new_i64();
9678 gen_load_fpr64(ctx, fp0, fs);
9679 gen_load_fpr64(ctx, fp1, ft);
9680 gen_load_fpr64(ctx, fp2, fd);
9681 gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2);
9682 gen_store_fpr64(ctx, fp2, fd);
9683 tcg_temp_free_i64(fp2);
9684 tcg_temp_free_i64(fp1);
9685 tcg_temp_free_i64(fp0);
9686 }
9687 break;
9688 case OPC_MSUBF_D:
9689 check_insn(ctx, ISA_MIPS32R6);
9690 {
9691 TCGv_i64 fp0 = tcg_temp_new_i64();
9692 TCGv_i64 fp1 = tcg_temp_new_i64();
9693 TCGv_i64 fp2 = tcg_temp_new_i64();
9694 gen_load_fpr64(ctx, fp0, fs);
9695 gen_load_fpr64(ctx, fp1, ft);
9696 gen_load_fpr64(ctx, fp2, fd);
9697 gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2);
9698 gen_store_fpr64(ctx, fp2, fd);
9699 tcg_temp_free_i64(fp2);
9700 tcg_temp_free_i64(fp1);
9701 tcg_temp_free_i64(fp0);
9702 }
9703 break;
9704 case OPC_RINT_D:
9705 check_insn(ctx, ISA_MIPS32R6);
9706 {
9707 TCGv_i64 fp0 = tcg_temp_new_i64();
9708 gen_load_fpr64(ctx, fp0, fs);
9709 gen_helper_float_rint_d(fp0, cpu_env, fp0);
9710 gen_store_fpr64(ctx, fp0, fd);
9711 tcg_temp_free_i64(fp0);
9712 }
9713 break;
9714 case OPC_CLASS_D:
9715 check_insn(ctx, ISA_MIPS32R6);
9716 {
9717 TCGv_i64 fp0 = tcg_temp_new_i64();
9718 gen_load_fpr64(ctx, fp0, fs);
9719 gen_helper_float_class_d(fp0, cpu_env, fp0);
9720 gen_store_fpr64(ctx, fp0, fd);
9721 tcg_temp_free_i64(fp0);
9722 }
9723 break;
9724 case OPC_MIN_D: /* OPC_RECIP2_D */
9725 if (ctx->insn_flags & ISA_MIPS32R6) {
9726 /* OPC_MIN_D */
9727 TCGv_i64 fp0 = tcg_temp_new_i64();
9728 TCGv_i64 fp1 = tcg_temp_new_i64();
9729 gen_load_fpr64(ctx, fp0, fs);
9730 gen_load_fpr64(ctx, fp1, ft);
9731 gen_helper_float_min_d(fp1, cpu_env, fp0, fp1);
9732 gen_store_fpr64(ctx, fp1, fd);
9733 tcg_temp_free_i64(fp1);
9734 tcg_temp_free_i64(fp0);
9735 } else {
9736 /* OPC_RECIP2_D */
9737 check_cp1_64bitmode(ctx);
9738 {
9739 TCGv_i64 fp0 = tcg_temp_new_i64();
9740 TCGv_i64 fp1 = tcg_temp_new_i64();
9741
9742 gen_load_fpr64(ctx, fp0, fs);
9743 gen_load_fpr64(ctx, fp1, ft);
9744 gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1);
9745 tcg_temp_free_i64(fp1);
9746 gen_store_fpr64(ctx, fp0, fd);
9747 tcg_temp_free_i64(fp0);
9748 }
9749 }
9750 break;
9751 case OPC_MINA_D: /* OPC_RECIP1_D */
9752 if (ctx->insn_flags & ISA_MIPS32R6) {
9753 /* OPC_MINA_D */
9754 TCGv_i64 fp0 = tcg_temp_new_i64();
9755 TCGv_i64 fp1 = tcg_temp_new_i64();
9756 gen_load_fpr64(ctx, fp0, fs);
9757 gen_load_fpr64(ctx, fp1, ft);
9758 gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1);
9759 gen_store_fpr64(ctx, fp1, fd);
9760 tcg_temp_free_i64(fp1);
9761 tcg_temp_free_i64(fp0);
9762 } else {
9763 /* OPC_RECIP1_D */
9764 check_cp1_64bitmode(ctx);
9765 {
9766 TCGv_i64 fp0 = tcg_temp_new_i64();
9767
9768 gen_load_fpr64(ctx, fp0, fs);
9769 gen_helper_float_recip1_d(fp0, cpu_env, fp0);
9770 gen_store_fpr64(ctx, fp0, fd);
9771 tcg_temp_free_i64(fp0);
9772 }
9773 }
9774 break;
9775 case OPC_MAX_D: /* OPC_RSQRT1_D */
9776 if (ctx->insn_flags & ISA_MIPS32R6) {
9777 /* OPC_MAX_D */
9778 TCGv_i64 fp0 = tcg_temp_new_i64();
9779 TCGv_i64 fp1 = tcg_temp_new_i64();
9780 gen_load_fpr64(ctx, fp0, fs);
9781 gen_load_fpr64(ctx, fp1, ft);
9782 gen_helper_float_max_d(fp1, cpu_env, fp0, fp1);
9783 gen_store_fpr64(ctx, fp1, fd);
9784 tcg_temp_free_i64(fp1);
9785 tcg_temp_free_i64(fp0);
9786 } else {
9787 /* OPC_RSQRT1_D */
9788 check_cp1_64bitmode(ctx);
9789 {
9790 TCGv_i64 fp0 = tcg_temp_new_i64();
9791
9792 gen_load_fpr64(ctx, fp0, fs);
9793 gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0);
9794 gen_store_fpr64(ctx, fp0, fd);
9795 tcg_temp_free_i64(fp0);
9796 }
9797 }
9798 break;
9799 case OPC_MAXA_D: /* OPC_RSQRT2_D */
9800 if (ctx->insn_flags & ISA_MIPS32R6) {
9801 /* OPC_MAXA_D */
9802 TCGv_i64 fp0 = tcg_temp_new_i64();
9803 TCGv_i64 fp1 = tcg_temp_new_i64();
9804 gen_load_fpr64(ctx, fp0, fs);
9805 gen_load_fpr64(ctx, fp1, ft);
9806 gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1);
9807 gen_store_fpr64(ctx, fp1, fd);
9808 tcg_temp_free_i64(fp1);
9809 tcg_temp_free_i64(fp0);
9810 } else {
9811 /* OPC_RSQRT2_D */
9812 check_cp1_64bitmode(ctx);
9813 {
9814 TCGv_i64 fp0 = tcg_temp_new_i64();
9815 TCGv_i64 fp1 = tcg_temp_new_i64();
9816
9817 gen_load_fpr64(ctx, fp0, fs);
9818 gen_load_fpr64(ctx, fp1, ft);
9819 gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1);
9820 tcg_temp_free_i64(fp1);
9821 gen_store_fpr64(ctx, fp0, fd);
9822 tcg_temp_free_i64(fp0);
9823 }
9824 }
9825 break;
9826 case OPC_CMP_F_D:
9827 case OPC_CMP_UN_D:
9828 case OPC_CMP_EQ_D:
9829 case OPC_CMP_UEQ_D:
9830 case OPC_CMP_OLT_D:
9831 case OPC_CMP_ULT_D:
9832 case OPC_CMP_OLE_D:
9833 case OPC_CMP_ULE_D:
9834 case OPC_CMP_SF_D:
9835 case OPC_CMP_NGLE_D:
9836 case OPC_CMP_SEQ_D:
9837 case OPC_CMP_NGL_D:
9838 case OPC_CMP_LT_D:
9839 case OPC_CMP_NGE_D:
9840 case OPC_CMP_LE_D:
9841 case OPC_CMP_NGT_D:
9842 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9843 if (ctx->opcode & (1 << 6)) {
9844 gen_cmpabs_d(ctx, func-48, ft, fs, cc);
9845 } else {
9846 gen_cmp_d(ctx, func-48, ft, fs, cc);
9847 }
9848 break;
9849 case OPC_CVT_S_D:
9850 check_cp1_registers(ctx, fs);
9851 {
9852 TCGv_i32 fp32 = tcg_temp_new_i32();
9853 TCGv_i64 fp64 = tcg_temp_new_i64();
9854
9855 gen_load_fpr64(ctx, fp64, fs);
9856 gen_helper_float_cvts_d(fp32, cpu_env, fp64);
9857 tcg_temp_free_i64(fp64);
9858 gen_store_fpr32(ctx, fp32, fd);
9859 tcg_temp_free_i32(fp32);
9860 }
9861 break;
9862 case OPC_CVT_W_D:
9863 check_cp1_registers(ctx, fs);
9864 {
9865 TCGv_i32 fp32 = tcg_temp_new_i32();
9866 TCGv_i64 fp64 = tcg_temp_new_i64();
9867
9868 gen_load_fpr64(ctx, fp64, fs);
9869 if (ctx->nan2008) {
9870 gen_helper_float_cvt_2008_w_d(fp32, cpu_env, fp64);
9871 } else {
9872 gen_helper_float_cvt_w_d(fp32, cpu_env, fp64);
9873 }
9874 tcg_temp_free_i64(fp64);
9875 gen_store_fpr32(ctx, fp32, fd);
9876 tcg_temp_free_i32(fp32);
9877 }
9878 break;
9879 case OPC_CVT_L_D:
9880 check_cp1_64bitmode(ctx);
9881 {
9882 TCGv_i64 fp0 = tcg_temp_new_i64();
9883
9884 gen_load_fpr64(ctx, fp0, fs);
9885 if (ctx->nan2008) {
9886 gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0);
9887 } else {
9888 gen_helper_float_cvt_l_d(fp0, cpu_env, fp0);
9889 }
9890 gen_store_fpr64(ctx, fp0, fd);
9891 tcg_temp_free_i64(fp0);
9892 }
9893 break;
9894 case OPC_CVT_S_W:
9895 {
9896 TCGv_i32 fp0 = tcg_temp_new_i32();
9897
9898 gen_load_fpr32(ctx, fp0, fs);
9899 gen_helper_float_cvts_w(fp0, cpu_env, fp0);
9900 gen_store_fpr32(ctx, fp0, fd);
9901 tcg_temp_free_i32(fp0);
9902 }
9903 break;
9904 case OPC_CVT_D_W:
9905 check_cp1_registers(ctx, fd);
9906 {
9907 TCGv_i32 fp32 = tcg_temp_new_i32();
9908 TCGv_i64 fp64 = tcg_temp_new_i64();
9909
9910 gen_load_fpr32(ctx, fp32, fs);
9911 gen_helper_float_cvtd_w(fp64, cpu_env, fp32);
9912 tcg_temp_free_i32(fp32);
9913 gen_store_fpr64(ctx, fp64, fd);
9914 tcg_temp_free_i64(fp64);
9915 }
9916 break;
9917 case OPC_CVT_S_L:
9918 check_cp1_64bitmode(ctx);
9919 {
9920 TCGv_i32 fp32 = tcg_temp_new_i32();
9921 TCGv_i64 fp64 = tcg_temp_new_i64();
9922
9923 gen_load_fpr64(ctx, fp64, fs);
9924 gen_helper_float_cvts_l(fp32, cpu_env, fp64);
9925 tcg_temp_free_i64(fp64);
9926 gen_store_fpr32(ctx, fp32, fd);
9927 tcg_temp_free_i32(fp32);
9928 }
9929 break;
9930 case OPC_CVT_D_L:
9931 check_cp1_64bitmode(ctx);
9932 {
9933 TCGv_i64 fp0 = tcg_temp_new_i64();
9934
9935 gen_load_fpr64(ctx, fp0, fs);
9936 gen_helper_float_cvtd_l(fp0, cpu_env, fp0);
9937 gen_store_fpr64(ctx, fp0, fd);
9938 tcg_temp_free_i64(fp0);
9939 }
9940 break;
9941 case OPC_CVT_PS_PW:
9942 check_ps(ctx);
9943 {
9944 TCGv_i64 fp0 = tcg_temp_new_i64();
9945
9946 gen_load_fpr64(ctx, fp0, fs);
9947 gen_helper_float_cvtps_pw(fp0, cpu_env, fp0);
9948 gen_store_fpr64(ctx, fp0, fd);
9949 tcg_temp_free_i64(fp0);
9950 }
9951 break;
9952 case OPC_ADD_PS:
9953 check_ps(ctx);
9954 {
9955 TCGv_i64 fp0 = tcg_temp_new_i64();
9956 TCGv_i64 fp1 = tcg_temp_new_i64();
9957
9958 gen_load_fpr64(ctx, fp0, fs);
9959 gen_load_fpr64(ctx, fp1, ft);
9960 gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1);
9961 tcg_temp_free_i64(fp1);
9962 gen_store_fpr64(ctx, fp0, fd);
9963 tcg_temp_free_i64(fp0);
9964 }
9965 break;
9966 case OPC_SUB_PS:
9967 check_ps(ctx);
9968 {
9969 TCGv_i64 fp0 = tcg_temp_new_i64();
9970 TCGv_i64 fp1 = tcg_temp_new_i64();
9971
9972 gen_load_fpr64(ctx, fp0, fs);
9973 gen_load_fpr64(ctx, fp1, ft);
9974 gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1);
9975 tcg_temp_free_i64(fp1);
9976 gen_store_fpr64(ctx, fp0, fd);
9977 tcg_temp_free_i64(fp0);
9978 }
9979 break;
9980 case OPC_MUL_PS:
9981 check_ps(ctx);
9982 {
9983 TCGv_i64 fp0 = tcg_temp_new_i64();
9984 TCGv_i64 fp1 = tcg_temp_new_i64();
9985
9986 gen_load_fpr64(ctx, fp0, fs);
9987 gen_load_fpr64(ctx, fp1, ft);
9988 gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1);
9989 tcg_temp_free_i64(fp1);
9990 gen_store_fpr64(ctx, fp0, fd);
9991 tcg_temp_free_i64(fp0);
9992 }
9993 break;
9994 case OPC_ABS_PS:
9995 check_ps(ctx);
9996 {
9997 TCGv_i64 fp0 = tcg_temp_new_i64();
9998
9999 gen_load_fpr64(ctx, fp0, fs);
10000 gen_helper_float_abs_ps(fp0, fp0);
10001 gen_store_fpr64(ctx, fp0, fd);
10002 tcg_temp_free_i64(fp0);
10003 }
10004 break;
10005 case OPC_MOV_PS:
10006 check_ps(ctx);
10007 {
10008 TCGv_i64 fp0 = tcg_temp_new_i64();
10009
10010 gen_load_fpr64(ctx, fp0, fs);
10011 gen_store_fpr64(ctx, fp0, fd);
10012 tcg_temp_free_i64(fp0);
10013 }
10014 break;
10015 case OPC_NEG_PS:
10016 check_ps(ctx);
10017 {
10018 TCGv_i64 fp0 = tcg_temp_new_i64();
10019
10020 gen_load_fpr64(ctx, fp0, fs);
10021 gen_helper_float_chs_ps(fp0, fp0);
10022 gen_store_fpr64(ctx, fp0, fd);
10023 tcg_temp_free_i64(fp0);
10024 }
10025 break;
10026 case OPC_MOVCF_PS:
10027 check_ps(ctx);
10028 gen_movcf_ps(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
10029 break;
10030 case OPC_MOVZ_PS:
10031 check_ps(ctx);
10032 {
10033 TCGLabel *l1 = gen_new_label();
10034 TCGv_i64 fp0;
10035
10036 if (ft != 0)
10037 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
10038 fp0 = tcg_temp_new_i64();
10039 gen_load_fpr64(ctx, fp0, fs);
10040 gen_store_fpr64(ctx, fp0, fd);
10041 tcg_temp_free_i64(fp0);
10042 gen_set_label(l1);
10043 }
10044 break;
10045 case OPC_MOVN_PS:
10046 check_ps(ctx);
10047 {
10048 TCGLabel *l1 = gen_new_label();
10049 TCGv_i64 fp0;
10050
10051 if (ft != 0) {
10052 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
10053 fp0 = tcg_temp_new_i64();
10054 gen_load_fpr64(ctx, fp0, fs);
10055 gen_store_fpr64(ctx, fp0, fd);
10056 tcg_temp_free_i64(fp0);
10057 gen_set_label(l1);
10058 }
10059 }
10060 break;
10061 case OPC_ADDR_PS:
10062 check_ps(ctx);
10063 {
10064 TCGv_i64 fp0 = tcg_temp_new_i64();
10065 TCGv_i64 fp1 = tcg_temp_new_i64();
10066
10067 gen_load_fpr64(ctx, fp0, ft);
10068 gen_load_fpr64(ctx, fp1, fs);
10069 gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1);
10070 tcg_temp_free_i64(fp1);
10071 gen_store_fpr64(ctx, fp0, fd);
10072 tcg_temp_free_i64(fp0);
10073 }
10074 break;
10075 case OPC_MULR_PS:
10076 check_ps(ctx);
10077 {
10078 TCGv_i64 fp0 = tcg_temp_new_i64();
10079 TCGv_i64 fp1 = tcg_temp_new_i64();
10080
10081 gen_load_fpr64(ctx, fp0, ft);
10082 gen_load_fpr64(ctx, fp1, fs);
10083 gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1);
10084 tcg_temp_free_i64(fp1);
10085 gen_store_fpr64(ctx, fp0, fd);
10086 tcg_temp_free_i64(fp0);
10087 }
10088 break;
10089 case OPC_RECIP2_PS:
10090 check_ps(ctx);
10091 {
10092 TCGv_i64 fp0 = tcg_temp_new_i64();
10093 TCGv_i64 fp1 = tcg_temp_new_i64();
10094
10095 gen_load_fpr64(ctx, fp0, fs);
10096 gen_load_fpr64(ctx, fp1, ft);
10097 gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1);
10098 tcg_temp_free_i64(fp1);
10099 gen_store_fpr64(ctx, fp0, fd);
10100 tcg_temp_free_i64(fp0);
10101 }
10102 break;
10103 case OPC_RECIP1_PS:
10104 check_ps(ctx);
10105 {
10106 TCGv_i64 fp0 = tcg_temp_new_i64();
10107
10108 gen_load_fpr64(ctx, fp0, fs);
10109 gen_helper_float_recip1_ps(fp0, cpu_env, fp0);
10110 gen_store_fpr64(ctx, fp0, fd);
10111 tcg_temp_free_i64(fp0);
10112 }
10113 break;
10114 case OPC_RSQRT1_PS:
10115 check_ps(ctx);
10116 {
10117 TCGv_i64 fp0 = tcg_temp_new_i64();
10118
10119 gen_load_fpr64(ctx, fp0, fs);
10120 gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0);
10121 gen_store_fpr64(ctx, fp0, fd);
10122 tcg_temp_free_i64(fp0);
10123 }
10124 break;
10125 case OPC_RSQRT2_PS:
10126 check_ps(ctx);
10127 {
10128 TCGv_i64 fp0 = tcg_temp_new_i64();
10129 TCGv_i64 fp1 = tcg_temp_new_i64();
10130
10131 gen_load_fpr64(ctx, fp0, fs);
10132 gen_load_fpr64(ctx, fp1, ft);
10133 gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1);
10134 tcg_temp_free_i64(fp1);
10135 gen_store_fpr64(ctx, fp0, fd);
10136 tcg_temp_free_i64(fp0);
10137 }
10138 break;
10139 case OPC_CVT_S_PU:
10140 check_cp1_64bitmode(ctx);
10141 {
10142 TCGv_i32 fp0 = tcg_temp_new_i32();
10143
10144 gen_load_fpr32h(ctx, fp0, fs);
10145 gen_helper_float_cvts_pu(fp0, cpu_env, fp0);
10146 gen_store_fpr32(ctx, fp0, fd);
10147 tcg_temp_free_i32(fp0);
10148 }
10149 break;
10150 case OPC_CVT_PW_PS:
10151 check_ps(ctx);
10152 {
10153 TCGv_i64 fp0 = tcg_temp_new_i64();
10154
10155 gen_load_fpr64(ctx, fp0, fs);
10156 gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0);
10157 gen_store_fpr64(ctx, fp0, fd);
10158 tcg_temp_free_i64(fp0);
10159 }
10160 break;
10161 case OPC_CVT_S_PL:
10162 check_cp1_64bitmode(ctx);
10163 {
10164 TCGv_i32 fp0 = tcg_temp_new_i32();
10165
10166 gen_load_fpr32(ctx, fp0, fs);
10167 gen_helper_float_cvts_pl(fp0, cpu_env, fp0);
10168 gen_store_fpr32(ctx, fp0, fd);
10169 tcg_temp_free_i32(fp0);
10170 }
10171 break;
10172 case OPC_PLL_PS:
10173 check_ps(ctx);
10174 {
10175 TCGv_i32 fp0 = tcg_temp_new_i32();
10176 TCGv_i32 fp1 = tcg_temp_new_i32();
10177
10178 gen_load_fpr32(ctx, fp0, fs);
10179 gen_load_fpr32(ctx, fp1, ft);
10180 gen_store_fpr32h(ctx, fp0, fd);
10181 gen_store_fpr32(ctx, fp1, fd);
10182 tcg_temp_free_i32(fp0);
10183 tcg_temp_free_i32(fp1);
10184 }
10185 break;
10186 case OPC_PLU_PS:
10187 check_ps(ctx);
10188 {
10189 TCGv_i32 fp0 = tcg_temp_new_i32();
10190 TCGv_i32 fp1 = tcg_temp_new_i32();
10191
10192 gen_load_fpr32(ctx, fp0, fs);
10193 gen_load_fpr32h(ctx, fp1, ft);
10194 gen_store_fpr32(ctx, fp1, fd);
10195 gen_store_fpr32h(ctx, fp0, fd);
10196 tcg_temp_free_i32(fp0);
10197 tcg_temp_free_i32(fp1);
10198 }
10199 break;
10200 case OPC_PUL_PS:
10201 check_ps(ctx);
10202 {
10203 TCGv_i32 fp0 = tcg_temp_new_i32();
10204 TCGv_i32 fp1 = tcg_temp_new_i32();
10205
10206 gen_load_fpr32h(ctx, fp0, fs);
10207 gen_load_fpr32(ctx, fp1, ft);
10208 gen_store_fpr32(ctx, fp1, fd);
10209 gen_store_fpr32h(ctx, fp0, fd);
10210 tcg_temp_free_i32(fp0);
10211 tcg_temp_free_i32(fp1);
10212 }
10213 break;
10214 case OPC_PUU_PS:
10215 check_ps(ctx);
10216 {
10217 TCGv_i32 fp0 = tcg_temp_new_i32();
10218 TCGv_i32 fp1 = tcg_temp_new_i32();
10219
10220 gen_load_fpr32h(ctx, fp0, fs);
10221 gen_load_fpr32h(ctx, fp1, ft);
10222 gen_store_fpr32(ctx, fp1, fd);
10223 gen_store_fpr32h(ctx, fp0, fd);
10224 tcg_temp_free_i32(fp0);
10225 tcg_temp_free_i32(fp1);
10226 }
10227 break;
10228 case OPC_CMP_F_PS:
10229 case OPC_CMP_UN_PS:
10230 case OPC_CMP_EQ_PS:
10231 case OPC_CMP_UEQ_PS:
10232 case OPC_CMP_OLT_PS:
10233 case OPC_CMP_ULT_PS:
10234 case OPC_CMP_OLE_PS:
10235 case OPC_CMP_ULE_PS:
10236 case OPC_CMP_SF_PS:
10237 case OPC_CMP_NGLE_PS:
10238 case OPC_CMP_SEQ_PS:
10239 case OPC_CMP_NGL_PS:
10240 case OPC_CMP_LT_PS:
10241 case OPC_CMP_NGE_PS:
10242 case OPC_CMP_LE_PS:
10243 case OPC_CMP_NGT_PS:
10244 if (ctx->opcode & (1 << 6)) {
10245 gen_cmpabs_ps(ctx, func-48, ft, fs, cc);
10246 } else {
10247 gen_cmp_ps(ctx, func-48, ft, fs, cc);
10248 }
10249 break;
10250 default:
10251 MIPS_INVAL("farith");
10252 generate_exception_end(ctx, EXCP_RI);
10253 return;
10254 }
10255 }
10256
10257 /* Coprocessor 3 (FPU) */
10258 static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
10259 int fd, int fs, int base, int index)
10260 {
10261 TCGv t0 = tcg_temp_new();
10262
10263 if (base == 0) {
10264 gen_load_gpr(t0, index);
10265 } else if (index == 0) {
10266 gen_load_gpr(t0, base);
10267 } else {
10268 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
10269 }
10270 /* Don't do NOP if destination is zero: we must perform the actual
10271 memory access. */
10272 switch (opc) {
10273 case OPC_LWXC1:
10274 check_cop1x(ctx);
10275 {
10276 TCGv_i32 fp0 = tcg_temp_new_i32();
10277
10278 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
10279 tcg_gen_trunc_tl_i32(fp0, t0);
10280 gen_store_fpr32(ctx, fp0, fd);
10281 tcg_temp_free_i32(fp0);
10282 }
10283 break;
10284 case OPC_LDXC1:
10285 check_cop1x(ctx);
10286 check_cp1_registers(ctx, fd);
10287 {
10288 TCGv_i64 fp0 = tcg_temp_new_i64();
10289 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
10290 gen_store_fpr64(ctx, fp0, fd);
10291 tcg_temp_free_i64(fp0);
10292 }
10293 break;
10294 case OPC_LUXC1:
10295 check_cp1_64bitmode(ctx);
10296 tcg_gen_andi_tl(t0, t0, ~0x7);
10297 {
10298 TCGv_i64 fp0 = tcg_temp_new_i64();
10299
10300 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
10301 gen_store_fpr64(ctx, fp0, fd);
10302 tcg_temp_free_i64(fp0);
10303 }
10304 break;
10305 case OPC_SWXC1:
10306 check_cop1x(ctx);
10307 {
10308 TCGv_i32 fp0 = tcg_temp_new_i32();
10309 gen_load_fpr32(ctx, fp0, fs);
10310 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL);
10311 tcg_temp_free_i32(fp0);
10312 }
10313 break;
10314 case OPC_SDXC1:
10315 check_cop1x(ctx);
10316 check_cp1_registers(ctx, fs);
10317 {
10318 TCGv_i64 fp0 = tcg_temp_new_i64();
10319 gen_load_fpr64(ctx, fp0, fs);
10320 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
10321 tcg_temp_free_i64(fp0);
10322 }
10323 break;
10324 case OPC_SUXC1:
10325 check_cp1_64bitmode(ctx);
10326 tcg_gen_andi_tl(t0, t0, ~0x7);
10327 {
10328 TCGv_i64 fp0 = tcg_temp_new_i64();
10329 gen_load_fpr64(ctx, fp0, fs);
10330 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
10331 tcg_temp_free_i64(fp0);
10332 }
10333 break;
10334 }
10335 tcg_temp_free(t0);
10336 }
10337
10338 static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
10339 int fd, int fr, int fs, int ft)
10340 {
10341 switch (opc) {
10342 case OPC_ALNV_PS:
10343 check_ps(ctx);
10344 {
10345 TCGv t0 = tcg_temp_local_new();
10346 TCGv_i32 fp = tcg_temp_new_i32();
10347 TCGv_i32 fph = tcg_temp_new_i32();
10348 TCGLabel *l1 = gen_new_label();
10349 TCGLabel *l2 = gen_new_label();
10350
10351 gen_load_gpr(t0, fr);
10352 tcg_gen_andi_tl(t0, t0, 0x7);
10353
10354 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
10355 gen_load_fpr32(ctx, fp, fs);
10356 gen_load_fpr32h(ctx, fph, fs);
10357 gen_store_fpr32(ctx, fp, fd);
10358 gen_store_fpr32h(ctx, fph, fd);
10359 tcg_gen_br(l2);
10360 gen_set_label(l1);
10361 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
10362 tcg_temp_free(t0);
10363 #ifdef TARGET_WORDS_BIGENDIAN
10364 gen_load_fpr32(ctx, fp, fs);
10365 gen_load_fpr32h(ctx, fph, ft);
10366 gen_store_fpr32h(ctx, fp, fd);
10367 gen_store_fpr32(ctx, fph, fd);
10368 #else
10369 gen_load_fpr32h(ctx, fph, fs);
10370 gen_load_fpr32(ctx, fp, ft);
10371 gen_store_fpr32(ctx, fph, fd);
10372 gen_store_fpr32h(ctx, fp, fd);
10373 #endif
10374 gen_set_label(l2);
10375 tcg_temp_free_i32(fp);
10376 tcg_temp_free_i32(fph);
10377 }
10378 break;
10379 case OPC_MADD_S:
10380 check_cop1x(ctx);
10381 {
10382 TCGv_i32 fp0 = tcg_temp_new_i32();
10383 TCGv_i32 fp1 = tcg_temp_new_i32();
10384 TCGv_i32 fp2 = tcg_temp_new_i32();
10385
10386 gen_load_fpr32(ctx, fp0, fs);
10387 gen_load_fpr32(ctx, fp1, ft);
10388 gen_load_fpr32(ctx, fp2, fr);
10389 gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2);
10390 tcg_temp_free_i32(fp0);
10391 tcg_temp_free_i32(fp1);
10392 gen_store_fpr32(ctx, fp2, fd);
10393 tcg_temp_free_i32(fp2);
10394 }
10395 break;
10396 case OPC_MADD_D:
10397 check_cop1x(ctx);
10398 check_cp1_registers(ctx, fd | fs | ft | fr);
10399 {
10400 TCGv_i64 fp0 = tcg_temp_new_i64();
10401 TCGv_i64 fp1 = tcg_temp_new_i64();
10402 TCGv_i64 fp2 = tcg_temp_new_i64();
10403
10404 gen_load_fpr64(ctx, fp0, fs);
10405 gen_load_fpr64(ctx, fp1, ft);
10406 gen_load_fpr64(ctx, fp2, fr);
10407 gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2);
10408 tcg_temp_free_i64(fp0);
10409 tcg_temp_free_i64(fp1);
10410 gen_store_fpr64(ctx, fp2, fd);
10411 tcg_temp_free_i64(fp2);
10412 }
10413 break;
10414 case OPC_MADD_PS:
10415 check_ps(ctx);
10416 {
10417 TCGv_i64 fp0 = tcg_temp_new_i64();
10418 TCGv_i64 fp1 = tcg_temp_new_i64();
10419 TCGv_i64 fp2 = tcg_temp_new_i64();
10420
10421 gen_load_fpr64(ctx, fp0, fs);
10422 gen_load_fpr64(ctx, fp1, ft);
10423 gen_load_fpr64(ctx, fp2, fr);
10424 gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2);
10425 tcg_temp_free_i64(fp0);
10426 tcg_temp_free_i64(fp1);
10427 gen_store_fpr64(ctx, fp2, fd);
10428 tcg_temp_free_i64(fp2);
10429 }
10430 break;
10431 case OPC_MSUB_S:
10432 check_cop1x(ctx);
10433 {
10434 TCGv_i32 fp0 = tcg_temp_new_i32();
10435 TCGv_i32 fp1 = tcg_temp_new_i32();
10436 TCGv_i32 fp2 = tcg_temp_new_i32();
10437
10438 gen_load_fpr32(ctx, fp0, fs);
10439 gen_load_fpr32(ctx, fp1, ft);
10440 gen_load_fpr32(ctx, fp2, fr);
10441 gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2);
10442 tcg_temp_free_i32(fp0);
10443 tcg_temp_free_i32(fp1);
10444 gen_store_fpr32(ctx, fp2, fd);
10445 tcg_temp_free_i32(fp2);
10446 }
10447 break;
10448 case OPC_MSUB_D:
10449 check_cop1x(ctx);
10450 check_cp1_registers(ctx, fd | fs | ft | fr);
10451 {
10452 TCGv_i64 fp0 = tcg_temp_new_i64();
10453 TCGv_i64 fp1 = tcg_temp_new_i64();
10454 TCGv_i64 fp2 = tcg_temp_new_i64();
10455
10456 gen_load_fpr64(ctx, fp0, fs);
10457 gen_load_fpr64(ctx, fp1, ft);
10458 gen_load_fpr64(ctx, fp2, fr);
10459 gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2);
10460 tcg_temp_free_i64(fp0);
10461 tcg_temp_free_i64(fp1);
10462 gen_store_fpr64(ctx, fp2, fd);
10463 tcg_temp_free_i64(fp2);
10464 }
10465 break;
10466 case OPC_MSUB_PS:
10467 check_ps(ctx);
10468 {
10469 TCGv_i64 fp0 = tcg_temp_new_i64();
10470 TCGv_i64 fp1 = tcg_temp_new_i64();
10471 TCGv_i64 fp2 = tcg_temp_new_i64();
10472
10473 gen_load_fpr64(ctx, fp0, fs);
10474 gen_load_fpr64(ctx, fp1, ft);
10475 gen_load_fpr64(ctx, fp2, fr);
10476 gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2);
10477 tcg_temp_free_i64(fp0);
10478 tcg_temp_free_i64(fp1);
10479 gen_store_fpr64(ctx, fp2, fd);
10480 tcg_temp_free_i64(fp2);
10481 }
10482 break;
10483 case OPC_NMADD_S:
10484 check_cop1x(ctx);
10485 {
10486 TCGv_i32 fp0 = tcg_temp_new_i32();
10487 TCGv_i32 fp1 = tcg_temp_new_i32();
10488 TCGv_i32 fp2 = tcg_temp_new_i32();
10489
10490 gen_load_fpr32(ctx, fp0, fs);
10491 gen_load_fpr32(ctx, fp1, ft);
10492 gen_load_fpr32(ctx, fp2, fr);
10493 gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2);
10494 tcg_temp_free_i32(fp0);
10495 tcg_temp_free_i32(fp1);
10496 gen_store_fpr32(ctx, fp2, fd);
10497 tcg_temp_free_i32(fp2);
10498 }
10499 break;
10500 case OPC_NMADD_D:
10501 check_cop1x(ctx);
10502 check_cp1_registers(ctx, fd | fs | ft | fr);
10503 {
10504 TCGv_i64 fp0 = tcg_temp_new_i64();
10505 TCGv_i64 fp1 = tcg_temp_new_i64();
10506 TCGv_i64 fp2 = tcg_temp_new_i64();
10507
10508 gen_load_fpr64(ctx, fp0, fs);
10509 gen_load_fpr64(ctx, fp1, ft);
10510 gen_load_fpr64(ctx, fp2, fr);
10511 gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2);
10512 tcg_temp_free_i64(fp0);
10513 tcg_temp_free_i64(fp1);
10514 gen_store_fpr64(ctx, fp2, fd);
10515 tcg_temp_free_i64(fp2);
10516 }
10517 break;
10518 case OPC_NMADD_PS:
10519 check_ps(ctx);
10520 {
10521 TCGv_i64 fp0 = tcg_temp_new_i64();
10522 TCGv_i64 fp1 = tcg_temp_new_i64();
10523 TCGv_i64 fp2 = tcg_temp_new_i64();
10524
10525 gen_load_fpr64(ctx, fp0, fs);
10526 gen_load_fpr64(ctx, fp1, ft);
10527 gen_load_fpr64(ctx, fp2, fr);
10528 gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2);
10529 tcg_temp_free_i64(fp0);
10530 tcg_temp_free_i64(fp1);
10531 gen_store_fpr64(ctx, fp2, fd);
10532 tcg_temp_free_i64(fp2);
10533 }
10534 break;
10535 case OPC_NMSUB_S:
10536 check_cop1x(ctx);
10537 {
10538 TCGv_i32 fp0 = tcg_temp_new_i32();
10539 TCGv_i32 fp1 = tcg_temp_new_i32();
10540 TCGv_i32 fp2 = tcg_temp_new_i32();
10541
10542 gen_load_fpr32(ctx, fp0, fs);
10543 gen_load_fpr32(ctx, fp1, ft);
10544 gen_load_fpr32(ctx, fp2, fr);
10545 gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2);
10546 tcg_temp_free_i32(fp0);
10547 tcg_temp_free_i32(fp1);
10548 gen_store_fpr32(ctx, fp2, fd);
10549 tcg_temp_free_i32(fp2);
10550 }
10551 break;
10552 case OPC_NMSUB_D:
10553 check_cop1x(ctx);
10554 check_cp1_registers(ctx, fd | fs | ft | fr);
10555 {
10556 TCGv_i64 fp0 = tcg_temp_new_i64();
10557 TCGv_i64 fp1 = tcg_temp_new_i64();
10558 TCGv_i64 fp2 = tcg_temp_new_i64();
10559
10560 gen_load_fpr64(ctx, fp0, fs);
10561 gen_load_fpr64(ctx, fp1, ft);
10562 gen_load_fpr64(ctx, fp2, fr);
10563 gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2);
10564 tcg_temp_free_i64(fp0);
10565 tcg_temp_free_i64(fp1);
10566 gen_store_fpr64(ctx, fp2, fd);
10567 tcg_temp_free_i64(fp2);
10568 }
10569 break;
10570 case OPC_NMSUB_PS:
10571 check_ps(ctx);
10572 {
10573 TCGv_i64 fp0 = tcg_temp_new_i64();
10574 TCGv_i64 fp1 = tcg_temp_new_i64();
10575 TCGv_i64 fp2 = tcg_temp_new_i64();
10576
10577 gen_load_fpr64(ctx, fp0, fs);
10578 gen_load_fpr64(ctx, fp1, ft);
10579 gen_load_fpr64(ctx, fp2, fr);
10580 gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2);
10581 tcg_temp_free_i64(fp0);
10582 tcg_temp_free_i64(fp1);
10583 gen_store_fpr64(ctx, fp2, fd);
10584 tcg_temp_free_i64(fp2);
10585 }
10586 break;
10587 default:
10588 MIPS_INVAL("flt3_arith");
10589 generate_exception_end(ctx, EXCP_RI);
10590 return;
10591 }
10592 }
10593
10594 static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
10595 {
10596 TCGv t0;
10597
10598 #if !defined(CONFIG_USER_ONLY)
10599 /* The Linux kernel will emulate rdhwr if it's not supported natively.
10600 Therefore only check the ISA in system mode. */
10601 check_insn(ctx, ISA_MIPS32R2);
10602 #endif
10603 t0 = tcg_temp_new();
10604
10605 switch (rd) {
10606 case 0:
10607 gen_helper_rdhwr_cpunum(t0, cpu_env);
10608 gen_store_gpr(t0, rt);
10609 break;
10610 case 1:
10611 gen_helper_rdhwr_synci_step(t0, cpu_env);
10612 gen_store_gpr(t0, rt);
10613 break;
10614 case 2:
10615 gen_helper_rdhwr_cc(t0, cpu_env);
10616 gen_store_gpr(t0, rt);
10617 break;
10618 case 3:
10619 gen_helper_rdhwr_ccres(t0, cpu_env);
10620 gen_store_gpr(t0, rt);
10621 break;
10622 case 4:
10623 check_insn(ctx, ISA_MIPS32R6);
10624 if (sel != 0) {
10625 /* Performance counter registers are not implemented other than
10626 * control register 0.
10627 */
10628 generate_exception(ctx, EXCP_RI);
10629 }
10630 gen_helper_rdhwr_performance(t0, cpu_env);
10631 gen_store_gpr(t0, rt);
10632 break;
10633 case 5:
10634 check_insn(ctx, ISA_MIPS32R6);
10635 gen_helper_rdhwr_xnp(t0, cpu_env);
10636 gen_store_gpr(t0, rt);
10637 break;
10638 case 29:
10639 #if defined(CONFIG_USER_ONLY)
10640 tcg_gen_ld_tl(t0, cpu_env,
10641 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
10642 gen_store_gpr(t0, rt);
10643 break;
10644 #else
10645 if ((ctx->hflags & MIPS_HFLAG_CP0) ||
10646 (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) {
10647 tcg_gen_ld_tl(t0, cpu_env,
10648 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
10649 gen_store_gpr(t0, rt);
10650 } else {
10651 generate_exception_end(ctx, EXCP_RI);
10652 }
10653 break;
10654 #endif
10655 default: /* Invalid */
10656 MIPS_INVAL("rdhwr");
10657 generate_exception_end(ctx, EXCP_RI);
10658 break;
10659 }
10660 tcg_temp_free(t0);
10661 }
10662
10663 static inline void clear_branch_hflags(DisasContext *ctx)
10664 {
10665 ctx->hflags &= ~MIPS_HFLAG_BMASK;
10666 if (ctx->bstate == BS_NONE) {
10667 save_cpu_state(ctx, 0);
10668 } else {
10669 /* it is not safe to save ctx->hflags as hflags may be changed
10670 in execution time by the instruction in delay / forbidden slot. */
10671 tcg_gen_andi_i32(hflags, hflags, ~MIPS_HFLAG_BMASK);
10672 }
10673 }
10674
10675 static void gen_branch(DisasContext *ctx, int insn_bytes)
10676 {
10677 if (ctx->hflags & MIPS_HFLAG_BMASK) {
10678 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK;
10679 /* Branches completion */
10680 clear_branch_hflags(ctx);
10681 ctx->bstate = BS_BRANCH;
10682 /* FIXME: Need to clear can_do_io. */
10683 switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) {
10684 case MIPS_HFLAG_FBNSLOT:
10685 gen_goto_tb(ctx, 0, ctx->pc + insn_bytes);
10686 break;
10687 case MIPS_HFLAG_B:
10688 /* unconditional branch */
10689 if (proc_hflags & MIPS_HFLAG_BX) {
10690 tcg_gen_xori_i32(hflags, hflags, MIPS_HFLAG_M16);
10691 }
10692 gen_goto_tb(ctx, 0, ctx->btarget);
10693 break;
10694 case MIPS_HFLAG_BL:
10695 /* blikely taken case */
10696 gen_goto_tb(ctx, 0, ctx->btarget);
10697 break;
10698 case MIPS_HFLAG_BC:
10699 /* Conditional branch */
10700 {
10701 TCGLabel *l1 = gen_new_label();
10702
10703 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
10704 gen_goto_tb(ctx, 1, ctx->pc + insn_bytes);
10705 gen_set_label(l1);
10706 gen_goto_tb(ctx, 0, ctx->btarget);
10707 }
10708 break;
10709 case MIPS_HFLAG_BR:
10710 /* unconditional branch to register */
10711 if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) {
10712 TCGv t0 = tcg_temp_new();
10713 TCGv_i32 t1 = tcg_temp_new_i32();
10714
10715 tcg_gen_andi_tl(t0, btarget, 0x1);
10716 tcg_gen_trunc_tl_i32(t1, t0);
10717 tcg_temp_free(t0);
10718 tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16);
10719 tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT);
10720 tcg_gen_or_i32(hflags, hflags, t1);
10721 tcg_temp_free_i32(t1);
10722
10723 tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1);
10724 } else {
10725 tcg_gen_mov_tl(cpu_PC, btarget);
10726 }
10727 if (ctx->singlestep_enabled) {
10728 save_cpu_state(ctx, 0);
10729 gen_helper_raise_exception_debug(cpu_env);
10730 }
10731 tcg_gen_exit_tb(0);
10732 break;
10733 default:
10734 fprintf(stderr, "unknown branch 0x%x\n", proc_hflags);
10735 abort();
10736 }
10737 }
10738 }
10739
10740 /* Compact Branches */
10741 static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
10742 int rs, int rt, int32_t offset)
10743 {
10744 int bcond_compute = 0;
10745 TCGv t0 = tcg_temp_new();
10746 TCGv t1 = tcg_temp_new();
10747 int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0;
10748
10749 if (ctx->hflags & MIPS_HFLAG_BMASK) {
10750 #ifdef MIPS_DEBUG_DISAS
10751 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
10752 "\n", ctx->pc);
10753 #endif
10754 generate_exception_end(ctx, EXCP_RI);
10755 goto out;
10756 }
10757
10758 /* Load needed operands and calculate btarget */
10759 switch (opc) {
10760 /* compact branch */
10761 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
10762 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
10763 gen_load_gpr(t0, rs);
10764 gen_load_gpr(t1, rt);
10765 bcond_compute = 1;
10766 ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
10767 if (rs <= rt && rs == 0) {
10768 /* OPC_BEQZALC, OPC_BNEZALC */
10769 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
10770 }
10771 break;
10772 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
10773 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
10774 gen_load_gpr(t0, rs);
10775 gen_load_gpr(t1, rt);
10776 bcond_compute = 1;
10777 ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
10778 break;
10779 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
10780 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
10781 if (rs == 0 || rs == rt) {
10782 /* OPC_BLEZALC, OPC_BGEZALC */
10783 /* OPC_BGTZALC, OPC_BLTZALC */
10784 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
10785 }
10786 gen_load_gpr(t0, rs);
10787 gen_load_gpr(t1, rt);
10788 bcond_compute = 1;
10789 ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
10790 break;
10791 case OPC_BC:
10792 case OPC_BALC:
10793 ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
10794 break;
10795 case OPC_BEQZC:
10796 case OPC_BNEZC:
10797 if (rs != 0) {
10798 /* OPC_BEQZC, OPC_BNEZC */
10799 gen_load_gpr(t0, rs);
10800 bcond_compute = 1;
10801 ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
10802 } else {
10803 /* OPC_JIC, OPC_JIALC */
10804 TCGv tbase = tcg_temp_new();
10805 TCGv toffset = tcg_temp_new();
10806
10807 gen_load_gpr(tbase, rt);
10808 tcg_gen_movi_tl(toffset, offset);
10809 gen_op_addr_add(ctx, btarget, tbase, toffset);
10810 tcg_temp_free(tbase);
10811 tcg_temp_free(toffset);
10812 }
10813 break;
10814 default:
10815 MIPS_INVAL("Compact branch/jump");
10816 generate_exception_end(ctx, EXCP_RI);
10817 goto out;
10818 }
10819
10820 if (bcond_compute == 0) {
10821 /* Uncoditional compact branch */
10822 switch (opc) {
10823 case OPC_JIALC:
10824 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
10825 /* Fallthrough */
10826 case OPC_JIC:
10827 ctx->hflags |= MIPS_HFLAG_BR;
10828 break;
10829 case OPC_BALC:
10830 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
10831 /* Fallthrough */
10832 case OPC_BC:
10833 ctx->hflags |= MIPS_HFLAG_B;
10834 break;
10835 default:
10836 MIPS_INVAL("Compact branch/jump");
10837 generate_exception_end(ctx, EXCP_RI);
10838 goto out;
10839 }
10840
10841 /* Generating branch here as compact branches don't have delay slot */
10842 gen_branch(ctx, 4);
10843 } else {
10844 /* Conditional compact branch */
10845 TCGLabel *fs = gen_new_label();
10846 save_cpu_state(ctx, 0);
10847
10848 switch (opc) {
10849 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
10850 if (rs == 0 && rt != 0) {
10851 /* OPC_BLEZALC */
10852 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
10853 } else if (rs != 0 && rt != 0 && rs == rt) {
10854 /* OPC_BGEZALC */
10855 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
10856 } else {
10857 /* OPC_BGEUC */
10858 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs);
10859 }
10860 break;
10861 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
10862 if (rs == 0 && rt != 0) {
10863 /* OPC_BGTZALC */
10864 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
10865 } else if (rs != 0 && rt != 0 && rs == rt) {
10866 /* OPC_BLTZALC */
10867 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
10868 } else {
10869 /* OPC_BLTUC */
10870 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs);
10871 }
10872 break;
10873 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
10874 if (rs == 0 && rt != 0) {
10875 /* OPC_BLEZC */
10876 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
10877 } else if (rs != 0 && rt != 0 && rs == rt) {
10878 /* OPC_BGEZC */
10879 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
10880 } else {
10881 /* OPC_BGEC */
10882 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
10883 }
10884 break;
10885 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
10886 if (rs == 0 && rt != 0) {
10887 /* OPC_BGTZC */
10888 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
10889 } else if (rs != 0 && rt != 0 && rs == rt) {
10890 /* OPC_BLTZC */
10891 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
10892 } else {
10893 /* OPC_BLTC */
10894 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs);
10895 }
10896 break;
10897 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
10898 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
10899 if (rs >= rt) {
10900 /* OPC_BOVC, OPC_BNVC */
10901 TCGv t2 = tcg_temp_new();
10902 TCGv t3 = tcg_temp_new();
10903 TCGv t4 = tcg_temp_new();
10904 TCGv input_overflow = tcg_temp_new();
10905
10906 gen_load_gpr(t0, rs);
10907 gen_load_gpr(t1, rt);
10908 tcg_gen_ext32s_tl(t2, t0);
10909 tcg_gen_setcond_tl(TCG_COND_NE, input_overflow, t2, t0);
10910 tcg_gen_ext32s_tl(t3, t1);
10911 tcg_gen_setcond_tl(TCG_COND_NE, t4, t3, t1);
10912 tcg_gen_or_tl(input_overflow, input_overflow, t4);
10913
10914 tcg_gen_add_tl(t4, t2, t3);
10915 tcg_gen_ext32s_tl(t4, t4);
10916 tcg_gen_xor_tl(t2, t2, t3);
10917 tcg_gen_xor_tl(t3, t4, t3);
10918 tcg_gen_andc_tl(t2, t3, t2);
10919 tcg_gen_setcondi_tl(TCG_COND_LT, t4, t2, 0);
10920 tcg_gen_or_tl(t4, t4, input_overflow);
10921 if (opc == OPC_BOVC) {
10922 /* OPC_BOVC */
10923 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t4, 0, fs);
10924 } else {
10925 /* OPC_BNVC */
10926 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs);
10927 }
10928 tcg_temp_free(input_overflow);
10929 tcg_temp_free(t4);
10930 tcg_temp_free(t3);
10931 tcg_temp_free(t2);
10932 } else if (rs < rt && rs == 0) {
10933 /* OPC_BEQZALC, OPC_BNEZALC */
10934 if (opc == OPC_BEQZALC) {
10935 /* OPC_BEQZALC */
10936 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t1, 0, fs);
10937 } else {
10938 /* OPC_BNEZALC */
10939 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t1, 0, fs);
10940 }
10941 } else {
10942 /* OPC_BEQC, OPC_BNEC */
10943 if (opc == OPC_BEQC) {
10944 /* OPC_BEQC */
10945 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs);
10946 } else {
10947 /* OPC_BNEC */
10948 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs);
10949 }
10950 }
10951 break;
10952 case OPC_BEQZC:
10953 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs);
10954 break;
10955 case OPC_BNEZC:
10956 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t0, 0, fs);
10957 break;
10958 default:
10959 MIPS_INVAL("Compact conditional branch/jump");
10960 generate_exception_end(ctx, EXCP_RI);
10961 goto out;
10962 }
10963
10964 /* Generating branch here as compact branches don't have delay slot */
10965 gen_goto_tb(ctx, 1, ctx->btarget);
10966 gen_set_label(fs);
10967
10968 ctx->hflags |= MIPS_HFLAG_FBNSLOT;
10969 }
10970
10971 out:
10972 tcg_temp_free(t0);
10973 tcg_temp_free(t1);
10974 }
10975
10976 /* ISA extensions (ASEs) */
10977 /* MIPS16 extension to MIPS32 */
10978
10979 /* MIPS16 major opcodes */
10980 enum {
10981 M16_OPC_ADDIUSP = 0x00,
10982 M16_OPC_ADDIUPC = 0x01,
10983 M16_OPC_B = 0x02,
10984 M16_OPC_JAL = 0x03,
10985 M16_OPC_BEQZ = 0x04,
10986 M16_OPC_BNEQZ = 0x05,
10987 M16_OPC_SHIFT = 0x06,
10988 M16_OPC_LD = 0x07,
10989 M16_OPC_RRIA = 0x08,
10990 M16_OPC_ADDIU8 = 0x09,
10991 M16_OPC_SLTI = 0x0a,
10992 M16_OPC_SLTIU = 0x0b,
10993 M16_OPC_I8 = 0x0c,
10994 M16_OPC_LI = 0x0d,
10995 M16_OPC_CMPI = 0x0e,
10996 M16_OPC_SD = 0x0f,
10997 M16_OPC_LB = 0x10,
10998 M16_OPC_LH = 0x11,
10999 M16_OPC_LWSP = 0x12,
11000 M16_OPC_LW = 0x13,
11001 M16_OPC_LBU = 0x14,
11002 M16_OPC_LHU = 0x15,
11003 M16_OPC_LWPC = 0x16,
11004 M16_OPC_LWU = 0x17,
11005 M16_OPC_SB = 0x18,
11006 M16_OPC_SH = 0x19,
11007 M16_OPC_SWSP = 0x1a,
11008 M16_OPC_SW = 0x1b,
11009 M16_OPC_RRR = 0x1c,
11010 M16_OPC_RR = 0x1d,
11011 M16_OPC_EXTEND = 0x1e,
11012 M16_OPC_I64 = 0x1f
11013 };
11014
11015 /* I8 funct field */
11016 enum {
11017 I8_BTEQZ = 0x0,
11018 I8_BTNEZ = 0x1,
11019 I8_SWRASP = 0x2,
11020 I8_ADJSP = 0x3,
11021 I8_SVRS = 0x4,
11022 I8_MOV32R = 0x5,
11023 I8_MOVR32 = 0x7
11024 };
11025
11026 /* RRR f field */
11027 enum {
11028 RRR_DADDU = 0x0,
11029 RRR_ADDU = 0x1,
11030 RRR_DSUBU = 0x2,
11031 RRR_SUBU = 0x3
11032 };
11033
11034 /* RR funct field */
11035 enum {
11036 RR_JR = 0x00,
11037 RR_SDBBP = 0x01,
11038 RR_SLT = 0x02,
11039 RR_SLTU = 0x03,
11040 RR_SLLV = 0x04,
11041 RR_BREAK = 0x05,
11042 RR_SRLV = 0x06,
11043 RR_SRAV = 0x07,
11044 RR_DSRL = 0x08,
11045 RR_CMP = 0x0a,
11046 RR_NEG = 0x0b,
11047 RR_AND = 0x0c,
11048 RR_OR = 0x0d,
11049 RR_XOR = 0x0e,
11050 RR_NOT = 0x0f,
11051 RR_MFHI = 0x10,
11052 RR_CNVT = 0x11,
11053 RR_MFLO = 0x12,
11054 RR_DSRA = 0x13,
11055 RR_DSLLV = 0x14,
11056 RR_DSRLV = 0x16,
11057 RR_DSRAV = 0x17,
11058 RR_MULT = 0x18,
11059 RR_MULTU = 0x19,
11060 RR_DIV = 0x1a,
11061 RR_DIVU = 0x1b,
11062 RR_DMULT = 0x1c,
11063 RR_DMULTU = 0x1d,
11064 RR_DDIV = 0x1e,
11065 RR_DDIVU = 0x1f
11066 };
11067
11068 /* I64 funct field */
11069 enum {
11070 I64_LDSP = 0x0,
11071 I64_SDSP = 0x1,
11072 I64_SDRASP = 0x2,
11073 I64_DADJSP = 0x3,
11074 I64_LDPC = 0x4,
11075 I64_DADDIU5 = 0x5,
11076 I64_DADDIUPC = 0x6,
11077 I64_DADDIUSP = 0x7
11078 };
11079
11080 /* RR ry field for CNVT */
11081 enum {
11082 RR_RY_CNVT_ZEB = 0x0,
11083 RR_RY_CNVT_ZEH = 0x1,
11084 RR_RY_CNVT_ZEW = 0x2,
11085 RR_RY_CNVT_SEB = 0x4,
11086 RR_RY_CNVT_SEH = 0x5,
11087 RR_RY_CNVT_SEW = 0x6,
11088 };
11089
11090 static int xlat (int r)
11091 {
11092 static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
11093
11094 return map[r];
11095 }
11096
11097 static void gen_mips16_save (DisasContext *ctx,
11098 int xsregs, int aregs,
11099 int do_ra, int do_s0, int do_s1,
11100 int framesize)
11101 {
11102 TCGv t0 = tcg_temp_new();
11103 TCGv t1 = tcg_temp_new();
11104 TCGv t2 = tcg_temp_new();
11105 int args, astatic;
11106
11107 switch (aregs) {
11108 case 0:
11109 case 1:
11110 case 2:
11111 case 3:
11112 case 11:
11113 args = 0;
11114 break;
11115 case 4:
11116 case 5:
11117 case 6:
11118 case 7:
11119 args = 1;
11120 break;
11121 case 8:
11122 case 9:
11123 case 10:
11124 args = 2;
11125 break;
11126 case 12:
11127 case 13:
11128 args = 3;
11129 break;
11130 case 14:
11131 args = 4;
11132 break;
11133 default:
11134 generate_exception_end(ctx, EXCP_RI);
11135 return;
11136 }
11137
11138 switch (args) {
11139 case 4:
11140 gen_base_offset_addr(ctx, t0, 29, 12);
11141 gen_load_gpr(t1, 7);
11142 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
11143 /* Fall through */
11144 case 3:
11145 gen_base_offset_addr(ctx, t0, 29, 8);
11146 gen_load_gpr(t1, 6);
11147 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
11148 /* Fall through */
11149 case 2:
11150 gen_base_offset_addr(ctx, t0, 29, 4);
11151 gen_load_gpr(t1, 5);
11152 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
11153 /* Fall through */
11154 case 1:
11155 gen_base_offset_addr(ctx, t0, 29, 0);
11156 gen_load_gpr(t1, 4);
11157 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
11158 }
11159
11160 gen_load_gpr(t0, 29);
11161
11162 #define DECR_AND_STORE(reg) do { \
11163 tcg_gen_movi_tl(t2, -4); \
11164 gen_op_addr_add(ctx, t0, t0, t2); \
11165 gen_load_gpr(t1, reg); \
11166 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); \
11167 } while (0)
11168
11169 if (do_ra) {
11170 DECR_AND_STORE(31);
11171 }
11172
11173 switch (xsregs) {
11174 case 7:
11175 DECR_AND_STORE(30);
11176 /* Fall through */
11177 case 6:
11178 DECR_AND_STORE(23);
11179 /* Fall through */
11180 case 5:
11181 DECR_AND_STORE(22);
11182 /* Fall through */
11183 case 4:
11184 DECR_AND_STORE(21);
11185 /* Fall through */
11186 case 3:
11187 DECR_AND_STORE(20);
11188 /* Fall through */
11189 case 2:
11190 DECR_AND_STORE(19);
11191 /* Fall through */
11192 case 1:
11193 DECR_AND_STORE(18);
11194 }
11195
11196 if (do_s1) {
11197 DECR_AND_STORE(17);
11198 }
11199 if (do_s0) {
11200 DECR_AND_STORE(16);
11201 }
11202
11203 switch (aregs) {
11204 case 0:
11205 case 4:
11206 case 8:
11207 case 12:
11208 case 14:
11209 astatic = 0;
11210 break;
11211 case 1:
11212 case 5:
11213 case 9:
11214 case 13:
11215 astatic = 1;
11216 break;
11217 case 2:
11218 case 6:
11219 case 10:
11220 astatic = 2;
11221 break;
11222 case 3:
11223 case 7:
11224 astatic = 3;
11225 break;
11226 case 11:
11227 astatic = 4;
11228 break;
11229 default:
11230 generate_exception_end(ctx, EXCP_RI);
11231 return;
11232 }
11233
11234 if (astatic > 0) {
11235 DECR_AND_STORE(7);
11236 if (astatic > 1) {
11237 DECR_AND_STORE(6);
11238 if (astatic > 2) {
11239 DECR_AND_STORE(5);
11240 if (astatic > 3) {
11241 DECR_AND_STORE(4);
11242 }
11243 }
11244 }
11245 }
11246 #undef DECR_AND_STORE
11247
11248 tcg_gen_movi_tl(t2, -framesize);
11249 gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
11250 tcg_temp_free(t0);
11251 tcg_temp_free(t1);
11252 tcg_temp_free(t2);
11253 }
11254
11255 static void gen_mips16_restore (DisasContext *ctx,
11256 int xsregs, int aregs,
11257 int do_ra, int do_s0, int do_s1,
11258 int framesize)
11259 {
11260 int astatic;
11261 TCGv t0 = tcg_temp_new();
11262 TCGv t1 = tcg_temp_new();
11263 TCGv t2 = tcg_temp_new();
11264
11265 tcg_gen_movi_tl(t2, framesize);
11266 gen_op_addr_add(ctx, t0, cpu_gpr[29], t2);
11267
11268 #define DECR_AND_LOAD(reg) do { \
11269 tcg_gen_movi_tl(t2, -4); \
11270 gen_op_addr_add(ctx, t0, t0, t2); \
11271 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); \
11272 gen_store_gpr(t1, reg); \
11273 } while (0)
11274
11275 if (do_ra) {
11276 DECR_AND_LOAD(31);
11277 }
11278
11279 switch (xsregs) {
11280 case 7:
11281 DECR_AND_LOAD(30);
11282 /* Fall through */
11283 case 6:
11284 DECR_AND_LOAD(23);
11285 /* Fall through */
11286 case 5:
11287 DECR_AND_LOAD(22);
11288 /* Fall through */
11289 case 4:
11290 DECR_AND_LOAD(21);
11291 /* Fall through */
11292 case 3:
11293 DECR_AND_LOAD(20);
11294 /* Fall through */
11295 case 2:
11296 DECR_AND_LOAD(19);
11297 /* Fall through */
11298 case 1:
11299 DECR_AND_LOAD(18);
11300 }
11301
11302 if (do_s1) {
11303 DECR_AND_LOAD(17);
11304 }
11305 if (do_s0) {
11306 DECR_AND_LOAD(16);
11307 }
11308
11309 switch (aregs) {
11310 case 0:
11311 case 4:
11312 case 8:
11313 case 12:
11314 case 14:
11315 astatic = 0;
11316 break;
11317 case 1:
11318 case 5:
11319 case 9:
11320 case 13:
11321 astatic = 1;
11322 break;
11323 case 2:
11324 case 6:
11325 case 10:
11326 astatic = 2;
11327 break;
11328 case 3:
11329 case 7:
11330 astatic = 3;
11331 break;
11332 case 11:
11333 astatic = 4;
11334 break;
11335 default:
11336 generate_exception_end(ctx, EXCP_RI);
11337 return;
11338 }
11339
11340 if (astatic > 0) {
11341 DECR_AND_LOAD(7);
11342 if (astatic > 1) {
11343 DECR_AND_LOAD(6);
11344 if (astatic > 2) {
11345 DECR_AND_LOAD(5);
11346 if (astatic > 3) {
11347 DECR_AND_LOAD(4);
11348 }
11349 }
11350 }
11351 }
11352 #undef DECR_AND_LOAD
11353
11354 tcg_gen_movi_tl(t2, framesize);
11355 gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
11356 tcg_temp_free(t0);
11357 tcg_temp_free(t1);
11358 tcg_temp_free(t2);
11359 }
11360
11361 static void gen_addiupc (DisasContext *ctx, int rx, int imm,
11362 int is_64_bit, int extended)
11363 {
11364 TCGv t0;
11365
11366 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
11367 generate_exception_end(ctx, EXCP_RI);
11368 return;
11369 }
11370
11371 t0 = tcg_temp_new();
11372
11373 tcg_gen_movi_tl(t0, pc_relative_pc(ctx));
11374 tcg_gen_addi_tl(cpu_gpr[rx], t0, imm);
11375 if (!is_64_bit) {
11376 tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
11377 }
11378
11379 tcg_temp_free(t0);
11380 }
11381
11382 static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
11383 int16_t offset)
11384 {
11385 TCGv_i32 t0 = tcg_const_i32(op);
11386 TCGv t1 = tcg_temp_new();
11387 gen_base_offset_addr(ctx, t1, base, offset);
11388 gen_helper_cache(cpu_env, t1, t0);
11389 }
11390
11391 #if defined(TARGET_MIPS64)
11392 static void decode_i64_mips16 (DisasContext *ctx,
11393 int ry, int funct, int16_t offset,
11394 int extended)
11395 {
11396 switch (funct) {
11397 case I64_LDSP:
11398 check_insn(ctx, ISA_MIPS3);
11399 check_mips_64(ctx);
11400 offset = extended ? offset : offset << 3;
11401 gen_ld(ctx, OPC_LD, ry, 29, offset);
11402 break;
11403 case I64_SDSP:
11404 check_insn(ctx, ISA_MIPS3);
11405 check_mips_64(ctx);
11406 offset = extended ? offset : offset << 3;
11407 gen_st(ctx, OPC_SD, ry, 29, offset);
11408 break;
11409 case I64_SDRASP:
11410 check_insn(ctx, ISA_MIPS3);
11411 check_mips_64(ctx);
11412 offset = extended ? offset : (ctx->opcode & 0xff) << 3;
11413 gen_st(ctx, OPC_SD, 31, 29, offset);
11414 break;
11415 case I64_DADJSP:
11416 check_insn(ctx, ISA_MIPS3);
11417 check_mips_64(ctx);
11418 offset = extended ? offset : ((int8_t)ctx->opcode) << 3;
11419 gen_arith_imm(ctx, OPC_DADDIU, 29, 29, offset);
11420 break;
11421 case I64_LDPC:
11422 check_insn(ctx, ISA_MIPS3);
11423 check_mips_64(ctx);
11424 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
11425 generate_exception_end(ctx, EXCP_RI);
11426 } else {
11427 offset = extended ? offset : offset << 3;
11428 gen_ld(ctx, OPC_LDPC, ry, 0, offset);
11429 }
11430 break;
11431 case I64_DADDIU5:
11432 check_insn(ctx, ISA_MIPS3);
11433 check_mips_64(ctx);
11434 offset = extended ? offset : ((int8_t)(offset << 3)) >> 3;
11435 gen_arith_imm(ctx, OPC_DADDIU, ry, ry, offset);
11436 break;
11437 case I64_DADDIUPC:
11438 check_insn(ctx, ISA_MIPS3);
11439 check_mips_64(ctx);
11440 offset = extended ? offset : offset << 2;
11441 gen_addiupc(ctx, ry, offset, 1, extended);
11442 break;
11443 case I64_DADDIUSP:
11444 check_insn(ctx, ISA_MIPS3);
11445 check_mips_64(ctx);
11446 offset = extended ? offset : offset << 2;
11447 gen_arith_imm(ctx, OPC_DADDIU, ry, 29, offset);
11448 break;
11449 }
11450 }
11451 #endif
11452
11453 static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
11454 {
11455 int extend = cpu_lduw_code(env, ctx->pc + 2);
11456 int op, rx, ry, funct, sa;
11457 int16_t imm, offset;
11458
11459 ctx->opcode = (ctx->opcode << 16) | extend;
11460 op = (ctx->opcode >> 11) & 0x1f;
11461 sa = (ctx->opcode >> 22) & 0x1f;
11462 funct = (ctx->opcode >> 8) & 0x7;
11463 rx = xlat((ctx->opcode >> 8) & 0x7);
11464 ry = xlat((ctx->opcode >> 5) & 0x7);
11465 offset = imm = (int16_t) (((ctx->opcode >> 16) & 0x1f) << 11
11466 | ((ctx->opcode >> 21) & 0x3f) << 5
11467 | (ctx->opcode & 0x1f));
11468
11469 /* The extended opcodes cleverly reuse the opcodes from their 16-bit
11470 counterparts. */
11471 switch (op) {
11472 case M16_OPC_ADDIUSP:
11473 gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm);
11474 break;
11475 case M16_OPC_ADDIUPC:
11476 gen_addiupc(ctx, rx, imm, 0, 1);
11477 break;
11478 case M16_OPC_B:
11479 gen_compute_branch(ctx, OPC_BEQ, 4, 0, 0, offset << 1, 0);
11480 /* No delay slot, so just process as a normal instruction */
11481 break;
11482 case M16_OPC_BEQZ:
11483 gen_compute_branch(ctx, OPC_BEQ, 4, rx, 0, offset << 1, 0);
11484 /* No delay slot, so just process as a normal instruction */
11485 break;
11486 case M16_OPC_BNEQZ:
11487 gen_compute_branch(ctx, OPC_BNE, 4, rx, 0, offset << 1, 0);
11488 /* No delay slot, so just process as a normal instruction */
11489 break;
11490 case M16_OPC_SHIFT:
11491 switch (ctx->opcode & 0x3) {
11492 case 0x0:
11493 gen_shift_imm(ctx, OPC_SLL, rx, ry, sa);
11494 break;
11495 case 0x1:
11496 #if defined(TARGET_MIPS64)
11497 check_mips_64(ctx);
11498 gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
11499 #else
11500 generate_exception_end(ctx, EXCP_RI);
11501 #endif
11502 break;
11503 case 0x2:
11504 gen_shift_imm(ctx, OPC_SRL, rx, ry, sa);
11505 break;
11506 case 0x3:
11507 gen_shift_imm(ctx, OPC_SRA, rx, ry, sa);
11508 break;
11509 }
11510 break;
11511 #if defined(TARGET_MIPS64)
11512 case M16_OPC_LD:
11513 check_insn(ctx, ISA_MIPS3);
11514 check_mips_64(ctx);
11515 gen_ld(ctx, OPC_LD, ry, rx, offset);
11516 break;
11517 #endif
11518 case M16_OPC_RRIA:
11519 imm = ctx->opcode & 0xf;
11520 imm = imm | ((ctx->opcode >> 20) & 0x7f) << 4;
11521 imm = imm | ((ctx->opcode >> 16) & 0xf) << 11;
11522 imm = (int16_t) (imm << 1) >> 1;
11523 if ((ctx->opcode >> 4) & 0x1) {
11524 #if defined(TARGET_MIPS64)
11525 check_mips_64(ctx);
11526 gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
11527 #else
11528 generate_exception_end(ctx, EXCP_RI);
11529 #endif
11530 } else {
11531 gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
11532 }
11533 break;
11534 case M16_OPC_ADDIU8:
11535 gen_arith_imm(ctx, OPC_ADDIU, rx, rx, imm);
11536 break;
11537 case M16_OPC_SLTI:
11538 gen_slt_imm(ctx, OPC_SLTI, 24, rx, imm);
11539 break;
11540 case M16_OPC_SLTIU:
11541 gen_slt_imm(ctx, OPC_SLTIU, 24, rx, imm);
11542 break;
11543 case M16_OPC_I8:
11544 switch (funct) {
11545 case I8_BTEQZ:
11546 gen_compute_branch(ctx, OPC_BEQ, 4, 24, 0, offset << 1, 0);
11547 break;
11548 case I8_BTNEZ:
11549 gen_compute_branch(ctx, OPC_BNE, 4, 24, 0, offset << 1, 0);
11550 break;
11551 case I8_SWRASP:
11552 gen_st(ctx, OPC_SW, 31, 29, imm);
11553 break;
11554 case I8_ADJSP:
11555 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm);
11556 break;
11557 case I8_SVRS:
11558 check_insn(ctx, ISA_MIPS32);
11559 {
11560 int xsregs = (ctx->opcode >> 24) & 0x7;
11561 int aregs = (ctx->opcode >> 16) & 0xf;
11562 int do_ra = (ctx->opcode >> 6) & 0x1;
11563 int do_s0 = (ctx->opcode >> 5) & 0x1;
11564 int do_s1 = (ctx->opcode >> 4) & 0x1;
11565 int framesize = (((ctx->opcode >> 20) & 0xf) << 4
11566 | (ctx->opcode & 0xf)) << 3;
11567
11568 if (ctx->opcode & (1 << 7)) {
11569 gen_mips16_save(ctx, xsregs, aregs,
11570 do_ra, do_s0, do_s1,
11571 framesize);
11572 } else {
11573 gen_mips16_restore(ctx, xsregs, aregs,
11574 do_ra, do_s0, do_s1,
11575 framesize);
11576 }
11577 }
11578 break;
11579 default:
11580 generate_exception_end(ctx, EXCP_RI);
11581 break;
11582 }
11583 break;
11584 case M16_OPC_LI:
11585 tcg_gen_movi_tl(cpu_gpr[rx], (uint16_t) imm);
11586 break;
11587 case M16_OPC_CMPI:
11588 tcg_gen_xori_tl(cpu_gpr[24], cpu_gpr[rx], (uint16_t) imm);
11589 break;
11590 #if defined(TARGET_MIPS64)
11591 case M16_OPC_SD:
11592 check_insn(ctx, ISA_MIPS3);
11593 check_mips_64(ctx);
11594 gen_st(ctx, OPC_SD, ry, rx, offset);
11595 break;
11596 #endif
11597 case M16_OPC_LB:
11598 gen_ld(ctx, OPC_LB, ry, rx, offset);
11599 break;
11600 case M16_OPC_LH:
11601 gen_ld(ctx, OPC_LH, ry, rx, offset);
11602 break;
11603 case M16_OPC_LWSP:
11604 gen_ld(ctx, OPC_LW, rx, 29, offset);
11605 break;
11606 case M16_OPC_LW:
11607 gen_ld(ctx, OPC_LW, ry, rx, offset);
11608 break;
11609 case M16_OPC_LBU:
11610 gen_ld(ctx, OPC_LBU, ry, rx, offset);
11611 break;
11612 case M16_OPC_LHU:
11613 gen_ld(ctx, OPC_LHU, ry, rx, offset);
11614 break;
11615 case M16_OPC_LWPC:
11616 gen_ld(ctx, OPC_LWPC, rx, 0, offset);
11617 break;
11618 #if defined(TARGET_MIPS64)
11619 case M16_OPC_LWU:
11620 check_insn(ctx, ISA_MIPS3);
11621 check_mips_64(ctx);
11622 gen_ld(ctx, OPC_LWU, ry, rx, offset);
11623 break;
11624 #endif
11625 case M16_OPC_SB:
11626 gen_st(ctx, OPC_SB, ry, rx, offset);
11627 break;
11628 case M16_OPC_SH:
11629 gen_st(ctx, OPC_SH, ry, rx, offset);
11630 break;
11631 case M16_OPC_SWSP:
11632 gen_st(ctx, OPC_SW, rx, 29, offset);
11633 break;
11634 case M16_OPC_SW:
11635 gen_st(ctx, OPC_SW, ry, rx, offset);
11636 break;
11637 #if defined(TARGET_MIPS64)
11638 case M16_OPC_I64:
11639 decode_i64_mips16(ctx, ry, funct, offset, 1);
11640 break;
11641 #endif
11642 default:
11643 generate_exception_end(ctx, EXCP_RI);
11644 break;
11645 }
11646
11647 return 4;
11648 }
11649
11650 static inline bool is_uhi(int sdbbp_code)
11651 {
11652 #ifdef CONFIG_USER_ONLY
11653 return false;
11654 #else
11655 return semihosting_enabled() && sdbbp_code == 1;
11656 #endif
11657 }
11658
11659 static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
11660 {
11661 int rx, ry;
11662 int sa;
11663 int op, cnvt_op, op1, offset;
11664 int funct;
11665 int n_bytes;
11666
11667 op = (ctx->opcode >> 11) & 0x1f;
11668 sa = (ctx->opcode >> 2) & 0x7;
11669 sa = sa == 0 ? 8 : sa;
11670 rx = xlat((ctx->opcode >> 8) & 0x7);
11671 cnvt_op = (ctx->opcode >> 5) & 0x7;
11672 ry = xlat((ctx->opcode >> 5) & 0x7);
11673 op1 = offset = ctx->opcode & 0x1f;
11674
11675 n_bytes = 2;
11676
11677 switch (op) {
11678 case M16_OPC_ADDIUSP:
11679 {
11680 int16_t imm = ((uint8_t) ctx->opcode) << 2;
11681
11682 gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm);
11683 }
11684 break;
11685 case M16_OPC_ADDIUPC:
11686 gen_addiupc(ctx, rx, ((uint8_t) ctx->opcode) << 2, 0, 0);
11687 break;
11688 case M16_OPC_B:
11689 offset = (ctx->opcode & 0x7ff) << 1;
11690 offset = (int16_t)(offset << 4) >> 4;
11691 gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, offset, 0);
11692 /* No delay slot, so just process as a normal instruction */
11693 break;
11694 case M16_OPC_JAL:
11695 offset = cpu_lduw_code(env, ctx->pc + 2);
11696 offset = (((ctx->opcode & 0x1f) << 21)
11697 | ((ctx->opcode >> 5) & 0x1f) << 16
11698 | offset) << 2;
11699 op = ((ctx->opcode >> 10) & 0x1) ? OPC_JALX : OPC_JAL;
11700 gen_compute_branch(ctx, op, 4, rx, ry, offset, 2);
11701 n_bytes = 4;
11702 break;
11703 case M16_OPC_BEQZ:
11704 gen_compute_branch(ctx, OPC_BEQ, 2, rx, 0,
11705 ((int8_t)ctx->opcode) << 1, 0);
11706 /* No delay slot, so just process as a normal instruction */
11707 break;
11708 case M16_OPC_BNEQZ:
11709 gen_compute_branch(ctx, OPC_BNE, 2, rx, 0,
11710 ((int8_t)ctx->opcode) << 1, 0);
11711 /* No delay slot, so just process as a normal instruction */
11712 break;
11713 case M16_OPC_SHIFT:
11714 switch (ctx->opcode & 0x3) {
11715 case 0x0:
11716 gen_shift_imm(ctx, OPC_SLL, rx, ry, sa);
11717 break;
11718 case 0x1:
11719 #if defined(TARGET_MIPS64)
11720 check_insn(ctx, ISA_MIPS3);
11721 check_mips_64(ctx);
11722 gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
11723 #else
11724 generate_exception_end(ctx, EXCP_RI);
11725 #endif
11726 break;
11727 case 0x2:
11728 gen_shift_imm(ctx, OPC_SRL, rx, ry, sa);
11729 break;
11730 case 0x3:
11731 gen_shift_imm(ctx, OPC_SRA, rx, ry, sa);
11732 break;
11733 }
11734 break;
11735 #if defined(TARGET_MIPS64)
11736 case M16_OPC_LD:
11737 check_insn(ctx, ISA_MIPS3);
11738 check_mips_64(ctx);
11739 gen_ld(ctx, OPC_LD, ry, rx, offset << 3);
11740 break;
11741 #endif
11742 case M16_OPC_RRIA:
11743 {
11744 int16_t imm = (int8_t)((ctx->opcode & 0xf) << 4) >> 4;
11745
11746 if ((ctx->opcode >> 4) & 1) {
11747 #if defined(TARGET_MIPS64)
11748 check_insn(ctx, ISA_MIPS3);
11749 check_mips_64(ctx);
11750 gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
11751 #else
11752 generate_exception_end(ctx, EXCP_RI);
11753 #endif
11754 } else {
11755 gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
11756 }
11757 }
11758 break;
11759 case M16_OPC_ADDIU8:
11760 {
11761 int16_t imm = (int8_t) ctx->opcode;
11762
11763 gen_arith_imm(ctx, OPC_ADDIU, rx, rx, imm);
11764 }
11765 break;
11766 case M16_OPC_SLTI:
11767 {
11768 int16_t imm = (uint8_t) ctx->opcode;
11769 gen_slt_imm(ctx, OPC_SLTI, 24, rx, imm);
11770 }
11771 break;
11772 case M16_OPC_SLTIU:
11773 {
11774 int16_t imm = (uint8_t) ctx->opcode;
11775 gen_slt_imm(ctx, OPC_SLTIU, 24, rx, imm);
11776 }
11777 break;
11778 case M16_OPC_I8:
11779 {
11780 int reg32;
11781
11782 funct = (ctx->opcode >> 8) & 0x7;
11783 switch (funct) {
11784 case I8_BTEQZ:
11785 gen_compute_branch(ctx, OPC_BEQ, 2, 24, 0,
11786 ((int8_t)ctx->opcode) << 1, 0);
11787 break;
11788 case I8_BTNEZ:
11789 gen_compute_branch(ctx, OPC_BNE, 2, 24, 0,
11790 ((int8_t)ctx->opcode) << 1, 0);
11791 break;
11792 case I8_SWRASP:
11793 gen_st(ctx, OPC_SW, 31, 29, (ctx->opcode & 0xff) << 2);
11794 break;
11795 case I8_ADJSP:
11796 gen_arith_imm(ctx, OPC_ADDIU, 29, 29,
11797 ((int8_t)ctx->opcode) << 3);
11798 break;
11799 case I8_SVRS:
11800 check_insn(ctx, ISA_MIPS32);
11801 {
11802 int do_ra = ctx->opcode & (1 << 6);
11803 int do_s0 = ctx->opcode & (1 << 5);
11804 int do_s1 = ctx->opcode & (1 << 4);
11805 int framesize = ctx->opcode & 0xf;
11806
11807 if (framesize == 0) {
11808 framesize = 128;
11809 } else {
11810 framesize = framesize << 3;
11811 }
11812
11813 if (ctx->opcode & (1 << 7)) {
11814 gen_mips16_save(ctx, 0, 0,
11815 do_ra, do_s0, do_s1, framesize);
11816 } else {
11817 gen_mips16_restore(ctx, 0, 0,
11818 do_ra, do_s0, do_s1, framesize);
11819 }
11820 }
11821 break;
11822 case I8_MOV32R:
11823 {
11824 int rz = xlat(ctx->opcode & 0x7);
11825
11826 reg32 = (((ctx->opcode >> 3) & 0x3) << 3) |
11827 ((ctx->opcode >> 5) & 0x7);
11828 gen_arith(ctx, OPC_ADDU, reg32, rz, 0);
11829 }
11830 break;
11831 case I8_MOVR32:
11832 reg32 = ctx->opcode & 0x1f;
11833 gen_arith(ctx, OPC_ADDU, ry, reg32, 0);
11834 break;
11835 default:
11836 generate_exception_end(ctx, EXCP_RI);
11837 break;
11838 }
11839 }
11840 break;
11841 case M16_OPC_LI:
11842 {
11843 int16_t imm = (uint8_t) ctx->opcode;
11844
11845 gen_arith_imm(ctx, OPC_ADDIU, rx, 0, imm);
11846 }
11847 break;
11848 case M16_OPC_CMPI:
11849 {
11850 int16_t imm = (uint8_t) ctx->opcode;
11851 gen_logic_imm(ctx, OPC_XORI, 24, rx, imm);
11852 }
11853 break;
11854 #if defined(TARGET_MIPS64)
11855 case M16_OPC_SD:
11856 check_insn(ctx, ISA_MIPS3);
11857 check_mips_64(ctx);
11858 gen_st(ctx, OPC_SD, ry, rx, offset << 3);
11859 break;
11860 #endif
11861 case M16_OPC_LB:
11862 gen_ld(ctx, OPC_LB, ry, rx, offset);
11863 break;
11864 case M16_OPC_LH:
11865 gen_ld(ctx, OPC_LH, ry, rx, offset << 1);
11866 break;
11867 case M16_OPC_LWSP:
11868 gen_ld(ctx, OPC_LW, rx, 29, ((uint8_t)ctx->opcode) << 2);
11869 break;
11870 case M16_OPC_LW:
11871 gen_ld(ctx, OPC_LW, ry, rx, offset << 2);
11872 break;
11873 case M16_OPC_LBU:
11874 gen_ld(ctx, OPC_LBU, ry, rx, offset);
11875 break;
11876 case M16_OPC_LHU:
11877 gen_ld(ctx, OPC_LHU, ry, rx, offset << 1);
11878 break;
11879 case M16_OPC_LWPC:
11880 gen_ld(ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2);
11881 break;
11882 #if defined (TARGET_MIPS64)
11883 case M16_OPC_LWU:
11884 check_insn(ctx, ISA_MIPS3);
11885 check_mips_64(ctx);
11886 gen_ld(ctx, OPC_LWU, ry, rx, offset << 2);
11887 break;
11888 #endif
11889 case M16_OPC_SB:
11890 gen_st(ctx, OPC_SB, ry, rx, offset);
11891 break;
11892 case M16_OPC_SH:
11893 gen_st(ctx, OPC_SH, ry, rx, offset << 1);
11894 break;
11895 case M16_OPC_SWSP:
11896 gen_st(ctx, OPC_SW, rx, 29, ((uint8_t)ctx->opcode) << 2);
11897 break;
11898 case M16_OPC_SW:
11899 gen_st(ctx, OPC_SW, ry, rx, offset << 2);
11900 break;
11901 case M16_OPC_RRR:
11902 {
11903 int rz = xlat((ctx->opcode >> 2) & 0x7);
11904 int mips32_op;
11905
11906 switch (ctx->opcode & 0x3) {
11907 case RRR_ADDU:
11908 mips32_op = OPC_ADDU;
11909 break;
11910 case RRR_SUBU:
11911 mips32_op = OPC_SUBU;
11912 break;
11913 #if defined(TARGET_MIPS64)
11914 case RRR_DADDU:
11915 mips32_op = OPC_DADDU;
11916 check_insn(ctx, ISA_MIPS3);
11917 check_mips_64(ctx);
11918 break;
11919 case RRR_DSUBU:
11920 mips32_op = OPC_DSUBU;
11921 check_insn(ctx, ISA_MIPS3);
11922 check_mips_64(ctx);
11923 break;
11924 #endif
11925 default:
11926 generate_exception_end(ctx, EXCP_RI);
11927 goto done;
11928 }
11929
11930 gen_arith(ctx, mips32_op, rz, rx, ry);
11931 done:
11932 ;
11933 }
11934 break;
11935 case M16_OPC_RR:
11936 switch (op1) {
11937 case RR_JR:
11938 {
11939 int nd = (ctx->opcode >> 7) & 0x1;
11940 int link = (ctx->opcode >> 6) & 0x1;
11941 int ra = (ctx->opcode >> 5) & 0x1;
11942
11943 if (nd) {
11944 check_insn(ctx, ISA_MIPS32);
11945 }
11946
11947 if (link) {
11948 op = OPC_JALR;
11949 } else {
11950 op = OPC_JR;
11951 }
11952
11953 gen_compute_branch(ctx, op, 2, ra ? 31 : rx, 31, 0,
11954 (nd ? 0 : 2));
11955 }
11956 break;
11957 case RR_SDBBP:
11958 if (is_uhi(extract32(ctx->opcode, 5, 6))) {
11959 gen_helper_do_semihosting(cpu_env);
11960 } else {
11961 /* XXX: not clear which exception should be raised
11962 * when in debug mode...
11963 */
11964 check_insn(ctx, ISA_MIPS32);
11965 generate_exception_end(ctx, EXCP_DBp);
11966 }
11967 break;
11968 case RR_SLT:
11969 gen_slt(ctx, OPC_SLT, 24, rx, ry);
11970 break;
11971 case RR_SLTU:
11972 gen_slt(ctx, OPC_SLTU, 24, rx, ry);
11973 break;
11974 case RR_BREAK:
11975 generate_exception_end(ctx, EXCP_BREAK);
11976 break;
11977 case RR_SLLV:
11978 gen_shift(ctx, OPC_SLLV, ry, rx, ry);
11979 break;
11980 case RR_SRLV:
11981 gen_shift(ctx, OPC_SRLV, ry, rx, ry);
11982 break;
11983 case RR_SRAV:
11984 gen_shift(ctx, OPC_SRAV, ry, rx, ry);
11985 break;
11986 #if defined (TARGET_MIPS64)
11987 case RR_DSRL:
11988 check_insn(ctx, ISA_MIPS3);
11989 check_mips_64(ctx);
11990 gen_shift_imm(ctx, OPC_DSRL, ry, ry, sa);
11991 break;
11992 #endif
11993 case RR_CMP:
11994 gen_logic(ctx, OPC_XOR, 24, rx, ry);
11995 break;
11996 case RR_NEG:
11997 gen_arith(ctx, OPC_SUBU, rx, 0, ry);
11998 break;
11999 case RR_AND:
12000 gen_logic(ctx, OPC_AND, rx, rx, ry);
12001 break;
12002 case RR_OR:
12003 gen_logic(ctx, OPC_OR, rx, rx, ry);
12004 break;
12005 case RR_XOR:
12006 gen_logic(ctx, OPC_XOR, rx, rx, ry);
12007 break;
12008 case RR_NOT:
12009 gen_logic(ctx, OPC_NOR, rx, ry, 0);
12010 break;
12011 case RR_MFHI:
12012 gen_HILO(ctx, OPC_MFHI, 0, rx);
12013 break;
12014 case RR_CNVT:
12015 check_insn(ctx, ISA_MIPS32);
12016 switch (cnvt_op) {
12017 case RR_RY_CNVT_ZEB:
12018 tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]);
12019 break;
12020 case RR_RY_CNVT_ZEH:
12021 tcg_gen_ext16u_tl(cpu_gpr[rx], cpu_gpr[rx]);
12022 break;
12023 case RR_RY_CNVT_SEB:
12024 tcg_gen_ext8s_tl(cpu_gpr[rx], cpu_gpr[rx]);
12025 break;
12026 case RR_RY_CNVT_SEH:
12027 tcg_gen_ext16s_tl(cpu_gpr[rx], cpu_gpr[rx]);
12028 break;
12029 #if defined (TARGET_MIPS64)
12030 case RR_RY_CNVT_ZEW:
12031 check_insn(ctx, ISA_MIPS64);
12032 check_mips_64(ctx);
12033 tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]);
12034 break;
12035 case RR_RY_CNVT_SEW:
12036 check_insn(ctx, ISA_MIPS64);
12037 check_mips_64(ctx);
12038 tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
12039 break;
12040 #endif
12041 default:
12042 generate_exception_end(ctx, EXCP_RI);
12043 break;
12044 }
12045 break;
12046 case RR_MFLO:
12047 gen_HILO(ctx, OPC_MFLO, 0, rx);
12048 break;
12049 #if defined (TARGET_MIPS64)
12050 case RR_DSRA:
12051 check_insn(ctx, ISA_MIPS3);
12052 check_mips_64(ctx);
12053 gen_shift_imm(ctx, OPC_DSRA, ry, ry, sa);
12054 break;
12055 case RR_DSLLV:
12056 check_insn(ctx, ISA_MIPS3);
12057 check_mips_64(ctx);
12058 gen_shift(ctx, OPC_DSLLV, ry, rx, ry);
12059 break;
12060 case RR_DSRLV:
12061 check_insn(ctx, ISA_MIPS3);
12062 check_mips_64(ctx);
12063 gen_shift(ctx, OPC_DSRLV, ry, rx, ry);
12064 break;
12065 case RR_DSRAV:
12066 check_insn(ctx, ISA_MIPS3);
12067 check_mips_64(ctx);
12068 gen_shift(ctx, OPC_DSRAV, ry, rx, ry);
12069 break;
12070 #endif
12071 case RR_MULT:
12072 gen_muldiv(ctx, OPC_MULT, 0, rx, ry);
12073 break;
12074 case RR_MULTU:
12075 gen_muldiv(ctx, OPC_MULTU, 0, rx, ry);
12076 break;
12077 case RR_DIV:
12078 gen_muldiv(ctx, OPC_DIV, 0, rx, ry);
12079 break;
12080 case RR_DIVU:
12081 gen_muldiv(ctx, OPC_DIVU, 0, rx, ry);
12082 break;
12083 #if defined (TARGET_MIPS64)
12084 case RR_DMULT:
12085 check_insn(ctx, ISA_MIPS3);
12086 check_mips_64(ctx);
12087 gen_muldiv(ctx, OPC_DMULT, 0, rx, ry);
12088 break;
12089 case RR_DMULTU:
12090 check_insn(ctx, ISA_MIPS3);
12091 check_mips_64(ctx);
12092 gen_muldiv(ctx, OPC_DMULTU, 0, rx, ry);
12093 break;
12094 case RR_DDIV:
12095 check_insn(ctx, ISA_MIPS3);
12096 check_mips_64(ctx);
12097 gen_muldiv(ctx, OPC_DDIV, 0, rx, ry);
12098 break;
12099 case RR_DDIVU:
12100 check_insn(ctx, ISA_MIPS3);
12101 check_mips_64(ctx);
12102 gen_muldiv(ctx, OPC_DDIVU, 0, rx, ry);
12103 break;
12104 #endif
12105 default:
12106 generate_exception_end(ctx, EXCP_RI);
12107 break;
12108 }
12109 break;
12110 case M16_OPC_EXTEND:
12111 decode_extended_mips16_opc(env, ctx);
12112 n_bytes = 4;
12113 break;
12114 #if defined(TARGET_MIPS64)
12115 case M16_OPC_I64:
12116 funct = (ctx->opcode >> 8) & 0x7;
12117 decode_i64_mips16(ctx, ry, funct, offset, 0);
12118 break;
12119 #endif
12120 default:
12121 generate_exception_end(ctx, EXCP_RI);
12122 break;
12123 }
12124
12125 return n_bytes;
12126 }
12127
12128 /* microMIPS extension to MIPS32/MIPS64 */
12129
12130 /*
12131 * microMIPS32/microMIPS64 major opcodes
12132 *
12133 * 1. MIPS Architecture for Programmers Volume II-B:
12134 * The microMIPS32 Instruction Set (Revision 3.05)
12135 *
12136 * Table 6.2 microMIPS32 Encoding of Major Opcode Field
12137 *
12138 * 2. MIPS Architecture For Programmers Volume II-A:
12139 * The MIPS64 Instruction Set (Revision 3.51)
12140 */
12141
12142 enum {
12143 POOL32A = 0x00,
12144 POOL16A = 0x01,
12145 LBU16 = 0x02,
12146 MOVE16 = 0x03,
12147 ADDI32 = 0x04,
12148 R6_LUI = 0x04,
12149 AUI = 0x04,
12150 LBU32 = 0x05,
12151 SB32 = 0x06,
12152 LB32 = 0x07,
12153
12154 POOL32B = 0x08,
12155 POOL16B = 0x09,
12156 LHU16 = 0x0a,
12157 ANDI16 = 0x0b,
12158 ADDIU32 = 0x0c,
12159 LHU32 = 0x0d,
12160 SH32 = 0x0e,
12161 LH32 = 0x0f,
12162
12163 POOL32I = 0x10,
12164 POOL16C = 0x11,
12165 LWSP16 = 0x12,
12166 POOL16D = 0x13,
12167 ORI32 = 0x14,
12168 POOL32F = 0x15,
12169 POOL32S = 0x16, /* MIPS64 */
12170 DADDIU32 = 0x17, /* MIPS64 */
12171
12172 POOL32C = 0x18,
12173 LWGP16 = 0x19,
12174 LW16 = 0x1a,
12175 POOL16E = 0x1b,
12176 XORI32 = 0x1c,
12177 JALS32 = 0x1d,
12178 BOVC = 0x1d,
12179 BEQC = 0x1d,
12180 BEQZALC = 0x1d,
12181 ADDIUPC = 0x1e,
12182 PCREL = 0x1e,
12183 BNVC = 0x1f,
12184 BNEC = 0x1f,
12185 BNEZALC = 0x1f,
12186
12187 R6_BEQZC = 0x20,
12188 JIC = 0x20,
12189 POOL16F = 0x21,
12190 SB16 = 0x22,
12191 BEQZ16 = 0x23,
12192 BEQZC16 = 0x23,
12193 SLTI32 = 0x24,
12194 BEQ32 = 0x25,
12195 BC = 0x25,
12196 SWC132 = 0x26,
12197 LWC132 = 0x27,
12198
12199 /* 0x29 is reserved */
12200 RES_29 = 0x29,
12201 R6_BNEZC = 0x28,
12202 JIALC = 0x28,
12203 SH16 = 0x2a,
12204 BNEZ16 = 0x2b,
12205 BNEZC16 = 0x2b,
12206 SLTIU32 = 0x2c,
12207 BNE32 = 0x2d,
12208 BALC = 0x2d,
12209 SDC132 = 0x2e,
12210 LDC132 = 0x2f,
12211
12212 /* 0x31 is reserved */
12213 RES_31 = 0x31,
12214 BLEZALC = 0x30,
12215 BGEZALC = 0x30,
12216 BGEUC = 0x30,
12217 SWSP16 = 0x32,
12218 B16 = 0x33,
12219 BC16 = 0x33,
12220 ANDI32 = 0x34,
12221 J32 = 0x35,
12222 BGTZC = 0x35,
12223 BLTZC = 0x35,
12224 BLTC = 0x35,
12225 SD32 = 0x36, /* MIPS64 */
12226 LD32 = 0x37, /* MIPS64 */
12227
12228 /* 0x39 is reserved */
12229 RES_39 = 0x39,
12230 BGTZALC = 0x38,
12231 BLTZALC = 0x38,
12232 BLTUC = 0x38,
12233 SW16 = 0x3a,
12234 LI16 = 0x3b,
12235 JALX32 = 0x3c,
12236 JAL32 = 0x3d,
12237 BLEZC = 0x3d,
12238 BGEZC = 0x3d,
12239 BGEC = 0x3d,
12240 SW32 = 0x3e,
12241 LW32 = 0x3f
12242 };
12243
12244 /* PCREL Instructions perform PC-Relative address calculation. bits 20..16 */
12245 enum {
12246 ADDIUPC_00 = 0x00,
12247 ADDIUPC_07 = 0x07,
12248 AUIPC = 0x1e,
12249 ALUIPC = 0x1f,
12250 LWPC_08 = 0x08,
12251 LWPC_0F = 0x0F,
12252 };
12253
12254 /* POOL32A encoding of minor opcode field */
12255
12256 enum {
12257 /* These opcodes are distinguished only by bits 9..6; those bits are
12258 * what are recorded below. */
12259 SLL32 = 0x0,
12260 SRL32 = 0x1,
12261 SRA = 0x2,
12262 ROTR = 0x3,
12263 SELEQZ = 0x5,
12264 SELNEZ = 0x6,
12265 R6_RDHWR = 0x7,
12266
12267 SLLV = 0x0,
12268 SRLV = 0x1,
12269 SRAV = 0x2,
12270 ROTRV = 0x3,
12271 ADD = 0x4,
12272 ADDU32 = 0x5,
12273 SUB = 0x6,
12274 SUBU32 = 0x7,
12275 MUL = 0x8,
12276 AND = 0x9,
12277 OR32 = 0xa,
12278 NOR = 0xb,
12279 XOR32 = 0xc,
12280 SLT = 0xd,
12281 SLTU = 0xe,
12282
12283 MOVN = 0x0,
12284 R6_MUL = 0x0,
12285 MOVZ = 0x1,
12286 MUH = 0x1,
12287 MULU = 0x2,
12288 MUHU = 0x3,
12289 LWXS = 0x4,
12290 R6_DIV = 0x4,
12291 MOD = 0x5,
12292 R6_DIVU = 0x6,
12293 MODU = 0x7,
12294
12295 /* The following can be distinguished by their lower 6 bits. */
12296 BREAK32 = 0x07,
12297 INS = 0x0c,
12298 LSA = 0x0f,
12299 ALIGN = 0x1f,
12300 EXT = 0x2c,
12301 POOL32AXF = 0x3c,
12302 SIGRIE = 0x3f
12303 };
12304
12305 /* POOL32AXF encoding of minor opcode field extension */
12306
12307 /*
12308 * 1. MIPS Architecture for Programmers Volume II-B:
12309 * The microMIPS32 Instruction Set (Revision 3.05)
12310 *
12311 * Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field
12312 *
12313 * 2. MIPS Architecture for Programmers VolumeIV-e:
12314 * The MIPS DSP Application-Specific Extension
12315 * to the microMIPS32 Architecture (Revision 2.34)
12316 *
12317 * Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field
12318 */
12319
12320 enum {
12321 /* bits 11..6 */
12322 TEQ = 0x00,
12323 TGE = 0x08,
12324 TGEU = 0x10,
12325 TLT = 0x20,
12326 TLTU = 0x28,
12327 TNE = 0x30,
12328
12329 MFC0 = 0x03,
12330 MTC0 = 0x0b,
12331
12332 /* begin of microMIPS32 DSP */
12333
12334 /* bits 13..12 for 0x01 */
12335 MFHI_ACC = 0x0,
12336 MFLO_ACC = 0x1,
12337 MTHI_ACC = 0x2,
12338 MTLO_ACC = 0x3,
12339
12340 /* bits 13..12 for 0x2a */
12341 MADD_ACC = 0x0,
12342 MADDU_ACC = 0x1,
12343 MSUB_ACC = 0x2,
12344 MSUBU_ACC = 0x3,
12345
12346 /* bits 13..12 for 0x32 */
12347 MULT_ACC = 0x0,
12348 MULTU_ACC = 0x1,
12349
12350 /* end of microMIPS32 DSP */
12351
12352 /* bits 15..12 for 0x2c */
12353 BITSWAP = 0x0,
12354 SEB = 0x2,
12355 SEH = 0x3,
12356 CLO = 0x4,
12357 CLZ = 0x5,
12358 RDHWR = 0x6,
12359 WSBH = 0x7,
12360 MULT = 0x8,
12361 MULTU = 0x9,
12362 DIV = 0xa,
12363 DIVU = 0xb,
12364 MADD = 0xc,
12365 MADDU = 0xd,
12366 MSUB = 0xe,
12367 MSUBU = 0xf,
12368
12369 /* bits 15..12 for 0x34 */
12370 MFC2 = 0x4,
12371 MTC2 = 0x5,
12372 MFHC2 = 0x8,
12373 MTHC2 = 0x9,
12374 CFC2 = 0xc,
12375 CTC2 = 0xd,
12376
12377 /* bits 15..12 for 0x3c */
12378 JALR = 0x0,
12379 JR = 0x0, /* alias */
12380 JALRC = 0x0,
12381 JRC = 0x0,
12382 JALR_HB = 0x1,
12383 JALRC_HB = 0x1,
12384 JALRS = 0x4,
12385 JALRS_HB = 0x5,
12386
12387 /* bits 15..12 for 0x05 */
12388 RDPGPR = 0xe,
12389 WRPGPR = 0xf,
12390
12391 /* bits 15..12 for 0x0d */
12392 TLBP = 0x0,
12393 TLBR = 0x1,
12394 TLBWI = 0x2,
12395 TLBWR = 0x3,
12396 TLBINV = 0x4,
12397 TLBINVF = 0x5,
12398 WAIT = 0x9,
12399 IRET = 0xd,
12400 DERET = 0xe,
12401 ERET = 0xf,
12402
12403 /* bits 15..12 for 0x15 */
12404 DMT = 0x0,
12405 DVPE = 0x1,
12406 EMT = 0x2,
12407 EVPE = 0x3,
12408
12409 /* bits 15..12 for 0x1d */
12410 DI = 0x4,
12411 EI = 0x5,
12412
12413 /* bits 15..12 for 0x2d */
12414 SYNC = 0x6,
12415 SYSCALL = 0x8,
12416 SDBBP = 0xd,
12417
12418 /* bits 15..12 for 0x35 */
12419 MFHI32 = 0x0,
12420 MFLO32 = 0x1,
12421 MTHI32 = 0x2,
12422 MTLO32 = 0x3,
12423 };
12424
12425 /* POOL32B encoding of minor opcode field (bits 15..12) */
12426
12427 enum {
12428 LWC2 = 0x0,
12429 LWP = 0x1,
12430 LDP = 0x4,
12431 LWM32 = 0x5,
12432 CACHE = 0x6,
12433 LDM = 0x7,
12434 SWC2 = 0x8,
12435 SWP = 0x9,
12436 SDP = 0xc,
12437 SWM32 = 0xd,
12438 SDM = 0xf
12439 };
12440
12441 /* POOL32C encoding of minor opcode field (bits 15..12) */
12442
12443 enum {
12444 LWL = 0x0,
12445 SWL = 0x8,
12446 LWR = 0x1,
12447 SWR = 0x9,
12448 PREF = 0x2,
12449 /* 0xa is reserved */
12450 LL = 0x3,
12451 SC = 0xb,
12452 LDL = 0x4,
12453 SDL = 0xc,
12454 LDR = 0x5,
12455 SDR = 0xd,
12456 /* 0x6 is reserved */
12457 LWU = 0xe,
12458 LLD = 0x7,
12459 SCD = 0xf
12460 };
12461
12462 /* POOL32F encoding of minor opcode field (bits 5..0) */
12463
12464 enum {
12465 /* These are the bit 7..6 values */
12466 ADD_FMT = 0x0,
12467
12468 SUB_FMT = 0x1,
12469
12470 MUL_FMT = 0x2,
12471
12472 DIV_FMT = 0x3,
12473
12474 /* These are the bit 8..6 values */
12475 MOVN_FMT = 0x0,
12476 RSQRT2_FMT = 0x0,
12477 MOVF_FMT = 0x0,
12478 RINT_FMT = 0x0,
12479 SELNEZ_FMT = 0x0,
12480
12481 MOVZ_FMT = 0x1,
12482 LWXC1 = 0x1,
12483 MOVT_FMT = 0x1,
12484 CLASS_FMT = 0x1,
12485 SELEQZ_FMT = 0x1,
12486
12487 PLL_PS = 0x2,
12488 SWXC1 = 0x2,
12489 SEL_FMT = 0x2,
12490
12491 PLU_PS = 0x3,
12492 LDXC1 = 0x3,
12493
12494 MOVN_FMT_04 = 0x4,
12495 PUL_PS = 0x4,
12496 SDXC1 = 0x4,
12497 RECIP2_FMT = 0x4,
12498
12499 MOVZ_FMT_05 = 0x05,
12500 PUU_PS = 0x5,
12501 LUXC1 = 0x5,
12502
12503 CVT_PS_S = 0x6,
12504 SUXC1 = 0x6,
12505 ADDR_PS = 0x6,
12506 PREFX = 0x6,
12507 MADDF_FMT = 0x6,
12508
12509 MULR_PS = 0x7,
12510 MSUBF_FMT = 0x7,
12511
12512 MADD_S = 0x01,
12513 MADD_D = 0x09,
12514 MADD_PS = 0x11,
12515 ALNV_PS = 0x19,
12516 MSUB_S = 0x21,
12517 MSUB_D = 0x29,
12518 MSUB_PS = 0x31,
12519
12520 NMADD_S = 0x02,
12521 NMADD_D = 0x0a,
12522 NMADD_PS = 0x12,
12523 NMSUB_S = 0x22,
12524 NMSUB_D = 0x2a,
12525 NMSUB_PS = 0x32,
12526
12527 MIN_FMT = 0x3,
12528 MAX_FMT = 0xb,
12529 MINA_FMT = 0x23,
12530 MAXA_FMT = 0x2b,
12531 POOL32FXF = 0x3b,
12532
12533 CABS_COND_FMT = 0x1c, /* MIPS3D */
12534 C_COND_FMT = 0x3c,
12535
12536 CMP_CONDN_S = 0x5,
12537 CMP_CONDN_D = 0x15
12538 };
12539
12540 /* POOL32Fxf encoding of minor opcode extension field */
12541
12542 enum {
12543 CVT_L = 0x04,
12544 RSQRT_FMT = 0x08,
12545 FLOOR_L = 0x0c,
12546 CVT_PW_PS = 0x1c,
12547 CVT_W = 0x24,
12548 SQRT_FMT = 0x28,
12549 FLOOR_W = 0x2c,
12550 CVT_PS_PW = 0x3c,
12551 CFC1 = 0x40,
12552 RECIP_FMT = 0x48,
12553 CEIL_L = 0x4c,
12554 CTC1 = 0x60,
12555 CEIL_W = 0x6c,
12556 MFC1 = 0x80,
12557 CVT_S_PL = 0x84,
12558 TRUNC_L = 0x8c,
12559 MTC1 = 0xa0,
12560 CVT_S_PU = 0xa4,
12561 TRUNC_W = 0xac,
12562 MFHC1 = 0xc0,
12563 ROUND_L = 0xcc,
12564 MTHC1 = 0xe0,
12565 ROUND_W = 0xec,
12566
12567 MOV_FMT = 0x01,
12568 MOVF = 0x05,
12569 ABS_FMT = 0x0d,
12570 RSQRT1_FMT = 0x1d,
12571 MOVT = 0x25,
12572 NEG_FMT = 0x2d,
12573 CVT_D = 0x4d,
12574 RECIP1_FMT = 0x5d,
12575 CVT_S = 0x6d
12576 };
12577
12578 /* POOL32I encoding of minor opcode field (bits 25..21) */
12579
12580 enum {
12581 BLTZ = 0x00,
12582 BLTZAL = 0x01,
12583 BGEZ = 0x02,
12584 BGEZAL = 0x03,
12585 BLEZ = 0x04,
12586 BNEZC = 0x05,
12587 BGTZ = 0x06,
12588 BEQZC = 0x07,
12589 TLTI = 0x08,
12590 BC1EQZC = 0x08,
12591 TGEI = 0x09,
12592 BC1NEZC = 0x09,
12593 TLTIU = 0x0a,
12594 BC2EQZC = 0x0a,
12595 TGEIU = 0x0b,
12596 BC2NEZC = 0x0a,
12597 TNEI = 0x0c,
12598 R6_SYNCI = 0x0c,
12599 LUI = 0x0d,
12600 TEQI = 0x0e,
12601 SYNCI = 0x10,
12602 BLTZALS = 0x11,
12603 BGEZALS = 0x13,
12604 BC2F = 0x14,
12605 BC2T = 0x15,
12606 BPOSGE64 = 0x1a,
12607 BPOSGE32 = 0x1b,
12608 /* These overlap and are distinguished by bit16 of the instruction */
12609 BC1F = 0x1c,
12610 BC1T = 0x1d,
12611 BC1ANY2F = 0x1c,
12612 BC1ANY2T = 0x1d,
12613 BC1ANY4F = 0x1e,
12614 BC1ANY4T = 0x1f
12615 };
12616
12617 /* POOL16A encoding of minor opcode field */
12618
12619 enum {
12620 ADDU16 = 0x0,
12621 SUBU16 = 0x1
12622 };
12623
12624 /* POOL16B encoding of minor opcode field */
12625
12626 enum {
12627 SLL16 = 0x0,
12628 SRL16 = 0x1
12629 };
12630
12631 /* POOL16C encoding of minor opcode field */
12632
12633 enum {
12634 NOT16 = 0x00,
12635 XOR16 = 0x04,
12636 AND16 = 0x08,
12637 OR16 = 0x0c,
12638 LWM16 = 0x10,
12639 SWM16 = 0x14,
12640 JR16 = 0x18,
12641 JRC16 = 0x1a,
12642 JALR16 = 0x1c,
12643 JALR16S = 0x1e,
12644 MFHI16 = 0x20,
12645 MFLO16 = 0x24,
12646 BREAK16 = 0x28,
12647 SDBBP16 = 0x2c,
12648 JRADDIUSP = 0x30
12649 };
12650
12651 /* R6 POOL16C encoding of minor opcode field (bits 0..5) */
12652
12653 enum {
12654 R6_NOT16 = 0x00,
12655 R6_AND16 = 0x01,
12656 R6_LWM16 = 0x02,
12657 R6_JRC16 = 0x03,
12658 MOVEP = 0x04,
12659 MOVEP_07 = 0x07,
12660 R6_XOR16 = 0x08,
12661 R6_OR16 = 0x09,
12662 R6_SWM16 = 0x0a,
12663 JALRC16 = 0x0b,
12664 MOVEP_0C = 0x0c,
12665 MOVEP_0F = 0x0f,
12666 JRCADDIUSP = 0x13,
12667 R6_BREAK16 = 0x1b,
12668 R6_SDBBP16 = 0x3b
12669 };
12670
12671 /* POOL16D encoding of minor opcode field */
12672
12673 enum {
12674 ADDIUS5 = 0x0,
12675 ADDIUSP = 0x1
12676 };
12677
12678 /* POOL16E encoding of minor opcode field */
12679
12680 enum {
12681 ADDIUR2 = 0x0,
12682 ADDIUR1SP = 0x1
12683 };
12684
12685 static int mmreg (int r)
12686 {
12687 static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
12688
12689 return map[r];
12690 }
12691
12692 /* Used for 16-bit store instructions. */
12693 static int mmreg2 (int r)
12694 {
12695 static const int map[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
12696
12697 return map[r];
12698 }
12699
12700 #define uMIPS_RD(op) ((op >> 7) & 0x7)
12701 #define uMIPS_RS(op) ((op >> 4) & 0x7)
12702 #define uMIPS_RS2(op) uMIPS_RS(op)
12703 #define uMIPS_RS1(op) ((op >> 1) & 0x7)
12704 #define uMIPS_RD5(op) ((op >> 5) & 0x1f)
12705 #define uMIPS_RS5(op) (op & 0x1f)
12706
12707 /* Signed immediate */
12708 #define SIMM(op, start, width) \
12709 ((int32_t)(((op >> start) & ((~0U) >> (32-width))) \
12710 << (32-width)) \
12711 >> (32-width))
12712 /* Zero-extended immediate */
12713 #define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32-width)))
12714
12715 static void gen_addiur1sp(DisasContext *ctx)
12716 {
12717 int rd = mmreg(uMIPS_RD(ctx->opcode));
12718
12719 gen_arith_imm(ctx, OPC_ADDIU, rd, 29, ((ctx->opcode >> 1) & 0x3f) << 2);
12720 }
12721
12722 static void gen_addiur2(DisasContext *ctx)
12723 {
12724 static const int decoded_imm[] = { 1, 4, 8, 12, 16, 20, 24, -1 };
12725 int rd = mmreg(uMIPS_RD(ctx->opcode));
12726 int rs = mmreg(uMIPS_RS(ctx->opcode));
12727
12728 gen_arith_imm(ctx, OPC_ADDIU, rd, rs, decoded_imm[ZIMM(ctx->opcode, 1, 3)]);
12729 }
12730
12731 static void gen_addiusp(DisasContext *ctx)
12732 {
12733 int encoded = ZIMM(ctx->opcode, 1, 9);
12734 int decoded;
12735
12736 if (encoded <= 1) {
12737 decoded = 256 + encoded;
12738 } else if (encoded <= 255) {
12739 decoded = encoded;
12740 } else if (encoded <= 509) {
12741 decoded = encoded - 512;
12742 } else {
12743 decoded = encoded - 768;
12744 }
12745
12746 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, decoded << 2);
12747 }
12748
12749 static void gen_addius5(DisasContext *ctx)
12750 {
12751 int imm = SIMM(ctx->opcode, 1, 4);
12752 int rd = (ctx->opcode >> 5) & 0x1f;
12753
12754 gen_arith_imm(ctx, OPC_ADDIU, rd, rd, imm);
12755 }
12756
12757 static void gen_andi16(DisasContext *ctx)
12758 {
12759 static const int decoded_imm[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16,
12760 31, 32, 63, 64, 255, 32768, 65535 };
12761 int rd = mmreg(uMIPS_RD(ctx->opcode));
12762 int rs = mmreg(uMIPS_RS(ctx->opcode));
12763 int encoded = ZIMM(ctx->opcode, 0, 4);
12764
12765 gen_logic_imm(ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]);
12766 }
12767
12768 static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist,
12769 int base, int16_t offset)
12770 {
12771 TCGv t0, t1;
12772 TCGv_i32 t2;
12773
12774 if (ctx->hflags & MIPS_HFLAG_BMASK) {
12775 generate_exception_end(ctx, EXCP_RI);
12776 return;
12777 }
12778
12779 t0 = tcg_temp_new();
12780
12781 gen_base_offset_addr(ctx, t0, base, offset);
12782
12783 t1 = tcg_const_tl(reglist);
12784 t2 = tcg_const_i32(ctx->mem_idx);
12785
12786 save_cpu_state(ctx, 1);
12787 switch (opc) {
12788 case LWM32:
12789 gen_helper_lwm(cpu_env, t0, t1, t2);
12790 break;
12791 case SWM32:
12792 gen_helper_swm(cpu_env, t0, t1, t2);
12793 break;
12794 #ifdef TARGET_MIPS64
12795 case LDM:
12796 gen_helper_ldm(cpu_env, t0, t1, t2);
12797 break;
12798 case SDM:
12799 gen_helper_sdm(cpu_env, t0, t1, t2);
12800 break;
12801 #endif
12802 }
12803 tcg_temp_free(t0);
12804 tcg_temp_free(t1);
12805 tcg_temp_free_i32(t2);
12806 }
12807
12808
12809 static void gen_pool16c_insn(DisasContext *ctx)
12810 {
12811 int rd = mmreg((ctx->opcode >> 3) & 0x7);
12812 int rs = mmreg(ctx->opcode & 0x7);
12813
12814 switch (((ctx->opcode) >> 4) & 0x3f) {
12815 case NOT16 + 0:
12816 case NOT16 + 1:
12817 case NOT16 + 2:
12818 case NOT16 + 3:
12819 gen_logic(ctx, OPC_NOR, rd, rs, 0);
12820 break;
12821 case XOR16 + 0:
12822 case XOR16 + 1:
12823 case XOR16 + 2:
12824 case XOR16 + 3:
12825 gen_logic(ctx, OPC_XOR, rd, rd, rs);
12826 break;
12827 case AND16 + 0:
12828 case AND16 + 1:
12829 case AND16 + 2:
12830 case AND16 + 3:
12831 gen_logic(ctx, OPC_AND, rd, rd, rs);
12832 break;
12833 case OR16 + 0:
12834 case OR16 + 1:
12835 case OR16 + 2:
12836 case OR16 + 3:
12837 gen_logic(ctx, OPC_OR, rd, rd, rs);
12838 break;
12839 case LWM16 + 0:
12840 case LWM16 + 1:
12841 case LWM16 + 2:
12842 case LWM16 + 3:
12843 {
12844 static const int lwm_convert[] = { 0x11, 0x12, 0x13, 0x14 };
12845 int offset = ZIMM(ctx->opcode, 0, 4);
12846
12847 gen_ldst_multiple(ctx, LWM32, lwm_convert[(ctx->opcode >> 4) & 0x3],
12848 29, offset << 2);
12849 }
12850 break;
12851 case SWM16 + 0:
12852 case SWM16 + 1:
12853 case SWM16 + 2:
12854 case SWM16 + 3:
12855 {
12856 static const int swm_convert[] = { 0x11, 0x12, 0x13, 0x14 };
12857 int offset = ZIMM(ctx->opcode, 0, 4);
12858
12859 gen_ldst_multiple(ctx, SWM32, swm_convert[(ctx->opcode >> 4) & 0x3],
12860 29, offset << 2);
12861 }
12862 break;
12863 case JR16 + 0:
12864 case JR16 + 1:
12865 {
12866 int reg = ctx->opcode & 0x1f;
12867
12868 gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 4);
12869 }
12870 break;
12871 case JRC16 + 0:
12872 case JRC16 + 1:
12873 {
12874 int reg = ctx->opcode & 0x1f;
12875 gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 0);
12876 /* Let normal delay slot handling in our caller take us
12877 to the branch target. */
12878 }
12879 break;
12880 case JALR16 + 0:
12881 case JALR16 + 1:
12882 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 4);
12883 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
12884 break;
12885 case JALR16S + 0:
12886 case JALR16S + 1:
12887 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 2);
12888 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
12889 break;
12890 case MFHI16 + 0:
12891 case MFHI16 + 1:
12892 gen_HILO(ctx, OPC_MFHI, 0, uMIPS_RS5(ctx->opcode));
12893 break;
12894 case MFLO16 + 0:
12895 case MFLO16 + 1:
12896 gen_HILO(ctx, OPC_MFLO, 0, uMIPS_RS5(ctx->opcode));
12897 break;
12898 case BREAK16:
12899 generate_exception_end(ctx, EXCP_BREAK);
12900 break;
12901 case SDBBP16:
12902 if (is_uhi(extract32(ctx->opcode, 0, 4))) {
12903 gen_helper_do_semihosting(cpu_env);
12904 } else {
12905 /* XXX: not clear which exception should be raised
12906 * when in debug mode...
12907 */
12908 check_insn(ctx, ISA_MIPS32);
12909 generate_exception_end(ctx, EXCP_DBp);
12910 }
12911 break;
12912 case JRADDIUSP + 0:
12913 case JRADDIUSP + 1:
12914 {
12915 int imm = ZIMM(ctx->opcode, 0, 5);
12916 gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0);
12917 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2);
12918 /* Let normal delay slot handling in our caller take us
12919 to the branch target. */
12920 }
12921 break;
12922 default:
12923 generate_exception_end(ctx, EXCP_RI);
12924 break;
12925 }
12926 }
12927
12928 static inline void gen_movep(DisasContext *ctx, int enc_dest, int enc_rt,
12929 int enc_rs)
12930 {
12931 int rd, rs, re, rt;
12932 static const int rd_enc[] = { 5, 5, 6, 4, 4, 4, 4, 4 };
12933 static const int re_enc[] = { 6, 7, 7, 21, 22, 5, 6, 7 };
12934 static const int rs_rt_enc[] = { 0, 17, 2, 3, 16, 18, 19, 20 };
12935 rd = rd_enc[enc_dest];
12936 re = re_enc[enc_dest];
12937 rs = rs_rt_enc[enc_rs];
12938 rt = rs_rt_enc[enc_rt];
12939 if (rs) {
12940 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
12941 } else {
12942 tcg_gen_movi_tl(cpu_gpr[rd], 0);
12943 }
12944 if (rt) {
12945 tcg_gen_mov_tl(cpu_gpr[re], cpu_gpr[rt]);
12946 } else {
12947 tcg_gen_movi_tl(cpu_gpr[re], 0);
12948 }
12949 }
12950
12951 static void gen_pool16c_r6_insn(DisasContext *ctx)
12952 {
12953 int rt = mmreg((ctx->opcode >> 7) & 0x7);
12954 int rs = mmreg((ctx->opcode >> 4) & 0x7);
12955
12956 switch (ctx->opcode & 0xf) {
12957 case R6_NOT16:
12958 gen_logic(ctx, OPC_NOR, rt, rs, 0);
12959 break;
12960 case R6_AND16:
12961 gen_logic(ctx, OPC_AND, rt, rt, rs);
12962 break;
12963 case R6_LWM16:
12964 {
12965 int lwm_converted = 0x11 + extract32(ctx->opcode, 8, 2);
12966 int offset = extract32(ctx->opcode, 4, 4);
12967 gen_ldst_multiple(ctx, LWM32, lwm_converted, 29, offset << 2);
12968 }
12969 break;
12970 case R6_JRC16: /* JRCADDIUSP */
12971 if ((ctx->opcode >> 4) & 1) {
12972 /* JRCADDIUSP */
12973 int imm = extract32(ctx->opcode, 5, 5);
12974 gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0);
12975 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2);
12976 } else {
12977 /* JRC16 */
12978 int rs = extract32(ctx->opcode, 5, 5);
12979 gen_compute_branch(ctx, OPC_JR, 2, rs, 0, 0, 0);
12980 }
12981 break;
12982 case MOVEP ... MOVEP_07:
12983 case MOVEP_0C ... MOVEP_0F:
12984 {
12985 int enc_dest = uMIPS_RD(ctx->opcode);
12986 int enc_rt = uMIPS_RS2(ctx->opcode);
12987 int enc_rs = (ctx->opcode & 3) | ((ctx->opcode >> 1) & 4);
12988 gen_movep(ctx, enc_dest, enc_rt, enc_rs);
12989 }
12990 break;
12991 case R6_XOR16:
12992 gen_logic(ctx, OPC_XOR, rt, rt, rs);
12993 break;
12994 case R6_OR16:
12995 gen_logic(ctx, OPC_OR, rt, rt, rs);
12996 break;
12997 case R6_SWM16:
12998 {
12999 int swm_converted = 0x11 + extract32(ctx->opcode, 8, 2);
13000 int offset = extract32(ctx->opcode, 4, 4);
13001 gen_ldst_multiple(ctx, SWM32, swm_converted, 29, offset << 2);
13002 }
13003 break;
13004 case JALRC16: /* BREAK16, SDBBP16 */
13005 switch (ctx->opcode & 0x3f) {
13006 case JALRC16:
13007 case JALRC16 + 0x20:
13008 /* JALRC16 */
13009 gen_compute_branch(ctx, OPC_JALR, 2, (ctx->opcode >> 5) & 0x1f,
13010 31, 0, 0);
13011 break;
13012 case R6_BREAK16:
13013 /* BREAK16 */
13014 generate_exception(ctx, EXCP_BREAK);
13015 break;
13016 case R6_SDBBP16:
13017 /* SDBBP16 */
13018 if (is_uhi(extract32(ctx->opcode, 6, 4))) {
13019 gen_helper_do_semihosting(cpu_env);
13020 } else {
13021 if (ctx->hflags & MIPS_HFLAG_SBRI) {
13022 generate_exception(ctx, EXCP_RI);
13023 } else {
13024 generate_exception(ctx, EXCP_DBp);
13025 }
13026 }
13027 break;
13028 }
13029 break;
13030 default:
13031 generate_exception(ctx, EXCP_RI);
13032 break;
13033 }
13034 }
13035
13036 static void gen_ldxs (DisasContext *ctx, int base, int index, int rd)
13037 {
13038 TCGv t0 = tcg_temp_new();
13039 TCGv t1 = tcg_temp_new();
13040
13041 gen_load_gpr(t0, base);
13042
13043 if (index != 0) {
13044 gen_load_gpr(t1, index);
13045 tcg_gen_shli_tl(t1, t1, 2);
13046 gen_op_addr_add(ctx, t0, t1, t0);
13047 }
13048
13049 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
13050 gen_store_gpr(t1, rd);
13051
13052 tcg_temp_free(t0);
13053 tcg_temp_free(t1);
13054 }
13055
13056 static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
13057 int base, int16_t offset)
13058 {
13059 TCGv t0, t1;
13060
13061 if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) {
13062 generate_exception_end(ctx, EXCP_RI);
13063 return;
13064 }
13065
13066 t0 = tcg_temp_new();
13067 t1 = tcg_temp_new();
13068
13069 gen_base_offset_addr(ctx, t0, base, offset);
13070
13071 switch (opc) {
13072 case LWP:
13073 if (rd == base) {
13074 generate_exception_end(ctx, EXCP_RI);
13075 return;
13076 }
13077 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
13078 gen_store_gpr(t1, rd);
13079 tcg_gen_movi_tl(t1, 4);
13080 gen_op_addr_add(ctx, t0, t0, t1);
13081 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
13082 gen_store_gpr(t1, rd+1);
13083 break;
13084 case SWP:
13085 gen_load_gpr(t1, rd);
13086 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
13087 tcg_gen_movi_tl(t1, 4);
13088 gen_op_addr_add(ctx, t0, t0, t1);
13089 gen_load_gpr(t1, rd+1);
13090 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
13091 break;
13092 #ifdef TARGET_MIPS64
13093 case LDP:
13094 if (rd == base) {
13095 generate_exception_end(ctx, EXCP_RI);
13096 return;
13097 }
13098 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ);
13099 gen_store_gpr(t1, rd);
13100 tcg_gen_movi_tl(t1, 8);
13101 gen_op_addr_add(ctx, t0, t0, t1);
13102 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ);
13103 gen_store_gpr(t1, rd+1);
13104 break;
13105 case SDP:
13106 gen_load_gpr(t1, rd);
13107 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
13108 tcg_gen_movi_tl(t1, 8);
13109 gen_op_addr_add(ctx, t0, t0, t1);
13110 gen_load_gpr(t1, rd+1);
13111 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
13112 break;
13113 #endif
13114 }
13115 tcg_temp_free(t0);
13116 tcg_temp_free(t1);
13117 }
13118
13119 static void gen_sync(int stype)
13120 {
13121 TCGBar tcg_mo = TCG_BAR_SC;
13122
13123 switch (stype) {
13124 case 0x4: /* SYNC_WMB */
13125 tcg_mo |= TCG_MO_ST_ST;
13126 break;
13127 case 0x10: /* SYNC_MB */
13128 tcg_mo |= TCG_MO_ALL;
13129 break;
13130 case 0x11: /* SYNC_ACQUIRE */
13131 tcg_mo |= TCG_MO_LD_LD | TCG_MO_LD_ST;
13132 break;
13133 case 0x12: /* SYNC_RELEASE */
13134 tcg_mo |= TCG_MO_ST_ST | TCG_MO_LD_ST;
13135 break;
13136 case 0x13: /* SYNC_RMB */
13137 tcg_mo |= TCG_MO_LD_LD;
13138 break;
13139 default:
13140 tcg_mo |= TCG_MO_ALL;
13141 break;
13142 }
13143
13144 tcg_gen_mb(tcg_mo);
13145 }
13146
13147 static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
13148 {
13149 int extension = (ctx->opcode >> 6) & 0x3f;
13150 int minor = (ctx->opcode >> 12) & 0xf;
13151 uint32_t mips32_op;
13152
13153 switch (extension) {
13154 case TEQ:
13155 mips32_op = OPC_TEQ;
13156 goto do_trap;
13157 case TGE:
13158 mips32_op = OPC_TGE;
13159 goto do_trap;
13160 case TGEU:
13161 mips32_op = OPC_TGEU;
13162 goto do_trap;
13163 case TLT:
13164 mips32_op = OPC_TLT;
13165 goto do_trap;
13166 case TLTU:
13167 mips32_op = OPC_TLTU;
13168 goto do_trap;
13169 case TNE:
13170 mips32_op = OPC_TNE;
13171 do_trap:
13172 gen_trap(ctx, mips32_op, rs, rt, -1);
13173 break;
13174 #ifndef CONFIG_USER_ONLY
13175 case MFC0:
13176 case MFC0 + 32:
13177 check_cp0_enabled(ctx);
13178 if (rt == 0) {
13179 /* Treat as NOP. */
13180 break;
13181 }
13182 gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7);
13183 break;
13184 case MTC0:
13185 case MTC0 + 32:
13186 check_cp0_enabled(ctx);
13187 {
13188 TCGv t0 = tcg_temp_new();
13189
13190 gen_load_gpr(t0, rt);
13191 gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7);
13192 tcg_temp_free(t0);
13193 }
13194 break;
13195 #endif
13196 case 0x2a:
13197 switch (minor & 3) {
13198 case MADD_ACC:
13199 gen_muldiv(ctx, OPC_MADD, (ctx->opcode >> 14) & 3, rs, rt);
13200 break;
13201 case MADDU_ACC:
13202 gen_muldiv(ctx, OPC_MADDU, (ctx->opcode >> 14) & 3, rs, rt);
13203 break;
13204 case MSUB_ACC:
13205 gen_muldiv(ctx, OPC_MSUB, (ctx->opcode >> 14) & 3, rs, rt);
13206 break;
13207 case MSUBU_ACC:
13208 gen_muldiv(ctx, OPC_MSUBU, (ctx->opcode >> 14) & 3, rs, rt);
13209 break;
13210 default:
13211 goto pool32axf_invalid;
13212 }
13213 break;
13214 case 0x32:
13215 switch (minor & 3) {
13216 case MULT_ACC:
13217 gen_muldiv(ctx, OPC_MULT, (ctx->opcode >> 14) & 3, rs, rt);
13218 break;
13219 case MULTU_ACC:
13220 gen_muldiv(ctx, OPC_MULTU, (ctx->opcode >> 14) & 3, rs, rt);
13221 break;
13222 default:
13223 goto pool32axf_invalid;
13224 }
13225 break;
13226 case 0x2c:
13227 switch (minor) {
13228 case BITSWAP:
13229 check_insn(ctx, ISA_MIPS32R6);
13230 gen_bitswap(ctx, OPC_BITSWAP, rs, rt);
13231 break;
13232 case SEB:
13233 gen_bshfl(ctx, OPC_SEB, rs, rt);
13234 break;
13235 case SEH:
13236 gen_bshfl(ctx, OPC_SEH, rs, rt);
13237 break;
13238 case CLO:
13239 mips32_op = OPC_CLO;
13240 goto do_cl;
13241 case CLZ:
13242 mips32_op = OPC_CLZ;
13243 do_cl:
13244 check_insn(ctx, ISA_MIPS32);
13245 gen_cl(ctx, mips32_op, rt, rs);
13246 break;
13247 case RDHWR:
13248 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13249 gen_rdhwr(ctx, rt, rs, 0);
13250 break;
13251 case WSBH:
13252 gen_bshfl(ctx, OPC_WSBH, rs, rt);
13253 break;
13254 case MULT:
13255 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13256 mips32_op = OPC_MULT;
13257 goto do_mul;
13258 case MULTU:
13259 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13260 mips32_op = OPC_MULTU;
13261 goto do_mul;
13262 case DIV:
13263 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13264 mips32_op = OPC_DIV;
13265 goto do_div;
13266 case DIVU:
13267 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13268 mips32_op = OPC_DIVU;
13269 goto do_div;
13270 do_div:
13271 check_insn(ctx, ISA_MIPS32);
13272 gen_muldiv(ctx, mips32_op, 0, rs, rt);
13273 break;
13274 case MADD:
13275 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13276 mips32_op = OPC_MADD;
13277 goto do_mul;
13278 case MADDU:
13279 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13280 mips32_op = OPC_MADDU;
13281 goto do_mul;
13282 case MSUB:
13283 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13284 mips32_op = OPC_MSUB;
13285 goto do_mul;
13286 case MSUBU:
13287 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13288 mips32_op = OPC_MSUBU;
13289 do_mul:
13290 check_insn(ctx, ISA_MIPS32);
13291 gen_muldiv(ctx, mips32_op, 0, rs, rt);
13292 break;
13293 default:
13294 goto pool32axf_invalid;
13295 }
13296 break;
13297 case 0x34:
13298 switch (minor) {
13299 case MFC2:
13300 case MTC2:
13301 case MFHC2:
13302 case MTHC2:
13303 case CFC2:
13304 case CTC2:
13305 generate_exception_err(ctx, EXCP_CpU, 2);
13306 break;
13307 default:
13308 goto pool32axf_invalid;
13309 }
13310 break;
13311 case 0x3c:
13312 switch (minor) {
13313 case JALR: /* JALRC */
13314 case JALR_HB: /* JALRC_HB */
13315 if (ctx->insn_flags & ISA_MIPS32R6) {
13316 /* JALRC, JALRC_HB */
13317 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0);
13318 } else {
13319 /* JALR, JALR_HB */
13320 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 4);
13321 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
13322 }
13323 break;
13324 case JALRS:
13325 case JALRS_HB:
13326 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13327 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2);
13328 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
13329 break;
13330 default:
13331 goto pool32axf_invalid;
13332 }
13333 break;
13334 case 0x05:
13335 switch (minor) {
13336 case RDPGPR:
13337 check_cp0_enabled(ctx);
13338 check_insn(ctx, ISA_MIPS32R2);
13339 gen_load_srsgpr(rs, rt);
13340 break;
13341 case WRPGPR:
13342 check_cp0_enabled(ctx);
13343 check_insn(ctx, ISA_MIPS32R2);
13344 gen_store_srsgpr(rs, rt);
13345 break;
13346 default:
13347 goto pool32axf_invalid;
13348 }
13349 break;
13350 #ifndef CONFIG_USER_ONLY
13351 case 0x0d:
13352 switch (minor) {
13353 case TLBP:
13354 mips32_op = OPC_TLBP;
13355 goto do_cp0;
13356 case TLBR:
13357 mips32_op = OPC_TLBR;
13358 goto do_cp0;
13359 case TLBWI:
13360 mips32_op = OPC_TLBWI;
13361 goto do_cp0;
13362 case TLBWR:
13363 mips32_op = OPC_TLBWR;
13364 goto do_cp0;
13365 case TLBINV:
13366 mips32_op = OPC_TLBINV;
13367 goto do_cp0;
13368 case TLBINVF:
13369 mips32_op = OPC_TLBINVF;
13370 goto do_cp0;
13371 case WAIT:
13372 mips32_op = OPC_WAIT;
13373 goto do_cp0;
13374 case DERET:
13375 mips32_op = OPC_DERET;
13376 goto do_cp0;
13377 case ERET:
13378 mips32_op = OPC_ERET;
13379 do_cp0:
13380 gen_cp0(env, ctx, mips32_op, rt, rs);
13381 break;
13382 default:
13383 goto pool32axf_invalid;
13384 }
13385 break;
13386 case 0x1d:
13387 switch (minor) {
13388 case DI:
13389 check_cp0_enabled(ctx);
13390 {
13391 TCGv t0 = tcg_temp_new();
13392
13393 save_cpu_state(ctx, 1);
13394 gen_helper_di(t0, cpu_env);
13395 gen_store_gpr(t0, rs);
13396 /* Stop translation as we may have switched the execution mode */
13397 ctx->bstate = BS_STOP;
13398 tcg_temp_free(t0);
13399 }
13400 break;
13401 case EI:
13402 check_cp0_enabled(ctx);
13403 {
13404 TCGv t0 = tcg_temp_new();
13405
13406 save_cpu_state(ctx, 1);
13407 gen_helper_ei(t0, cpu_env);
13408 gen_store_gpr(t0, rs);
13409 /* Stop translation as we may have switched the execution mode */
13410 ctx->bstate = BS_STOP;
13411 tcg_temp_free(t0);
13412 }
13413 break;
13414 default:
13415 goto pool32axf_invalid;
13416 }
13417 break;
13418 #endif
13419 case 0x2d:
13420 switch (minor) {
13421 case SYNC:
13422 gen_sync(extract32(ctx->opcode, 16, 5));
13423 break;
13424 case SYSCALL:
13425 generate_exception_end(ctx, EXCP_SYSCALL);
13426 break;
13427 case SDBBP:
13428 if (is_uhi(extract32(ctx->opcode, 16, 10))) {
13429 gen_helper_do_semihosting(cpu_env);
13430 } else {
13431 check_insn(ctx, ISA_MIPS32);
13432 if (ctx->hflags & MIPS_HFLAG_SBRI) {
13433 generate_exception_end(ctx, EXCP_RI);
13434 } else {
13435 generate_exception_end(ctx, EXCP_DBp);
13436 }
13437 }
13438 break;
13439 default:
13440 goto pool32axf_invalid;
13441 }
13442 break;
13443 case 0x01:
13444 switch (minor & 3) {
13445 case MFHI_ACC:
13446 gen_HILO(ctx, OPC_MFHI, minor >> 2, rs);
13447 break;
13448 case MFLO_ACC:
13449 gen_HILO(ctx, OPC_MFLO, minor >> 2, rs);
13450 break;
13451 case MTHI_ACC:
13452 gen_HILO(ctx, OPC_MTHI, minor >> 2, rs);
13453 break;
13454 case MTLO_ACC:
13455 gen_HILO(ctx, OPC_MTLO, minor >> 2, rs);
13456 break;
13457 default:
13458 goto pool32axf_invalid;
13459 }
13460 break;
13461 case 0x35:
13462 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13463 switch (minor) {
13464 case MFHI32:
13465 gen_HILO(ctx, OPC_MFHI, 0, rs);
13466 break;
13467 case MFLO32:
13468 gen_HILO(ctx, OPC_MFLO, 0, rs);
13469 break;
13470 case MTHI32:
13471 gen_HILO(ctx, OPC_MTHI, 0, rs);
13472 break;
13473 case MTLO32:
13474 gen_HILO(ctx, OPC_MTLO, 0, rs);
13475 break;
13476 default:
13477 goto pool32axf_invalid;
13478 }
13479 break;
13480 default:
13481 pool32axf_invalid:
13482 MIPS_INVAL("pool32axf");
13483 generate_exception_end(ctx, EXCP_RI);
13484 break;
13485 }
13486 }
13487
13488 /* Values for microMIPS fmt field. Variable-width, depending on which
13489 formats the instruction supports. */
13490
13491 enum {
13492 FMT_SD_S = 0,
13493 FMT_SD_D = 1,
13494
13495 FMT_SDPS_S = 0,
13496 FMT_SDPS_D = 1,
13497 FMT_SDPS_PS = 2,
13498
13499 FMT_SWL_S = 0,
13500 FMT_SWL_W = 1,
13501 FMT_SWL_L = 2,
13502
13503 FMT_DWL_D = 0,
13504 FMT_DWL_W = 1,
13505 FMT_DWL_L = 2
13506 };
13507
13508 static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
13509 {
13510 int extension = (ctx->opcode >> 6) & 0x3ff;
13511 uint32_t mips32_op;
13512
13513 #define FLOAT_1BIT_FMT(opc, fmt) (fmt << 8) | opc
13514 #define FLOAT_2BIT_FMT(opc, fmt) (fmt << 7) | opc
13515 #define COND_FLOAT_MOV(opc, cond) (cond << 7) | opc
13516
13517 switch (extension) {
13518 case FLOAT_1BIT_FMT(CFC1, 0):
13519 mips32_op = OPC_CFC1;
13520 goto do_cp1;
13521 case FLOAT_1BIT_FMT(CTC1, 0):
13522 mips32_op = OPC_CTC1;
13523 goto do_cp1;
13524 case FLOAT_1BIT_FMT(MFC1, 0):
13525 mips32_op = OPC_MFC1;
13526 goto do_cp1;
13527 case FLOAT_1BIT_FMT(MTC1, 0):
13528 mips32_op = OPC_MTC1;
13529 goto do_cp1;
13530 case FLOAT_1BIT_FMT(MFHC1, 0):
13531 mips32_op = OPC_MFHC1;
13532 goto do_cp1;
13533 case FLOAT_1BIT_FMT(MTHC1, 0):
13534 mips32_op = OPC_MTHC1;
13535 do_cp1:
13536 gen_cp1(ctx, mips32_op, rt, rs);
13537 break;
13538
13539 /* Reciprocal square root */
13540 case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_S):
13541 mips32_op = OPC_RSQRT_S;
13542 goto do_unaryfp;
13543 case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_D):
13544 mips32_op = OPC_RSQRT_D;
13545 goto do_unaryfp;
13546
13547 /* Square root */
13548 case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_S):
13549 mips32_op = OPC_SQRT_S;
13550 goto do_unaryfp;
13551 case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_D):
13552 mips32_op = OPC_SQRT_D;
13553 goto do_unaryfp;
13554
13555 /* Reciprocal */
13556 case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_S):
13557 mips32_op = OPC_RECIP_S;
13558 goto do_unaryfp;
13559 case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_D):
13560 mips32_op = OPC_RECIP_D;
13561 goto do_unaryfp;
13562
13563 /* Floor */
13564 case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_S):
13565 mips32_op = OPC_FLOOR_L_S;
13566 goto do_unaryfp;
13567 case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_D):
13568 mips32_op = OPC_FLOOR_L_D;
13569 goto do_unaryfp;
13570 case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_S):
13571 mips32_op = OPC_FLOOR_W_S;
13572 goto do_unaryfp;
13573 case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_D):
13574 mips32_op = OPC_FLOOR_W_D;
13575 goto do_unaryfp;
13576
13577 /* Ceiling */
13578 case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_S):
13579 mips32_op = OPC_CEIL_L_S;
13580 goto do_unaryfp;
13581 case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_D):
13582 mips32_op = OPC_CEIL_L_D;
13583 goto do_unaryfp;
13584 case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_S):
13585 mips32_op = OPC_CEIL_W_S;
13586 goto do_unaryfp;
13587 case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_D):
13588 mips32_op = OPC_CEIL_W_D;
13589 goto do_unaryfp;
13590
13591 /* Truncation */
13592 case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_S):
13593 mips32_op = OPC_TRUNC_L_S;
13594 goto do_unaryfp;
13595 case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_D):
13596 mips32_op = OPC_TRUNC_L_D;
13597 goto do_unaryfp;
13598 case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_S):
13599 mips32_op = OPC_TRUNC_W_S;
13600 goto do_unaryfp;
13601 case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_D):
13602 mips32_op = OPC_TRUNC_W_D;
13603 goto do_unaryfp;
13604
13605 /* Round */
13606 case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_S):
13607 mips32_op = OPC_ROUND_L_S;
13608 goto do_unaryfp;
13609 case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_D):
13610 mips32_op = OPC_ROUND_L_D;
13611 goto do_unaryfp;
13612 case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_S):
13613 mips32_op = OPC_ROUND_W_S;
13614 goto do_unaryfp;
13615 case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_D):
13616 mips32_op = OPC_ROUND_W_D;
13617 goto do_unaryfp;
13618
13619 /* Integer to floating-point conversion */
13620 case FLOAT_1BIT_FMT(CVT_L, FMT_SD_S):
13621 mips32_op = OPC_CVT_L_S;
13622 goto do_unaryfp;
13623 case FLOAT_1BIT_FMT(CVT_L, FMT_SD_D):
13624 mips32_op = OPC_CVT_L_D;
13625 goto do_unaryfp;
13626 case FLOAT_1BIT_FMT(CVT_W, FMT_SD_S):
13627 mips32_op = OPC_CVT_W_S;
13628 goto do_unaryfp;
13629 case FLOAT_1BIT_FMT(CVT_W, FMT_SD_D):
13630 mips32_op = OPC_CVT_W_D;
13631 goto do_unaryfp;
13632
13633 /* Paired-foo conversions */
13634 case FLOAT_1BIT_FMT(CVT_S_PL, 0):
13635 mips32_op = OPC_CVT_S_PL;
13636 goto do_unaryfp;
13637 case FLOAT_1BIT_FMT(CVT_S_PU, 0):
13638 mips32_op = OPC_CVT_S_PU;
13639 goto do_unaryfp;
13640 case FLOAT_1BIT_FMT(CVT_PW_PS, 0):
13641 mips32_op = OPC_CVT_PW_PS;
13642 goto do_unaryfp;
13643 case FLOAT_1BIT_FMT(CVT_PS_PW, 0):
13644 mips32_op = OPC_CVT_PS_PW;
13645 goto do_unaryfp;
13646
13647 /* Floating-point moves */
13648 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_S):
13649 mips32_op = OPC_MOV_S;
13650 goto do_unaryfp;
13651 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_D):
13652 mips32_op = OPC_MOV_D;
13653 goto do_unaryfp;
13654 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_PS):
13655 mips32_op = OPC_MOV_PS;
13656 goto do_unaryfp;
13657
13658 /* Absolute value */
13659 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_S):
13660 mips32_op = OPC_ABS_S;
13661 goto do_unaryfp;
13662 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_D):
13663 mips32_op = OPC_ABS_D;
13664 goto do_unaryfp;
13665 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_PS):
13666 mips32_op = OPC_ABS_PS;
13667 goto do_unaryfp;
13668
13669 /* Negation */
13670 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_S):
13671 mips32_op = OPC_NEG_S;
13672 goto do_unaryfp;
13673 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_D):
13674 mips32_op = OPC_NEG_D;
13675 goto do_unaryfp;
13676 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_PS):
13677 mips32_op = OPC_NEG_PS;
13678 goto do_unaryfp;
13679
13680 /* Reciprocal square root step */
13681 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_S):
13682 mips32_op = OPC_RSQRT1_S;
13683 goto do_unaryfp;
13684 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_D):
13685 mips32_op = OPC_RSQRT1_D;
13686 goto do_unaryfp;
13687 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_PS):
13688 mips32_op = OPC_RSQRT1_PS;
13689 goto do_unaryfp;
13690
13691 /* Reciprocal step */
13692 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_S):
13693 mips32_op = OPC_RECIP1_S;
13694 goto do_unaryfp;
13695 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_D):
13696 mips32_op = OPC_RECIP1_S;
13697 goto do_unaryfp;
13698 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_PS):
13699 mips32_op = OPC_RECIP1_PS;
13700 goto do_unaryfp;
13701
13702 /* Conversions from double */
13703 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_S):
13704 mips32_op = OPC_CVT_D_S;
13705 goto do_unaryfp;
13706 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_W):
13707 mips32_op = OPC_CVT_D_W;
13708 goto do_unaryfp;
13709 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_L):
13710 mips32_op = OPC_CVT_D_L;
13711 goto do_unaryfp;
13712
13713 /* Conversions from single */
13714 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_D):
13715 mips32_op = OPC_CVT_S_D;
13716 goto do_unaryfp;
13717 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_W):
13718 mips32_op = OPC_CVT_S_W;
13719 goto do_unaryfp;
13720 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_L):
13721 mips32_op = OPC_CVT_S_L;
13722 do_unaryfp:
13723 gen_farith(ctx, mips32_op, -1, rs, rt, 0);
13724 break;
13725
13726 /* Conditional moves on floating-point codes */
13727 case COND_FLOAT_MOV(MOVT, 0):
13728 case COND_FLOAT_MOV(MOVT, 1):
13729 case COND_FLOAT_MOV(MOVT, 2):
13730 case COND_FLOAT_MOV(MOVT, 3):
13731 case COND_FLOAT_MOV(MOVT, 4):
13732 case COND_FLOAT_MOV(MOVT, 5):
13733 case COND_FLOAT_MOV(MOVT, 6):
13734 case COND_FLOAT_MOV(MOVT, 7):
13735 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13736 gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1);
13737 break;
13738 case COND_FLOAT_MOV(MOVF, 0):
13739 case COND_FLOAT_MOV(MOVF, 1):
13740 case COND_FLOAT_MOV(MOVF, 2):
13741 case COND_FLOAT_MOV(MOVF, 3):
13742 case COND_FLOAT_MOV(MOVF, 4):
13743 case COND_FLOAT_MOV(MOVF, 5):
13744 case COND_FLOAT_MOV(MOVF, 6):
13745 case COND_FLOAT_MOV(MOVF, 7):
13746 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13747 gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0);
13748 break;
13749 default:
13750 MIPS_INVAL("pool32fxf");
13751 generate_exception_end(ctx, EXCP_RI);
13752 break;
13753 }
13754 }
13755
13756 static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
13757 {
13758 int32_t offset;
13759 uint16_t insn;
13760 int rt, rs, rd, rr;
13761 int16_t imm;
13762 uint32_t op, minor, mips32_op;
13763 uint32_t cond, fmt, cc;
13764
13765 insn = cpu_lduw_code(env, ctx->pc + 2);
13766 ctx->opcode = (ctx->opcode << 16) | insn;
13767
13768 rt = (ctx->opcode >> 21) & 0x1f;
13769 rs = (ctx->opcode >> 16) & 0x1f;
13770 rd = (ctx->opcode >> 11) & 0x1f;
13771 rr = (ctx->opcode >> 6) & 0x1f;
13772 imm = (int16_t) ctx->opcode;
13773
13774 op = (ctx->opcode >> 26) & 0x3f;
13775 switch (op) {
13776 case POOL32A:
13777 minor = ctx->opcode & 0x3f;
13778 switch (minor) {
13779 case 0x00:
13780 minor = (ctx->opcode >> 6) & 0xf;
13781 switch (minor) {
13782 case SLL32:
13783 mips32_op = OPC_SLL;
13784 goto do_shifti;
13785 case SRA:
13786 mips32_op = OPC_SRA;
13787 goto do_shifti;
13788 case SRL32:
13789 mips32_op = OPC_SRL;
13790 goto do_shifti;
13791 case ROTR:
13792 mips32_op = OPC_ROTR;
13793 do_shifti:
13794 gen_shift_imm(ctx, mips32_op, rt, rs, rd);
13795 break;
13796 case SELEQZ:
13797 check_insn(ctx, ISA_MIPS32R6);
13798 gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt);
13799 break;
13800 case SELNEZ:
13801 check_insn(ctx, ISA_MIPS32R6);
13802 gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt);
13803 break;
13804 case R6_RDHWR:
13805 check_insn(ctx, ISA_MIPS32R6);
13806 gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3));
13807 break;
13808 default:
13809 goto pool32a_invalid;
13810 }
13811 break;
13812 case 0x10:
13813 minor = (ctx->opcode >> 6) & 0xf;
13814 switch (minor) {
13815 /* Arithmetic */
13816 case ADD:
13817 mips32_op = OPC_ADD;
13818 goto do_arith;
13819 case ADDU32:
13820 mips32_op = OPC_ADDU;
13821 goto do_arith;
13822 case SUB:
13823 mips32_op = OPC_SUB;
13824 goto do_arith;
13825 case SUBU32:
13826 mips32_op = OPC_SUBU;
13827 goto do_arith;
13828 case MUL:
13829 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13830 mips32_op = OPC_MUL;
13831 do_arith:
13832 gen_arith(ctx, mips32_op, rd, rs, rt);
13833 break;
13834 /* Shifts */
13835 case SLLV:
13836 mips32_op = OPC_SLLV;
13837 goto do_shift;
13838 case SRLV:
13839 mips32_op = OPC_SRLV;
13840 goto do_shift;
13841 case SRAV:
13842 mips32_op = OPC_SRAV;
13843 goto do_shift;
13844 case ROTRV:
13845 mips32_op = OPC_ROTRV;
13846 do_shift:
13847 gen_shift(ctx, mips32_op, rd, rs, rt);
13848 break;
13849 /* Logical operations */
13850 case AND:
13851 mips32_op = OPC_AND;
13852 goto do_logic;
13853 case OR32:
13854 mips32_op = OPC_OR;
13855 goto do_logic;
13856 case NOR:
13857 mips32_op = OPC_NOR;
13858 goto do_logic;
13859 case XOR32:
13860 mips32_op = OPC_XOR;
13861 do_logic:
13862 gen_logic(ctx, mips32_op, rd, rs, rt);
13863 break;
13864 /* Set less than */
13865 case SLT:
13866 mips32_op = OPC_SLT;
13867 goto do_slt;
13868 case SLTU:
13869 mips32_op = OPC_SLTU;
13870 do_slt:
13871 gen_slt(ctx, mips32_op, rd, rs, rt);
13872 break;
13873 default:
13874 goto pool32a_invalid;
13875 }
13876 break;
13877 case 0x18:
13878 minor = (ctx->opcode >> 6) & 0xf;
13879 switch (minor) {
13880 /* Conditional moves */
13881 case MOVN: /* MUL */
13882 if (ctx->insn_flags & ISA_MIPS32R6) {
13883 /* MUL */
13884 gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt);
13885 } else {
13886 /* MOVN */
13887 gen_cond_move(ctx, OPC_MOVN, rd, rs, rt);
13888 }
13889 break;
13890 case MOVZ: /* MUH */
13891 if (ctx->insn_flags & ISA_MIPS32R6) {
13892 /* MUH */
13893 gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt);
13894 } else {
13895 /* MOVZ */
13896 gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt);
13897 }
13898 break;
13899 case MULU:
13900 check_insn(ctx, ISA_MIPS32R6);
13901 gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt);
13902 break;
13903 case MUHU:
13904 check_insn(ctx, ISA_MIPS32R6);
13905 gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt);
13906 break;
13907 case LWXS: /* DIV */
13908 if (ctx->insn_flags & ISA_MIPS32R6) {
13909 /* DIV */
13910 gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt);
13911 } else {
13912 /* LWXS */
13913 gen_ldxs(ctx, rs, rt, rd);
13914 }
13915 break;
13916 case MOD:
13917 check_insn(ctx, ISA_MIPS32R6);
13918 gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt);
13919 break;
13920 case R6_DIVU:
13921 check_insn(ctx, ISA_MIPS32R6);
13922 gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt);
13923 break;
13924 case MODU:
13925 check_insn(ctx, ISA_MIPS32R6);
13926 gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt);
13927 break;
13928 default:
13929 goto pool32a_invalid;
13930 }
13931 break;
13932 case INS:
13933 gen_bitops(ctx, OPC_INS, rt, rs, rr, rd);
13934 return;
13935 case LSA:
13936 check_insn(ctx, ISA_MIPS32R6);
13937 gen_lsa(ctx, OPC_LSA, rd, rs, rt,
13938 extract32(ctx->opcode, 9, 2));
13939 break;
13940 case ALIGN:
13941 check_insn(ctx, ISA_MIPS32R6);
13942 gen_align(ctx, OPC_ALIGN, rd, rs, rt,
13943 extract32(ctx->opcode, 9, 2));
13944 break;
13945 case EXT:
13946 gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd);
13947 return;
13948 case POOL32AXF:
13949 gen_pool32axf(env, ctx, rt, rs);
13950 break;
13951 case BREAK32:
13952 generate_exception_end(ctx, EXCP_BREAK);
13953 break;
13954 case SIGRIE:
13955 check_insn(ctx, ISA_MIPS32R6);
13956 generate_exception_end(ctx, EXCP_RI);
13957 break;
13958 default:
13959 pool32a_invalid:
13960 MIPS_INVAL("pool32a");
13961 generate_exception_end(ctx, EXCP_RI);
13962 break;
13963 }
13964 break;
13965 case POOL32B:
13966 minor = (ctx->opcode >> 12) & 0xf;
13967 switch (minor) {
13968 case CACHE:
13969 check_cp0_enabled(ctx);
13970 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
13971 gen_cache_operation(ctx, rt, rs, imm);
13972 }
13973 break;
13974 case LWC2:
13975 case SWC2:
13976 /* COP2: Not implemented. */
13977 generate_exception_err(ctx, EXCP_CpU, 2);
13978 break;
13979 #ifdef TARGET_MIPS64
13980 case LDP:
13981 case SDP:
13982 check_insn(ctx, ISA_MIPS3);
13983 check_mips_64(ctx);
13984 /* Fallthrough */
13985 #endif
13986 case LWP:
13987 case SWP:
13988 gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
13989 break;
13990 #ifdef TARGET_MIPS64
13991 case LDM:
13992 case SDM:
13993 check_insn(ctx, ISA_MIPS3);
13994 check_mips_64(ctx);
13995 /* Fallthrough */
13996 #endif
13997 case LWM32:
13998 case SWM32:
13999 gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
14000 break;
14001 default:
14002 MIPS_INVAL("pool32b");
14003 generate_exception_end(ctx, EXCP_RI);
14004 break;
14005 }
14006 break;
14007 case POOL32F:
14008 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
14009 minor = ctx->opcode & 0x3f;
14010 check_cp1_enabled(ctx);
14011 switch (minor) {
14012 case ALNV_PS:
14013 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14014 mips32_op = OPC_ALNV_PS;
14015 goto do_madd;
14016 case MADD_S:
14017 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14018 mips32_op = OPC_MADD_S;
14019 goto do_madd;
14020 case MADD_D:
14021 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14022 mips32_op = OPC_MADD_D;
14023 goto do_madd;
14024 case MADD_PS:
14025 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14026 mips32_op = OPC_MADD_PS;
14027 goto do_madd;
14028 case MSUB_S:
14029 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14030 mips32_op = OPC_MSUB_S;
14031 goto do_madd;
14032 case MSUB_D:
14033 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14034 mips32_op = OPC_MSUB_D;
14035 goto do_madd;
14036 case MSUB_PS:
14037 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14038 mips32_op = OPC_MSUB_PS;
14039 goto do_madd;
14040 case NMADD_S:
14041 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14042 mips32_op = OPC_NMADD_S;
14043 goto do_madd;
14044 case NMADD_D:
14045 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14046 mips32_op = OPC_NMADD_D;
14047 goto do_madd;
14048 case NMADD_PS:
14049 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14050 mips32_op = OPC_NMADD_PS;
14051 goto do_madd;
14052 case NMSUB_S:
14053 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14054 mips32_op = OPC_NMSUB_S;
14055 goto do_madd;
14056 case NMSUB_D:
14057 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14058 mips32_op = OPC_NMSUB_D;
14059 goto do_madd;
14060 case NMSUB_PS:
14061 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14062 mips32_op = OPC_NMSUB_PS;
14063 do_madd:
14064 gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt);
14065 break;
14066 case CABS_COND_FMT:
14067 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14068 cond = (ctx->opcode >> 6) & 0xf;
14069 cc = (ctx->opcode >> 13) & 0x7;
14070 fmt = (ctx->opcode >> 10) & 0x3;
14071 switch (fmt) {
14072 case 0x0:
14073 gen_cmpabs_s(ctx, cond, rt, rs, cc);
14074 break;
14075 case 0x1:
14076 gen_cmpabs_d(ctx, cond, rt, rs, cc);
14077 break;
14078 case 0x2:
14079 gen_cmpabs_ps(ctx, cond, rt, rs, cc);
14080 break;
14081 default:
14082 goto pool32f_invalid;
14083 }
14084 break;
14085 case C_COND_FMT:
14086 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14087 cond = (ctx->opcode >> 6) & 0xf;
14088 cc = (ctx->opcode >> 13) & 0x7;
14089 fmt = (ctx->opcode >> 10) & 0x3;
14090 switch (fmt) {
14091 case 0x0:
14092 gen_cmp_s(ctx, cond, rt, rs, cc);
14093 break;
14094 case 0x1:
14095 gen_cmp_d(ctx, cond, rt, rs, cc);
14096 break;
14097 case 0x2:
14098 gen_cmp_ps(ctx, cond, rt, rs, cc);
14099 break;
14100 default:
14101 goto pool32f_invalid;
14102 }
14103 break;
14104 case CMP_CONDN_S:
14105 check_insn(ctx, ISA_MIPS32R6);
14106 gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
14107 break;
14108 case CMP_CONDN_D:
14109 check_insn(ctx, ISA_MIPS32R6);
14110 gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
14111 break;
14112 case POOL32FXF:
14113 gen_pool32fxf(ctx, rt, rs);
14114 break;
14115 case 0x00:
14116 /* PLL foo */
14117 switch ((ctx->opcode >> 6) & 0x7) {
14118 case PLL_PS:
14119 mips32_op = OPC_PLL_PS;
14120 goto do_ps;
14121 case PLU_PS:
14122 mips32_op = OPC_PLU_PS;
14123 goto do_ps;
14124 case PUL_PS:
14125 mips32_op = OPC_PUL_PS;
14126 goto do_ps;
14127 case PUU_PS:
14128 mips32_op = OPC_PUU_PS;
14129 goto do_ps;
14130 case CVT_PS_S:
14131 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14132 mips32_op = OPC_CVT_PS_S;
14133 do_ps:
14134 gen_farith(ctx, mips32_op, rt, rs, rd, 0);
14135 break;
14136 default:
14137 goto pool32f_invalid;
14138 }
14139 break;
14140 case MIN_FMT:
14141 check_insn(ctx, ISA_MIPS32R6);
14142 switch ((ctx->opcode >> 9) & 0x3) {
14143 case FMT_SDPS_S:
14144 gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
14145 break;
14146 case FMT_SDPS_D:
14147 gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);
14148 break;
14149 default:
14150 goto pool32f_invalid;
14151 }
14152 break;
14153 case 0x08:
14154 /* [LS][WDU]XC1 */
14155 switch ((ctx->opcode >> 6) & 0x7) {
14156 case LWXC1:
14157 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14158 mips32_op = OPC_LWXC1;
14159 goto do_ldst_cp1;
14160 case SWXC1:
14161 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14162 mips32_op = OPC_SWXC1;
14163 goto do_ldst_cp1;
14164 case LDXC1:
14165 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14166 mips32_op = OPC_LDXC1;
14167 goto do_ldst_cp1;
14168 case SDXC1:
14169 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14170 mips32_op = OPC_SDXC1;
14171 goto do_ldst_cp1;
14172 case LUXC1:
14173 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14174 mips32_op = OPC_LUXC1;
14175 goto do_ldst_cp1;
14176 case SUXC1:
14177 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14178 mips32_op = OPC_SUXC1;
14179 do_ldst_cp1:
14180 gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs);
14181 break;
14182 default:
14183 goto pool32f_invalid;
14184 }
14185 break;
14186 case MAX_FMT:
14187 check_insn(ctx, ISA_MIPS32R6);
14188 switch ((ctx->opcode >> 9) & 0x3) {
14189 case FMT_SDPS_S:
14190 gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
14191 break;
14192 case FMT_SDPS_D:
14193 gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);
14194 break;
14195 default:
14196 goto pool32f_invalid;
14197 }
14198 break;
14199 case 0x18:
14200 /* 3D insns */
14201 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14202 fmt = (ctx->opcode >> 9) & 0x3;
14203 switch ((ctx->opcode >> 6) & 0x7) {
14204 case RSQRT2_FMT:
14205 switch (fmt) {
14206 case FMT_SDPS_S:
14207 mips32_op = OPC_RSQRT2_S;
14208 goto do_3d;
14209 case FMT_SDPS_D:
14210 mips32_op = OPC_RSQRT2_D;
14211 goto do_3d;
14212 case FMT_SDPS_PS:
14213 mips32_op = OPC_RSQRT2_PS;
14214 goto do_3d;
14215 default:
14216 goto pool32f_invalid;
14217 }
14218 break;
14219 case RECIP2_FMT:
14220 switch (fmt) {
14221 case FMT_SDPS_S:
14222 mips32_op = OPC_RECIP2_S;
14223 goto do_3d;
14224 case FMT_SDPS_D:
14225 mips32_op = OPC_RECIP2_D;
14226 goto do_3d;
14227 case FMT_SDPS_PS:
14228 mips32_op = OPC_RECIP2_PS;
14229 goto do_3d;
14230 default:
14231 goto pool32f_invalid;
14232 }
14233 break;
14234 case ADDR_PS:
14235 mips32_op = OPC_ADDR_PS;
14236 goto do_3d;
14237 case MULR_PS:
14238 mips32_op = OPC_MULR_PS;
14239 do_3d:
14240 gen_farith(ctx, mips32_op, rt, rs, rd, 0);
14241 break;
14242 default:
14243 goto pool32f_invalid;
14244 }
14245 break;
14246 case 0x20:
14247 /* MOV[FT].fmt, PREFX, RINT.fmt, CLASS.fmt*/
14248 cc = (ctx->opcode >> 13) & 0x7;
14249 fmt = (ctx->opcode >> 9) & 0x3;
14250 switch ((ctx->opcode >> 6) & 0x7) {
14251 case MOVF_FMT: /* RINT_FMT */
14252 if (ctx->insn_flags & ISA_MIPS32R6) {
14253 /* RINT_FMT */
14254 switch (fmt) {
14255 case FMT_SDPS_S:
14256 gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);
14257 break;
14258 case FMT_SDPS_D:
14259 gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);
14260 break;
14261 default:
14262 goto pool32f_invalid;
14263 }
14264 } else {
14265 /* MOVF_FMT */
14266 switch (fmt) {
14267 case FMT_SDPS_S:
14268 gen_movcf_s(ctx, rs, rt, cc, 0);
14269 break;
14270 case FMT_SDPS_D:
14271 gen_movcf_d(ctx, rs, rt, cc, 0);
14272 break;
14273 case FMT_SDPS_PS:
14274 check_ps(ctx);
14275 gen_movcf_ps(ctx, rs, rt, cc, 0);
14276 break;
14277 default:
14278 goto pool32f_invalid;
14279 }
14280 }
14281 break;
14282 case MOVT_FMT: /* CLASS_FMT */
14283 if (ctx->insn_flags & ISA_MIPS32R6) {
14284 /* CLASS_FMT */
14285 switch (fmt) {
14286 case FMT_SDPS_S:
14287 gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);
14288 break;
14289 case FMT_SDPS_D:
14290 gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);
14291 break;
14292 default:
14293 goto pool32f_invalid;
14294 }
14295 } else {
14296 /* MOVT_FMT */
14297 switch (fmt) {
14298 case FMT_SDPS_S:
14299 gen_movcf_s(ctx, rs, rt, cc, 1);
14300 break;
14301 case FMT_SDPS_D:
14302 gen_movcf_d(ctx, rs, rt, cc, 1);
14303 break;
14304 case FMT_SDPS_PS:
14305 check_ps(ctx);
14306 gen_movcf_ps(ctx, rs, rt, cc, 1);
14307 break;
14308 default:
14309 goto pool32f_invalid;
14310 }
14311 }
14312 break;
14313 case PREFX:
14314 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14315 break;
14316 default:
14317 goto pool32f_invalid;
14318 }
14319 break;
14320 #define FINSN_3ARG_SDPS(prfx) \
14321 switch ((ctx->opcode >> 8) & 0x3) { \
14322 case FMT_SDPS_S: \
14323 mips32_op = OPC_##prfx##_S; \
14324 goto do_fpop; \
14325 case FMT_SDPS_D: \
14326 mips32_op = OPC_##prfx##_D; \
14327 goto do_fpop; \
14328 case FMT_SDPS_PS: \
14329 check_ps(ctx); \
14330 mips32_op = OPC_##prfx##_PS; \
14331 goto do_fpop; \
14332 default: \
14333 goto pool32f_invalid; \
14334 }
14335 case MINA_FMT:
14336 check_insn(ctx, ISA_MIPS32R6);
14337 switch ((ctx->opcode >> 9) & 0x3) {
14338 case FMT_SDPS_S:
14339 gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
14340 break;
14341 case FMT_SDPS_D:
14342 gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);
14343 break;
14344 default:
14345 goto pool32f_invalid;
14346 }
14347 break;
14348 case MAXA_FMT:
14349 check_insn(ctx, ISA_MIPS32R6);
14350 switch ((ctx->opcode >> 9) & 0x3) {
14351 case FMT_SDPS_S:
14352 gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
14353 break;
14354 case FMT_SDPS_D:
14355 gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);
14356 break;
14357 default:
14358 goto pool32f_invalid;
14359 }
14360 break;
14361 case 0x30:
14362 /* regular FP ops */
14363 switch ((ctx->opcode >> 6) & 0x3) {
14364 case ADD_FMT:
14365 FINSN_3ARG_SDPS(ADD);
14366 break;
14367 case SUB_FMT:
14368 FINSN_3ARG_SDPS(SUB);
14369 break;
14370 case MUL_FMT:
14371 FINSN_3ARG_SDPS(MUL);
14372 break;
14373 case DIV_FMT:
14374 fmt = (ctx->opcode >> 8) & 0x3;
14375 if (fmt == 1) {
14376 mips32_op = OPC_DIV_D;
14377 } else if (fmt == 0) {
14378 mips32_op = OPC_DIV_S;
14379 } else {
14380 goto pool32f_invalid;
14381 }
14382 goto do_fpop;
14383 default:
14384 goto pool32f_invalid;
14385 }
14386 break;
14387 case 0x38:
14388 /* cmovs */
14389 switch ((ctx->opcode >> 6) & 0x7) {
14390 case MOVN_FMT: /* SELNEZ_FMT */
14391 if (ctx->insn_flags & ISA_MIPS32R6) {
14392 /* SELNEZ_FMT */
14393 switch ((ctx->opcode >> 9) & 0x3) {
14394 case FMT_SDPS_S:
14395 gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
14396 break;
14397 case FMT_SDPS_D:
14398 gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
14399 break;
14400 default:
14401 goto pool32f_invalid;
14402 }
14403 } else {
14404 /* MOVN_FMT */
14405 FINSN_3ARG_SDPS(MOVN);
14406 }
14407 break;
14408 case MOVN_FMT_04:
14409 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14410 FINSN_3ARG_SDPS(MOVN);
14411 break;
14412 case MOVZ_FMT: /* SELEQZ_FMT */
14413 if (ctx->insn_flags & ISA_MIPS32R6) {
14414 /* SELEQZ_FMT */
14415 switch ((ctx->opcode >> 9) & 0x3) {
14416 case FMT_SDPS_S:
14417 gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
14418 break;
14419 case FMT_SDPS_D:
14420 gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
14421 break;
14422 default:
14423 goto pool32f_invalid;
14424 }
14425 } else {
14426 /* MOVZ_FMT */
14427 FINSN_3ARG_SDPS(MOVZ);
14428 }
14429 break;
14430 case MOVZ_FMT_05:
14431 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14432 FINSN_3ARG_SDPS(MOVZ);
14433 break;
14434 case SEL_FMT:
14435 check_insn(ctx, ISA_MIPS32R6);
14436 switch ((ctx->opcode >> 9) & 0x3) {
14437 case FMT_SDPS_S:
14438 gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
14439 break;
14440 case FMT_SDPS_D:
14441 gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);
14442 break;
14443 default:
14444 goto pool32f_invalid;
14445 }
14446 break;
14447 case MADDF_FMT:
14448 check_insn(ctx, ISA_MIPS32R6);
14449 switch ((ctx->opcode >> 9) & 0x3) {
14450 case FMT_SDPS_S:
14451 mips32_op = OPC_MADDF_S;
14452 goto do_fpop;
14453 case FMT_SDPS_D:
14454 mips32_op = OPC_MADDF_D;
14455 goto do_fpop;
14456 default:
14457 goto pool32f_invalid;
14458 }
14459 break;
14460 case MSUBF_FMT:
14461 check_insn(ctx, ISA_MIPS32R6);
14462 switch ((ctx->opcode >> 9) & 0x3) {
14463 case FMT_SDPS_S:
14464 mips32_op = OPC_MSUBF_S;
14465 goto do_fpop;
14466 case FMT_SDPS_D:
14467 mips32_op = OPC_MSUBF_D;
14468 goto do_fpop;
14469 default:
14470 goto pool32f_invalid;
14471 }
14472 break;
14473 default:
14474 goto pool32f_invalid;
14475 }
14476 break;
14477 do_fpop:
14478 gen_farith(ctx, mips32_op, rt, rs, rd, 0);
14479 break;
14480 default:
14481 pool32f_invalid:
14482 MIPS_INVAL("pool32f");
14483 generate_exception_end(ctx, EXCP_RI);
14484 break;
14485 }
14486 } else {
14487 generate_exception_err(ctx, EXCP_CpU, 1);
14488 }
14489 break;
14490 case POOL32I:
14491 minor = (ctx->opcode >> 21) & 0x1f;
14492 switch (minor) {
14493 case BLTZ:
14494 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14495 gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4);
14496 break;
14497 case BLTZAL:
14498 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14499 gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4);
14500 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14501 break;
14502 case BLTZALS:
14503 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14504 gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2);
14505 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14506 break;
14507 case BGEZ:
14508 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14509 gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4);
14510 break;
14511 case BGEZAL:
14512 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14513 gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4);
14514 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14515 break;
14516 case BGEZALS:
14517 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14518 gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2);
14519 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14520 break;
14521 case BLEZ:
14522 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14523 gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4);
14524 break;
14525 case BGTZ:
14526 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14527 gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4);
14528 break;
14529
14530 /* Traps */
14531 case TLTI: /* BC1EQZC */
14532 if (ctx->insn_flags & ISA_MIPS32R6) {
14533 /* BC1EQZC */
14534 check_cp1_enabled(ctx);
14535 gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0);
14536 } else {
14537 /* TLTI */
14538 mips32_op = OPC_TLTI;
14539 goto do_trapi;
14540 }
14541 break;
14542 case TGEI: /* BC1NEZC */
14543 if (ctx->insn_flags & ISA_MIPS32R6) {
14544 /* BC1NEZC */
14545 check_cp1_enabled(ctx);
14546 gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0);
14547 } else {
14548 /* TGEI */
14549 mips32_op = OPC_TGEI;
14550 goto do_trapi;
14551 }
14552 break;
14553 case TLTIU:
14554 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14555 mips32_op = OPC_TLTIU;
14556 goto do_trapi;
14557 case TGEIU:
14558 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14559 mips32_op = OPC_TGEIU;
14560 goto do_trapi;
14561 case TNEI: /* SYNCI */
14562 if (ctx->insn_flags & ISA_MIPS32R6) {
14563 /* SYNCI */
14564 /* Break the TB to be able to sync copied instructions
14565 immediately */
14566 ctx->bstate = BS_STOP;
14567 } else {
14568 /* TNEI */
14569 mips32_op = OPC_TNEI;
14570 goto do_trapi;
14571 }
14572 break;
14573 case TEQI:
14574 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14575 mips32_op = OPC_TEQI;
14576 do_trapi:
14577 gen_trap(ctx, mips32_op, rs, -1, imm);
14578 break;
14579
14580 case BNEZC:
14581 case BEQZC:
14582 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14583 gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ,
14584 4, rs, 0, imm << 1, 0);
14585 /* Compact branches don't have a delay slot, so just let
14586 the normal delay slot handling take us to the branch
14587 target. */
14588 break;
14589 case LUI:
14590 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14591 gen_logic_imm(ctx, OPC_LUI, rs, 0, imm);
14592 break;
14593 case SYNCI:
14594 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14595 /* Break the TB to be able to sync copied instructions
14596 immediately */
14597 ctx->bstate = BS_STOP;
14598 break;
14599 case BC2F:
14600 case BC2T:
14601 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14602 /* COP2: Not implemented. */
14603 generate_exception_err(ctx, EXCP_CpU, 2);
14604 break;
14605 case BC1F:
14606 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14607 mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_BC1F;
14608 goto do_cp1branch;
14609 case BC1T:
14610 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14611 mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_BC1T;
14612 goto do_cp1branch;
14613 case BC1ANY4F:
14614 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14615 mips32_op = OPC_BC1FANY4;
14616 goto do_cp1mips3d;
14617 case BC1ANY4T:
14618 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14619 mips32_op = OPC_BC1TANY4;
14620 do_cp1mips3d:
14621 check_cop1x(ctx);
14622 check_insn(ctx, ASE_MIPS3D);
14623 /* Fall through */
14624 do_cp1branch:
14625 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
14626 check_cp1_enabled(ctx);
14627 gen_compute_branch1(ctx, mips32_op,
14628 (ctx->opcode >> 18) & 0x7, imm << 1);
14629 } else {
14630 generate_exception_err(ctx, EXCP_CpU, 1);
14631 }
14632 break;
14633 case BPOSGE64:
14634 case BPOSGE32:
14635 /* MIPS DSP: not implemented */
14636 /* Fall through */
14637 default:
14638 MIPS_INVAL("pool32i");
14639 generate_exception_end(ctx, EXCP_RI);
14640 break;
14641 }
14642 break;
14643 case POOL32C:
14644 minor = (ctx->opcode >> 12) & 0xf;
14645 offset = sextract32(ctx->opcode, 0,
14646 (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12);
14647 switch (minor) {
14648 case LWL:
14649 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14650 mips32_op = OPC_LWL;
14651 goto do_ld_lr;
14652 case SWL:
14653 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14654 mips32_op = OPC_SWL;
14655 goto do_st_lr;
14656 case LWR:
14657 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14658 mips32_op = OPC_LWR;
14659 goto do_ld_lr;
14660 case SWR:
14661 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14662 mips32_op = OPC_SWR;
14663 goto do_st_lr;
14664 #if defined(TARGET_MIPS64)
14665 case LDL:
14666 check_insn(ctx, ISA_MIPS3);
14667 check_mips_64(ctx);
14668 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14669 mips32_op = OPC_LDL;
14670 goto do_ld_lr;
14671 case SDL:
14672 check_insn(ctx, ISA_MIPS3);
14673 check_mips_64(ctx);
14674 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14675 mips32_op = OPC_SDL;
14676 goto do_st_lr;
14677 case LDR:
14678 check_insn(ctx, ISA_MIPS3);
14679 check_mips_64(ctx);
14680 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14681 mips32_op = OPC_LDR;
14682 goto do_ld_lr;
14683 case SDR:
14684 check_insn(ctx, ISA_MIPS3);
14685 check_mips_64(ctx);
14686 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14687 mips32_op = OPC_SDR;
14688 goto do_st_lr;
14689 case LWU:
14690 check_insn(ctx, ISA_MIPS3);
14691 check_mips_64(ctx);
14692 mips32_op = OPC_LWU;
14693 goto do_ld_lr;
14694 case LLD:
14695 check_insn(ctx, ISA_MIPS3);
14696 check_mips_64(ctx);
14697 mips32_op = OPC_LLD;
14698 goto do_ld_lr;
14699 #endif
14700 case LL:
14701 mips32_op = OPC_LL;
14702 goto do_ld_lr;
14703 do_ld_lr:
14704 gen_ld(ctx, mips32_op, rt, rs, offset);
14705 break;
14706 do_st_lr:
14707 gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12));
14708 break;
14709 case SC:
14710 gen_st_cond(ctx, OPC_SC, rt, rs, offset);
14711 break;
14712 #if defined(TARGET_MIPS64)
14713 case SCD:
14714 check_insn(ctx, ISA_MIPS3);
14715 check_mips_64(ctx);
14716 gen_st_cond(ctx, OPC_SCD, rt, rs, offset);
14717 break;
14718 #endif
14719 case PREF:
14720 /* Treat as no-op */
14721 if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) {
14722 /* hint codes 24-31 are reserved and signal RI */
14723 generate_exception(ctx, EXCP_RI);
14724 }
14725 break;
14726 default:
14727 MIPS_INVAL("pool32c");
14728 generate_exception_end(ctx, EXCP_RI);
14729 break;
14730 }
14731 break;
14732 case ADDI32: /* AUI, LUI */
14733 if (ctx->insn_flags & ISA_MIPS32R6) {
14734 /* AUI, LUI */
14735 gen_logic_imm(ctx, OPC_LUI, rt, rs, imm);
14736 } else {
14737 /* ADDI32 */
14738 mips32_op = OPC_ADDI;
14739 goto do_addi;
14740 }
14741 break;
14742 case ADDIU32:
14743 mips32_op = OPC_ADDIU;
14744 do_addi:
14745 gen_arith_imm(ctx, mips32_op, rt, rs, imm);
14746 break;
14747
14748 /* Logical operations */
14749 case ORI32:
14750 mips32_op = OPC_ORI;
14751 goto do_logici;
14752 case XORI32:
14753 mips32_op = OPC_XORI;
14754 goto do_logici;
14755 case ANDI32:
14756 mips32_op = OPC_ANDI;
14757 do_logici:
14758 gen_logic_imm(ctx, mips32_op, rt, rs, imm);
14759 break;
14760
14761 /* Set less than immediate */
14762 case SLTI32:
14763 mips32_op = OPC_SLTI;
14764 goto do_slti;
14765 case SLTIU32:
14766 mips32_op = OPC_SLTIU;
14767 do_slti:
14768 gen_slt_imm(ctx, mips32_op, rt, rs, imm);
14769 break;
14770 case JALX32:
14771 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14772 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
14773 gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4);
14774 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14775 break;
14776 case JALS32: /* BOVC, BEQC, BEQZALC */
14777 if (ctx->insn_flags & ISA_MIPS32R6) {
14778 if (rs >= rt) {
14779 /* BOVC */
14780 mips32_op = OPC_BOVC;
14781 } else if (rs < rt && rs == 0) {
14782 /* BEQZALC */
14783 mips32_op = OPC_BEQZALC;
14784 } else {
14785 /* BEQC */
14786 mips32_op = OPC_BEQC;
14787 }
14788 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
14789 } else {
14790 /* JALS32 */
14791 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 1;
14792 gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, offset, 2);
14793 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14794 }
14795 break;
14796 case BEQ32: /* BC */
14797 if (ctx->insn_flags & ISA_MIPS32R6) {
14798 /* BC */
14799 gen_compute_compact_branch(ctx, OPC_BC, 0, 0,
14800 sextract32(ctx->opcode << 1, 0, 27));
14801 } else {
14802 /* BEQ32 */
14803 gen_compute_branch(ctx, OPC_BEQ, 4, rt, rs, imm << 1, 4);
14804 }
14805 break;
14806 case BNE32: /* BALC */
14807 if (ctx->insn_flags & ISA_MIPS32R6) {
14808 /* BALC */
14809 gen_compute_compact_branch(ctx, OPC_BALC, 0, 0,
14810 sextract32(ctx->opcode << 1, 0, 27));
14811 } else {
14812 /* BNE32 */
14813 gen_compute_branch(ctx, OPC_BNE, 4, rt, rs, imm << 1, 4);
14814 }
14815 break;
14816 case J32: /* BGTZC, BLTZC, BLTC */
14817 if (ctx->insn_flags & ISA_MIPS32R6) {
14818 if (rs == 0 && rt != 0) {
14819 /* BGTZC */
14820 mips32_op = OPC_BGTZC;
14821 } else if (rs != 0 && rt != 0 && rs == rt) {
14822 /* BLTZC */
14823 mips32_op = OPC_BLTZC;
14824 } else {
14825 /* BLTC */
14826 mips32_op = OPC_BLTC;
14827 }
14828 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
14829 } else {
14830 /* J32 */
14831 gen_compute_branch(ctx, OPC_J, 4, rt, rs,
14832 (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4);
14833 }
14834 break;
14835 case JAL32: /* BLEZC, BGEZC, BGEC */
14836 if (ctx->insn_flags & ISA_MIPS32R6) {
14837 if (rs == 0 && rt != 0) {
14838 /* BLEZC */
14839 mips32_op = OPC_BLEZC;
14840 } else if (rs != 0 && rt != 0 && rs == rt) {
14841 /* BGEZC */
14842 mips32_op = OPC_BGEZC;
14843 } else {
14844 /* BGEC */
14845 mips32_op = OPC_BGEC;
14846 }
14847 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
14848 } else {
14849 /* JAL32 */
14850 gen_compute_branch(ctx, OPC_JAL, 4, rt, rs,
14851 (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4);
14852 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14853 }
14854 break;
14855 /* Floating point (COP1) */
14856 case LWC132:
14857 mips32_op = OPC_LWC1;
14858 goto do_cop1;
14859 case LDC132:
14860 mips32_op = OPC_LDC1;
14861 goto do_cop1;
14862 case SWC132:
14863 mips32_op = OPC_SWC1;
14864 goto do_cop1;
14865 case SDC132:
14866 mips32_op = OPC_SDC1;
14867 do_cop1:
14868 gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
14869 break;
14870 case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
14871 if (ctx->insn_flags & ISA_MIPS32R6) {
14872 /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
14873 switch ((ctx->opcode >> 16) & 0x1f) {
14874 case ADDIUPC_00 ... ADDIUPC_07:
14875 gen_pcrel(ctx, OPC_ADDIUPC, ctx->pc & ~0x3, rt);
14876 break;
14877 case AUIPC:
14878 gen_pcrel(ctx, OPC_AUIPC, ctx->pc, rt);
14879 break;
14880 case ALUIPC:
14881 gen_pcrel(ctx, OPC_ALUIPC, ctx->pc, rt);
14882 break;
14883 case LWPC_08 ... LWPC_0F:
14884 gen_pcrel(ctx, R6_OPC_LWPC, ctx->pc & ~0x3, rt);
14885 break;
14886 default:
14887 generate_exception(ctx, EXCP_RI);
14888 break;
14889 }
14890 } else {
14891 /* ADDIUPC */
14892 int reg = mmreg(ZIMM(ctx->opcode, 23, 3));
14893 int offset = SIMM(ctx->opcode, 0, 23) << 2;
14894
14895 gen_addiupc(ctx, reg, offset, 0, 0);
14896 }
14897 break;
14898 case BNVC: /* BNEC, BNEZALC */
14899 check_insn(ctx, ISA_MIPS32R6);
14900 if (rs >= rt) {
14901 /* BNVC */
14902 mips32_op = OPC_BNVC;
14903 } else if (rs < rt && rs == 0) {
14904 /* BNEZALC */
14905 mips32_op = OPC_BNEZALC;
14906 } else {
14907 /* BNEC */
14908 mips32_op = OPC_BNEC;
14909 }
14910 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
14911 break;
14912 case R6_BNEZC: /* JIALC */
14913 check_insn(ctx, ISA_MIPS32R6);
14914 if (rt != 0) {
14915 /* BNEZC */
14916 gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0,
14917 sextract32(ctx->opcode << 1, 0, 22));
14918 } else {
14919 /* JIALC */
14920 gen_compute_compact_branch(ctx, OPC_JIALC, 0, rs, imm);
14921 }
14922 break;
14923 case R6_BEQZC: /* JIC */
14924 check_insn(ctx, ISA_MIPS32R6);
14925 if (rt != 0) {
14926 /* BEQZC */
14927 gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0,
14928 sextract32(ctx->opcode << 1, 0, 22));
14929 } else {
14930 /* JIC */
14931 gen_compute_compact_branch(ctx, OPC_JIC, 0, rs, imm);
14932 }
14933 break;
14934 case BLEZALC: /* BGEZALC, BGEUC */
14935 check_insn(ctx, ISA_MIPS32R6);
14936 if (rs == 0 && rt != 0) {
14937 /* BLEZALC */
14938 mips32_op = OPC_BLEZALC;
14939 } else if (rs != 0 && rt != 0 && rs == rt) {
14940 /* BGEZALC */
14941 mips32_op = OPC_BGEZALC;
14942 } else {
14943 /* BGEUC */
14944 mips32_op = OPC_BGEUC;
14945 }
14946 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
14947 break;
14948 case BGTZALC: /* BLTZALC, BLTUC */
14949 check_insn(ctx, ISA_MIPS32R6);
14950 if (rs == 0 && rt != 0) {
14951 /* BGTZALC */
14952 mips32_op = OPC_BGTZALC;
14953 } else if (rs != 0 && rt != 0 && rs == rt) {
14954 /* BLTZALC */
14955 mips32_op = OPC_BLTZALC;
14956 } else {
14957 /* BLTUC */
14958 mips32_op = OPC_BLTUC;
14959 }
14960 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
14961 break;
14962 /* Loads and stores */
14963 case LB32:
14964 mips32_op = OPC_LB;
14965 goto do_ld;
14966 case LBU32:
14967 mips32_op = OPC_LBU;
14968 goto do_ld;
14969 case LH32:
14970 mips32_op = OPC_LH;
14971 goto do_ld;
14972 case LHU32:
14973 mips32_op = OPC_LHU;
14974 goto do_ld;
14975 case LW32:
14976 mips32_op = OPC_LW;
14977 goto do_ld;
14978 #ifdef TARGET_MIPS64
14979 case LD32:
14980 check_insn(ctx, ISA_MIPS3);
14981 check_mips_64(ctx);
14982 mips32_op = OPC_LD;
14983 goto do_ld;
14984 case SD32:
14985 check_insn(ctx, ISA_MIPS3);
14986 check_mips_64(ctx);
14987 mips32_op = OPC_SD;
14988 goto do_st;
14989 #endif
14990 case SB32:
14991 mips32_op = OPC_SB;
14992 goto do_st;
14993 case SH32:
14994 mips32_op = OPC_SH;
14995 goto do_st;
14996 case SW32:
14997 mips32_op = OPC_SW;
14998 goto do_st;
14999 do_ld:
15000 gen_ld(ctx, mips32_op, rt, rs, imm);
15001 break;
15002 do_st:
15003 gen_st(ctx, mips32_op, rt, rs, imm);
15004 break;
15005 default:
15006 generate_exception_end(ctx, EXCP_RI);
15007 break;
15008 }
15009 }
15010
15011 static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx)
15012 {
15013 uint32_t op;
15014
15015 /* make sure instructions are on a halfword boundary */
15016 if (ctx->pc & 0x1) {
15017 env->CP0_BadVAddr = ctx->pc;
15018 generate_exception_end(ctx, EXCP_AdEL);
15019 return 2;
15020 }
15021
15022 op = (ctx->opcode >> 10) & 0x3f;
15023 /* Enforce properly-sized instructions in a delay slot */
15024 if (ctx->hflags & MIPS_HFLAG_BDS_STRICT) {
15025 switch (op & 0x7) { /* MSB-3..MSB-5 */
15026 case 0:
15027 /* POOL32A, POOL32B, POOL32I, POOL32C */
15028 case 4:
15029 /* ADDI32, ADDIU32, ORI32, XORI32, SLTI32, SLTIU32, ANDI32, JALX32 */
15030 case 5:
15031 /* LBU32, LHU32, POOL32F, JALS32, BEQ32, BNE32, J32, JAL32 */
15032 case 6:
15033 /* SB32, SH32, ADDIUPC, SWC132, SDC132, SW32 */
15034 case 7:
15035 /* LB32, LH32, LWC132, LDC132, LW32 */
15036 if (ctx->hflags & MIPS_HFLAG_BDS16) {
15037 generate_exception_end(ctx, EXCP_RI);
15038 return 2;
15039 }
15040 break;
15041 case 1:
15042 /* POOL16A, POOL16B, POOL16C, LWGP16, POOL16F */
15043 case 2:
15044 /* LBU16, LHU16, LWSP16, LW16, SB16, SH16, SWSP16, SW16 */
15045 case 3:
15046 /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */
15047 if (ctx->hflags & MIPS_HFLAG_BDS32) {
15048 generate_exception_end(ctx, EXCP_RI);
15049 return 2;
15050 }
15051 break;
15052 }
15053 }
15054
15055 switch (op) {
15056 case POOL16A:
15057 {
15058 int rd = mmreg(uMIPS_RD(ctx->opcode));
15059 int rs1 = mmreg(uMIPS_RS1(ctx->opcode));
15060 int rs2 = mmreg(uMIPS_RS2(ctx->opcode));
15061 uint32_t opc = 0;
15062
15063 switch (ctx->opcode & 0x1) {
15064 case ADDU16:
15065 opc = OPC_ADDU;
15066 break;
15067 case SUBU16:
15068 opc = OPC_SUBU;
15069 break;
15070 }
15071 if (ctx->insn_flags & ISA_MIPS32R6) {
15072 /* In the Release 6 the register number location in
15073 * the instruction encoding has changed.
15074 */
15075 gen_arith(ctx, opc, rs1, rd, rs2);
15076 } else {
15077 gen_arith(ctx, opc, rd, rs1, rs2);
15078 }
15079 }
15080 break;
15081 case POOL16B:
15082 {
15083 int rd = mmreg(uMIPS_RD(ctx->opcode));
15084 int rs = mmreg(uMIPS_RS(ctx->opcode));
15085 int amount = (ctx->opcode >> 1) & 0x7;
15086 uint32_t opc = 0;
15087 amount = amount == 0 ? 8 : amount;
15088
15089 switch (ctx->opcode & 0x1) {
15090 case SLL16:
15091 opc = OPC_SLL;
15092 break;
15093 case SRL16:
15094 opc = OPC_SRL;
15095 break;
15096 }
15097
15098 gen_shift_imm(ctx, opc, rd, rs, amount);
15099 }
15100 break;
15101 case POOL16C:
15102 if (ctx->insn_flags & ISA_MIPS32R6) {
15103 gen_pool16c_r6_insn(ctx);
15104 } else {
15105 gen_pool16c_insn(ctx);
15106 }
15107 break;
15108 case LWGP16:
15109 {
15110 int rd = mmreg(uMIPS_RD(ctx->opcode));
15111 int rb = 28; /* GP */
15112 int16_t offset = SIMM(ctx->opcode, 0, 7) << 2;
15113
15114 gen_ld(ctx, OPC_LW, rd, rb, offset);
15115 }
15116 break;
15117 case POOL16F:
15118 check_insn_opc_removed(ctx, ISA_MIPS32R6);
15119 if (ctx->opcode & 1) {
15120 generate_exception_end(ctx, EXCP_RI);
15121 } else {
15122 /* MOVEP */
15123 int enc_dest = uMIPS_RD(ctx->opcode);
15124 int enc_rt = uMIPS_RS2(ctx->opcode);
15125 int enc_rs = uMIPS_RS1(ctx->opcode);
15126 gen_movep(ctx, enc_dest, enc_rt, enc_rs);
15127 }
15128 break;
15129 case LBU16:
15130 {
15131 int rd = mmreg(uMIPS_RD(ctx->opcode));
15132 int rb = mmreg(uMIPS_RS(ctx->opcode));
15133 int16_t offset = ZIMM(ctx->opcode, 0, 4);
15134 offset = (offset == 0xf ? -1 : offset);
15135
15136 gen_ld(ctx, OPC_LBU, rd, rb, offset);
15137 }
15138 break;
15139 case LHU16:
15140 {
15141 int rd = mmreg(uMIPS_RD(ctx->opcode));
15142 int rb = mmreg(uMIPS_RS(ctx->opcode));
15143 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1;
15144
15145 gen_ld(ctx, OPC_LHU, rd, rb, offset);
15146 }
15147 break;
15148 case LWSP16:
15149 {
15150 int rd = (ctx->opcode >> 5) & 0x1f;
15151 int rb = 29; /* SP */
15152 int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2;
15153
15154 gen_ld(ctx, OPC_LW, rd, rb, offset);
15155 }
15156 break;
15157 case LW16:
15158 {
15159 int rd = mmreg(uMIPS_RD(ctx->opcode));
15160 int rb = mmreg(uMIPS_RS(ctx->opcode));
15161 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2;
15162
15163 gen_ld(ctx, OPC_LW, rd, rb, offset);
15164 }
15165 break;
15166 case SB16:
15167 {
15168 int rd = mmreg2(uMIPS_RD(ctx->opcode));
15169 int rb = mmreg(uMIPS_RS(ctx->opcode));
15170 int16_t offset = ZIMM(ctx->opcode, 0, 4);
15171
15172 gen_st(ctx, OPC_SB, rd, rb, offset);
15173 }
15174 break;
15175 case SH16:
15176 {
15177 int rd = mmreg2(uMIPS_RD(ctx->opcode));
15178 int rb = mmreg(uMIPS_RS(ctx->opcode));
15179 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1;
15180
15181 gen_st(ctx, OPC_SH, rd, rb, offset);
15182 }
15183 break;
15184 case SWSP16:
15185 {
15186 int rd = (ctx->opcode >> 5) & 0x1f;
15187 int rb = 29; /* SP */
15188 int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2;
15189
15190 gen_st(ctx, OPC_SW, rd, rb, offset);
15191 }
15192 break;
15193 case SW16:
15194 {
15195 int rd = mmreg2(uMIPS_RD(ctx->opcode));
15196 int rb = mmreg(uMIPS_RS(ctx->opcode));
15197 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2;
15198
15199 gen_st(ctx, OPC_SW, rd, rb, offset);
15200 }
15201 break;
15202 case MOVE16:
15203 {
15204 int rd = uMIPS_RD5(ctx->opcode);
15205 int rs = uMIPS_RS5(ctx->opcode);
15206
15207 gen_arith(ctx, OPC_ADDU, rd, rs, 0);
15208 }
15209 break;
15210 case ANDI16:
15211 gen_andi16(ctx);
15212 break;
15213 case POOL16D:
15214 switch (ctx->opcode & 0x1) {
15215 case ADDIUS5:
15216 gen_addius5(ctx);
15217 break;
15218 case ADDIUSP:
15219 gen_addiusp(ctx);
15220 break;
15221 }
15222 break;
15223 case POOL16E:
15224 switch (ctx->opcode & 0x1) {
15225 case ADDIUR2:
15226 gen_addiur2(ctx);
15227 break;
15228 case ADDIUR1SP:
15229 gen_addiur1sp(ctx);
15230 break;
15231 }
15232 break;
15233 case B16: /* BC16 */
15234 gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0,
15235 sextract32(ctx->opcode, 0, 10) << 1,
15236 (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4);
15237 break;
15238 case BNEZ16: /* BNEZC16 */
15239 case BEQZ16: /* BEQZC16 */
15240 gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2,
15241 mmreg(uMIPS_RD(ctx->opcode)),
15242 0, sextract32(ctx->opcode, 0, 7) << 1,
15243 (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4);
15244
15245 break;
15246 case LI16:
15247 {
15248 int reg = mmreg(uMIPS_RD(ctx->opcode));
15249 int imm = ZIMM(ctx->opcode, 0, 7);
15250
15251 imm = (imm == 0x7f ? -1 : imm);
15252 tcg_gen_movi_tl(cpu_gpr[reg], imm);
15253 }
15254 break;
15255 case RES_29:
15256 case RES_31:
15257 case RES_39:
15258 generate_exception_end(ctx, EXCP_RI);
15259 break;
15260 default:
15261 decode_micromips32_opc(env, ctx);
15262 return 4;
15263 }
15264
15265 return 2;
15266 }
15267
15268 /* SmartMIPS extension to MIPS32 */
15269
15270 #if defined(TARGET_MIPS64)
15271
15272 /* MDMX extension to MIPS64 */
15273
15274 #endif
15275
15276 /* MIPSDSP functions. */
15277 static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc,
15278 int rd, int base, int offset)
15279 {
15280 TCGv t0;
15281
15282 check_dsp(ctx);
15283 t0 = tcg_temp_new();
15284
15285 if (base == 0) {
15286 gen_load_gpr(t0, offset);
15287 } else if (offset == 0) {
15288 gen_load_gpr(t0, base);
15289 } else {
15290 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]);
15291 }
15292
15293 switch (opc) {
15294 case OPC_LBUX:
15295 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
15296 gen_store_gpr(t0, rd);
15297 break;
15298 case OPC_LHX:
15299 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW);
15300 gen_store_gpr(t0, rd);
15301 break;
15302 case OPC_LWX:
15303 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
15304 gen_store_gpr(t0, rd);
15305 break;
15306 #if defined(TARGET_MIPS64)
15307 case OPC_LDX:
15308 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
15309 gen_store_gpr(t0, rd);
15310 break;
15311 #endif
15312 }
15313 tcg_temp_free(t0);
15314 }
15315
15316 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
15317 int ret, int v1, int v2)
15318 {
15319 TCGv v1_t;
15320 TCGv v2_t;
15321
15322 if (ret == 0) {
15323 /* Treat as NOP. */
15324 return;
15325 }
15326
15327 v1_t = tcg_temp_new();
15328 v2_t = tcg_temp_new();
15329
15330 gen_load_gpr(v1_t, v1);
15331 gen_load_gpr(v2_t, v2);
15332
15333 switch (op1) {
15334 /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
15335 case OPC_MULT_G_2E:
15336 check_dspr2(ctx);
15337 switch (op2) {
15338 case OPC_ADDUH_QB:
15339 gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t);
15340 break;
15341 case OPC_ADDUH_R_QB:
15342 gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t);
15343 break;
15344 case OPC_ADDQH_PH:
15345 gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t);
15346 break;
15347 case OPC_ADDQH_R_PH:
15348 gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
15349 break;
15350 case OPC_ADDQH_W:
15351 gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t);
15352 break;
15353 case OPC_ADDQH_R_W:
15354 gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t);
15355 break;
15356 case OPC_SUBUH_QB:
15357 gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t);
15358 break;
15359 case OPC_SUBUH_R_QB:
15360 gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t);
15361 break;
15362 case OPC_SUBQH_PH:
15363 gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t);
15364 break;
15365 case OPC_SUBQH_R_PH:
15366 gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
15367 break;
15368 case OPC_SUBQH_W:
15369 gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t);
15370 break;
15371 case OPC_SUBQH_R_W:
15372 gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t);
15373 break;
15374 }
15375 break;
15376 case OPC_ABSQ_S_PH_DSP:
15377 switch (op2) {
15378 case OPC_ABSQ_S_QB:
15379 check_dspr2(ctx);
15380 gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env);
15381 break;
15382 case OPC_ABSQ_S_PH:
15383 check_dsp(ctx);
15384 gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, cpu_env);
15385 break;
15386 case OPC_ABSQ_S_W:
15387 check_dsp(ctx);
15388 gen_helper_absq_s_w(cpu_gpr[ret], v2_t, cpu_env);
15389 break;
15390 case OPC_PRECEQ_W_PHL:
15391 check_dsp(ctx);
15392 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFF0000);
15393 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
15394 break;
15395 case OPC_PRECEQ_W_PHR:
15396 check_dsp(ctx);
15397 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0x0000FFFF);
15398 tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 16);
15399 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
15400 break;
15401 case OPC_PRECEQU_PH_QBL:
15402 check_dsp(ctx);
15403 gen_helper_precequ_ph_qbl(cpu_gpr[ret], v2_t);
15404 break;
15405 case OPC_PRECEQU_PH_QBR:
15406 check_dsp(ctx);
15407 gen_helper_precequ_ph_qbr(cpu_gpr[ret], v2_t);
15408 break;
15409 case OPC_PRECEQU_PH_QBLA:
15410 check_dsp(ctx);
15411 gen_helper_precequ_ph_qbla(cpu_gpr[ret], v2_t);
15412 break;
15413 case OPC_PRECEQU_PH_QBRA:
15414 check_dsp(ctx);
15415 gen_helper_precequ_ph_qbra(cpu_gpr[ret], v2_t);
15416 break;
15417 case OPC_PRECEU_PH_QBL:
15418 check_dsp(ctx);
15419 gen_helper_preceu_ph_qbl(cpu_gpr[ret], v2_t);
15420 break;
15421 case OPC_PRECEU_PH_QBR:
15422 check_dsp(ctx);
15423 gen_helper_preceu_ph_qbr(cpu_gpr[ret], v2_t);
15424 break;
15425 case OPC_PRECEU_PH_QBLA:
15426 check_dsp(ctx);
15427 gen_helper_preceu_ph_qbla(cpu_gpr[ret], v2_t);
15428 break;
15429 case OPC_PRECEU_PH_QBRA:
15430 check_dsp(ctx);
15431 gen_helper_preceu_ph_qbra(cpu_gpr[ret], v2_t);
15432 break;
15433 }
15434 break;
15435 case OPC_ADDU_QB_DSP:
15436 switch (op2) {
15437 case OPC_ADDQ_PH:
15438 check_dsp(ctx);
15439 gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15440 break;
15441 case OPC_ADDQ_S_PH:
15442 check_dsp(ctx);
15443 gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15444 break;
15445 case OPC_ADDQ_S_W:
15446 check_dsp(ctx);
15447 gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15448 break;
15449 case OPC_ADDU_QB:
15450 check_dsp(ctx);
15451 gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15452 break;
15453 case OPC_ADDU_S_QB:
15454 check_dsp(ctx);
15455 gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15456 break;
15457 case OPC_ADDU_PH:
15458 check_dspr2(ctx);
15459 gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15460 break;
15461 case OPC_ADDU_S_PH:
15462 check_dspr2(ctx);
15463 gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15464 break;
15465 case OPC_SUBQ_PH:
15466 check_dsp(ctx);
15467 gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15468 break;
15469 case OPC_SUBQ_S_PH:
15470 check_dsp(ctx);
15471 gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15472 break;
15473 case OPC_SUBQ_S_W:
15474 check_dsp(ctx);
15475 gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15476 break;
15477 case OPC_SUBU_QB:
15478 check_dsp(ctx);
15479 gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15480 break;
15481 case OPC_SUBU_S_QB:
15482 check_dsp(ctx);
15483 gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15484 break;
15485 case OPC_SUBU_PH:
15486 check_dspr2(ctx);
15487 gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15488 break;
15489 case OPC_SUBU_S_PH:
15490 check_dspr2(ctx);
15491 gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15492 break;
15493 case OPC_ADDSC:
15494 check_dsp(ctx);
15495 gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15496 break;
15497 case OPC_ADDWC:
15498 check_dsp(ctx);
15499 gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15500 break;
15501 case OPC_MODSUB:
15502 check_dsp(ctx);
15503 gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t);
15504 break;
15505 case OPC_RADDU_W_QB:
15506 check_dsp(ctx);
15507 gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t);
15508 break;
15509 }
15510 break;
15511 case OPC_CMPU_EQ_QB_DSP:
15512 switch (op2) {
15513 case OPC_PRECR_QB_PH:
15514 check_dspr2(ctx);
15515 gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t);
15516 break;
15517 case OPC_PRECRQ_QB_PH:
15518 check_dsp(ctx);
15519 gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t);
15520 break;
15521 case OPC_PRECR_SRA_PH_W:
15522 check_dspr2(ctx);
15523 {
15524 TCGv_i32 sa_t = tcg_const_i32(v2);
15525 gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t,
15526 cpu_gpr[ret]);
15527 tcg_temp_free_i32(sa_t);
15528 break;
15529 }
15530 case OPC_PRECR_SRA_R_PH_W:
15531 check_dspr2(ctx);
15532 {
15533 TCGv_i32 sa_t = tcg_const_i32(v2);
15534 gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t,
15535 cpu_gpr[ret]);
15536 tcg_temp_free_i32(sa_t);
15537 break;
15538 }
15539 case OPC_PRECRQ_PH_W:
15540 check_dsp(ctx);
15541 gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t);
15542 break;
15543 case OPC_PRECRQ_RS_PH_W:
15544 check_dsp(ctx);
15545 gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15546 break;
15547 case OPC_PRECRQU_S_QB_PH:
15548 check_dsp(ctx);
15549 gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15550 break;
15551 }
15552 break;
15553 #ifdef TARGET_MIPS64
15554 case OPC_ABSQ_S_QH_DSP:
15555 switch (op2) {
15556 case OPC_PRECEQ_L_PWL:
15557 check_dsp(ctx);
15558 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFFFFFF00000000ull);
15559 break;
15560 case OPC_PRECEQ_L_PWR:
15561 check_dsp(ctx);
15562 tcg_gen_shli_tl(cpu_gpr[ret], v2_t, 32);
15563 break;
15564 case OPC_PRECEQ_PW_QHL:
15565 check_dsp(ctx);
15566 gen_helper_preceq_pw_qhl(cpu_gpr[ret], v2_t);
15567 break;
15568 case OPC_PRECEQ_PW_QHR:
15569 check_dsp(ctx);
15570 gen_helper_preceq_pw_qhr(cpu_gpr[ret], v2_t);
15571 break;
15572 case OPC_PRECEQ_PW_QHLA:
15573 check_dsp(ctx);
15574 gen_helper_preceq_pw_qhla(cpu_gpr[ret], v2_t);
15575 break;
15576 case OPC_PRECEQ_PW_QHRA:
15577 check_dsp(ctx);
15578 gen_helper_preceq_pw_qhra(cpu_gpr[ret], v2_t);
15579 break;
15580 case OPC_PRECEQU_QH_OBL:
15581 check_dsp(ctx);
15582 gen_helper_precequ_qh_obl(cpu_gpr[ret], v2_t);
15583 break;
15584 case OPC_PRECEQU_QH_OBR:
15585 check_dsp(ctx);
15586 gen_helper_precequ_qh_obr(cpu_gpr[ret], v2_t);
15587 break;
15588 case OPC_PRECEQU_QH_OBLA:
15589 check_dsp(ctx);
15590 gen_helper_precequ_qh_obla(cpu_gpr[ret], v2_t);
15591 break;
15592 case OPC_PRECEQU_QH_OBRA:
15593 check_dsp(ctx);
15594 gen_helper_precequ_qh_obra(cpu_gpr[ret], v2_t);
15595 break;
15596 case OPC_PRECEU_QH_OBL:
15597 check_dsp(ctx);
15598 gen_helper_preceu_qh_obl(cpu_gpr[ret], v2_t);
15599 break;
15600 case OPC_PRECEU_QH_OBR:
15601 check_dsp(ctx);
15602 gen_helper_preceu_qh_obr(cpu_gpr[ret], v2_t);
15603 break;
15604 case OPC_PRECEU_QH_OBLA:
15605 check_dsp(ctx);
15606 gen_helper_preceu_qh_obla(cpu_gpr[ret], v2_t);
15607 break;
15608 case OPC_PRECEU_QH_OBRA:
15609 check_dsp(ctx);
15610 gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t);
15611 break;
15612 case OPC_ABSQ_S_OB:
15613 check_dspr2(ctx);
15614 gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env);
15615 break;
15616 case OPC_ABSQ_S_PW:
15617 check_dsp(ctx);
15618 gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, cpu_env);
15619 break;
15620 case OPC_ABSQ_S_QH:
15621 check_dsp(ctx);
15622 gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, cpu_env);
15623 break;
15624 }
15625 break;
15626 case OPC_ADDU_OB_DSP:
15627 switch (op2) {
15628 case OPC_RADDU_L_OB:
15629 check_dsp(ctx);
15630 gen_helper_raddu_l_ob(cpu_gpr[ret], v1_t);
15631 break;
15632 case OPC_SUBQ_PW:
15633 check_dsp(ctx);
15634 gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15635 break;
15636 case OPC_SUBQ_S_PW:
15637 check_dsp(ctx);
15638 gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15639 break;
15640 case OPC_SUBQ_QH:
15641 check_dsp(ctx);
15642 gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15643 break;
15644 case OPC_SUBQ_S_QH:
15645 check_dsp(ctx);
15646 gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15647 break;
15648 case OPC_SUBU_OB:
15649 check_dsp(ctx);
15650 gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15651 break;
15652 case OPC_SUBU_S_OB:
15653 check_dsp(ctx);
15654 gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15655 break;
15656 case OPC_SUBU_QH:
15657 check_dspr2(ctx);
15658 gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15659 break;
15660 case OPC_SUBU_S_QH:
15661 check_dspr2(ctx);
15662 gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15663 break;
15664 case OPC_SUBUH_OB:
15665 check_dspr2(ctx);
15666 gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t);
15667 break;
15668 case OPC_SUBUH_R_OB:
15669 check_dspr2(ctx);
15670 gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t);
15671 break;
15672 case OPC_ADDQ_PW:
15673 check_dsp(ctx);
15674 gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15675 break;
15676 case OPC_ADDQ_S_PW:
15677 check_dsp(ctx);
15678 gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15679 break;
15680 case OPC_ADDQ_QH:
15681 check_dsp(ctx);
15682 gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15683 break;
15684 case OPC_ADDQ_S_QH:
15685 check_dsp(ctx);
15686 gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15687 break;
15688 case OPC_ADDU_OB:
15689 check_dsp(ctx);
15690 gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15691 break;
15692 case OPC_ADDU_S_OB:
15693 check_dsp(ctx);
15694 gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15695 break;
15696 case OPC_ADDU_QH:
15697 check_dspr2(ctx);
15698 gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15699 break;
15700 case OPC_ADDU_S_QH:
15701 check_dspr2(ctx);
15702 gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15703 break;
15704 case OPC_ADDUH_OB:
15705 check_dspr2(ctx);
15706 gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t);
15707 break;
15708 case OPC_ADDUH_R_OB:
15709 check_dspr2(ctx);
15710 gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t);
15711 break;
15712 }
15713 break;
15714 case OPC_CMPU_EQ_OB_DSP:
15715 switch (op2) {
15716 case OPC_PRECR_OB_QH:
15717 check_dspr2(ctx);
15718 gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t);
15719 break;
15720 case OPC_PRECR_SRA_QH_PW:
15721 check_dspr2(ctx);
15722 {
15723 TCGv_i32 ret_t = tcg_const_i32(ret);
15724 gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t);
15725 tcg_temp_free_i32(ret_t);
15726 break;
15727 }
15728 case OPC_PRECR_SRA_R_QH_PW:
15729 check_dspr2(ctx);
15730 {
15731 TCGv_i32 sa_v = tcg_const_i32(ret);
15732 gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v);
15733 tcg_temp_free_i32(sa_v);
15734 break;
15735 }
15736 case OPC_PRECRQ_OB_QH:
15737 check_dsp(ctx);
15738 gen_helper_precrq_ob_qh(cpu_gpr[ret], v1_t, v2_t);
15739 break;
15740 case OPC_PRECRQ_PW_L:
15741 check_dsp(ctx);
15742 gen_helper_precrq_pw_l(cpu_gpr[ret], v1_t, v2_t);
15743 break;
15744 case OPC_PRECRQ_QH_PW:
15745 check_dsp(ctx);
15746 gen_helper_precrq_qh_pw(cpu_gpr[ret], v1_t, v2_t);
15747 break;
15748 case OPC_PRECRQ_RS_QH_PW:
15749 check_dsp(ctx);
15750 gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15751 break;
15752 case OPC_PRECRQU_S_OB_QH:
15753 check_dsp(ctx);
15754 gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15755 break;
15756 }
15757 break;
15758 #endif
15759 }
15760
15761 tcg_temp_free(v1_t);
15762 tcg_temp_free(v2_t);
15763 }
15764
15765 static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
15766 int ret, int v1, int v2)
15767 {
15768 uint32_t op2;
15769 TCGv t0;
15770 TCGv v1_t;
15771 TCGv v2_t;
15772
15773 if (ret == 0) {
15774 /* Treat as NOP. */
15775 return;
15776 }
15777
15778 t0 = tcg_temp_new();
15779 v1_t = tcg_temp_new();
15780 v2_t = tcg_temp_new();
15781
15782 tcg_gen_movi_tl(t0, v1);
15783 gen_load_gpr(v1_t, v1);
15784 gen_load_gpr(v2_t, v2);
15785
15786 switch (opc) {
15787 case OPC_SHLL_QB_DSP:
15788 {
15789 op2 = MASK_SHLL_QB(ctx->opcode);
15790 switch (op2) {
15791 case OPC_SHLL_QB:
15792 check_dsp(ctx);
15793 gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, cpu_env);
15794 break;
15795 case OPC_SHLLV_QB:
15796 check_dsp(ctx);
15797 gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15798 break;
15799 case OPC_SHLL_PH:
15800 check_dsp(ctx);
15801 gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
15802 break;
15803 case OPC_SHLLV_PH:
15804 check_dsp(ctx);
15805 gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15806 break;
15807 case OPC_SHLL_S_PH:
15808 check_dsp(ctx);
15809 gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
15810 break;
15811 case OPC_SHLLV_S_PH:
15812 check_dsp(ctx);
15813 gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15814 break;
15815 case OPC_SHLL_S_W:
15816 check_dsp(ctx);
15817 gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, cpu_env);
15818 break;
15819 case OPC_SHLLV_S_W:
15820 check_dsp(ctx);
15821 gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15822 break;
15823 case OPC_SHRL_QB:
15824 check_dsp(ctx);
15825 gen_helper_shrl_qb(cpu_gpr[ret], t0, v2_t);
15826 break;
15827 case OPC_SHRLV_QB:
15828 check_dsp(ctx);
15829 gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t);
15830 break;
15831 case OPC_SHRL_PH:
15832 check_dspr2(ctx);
15833 gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t);
15834 break;
15835 case OPC_SHRLV_PH:
15836 check_dspr2(ctx);
15837 gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t);
15838 break;
15839 case OPC_SHRA_QB:
15840 check_dspr2(ctx);
15841 gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t);
15842 break;
15843 case OPC_SHRA_R_QB:
15844 check_dspr2(ctx);
15845 gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t);
15846 break;
15847 case OPC_SHRAV_QB:
15848 check_dspr2(ctx);
15849 gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t);
15850 break;
15851 case OPC_SHRAV_R_QB:
15852 check_dspr2(ctx);
15853 gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t);
15854 break;
15855 case OPC_SHRA_PH:
15856 check_dsp(ctx);
15857 gen_helper_shra_ph(cpu_gpr[ret], t0, v2_t);
15858 break;
15859 case OPC_SHRA_R_PH:
15860 check_dsp(ctx);
15861 gen_helper_shra_r_ph(cpu_gpr[ret], t0, v2_t);
15862 break;
15863 case OPC_SHRAV_PH:
15864 check_dsp(ctx);
15865 gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t);
15866 break;
15867 case OPC_SHRAV_R_PH:
15868 check_dsp(ctx);
15869 gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t);
15870 break;
15871 case OPC_SHRA_R_W:
15872 check_dsp(ctx);
15873 gen_helper_shra_r_w(cpu_gpr[ret], t0, v2_t);
15874 break;
15875 case OPC_SHRAV_R_W:
15876 check_dsp(ctx);
15877 gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t);
15878 break;
15879 default: /* Invalid */
15880 MIPS_INVAL("MASK SHLL.QB");
15881 generate_exception_end(ctx, EXCP_RI);
15882 break;
15883 }
15884 break;
15885 }
15886 #ifdef TARGET_MIPS64
15887 case OPC_SHLL_OB_DSP:
15888 op2 = MASK_SHLL_OB(ctx->opcode);
15889 switch (op2) {
15890 case OPC_SHLL_PW:
15891 check_dsp(ctx);
15892 gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
15893 break;
15894 case OPC_SHLLV_PW:
15895 check_dsp(ctx);
15896 gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
15897 break;
15898 case OPC_SHLL_S_PW:
15899 check_dsp(ctx);
15900 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
15901 break;
15902 case OPC_SHLLV_S_PW:
15903 check_dsp(ctx);
15904 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
15905 break;
15906 case OPC_SHLL_OB:
15907 check_dsp(ctx);
15908 gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, cpu_env);
15909 break;
15910 case OPC_SHLLV_OB:
15911 check_dsp(ctx);
15912 gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, cpu_env);
15913 break;
15914 case OPC_SHLL_QH:
15915 check_dsp(ctx);
15916 gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
15917 break;
15918 case OPC_SHLLV_QH:
15919 check_dsp(ctx);
15920 gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
15921 break;
15922 case OPC_SHLL_S_QH:
15923 check_dsp(ctx);
15924 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
15925 break;
15926 case OPC_SHLLV_S_QH:
15927 check_dsp(ctx);
15928 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
15929 break;
15930 case OPC_SHRA_OB:
15931 check_dspr2(ctx);
15932 gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0);
15933 break;
15934 case OPC_SHRAV_OB:
15935 check_dspr2(ctx);
15936 gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t);
15937 break;
15938 case OPC_SHRA_R_OB:
15939 check_dspr2(ctx);
15940 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0);
15941 break;
15942 case OPC_SHRAV_R_OB:
15943 check_dspr2(ctx);
15944 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t);
15945 break;
15946 case OPC_SHRA_PW:
15947 check_dsp(ctx);
15948 gen_helper_shra_pw(cpu_gpr[ret], v2_t, t0);
15949 break;
15950 case OPC_SHRAV_PW:
15951 check_dsp(ctx);
15952 gen_helper_shra_pw(cpu_gpr[ret], v2_t, v1_t);
15953 break;
15954 case OPC_SHRA_R_PW:
15955 check_dsp(ctx);
15956 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, t0);
15957 break;
15958 case OPC_SHRAV_R_PW:
15959 check_dsp(ctx);
15960 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, v1_t);
15961 break;
15962 case OPC_SHRA_QH:
15963 check_dsp(ctx);
15964 gen_helper_shra_qh(cpu_gpr[ret], v2_t, t0);
15965 break;
15966 case OPC_SHRAV_QH:
15967 check_dsp(ctx);
15968 gen_helper_shra_qh(cpu_gpr[ret], v2_t, v1_t);
15969 break;
15970 case OPC_SHRA_R_QH:
15971 check_dsp(ctx);
15972 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, t0);
15973 break;
15974 case OPC_SHRAV_R_QH:
15975 check_dsp(ctx);
15976 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, v1_t);
15977 break;
15978 case OPC_SHRL_OB:
15979 check_dsp(ctx);
15980 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, t0);
15981 break;
15982 case OPC_SHRLV_OB:
15983 check_dsp(ctx);
15984 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t);
15985 break;
15986 case OPC_SHRL_QH:
15987 check_dspr2(ctx);
15988 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0);
15989 break;
15990 case OPC_SHRLV_QH:
15991 check_dspr2(ctx);
15992 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t);
15993 break;
15994 default: /* Invalid */
15995 MIPS_INVAL("MASK SHLL.OB");
15996 generate_exception_end(ctx, EXCP_RI);
15997 break;
15998 }
15999 break;
16000 #endif
16001 }
16002
16003 tcg_temp_free(t0);
16004 tcg_temp_free(v1_t);
16005 tcg_temp_free(v2_t);
16006 }
16007
16008 static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
16009 int ret, int v1, int v2, int check_ret)
16010 {
16011 TCGv_i32 t0;
16012 TCGv v1_t;
16013 TCGv v2_t;
16014
16015 if ((ret == 0) && (check_ret == 1)) {
16016 /* Treat as NOP. */
16017 return;
16018 }
16019
16020 t0 = tcg_temp_new_i32();
16021 v1_t = tcg_temp_new();
16022 v2_t = tcg_temp_new();
16023
16024 tcg_gen_movi_i32(t0, ret);
16025 gen_load_gpr(v1_t, v1);
16026 gen_load_gpr(v2_t, v2);
16027
16028 switch (op1) {
16029 /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
16030 * the same mask and op1. */
16031 case OPC_MULT_G_2E:
16032 check_dspr2(ctx);
16033 switch (op2) {
16034 case OPC_MUL_PH:
16035 gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16036 break;
16037 case OPC_MUL_S_PH:
16038 gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16039 break;
16040 case OPC_MULQ_S_W:
16041 gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16042 break;
16043 case OPC_MULQ_RS_W:
16044 gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16045 break;
16046 }
16047 break;
16048 case OPC_DPA_W_PH_DSP:
16049 switch (op2) {
16050 case OPC_DPAU_H_QBL:
16051 check_dsp(ctx);
16052 gen_helper_dpau_h_qbl(t0, v1_t, v2_t, cpu_env);
16053 break;
16054 case OPC_DPAU_H_QBR:
16055 check_dsp(ctx);
16056 gen_helper_dpau_h_qbr(t0, v1_t, v2_t, cpu_env);
16057 break;
16058 case OPC_DPSU_H_QBL:
16059 check_dsp(ctx);
16060 gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, cpu_env);
16061 break;
16062 case OPC_DPSU_H_QBR:
16063 check_dsp(ctx);
16064 gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, cpu_env);
16065 break;
16066 case OPC_DPA_W_PH:
16067 check_dspr2(ctx);
16068 gen_helper_dpa_w_ph(t0, v1_t, v2_t, cpu_env);
16069 break;
16070 case OPC_DPAX_W_PH:
16071 check_dspr2(ctx);
16072 gen_helper_dpax_w_ph(t0, v1_t, v2_t, cpu_env);
16073 break;
16074 case OPC_DPAQ_S_W_PH:
16075 check_dsp(ctx);
16076 gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
16077 break;
16078 case OPC_DPAQX_S_W_PH:
16079 check_dspr2(ctx);
16080 gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
16081 break;
16082 case OPC_DPAQX_SA_W_PH:
16083 check_dspr2(ctx);
16084 gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
16085 break;
16086 case OPC_DPS_W_PH:
16087 check_dspr2(ctx);
16088 gen_helper_dps_w_ph(t0, v1_t, v2_t, cpu_env);
16089 break;
16090 case OPC_DPSX_W_PH:
16091 check_dspr2(ctx);
16092 gen_helper_dpsx_w_ph(t0, v1_t, v2_t, cpu_env);
16093 break;
16094 case OPC_DPSQ_S_W_PH:
16095 check_dsp(ctx);
16096 gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, cpu_env);
16097 break;
16098 case OPC_DPSQX_S_W_PH:
16099 check_dspr2(ctx);
16100 gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
16101 break;
16102 case OPC_DPSQX_SA_W_PH:
16103 check_dspr2(ctx);
16104 gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
16105 break;
16106 case OPC_MULSAQ_S_W_PH:
16107 check_dsp(ctx);
16108 gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
16109 break;
16110 case OPC_DPAQ_SA_L_W:
16111 check_dsp(ctx);
16112 gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, cpu_env);
16113 break;
16114 case OPC_DPSQ_SA_L_W:
16115 check_dsp(ctx);
16116 gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, cpu_env);
16117 break;
16118 case OPC_MAQ_S_W_PHL:
16119 check_dsp(ctx);
16120 gen_helper_maq_s_w_phl(t0, v1_t, v2_t, cpu_env);
16121 break;
16122 case OPC_MAQ_S_W_PHR:
16123 check_dsp(ctx);
16124 gen_helper_maq_s_w_phr(t0, v1_t, v2_t, cpu_env);
16125 break;
16126 case OPC_MAQ_SA_W_PHL:
16127 check_dsp(ctx);
16128 gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, cpu_env);
16129 break;
16130 case OPC_MAQ_SA_W_PHR:
16131 check_dsp(ctx);
16132 gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, cpu_env);
16133 break;
16134 case OPC_MULSA_W_PH:
16135 check_dspr2(ctx);
16136 gen_helper_mulsa_w_ph(t0, v1_t, v2_t, cpu_env);
16137 break;
16138 }
16139 break;
16140 #ifdef TARGET_MIPS64
16141 case OPC_DPAQ_W_QH_DSP:
16142 {
16143 int ac = ret & 0x03;
16144 tcg_gen_movi_i32(t0, ac);
16145
16146 switch (op2) {
16147 case OPC_DMADD:
16148 check_dsp(ctx);
16149 gen_helper_dmadd(v1_t, v2_t, t0, cpu_env);
16150 break;
16151 case OPC_DMADDU:
16152 check_dsp(ctx);
16153 gen_helper_dmaddu(v1_t, v2_t, t0, cpu_env);
16154 break;
16155 case OPC_DMSUB:
16156 check_dsp(ctx);
16157 gen_helper_dmsub(v1_t, v2_t, t0, cpu_env);
16158 break;
16159 case OPC_DMSUBU:
16160 check_dsp(ctx);
16161 gen_helper_dmsubu(v1_t, v2_t, t0, cpu_env);
16162 break;
16163 case OPC_DPA_W_QH:
16164 check_dspr2(ctx);
16165 gen_helper_dpa_w_qh(v1_t, v2_t, t0, cpu_env);
16166 break;
16167 case OPC_DPAQ_S_W_QH:
16168 check_dsp(ctx);
16169 gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, cpu_env);
16170 break;
16171 case OPC_DPAQ_SA_L_PW:
16172 check_dsp(ctx);
16173 gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, cpu_env);
16174 break;
16175 case OPC_DPAU_H_OBL:
16176 check_dsp(ctx);
16177 gen_helper_dpau_h_obl(v1_t, v2_t, t0, cpu_env);
16178 break;
16179 case OPC_DPAU_H_OBR:
16180 check_dsp(ctx);
16181 gen_helper_dpau_h_obr(v1_t, v2_t, t0, cpu_env);
16182 break;
16183 case OPC_DPS_W_QH:
16184 check_dspr2(ctx);
16185 gen_helper_dps_w_qh(v1_t, v2_t, t0, cpu_env);
16186 break;
16187 case OPC_DPSQ_S_W_QH:
16188 check_dsp(ctx);
16189 gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, cpu_env);
16190 break;
16191 case OPC_DPSQ_SA_L_PW:
16192 check_dsp(ctx);
16193 gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, cpu_env);
16194 break;
16195 case OPC_DPSU_H_OBL:
16196 check_dsp(ctx);
16197 gen_helper_dpsu_h_obl(v1_t, v2_t, t0, cpu_env);
16198 break;
16199 case OPC_DPSU_H_OBR:
16200 check_dsp(ctx);
16201 gen_helper_dpsu_h_obr(v1_t, v2_t, t0, cpu_env);
16202 break;
16203 case OPC_MAQ_S_L_PWL:
16204 check_dsp(ctx);
16205 gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, cpu_env);
16206 break;
16207 case OPC_MAQ_S_L_PWR:
16208 check_dsp(ctx);
16209 gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, cpu_env);
16210 break;
16211 case OPC_MAQ_S_W_QHLL:
16212 check_dsp(ctx);
16213 gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, cpu_env);
16214 break;
16215 case OPC_MAQ_SA_W_QHLL:
16216 check_dsp(ctx);
16217 gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, cpu_env);
16218 break;
16219 case OPC_MAQ_S_W_QHLR:
16220 check_dsp(ctx);
16221 gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, cpu_env);
16222 break;
16223 case OPC_MAQ_SA_W_QHLR:
16224 check_dsp(ctx);
16225 gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, cpu_env);
16226 break;
16227 case OPC_MAQ_S_W_QHRL:
16228 check_dsp(ctx);
16229 gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, cpu_env);
16230 break;
16231 case OPC_MAQ_SA_W_QHRL:
16232 check_dsp(ctx);
16233 gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, cpu_env);
16234 break;
16235 case OPC_MAQ_S_W_QHRR:
16236 check_dsp(ctx);
16237 gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, cpu_env);
16238 break;
16239 case OPC_MAQ_SA_W_QHRR:
16240 check_dsp(ctx);
16241 gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, cpu_env);
16242 break;
16243 case OPC_MULSAQ_S_L_PW:
16244 check_dsp(ctx);
16245 gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, cpu_env);
16246 break;
16247 case OPC_MULSAQ_S_W_QH:
16248 check_dsp(ctx);
16249 gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, cpu_env);
16250 break;
16251 }
16252 }
16253 break;
16254 #endif
16255 case OPC_ADDU_QB_DSP:
16256 switch (op2) {
16257 case OPC_MULEU_S_PH_QBL:
16258 check_dsp(ctx);
16259 gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16260 break;
16261 case OPC_MULEU_S_PH_QBR:
16262 check_dsp(ctx);
16263 gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16264 break;
16265 case OPC_MULQ_RS_PH:
16266 check_dsp(ctx);
16267 gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16268 break;
16269 case OPC_MULEQ_S_W_PHL:
16270 check_dsp(ctx);
16271 gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16272 break;
16273 case OPC_MULEQ_S_W_PHR:
16274 check_dsp(ctx);
16275 gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16276 break;
16277 case OPC_MULQ_S_PH:
16278 check_dspr2(ctx);
16279 gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16280 break;
16281 }
16282 break;
16283 #ifdef TARGET_MIPS64
16284 case OPC_ADDU_OB_DSP:
16285 switch (op2) {
16286 case OPC_MULEQ_S_PW_QHL:
16287 check_dsp(ctx);
16288 gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16289 break;
16290 case OPC_MULEQ_S_PW_QHR:
16291 check_dsp(ctx);
16292 gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16293 break;
16294 case OPC_MULEU_S_QH_OBL:
16295 check_dsp(ctx);
16296 gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16297 break;
16298 case OPC_MULEU_S_QH_OBR:
16299 check_dsp(ctx);
16300 gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16301 break;
16302 case OPC_MULQ_RS_QH:
16303 check_dsp(ctx);
16304 gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16305 break;
16306 }
16307 break;
16308 #endif
16309 }
16310
16311 tcg_temp_free_i32(t0);
16312 tcg_temp_free(v1_t);
16313 tcg_temp_free(v2_t);
16314 }
16315
16316 static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
16317 int ret, int val)
16318 {
16319 int16_t imm;
16320 TCGv t0;
16321 TCGv val_t;
16322
16323 if (ret == 0) {
16324 /* Treat as NOP. */
16325 return;
16326 }
16327
16328 t0 = tcg_temp_new();
16329 val_t = tcg_temp_new();
16330 gen_load_gpr(val_t, val);
16331
16332 switch (op1) {
16333 case OPC_ABSQ_S_PH_DSP:
16334 switch (op2) {
16335 case OPC_BITREV:
16336 check_dsp(ctx);
16337 gen_helper_bitrev(cpu_gpr[ret], val_t);
16338 break;
16339 case OPC_REPL_QB:
16340 check_dsp(ctx);
16341 {
16342 target_long result;
16343 imm = (ctx->opcode >> 16) & 0xFF;
16344 result = (uint32_t)imm << 24 |
16345 (uint32_t)imm << 16 |
16346 (uint32_t)imm << 8 |
16347 (uint32_t)imm;
16348 result = (int32_t)result;
16349 tcg_gen_movi_tl(cpu_gpr[ret], result);
16350 }
16351 break;
16352 case OPC_REPLV_QB:
16353 check_dsp(ctx);
16354 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
16355 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
16356 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16357 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
16358 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16359 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
16360 break;
16361 case OPC_REPL_PH:
16362 check_dsp(ctx);
16363 {
16364 imm = (ctx->opcode >> 16) & 0x03FF;
16365 imm = (int16_t)(imm << 6) >> 6;
16366 tcg_gen_movi_tl(cpu_gpr[ret], \
16367 (target_long)((int32_t)imm << 16 | \
16368 (uint16_t)imm));
16369 }
16370 break;
16371 case OPC_REPLV_PH:
16372 check_dsp(ctx);
16373 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
16374 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
16375 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16376 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
16377 break;
16378 }
16379 break;
16380 #ifdef TARGET_MIPS64
16381 case OPC_ABSQ_S_QH_DSP:
16382 switch (op2) {
16383 case OPC_REPL_OB:
16384 check_dsp(ctx);
16385 {
16386 target_long temp;
16387
16388 imm = (ctx->opcode >> 16) & 0xFF;
16389 temp = ((uint64_t)imm << 8) | (uint64_t)imm;
16390 temp = (temp << 16) | temp;
16391 temp = (temp << 32) | temp;
16392 tcg_gen_movi_tl(cpu_gpr[ret], temp);
16393 break;
16394 }
16395 case OPC_REPL_PW:
16396 check_dsp(ctx);
16397 {
16398 target_long temp;
16399
16400 imm = (ctx->opcode >> 16) & 0x03FF;
16401 imm = (int16_t)(imm << 6) >> 6;
16402 temp = ((target_long)imm << 32) \
16403 | ((target_long)imm & 0xFFFFFFFF);
16404 tcg_gen_movi_tl(cpu_gpr[ret], temp);
16405 break;
16406 }
16407 case OPC_REPL_QH:
16408 check_dsp(ctx);
16409 {
16410 target_long temp;
16411
16412 imm = (ctx->opcode >> 16) & 0x03FF;
16413 imm = (int16_t)(imm << 6) >> 6;
16414
16415 temp = ((uint64_t)(uint16_t)imm << 48) |
16416 ((uint64_t)(uint16_t)imm << 32) |
16417 ((uint64_t)(uint16_t)imm << 16) |
16418 (uint64_t)(uint16_t)imm;
16419 tcg_gen_movi_tl(cpu_gpr[ret], temp);
16420 break;
16421 }
16422 case OPC_REPLV_OB:
16423 check_dsp(ctx);
16424 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
16425 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
16426 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16427 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
16428 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16429 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
16430 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16431 break;
16432 case OPC_REPLV_PW:
16433 check_dsp(ctx);
16434 tcg_gen_ext32u_i64(cpu_gpr[ret], val_t);
16435 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
16436 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16437 break;
16438 case OPC_REPLV_QH:
16439 check_dsp(ctx);
16440 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
16441 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
16442 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16443 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
16444 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16445 break;
16446 }
16447 break;
16448 #endif
16449 }
16450 tcg_temp_free(t0);
16451 tcg_temp_free(val_t);
16452 }
16453
16454 static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
16455 uint32_t op1, uint32_t op2,
16456 int ret, int v1, int v2, int check_ret)
16457 {
16458 TCGv t1;
16459 TCGv v1_t;
16460 TCGv v2_t;
16461
16462 if ((ret == 0) && (check_ret == 1)) {
16463 /* Treat as NOP. */
16464 return;
16465 }
16466
16467 t1 = tcg_temp_new();
16468 v1_t = tcg_temp_new();
16469 v2_t = tcg_temp_new();
16470
16471 gen_load_gpr(v1_t, v1);
16472 gen_load_gpr(v2_t, v2);
16473
16474 switch (op1) {
16475 case OPC_CMPU_EQ_QB_DSP:
16476 switch (op2) {
16477 case OPC_CMPU_EQ_QB:
16478 check_dsp(ctx);
16479 gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env);
16480 break;
16481 case OPC_CMPU_LT_QB:
16482 check_dsp(ctx);
16483 gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env);
16484 break;
16485 case OPC_CMPU_LE_QB:
16486 check_dsp(ctx);
16487 gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env);
16488 break;
16489 case OPC_CMPGU_EQ_QB:
16490 check_dsp(ctx);
16491 gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t);
16492 break;
16493 case OPC_CMPGU_LT_QB:
16494 check_dsp(ctx);
16495 gen_helper_cmpgu_lt_qb(cpu_gpr[ret], v1_t, v2_t);
16496 break;
16497 case OPC_CMPGU_LE_QB:
16498 check_dsp(ctx);
16499 gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t);
16500 break;
16501 case OPC_CMPGDU_EQ_QB:
16502 check_dspr2(ctx);
16503 gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t);
16504 tcg_gen_mov_tl(cpu_gpr[ret], t1);
16505 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
16506 tcg_gen_shli_tl(t1, t1, 24);
16507 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
16508 break;
16509 case OPC_CMPGDU_LT_QB:
16510 check_dspr2(ctx);
16511 gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t);
16512 tcg_gen_mov_tl(cpu_gpr[ret], t1);
16513 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
16514 tcg_gen_shli_tl(t1, t1, 24);
16515 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
16516 break;
16517 case OPC_CMPGDU_LE_QB:
16518 check_dspr2(ctx);
16519 gen_helper_cmpgu_le_qb(t1, v1_t, v2_t);
16520 tcg_gen_mov_tl(cpu_gpr[ret], t1);
16521 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
16522 tcg_gen_shli_tl(t1, t1, 24);
16523 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
16524 break;
16525 case OPC_CMP_EQ_PH:
16526 check_dsp(ctx);
16527 gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env);
16528 break;
16529 case OPC_CMP_LT_PH:
16530 check_dsp(ctx);
16531 gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env);
16532 break;
16533 case OPC_CMP_LE_PH:
16534 check_dsp(ctx);
16535 gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env);
16536 break;
16537 case OPC_PICK_QB:
16538 check_dsp(ctx);
16539 gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16540 break;
16541 case OPC_PICK_PH:
16542 check_dsp(ctx);
16543 gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16544 break;
16545 case OPC_PACKRL_PH:
16546 check_dsp(ctx);
16547 gen_helper_packrl_ph(cpu_gpr[ret], v1_t, v2_t);
16548 break;
16549 }
16550 break;
16551 #ifdef TARGET_MIPS64
16552 case OPC_CMPU_EQ_OB_DSP:
16553 switch (op2) {
16554 case OPC_CMP_EQ_PW:
16555 check_dsp(ctx);
16556 gen_helper_cmp_eq_pw(v1_t, v2_t, cpu_env);
16557 break;
16558 case OPC_CMP_LT_PW:
16559 check_dsp(ctx);
16560 gen_helper_cmp_lt_pw(v1_t, v2_t, cpu_env);
16561 break;
16562 case OPC_CMP_LE_PW:
16563 check_dsp(ctx);
16564 gen_helper_cmp_le_pw(v1_t, v2_t, cpu_env);
16565 break;
16566 case OPC_CMP_EQ_QH:
16567 check_dsp(ctx);
16568 gen_helper_cmp_eq_qh(v1_t, v2_t, cpu_env);
16569 break;
16570 case OPC_CMP_LT_QH:
16571 check_dsp(ctx);
16572 gen_helper_cmp_lt_qh(v1_t, v2_t, cpu_env);
16573 break;
16574 case OPC_CMP_LE_QH:
16575 check_dsp(ctx);
16576 gen_helper_cmp_le_qh(v1_t, v2_t, cpu_env);
16577 break;
16578 case OPC_CMPGDU_EQ_OB:
16579 check_dspr2(ctx);
16580 gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16581 break;
16582 case OPC_CMPGDU_LT_OB:
16583 check_dspr2(ctx);
16584 gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16585 break;
16586 case OPC_CMPGDU_LE_OB:
16587 check_dspr2(ctx);
16588 gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16589 break;
16590 case OPC_CMPGU_EQ_OB:
16591 check_dsp(ctx);
16592 gen_helper_cmpgu_eq_ob(cpu_gpr[ret], v1_t, v2_t);
16593 break;
16594 case OPC_CMPGU_LT_OB:
16595 check_dsp(ctx);
16596 gen_helper_cmpgu_lt_ob(cpu_gpr[ret], v1_t, v2_t);
16597 break;
16598 case OPC_CMPGU_LE_OB:
16599 check_dsp(ctx);
16600 gen_helper_cmpgu_le_ob(cpu_gpr[ret], v1_t, v2_t);
16601 break;
16602 case OPC_CMPU_EQ_OB:
16603 check_dsp(ctx);
16604 gen_helper_cmpu_eq_ob(v1_t, v2_t, cpu_env);
16605 break;
16606 case OPC_CMPU_LT_OB:
16607 check_dsp(ctx);
16608 gen_helper_cmpu_lt_ob(v1_t, v2_t, cpu_env);
16609 break;
16610 case OPC_CMPU_LE_OB:
16611 check_dsp(ctx);
16612 gen_helper_cmpu_le_ob(v1_t, v2_t, cpu_env);
16613 break;
16614 case OPC_PACKRL_PW:
16615 check_dsp(ctx);
16616 gen_helper_packrl_pw(cpu_gpr[ret], v1_t, v2_t);
16617 break;
16618 case OPC_PICK_OB:
16619 check_dsp(ctx);
16620 gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16621 break;
16622 case OPC_PICK_PW:
16623 check_dsp(ctx);
16624 gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16625 break;
16626 case OPC_PICK_QH:
16627 check_dsp(ctx);
16628 gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16629 break;
16630 }
16631 break;
16632 #endif
16633 }
16634
16635 tcg_temp_free(t1);
16636 tcg_temp_free(v1_t);
16637 tcg_temp_free(v2_t);
16638 }
16639
16640 static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
16641 uint32_t op1, int rt, int rs, int sa)
16642 {
16643 TCGv t0;
16644
16645 check_dspr2(ctx);
16646
16647 if (rt == 0) {
16648 /* Treat as NOP. */
16649 return;
16650 }
16651
16652 t0 = tcg_temp_new();
16653 gen_load_gpr(t0, rs);
16654
16655 switch (op1) {
16656 case OPC_APPEND_DSP:
16657 switch (MASK_APPEND(ctx->opcode)) {
16658 case OPC_APPEND:
16659 if (sa != 0) {
16660 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa);
16661 }
16662 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
16663 break;
16664 case OPC_PREPEND:
16665 if (sa != 0) {
16666 tcg_gen_ext32u_tl(cpu_gpr[rt], cpu_gpr[rt]);
16667 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa);
16668 tcg_gen_shli_tl(t0, t0, 32 - sa);
16669 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
16670 }
16671 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
16672 break;
16673 case OPC_BALIGN:
16674 sa &= 3;
16675 if (sa != 0 && sa != 2) {
16676 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa);
16677 tcg_gen_ext32u_tl(t0, t0);
16678 tcg_gen_shri_tl(t0, t0, 8 * (4 - sa));
16679 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
16680 }
16681 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
16682 break;
16683 default: /* Invalid */
16684 MIPS_INVAL("MASK APPEND");
16685 generate_exception_end(ctx, EXCP_RI);
16686 break;
16687 }
16688 break;
16689 #ifdef TARGET_MIPS64
16690 case OPC_DAPPEND_DSP:
16691 switch (MASK_DAPPEND(ctx->opcode)) {
16692 case OPC_DAPPEND:
16693 if (sa != 0) {
16694 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa);
16695 }
16696 break;
16697 case OPC_PREPENDD:
16698 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], 0x20 | sa);
16699 tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa));
16700 tcg_gen_or_tl(cpu_gpr[rt], t0, t0);
16701 break;
16702 case OPC_PREPENDW:
16703 if (sa != 0) {
16704 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa);
16705 tcg_gen_shli_tl(t0, t0, 64 - sa);
16706 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
16707 }
16708 break;
16709 case OPC_DBALIGN:
16710 sa &= 7;
16711 if (sa != 0 && sa != 2 && sa != 4) {
16712 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa);
16713 tcg_gen_shri_tl(t0, t0, 8 * (8 - sa));
16714 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
16715 }
16716 break;
16717 default: /* Invalid */
16718 MIPS_INVAL("MASK DAPPEND");
16719 generate_exception_end(ctx, EXCP_RI);
16720 break;
16721 }
16722 break;
16723 #endif
16724 }
16725 tcg_temp_free(t0);
16726 }
16727
16728 static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
16729 int ret, int v1, int v2, int check_ret)
16730
16731 {
16732 TCGv t0;
16733 TCGv t1;
16734 TCGv v1_t;
16735 TCGv v2_t;
16736 int16_t imm;
16737
16738 if ((ret == 0) && (check_ret == 1)) {
16739 /* Treat as NOP. */
16740 return;
16741 }
16742
16743 t0 = tcg_temp_new();
16744 t1 = tcg_temp_new();
16745 v1_t = tcg_temp_new();
16746 v2_t = tcg_temp_new();
16747
16748 gen_load_gpr(v1_t, v1);
16749 gen_load_gpr(v2_t, v2);
16750
16751 switch (op1) {
16752 case OPC_EXTR_W_DSP:
16753 check_dsp(ctx);
16754 switch (op2) {
16755 case OPC_EXTR_W:
16756 tcg_gen_movi_tl(t0, v2);
16757 tcg_gen_movi_tl(t1, v1);
16758 gen_helper_extr_w(cpu_gpr[ret], t0, t1, cpu_env);
16759 break;
16760 case OPC_EXTR_R_W:
16761 tcg_gen_movi_tl(t0, v2);
16762 tcg_gen_movi_tl(t1, v1);
16763 gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
16764 break;
16765 case OPC_EXTR_RS_W:
16766 tcg_gen_movi_tl(t0, v2);
16767 tcg_gen_movi_tl(t1, v1);
16768 gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
16769 break;
16770 case OPC_EXTR_S_H:
16771 tcg_gen_movi_tl(t0, v2);
16772 tcg_gen_movi_tl(t1, v1);
16773 gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
16774 break;
16775 case OPC_EXTRV_S_H:
16776 tcg_gen_movi_tl(t0, v2);
16777 gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
16778 break;
16779 case OPC_EXTRV_W:
16780 tcg_gen_movi_tl(t0, v2);
16781 gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
16782 break;
16783 case OPC_EXTRV_R_W:
16784 tcg_gen_movi_tl(t0, v2);
16785 gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
16786 break;
16787 case OPC_EXTRV_RS_W:
16788 tcg_gen_movi_tl(t0, v2);
16789 gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
16790 break;
16791 case OPC_EXTP:
16792 tcg_gen_movi_tl(t0, v2);
16793 tcg_gen_movi_tl(t1, v1);
16794 gen_helper_extp(cpu_gpr[ret], t0, t1, cpu_env);
16795 break;
16796 case OPC_EXTPV:
16797 tcg_gen_movi_tl(t0, v2);
16798 gen_helper_extp(cpu_gpr[ret], t0, v1_t, cpu_env);
16799 break;
16800 case OPC_EXTPDP:
16801 tcg_gen_movi_tl(t0, v2);
16802 tcg_gen_movi_tl(t1, v1);
16803 gen_helper_extpdp(cpu_gpr[ret], t0, t1, cpu_env);
16804 break;
16805 case OPC_EXTPDPV:
16806 tcg_gen_movi_tl(t0, v2);
16807 gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
16808 break;
16809 case OPC_SHILO:
16810 imm = (ctx->opcode >> 20) & 0x3F;
16811 tcg_gen_movi_tl(t0, ret);
16812 tcg_gen_movi_tl(t1, imm);
16813 gen_helper_shilo(t0, t1, cpu_env);
16814 break;
16815 case OPC_SHILOV:
16816 tcg_gen_movi_tl(t0, ret);
16817 gen_helper_shilo(t0, v1_t, cpu_env);
16818 break;
16819 case OPC_MTHLIP:
16820 tcg_gen_movi_tl(t0, ret);
16821 gen_helper_mthlip(t0, v1_t, cpu_env);
16822 break;
16823 case OPC_WRDSP:
16824 imm = (ctx->opcode >> 11) & 0x3FF;
16825 tcg_gen_movi_tl(t0, imm);
16826 gen_helper_wrdsp(v1_t, t0, cpu_env);
16827 break;
16828 case OPC_RDDSP:
16829 imm = (ctx->opcode >> 16) & 0x03FF;
16830 tcg_gen_movi_tl(t0, imm);
16831 gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env);
16832 break;
16833 }
16834 break;
16835 #ifdef TARGET_MIPS64
16836 case OPC_DEXTR_W_DSP:
16837 check_dsp(ctx);
16838 switch (op2) {
16839 case OPC_DMTHLIP:
16840 tcg_gen_movi_tl(t0, ret);
16841 gen_helper_dmthlip(v1_t, t0, cpu_env);
16842 break;
16843 case OPC_DSHILO:
16844 {
16845 int shift = (ctx->opcode >> 19) & 0x7F;
16846 int ac = (ctx->opcode >> 11) & 0x03;
16847 tcg_gen_movi_tl(t0, shift);
16848 tcg_gen_movi_tl(t1, ac);
16849 gen_helper_dshilo(t0, t1, cpu_env);
16850 break;
16851 }
16852 case OPC_DSHILOV:
16853 {
16854 int ac = (ctx->opcode >> 11) & 0x03;
16855 tcg_gen_movi_tl(t0, ac);
16856 gen_helper_dshilo(v1_t, t0, cpu_env);
16857 break;
16858 }
16859 case OPC_DEXTP:
16860 tcg_gen_movi_tl(t0, v2);
16861 tcg_gen_movi_tl(t1, v1);
16862
16863 gen_helper_dextp(cpu_gpr[ret], t0, t1, cpu_env);
16864 break;
16865 case OPC_DEXTPV:
16866 tcg_gen_movi_tl(t0, v2);
16867 gen_helper_dextp(cpu_gpr[ret], t0, v1_t, cpu_env);
16868 break;
16869 case OPC_DEXTPDP:
16870 tcg_gen_movi_tl(t0, v2);
16871 tcg_gen_movi_tl(t1, v1);
16872 gen_helper_dextpdp(cpu_gpr[ret], t0, t1, cpu_env);
16873 break;
16874 case OPC_DEXTPDPV:
16875 tcg_gen_movi_tl(t0, v2);
16876 gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
16877 break;
16878 case OPC_DEXTR_L:
16879 tcg_gen_movi_tl(t0, v2);
16880 tcg_gen_movi_tl(t1, v1);
16881 gen_helper_dextr_l(cpu_gpr[ret], t0, t1, cpu_env);
16882 break;
16883 case OPC_DEXTR_R_L:
16884 tcg_gen_movi_tl(t0, v2);
16885 tcg_gen_movi_tl(t1, v1);
16886 gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, cpu_env);
16887 break;
16888 case OPC_DEXTR_RS_L:
16889 tcg_gen_movi_tl(t0, v2);
16890 tcg_gen_movi_tl(t1, v1);
16891 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, cpu_env);
16892 break;
16893 case OPC_DEXTR_W:
16894 tcg_gen_movi_tl(t0, v2);
16895 tcg_gen_movi_tl(t1, v1);
16896 gen_helper_dextr_w(cpu_gpr[ret], t0, t1, cpu_env);
16897 break;
16898 case OPC_DEXTR_R_W:
16899 tcg_gen_movi_tl(t0, v2);
16900 tcg_gen_movi_tl(t1, v1);
16901 gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
16902 break;
16903 case OPC_DEXTR_RS_W:
16904 tcg_gen_movi_tl(t0, v2);
16905 tcg_gen_movi_tl(t1, v1);
16906 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
16907 break;
16908 case OPC_DEXTR_S_H:
16909 tcg_gen_movi_tl(t0, v2);
16910 tcg_gen_movi_tl(t1, v1);
16911 gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
16912 break;
16913 case OPC_DEXTRV_S_H:
16914 tcg_gen_movi_tl(t0, v2);
16915 tcg_gen_movi_tl(t1, v1);
16916 gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
16917 break;
16918 case OPC_DEXTRV_L:
16919 tcg_gen_movi_tl(t0, v2);
16920 gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, cpu_env);
16921 break;
16922 case OPC_DEXTRV_R_L:
16923 tcg_gen_movi_tl(t0, v2);
16924 gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, cpu_env);
16925 break;
16926 case OPC_DEXTRV_RS_L:
16927 tcg_gen_movi_tl(t0, v2);
16928 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, cpu_env);
16929 break;
16930 case OPC_DEXTRV_W:
16931 tcg_gen_movi_tl(t0, v2);
16932 gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
16933 break;
16934 case OPC_DEXTRV_R_W:
16935 tcg_gen_movi_tl(t0, v2);
16936 gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
16937 break;
16938 case OPC_DEXTRV_RS_W:
16939 tcg_gen_movi_tl(t0, v2);
16940 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
16941 break;
16942 }
16943 break;
16944 #endif
16945 }
16946
16947 tcg_temp_free(t0);
16948 tcg_temp_free(t1);
16949 tcg_temp_free(v1_t);
16950 tcg_temp_free(v2_t);
16951 }
16952
16953 /* End MIPSDSP functions. */
16954
16955 static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
16956 {
16957 int rs, rt, rd, sa;
16958 uint32_t op1, op2;
16959
16960 rs = (ctx->opcode >> 21) & 0x1f;
16961 rt = (ctx->opcode >> 16) & 0x1f;
16962 rd = (ctx->opcode >> 11) & 0x1f;
16963 sa = (ctx->opcode >> 6) & 0x1f;
16964
16965 op1 = MASK_SPECIAL(ctx->opcode);
16966 switch (op1) {
16967 case OPC_LSA:
16968 gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
16969 break;
16970 case OPC_MULT ... OPC_DIVU:
16971 op2 = MASK_R6_MULDIV(ctx->opcode);
16972 switch (op2) {
16973 case R6_OPC_MUL:
16974 case R6_OPC_MUH:
16975 case R6_OPC_MULU:
16976 case R6_OPC_MUHU:
16977 case R6_OPC_DIV:
16978 case R6_OPC_MOD:
16979 case R6_OPC_DIVU:
16980 case R6_OPC_MODU:
16981 gen_r6_muldiv(ctx, op2, rd, rs, rt);
16982 break;
16983 default:
16984 MIPS_INVAL("special_r6 muldiv");
16985 generate_exception_end(ctx, EXCP_RI);
16986 break;
16987 }
16988 break;
16989 case OPC_SELEQZ:
16990 case OPC_SELNEZ:
16991 gen_cond_move(ctx, op1, rd, rs, rt);
16992 break;
16993 case R6_OPC_CLO:
16994 case R6_OPC_CLZ:
16995 if (rt == 0 && sa == 1) {
16996 /* Major opcode and function field is shared with preR6 MFHI/MTHI.
16997 We need additionally to check other fields */
16998 gen_cl(ctx, op1, rd, rs);
16999 } else {
17000 generate_exception_end(ctx, EXCP_RI);
17001 }
17002 break;
17003 case R6_OPC_SDBBP:
17004 if (is_uhi(extract32(ctx->opcode, 6, 20))) {
17005 gen_helper_do_semihosting(cpu_env);
17006 } else {
17007 if (ctx->hflags & MIPS_HFLAG_SBRI) {
17008 generate_exception_end(ctx, EXCP_RI);
17009 } else {
17010 generate_exception_end(ctx, EXCP_DBp);
17011 }
17012 }
17013 break;
17014 #if defined(TARGET_MIPS64)
17015 case OPC_DLSA:
17016 check_mips_64(ctx);
17017 gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
17018 break;
17019 case R6_OPC_DCLO:
17020 case R6_OPC_DCLZ:
17021 if (rt == 0 && sa == 1) {
17022 /* Major opcode and function field is shared with preR6 MFHI/MTHI.
17023 We need additionally to check other fields */
17024 check_mips_64(ctx);
17025 gen_cl(ctx, op1, rd, rs);
17026 } else {
17027 generate_exception_end(ctx, EXCP_RI);
17028 }
17029 break;
17030 case OPC_DMULT ... OPC_DDIVU:
17031 op2 = MASK_R6_MULDIV(ctx->opcode);
17032 switch (op2) {
17033 case R6_OPC_DMUL:
17034 case R6_OPC_DMUH:
17035 case R6_OPC_DMULU:
17036 case R6_OPC_DMUHU:
17037 case R6_OPC_DDIV:
17038 case R6_OPC_DMOD:
17039 case R6_OPC_DDIVU:
17040 case R6_OPC_DMODU:
17041 check_mips_64(ctx);
17042 gen_r6_muldiv(ctx, op2, rd, rs, rt);
17043 break;
17044 default:
17045 MIPS_INVAL("special_r6 muldiv");
17046 generate_exception_end(ctx, EXCP_RI);
17047 break;
17048 }
17049 break;
17050 #endif
17051 default: /* Invalid */
17052 MIPS_INVAL("special_r6");
17053 generate_exception_end(ctx, EXCP_RI);
17054 break;
17055 }
17056 }
17057
17058 static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
17059 {
17060 int rs, rt, rd, sa;
17061 uint32_t op1;
17062
17063 rs = (ctx->opcode >> 21) & 0x1f;
17064 rt = (ctx->opcode >> 16) & 0x1f;
17065 rd = (ctx->opcode >> 11) & 0x1f;
17066 sa = (ctx->opcode >> 6) & 0x1f;
17067
17068 op1 = MASK_SPECIAL(ctx->opcode);
17069 switch (op1) {
17070 case OPC_MOVN: /* Conditional move */
17071 case OPC_MOVZ:
17072 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
17073 INSN_LOONGSON2E | INSN_LOONGSON2F);
17074 gen_cond_move(ctx, op1, rd, rs, rt);
17075 break;
17076 case OPC_MFHI: /* Move from HI/LO */
17077 case OPC_MFLO:
17078 gen_HILO(ctx, op1, rs & 3, rd);
17079 break;
17080 case OPC_MTHI:
17081 case OPC_MTLO: /* Move to HI/LO */
17082 gen_HILO(ctx, op1, rd & 3, rs);
17083 break;
17084 case OPC_MOVCI:
17085 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
17086 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
17087 check_cp1_enabled(ctx);
17088 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
17089 (ctx->opcode >> 16) & 1);
17090 } else {
17091 generate_exception_err(ctx, EXCP_CpU, 1);
17092 }
17093 break;
17094 case OPC_MULT:
17095 case OPC_MULTU:
17096 if (sa) {
17097 check_insn(ctx, INSN_VR54XX);
17098 op1 = MASK_MUL_VR54XX(ctx->opcode);
17099 gen_mul_vr54xx(ctx, op1, rd, rs, rt);
17100 } else {
17101 gen_muldiv(ctx, op1, rd & 3, rs, rt);
17102 }
17103 break;
17104 case OPC_DIV:
17105 case OPC_DIVU:
17106 gen_muldiv(ctx, op1, 0, rs, rt);
17107 break;
17108 #if defined(TARGET_MIPS64)
17109 case OPC_DMULT ... OPC_DDIVU:
17110 check_insn(ctx, ISA_MIPS3);
17111 check_mips_64(ctx);
17112 gen_muldiv(ctx, op1, 0, rs, rt);
17113 break;
17114 #endif
17115 case OPC_JR:
17116 gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
17117 break;
17118 case OPC_SPIM:
17119 #ifdef MIPS_STRICT_STANDARD
17120 MIPS_INVAL("SPIM");
17121 generate_exception_end(ctx, EXCP_RI);
17122 #else
17123 /* Implemented as RI exception for now. */
17124 MIPS_INVAL("spim (unofficial)");
17125 generate_exception_end(ctx, EXCP_RI);
17126 #endif
17127 break;
17128 default: /* Invalid */
17129 MIPS_INVAL("special_legacy");
17130 generate_exception_end(ctx, EXCP_RI);
17131 break;
17132 }
17133 }
17134
17135 static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
17136 {
17137 int rs, rt, rd, sa;
17138 uint32_t op1;
17139
17140 rs = (ctx->opcode >> 21) & 0x1f;
17141 rt = (ctx->opcode >> 16) & 0x1f;
17142 rd = (ctx->opcode >> 11) & 0x1f;
17143 sa = (ctx->opcode >> 6) & 0x1f;
17144
17145 op1 = MASK_SPECIAL(ctx->opcode);
17146 switch (op1) {
17147 case OPC_SLL: /* Shift with immediate */
17148 if (sa == 5 && rd == 0 &&
17149 rs == 0 && rt == 0) { /* PAUSE */
17150 if ((ctx->insn_flags & ISA_MIPS32R6) &&
17151 (ctx->hflags & MIPS_HFLAG_BMASK)) {
17152 generate_exception_end(ctx, EXCP_RI);
17153 break;
17154 }
17155 }
17156 /* Fallthrough */
17157 case OPC_SRA:
17158 gen_shift_imm(ctx, op1, rd, rt, sa);
17159 break;
17160 case OPC_SRL:
17161 switch ((ctx->opcode >> 21) & 0x1f) {
17162 case 1:
17163 /* rotr is decoded as srl on non-R2 CPUs */
17164 if (ctx->insn_flags & ISA_MIPS32R2) {
17165 op1 = OPC_ROTR;
17166 }
17167 /* Fallthrough */
17168 case 0:
17169 gen_shift_imm(ctx, op1, rd, rt, sa);
17170 break;
17171 default:
17172 generate_exception_end(ctx, EXCP_RI);
17173 break;
17174 }
17175 break;
17176 case OPC_ADD ... OPC_SUBU:
17177 gen_arith(ctx, op1, rd, rs, rt);
17178 break;
17179 case OPC_SLLV: /* Shifts */
17180 case OPC_SRAV:
17181 gen_shift(ctx, op1, rd, rs, rt);
17182 break;
17183 case OPC_SRLV:
17184 switch ((ctx->opcode >> 6) & 0x1f) {
17185 case 1:
17186 /* rotrv is decoded as srlv on non-R2 CPUs */
17187 if (ctx->insn_flags & ISA_MIPS32R2) {
17188 op1 = OPC_ROTRV;
17189 }
17190 /* Fallthrough */
17191 case 0:
17192 gen_shift(ctx, op1, rd, rs, rt);
17193 break;
17194 default:
17195 generate_exception_end(ctx, EXCP_RI);
17196 break;
17197 }
17198 break;
17199 case OPC_SLT: /* Set on less than */
17200 case OPC_SLTU:
17201 gen_slt(ctx, op1, rd, rs, rt);
17202 break;
17203 case OPC_AND: /* Logic*/
17204 case OPC_OR:
17205 case OPC_NOR:
17206 case OPC_XOR:
17207 gen_logic(ctx, op1, rd, rs, rt);
17208 break;
17209 case OPC_JALR:
17210 gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
17211 break;
17212 case OPC_TGE ... OPC_TEQ: /* Traps */
17213 case OPC_TNE:
17214 check_insn(ctx, ISA_MIPS2);
17215 gen_trap(ctx, op1, rs, rt, -1);
17216 break;
17217 case OPC_LSA: /* OPC_PMON */
17218 if ((ctx->insn_flags & ISA_MIPS32R6) ||
17219 (env->CP0_Config3 & (1 << CP0C3_MSAP))) {
17220 decode_opc_special_r6(env, ctx);
17221 } else {
17222 /* Pmon entry point, also R4010 selsl */
17223 #ifdef MIPS_STRICT_STANDARD
17224 MIPS_INVAL("PMON / selsl");
17225 generate_exception_end(ctx, EXCP_RI);
17226 #else
17227 gen_helper_0e0i(pmon, sa);
17228 #endif
17229 }
17230 break;
17231 case OPC_SYSCALL:
17232 generate_exception_end(ctx, EXCP_SYSCALL);
17233 break;
17234 case OPC_BREAK:
17235 generate_exception_end(ctx, EXCP_BREAK);
17236 break;
17237 case OPC_SYNC:
17238 check_insn(ctx, ISA_MIPS2);
17239 gen_sync(extract32(ctx->opcode, 6, 5));
17240 break;
17241
17242 #if defined(TARGET_MIPS64)
17243 /* MIPS64 specific opcodes */
17244 case OPC_DSLL:
17245 case OPC_DSRA:
17246 case OPC_DSLL32:
17247 case OPC_DSRA32:
17248 check_insn(ctx, ISA_MIPS3);
17249 check_mips_64(ctx);
17250 gen_shift_imm(ctx, op1, rd, rt, sa);
17251 break;
17252 case OPC_DSRL:
17253 switch ((ctx->opcode >> 21) & 0x1f) {
17254 case 1:
17255 /* drotr is decoded as dsrl on non-R2 CPUs */
17256 if (ctx->insn_flags & ISA_MIPS32R2) {
17257 op1 = OPC_DROTR;
17258 }
17259 /* Fallthrough */
17260 case 0:
17261 check_insn(ctx, ISA_MIPS3);
17262 check_mips_64(ctx);
17263 gen_shift_imm(ctx, op1, rd, rt, sa);
17264 break;
17265 default:
17266 generate_exception_end(ctx, EXCP_RI);
17267 break;
17268 }
17269 break;
17270 case OPC_DSRL32:
17271 switch ((ctx->opcode >> 21) & 0x1f) {
17272 case 1:
17273 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
17274 if (ctx->insn_flags & ISA_MIPS32R2) {
17275 op1 = OPC_DROTR32;
17276 }
17277 /* Fallthrough */
17278 case 0:
17279 check_insn(ctx, ISA_MIPS3);
17280 check_mips_64(ctx);
17281 gen_shift_imm(ctx, op1, rd, rt, sa);
17282 break;
17283 default:
17284 generate_exception_end(ctx, EXCP_RI);
17285 break;
17286 }
17287 break;
17288 case OPC_DADD ... OPC_DSUBU:
17289 check_insn(ctx, ISA_MIPS3);
17290 check_mips_64(ctx);
17291 gen_arith(ctx, op1, rd, rs, rt);
17292 break;
17293 case OPC_DSLLV:
17294 case OPC_DSRAV:
17295 check_insn(ctx, ISA_MIPS3);
17296 check_mips_64(ctx);
17297 gen_shift(ctx, op1, rd, rs, rt);
17298 break;
17299 case OPC_DSRLV:
17300 switch ((ctx->opcode >> 6) & 0x1f) {
17301 case 1:
17302 /* drotrv is decoded as dsrlv on non-R2 CPUs */
17303 if (ctx->insn_flags & ISA_MIPS32R2) {
17304 op1 = OPC_DROTRV;
17305 }
17306 /* Fallthrough */
17307 case 0:
17308 check_insn(ctx, ISA_MIPS3);
17309 check_mips_64(ctx);
17310 gen_shift(ctx, op1, rd, rs, rt);
17311 break;
17312 default:
17313 generate_exception_end(ctx, EXCP_RI);
17314 break;
17315 }
17316 break;
17317 case OPC_DLSA:
17318 if ((ctx->insn_flags & ISA_MIPS32R6) ||
17319 (env->CP0_Config3 & (1 << CP0C3_MSAP))) {
17320 decode_opc_special_r6(env, ctx);
17321 }
17322 break;
17323 #endif
17324 default:
17325 if (ctx->insn_flags & ISA_MIPS32R6) {
17326 decode_opc_special_r6(env, ctx);
17327 } else {
17328 decode_opc_special_legacy(env, ctx);
17329 }
17330 }
17331 }
17332
17333 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
17334 {
17335 int rs, rt, rd;
17336 uint32_t op1;
17337
17338 check_insn_opc_removed(ctx, ISA_MIPS32R6);
17339
17340 rs = (ctx->opcode >> 21) & 0x1f;
17341 rt = (ctx->opcode >> 16) & 0x1f;
17342 rd = (ctx->opcode >> 11) & 0x1f;
17343
17344 op1 = MASK_SPECIAL2(ctx->opcode);
17345 switch (op1) {
17346 case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
17347 case OPC_MSUB ... OPC_MSUBU:
17348 check_insn(ctx, ISA_MIPS32);
17349 gen_muldiv(ctx, op1, rd & 3, rs, rt);
17350 break;
17351 case OPC_MUL:
17352 gen_arith(ctx, op1, rd, rs, rt);
17353 break;
17354 case OPC_DIV_G_2F:
17355 case OPC_DIVU_G_2F:
17356 case OPC_MULT_G_2F:
17357 case OPC_MULTU_G_2F:
17358 case OPC_MOD_G_2F:
17359 case OPC_MODU_G_2F:
17360 check_insn(ctx, INSN_LOONGSON2F);
17361 gen_loongson_integer(ctx, op1, rd, rs, rt);
17362 break;
17363 case OPC_CLO:
17364 case OPC_CLZ:
17365 check_insn(ctx, ISA_MIPS32);
17366 gen_cl(ctx, op1, rd, rs);
17367 break;
17368 case OPC_SDBBP:
17369 if (is_uhi(extract32(ctx->opcode, 6, 20))) {
17370 gen_helper_do_semihosting(cpu_env);
17371 } else {
17372 /* XXX: not clear which exception should be raised
17373 * when in debug mode...
17374 */
17375 check_insn(ctx, ISA_MIPS32);
17376 generate_exception_end(ctx, EXCP_DBp);
17377 }
17378 break;
17379 #if defined(TARGET_MIPS64)
17380 case OPC_DCLO:
17381 case OPC_DCLZ:
17382 check_insn(ctx, ISA_MIPS64);
17383 check_mips_64(ctx);
17384 gen_cl(ctx, op1, rd, rs);
17385 break;
17386 case OPC_DMULT_G_2F:
17387 case OPC_DMULTU_G_2F:
17388 case OPC_DDIV_G_2F:
17389 case OPC_DDIVU_G_2F:
17390 case OPC_DMOD_G_2F:
17391 case OPC_DMODU_G_2F:
17392 check_insn(ctx, INSN_LOONGSON2F);
17393 gen_loongson_integer(ctx, op1, rd, rs, rt);
17394 break;
17395 #endif
17396 default: /* Invalid */
17397 MIPS_INVAL("special2_legacy");
17398 generate_exception_end(ctx, EXCP_RI);
17399 break;
17400 }
17401 }
17402
17403 static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
17404 {
17405 int rs, rt, rd, sa;
17406 uint32_t op1, op2;
17407 int16_t imm;
17408
17409 rs = (ctx->opcode >> 21) & 0x1f;
17410 rt = (ctx->opcode >> 16) & 0x1f;
17411 rd = (ctx->opcode >> 11) & 0x1f;
17412 sa = (ctx->opcode >> 6) & 0x1f;
17413 imm = (int16_t)ctx->opcode >> 7;
17414
17415 op1 = MASK_SPECIAL3(ctx->opcode);
17416 switch (op1) {
17417 case R6_OPC_PREF:
17418 if (rt >= 24) {
17419 /* hint codes 24-31 are reserved and signal RI */
17420 generate_exception_end(ctx, EXCP_RI);
17421 }
17422 /* Treat as NOP. */
17423 break;
17424 case R6_OPC_CACHE:
17425 check_cp0_enabled(ctx);
17426 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
17427 gen_cache_operation(ctx, rt, rs, imm);
17428 }
17429 break;
17430 case R6_OPC_SC:
17431 gen_st_cond(ctx, op1, rt, rs, imm);
17432 break;
17433 case R6_OPC_LL:
17434 gen_ld(ctx, op1, rt, rs, imm);
17435 break;
17436 case OPC_BSHFL:
17437 {
17438 if (rd == 0) {
17439 /* Treat as NOP. */
17440 break;
17441 }
17442 op2 = MASK_BSHFL(ctx->opcode);
17443 switch (op2) {
17444 case OPC_ALIGN ... OPC_ALIGN_END:
17445 gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3);
17446 break;
17447 case OPC_BITSWAP:
17448 gen_bitswap(ctx, op2, rd, rt);
17449 break;
17450 }
17451 }
17452 break;
17453 #if defined(TARGET_MIPS64)
17454 case R6_OPC_SCD:
17455 gen_st_cond(ctx, op1, rt, rs, imm);
17456 break;
17457 case R6_OPC_LLD:
17458 gen_ld(ctx, op1, rt, rs, imm);
17459 break;
17460 case OPC_DBSHFL:
17461 check_mips_64(ctx);
17462 {
17463 if (rd == 0) {
17464 /* Treat as NOP. */
17465 break;
17466 }
17467 op2 = MASK_DBSHFL(ctx->opcode);
17468 switch (op2) {
17469 case OPC_DALIGN ... OPC_DALIGN_END:
17470 gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7);
17471 break;
17472 case OPC_DBITSWAP:
17473 gen_bitswap(ctx, op2, rd, rt);
17474 break;
17475 }
17476
17477 }
17478 break;
17479 #endif
17480 default: /* Invalid */
17481 MIPS_INVAL("special3_r6");
17482 generate_exception_end(ctx, EXCP_RI);
17483 break;
17484 }
17485 }
17486
17487 static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
17488 {
17489 int rs, rt, rd;
17490 uint32_t op1, op2;
17491
17492 rs = (ctx->opcode >> 21) & 0x1f;
17493 rt = (ctx->opcode >> 16) & 0x1f;
17494 rd = (ctx->opcode >> 11) & 0x1f;
17495
17496 op1 = MASK_SPECIAL3(ctx->opcode);
17497 switch (op1) {
17498 case OPC_DIV_G_2E ... OPC_DIVU_G_2E:
17499 case OPC_MOD_G_2E ... OPC_MODU_G_2E:
17500 case OPC_MULT_G_2E ... OPC_MULTU_G_2E:
17501 /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
17502 * the same mask and op1. */
17503 if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) {
17504 op2 = MASK_ADDUH_QB(ctx->opcode);
17505 switch (op2) {
17506 case OPC_ADDUH_QB:
17507 case OPC_ADDUH_R_QB:
17508 case OPC_ADDQH_PH:
17509 case OPC_ADDQH_R_PH:
17510 case OPC_ADDQH_W:
17511 case OPC_ADDQH_R_W:
17512 case OPC_SUBUH_QB:
17513 case OPC_SUBUH_R_QB:
17514 case OPC_SUBQH_PH:
17515 case OPC_SUBQH_R_PH:
17516 case OPC_SUBQH_W:
17517 case OPC_SUBQH_R_W:
17518 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17519 break;
17520 case OPC_MUL_PH:
17521 case OPC_MUL_S_PH:
17522 case OPC_MULQ_S_W:
17523 case OPC_MULQ_RS_W:
17524 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
17525 break;
17526 default:
17527 MIPS_INVAL("MASK ADDUH.QB");
17528 generate_exception_end(ctx, EXCP_RI);
17529 break;
17530 }
17531 } else if (ctx->insn_flags & INSN_LOONGSON2E) {
17532 gen_loongson_integer(ctx, op1, rd, rs, rt);
17533 } else {
17534 generate_exception_end(ctx, EXCP_RI);
17535 }
17536 break;
17537 case OPC_LX_DSP:
17538 op2 = MASK_LX(ctx->opcode);
17539 switch (op2) {
17540 #if defined(TARGET_MIPS64)
17541 case OPC_LDX:
17542 #endif
17543 case OPC_LBUX:
17544 case OPC_LHX:
17545 case OPC_LWX:
17546 gen_mipsdsp_ld(ctx, op2, rd, rs, rt);
17547 break;
17548 default: /* Invalid */
17549 MIPS_INVAL("MASK LX");
17550 generate_exception_end(ctx, EXCP_RI);
17551 break;
17552 }
17553 break;
17554 case OPC_ABSQ_S_PH_DSP:
17555 op2 = MASK_ABSQ_S_PH(ctx->opcode);
17556 switch (op2) {
17557 case OPC_ABSQ_S_QB:
17558 case OPC_ABSQ_S_PH:
17559 case OPC_ABSQ_S_W:
17560 case OPC_PRECEQ_W_PHL:
17561 case OPC_PRECEQ_W_PHR:
17562 case OPC_PRECEQU_PH_QBL:
17563 case OPC_PRECEQU_PH_QBR:
17564 case OPC_PRECEQU_PH_QBLA:
17565 case OPC_PRECEQU_PH_QBRA:
17566 case OPC_PRECEU_PH_QBL:
17567 case OPC_PRECEU_PH_QBR:
17568 case OPC_PRECEU_PH_QBLA:
17569 case OPC_PRECEU_PH_QBRA:
17570 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17571 break;
17572 case OPC_BITREV:
17573 case OPC_REPL_QB:
17574 case OPC_REPLV_QB:
17575 case OPC_REPL_PH:
17576 case OPC_REPLV_PH:
17577 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt);
17578 break;
17579 default:
17580 MIPS_INVAL("MASK ABSQ_S.PH");
17581 generate_exception_end(ctx, EXCP_RI);
17582 break;
17583 }
17584 break;
17585 case OPC_ADDU_QB_DSP:
17586 op2 = MASK_ADDU_QB(ctx->opcode);
17587 switch (op2) {
17588 case OPC_ADDQ_PH:
17589 case OPC_ADDQ_S_PH:
17590 case OPC_ADDQ_S_W:
17591 case OPC_ADDU_QB:
17592 case OPC_ADDU_S_QB:
17593 case OPC_ADDU_PH:
17594 case OPC_ADDU_S_PH:
17595 case OPC_SUBQ_PH:
17596 case OPC_SUBQ_S_PH:
17597 case OPC_SUBQ_S_W:
17598 case OPC_SUBU_QB:
17599 case OPC_SUBU_S_QB:
17600 case OPC_SUBU_PH:
17601 case OPC_SUBU_S_PH:
17602 case OPC_ADDSC:
17603 case OPC_ADDWC:
17604 case OPC_MODSUB:
17605 case OPC_RADDU_W_QB:
17606 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17607 break;
17608 case OPC_MULEU_S_PH_QBL:
17609 case OPC_MULEU_S_PH_QBR:
17610 case OPC_MULQ_RS_PH:
17611 case OPC_MULEQ_S_W_PHL:
17612 case OPC_MULEQ_S_W_PHR:
17613 case OPC_MULQ_S_PH:
17614 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
17615 break;
17616 default: /* Invalid */
17617 MIPS_INVAL("MASK ADDU.QB");
17618 generate_exception_end(ctx, EXCP_RI);
17619 break;
17620
17621 }
17622 break;
17623 case OPC_CMPU_EQ_QB_DSP:
17624 op2 = MASK_CMPU_EQ_QB(ctx->opcode);
17625 switch (op2) {
17626 case OPC_PRECR_SRA_PH_W:
17627 case OPC_PRECR_SRA_R_PH_W:
17628 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd);
17629 break;
17630 case OPC_PRECR_QB_PH:
17631 case OPC_PRECRQ_QB_PH:
17632 case OPC_PRECRQ_PH_W:
17633 case OPC_PRECRQ_RS_PH_W:
17634 case OPC_PRECRQU_S_QB_PH:
17635 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17636 break;
17637 case OPC_CMPU_EQ_QB:
17638 case OPC_CMPU_LT_QB:
17639 case OPC_CMPU_LE_QB:
17640 case OPC_CMP_EQ_PH:
17641 case OPC_CMP_LT_PH:
17642 case OPC_CMP_LE_PH:
17643 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0);
17644 break;
17645 case OPC_CMPGU_EQ_QB:
17646 case OPC_CMPGU_LT_QB:
17647 case OPC_CMPGU_LE_QB:
17648 case OPC_CMPGDU_EQ_QB:
17649 case OPC_CMPGDU_LT_QB:
17650 case OPC_CMPGDU_LE_QB:
17651 case OPC_PICK_QB:
17652 case OPC_PICK_PH:
17653 case OPC_PACKRL_PH:
17654 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1);
17655 break;
17656 default: /* Invalid */
17657 MIPS_INVAL("MASK CMPU.EQ.QB");
17658 generate_exception_end(ctx, EXCP_RI);
17659 break;
17660 }
17661 break;
17662 case OPC_SHLL_QB_DSP:
17663 gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
17664 break;
17665 case OPC_DPA_W_PH_DSP:
17666 op2 = MASK_DPA_W_PH(ctx->opcode);
17667 switch (op2) {
17668 case OPC_DPAU_H_QBL:
17669 case OPC_DPAU_H_QBR:
17670 case OPC_DPSU_H_QBL:
17671 case OPC_DPSU_H_QBR:
17672 case OPC_DPA_W_PH:
17673 case OPC_DPAX_W_PH:
17674 case OPC_DPAQ_S_W_PH:
17675 case OPC_DPAQX_S_W_PH:
17676 case OPC_DPAQX_SA_W_PH:
17677 case OPC_DPS_W_PH:
17678 case OPC_DPSX_W_PH:
17679 case OPC_DPSQ_S_W_PH:
17680 case OPC_DPSQX_S_W_PH:
17681 case OPC_DPSQX_SA_W_PH:
17682 case OPC_MULSAQ_S_W_PH:
17683 case OPC_DPAQ_SA_L_W:
17684 case OPC_DPSQ_SA_L_W:
17685 case OPC_MAQ_S_W_PHL:
17686 case OPC_MAQ_S_W_PHR:
17687 case OPC_MAQ_SA_W_PHL:
17688 case OPC_MAQ_SA_W_PHR:
17689 case OPC_MULSA_W_PH:
17690 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
17691 break;
17692 default: /* Invalid */
17693 MIPS_INVAL("MASK DPAW.PH");
17694 generate_exception_end(ctx, EXCP_RI);
17695 break;
17696 }
17697 break;
17698 case OPC_INSV_DSP:
17699 op2 = MASK_INSV(ctx->opcode);
17700 switch (op2) {
17701 case OPC_INSV:
17702 check_dsp(ctx);
17703 {
17704 TCGv t0, t1;
17705
17706 if (rt == 0) {
17707 break;
17708 }
17709
17710 t0 = tcg_temp_new();
17711 t1 = tcg_temp_new();
17712
17713 gen_load_gpr(t0, rt);
17714 gen_load_gpr(t1, rs);
17715
17716 gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0);
17717
17718 tcg_temp_free(t0);
17719 tcg_temp_free(t1);
17720 break;
17721 }
17722 default: /* Invalid */
17723 MIPS_INVAL("MASK INSV");
17724 generate_exception_end(ctx, EXCP_RI);
17725 break;
17726 }
17727 break;
17728 case OPC_APPEND_DSP:
17729 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd);
17730 break;
17731 case OPC_EXTR_W_DSP:
17732 op2 = MASK_EXTR_W(ctx->opcode);
17733 switch (op2) {
17734 case OPC_EXTR_W:
17735 case OPC_EXTR_R_W:
17736 case OPC_EXTR_RS_W:
17737 case OPC_EXTR_S_H:
17738 case OPC_EXTRV_S_H:
17739 case OPC_EXTRV_W:
17740 case OPC_EXTRV_R_W:
17741 case OPC_EXTRV_RS_W:
17742 case OPC_EXTP:
17743 case OPC_EXTPV:
17744 case OPC_EXTPDP:
17745 case OPC_EXTPDPV:
17746 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1);
17747 break;
17748 case OPC_RDDSP:
17749 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 1);
17750 break;
17751 case OPC_SHILO:
17752 case OPC_SHILOV:
17753 case OPC_MTHLIP:
17754 case OPC_WRDSP:
17755 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0);
17756 break;
17757 default: /* Invalid */
17758 MIPS_INVAL("MASK EXTR.W");
17759 generate_exception_end(ctx, EXCP_RI);
17760 break;
17761 }
17762 break;
17763 #if defined(TARGET_MIPS64)
17764 case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E:
17765 case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E:
17766 case OPC_DMOD_G_2E ... OPC_DMODU_G_2E:
17767 check_insn(ctx, INSN_LOONGSON2E);
17768 gen_loongson_integer(ctx, op1, rd, rs, rt);
17769 break;
17770 case OPC_ABSQ_S_QH_DSP:
17771 op2 = MASK_ABSQ_S_QH(ctx->opcode);
17772 switch (op2) {
17773 case OPC_PRECEQ_L_PWL:
17774 case OPC_PRECEQ_L_PWR:
17775 case OPC_PRECEQ_PW_QHL:
17776 case OPC_PRECEQ_PW_QHR:
17777 case OPC_PRECEQ_PW_QHLA:
17778 case OPC_PRECEQ_PW_QHRA:
17779 case OPC_PRECEQU_QH_OBL:
17780 case OPC_PRECEQU_QH_OBR:
17781 case OPC_PRECEQU_QH_OBLA:
17782 case OPC_PRECEQU_QH_OBRA:
17783 case OPC_PRECEU_QH_OBL:
17784 case OPC_PRECEU_QH_OBR:
17785 case OPC_PRECEU_QH_OBLA:
17786 case OPC_PRECEU_QH_OBRA:
17787 case OPC_ABSQ_S_OB:
17788 case OPC_ABSQ_S_PW:
17789 case OPC_ABSQ_S_QH:
17790 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17791 break;
17792 case OPC_REPL_OB:
17793 case OPC_REPL_PW:
17794 case OPC_REPL_QH:
17795 case OPC_REPLV_OB:
17796 case OPC_REPLV_PW:
17797 case OPC_REPLV_QH:
17798 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt);
17799 break;
17800 default: /* Invalid */
17801 MIPS_INVAL("MASK ABSQ_S.QH");
17802 generate_exception_end(ctx, EXCP_RI);
17803 break;
17804 }
17805 break;
17806 case OPC_ADDU_OB_DSP:
17807 op2 = MASK_ADDU_OB(ctx->opcode);
17808 switch (op2) {
17809 case OPC_RADDU_L_OB:
17810 case OPC_SUBQ_PW:
17811 case OPC_SUBQ_S_PW:
17812 case OPC_SUBQ_QH:
17813 case OPC_SUBQ_S_QH:
17814 case OPC_SUBU_OB:
17815 case OPC_SUBU_S_OB:
17816 case OPC_SUBU_QH:
17817 case OPC_SUBU_S_QH:
17818 case OPC_SUBUH_OB:
17819 case OPC_SUBUH_R_OB:
17820 case OPC_ADDQ_PW:
17821 case OPC_ADDQ_S_PW:
17822 case OPC_ADDQ_QH:
17823 case OPC_ADDQ_S_QH:
17824 case OPC_ADDU_OB:
17825 case OPC_ADDU_S_OB:
17826 case OPC_ADDU_QH:
17827 case OPC_ADDU_S_QH:
17828 case OPC_ADDUH_OB:
17829 case OPC_ADDUH_R_OB:
17830 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17831 break;
17832 case OPC_MULEQ_S_PW_QHL:
17833 case OPC_MULEQ_S_PW_QHR:
17834 case OPC_MULEU_S_QH_OBL:
17835 case OPC_MULEU_S_QH_OBR:
17836 case OPC_MULQ_RS_QH:
17837 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
17838 break;
17839 default: /* Invalid */
17840 MIPS_INVAL("MASK ADDU.OB");
17841 generate_exception_end(ctx, EXCP_RI);
17842 break;
17843 }
17844 break;
17845 case OPC_CMPU_EQ_OB_DSP:
17846 op2 = MASK_CMPU_EQ_OB(ctx->opcode);
17847 switch (op2) {
17848 case OPC_PRECR_SRA_QH_PW:
17849 case OPC_PRECR_SRA_R_QH_PW:
17850 /* Return value is rt. */
17851 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd);
17852 break;
17853 case OPC_PRECR_OB_QH:
17854 case OPC_PRECRQ_OB_QH:
17855 case OPC_PRECRQ_PW_L:
17856 case OPC_PRECRQ_QH_PW:
17857 case OPC_PRECRQ_RS_QH_PW:
17858 case OPC_PRECRQU_S_OB_QH:
17859 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17860 break;
17861 case OPC_CMPU_EQ_OB:
17862 case OPC_CMPU_LT_OB:
17863 case OPC_CMPU_LE_OB:
17864 case OPC_CMP_EQ_QH:
17865 case OPC_CMP_LT_QH:
17866 case OPC_CMP_LE_QH:
17867 case OPC_CMP_EQ_PW:
17868 case OPC_CMP_LT_PW:
17869 case OPC_CMP_LE_PW:
17870 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0);
17871 break;
17872 case OPC_CMPGDU_EQ_OB:
17873 case OPC_CMPGDU_LT_OB:
17874 case OPC_CMPGDU_LE_OB:
17875 case OPC_CMPGU_EQ_OB:
17876 case OPC_CMPGU_LT_OB:
17877 case OPC_CMPGU_LE_OB:
17878 case OPC_PACKRL_PW:
17879 case OPC_PICK_OB:
17880 case OPC_PICK_PW:
17881 case OPC_PICK_QH:
17882 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1);
17883 break;
17884 default: /* Invalid */
17885 MIPS_INVAL("MASK CMPU_EQ.OB");
17886 generate_exception_end(ctx, EXCP_RI);
17887 break;
17888 }
17889 break;
17890 case OPC_DAPPEND_DSP:
17891 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd);
17892 break;
17893 case OPC_DEXTR_W_DSP:
17894 op2 = MASK_DEXTR_W(ctx->opcode);
17895 switch (op2) {
17896 case OPC_DEXTP:
17897 case OPC_DEXTPDP:
17898 case OPC_DEXTPDPV:
17899 case OPC_DEXTPV:
17900 case OPC_DEXTR_L:
17901 case OPC_DEXTR_R_L:
17902 case OPC_DEXTR_RS_L:
17903 case OPC_DEXTR_W:
17904 case OPC_DEXTR_R_W:
17905 case OPC_DEXTR_RS_W:
17906 case OPC_DEXTR_S_H:
17907 case OPC_DEXTRV_L:
17908 case OPC_DEXTRV_R_L:
17909 case OPC_DEXTRV_RS_L:
17910 case OPC_DEXTRV_S_H:
17911 case OPC_DEXTRV_W:
17912 case OPC_DEXTRV_R_W:
17913 case OPC_DEXTRV_RS_W:
17914 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1);
17915 break;
17916 case OPC_DMTHLIP:
17917 case OPC_DSHILO:
17918 case OPC_DSHILOV:
17919 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0);
17920 break;
17921 default: /* Invalid */
17922 MIPS_INVAL("MASK EXTR.W");
17923 generate_exception_end(ctx, EXCP_RI);
17924 break;
17925 }
17926 break;
17927 case OPC_DPAQ_W_QH_DSP:
17928 op2 = MASK_DPAQ_W_QH(ctx->opcode);
17929 switch (op2) {
17930 case OPC_DPAU_H_OBL:
17931 case OPC_DPAU_H_OBR:
17932 case OPC_DPSU_H_OBL:
17933 case OPC_DPSU_H_OBR:
17934 case OPC_DPA_W_QH:
17935 case OPC_DPAQ_S_W_QH:
17936 case OPC_DPS_W_QH:
17937 case OPC_DPSQ_S_W_QH:
17938 case OPC_MULSAQ_S_W_QH:
17939 case OPC_DPAQ_SA_L_PW:
17940 case OPC_DPSQ_SA_L_PW:
17941 case OPC_MULSAQ_S_L_PW:
17942 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
17943 break;
17944 case OPC_MAQ_S_W_QHLL:
17945 case OPC_MAQ_S_W_QHLR:
17946 case OPC_MAQ_S_W_QHRL:
17947 case OPC_MAQ_S_W_QHRR:
17948 case OPC_MAQ_SA_W_QHLL:
17949 case OPC_MAQ_SA_W_QHLR:
17950 case OPC_MAQ_SA_W_QHRL:
17951 case OPC_MAQ_SA_W_QHRR:
17952 case OPC_MAQ_S_L_PWL:
17953 case OPC_MAQ_S_L_PWR:
17954 case OPC_DMADD:
17955 case OPC_DMADDU:
17956 case OPC_DMSUB:
17957 case OPC_DMSUBU:
17958 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
17959 break;
17960 default: /* Invalid */
17961 MIPS_INVAL("MASK DPAQ.W.QH");
17962 generate_exception_end(ctx, EXCP_RI);
17963 break;
17964 }
17965 break;
17966 case OPC_DINSV_DSP:
17967 op2 = MASK_INSV(ctx->opcode);
17968 switch (op2) {
17969 case OPC_DINSV:
17970 {
17971 TCGv t0, t1;
17972
17973 if (rt == 0) {
17974 break;
17975 }
17976 check_dsp(ctx);
17977
17978 t0 = tcg_temp_new();
17979 t1 = tcg_temp_new();
17980
17981 gen_load_gpr(t0, rt);
17982 gen_load_gpr(t1, rs);
17983
17984 gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0);
17985
17986 tcg_temp_free(t0);
17987 tcg_temp_free(t1);
17988 break;
17989 }
17990 default: /* Invalid */
17991 MIPS_INVAL("MASK DINSV");
17992 generate_exception_end(ctx, EXCP_RI);
17993 break;
17994 }
17995 break;
17996 case OPC_SHLL_OB_DSP:
17997 gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
17998 break;
17999 #endif
18000 default: /* Invalid */
18001 MIPS_INVAL("special3_legacy");
18002 generate_exception_end(ctx, EXCP_RI);
18003 break;
18004 }
18005 }
18006
18007 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
18008 {
18009 int rs, rt, rd, sa;
18010 uint32_t op1, op2;
18011
18012 rs = (ctx->opcode >> 21) & 0x1f;
18013 rt = (ctx->opcode >> 16) & 0x1f;
18014 rd = (ctx->opcode >> 11) & 0x1f;
18015 sa = (ctx->opcode >> 6) & 0x1f;
18016
18017 op1 = MASK_SPECIAL3(ctx->opcode);
18018 switch (op1) {
18019 case OPC_EXT:
18020 case OPC_INS:
18021 check_insn(ctx, ISA_MIPS32R2);
18022 gen_bitops(ctx, op1, rt, rs, sa, rd);
18023 break;
18024 case OPC_BSHFL:
18025 op2 = MASK_BSHFL(ctx->opcode);
18026 switch (op2) {
18027 case OPC_ALIGN ... OPC_ALIGN_END:
18028 case OPC_BITSWAP:
18029 check_insn(ctx, ISA_MIPS32R6);
18030 decode_opc_special3_r6(env, ctx);
18031 break;
18032 default:
18033 check_insn(ctx, ISA_MIPS32R2);
18034 gen_bshfl(ctx, op2, rt, rd);
18035 break;
18036 }
18037 break;
18038 #if defined(TARGET_MIPS64)
18039 case OPC_DEXTM ... OPC_DEXT:
18040 case OPC_DINSM ... OPC_DINS:
18041 check_insn(ctx, ISA_MIPS64R2);
18042 check_mips_64(ctx);
18043 gen_bitops(ctx, op1, rt, rs, sa, rd);
18044 break;
18045 case OPC_DBSHFL:
18046 op2 = MASK_DBSHFL(ctx->opcode);
18047 switch (op2) {
18048 case OPC_DALIGN ... OPC_DALIGN_END:
18049 case OPC_DBITSWAP:
18050 check_insn(ctx, ISA_MIPS32R6);
18051 decode_opc_special3_r6(env, ctx);
18052 break;
18053 default:
18054 check_insn(ctx, ISA_MIPS64R2);
18055 check_mips_64(ctx);
18056 op2 = MASK_DBSHFL(ctx->opcode);
18057 gen_bshfl(ctx, op2, rt, rd);
18058 break;
18059 }
18060 break;
18061 #endif
18062 case OPC_RDHWR:
18063 gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3));
18064 break;
18065 case OPC_FORK:
18066 check_insn(ctx, ASE_MT);
18067 {
18068 TCGv t0 = tcg_temp_new();
18069 TCGv t1 = tcg_temp_new();
18070
18071 gen_load_gpr(t0, rt);
18072 gen_load_gpr(t1, rs);
18073 gen_helper_fork(t0, t1);
18074 tcg_temp_free(t0);
18075 tcg_temp_free(t1);
18076 }
18077 break;
18078 case OPC_YIELD:
18079 check_insn(ctx, ASE_MT);
18080 {
18081 TCGv t0 = tcg_temp_new();
18082
18083 gen_load_gpr(t0, rs);
18084 gen_helper_yield(t0, cpu_env, t0);
18085 gen_store_gpr(t0, rd);
18086 tcg_temp_free(t0);
18087 }
18088 break;
18089 default:
18090 if (ctx->insn_flags & ISA_MIPS32R6) {
18091 decode_opc_special3_r6(env, ctx);
18092 } else {
18093 decode_opc_special3_legacy(env, ctx);
18094 }
18095 }
18096 }
18097
18098 /* MIPS SIMD Architecture (MSA) */
18099 static inline int check_msa_access(DisasContext *ctx)
18100 {
18101 if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
18102 !(ctx->hflags & MIPS_HFLAG_F64))) {
18103 generate_exception_end(ctx, EXCP_RI);
18104 return 0;
18105 }
18106
18107 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
18108 if (ctx->insn_flags & ASE_MSA) {
18109 generate_exception_end(ctx, EXCP_MSADIS);
18110 return 0;
18111 } else {
18112 generate_exception_end(ctx, EXCP_RI);
18113 return 0;
18114 }
18115 }
18116 return 1;
18117 }
18118
18119 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt)
18120 {
18121 /* generates tcg ops to check if any element is 0 */
18122 /* Note this function only works with MSA_WRLEN = 128 */
18123 uint64_t eval_zero_or_big = 0;
18124 uint64_t eval_big = 0;
18125 TCGv_i64 t0 = tcg_temp_new_i64();
18126 TCGv_i64 t1 = tcg_temp_new_i64();
18127 switch (df) {
18128 case DF_BYTE:
18129 eval_zero_or_big = 0x0101010101010101ULL;
18130 eval_big = 0x8080808080808080ULL;
18131 break;
18132 case DF_HALF:
18133 eval_zero_or_big = 0x0001000100010001ULL;
18134 eval_big = 0x8000800080008000ULL;
18135 break;
18136 case DF_WORD:
18137 eval_zero_or_big = 0x0000000100000001ULL;
18138 eval_big = 0x8000000080000000ULL;
18139 break;
18140 case DF_DOUBLE:
18141 eval_zero_or_big = 0x0000000000000001ULL;
18142 eval_big = 0x8000000000000000ULL;
18143 break;
18144 }
18145 tcg_gen_subi_i64(t0, msa_wr_d[wt<<1], eval_zero_or_big);
18146 tcg_gen_andc_i64(t0, t0, msa_wr_d[wt<<1]);
18147 tcg_gen_andi_i64(t0, t0, eval_big);
18148 tcg_gen_subi_i64(t1, msa_wr_d[(wt<<1)+1], eval_zero_or_big);
18149 tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt<<1)+1]);
18150 tcg_gen_andi_i64(t1, t1, eval_big);
18151 tcg_gen_or_i64(t0, t0, t1);
18152 /* if all bits are zero then all elements are not zero */
18153 /* if some bit is non-zero then some element is zero */
18154 tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0);
18155 tcg_gen_trunc_i64_tl(tresult, t0);
18156 tcg_temp_free_i64(t0);
18157 tcg_temp_free_i64(t1);
18158 }
18159
18160 static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
18161 {
18162 uint8_t df = (ctx->opcode >> 21) & 0x3;
18163 uint8_t wt = (ctx->opcode >> 16) & 0x1f;
18164 int64_t s16 = (int16_t)ctx->opcode;
18165
18166 check_msa_access(ctx);
18167
18168 if (ctx->insn_flags & ISA_MIPS32R6 && ctx->hflags & MIPS_HFLAG_BMASK) {
18169 generate_exception_end(ctx, EXCP_RI);
18170 return;
18171 }
18172 switch (op1) {
18173 case OPC_BZ_V:
18174 case OPC_BNZ_V:
18175 {
18176 TCGv_i64 t0 = tcg_temp_new_i64();
18177 tcg_gen_or_i64(t0, msa_wr_d[wt<<1], msa_wr_d[(wt<<1)+1]);
18178 tcg_gen_setcondi_i64((op1 == OPC_BZ_V) ?
18179 TCG_COND_EQ : TCG_COND_NE, t0, t0, 0);
18180 tcg_gen_trunc_i64_tl(bcond, t0);
18181 tcg_temp_free_i64(t0);
18182 }
18183 break;
18184 case OPC_BZ_B:
18185 case OPC_BZ_H:
18186 case OPC_BZ_W:
18187 case OPC_BZ_D:
18188 gen_check_zero_element(bcond, df, wt);
18189 break;
18190 case OPC_BNZ_B:
18191 case OPC_BNZ_H:
18192 case OPC_BNZ_W:
18193 case OPC_BNZ_D:
18194 gen_check_zero_element(bcond, df, wt);
18195 tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
18196 break;
18197 }
18198
18199 ctx->btarget = ctx->pc + (s16 << 2) + 4;
18200
18201 ctx->hflags |= MIPS_HFLAG_BC;
18202 ctx->hflags |= MIPS_HFLAG_BDS32;
18203 }
18204
18205 static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
18206 {
18207 #define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
18208 uint8_t i8 = (ctx->opcode >> 16) & 0xff;
18209 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18210 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18211
18212 TCGv_i32 twd = tcg_const_i32(wd);
18213 TCGv_i32 tws = tcg_const_i32(ws);
18214 TCGv_i32 ti8 = tcg_const_i32(i8);
18215
18216 switch (MASK_MSA_I8(ctx->opcode)) {
18217 case OPC_ANDI_B:
18218 gen_helper_msa_andi_b(cpu_env, twd, tws, ti8);
18219 break;
18220 case OPC_ORI_B:
18221 gen_helper_msa_ori_b(cpu_env, twd, tws, ti8);
18222 break;
18223 case OPC_NORI_B:
18224 gen_helper_msa_nori_b(cpu_env, twd, tws, ti8);
18225 break;
18226 case OPC_XORI_B:
18227 gen_helper_msa_xori_b(cpu_env, twd, tws, ti8);
18228 break;
18229 case OPC_BMNZI_B:
18230 gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8);
18231 break;
18232 case OPC_BMZI_B:
18233 gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8);
18234 break;
18235 case OPC_BSELI_B:
18236 gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
18237 break;
18238 case OPC_SHF_B:
18239 case OPC_SHF_H:
18240 case OPC_SHF_W:
18241 {
18242 uint8_t df = (ctx->opcode >> 24) & 0x3;
18243 if (df == DF_DOUBLE) {
18244 generate_exception_end(ctx, EXCP_RI);
18245 } else {
18246 TCGv_i32 tdf = tcg_const_i32(df);
18247 gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
18248 tcg_temp_free_i32(tdf);
18249 }
18250 }
18251 break;
18252 default:
18253 MIPS_INVAL("MSA instruction");
18254 generate_exception_end(ctx, EXCP_RI);
18255 break;
18256 }
18257
18258 tcg_temp_free_i32(twd);
18259 tcg_temp_free_i32(tws);
18260 tcg_temp_free_i32(ti8);
18261 }
18262
18263 static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
18264 {
18265 #define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
18266 uint8_t df = (ctx->opcode >> 21) & 0x3;
18267 int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
18268 uint8_t u5 = (ctx->opcode >> 16) & 0x1f;
18269 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18270 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18271
18272 TCGv_i32 tdf = tcg_const_i32(df);
18273 TCGv_i32 twd = tcg_const_i32(wd);
18274 TCGv_i32 tws = tcg_const_i32(ws);
18275 TCGv_i32 timm = tcg_temp_new_i32();
18276 tcg_gen_movi_i32(timm, u5);
18277
18278 switch (MASK_MSA_I5(ctx->opcode)) {
18279 case OPC_ADDVI_df:
18280 gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm);
18281 break;
18282 case OPC_SUBVI_df:
18283 gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
18284 break;
18285 case OPC_MAXI_S_df:
18286 tcg_gen_movi_i32(timm, s5);
18287 gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm);
18288 break;
18289 case OPC_MAXI_U_df:
18290 gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm);
18291 break;
18292 case OPC_MINI_S_df:
18293 tcg_gen_movi_i32(timm, s5);
18294 gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm);
18295 break;
18296 case OPC_MINI_U_df:
18297 gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm);
18298 break;
18299 case OPC_CEQI_df:
18300 tcg_gen_movi_i32(timm, s5);
18301 gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm);
18302 break;
18303 case OPC_CLTI_S_df:
18304 tcg_gen_movi_i32(timm, s5);
18305 gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm);
18306 break;
18307 case OPC_CLTI_U_df:
18308 gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm);
18309 break;
18310 case OPC_CLEI_S_df:
18311 tcg_gen_movi_i32(timm, s5);
18312 gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm);
18313 break;
18314 case OPC_CLEI_U_df:
18315 gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
18316 break;
18317 case OPC_LDI_df:
18318 {
18319 int32_t s10 = sextract32(ctx->opcode, 11, 10);
18320 tcg_gen_movi_i32(timm, s10);
18321 gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
18322 }
18323 break;
18324 default:
18325 MIPS_INVAL("MSA instruction");
18326 generate_exception_end(ctx, EXCP_RI);
18327 break;
18328 }
18329
18330 tcg_temp_free_i32(tdf);
18331 tcg_temp_free_i32(twd);
18332 tcg_temp_free_i32(tws);
18333 tcg_temp_free_i32(timm);
18334 }
18335
18336 static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
18337 {
18338 #define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
18339 uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
18340 uint32_t df = 0, m = 0;
18341 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18342 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18343
18344 TCGv_i32 tdf;
18345 TCGv_i32 tm;
18346 TCGv_i32 twd;
18347 TCGv_i32 tws;
18348
18349 if ((dfm & 0x40) == 0x00) {
18350 m = dfm & 0x3f;
18351 df = DF_DOUBLE;
18352 } else if ((dfm & 0x60) == 0x40) {
18353 m = dfm & 0x1f;
18354 df = DF_WORD;
18355 } else if ((dfm & 0x70) == 0x60) {
18356 m = dfm & 0x0f;
18357 df = DF_HALF;
18358 } else if ((dfm & 0x78) == 0x70) {
18359 m = dfm & 0x7;
18360 df = DF_BYTE;
18361 } else {
18362 generate_exception_end(ctx, EXCP_RI);
18363 return;
18364 }
18365
18366 tdf = tcg_const_i32(df);
18367 tm = tcg_const_i32(m);
18368 twd = tcg_const_i32(wd);
18369 tws = tcg_const_i32(ws);
18370
18371 switch (MASK_MSA_BIT(ctx->opcode)) {
18372 case OPC_SLLI_df:
18373 gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm);
18374 break;
18375 case OPC_SRAI_df:
18376 gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm);
18377 break;
18378 case OPC_SRLI_df:
18379 gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm);
18380 break;
18381 case OPC_BCLRI_df:
18382 gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm);
18383 break;
18384 case OPC_BSETI_df:
18385 gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm);
18386 break;
18387 case OPC_BNEGI_df:
18388 gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm);
18389 break;
18390 case OPC_BINSLI_df:
18391 gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm);
18392 break;
18393 case OPC_BINSRI_df:
18394 gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm);
18395 break;
18396 case OPC_SAT_S_df:
18397 gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm);
18398 break;
18399 case OPC_SAT_U_df:
18400 gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm);
18401 break;
18402 case OPC_SRARI_df:
18403 gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm);
18404 break;
18405 case OPC_SRLRI_df:
18406 gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm);
18407 break;
18408 default:
18409 MIPS_INVAL("MSA instruction");
18410 generate_exception_end(ctx, EXCP_RI);
18411 break;
18412 }
18413
18414 tcg_temp_free_i32(tdf);
18415 tcg_temp_free_i32(tm);
18416 tcg_temp_free_i32(twd);
18417 tcg_temp_free_i32(tws);
18418 }
18419
18420 static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
18421 {
18422 #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
18423 uint8_t df = (ctx->opcode >> 21) & 0x3;
18424 uint8_t wt = (ctx->opcode >> 16) & 0x1f;
18425 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18426 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18427
18428 TCGv_i32 tdf = tcg_const_i32(df);
18429 TCGv_i32 twd = tcg_const_i32(wd);
18430 TCGv_i32 tws = tcg_const_i32(ws);
18431 TCGv_i32 twt = tcg_const_i32(wt);
18432
18433 switch (MASK_MSA_3R(ctx->opcode)) {
18434 case OPC_SLL_df:
18435 gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt);
18436 break;
18437 case OPC_ADDV_df:
18438 gen_helper_msa_addv_df(cpu_env, tdf, twd, tws, twt);
18439 break;
18440 case OPC_CEQ_df:
18441 gen_helper_msa_ceq_df(cpu_env, tdf, twd, tws, twt);
18442 break;
18443 case OPC_ADD_A_df:
18444 gen_helper_msa_add_a_df(cpu_env, tdf, twd, tws, twt);
18445 break;
18446 case OPC_SUBS_S_df:
18447 gen_helper_msa_subs_s_df(cpu_env, tdf, twd, tws, twt);
18448 break;
18449 case OPC_MULV_df:
18450 gen_helper_msa_mulv_df(cpu_env, tdf, twd, tws, twt);
18451 break;
18452 case OPC_SLD_df:
18453 gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt);
18454 break;
18455 case OPC_VSHF_df:
18456 gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
18457 break;
18458 case OPC_SRA_df:
18459 gen_helper_msa_sra_df(cpu_env, tdf, twd, tws, twt);
18460 break;
18461 case OPC_SUBV_df:
18462 gen_helper_msa_subv_df(cpu_env, tdf, twd, tws, twt);
18463 break;
18464 case OPC_ADDS_A_df:
18465 gen_helper_msa_adds_a_df(cpu_env, tdf, twd, tws, twt);
18466 break;
18467 case OPC_SUBS_U_df:
18468 gen_helper_msa_subs_u_df(cpu_env, tdf, twd, tws, twt);
18469 break;
18470 case OPC_MADDV_df:
18471 gen_helper_msa_maddv_df(cpu_env, tdf, twd, tws, twt);
18472 break;
18473 case OPC_SPLAT_df:
18474 gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
18475 break;
18476 case OPC_SRAR_df:
18477 gen_helper_msa_srar_df(cpu_env, tdf, twd, tws, twt);
18478 break;
18479 case OPC_SRL_df:
18480 gen_helper_msa_srl_df(cpu_env, tdf, twd, tws, twt);
18481 break;
18482 case OPC_MAX_S_df:
18483 gen_helper_msa_max_s_df(cpu_env, tdf, twd, tws, twt);
18484 break;
18485 case OPC_CLT_S_df:
18486 gen_helper_msa_clt_s_df(cpu_env, tdf, twd, tws, twt);
18487 break;
18488 case OPC_ADDS_S_df:
18489 gen_helper_msa_adds_s_df(cpu_env, tdf, twd, tws, twt);
18490 break;
18491 case OPC_SUBSUS_U_df:
18492 gen_helper_msa_subsus_u_df(cpu_env, tdf, twd, tws, twt);
18493 break;
18494 case OPC_MSUBV_df:
18495 gen_helper_msa_msubv_df(cpu_env, tdf, twd, tws, twt);
18496 break;
18497 case OPC_PCKEV_df:
18498 gen_helper_msa_pckev_df(cpu_env, tdf, twd, tws, twt);
18499 break;
18500 case OPC_SRLR_df:
18501 gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt);
18502 break;
18503 case OPC_BCLR_df:
18504 gen_helper_msa_bclr_df(cpu_env, tdf, twd, tws, twt);
18505 break;
18506 case OPC_MAX_U_df:
18507 gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt);
18508 break;
18509 case OPC_CLT_U_df:
18510 gen_helper_msa_clt_u_df(cpu_env, tdf, twd, tws, twt);
18511 break;
18512 case OPC_ADDS_U_df:
18513 gen_helper_msa_adds_u_df(cpu_env, tdf, twd, tws, twt);
18514 break;
18515 case OPC_SUBSUU_S_df:
18516 gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt);
18517 break;
18518 case OPC_PCKOD_df:
18519 gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt);
18520 break;
18521 case OPC_BSET_df:
18522 gen_helper_msa_bset_df(cpu_env, tdf, twd, tws, twt);
18523 break;
18524 case OPC_MIN_S_df:
18525 gen_helper_msa_min_s_df(cpu_env, tdf, twd, tws, twt);
18526 break;
18527 case OPC_CLE_S_df:
18528 gen_helper_msa_cle_s_df(cpu_env, tdf, twd, tws, twt);
18529 break;
18530 case OPC_AVE_S_df:
18531 gen_helper_msa_ave_s_df(cpu_env, tdf, twd, tws, twt);
18532 break;
18533 case OPC_ASUB_S_df:
18534 gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt);
18535 break;
18536 case OPC_DIV_S_df:
18537 gen_helper_msa_div_s_df(cpu_env, tdf, twd, tws, twt);
18538 break;
18539 case OPC_ILVL_df:
18540 gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt);
18541 break;
18542 case OPC_BNEG_df:
18543 gen_helper_msa_bneg_df(cpu_env, tdf, twd, tws, twt);
18544 break;
18545 case OPC_MIN_U_df:
18546 gen_helper_msa_min_u_df(cpu_env, tdf, twd, tws, twt);
18547 break;
18548 case OPC_CLE_U_df:
18549 gen_helper_msa_cle_u_df(cpu_env, tdf, twd, tws, twt);
18550 break;
18551 case OPC_AVE_U_df:
18552 gen_helper_msa_ave_u_df(cpu_env, tdf, twd, tws, twt);
18553 break;
18554 case OPC_ASUB_U_df:
18555 gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt);
18556 break;
18557 case OPC_DIV_U_df:
18558 gen_helper_msa_div_u_df(cpu_env, tdf, twd, tws, twt);
18559 break;
18560 case OPC_ILVR_df:
18561 gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt);
18562 break;
18563 case OPC_BINSL_df:
18564 gen_helper_msa_binsl_df(cpu_env, tdf, twd, tws, twt);
18565 break;
18566 case OPC_MAX_A_df:
18567 gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt);
18568 break;
18569 case OPC_AVER_S_df:
18570 gen_helper_msa_aver_s_df(cpu_env, tdf, twd, tws, twt);
18571 break;
18572 case OPC_MOD_S_df:
18573 gen_helper_msa_mod_s_df(cpu_env, tdf, twd, tws, twt);
18574 break;
18575 case OPC_ILVEV_df:
18576 gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt);
18577 break;
18578 case OPC_BINSR_df:
18579 gen_helper_msa_binsr_df(cpu_env, tdf, twd, tws, twt);
18580 break;
18581 case OPC_MIN_A_df:
18582 gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt);
18583 break;
18584 case OPC_AVER_U_df:
18585 gen_helper_msa_aver_u_df(cpu_env, tdf, twd, tws, twt);
18586 break;
18587 case OPC_MOD_U_df:
18588 gen_helper_msa_mod_u_df(cpu_env, tdf, twd, tws, twt);
18589 break;
18590 case OPC_ILVOD_df:
18591 gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt);
18592 break;
18593
18594 case OPC_DOTP_S_df:
18595 case OPC_DOTP_U_df:
18596 case OPC_DPADD_S_df:
18597 case OPC_DPADD_U_df:
18598 case OPC_DPSUB_S_df:
18599 case OPC_HADD_S_df:
18600 case OPC_DPSUB_U_df:
18601 case OPC_HADD_U_df:
18602 case OPC_HSUB_S_df:
18603 case OPC_HSUB_U_df:
18604 if (df == DF_BYTE) {
18605 generate_exception_end(ctx, EXCP_RI);
18606 break;
18607 }
18608 switch (MASK_MSA_3R(ctx->opcode)) {
18609 case OPC_DOTP_S_df:
18610 gen_helper_msa_dotp_s_df(cpu_env, tdf, twd, tws, twt);
18611 break;
18612 case OPC_DOTP_U_df:
18613 gen_helper_msa_dotp_u_df(cpu_env, tdf, twd, tws, twt);
18614 break;
18615 case OPC_DPADD_S_df:
18616 gen_helper_msa_dpadd_s_df(cpu_env, tdf, twd, tws, twt);
18617 break;
18618 case OPC_DPADD_U_df:
18619 gen_helper_msa_dpadd_u_df(cpu_env, tdf, twd, tws, twt);
18620 break;
18621 case OPC_DPSUB_S_df:
18622 gen_helper_msa_dpsub_s_df(cpu_env, tdf, twd, tws, twt);
18623 break;
18624 case OPC_HADD_S_df:
18625 gen_helper_msa_hadd_s_df(cpu_env, tdf, twd, tws, twt);
18626 break;
18627 case OPC_DPSUB_U_df:
18628 gen_helper_msa_dpsub_u_df(cpu_env, tdf, twd, tws, twt);
18629 break;
18630 case OPC_HADD_U_df:
18631 gen_helper_msa_hadd_u_df(cpu_env, tdf, twd, tws, twt);
18632 break;
18633 case OPC_HSUB_S_df:
18634 gen_helper_msa_hsub_s_df(cpu_env, tdf, twd, tws, twt);
18635 break;
18636 case OPC_HSUB_U_df:
18637 gen_helper_msa_hsub_u_df(cpu_env, tdf, twd, tws, twt);
18638 break;
18639 }
18640 break;
18641 default:
18642 MIPS_INVAL("MSA instruction");
18643 generate_exception_end(ctx, EXCP_RI);
18644 break;
18645 }
18646 tcg_temp_free_i32(twd);
18647 tcg_temp_free_i32(tws);
18648 tcg_temp_free_i32(twt);
18649 tcg_temp_free_i32(tdf);
18650 }
18651
18652 static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
18653 {
18654 #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
18655 uint8_t source = (ctx->opcode >> 11) & 0x1f;
18656 uint8_t dest = (ctx->opcode >> 6) & 0x1f;
18657 TCGv telm = tcg_temp_new();
18658 TCGv_i32 tsr = tcg_const_i32(source);
18659 TCGv_i32 tdt = tcg_const_i32(dest);
18660
18661 switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
18662 case OPC_CTCMSA:
18663 gen_load_gpr(telm, source);
18664 gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
18665 break;
18666 case OPC_CFCMSA:
18667 gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
18668 gen_store_gpr(telm, dest);
18669 break;
18670 case OPC_MOVE_V:
18671 gen_helper_msa_move_v(cpu_env, tdt, tsr);
18672 break;
18673 default:
18674 MIPS_INVAL("MSA instruction");
18675 generate_exception_end(ctx, EXCP_RI);
18676 break;
18677 }
18678
18679 tcg_temp_free(telm);
18680 tcg_temp_free_i32(tdt);
18681 tcg_temp_free_i32(tsr);
18682 }
18683
18684 static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
18685 uint32_t n)
18686 {
18687 #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
18688 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18689 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18690
18691 TCGv_i32 tws = tcg_const_i32(ws);
18692 TCGv_i32 twd = tcg_const_i32(wd);
18693 TCGv_i32 tn = tcg_const_i32(n);
18694 TCGv_i32 tdf = tcg_const_i32(df);
18695
18696 switch (MASK_MSA_ELM(ctx->opcode)) {
18697 case OPC_SLDI_df:
18698 gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn);
18699 break;
18700 case OPC_SPLATI_df:
18701 gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn);
18702 break;
18703 case OPC_INSVE_df:
18704 gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn);
18705 break;
18706 case OPC_COPY_S_df:
18707 case OPC_COPY_U_df:
18708 case OPC_INSERT_df:
18709 #if !defined(TARGET_MIPS64)
18710 /* Double format valid only for MIPS64 */
18711 if (df == DF_DOUBLE) {
18712 generate_exception_end(ctx, EXCP_RI);
18713 break;
18714 }
18715 #endif
18716 switch (MASK_MSA_ELM(ctx->opcode)) {
18717 case OPC_COPY_S_df:
18718 gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn);
18719 break;
18720 case OPC_COPY_U_df:
18721 gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn);
18722 break;
18723 case OPC_INSERT_df:
18724 gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn);
18725 break;
18726 }
18727 break;
18728 default:
18729 MIPS_INVAL("MSA instruction");
18730 generate_exception_end(ctx, EXCP_RI);
18731 }
18732 tcg_temp_free_i32(twd);
18733 tcg_temp_free_i32(tws);
18734 tcg_temp_free_i32(tn);
18735 tcg_temp_free_i32(tdf);
18736 }
18737
18738 static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx)
18739 {
18740 uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
18741 uint32_t df = 0, n = 0;
18742
18743 if ((dfn & 0x30) == 0x00) {
18744 n = dfn & 0x0f;
18745 df = DF_BYTE;
18746 } else if ((dfn & 0x38) == 0x20) {
18747 n = dfn & 0x07;
18748 df = DF_HALF;
18749 } else if ((dfn & 0x3c) == 0x30) {
18750 n = dfn & 0x03;
18751 df = DF_WORD;
18752 } else if ((dfn & 0x3e) == 0x38) {
18753 n = dfn & 0x01;
18754 df = DF_DOUBLE;
18755 } else if (dfn == 0x3E) {
18756 /* CTCMSA, CFCMSA, MOVE.V */
18757 gen_msa_elm_3e(env, ctx);
18758 return;
18759 } else {
18760 generate_exception_end(ctx, EXCP_RI);
18761 return;
18762 }
18763
18764 gen_msa_elm_df(env, ctx, df, n);
18765 }
18766
18767 static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
18768 {
18769 #define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
18770 uint8_t df = (ctx->opcode >> 21) & 0x1;
18771 uint8_t wt = (ctx->opcode >> 16) & 0x1f;
18772 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18773 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18774
18775 TCGv_i32 twd = tcg_const_i32(wd);
18776 TCGv_i32 tws = tcg_const_i32(ws);
18777 TCGv_i32 twt = tcg_const_i32(wt);
18778 TCGv_i32 tdf = tcg_temp_new_i32();
18779
18780 /* adjust df value for floating-point instruction */
18781 tcg_gen_movi_i32(tdf, df + 2);
18782
18783 switch (MASK_MSA_3RF(ctx->opcode)) {
18784 case OPC_FCAF_df:
18785 gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt);
18786 break;
18787 case OPC_FADD_df:
18788 gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt);
18789 break;
18790 case OPC_FCUN_df:
18791 gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt);
18792 break;
18793 case OPC_FSUB_df:
18794 gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt);
18795 break;
18796 case OPC_FCOR_df:
18797 gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt);
18798 break;
18799 case OPC_FCEQ_df:
18800 gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt);
18801 break;
18802 case OPC_FMUL_df:
18803 gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt);
18804 break;
18805 case OPC_FCUNE_df:
18806 gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt);
18807 break;
18808 case OPC_FCUEQ_df:
18809 gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt);
18810 break;
18811 case OPC_FDIV_df:
18812 gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt);
18813 break;
18814 case OPC_FCNE_df:
18815 gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt);
18816 break;
18817 case OPC_FCLT_df:
18818 gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt);
18819 break;
18820 case OPC_FMADD_df:
18821 gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt);
18822 break;
18823 case OPC_MUL_Q_df:
18824 tcg_gen_movi_i32(tdf, df + 1);
18825 gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt);
18826 break;
18827 case OPC_FCULT_df:
18828 gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt);
18829 break;
18830 case OPC_FMSUB_df:
18831 gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt);
18832 break;
18833 case OPC_MADD_Q_df:
18834 tcg_gen_movi_i32(tdf, df + 1);
18835 gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt);
18836 break;
18837 case OPC_FCLE_df:
18838 gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt);
18839 break;
18840 case OPC_MSUB_Q_df:
18841 tcg_gen_movi_i32(tdf, df + 1);
18842 gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt);
18843 break;
18844 case OPC_FCULE_df:
18845 gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt);
18846 break;
18847 case OPC_FEXP2_df:
18848 gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt);
18849 break;
18850 case OPC_FSAF_df:
18851 gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt);
18852 break;
18853 case OPC_FEXDO_df:
18854 gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt);
18855 break;
18856 case OPC_FSUN_df:
18857 gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt);
18858 break;
18859 case OPC_FSOR_df:
18860 gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt);
18861 break;
18862 case OPC_FSEQ_df:
18863 gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt);
18864 break;
18865 case OPC_FTQ_df:
18866 gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt);
18867 break;
18868 case OPC_FSUNE_df:
18869 gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt);
18870 break;
18871 case OPC_FSUEQ_df:
18872 gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt);
18873 break;
18874 case OPC_FSNE_df:
18875 gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt);
18876 break;
18877 case OPC_FSLT_df:
18878 gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt);
18879 break;
18880 case OPC_FMIN_df:
18881 gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt);
18882 break;
18883 case OPC_MULR_Q_df:
18884 tcg_gen_movi_i32(tdf, df + 1);
18885 gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt);
18886 break;
18887 case OPC_FSULT_df:
18888 gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt);
18889 break;
18890 case OPC_FMIN_A_df:
18891 gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt);
18892 break;
18893 case OPC_MADDR_Q_df:
18894 tcg_gen_movi_i32(tdf, df + 1);
18895 gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt);
18896 break;
18897 case OPC_FSLE_df:
18898 gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt);
18899 break;
18900 case OPC_FMAX_df:
18901 gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt);
18902 break;
18903 case OPC_MSUBR_Q_df:
18904 tcg_gen_movi_i32(tdf, df + 1);
18905 gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt);
18906 break;
18907 case OPC_FSULE_df:
18908 gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt);
18909 break;
18910 case OPC_FMAX_A_df:
18911 gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt);
18912 break;
18913 default:
18914 MIPS_INVAL("MSA instruction");
18915 generate_exception_end(ctx, EXCP_RI);
18916 break;
18917 }
18918
18919 tcg_temp_free_i32(twd);
18920 tcg_temp_free_i32(tws);
18921 tcg_temp_free_i32(twt);
18922 tcg_temp_free_i32(tdf);
18923 }
18924
18925 static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
18926 {
18927 #define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
18928 (op & (0x7 << 18)))
18929 uint8_t wt = (ctx->opcode >> 16) & 0x1f;
18930 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18931 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18932 uint8_t df = (ctx->opcode >> 16) & 0x3;
18933 TCGv_i32 twd = tcg_const_i32(wd);
18934 TCGv_i32 tws = tcg_const_i32(ws);
18935 TCGv_i32 twt = tcg_const_i32(wt);
18936 TCGv_i32 tdf = tcg_const_i32(df);
18937
18938 switch (MASK_MSA_2R(ctx->opcode)) {
18939 case OPC_FILL_df:
18940 #if !defined(TARGET_MIPS64)
18941 /* Double format valid only for MIPS64 */
18942 if (df == DF_DOUBLE) {
18943 generate_exception_end(ctx, EXCP_RI);
18944 break;
18945 }
18946 #endif
18947 gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */
18948 break;
18949 case OPC_PCNT_df:
18950 gen_helper_msa_pcnt_df(cpu_env, tdf, twd, tws);
18951 break;
18952 case OPC_NLOC_df:
18953 gen_helper_msa_nloc_df(cpu_env, tdf, twd, tws);
18954 break;
18955 case OPC_NLZC_df:
18956 gen_helper_msa_nlzc_df(cpu_env, tdf, twd, tws);
18957 break;
18958 default:
18959 MIPS_INVAL("MSA instruction");
18960 generate_exception_end(ctx, EXCP_RI);
18961 break;
18962 }
18963
18964 tcg_temp_free_i32(twd);
18965 tcg_temp_free_i32(tws);
18966 tcg_temp_free_i32(twt);
18967 tcg_temp_free_i32(tdf);
18968 }
18969
18970 static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx)
18971 {
18972 #define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
18973 (op & (0xf << 17)))
18974 uint8_t wt = (ctx->opcode >> 16) & 0x1f;
18975 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18976 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18977 uint8_t df = (ctx->opcode >> 16) & 0x1;
18978 TCGv_i32 twd = tcg_const_i32(wd);
18979 TCGv_i32 tws = tcg_const_i32(ws);
18980 TCGv_i32 twt = tcg_const_i32(wt);
18981 /* adjust df value for floating-point instruction */
18982 TCGv_i32 tdf = tcg_const_i32(df + 2);
18983
18984 switch (MASK_MSA_2RF(ctx->opcode)) {
18985 case OPC_FCLASS_df:
18986 gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws);
18987 break;
18988 case OPC_FTRUNC_S_df:
18989 gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws);
18990 break;
18991 case OPC_FTRUNC_U_df:
18992 gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws);
18993 break;
18994 case OPC_FSQRT_df:
18995 gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws);
18996 break;
18997 case OPC_FRSQRT_df:
18998 gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws);
18999 break;
19000 case OPC_FRCP_df:
19001 gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws);
19002 break;
19003 case OPC_FRINT_df:
19004 gen_helper_msa_frint_df(cpu_env, tdf, twd, tws);
19005 break;
19006 case OPC_FLOG2_df:
19007 gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws);
19008 break;
19009 case OPC_FEXUPL_df:
19010 gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws);
19011 break;
19012 case OPC_FEXUPR_df:
19013 gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws);
19014 break;
19015 case OPC_FFQL_df:
19016 gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws);
19017 break;
19018 case OPC_FFQR_df:
19019 gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws);
19020 break;
19021 case OPC_FTINT_S_df:
19022 gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws);
19023 break;
19024 case OPC_FTINT_U_df:
19025 gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws);
19026 break;
19027 case OPC_FFINT_S_df:
19028 gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws);
19029 break;
19030 case OPC_FFINT_U_df:
19031 gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws);
19032 break;
19033 }
19034
19035 tcg_temp_free_i32(twd);
19036 tcg_temp_free_i32(tws);
19037 tcg_temp_free_i32(twt);
19038 tcg_temp_free_i32(tdf);
19039 }
19040
19041 static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
19042 {
19043 #define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
19044 uint8_t wt = (ctx->opcode >> 16) & 0x1f;
19045 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
19046 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
19047 TCGv_i32 twd = tcg_const_i32(wd);
19048 TCGv_i32 tws = tcg_const_i32(ws);
19049 TCGv_i32 twt = tcg_const_i32(wt);
19050
19051 switch (MASK_MSA_VEC(ctx->opcode)) {
19052 case OPC_AND_V:
19053 gen_helper_msa_and_v(cpu_env, twd, tws, twt);
19054 break;
19055 case OPC_OR_V:
19056 gen_helper_msa_or_v(cpu_env, twd, tws, twt);
19057 break;
19058 case OPC_NOR_V:
19059 gen_helper_msa_nor_v(cpu_env, twd, tws, twt);
19060 break;
19061 case OPC_XOR_V:
19062 gen_helper_msa_xor_v(cpu_env, twd, tws, twt);
19063 break;
19064 case OPC_BMNZ_V:
19065 gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt);
19066 break;
19067 case OPC_BMZ_V:
19068 gen_helper_msa_bmz_v(cpu_env, twd, tws, twt);
19069 break;
19070 case OPC_BSEL_V:
19071 gen_helper_msa_bsel_v(cpu_env, twd, tws, twt);
19072 break;
19073 default:
19074 MIPS_INVAL("MSA instruction");
19075 generate_exception_end(ctx, EXCP_RI);
19076 break;
19077 }
19078
19079 tcg_temp_free_i32(twd);
19080 tcg_temp_free_i32(tws);
19081 tcg_temp_free_i32(twt);
19082 }
19083
19084 static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
19085 {
19086 switch (MASK_MSA_VEC(ctx->opcode)) {
19087 case OPC_AND_V:
19088 case OPC_OR_V:
19089 case OPC_NOR_V:
19090 case OPC_XOR_V:
19091 case OPC_BMNZ_V:
19092 case OPC_BMZ_V:
19093 case OPC_BSEL_V:
19094 gen_msa_vec_v(env, ctx);
19095 break;
19096 case OPC_MSA_2R:
19097 gen_msa_2r(env, ctx);
19098 break;
19099 case OPC_MSA_2RF:
19100 gen_msa_2rf(env, ctx);
19101 break;
19102 default:
19103 MIPS_INVAL("MSA instruction");
19104 generate_exception_end(ctx, EXCP_RI);
19105 break;
19106 }
19107 }
19108
19109 static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
19110 {
19111 uint32_t opcode = ctx->opcode;
19112 check_insn(ctx, ASE_MSA);
19113 check_msa_access(ctx);
19114
19115 switch (MASK_MSA_MINOR(opcode)) {
19116 case OPC_MSA_I8_00:
19117 case OPC_MSA_I8_01:
19118 case OPC_MSA_I8_02:
19119 gen_msa_i8(env, ctx);
19120 break;
19121 case OPC_MSA_I5_06:
19122 case OPC_MSA_I5_07:
19123 gen_msa_i5(env, ctx);
19124 break;
19125 case OPC_MSA_BIT_09:
19126 case OPC_MSA_BIT_0A:
19127 gen_msa_bit(env, ctx);
19128 break;
19129 case OPC_MSA_3R_0D:
19130 case OPC_MSA_3R_0E:
19131 case OPC_MSA_3R_0F:
19132 case OPC_MSA_3R_10:
19133 case OPC_MSA_3R_11:
19134 case OPC_MSA_3R_12:
19135 case OPC_MSA_3R_13:
19136 case OPC_MSA_3R_14:
19137 case OPC_MSA_3R_15:
19138 gen_msa_3r(env, ctx);
19139 break;
19140 case OPC_MSA_ELM:
19141 gen_msa_elm(env, ctx);
19142 break;
19143 case OPC_MSA_3RF_1A:
19144 case OPC_MSA_3RF_1B:
19145 case OPC_MSA_3RF_1C:
19146 gen_msa_3rf(env, ctx);
19147 break;
19148 case OPC_MSA_VEC:
19149 gen_msa_vec(env, ctx);
19150 break;
19151 case OPC_LD_B:
19152 case OPC_LD_H:
19153 case OPC_LD_W:
19154 case OPC_LD_D:
19155 case OPC_ST_B:
19156 case OPC_ST_H:
19157 case OPC_ST_W:
19158 case OPC_ST_D:
19159 {
19160 int32_t s10 = sextract32(ctx->opcode, 16, 10);
19161 uint8_t rs = (ctx->opcode >> 11) & 0x1f;
19162 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
19163 uint8_t df = (ctx->opcode >> 0) & 0x3;
19164
19165 TCGv_i32 twd = tcg_const_i32(wd);
19166 TCGv taddr = tcg_temp_new();
19167 gen_base_offset_addr(ctx, taddr, rs, s10 << df);
19168
19169 switch (MASK_MSA_MINOR(opcode)) {
19170 case OPC_LD_B:
19171 gen_helper_msa_ld_b(cpu_env, twd, taddr);
19172 break;
19173 case OPC_LD_H:
19174 gen_helper_msa_ld_h(cpu_env, twd, taddr);
19175 break;
19176 case OPC_LD_W:
19177 gen_helper_msa_ld_w(cpu_env, twd, taddr);
19178 break;
19179 case OPC_LD_D:
19180 gen_helper_msa_ld_d(cpu_env, twd, taddr);
19181 break;
19182 case OPC_ST_B:
19183 gen_helper_msa_st_b(cpu_env, twd, taddr);
19184 break;
19185 case OPC_ST_H:
19186 gen_helper_msa_st_h(cpu_env, twd, taddr);
19187 break;
19188 case OPC_ST_W:
19189 gen_helper_msa_st_w(cpu_env, twd, taddr);
19190 break;
19191 case OPC_ST_D:
19192 gen_helper_msa_st_d(cpu_env, twd, taddr);
19193 break;
19194 }
19195
19196 tcg_temp_free_i32(twd);
19197 tcg_temp_free(taddr);
19198 }
19199 break;
19200 default:
19201 MIPS_INVAL("MSA instruction");
19202 generate_exception_end(ctx, EXCP_RI);
19203 break;
19204 }
19205
19206 }
19207
19208 static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
19209 {
19210 int32_t offset;
19211 int rs, rt, rd, sa;
19212 uint32_t op, op1;
19213 int16_t imm;
19214
19215 /* make sure instructions are on a word boundary */
19216 if (ctx->pc & 0x3) {
19217 env->CP0_BadVAddr = ctx->pc;
19218 generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
19219 return;
19220 }
19221
19222 /* Handle blikely not taken case */
19223 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
19224 TCGLabel *l1 = gen_new_label();
19225
19226 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
19227 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
19228 gen_goto_tb(ctx, 1, ctx->pc + 4);
19229 gen_set_label(l1);
19230 }
19231
19232 op = MASK_OP_MAJOR(ctx->opcode);
19233 rs = (ctx->opcode >> 21) & 0x1f;
19234 rt = (ctx->opcode >> 16) & 0x1f;
19235 rd = (ctx->opcode >> 11) & 0x1f;
19236 sa = (ctx->opcode >> 6) & 0x1f;
19237 imm = (int16_t)ctx->opcode;
19238 switch (op) {
19239 case OPC_SPECIAL:
19240 decode_opc_special(env, ctx);
19241 break;
19242 case OPC_SPECIAL2:
19243 decode_opc_special2_legacy(env, ctx);
19244 break;
19245 case OPC_SPECIAL3:
19246 decode_opc_special3(env, ctx);
19247 break;
19248 case OPC_REGIMM:
19249 op1 = MASK_REGIMM(ctx->opcode);
19250 switch (op1) {
19251 case OPC_BLTZL: /* REGIMM branches */
19252 case OPC_BGEZL:
19253 case OPC_BLTZALL:
19254 case OPC_BGEZALL:
19255 check_insn(ctx, ISA_MIPS2);
19256 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19257 /* Fallthrough */
19258 case OPC_BLTZ:
19259 case OPC_BGEZ:
19260 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
19261 break;
19262 case OPC_BLTZAL:
19263 case OPC_BGEZAL:
19264 if (ctx->insn_flags & ISA_MIPS32R6) {
19265 if (rs == 0) {
19266 /* OPC_NAL, OPC_BAL */
19267 gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4);
19268 } else {
19269 generate_exception_end(ctx, EXCP_RI);
19270 }
19271 } else {
19272 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
19273 }
19274 break;
19275 case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
19276 case OPC_TNEI:
19277 check_insn(ctx, ISA_MIPS2);
19278 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19279 gen_trap(ctx, op1, rs, -1, imm);
19280 break;
19281 case OPC_SIGRIE:
19282 check_insn(ctx, ISA_MIPS32R6);
19283 generate_exception_end(ctx, EXCP_RI);
19284 break;
19285 case OPC_SYNCI:
19286 check_insn(ctx, ISA_MIPS32R2);
19287 /* Break the TB to be able to sync copied instructions
19288 immediately */
19289 ctx->bstate = BS_STOP;
19290 break;
19291 case OPC_BPOSGE32: /* MIPS DSP branch */
19292 #if defined(TARGET_MIPS64)
19293 case OPC_BPOSGE64:
19294 #endif
19295 check_dsp(ctx);
19296 gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4);
19297 break;
19298 #if defined(TARGET_MIPS64)
19299 case OPC_DAHI:
19300 check_insn(ctx, ISA_MIPS32R6);
19301 check_mips_64(ctx);
19302 if (rs != 0) {
19303 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32);
19304 }
19305 break;
19306 case OPC_DATI:
19307 check_insn(ctx, ISA_MIPS32R6);
19308 check_mips_64(ctx);
19309 if (rs != 0) {
19310 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48);
19311 }
19312 break;
19313 #endif
19314 default: /* Invalid */
19315 MIPS_INVAL("regimm");
19316 generate_exception_end(ctx, EXCP_RI);
19317 break;
19318 }
19319 break;
19320 case OPC_CP0:
19321 check_cp0_enabled(ctx);
19322 op1 = MASK_CP0(ctx->opcode);
19323 switch (op1) {
19324 case OPC_MFC0:
19325 case OPC_MTC0:
19326 case OPC_MFTR:
19327 case OPC_MTTR:
19328 case OPC_MFHC0:
19329 case OPC_MTHC0:
19330 #if defined(TARGET_MIPS64)
19331 case OPC_DMFC0:
19332 case OPC_DMTC0:
19333 #endif
19334 #ifndef CONFIG_USER_ONLY
19335 gen_cp0(env, ctx, op1, rt, rd);
19336 #endif /* !CONFIG_USER_ONLY */
19337 break;
19338 case OPC_C0_FIRST ... OPC_C0_LAST:
19339 #ifndef CONFIG_USER_ONLY
19340 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
19341 #endif /* !CONFIG_USER_ONLY */
19342 break;
19343 case OPC_MFMC0:
19344 #ifndef CONFIG_USER_ONLY
19345 {
19346 uint32_t op2;
19347 TCGv t0 = tcg_temp_new();
19348
19349 op2 = MASK_MFMC0(ctx->opcode);
19350 switch (op2) {
19351 case OPC_DMT:
19352 check_insn(ctx, ASE_MT);
19353 gen_helper_dmt(t0);
19354 gen_store_gpr(t0, rt);
19355 break;
19356 case OPC_EMT:
19357 check_insn(ctx, ASE_MT);
19358 gen_helper_emt(t0);
19359 gen_store_gpr(t0, rt);
19360 break;
19361 case OPC_DVPE:
19362 check_insn(ctx, ASE_MT);
19363 gen_helper_dvpe(t0, cpu_env);
19364 gen_store_gpr(t0, rt);
19365 break;
19366 case OPC_EVPE:
19367 check_insn(ctx, ASE_MT);
19368 gen_helper_evpe(t0, cpu_env);
19369 gen_store_gpr(t0, rt);
19370 break;
19371 case OPC_DVP:
19372 check_insn(ctx, ISA_MIPS32R6);
19373 if (ctx->vp) {
19374 gen_helper_dvp(t0, cpu_env);
19375 gen_store_gpr(t0, rt);
19376 }
19377 break;
19378 case OPC_EVP:
19379 check_insn(ctx, ISA_MIPS32R6);
19380 if (ctx->vp) {
19381 gen_helper_evp(t0, cpu_env);
19382 gen_store_gpr(t0, rt);
19383 }
19384 break;
19385 case OPC_DI:
19386 check_insn(ctx, ISA_MIPS32R2);
19387 save_cpu_state(ctx, 1);
19388 gen_helper_di(t0, cpu_env);
19389 gen_store_gpr(t0, rt);
19390 /* Stop translation as we may have switched
19391 the execution mode. */
19392 ctx->bstate = BS_STOP;
19393 break;
19394 case OPC_EI:
19395 check_insn(ctx, ISA_MIPS32R2);
19396 save_cpu_state(ctx, 1);
19397 gen_helper_ei(t0, cpu_env);
19398 gen_store_gpr(t0, rt);
19399 /* Stop translation as we may have switched
19400 the execution mode. */
19401 ctx->bstate = BS_STOP;
19402 break;
19403 default: /* Invalid */
19404 MIPS_INVAL("mfmc0");
19405 generate_exception_end(ctx, EXCP_RI);
19406 break;
19407 }
19408 tcg_temp_free(t0);
19409 }
19410 #endif /* !CONFIG_USER_ONLY */
19411 break;
19412 case OPC_RDPGPR:
19413 check_insn(ctx, ISA_MIPS32R2);
19414 gen_load_srsgpr(rt, rd);
19415 break;
19416 case OPC_WRPGPR:
19417 check_insn(ctx, ISA_MIPS32R2);
19418 gen_store_srsgpr(rt, rd);
19419 break;
19420 default:
19421 MIPS_INVAL("cp0");
19422 generate_exception_end(ctx, EXCP_RI);
19423 break;
19424 }
19425 break;
19426 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */
19427 if (ctx->insn_flags & ISA_MIPS32R6) {
19428 /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */
19429 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19430 } else {
19431 /* OPC_ADDI */
19432 /* Arithmetic with immediate opcode */
19433 gen_arith_imm(ctx, op, rt, rs, imm);
19434 }
19435 break;
19436 case OPC_ADDIU:
19437 gen_arith_imm(ctx, op, rt, rs, imm);
19438 break;
19439 case OPC_SLTI: /* Set on less than with immediate opcode */
19440 case OPC_SLTIU:
19441 gen_slt_imm(ctx, op, rt, rs, imm);
19442 break;
19443 case OPC_ANDI: /* Arithmetic with immediate opcode */
19444 case OPC_LUI: /* OPC_AUI */
19445 case OPC_ORI:
19446 case OPC_XORI:
19447 gen_logic_imm(ctx, op, rt, rs, imm);
19448 break;
19449 case OPC_J ... OPC_JAL: /* Jump */
19450 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
19451 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
19452 break;
19453 /* Branch */
19454 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
19455 if (ctx->insn_flags & ISA_MIPS32R6) {
19456 if (rt == 0) {
19457 generate_exception_end(ctx, EXCP_RI);
19458 break;
19459 }
19460 /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
19461 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19462 } else {
19463 /* OPC_BLEZL */
19464 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
19465 }
19466 break;
19467 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
19468 if (ctx->insn_flags & ISA_MIPS32R6) {
19469 if (rt == 0) {
19470 generate_exception_end(ctx, EXCP_RI);
19471 break;
19472 }
19473 /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
19474 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19475 } else {
19476 /* OPC_BGTZL */
19477 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
19478 }
19479 break;
19480 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */
19481 if (rt == 0) {
19482 /* OPC_BLEZ */
19483 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
19484 } else {
19485 check_insn(ctx, ISA_MIPS32R6);
19486 /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */
19487 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19488 }
19489 break;
19490 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */
19491 if (rt == 0) {
19492 /* OPC_BGTZ */
19493 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
19494 } else {
19495 check_insn(ctx, ISA_MIPS32R6);
19496 /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */
19497 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19498 }
19499 break;
19500 case OPC_BEQL:
19501 case OPC_BNEL:
19502 check_insn(ctx, ISA_MIPS2);
19503 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19504 /* Fallthrough */
19505 case OPC_BEQ:
19506 case OPC_BNE:
19507 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
19508 break;
19509 case OPC_LL: /* Load and stores */
19510 check_insn(ctx, ISA_MIPS2);
19511 /* Fallthrough */
19512 case OPC_LWL:
19513 case OPC_LWR:
19514 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19515 /* Fallthrough */
19516 case OPC_LB ... OPC_LH:
19517 case OPC_LW ... OPC_LHU:
19518 gen_ld(ctx, op, rt, rs, imm);
19519 break;
19520 case OPC_SWL:
19521 case OPC_SWR:
19522 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19523 /* fall through */
19524 case OPC_SB ... OPC_SH:
19525 case OPC_SW:
19526 gen_st(ctx, op, rt, rs, imm);
19527 break;
19528 case OPC_SC:
19529 check_insn(ctx, ISA_MIPS2);
19530 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19531 gen_st_cond(ctx, op, rt, rs, imm);
19532 break;
19533 case OPC_CACHE:
19534 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19535 check_cp0_enabled(ctx);
19536 check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
19537 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
19538 gen_cache_operation(ctx, rt, rs, imm);
19539 }
19540 /* Treat as NOP. */
19541 break;
19542 case OPC_PREF:
19543 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19544 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
19545 /* Treat as NOP. */
19546 break;
19547
19548 /* Floating point (COP1). */
19549 case OPC_LWC1:
19550 case OPC_LDC1:
19551 case OPC_SWC1:
19552 case OPC_SDC1:
19553 gen_cop1_ldst(ctx, op, rt, rs, imm);
19554 break;
19555
19556 case OPC_CP1:
19557 op1 = MASK_CP1(ctx->opcode);
19558
19559 switch (op1) {
19560 case OPC_MFHC1:
19561 case OPC_MTHC1:
19562 check_cp1_enabled(ctx);
19563 check_insn(ctx, ISA_MIPS32R2);
19564 case OPC_MFC1:
19565 case OPC_CFC1:
19566 case OPC_MTC1:
19567 case OPC_CTC1:
19568 check_cp1_enabled(ctx);
19569 gen_cp1(ctx, op1, rt, rd);
19570 break;
19571 #if defined(TARGET_MIPS64)
19572 case OPC_DMFC1:
19573 case OPC_DMTC1:
19574 check_cp1_enabled(ctx);
19575 check_insn(ctx, ISA_MIPS3);
19576 check_mips_64(ctx);
19577 gen_cp1(ctx, op1, rt, rd);
19578 break;
19579 #endif
19580 case OPC_BC1EQZ: /* OPC_BC1ANY2 */
19581 check_cp1_enabled(ctx);
19582 if (ctx->insn_flags & ISA_MIPS32R6) {
19583 /* OPC_BC1EQZ */
19584 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
19585 rt, imm << 2, 4);
19586 } else {
19587 /* OPC_BC1ANY2 */
19588 check_cop1x(ctx);
19589 check_insn(ctx, ASE_MIPS3D);
19590 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
19591 (rt >> 2) & 0x7, imm << 2);
19592 }
19593 break;
19594 case OPC_BC1NEZ:
19595 check_cp1_enabled(ctx);
19596 check_insn(ctx, ISA_MIPS32R6);
19597 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
19598 rt, imm << 2, 4);
19599 break;
19600 case OPC_BC1ANY4:
19601 check_cp1_enabled(ctx);
19602 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19603 check_cop1x(ctx);
19604 check_insn(ctx, ASE_MIPS3D);
19605 /* fall through */
19606 case OPC_BC1:
19607 check_cp1_enabled(ctx);
19608 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19609 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
19610 (rt >> 2) & 0x7, imm << 2);
19611 break;
19612 case OPC_PS_FMT:
19613 check_ps(ctx);
19614 /* fall through */
19615 case OPC_S_FMT:
19616 case OPC_D_FMT:
19617 check_cp1_enabled(ctx);
19618 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
19619 (imm >> 8) & 0x7);
19620 break;
19621 case OPC_W_FMT:
19622 case OPC_L_FMT:
19623 {
19624 int r6_op = ctx->opcode & FOP(0x3f, 0x1f);
19625 check_cp1_enabled(ctx);
19626 if (ctx->insn_flags & ISA_MIPS32R6) {
19627 switch (r6_op) {
19628 case R6_OPC_CMP_AF_S:
19629 case R6_OPC_CMP_UN_S:
19630 case R6_OPC_CMP_EQ_S:
19631 case R6_OPC_CMP_UEQ_S:
19632 case R6_OPC_CMP_LT_S:
19633 case R6_OPC_CMP_ULT_S:
19634 case R6_OPC_CMP_LE_S:
19635 case R6_OPC_CMP_ULE_S:
19636 case R6_OPC_CMP_SAF_S:
19637 case R6_OPC_CMP_SUN_S:
19638 case R6_OPC_CMP_SEQ_S:
19639 case R6_OPC_CMP_SEUQ_S:
19640 case R6_OPC_CMP_SLT_S:
19641 case R6_OPC_CMP_SULT_S:
19642 case R6_OPC_CMP_SLE_S:
19643 case R6_OPC_CMP_SULE_S:
19644 case R6_OPC_CMP_OR_S:
19645 case R6_OPC_CMP_UNE_S:
19646 case R6_OPC_CMP_NE_S:
19647 case R6_OPC_CMP_SOR_S:
19648 case R6_OPC_CMP_SUNE_S:
19649 case R6_OPC_CMP_SNE_S:
19650 gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa);
19651 break;
19652 case R6_OPC_CMP_AF_D:
19653 case R6_OPC_CMP_UN_D:
19654 case R6_OPC_CMP_EQ_D:
19655 case R6_OPC_CMP_UEQ_D:
19656 case R6_OPC_CMP_LT_D:
19657 case R6_OPC_CMP_ULT_D:
19658 case R6_OPC_CMP_LE_D:
19659 case R6_OPC_CMP_ULE_D:
19660 case R6_OPC_CMP_SAF_D:
19661 case R6_OPC_CMP_SUN_D:
19662 case R6_OPC_CMP_SEQ_D:
19663 case R6_OPC_CMP_SEUQ_D:
19664 case R6_OPC_CMP_SLT_D:
19665 case R6_OPC_CMP_SULT_D:
19666 case R6_OPC_CMP_SLE_D:
19667 case R6_OPC_CMP_SULE_D:
19668 case R6_OPC_CMP_OR_D:
19669 case R6_OPC_CMP_UNE_D:
19670 case R6_OPC_CMP_NE_D:
19671 case R6_OPC_CMP_SOR_D:
19672 case R6_OPC_CMP_SUNE_D:
19673 case R6_OPC_CMP_SNE_D:
19674 gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa);
19675 break;
19676 default:
19677 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f),
19678 rt, rd, sa, (imm >> 8) & 0x7);
19679
19680 break;
19681 }
19682 } else {
19683 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
19684 (imm >> 8) & 0x7);
19685 }
19686 break;
19687 }
19688 case OPC_BZ_V:
19689 case OPC_BNZ_V:
19690 case OPC_BZ_B:
19691 case OPC_BZ_H:
19692 case OPC_BZ_W:
19693 case OPC_BZ_D:
19694 case OPC_BNZ_B:
19695 case OPC_BNZ_H:
19696 case OPC_BNZ_W:
19697 case OPC_BNZ_D:
19698 check_insn(ctx, ASE_MSA);
19699 gen_msa_branch(env, ctx, op1);
19700 break;
19701 default:
19702 MIPS_INVAL("cp1");
19703 generate_exception_end(ctx, EXCP_RI);
19704 break;
19705 }
19706 break;
19707
19708 /* Compact branches [R6] and COP2 [non-R6] */
19709 case OPC_BC: /* OPC_LWC2 */
19710 case OPC_BALC: /* OPC_SWC2 */
19711 if (ctx->insn_flags & ISA_MIPS32R6) {
19712 /* OPC_BC, OPC_BALC */
19713 gen_compute_compact_branch(ctx, op, 0, 0,
19714 sextract32(ctx->opcode << 2, 0, 28));
19715 } else {
19716 /* OPC_LWC2, OPC_SWC2 */
19717 /* COP2: Not implemented. */
19718 generate_exception_err(ctx, EXCP_CpU, 2);
19719 }
19720 break;
19721 case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */
19722 case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */
19723 if (ctx->insn_flags & ISA_MIPS32R6) {
19724 if (rs != 0) {
19725 /* OPC_BEQZC, OPC_BNEZC */
19726 gen_compute_compact_branch(ctx, op, rs, 0,
19727 sextract32(ctx->opcode << 2, 0, 23));
19728 } else {
19729 /* OPC_JIC, OPC_JIALC */
19730 gen_compute_compact_branch(ctx, op, 0, rt, imm);
19731 }
19732 } else {
19733 /* OPC_LWC2, OPC_SWC2 */
19734 /* COP2: Not implemented. */
19735 generate_exception_err(ctx, EXCP_CpU, 2);
19736 }
19737 break;
19738 case OPC_CP2:
19739 check_insn(ctx, INSN_LOONGSON2F);
19740 /* Note that these instructions use different fields. */
19741 gen_loongson_multimedia(ctx, sa, rd, rt);
19742 break;
19743
19744 case OPC_CP3:
19745 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19746 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
19747 check_cp1_enabled(ctx);
19748 op1 = MASK_CP3(ctx->opcode);
19749 switch (op1) {
19750 case OPC_LUXC1:
19751 case OPC_SUXC1:
19752 check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2);
19753 /* Fallthrough */
19754 case OPC_LWXC1:
19755 case OPC_LDXC1:
19756 case OPC_SWXC1:
19757 case OPC_SDXC1:
19758 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
19759 gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
19760 break;
19761 case OPC_PREFX:
19762 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
19763 /* Treat as NOP. */
19764 break;
19765 case OPC_ALNV_PS:
19766 check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2);
19767 /* Fallthrough */
19768 case OPC_MADD_S:
19769 case OPC_MADD_D:
19770 case OPC_MADD_PS:
19771 case OPC_MSUB_S:
19772 case OPC_MSUB_D:
19773 case OPC_MSUB_PS:
19774 case OPC_NMADD_S:
19775 case OPC_NMADD_D:
19776 case OPC_NMADD_PS:
19777 case OPC_NMSUB_S:
19778 case OPC_NMSUB_D:
19779 case OPC_NMSUB_PS:
19780 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
19781 gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
19782 break;
19783 default:
19784 MIPS_INVAL("cp3");
19785 generate_exception_end(ctx, EXCP_RI);
19786 break;
19787 }
19788 } else {
19789 generate_exception_err(ctx, EXCP_CpU, 1);
19790 }
19791 break;
19792
19793 #if defined(TARGET_MIPS64)
19794 /* MIPS64 opcodes */
19795 case OPC_LDL ... OPC_LDR:
19796 case OPC_LLD:
19797 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19798 /* fall through */
19799 case OPC_LWU:
19800 case OPC_LD:
19801 check_insn(ctx, ISA_MIPS3);
19802 check_mips_64(ctx);
19803 gen_ld(ctx, op, rt, rs, imm);
19804 break;
19805 case OPC_SDL ... OPC_SDR:
19806 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19807 /* fall through */
19808 case OPC_SD:
19809 check_insn(ctx, ISA_MIPS3);
19810 check_mips_64(ctx);
19811 gen_st(ctx, op, rt, rs, imm);
19812 break;
19813 case OPC_SCD:
19814 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19815 check_insn(ctx, ISA_MIPS3);
19816 check_mips_64(ctx);
19817 gen_st_cond(ctx, op, rt, rs, imm);
19818 break;
19819 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
19820 if (ctx->insn_flags & ISA_MIPS32R6) {
19821 /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
19822 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19823 } else {
19824 /* OPC_DADDI */
19825 check_insn(ctx, ISA_MIPS3);
19826 check_mips_64(ctx);
19827 gen_arith_imm(ctx, op, rt, rs, imm);
19828 }
19829 break;
19830 case OPC_DADDIU:
19831 check_insn(ctx, ISA_MIPS3);
19832 check_mips_64(ctx);
19833 gen_arith_imm(ctx, op, rt, rs, imm);
19834 break;
19835 #else
19836 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
19837 if (ctx->insn_flags & ISA_MIPS32R6) {
19838 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19839 } else {
19840 MIPS_INVAL("major opcode");
19841 generate_exception_end(ctx, EXCP_RI);
19842 }
19843 break;
19844 #endif
19845 case OPC_DAUI: /* OPC_JALX */
19846 if (ctx->insn_flags & ISA_MIPS32R6) {
19847 #if defined(TARGET_MIPS64)
19848 /* OPC_DAUI */
19849 check_mips_64(ctx);
19850 if (rs == 0) {
19851 generate_exception(ctx, EXCP_RI);
19852 } else if (rt != 0) {
19853 TCGv t0 = tcg_temp_new();
19854 gen_load_gpr(t0, rs);
19855 tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);
19856 tcg_temp_free(t0);
19857 }
19858 #else
19859 generate_exception_end(ctx, EXCP_RI);
19860 MIPS_INVAL("major opcode");
19861 #endif
19862 } else {
19863 /* OPC_JALX */
19864 check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS);
19865 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
19866 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
19867 }
19868 break;
19869 case OPC_MSA: /* OPC_MDMX */
19870 /* MDMX: Not implemented. */
19871 gen_msa(env, ctx);
19872 break;
19873 case OPC_PCREL:
19874 check_insn(ctx, ISA_MIPS32R6);
19875 gen_pcrel(ctx, ctx->opcode, ctx->pc, rs);
19876 break;
19877 default: /* Invalid */
19878 MIPS_INVAL("major opcode");
19879 generate_exception_end(ctx, EXCP_RI);
19880 break;
19881 }
19882 }
19883
19884 void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
19885 {
19886 MIPSCPU *cpu = mips_env_get_cpu(env);
19887 CPUState *cs = CPU(cpu);
19888 DisasContext ctx;
19889 target_ulong pc_start;
19890 target_ulong next_page_start;
19891 int num_insns;
19892 int max_insns;
19893 int insn_bytes;
19894 int is_slot;
19895
19896 pc_start = tb->pc;
19897 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
19898 ctx.pc = pc_start;
19899 ctx.saved_pc = -1;
19900 ctx.singlestep_enabled = cs->singlestep_enabled;
19901 ctx.insn_flags = env->insn_flags;
19902 ctx.CP0_Config1 = env->CP0_Config1;
19903 ctx.tb = tb;
19904 ctx.bstate = BS_NONE;
19905 ctx.btarget = 0;
19906 ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
19907 ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
19908 ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
19909 ctx.bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
19910 ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
19911 ctx.PAMask = env->PAMask;
19912 ctx.mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
19913 ctx.CP0_LLAddr_shift = env->CP0_LLAddr_shift;
19914 ctx.cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
19915 /* Restore delay slot state from the tb context. */
19916 ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
19917 ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
19918 ctx.ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
19919 (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
19920 ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
19921 ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
19922 ctx.nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
19923 ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
19924 restore_cpu_state(env, &ctx);
19925 #ifdef CONFIG_USER_ONLY
19926 ctx.mem_idx = MIPS_HFLAG_UM;
19927 #else
19928 ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
19929 #endif
19930 ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
19931 MO_UNALN : MO_ALIGN;
19932 num_insns = 0;
19933 max_insns = tb->cflags & CF_COUNT_MASK;
19934 if (max_insns == 0) {
19935 max_insns = CF_COUNT_MASK;
19936 }
19937 if (max_insns > TCG_MAX_INSNS) {
19938 max_insns = TCG_MAX_INSNS;
19939 }
19940
19941 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
19942 gen_tb_start(tb);
19943 while (ctx.bstate == BS_NONE) {
19944 tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
19945 num_insns++;
19946
19947 if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
19948 save_cpu_state(&ctx, 1);
19949 ctx.bstate = BS_BRANCH;
19950 gen_helper_raise_exception_debug(cpu_env);
19951 /* The address covered by the breakpoint must be included in
19952 [tb->pc, tb->pc + tb->size) in order to for it to be
19953 properly cleared -- thus we increment the PC here so that
19954 the logic setting tb->size below does the right thing. */
19955 ctx.pc += 4;
19956 goto done_generating;
19957 }
19958
19959 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
19960 gen_io_start();
19961 }
19962
19963 is_slot = ctx.hflags & MIPS_HFLAG_BMASK;
19964 if (!(ctx.hflags & MIPS_HFLAG_M16)) {
19965 ctx.opcode = cpu_ldl_code(env, ctx.pc);
19966 insn_bytes = 4;
19967 decode_opc(env, &ctx);
19968 } else if (ctx.insn_flags & ASE_MICROMIPS) {
19969 ctx.opcode = cpu_lduw_code(env, ctx.pc);
19970 insn_bytes = decode_micromips_opc(env, &ctx);
19971 } else if (ctx.insn_flags & ASE_MIPS16) {
19972 ctx.opcode = cpu_lduw_code(env, ctx.pc);
19973 insn_bytes = decode_mips16_opc(env, &ctx);
19974 } else {
19975 generate_exception_end(&ctx, EXCP_RI);
19976 break;
19977 }
19978
19979 if (ctx.hflags & MIPS_HFLAG_BMASK) {
19980 if (!(ctx.hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
19981 MIPS_HFLAG_FBNSLOT))) {
19982 /* force to generate branch as there is neither delay nor
19983 forbidden slot */
19984 is_slot = 1;
19985 }
19986 if ((ctx.hflags & MIPS_HFLAG_M16) &&
19987 (ctx.hflags & MIPS_HFLAG_FBNSLOT)) {
19988 /* Force to generate branch as microMIPS R6 doesn't restrict
19989 branches in the forbidden slot. */
19990 is_slot = 1;
19991 }
19992 }
19993 if (is_slot) {
19994 gen_branch(&ctx, insn_bytes);
19995 }
19996 ctx.pc += insn_bytes;
19997
19998 /* Execute a branch and its delay slot as a single instruction.
19999 This is what GDB expects and is consistent with what the
20000 hardware does (e.g. if a delay slot instruction faults, the
20001 reported PC is the PC of the branch). */
20002 if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
20003 break;
20004 }
20005
20006 if (ctx.pc >= next_page_start) {
20007 break;
20008 }
20009
20010 if (tcg_op_buf_full()) {
20011 break;
20012 }
20013
20014 if (num_insns >= max_insns)
20015 break;
20016
20017 if (singlestep)
20018 break;
20019 }
20020 if (tb->cflags & CF_LAST_IO) {
20021 gen_io_end();
20022 }
20023 if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
20024 save_cpu_state(&ctx, ctx.bstate != BS_EXCP);
20025 gen_helper_raise_exception_debug(cpu_env);
20026 } else {
20027 switch (ctx.bstate) {
20028 case BS_STOP:
20029 gen_goto_tb(&ctx, 0, ctx.pc);
20030 break;
20031 case BS_NONE:
20032 save_cpu_state(&ctx, 0);
20033 gen_goto_tb(&ctx, 0, ctx.pc);
20034 break;
20035 case BS_EXCP:
20036 tcg_gen_exit_tb(0);
20037 break;
20038 case BS_BRANCH:
20039 default:
20040 break;
20041 }
20042 }
20043 done_generating:
20044 gen_tb_end(tb, num_insns);
20045
20046 tb->size = ctx.pc - pc_start;
20047 tb->icount = num_insns;
20048
20049 #ifdef DEBUG_DISAS
20050 LOG_DISAS("\n");
20051 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
20052 && qemu_log_in_addr_range(pc_start)) {
20053 qemu_log_lock();
20054 qemu_log("IN: %s\n", lookup_symbol(pc_start));
20055 log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
20056 qemu_log("\n");
20057 qemu_log_unlock();
20058 }
20059 #endif
20060 }
20061
20062 static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fprintf,
20063 int flags)
20064 {
20065 int i;
20066 int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
20067
20068 #define printfpr(fp) \
20069 do { \
20070 if (is_fpu64) \
20071 fpu_fprintf(f, "w:%08x d:%016" PRIx64 \
20072 " fd:%13g fs:%13g psu: %13g\n", \
20073 (fp)->w[FP_ENDIAN_IDX], (fp)->d, \
20074 (double)(fp)->fd, \
20075 (double)(fp)->fs[FP_ENDIAN_IDX], \
20076 (double)(fp)->fs[!FP_ENDIAN_IDX]); \
20077 else { \
20078 fpr_t tmp; \
20079 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
20080 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
20081 fpu_fprintf(f, "w:%08x d:%016" PRIx64 \
20082 " fd:%13g fs:%13g psu:%13g\n", \
20083 tmp.w[FP_ENDIAN_IDX], tmp.d, \
20084 (double)tmp.fd, \
20085 (double)tmp.fs[FP_ENDIAN_IDX], \
20086 (double)tmp.fs[!FP_ENDIAN_IDX]); \
20087 } \
20088 } while(0)
20089
20090
20091 fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
20092 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
20093 get_float_exception_flags(&env->active_fpu.fp_status));
20094 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
20095 fpu_fprintf(f, "%3s: ", fregnames[i]);
20096 printfpr(&env->active_fpu.fpr[i]);
20097 }
20098
20099 #undef printfpr
20100 }
20101
20102 void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
20103 int flags)
20104 {
20105 MIPSCPU *cpu = MIPS_CPU(cs);
20106 CPUMIPSState *env = &cpu->env;
20107 int i;
20108
20109 cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
20110 " LO=0x" TARGET_FMT_lx " ds %04x "
20111 TARGET_FMT_lx " " TARGET_FMT_ld "\n",
20112 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
20113 env->hflags, env->btarget, env->bcond);
20114 for (i = 0; i < 32; i++) {
20115 if ((i & 3) == 0)
20116 cpu_fprintf(f, "GPR%02d:", i);
20117 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.gpr[i]);
20118 if ((i & 3) == 3)
20119 cpu_fprintf(f, "\n");
20120 }
20121
20122 cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
20123 env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
20124 cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
20125 PRIx64 "\n",
20126 env->CP0_Config0, env->CP0_Config1, env->lladdr);
20127 cpu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
20128 env->CP0_Config2, env->CP0_Config3);
20129 cpu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
20130 env->CP0_Config4, env->CP0_Config5);
20131 if (env->hflags & MIPS_HFLAG_FPU)
20132 fpu_dump_state(env, f, cpu_fprintf, flags);
20133 }
20134
20135 void mips_tcg_init(void)
20136 {
20137 int i;
20138 static int inited;
20139
20140 /* Initialize various static tables. */
20141 if (inited)
20142 return;
20143
20144 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
20145 tcg_ctx.tcg_env = cpu_env;
20146
20147 TCGV_UNUSED(cpu_gpr[0]);
20148 for (i = 1; i < 32; i++)
20149 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
20150 offsetof(CPUMIPSState, active_tc.gpr[i]),
20151 regnames[i]);
20152
20153 for (i = 0; i < 32; i++) {
20154 int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
20155 msa_wr_d[i * 2] =
20156 tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]);
20157 /* The scalar floating-point unit (FPU) registers are mapped on
20158 * the MSA vector registers. */
20159 fpu_f64[i] = msa_wr_d[i * 2];
20160 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
20161 msa_wr_d[i * 2 + 1] =
20162 tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
20163 }
20164
20165 cpu_PC = tcg_global_mem_new(cpu_env,
20166 offsetof(CPUMIPSState, active_tc.PC), "PC");
20167 for (i = 0; i < MIPS_DSP_ACC; i++) {
20168 cpu_HI[i] = tcg_global_mem_new(cpu_env,
20169 offsetof(CPUMIPSState, active_tc.HI[i]),
20170 regnames_HI[i]);
20171 cpu_LO[i] = tcg_global_mem_new(cpu_env,
20172 offsetof(CPUMIPSState, active_tc.LO[i]),
20173 regnames_LO[i]);
20174 }
20175 cpu_dspctrl = tcg_global_mem_new(cpu_env,
20176 offsetof(CPUMIPSState, active_tc.DSPControl),
20177 "DSPControl");
20178 bcond = tcg_global_mem_new(cpu_env,
20179 offsetof(CPUMIPSState, bcond), "bcond");
20180 btarget = tcg_global_mem_new(cpu_env,
20181 offsetof(CPUMIPSState, btarget), "btarget");
20182 hflags = tcg_global_mem_new_i32(cpu_env,
20183 offsetof(CPUMIPSState, hflags), "hflags");
20184
20185 fpu_fcr0 = tcg_global_mem_new_i32(cpu_env,
20186 offsetof(CPUMIPSState, active_fpu.fcr0),
20187 "fcr0");
20188 fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
20189 offsetof(CPUMIPSState, active_fpu.fcr31),
20190 "fcr31");
20191
20192 inited = 1;
20193 }
20194
20195 #include "translate_init.c"
20196
20197 MIPSCPU *cpu_mips_init(const char *cpu_model)
20198 {
20199 MIPSCPU *cpu;
20200 CPUMIPSState *env;
20201 const mips_def_t *def;
20202
20203 def = cpu_mips_find_by_name(cpu_model);
20204 if (!def)
20205 return NULL;
20206 cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));
20207 env = &cpu->env;
20208 env->cpu_model = def;
20209 env->exception_base = (int32_t)0xBFC00000;
20210
20211 #ifndef CONFIG_USER_ONLY
20212 mmu_init(env, def);
20213 #endif
20214 fpu_init(env, def);
20215 mvp_init(env, def);
20216
20217 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
20218
20219 return cpu;
20220 }
20221
20222 bool cpu_supports_cps_smp(const char *cpu_model)
20223 {
20224 const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
20225 if (!def) {
20226 return false;
20227 }
20228
20229 return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
20230 }
20231
20232 bool cpu_supports_isa(const char *cpu_model, unsigned int isa)
20233 {
20234 const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
20235 if (!def) {
20236 return false;
20237 }
20238
20239 return (def->insn_flags & isa) != 0;
20240 }
20241
20242 void cpu_set_exception_base(int vp_index, target_ulong address)
20243 {
20244 MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
20245 vp->env.exception_base = address;
20246 }
20247
20248 void cpu_state_reset(CPUMIPSState *env)
20249 {
20250 MIPSCPU *cpu = mips_env_get_cpu(env);
20251 CPUState *cs = CPU(cpu);
20252
20253 /* Reset registers to their default values */
20254 env->CP0_PRid = env->cpu_model->CP0_PRid;
20255 env->CP0_Config0 = env->cpu_model->CP0_Config0;
20256 #ifdef TARGET_WORDS_BIGENDIAN
20257 env->CP0_Config0 |= (1 << CP0C0_BE);
20258 #endif
20259 env->CP0_Config1 = env->cpu_model->CP0_Config1;
20260 env->CP0_Config2 = env->cpu_model->CP0_Config2;
20261 env->CP0_Config3 = env->cpu_model->CP0_Config3;
20262 env->CP0_Config4 = env->cpu_model->CP0_Config4;
20263 env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
20264 env->CP0_Config5 = env->cpu_model->CP0_Config5;
20265 env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
20266 env->CP0_Config6 = env->cpu_model->CP0_Config6;
20267 env->CP0_Config7 = env->cpu_model->CP0_Config7;
20268 env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
20269 << env->cpu_model->CP0_LLAddr_shift;
20270 env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
20271 env->SYNCI_Step = env->cpu_model->SYNCI_Step;
20272 env->CCRes = env->cpu_model->CCRes;
20273 env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
20274 env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
20275 env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
20276 env->current_tc = 0;
20277 env->SEGBITS = env->cpu_model->SEGBITS;
20278 env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
20279 #if defined(TARGET_MIPS64)
20280 if (env->cpu_model->insn_flags & ISA_MIPS3) {
20281 env->SEGMask |= 3ULL << 62;
20282 }
20283 #endif
20284 env->PABITS = env->cpu_model->PABITS;
20285 env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
20286 env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
20287 env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
20288 env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
20289 env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
20290 env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
20291 env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
20292 env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
20293 env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
20294 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
20295 env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
20296 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
20297 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
20298 env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
20299 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
20300 env->msair = env->cpu_model->MSAIR;
20301 env->insn_flags = env->cpu_model->insn_flags;
20302
20303 #if defined(CONFIG_USER_ONLY)
20304 env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
20305 # ifdef TARGET_MIPS64
20306 /* Enable 64-bit register mode. */
20307 env->CP0_Status |= (1 << CP0St_PX);
20308 # endif
20309 # ifdef TARGET_ABI_MIPSN64
20310 /* Enable 64-bit address mode. */
20311 env->CP0_Status |= (1 << CP0St_UX);
20312 # endif
20313 /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
20314 hardware registers. */
20315 env->CP0_HWREna |= 0x0000000F;
20316 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
20317 env->CP0_Status |= (1 << CP0St_CU1);
20318 }
20319 if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
20320 env->CP0_Status |= (1 << CP0St_MX);
20321 }
20322 # if defined(TARGET_MIPS64)
20323 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
20324 if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
20325 (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
20326 env->CP0_Status |= (1 << CP0St_FR);
20327 }
20328 # endif
20329 #else
20330 if (env->hflags & MIPS_HFLAG_BMASK) {
20331 /* If the exception was raised from a delay slot,
20332 come back to the jump. */
20333 env->CP0_ErrorEPC = (env->active_tc.PC
20334 - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
20335 } else {
20336 env->CP0_ErrorEPC = env->active_tc.PC;
20337 }
20338 env->active_tc.PC = env->exception_base;
20339 env->CP0_Random = env->tlb->nb_tlb - 1;
20340 env->tlb->tlb_in_use = env->tlb->nb_tlb;
20341 env->CP0_Wired = 0;
20342 env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
20343 env->CP0_EBase = (cs->cpu_index & 0x3FF);
20344 if (kvm_enabled()) {
20345 env->CP0_EBase |= 0x40000000;
20346 } else {
20347 env->CP0_EBase |= 0x80000000;
20348 }
20349 if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
20350 env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
20351 }
20352 env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ?
20353 0x3ff : 0xff;
20354 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
20355 /* vectored interrupts not implemented, timer on int 7,
20356 no performance counters. */
20357 env->CP0_IntCtl = 0xe0000000;
20358 {
20359 int i;
20360
20361 for (i = 0; i < 7; i++) {
20362 env->CP0_WatchLo[i] = 0;
20363 env->CP0_WatchHi[i] = 0x80000000;
20364 }
20365 env->CP0_WatchLo[7] = 0;
20366 env->CP0_WatchHi[7] = 0;
20367 }
20368 /* Count register increments in debug mode, EJTAG version 1 */
20369 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
20370
20371 cpu_mips_store_count(env, 1);
20372
20373 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
20374 int i;
20375
20376 /* Only TC0 on VPE 0 starts as active. */
20377 for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
20378 env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
20379 env->tcs[i].CP0_TCHalt = 1;
20380 }
20381 env->active_tc.CP0_TCHalt = 1;
20382 cs->halted = 1;
20383
20384 if (cs->cpu_index == 0) {
20385 /* VPE0 starts up enabled. */
20386 env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
20387 env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
20388
20389 /* TC0 starts up unhalted. */
20390 cs->halted = 0;
20391 env->active_tc.CP0_TCHalt = 0;
20392 env->tcs[0].CP0_TCHalt = 0;
20393 /* With thread 0 active. */
20394 env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
20395 env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
20396 }
20397 }
20398 #endif
20399 if ((env->insn_flags & ISA_MIPS32R6) &&
20400 (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
20401 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
20402 env->CP0_Status |= (1 << CP0St_FR);
20403 }
20404
20405 /* MSA */
20406 if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
20407 msa_reset(env);
20408 }
20409
20410 compute_hflags(env);
20411 restore_fp_status(env);
20412 restore_pamask(env);
20413 cs->exception_index = EXCP_NONE;
20414
20415 if (semihosting_get_argc()) {
20416 /* UHI interface can be used to obtain argc and argv */
20417 env->active_tc.gpr[4] = -1;
20418 }
20419 }
20420
20421 void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,
20422 target_ulong *data)
20423 {
20424 env->active_tc.PC = data[0];
20425 env->hflags &= ~MIPS_HFLAG_BMASK;
20426 env->hflags |= data[1];
20427 switch (env->hflags & MIPS_HFLAG_BMASK_BASE) {
20428 case MIPS_HFLAG_BR:
20429 break;
20430 case MIPS_HFLAG_BC:
20431 case MIPS_HFLAG_BL:
20432 case MIPS_HFLAG_B:
20433 env->btarget = data[2];
20434 break;
20435 }
20436 }
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