target/nios2/cpu.c

   1 /*
   2  * QEMU Nios II CPU
   3  *
   4  * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/module.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "exec/log.h"
  26 #include "exec/gdbstub.h"
  27 #include "hw/qdev-properties.h"
  28
  29 static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     Nios2CPU *cpu = NIOS2_CPU(cs);
  32     CPUNios2State *env = &cpu->env;
  33
  34     env->pc = value;
  35 }
  36
  37 static bool nios2_cpu_has_work(CPUState *cs)
  38 {
  39     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  40 }
  41
  42 static void nios2_cpu_reset(DeviceState *dev)
  43 {
  44     CPUState *cs = CPU(dev);
  45     Nios2CPU *cpu = NIOS2_CPU(cs);
  46     Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu);
  47     CPUNios2State *env = &cpu->env;
  48
  49     ncc->parent_reset(dev);
  50
  51     memset(env->regs, 0, sizeof(env->regs));
  52     memset(env->ctrl, 0, sizeof(env->ctrl));
  53     env->pc = cpu->reset_addr;
  54
  55 #if defined(CONFIG_USER_ONLY)
  56     /* Start in user mode with interrupts enabled. */
  57     env->ctrl[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE;
  58 #else
  59     env->ctrl[CR_STATUS] = 0;
  60 #endif
  61 }
  62
  63 #ifndef CONFIG_USER_ONLY
  64 static void nios2_cpu_set_irq(void *opaque, int irq, int level)
  65 {
  66     Nios2CPU *cpu = opaque;
  67     CPUNios2State *env = &cpu->env;
  68     CPUState *cs = CPU(cpu);
  69
  70     env->ctrl[CR_IPENDING] = deposit32(env->ctrl[CR_IPENDING], irq, 1, !!level);
  71
  72     if (env->ctrl[CR_IPENDING]) {
  73         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  74     } else {
  75         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  76     }
  77 }
  78 #endif
  79
  80 static void nios2_cpu_initfn(Object *obj)
  81 {
  82     Nios2CPU *cpu = NIOS2_CPU(obj);
  83
  84     cpu_set_cpustate_pointers(cpu);
  85
  86 #if !defined(CONFIG_USER_ONLY)
  87     mmu_init(&cpu->env);
  88
  89     /*
  90      * These interrupt lines model the IIC (internal interrupt
  91      * controller). QEMU does not currently support the EIC
  92      * (external interrupt controller) -- if we did it would be
  93      * a separate device in hw/intc with a custom interface to
  94      * the CPU, and boards using it would not wire up these IRQ lines.
  95      */
  96     qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32);
  97 #endif
  98 }
  99
 100 static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model)
 101 {
 102     return object_class_by_name(TYPE_NIOS2_CPU);
 103 }
 104
 105 static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
 106 {
 107     CPUState *cs = CPU(dev);
 108     Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
 109     Error *local_err = NULL;
 110
 111     cpu_exec_realizefn(cs, &local_err);
 112     if (local_err != NULL) {
 113         error_propagate(errp, local_err);
 114         return;
 115     }
 116
 117     qemu_init_vcpu(cs);
 118     cpu_reset(cs);
 119
 120     ncc->parent_realize(dev, errp);
 121 }
 122
 123 #ifndef CONFIG_USER_ONLY
 124 static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 125 {
 126     Nios2CPU *cpu = NIOS2_CPU(cs);
 127     CPUNios2State *env = &cpu->env;
 128
 129     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 130         (env->ctrl[CR_STATUS] & CR_STATUS_PIE) &&
 131         (env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE])) {
 132         cs->exception_index = EXCP_IRQ;
 133         nios2_cpu_do_interrupt(cs);
 134         return true;
 135     }
 136     return false;
 137 }
 138 #endif /* !CONFIG_USER_ONLY */
 139
 140 static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
 141 {
 142     /* NOTE: NiosII R2 is not supported yet. */
 143     info->mach = bfd_arch_nios2;
 144     info->print_insn = print_insn_nios2;
 145 }
 146
 147 static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
 148 {
 149     Nios2CPU *cpu = NIOS2_CPU(cs);
 150     CPUClass *cc = CPU_GET_CLASS(cs);
 151     CPUNios2State *env = &cpu->env;
 152
 153     if (n > cc->gdb_num_core_regs) {
 154         return 0;
 155     }
 156
 157     if (n < 32) {          /* GP regs */
 158         return gdb_get_reg32(mem_buf, env->regs[n]);
 159     } else if (n == 32) {    /* PC */
 160         return gdb_get_reg32(mem_buf, env->pc);
 161     } else if (n < 49) {     /* Status regs */
 162         return gdb_get_reg32(mem_buf, env->ctrl[n - 33]);
 163     }
 164
 165     /* Invalid regs */
 166     return 0;
 167 }
 168
 169 static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 170 {
 171     Nios2CPU *cpu = NIOS2_CPU(cs);
 172     CPUClass *cc = CPU_GET_CLASS(cs);
 173     CPUNios2State *env = &cpu->env;
 174
 175     if (n > cc->gdb_num_core_regs) {
 176         return 0;
 177     }
 178
 179     if (n < 32) {            /* GP regs */
 180         env->regs[n] = ldl_p(mem_buf);
 181     } else if (n == 32) {    /* PC */
 182         env->pc = ldl_p(mem_buf);
 183     } else if (n < 49) {     /* Status regs */
 184         env->ctrl[n - 33] = ldl_p(mem_buf);
 185     }
 186
 187     return 4;
 188 }
 189
 190 static Property nios2_properties[] = {
 191     DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true),
 192     /* ALTR,pid-num-bits */
 193     DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8),
 194     /* ALTR,tlb-num-ways */
 195     DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU, tlb_num_ways, 16),
 196     /* ALTR,tlb-num-entries */
 197     DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU, tlb_num_entries, 256),
 198     DEFINE_PROP_END_OF_LIST(),
 199 };
 200
 201 #ifndef CONFIG_USER_ONLY
 202 #include "hw/core/sysemu-cpu-ops.h"
 203
 204 static const struct SysemuCPUOps nios2_sysemu_ops = {
 205     .get_phys_page_debug = nios2_cpu_get_phys_page_debug,
 206 };
 207 #endif
 208
 209 #include "hw/core/tcg-cpu-ops.h"
 210
 211 static const struct TCGCPUOps nios2_tcg_ops = {
 212     .initialize = nios2_tcg_init,
 213
 214 #ifndef CONFIG_USER_ONLY
 215     .tlb_fill = nios2_cpu_tlb_fill,
 216     .cpu_exec_interrupt = nios2_cpu_exec_interrupt,
 217     .do_interrupt = nios2_cpu_do_interrupt,
 218     .do_unaligned_access = nios2_cpu_do_unaligned_access,
 219 #endif /* !CONFIG_USER_ONLY */
 220 };
 221
 222 static void nios2_cpu_class_init(ObjectClass *oc, void *data)
 223 {
 224     DeviceClass *dc = DEVICE_CLASS(oc);
 225     CPUClass *cc = CPU_CLASS(oc);
 226     Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc);
 227
 228     device_class_set_parent_realize(dc, nios2_cpu_realizefn,
 229                                     &ncc->parent_realize);
 230     device_class_set_props(dc, nios2_properties);
 231     device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset);
 232
 233     cc->class_by_name = nios2_cpu_class_by_name;
 234     cc->has_work = nios2_cpu_has_work;
 235     cc->dump_state = nios2_cpu_dump_state;
 236     cc->set_pc = nios2_cpu_set_pc;
 237     cc->disas_set_info = nios2_cpu_disas_set_info;
 238 #ifndef CONFIG_USER_ONLY
 239     cc->sysemu_ops = &nios2_sysemu_ops;
 240 #endif
 241     cc->gdb_read_register = nios2_cpu_gdb_read_register;
 242     cc->gdb_write_register = nios2_cpu_gdb_write_register;
 243     cc->gdb_num_core_regs = 49;
 244     cc->tcg_ops = &nios2_tcg_ops;
 245 }
 246
 247 static const TypeInfo nios2_cpu_type_info = {
 248     .name = TYPE_NIOS2_CPU,
 249     .parent = TYPE_CPU,
 250     .instance_size = sizeof(Nios2CPU),
 251     .instance_init = nios2_cpu_initfn,
 252     .class_size = sizeof(Nios2CPUClass),
 253     .class_init = nios2_cpu_class_init,
 254 };
 255
 256 static void nios2_cpu_register_types(void)
 257 {
 258     type_register_static(&nios2_cpu_type_info);
 259 }
 260
 261 type_init(nios2_cpu_register_types)