target/nios2/cpu.h

   1 /*
   2  * Altera Nios II virtual CPU header
   3  *
   4  * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #ifndef NIOS2_CPU_H
  22 #define NIOS2_CPU_H
  23
  24 #include "qemu-common.h"
  25 #include "exec/cpu-defs.h"
  26 #include "qom/cpu.h"
  27
  28 typedef struct CPUNios2State CPUNios2State;
  29 #if !defined(CONFIG_USER_ONLY)
  30 #include "mmu.h"
  31 #endif
  32
  33 #define TYPE_NIOS2_CPU "nios2-cpu"
  34
  35 #define NIOS2_CPU_CLASS(klass) \
  36     OBJECT_CLASS_CHECK(Nios2CPUClass, (klass), TYPE_NIOS2_CPU)
  37 #define NIOS2_CPU(obj) \
  38     OBJECT_CHECK(Nios2CPU, (obj), TYPE_NIOS2_CPU)
  39 #define NIOS2_CPU_GET_CLASS(obj) \
  40     OBJECT_GET_CLASS(Nios2CPUClass, (obj), TYPE_NIOS2_CPU)
  41
  42 /**
  43  * Nios2CPUClass:
  44  * @parent_reset: The parent class' reset handler.
  45  *
  46  * A Nios2 CPU model.
  47  */
  48 typedef struct Nios2CPUClass {
  49     /*< private >*/
  50     CPUClass parent_class;
  51     /*< public >*/
  52
  53     DeviceRealize parent_realize;
  54     void (*parent_reset)(CPUState *cpu);
  55 } Nios2CPUClass;
  56
  57 #define TARGET_HAS_ICE 1
  58
  59 /* Configuration options for Nios II */
  60 #define RESET_ADDRESS         0x00000000
  61 #define EXCEPTION_ADDRESS     0x00000004
  62 #define FAST_TLB_MISS_ADDRESS 0x00000008
  63
  64
  65 /* GP regs + CR regs + PC */
  66 #define NUM_CORE_REGS (32 + 32 + 1)
  67
  68 /* General purpose register aliases */
  69 #define R_ZERO   0
  70 #define R_AT     1
  71 #define R_RET0   2
  72 #define R_RET1   3
  73 #define R_ARG0   4
  74 #define R_ARG1   5
  75 #define R_ARG2   6
  76 #define R_ARG3   7
  77 #define R_ET     24
  78 #define R_BT     25
  79 #define R_GP     26
  80 #define R_SP     27
  81 #define R_FP     28
  82 #define R_EA     29
  83 #define R_BA     30
  84 #define R_RA     31
  85
  86 /* Control register aliases */
  87 #define CR_BASE  32
  88 #define CR_STATUS    (CR_BASE + 0)
  89 #define   CR_STATUS_PIE  (1 << 0)
  90 #define   CR_STATUS_U    (1 << 1)
  91 #define   CR_STATUS_EH   (1 << 2)
  92 #define   CR_STATUS_IH   (1 << 3)
  93 #define   CR_STATUS_IL   (63 << 4)
  94 #define   CR_STATUS_CRS  (63 << 10)
  95 #define   CR_STATUS_PRS  (63 << 16)
  96 #define   CR_STATUS_NMI  (1 << 22)
  97 #define   CR_STATUS_RSIE (1 << 23)
  98 #define CR_ESTATUS   (CR_BASE + 1)
  99 #define CR_BSTATUS   (CR_BASE + 2)
 100 #define CR_IENABLE   (CR_BASE + 3)
 101 #define CR_IPENDING  (CR_BASE + 4)
 102 #define CR_CPUID     (CR_BASE + 5)
 103 #define CR_CTL6      (CR_BASE + 6)
 104 #define CR_EXCEPTION (CR_BASE + 7)
 105 #define CR_PTEADDR   (CR_BASE + 8)
 106 #define   CR_PTEADDR_PTBASE_SHIFT 22
 107 #define   CR_PTEADDR_PTBASE_MASK  (0x3FF << CR_PTEADDR_PTBASE_SHIFT)
 108 #define   CR_PTEADDR_VPN_SHIFT    2
 109 #define   CR_PTEADDR_VPN_MASK     (0xFFFFF << CR_PTEADDR_VPN_SHIFT)
 110 #define CR_TLBACC    (CR_BASE + 9)
 111 #define   CR_TLBACC_IGN_SHIFT 25
 112 #define   CR_TLBACC_IGN_MASK  (0x7F << CR_TLBACC_IGN_SHIFT)
 113 #define   CR_TLBACC_C         (1 << 24)
 114 #define   CR_TLBACC_R         (1 << 23)
 115 #define   CR_TLBACC_W         (1 << 22)
 116 #define   CR_TLBACC_X         (1 << 21)
 117 #define   CR_TLBACC_G         (1 << 20)
 118 #define   CR_TLBACC_PFN_MASK  0x000FFFFF
 119 #define CR_TLBMISC   (CR_BASE + 10)
 120 #define   CR_TLBMISC_WAY_SHIFT 20
 121 #define   CR_TLBMISC_WAY_MASK  (0xF << CR_TLBMISC_WAY_SHIFT)
 122 #define   CR_TLBMISC_RD        (1 << 19)
 123 #define   CR_TLBMISC_WR        (1 << 18)
 124 #define   CR_TLBMISC_PID_SHIFT 4
 125 #define   CR_TLBMISC_PID_MASK  (0x3FFF << CR_TLBMISC_PID_SHIFT)
 126 #define   CR_TLBMISC_DBL       (1 << 3)
 127 #define   CR_TLBMISC_BAD       (1 << 2)
 128 #define   CR_TLBMISC_PERM      (1 << 1)
 129 #define   CR_TLBMISC_D         (1 << 0)
 130 #define CR_ENCINJ    (CR_BASE + 11)
 131 #define CR_BADADDR   (CR_BASE + 12)
 132 #define CR_CONFIG    (CR_BASE + 13)
 133 #define CR_MPUBASE   (CR_BASE + 14)
 134 #define CR_MPUACC    (CR_BASE + 15)
 135
 136 /* Other registers */
 137 #define R_PC         64
 138
 139 /* Exceptions */
 140 #define EXCP_BREAK    0x1000
 141 #define EXCP_RESET    0
 142 #define EXCP_PRESET   1
 143 #define EXCP_IRQ      2
 144 #define EXCP_TRAP     3
 145 #define EXCP_UNIMPL   4
 146 #define EXCP_ILLEGAL  5
 147 #define EXCP_UNALIGN  6
 148 #define EXCP_UNALIGND 7
 149 #define EXCP_DIV      8
 150 #define EXCP_SUPERA   9
 151 #define EXCP_SUPERI   10
 152 #define EXCP_SUPERD   11
 153 #define EXCP_TLBD     12
 154 #define EXCP_TLBX     13
 155 #define EXCP_TLBR     14
 156 #define EXCP_TLBW     15
 157 #define EXCP_MPUI     16
 158 #define EXCP_MPUD     17
 159
 160 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 161
 162 struct CPUNios2State {
 163     uint32_t regs[NUM_CORE_REGS];
 164
 165 #if !defined(CONFIG_USER_ONLY)
 166     Nios2MMU mmu;
 167
 168     uint32_t irq_pending;
 169 #endif
 170
 171     CPU_COMMON
 172 };
 173
 174 /**
 175  * Nios2CPU:
 176  * @env: #CPUNios2State
 177  *
 178  * A Nios2 CPU.
 179  */
 180 typedef struct Nios2CPU {
 181     /*< private >*/
 182     CPUState parent_obj;
 183     /*< public >*/
 184
 185     CPUNios2State env;
 186     bool mmu_present;
 187     uint32_t pid_num_bits;
 188     uint32_t tlb_num_ways;
 189     uint32_t tlb_num_entries;
 190
 191     /* Addresses that are hard-coded in the FPGA build settings */
 192     uint32_t reset_addr;
 193     uint32_t exception_addr;
 194     uint32_t fast_tlb_miss_addr;
 195 } Nios2CPU;
 196
 197 static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State *env)
 198 {
 199     return NIOS2_CPU(container_of(env, Nios2CPU, env));
 200 }
 201
 202 #define ENV_OFFSET offsetof(Nios2CPU, env)
 203
 204 void nios2_tcg_init(void);
 205 void nios2_cpu_do_interrupt(CPUState *cs);
 206 int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc);
 207 void dump_mmu(CPUNios2State *env);
 208 void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 209 hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 210 void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 211                                    MMUAccessType access_type,
 212                                    int mmu_idx, uintptr_t retaddr);
 213
 214 qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu);
 215 void nios2_check_interrupts(CPUNios2State *env);
 216
 217 void do_nios2_semihosting(CPUNios2State *env);
 218
 219 #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU
 220
 221 #define cpu_gen_code cpu_nios2_gen_code
 222 #define cpu_signal_handler cpu_nios2_signal_handler
 223
 224 #define CPU_SAVE_VERSION 1
 225
 226 /* MMU modes definitions */
 227 #define MMU_MODE0_SUFFIX _kernel
 228 #define MMU_MODE1_SUFFIX _user
 229 #define MMU_SUPERVISOR_IDX  0
 230 #define MMU_USER_IDX        1
 231
 232 static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
 233 {
 234     return (env->regs[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
 235                                                   MMU_SUPERVISOR_IDX;
 236 }
 237
 238 bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 239                         MMUAccessType access_type, int mmu_idx,
 240                         bool probe, uintptr_t retaddr);
 241
 242 static inline int cpu_interrupts_enabled(CPUNios2State *env)
 243 {
 244     return env->regs[CR_STATUS] & CR_STATUS_PIE;
 245 }
 246
 247 typedef CPUNios2State CPUArchState;
 248 typedef Nios2CPU ArchCPU;
 249
 250 #include "exec/cpu-all.h"
 251
 252 static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
 253                                         target_ulong *cs_base, uint32_t *flags)
 254 {
 255     *pc = env->regs[R_PC];
 256     *cs_base = 0;
 257     *flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U));
 258 }
 259
 260 #endif /* NIOS2_CPU_H */