target/openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "qemu/qemu-print.h"
  23 #include "cpu.h"
  24 #include "exec/exec-all.h"
  25
  26 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
  27 {
  28     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  29
  30     cpu->env.pc = value;
  31     cpu->env.dflag = 0;
  32 }
  33
  34 static vaddr openrisc_cpu_get_pc(CPUState *cs)
  35 {
  36     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  37
  38     return cpu->env.pc;
  39 }
  40
  41 static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
  42                                              const TranslationBlock *tb)
  43 {
  44     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  45
  46     cpu->env.pc = tb->pc;
  47 }
  48
  49
  50 static bool openrisc_cpu_has_work(CPUState *cs)
  51 {
  52     return cs->interrupt_request & (CPU_INTERRUPT_HARD |
  53                                     CPU_INTERRUPT_TIMER);
  54 }
  55
  56 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
  57 {
  58     info->print_insn = print_insn_or1k;
  59 }
  60
  61 static void openrisc_cpu_reset(DeviceState *dev)
  62 {
  63     CPUState *s = CPU(dev);
  64     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  65     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  66
  67     occ->parent_reset(dev);
  68
  69     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
  70
  71     cpu->env.pc = 0x100;
  72     cpu->env.sr = SR_FO | SR_SM;
  73     cpu->env.lock_addr = -1;
  74     s->exception_index = -1;
  75     cpu_set_fpcsr(&cpu->env, 0);
  76
  77 #ifndef CONFIG_USER_ONLY
  78     cpu->env.picmr = 0x00000000;
  79     cpu->env.picsr = 0x00000000;
  80
  81     cpu->env.ttmr = 0x00000000;
  82 #endif
  83 }
  84
  85 #ifndef CONFIG_USER_ONLY
  86 static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
  87 {
  88     OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
  89     CPUState *cs = CPU(cpu);
  90     uint32_t irq_bit;
  91
  92     if (irq > 31 || irq < 0) {
  93         return;
  94     }
  95
  96     irq_bit = 1U << irq;
  97
  98     if (level) {
  99         cpu->env.picsr |= irq_bit;
 100     } else {
 101         cpu->env.picsr &= ~irq_bit;
 102     }
 103
 104     if (cpu->env.picsr & cpu->env.picmr) {
 105         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 106     } else {
 107         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 108     }
 109 }
 110 #endif
 111
 112 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
 113 {
 114     CPUState *cs = CPU(dev);
 115     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
 116     Error *local_err = NULL;
 117
 118     cpu_exec_realizefn(cs, &local_err);
 119     if (local_err != NULL) {
 120         error_propagate(errp, local_err);
 121         return;
 122     }
 123
 124     qemu_init_vcpu(cs);
 125     cpu_reset(cs);
 126
 127     occ->parent_realize(dev, errp);
 128 }
 129
 130 static void openrisc_cpu_initfn(Object *obj)
 131 {
 132     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 133
 134     cpu_set_cpustate_pointers(cpu);
 135
 136 #ifndef CONFIG_USER_ONLY
 137     qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS);
 138 #endif
 139 }
 140
 141 /* CPU models */
 142
 143 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
 144 {
 145     ObjectClass *oc;
 146     char *typename;
 147
 148     typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
 149     oc = object_class_by_name(typename);
 150     g_free(typename);
 151     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
 152                        object_class_is_abstract(oc))) {
 153         return NULL;
 154     }
 155     return oc;
 156 }
 157
 158 static void or1200_initfn(Object *obj)
 159 {
 160     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 161
 162     cpu->env.vr = 0x13000008;
 163     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
 164     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
 165                        CPUCFGR_EVBARP;
 166
 167     /* 1Way, TLB_SIZE entries.  */
 168     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
 169                       | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
 170     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
 171                       | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
 172 }
 173
 174 static void openrisc_any_initfn(Object *obj)
 175 {
 176     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 177
 178     cpu->env.vr = 0x13000040;   /* Obsolete VER + UVRP for new SPRs */
 179     cpu->env.vr2 = 0;           /* No version specific id */
 180     cpu->env.avr = 0x01030000;  /* Architecture v1.3 */
 181
 182     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
 183     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
 184                        CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S;
 185
 186     /* 1Way, TLB_SIZE entries.  */
 187     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
 188                       | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
 189     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
 190                       | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
 191 }
 192
 193 #ifndef CONFIG_USER_ONLY
 194 #include "hw/core/sysemu-cpu-ops.h"
 195
 196 static const struct SysemuCPUOps openrisc_sysemu_ops = {
 197     .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
 198 };
 199 #endif
 200
 201 #include "hw/core/tcg-cpu-ops.h"
 202
 203 static const struct TCGCPUOps openrisc_tcg_ops = {
 204     .initialize = openrisc_translate_init,
 205     .synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
 206
 207 #ifndef CONFIG_USER_ONLY
 208     .tlb_fill = openrisc_cpu_tlb_fill,
 209     .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
 210     .do_interrupt = openrisc_cpu_do_interrupt,
 211 #endif /* !CONFIG_USER_ONLY */
 212 };
 213
 214 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 215 {
 216     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 217     CPUClass *cc = CPU_CLASS(occ);
 218     DeviceClass *dc = DEVICE_CLASS(oc);
 219
 220     device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
 221                                     &occ->parent_realize);
 222     device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset);
 223
 224     cc->class_by_name = openrisc_cpu_class_by_name;
 225     cc->has_work = openrisc_cpu_has_work;
 226     cc->dump_state = openrisc_cpu_dump_state;
 227     cc->set_pc = openrisc_cpu_set_pc;
 228     cc->get_pc = openrisc_cpu_get_pc;
 229     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
 230     cc->gdb_write_register = openrisc_cpu_gdb_write_register;
 231 #ifndef CONFIG_USER_ONLY
 232     dc->vmsd = &vmstate_openrisc_cpu;
 233     cc->sysemu_ops = &openrisc_sysemu_ops;
 234 #endif
 235     cc->gdb_num_core_regs = 32 + 3;
 236     cc->disas_set_info = openrisc_disas_set_info;
 237     cc->tcg_ops = &openrisc_tcg_ops;
 238 }
 239
 240 /* Sort alphabetically by type name, except for "any". */
 241 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 242 {
 243     ObjectClass *class_a = (ObjectClass *)a;
 244     ObjectClass *class_b = (ObjectClass *)b;
 245     const char *name_a, *name_b;
 246
 247     name_a = object_class_get_name(class_a);
 248     name_b = object_class_get_name(class_b);
 249     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
 250         return 1;
 251     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
 252         return -1;
 253     } else {
 254         return strcmp(name_a, name_b);
 255     }
 256 }
 257
 258 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 259 {
 260     ObjectClass *oc = data;
 261     const char *typename;
 262     char *name;
 263
 264     typename = object_class_get_name(oc);
 265     name = g_strndup(typename,
 266                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
 267     qemu_printf("  %s\n", name);
 268     g_free(name);
 269 }
 270
 271 void cpu_openrisc_list(void)
 272 {
 273     GSList *list;
 274
 275     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 276     list = g_slist_sort(list, openrisc_cpu_list_compare);
 277     qemu_printf("Available CPUs:\n");
 278     g_slist_foreach(list, openrisc_cpu_list_entry, NULL);
 279     g_slist_free(list);
 280 }
 281
 282 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
 283     {                                               \
 284         .parent = TYPE_OPENRISC_CPU,                \
 285         .instance_init = initfn,                    \
 286         .name = OPENRISC_CPU_TYPE_NAME(cpu_model),  \
 287     }
 288
 289 static const TypeInfo openrisc_cpus_type_infos[] = {
 290     { /* base class should be registered first */
 291         .name = TYPE_OPENRISC_CPU,
 292         .parent = TYPE_CPU,
 293         .instance_size = sizeof(OpenRISCCPU),
 294         .instance_init = openrisc_cpu_initfn,
 295         .abstract = true,
 296         .class_size = sizeof(OpenRISCCPUClass),
 297         .class_init = openrisc_cpu_class_init,
 298     },
 299     DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn),
 300     DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn),
 301 };
 302
 303 DEFINE_TYPES(openrisc_cpus_type_infos)