target/openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "qemu/qemu-print.h"
  23 #include "cpu.h"
  24 #include "exec/exec-all.h"
  25 #include "fpu/softfloat-helpers.h"
  26 #include "tcg/tcg.h"
  27
  28 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
  29 {
  30     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  31
  32     cpu->env.pc = value;
  33     cpu->env.dflag = 0;
  34 }
  35
  36 static vaddr openrisc_cpu_get_pc(CPUState *cs)
  37 {
  38     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  39
  40     return cpu->env.pc;
  41 }
  42
  43 static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
  44                                              const TranslationBlock *tb)
  45 {
  46     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  47
  48     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
  49     cpu->env.pc = tb->pc;
  50 }
  51
  52 static void openrisc_restore_state_to_opc(CPUState *cs,
  53                                           const TranslationBlock *tb,
  54                                           const uint64_t *data)
  55 {
  56     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  57
  58     cpu->env.pc = data[0];
  59     cpu->env.dflag = data[1] & 1;
  60     if (data[1] & 2) {
  61         cpu->env.ppc = cpu->env.pc - 4;
  62     }
  63 }
  64
  65 static bool openrisc_cpu_has_work(CPUState *cs)
  66 {
  67     return cs->interrupt_request & (CPU_INTERRUPT_HARD |
  68                                     CPU_INTERRUPT_TIMER);
  69 }
  70
  71 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
  72 {
  73     info->print_insn = print_insn_or1k;
  74 }
  75
  76 static void openrisc_cpu_reset_hold(Object *obj)
  77 {
  78     CPUState *s = CPU(obj);
  79     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  80     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  81
  82     if (occ->parent_phases.hold) {
  83         occ->parent_phases.hold(obj);
  84     }
  85
  86     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
  87
  88     cpu->env.pc = 0x100;
  89     cpu->env.sr = SR_FO | SR_SM;
  90     cpu->env.lock_addr = -1;
  91     s->exception_index = -1;
  92     cpu_set_fpcsr(&cpu->env, 0);
  93
  94     set_float_detect_tininess(float_tininess_before_rounding,
  95                               &cpu->env.fp_status);
  96
  97 #ifndef CONFIG_USER_ONLY
  98     cpu->env.picmr = 0x00000000;
  99     cpu->env.picsr = 0x00000000;
 100
 101     cpu->env.ttmr = 0x00000000;
 102 #endif
 103 }
 104
 105 #ifndef CONFIG_USER_ONLY
 106 static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
 107 {
 108     OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
 109     CPUState *cs = CPU(cpu);
 110     uint32_t irq_bit;
 111
 112     if (irq > 31 || irq < 0) {
 113         return;
 114     }
 115
 116     irq_bit = 1U << irq;
 117
 118     if (level) {
 119         cpu->env.picsr |= irq_bit;
 120     } else {
 121         cpu->env.picsr &= ~irq_bit;
 122     }
 123
 124     if (cpu->env.picsr & cpu->env.picmr) {
 125         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 126     } else {
 127         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 128     }
 129 }
 130 #endif
 131
 132 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
 133 {
 134     CPUState *cs = CPU(dev);
 135     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
 136     Error *local_err = NULL;
 137
 138     cpu_exec_realizefn(cs, &local_err);
 139     if (local_err != NULL) {
 140         error_propagate(errp, local_err);
 141         return;
 142     }
 143
 144     qemu_init_vcpu(cs);
 145     cpu_reset(cs);
 146
 147     occ->parent_realize(dev, errp);
 148 }
 149
 150 static void openrisc_cpu_initfn(Object *obj)
 151 {
 152     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 153
 154     cpu_set_cpustate_pointers(cpu);
 155
 156 #ifndef CONFIG_USER_ONLY
 157     qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS);
 158 #endif
 159 }
 160
 161 /* CPU models */
 162
 163 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
 164 {
 165     ObjectClass *oc;
 166     char *typename;
 167
 168     typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
 169     oc = object_class_by_name(typename);
 170     g_free(typename);
 171     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
 172                        object_class_is_abstract(oc))) {
 173         return NULL;
 174     }
 175     return oc;
 176 }
 177
 178 static void or1200_initfn(Object *obj)
 179 {
 180     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 181
 182     cpu->env.vr = 0x13000008;
 183     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
 184     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
 185                        CPUCFGR_EVBARP;
 186
 187     /* 1Way, TLB_SIZE entries.  */
 188     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
 189                       | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
 190     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
 191                       | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
 192 }
 193
 194 static void openrisc_any_initfn(Object *obj)
 195 {
 196     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 197
 198     cpu->env.vr = 0x13000040;   /* Obsolete VER + UVRP for new SPRs */
 199     cpu->env.vr2 = 0;           /* No version specific id */
 200     cpu->env.avr = 0x01030000;  /* Architecture v1.3 */
 201
 202     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
 203     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
 204                        CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S;
 205
 206     /* 1Way, TLB_SIZE entries.  */
 207     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
 208                       | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
 209     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
 210                       | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
 211 }
 212
 213 #ifndef CONFIG_USER_ONLY
 214 #include "hw/core/sysemu-cpu-ops.h"
 215
 216 static const struct SysemuCPUOps openrisc_sysemu_ops = {
 217     .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
 218 };
 219 #endif
 220
 221 #include "hw/core/tcg-cpu-ops.h"
 222
 223 static const struct TCGCPUOps openrisc_tcg_ops = {
 224     .initialize = openrisc_translate_init,
 225     .synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
 226     .restore_state_to_opc = openrisc_restore_state_to_opc,
 227
 228 #ifndef CONFIG_USER_ONLY
 229     .tlb_fill = openrisc_cpu_tlb_fill,
 230     .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
 231     .do_interrupt = openrisc_cpu_do_interrupt,
 232 #endif /* !CONFIG_USER_ONLY */
 233 };
 234
 235 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 236 {
 237     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 238     CPUClass *cc = CPU_CLASS(occ);
 239     DeviceClass *dc = DEVICE_CLASS(oc);
 240     ResettableClass *rc = RESETTABLE_CLASS(oc);
 241
 242     device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
 243                                     &occ->parent_realize);
 244     resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL,
 245                                        &occ->parent_phases);
 246
 247     cc->class_by_name = openrisc_cpu_class_by_name;
 248     cc->has_work = openrisc_cpu_has_work;
 249     cc->dump_state = openrisc_cpu_dump_state;
 250     cc->set_pc = openrisc_cpu_set_pc;
 251     cc->get_pc = openrisc_cpu_get_pc;
 252     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
 253     cc->gdb_write_register = openrisc_cpu_gdb_write_register;
 254 #ifndef CONFIG_USER_ONLY
 255     dc->vmsd = &vmstate_openrisc_cpu;
 256     cc->sysemu_ops = &openrisc_sysemu_ops;
 257 #endif
 258     cc->gdb_num_core_regs = 32 + 3;
 259     cc->disas_set_info = openrisc_disas_set_info;
 260     cc->tcg_ops = &openrisc_tcg_ops;
 261 }
 262
 263 /* Sort alphabetically by type name, except for "any". */
 264 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 265 {
 266     ObjectClass *class_a = (ObjectClass *)a;
 267     ObjectClass *class_b = (ObjectClass *)b;
 268     const char *name_a, *name_b;
 269
 270     name_a = object_class_get_name(class_a);
 271     name_b = object_class_get_name(class_b);
 272     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
 273         return 1;
 274     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
 275         return -1;
 276     } else {
 277         return strcmp(name_a, name_b);
 278     }
 279 }
 280
 281 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 282 {
 283     ObjectClass *oc = data;
 284     const char *typename;
 285     char *name;
 286
 287     typename = object_class_get_name(oc);
 288     name = g_strndup(typename,
 289                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
 290     qemu_printf("  %s\n", name);
 291     g_free(name);
 292 }
 293
 294 void cpu_openrisc_list(void)
 295 {
 296     GSList *list;
 297
 298     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 299     list = g_slist_sort(list, openrisc_cpu_list_compare);
 300     qemu_printf("Available CPUs:\n");
 301     g_slist_foreach(list, openrisc_cpu_list_entry, NULL);
 302     g_slist_free(list);
 303 }
 304
 305 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
 306     {                                               \
 307         .parent = TYPE_OPENRISC_CPU,                \
 308         .instance_init = initfn,                    \
 309         .name = OPENRISC_CPU_TYPE_NAME(cpu_model),  \
 310     }
 311
 312 static const TypeInfo openrisc_cpus_type_infos[] = {
 313     { /* base class should be registered first */
 314         .name = TYPE_OPENRISC_CPU,
 315         .parent = TYPE_CPU,
 316         .instance_size = sizeof(OpenRISCCPU),
 317         .instance_align = __alignof(OpenRISCCPU),
 318         .instance_init = openrisc_cpu_initfn,
 319         .abstract = true,
 320         .class_size = sizeof(OpenRISCCPUClass),
 321         .class_init = openrisc_cpu_class_init,
 322     },
 323     DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn),
 324     DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn),
 325 };
 326
 327 DEFINE_TYPES(openrisc_cpus_type_infos)