]>
git.proxmox.com Git - mirror_qemu.git/blob - target/openrisc/sys_helper.c
2 * OpenRISC system instructions helper routines
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Zhizhou Zhang <etouzh@gmail.com>
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25 #include "exception.h"
26 #include "sysemu/sysemu.h"
27 #ifndef CONFIG_USER_ONLY
28 #include "hw/boards.h"
31 #define TO_SPR(group, number) (((group) << 11) + (number))
33 void HELPER(mtspr
)(CPUOpenRISCState
*env
, target_ulong spr
, target_ulong rb
)
35 #ifndef CONFIG_USER_ONLY
36 OpenRISCCPU
*cpu
= env_archcpu(env
);
37 CPUState
*cs
= env_cpu(env
);
42 case TO_SPR(0, 11): /* EVBAR */
46 case TO_SPR(0, 16): /* NPC */
47 cpu_restore_state(cs
, GETPC(), true);
48 /* ??? Mirror or1ksim in not trashing delayed branch state
49 when "jumping" to the current instruction. */
57 case TO_SPR(0, 17): /* SR */
61 case TO_SPR(0, 32): /* EPCR */
65 case TO_SPR(0, 48): /* EEAR */
69 case TO_SPR(0, 64): /* ESR */
73 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
75 env
->shadow_gpr
[idx
/ 32][idx
% 32] = rb
;
78 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE
- 1): /* DTLBW0MR 0-127 */
79 idx
= spr
- TO_SPR(1, 512);
80 mr
= env
->tlb
.dtlb
[idx
].mr
;
82 tlb_flush_page(cs
, mr
& TARGET_PAGE_MASK
);
85 tlb_flush_page(cs
, rb
& TARGET_PAGE_MASK
);
87 env
->tlb
.dtlb
[idx
].mr
= rb
;
89 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE
- 1): /* DTLBW0TR 0-127 */
90 idx
= spr
- TO_SPR(1, 640);
91 env
->tlb
.dtlb
[idx
].tr
= rb
;
93 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
94 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
95 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
96 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
97 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
98 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
101 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE
- 1): /* ITLBW0MR 0-127 */
102 idx
= spr
- TO_SPR(2, 512);
103 mr
= env
->tlb
.itlb
[idx
].mr
;
105 tlb_flush_page(cs
, mr
& TARGET_PAGE_MASK
);
108 tlb_flush_page(cs
, rb
& TARGET_PAGE_MASK
);
110 env
->tlb
.itlb
[idx
].mr
= rb
;
112 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE
- 1): /* ITLBW0TR 0-127 */
113 idx
= spr
- TO_SPR(2, 640);
114 env
->tlb
.itlb
[idx
].tr
= rb
;
116 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
117 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
118 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
119 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
120 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
121 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
124 case TO_SPR(5, 1): /* MACLO */
125 env
->mac
= deposit64(env
->mac
, 0, 32, rb
);
127 case TO_SPR(5, 2): /* MACHI */
128 env
->mac
= deposit64(env
->mac
, 32, 32, rb
);
130 case TO_SPR(8, 0): /* PMR */
132 if (env
->pmr
& PMR_DME
|| env
->pmr
& PMR_SME
) {
133 cpu_restore_state(cs
, GETPC(), true);
136 raise_exception(cpu
, EXCP_HALTED
);
139 case TO_SPR(9, 0): /* PICMR */
142 case TO_SPR(9, 2): /* PICSR */
145 case TO_SPR(10, 0): /* TTMR */
147 if ((env
->ttmr
& TTMR_M
) ^ (rb
& TTMR_M
)) {
148 switch (rb
& TTMR_M
) {
150 cpu_openrisc_count_stop(cpu
);
155 cpu_openrisc_count_start(cpu
);
162 int ip
= env
->ttmr
& TTMR_IP
;
164 if (rb
& TTMR_IP
) { /* Keep IP bit. */
165 env
->ttmr
= (rb
& ~TTMR_IP
) | ip
;
166 } else { /* Clear IP bit. */
167 env
->ttmr
= rb
& ~TTMR_IP
;
168 cs
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
171 cpu_openrisc_timer_update(cpu
);
175 case TO_SPR(10, 1): /* TTCR */
176 cpu_openrisc_count_set(cpu
, rb
);
177 if (env
->ttmr
& TIMER_NONE
) {
180 cpu_openrisc_timer_update(cpu
);
188 target_ulong
HELPER(mfspr
)(CPUOpenRISCState
*env
, target_ulong rd
,
191 #ifndef CONFIG_USER_ONLY
192 MachineState
*ms
= MACHINE(qdev_get_machine());
193 OpenRISCCPU
*cpu
= env_archcpu(env
);
194 CPUState
*cs
= env_cpu(env
);
198 case TO_SPR(0, 0): /* VR */
201 case TO_SPR(0, 1): /* UPR */
204 case TO_SPR(0, 2): /* CPUCFGR */
207 case TO_SPR(0, 3): /* DMMUCFGR */
208 return env
->dmmucfgr
;
210 case TO_SPR(0, 4): /* IMMUCFGR */
211 return env
->immucfgr
;
213 case TO_SPR(0, 9): /* VR2 */
216 case TO_SPR(0, 10): /* AVR */
219 case TO_SPR(0, 11): /* EVBAR */
222 case TO_SPR(0, 16): /* NPC (equals PC) */
223 cpu_restore_state(cs
, GETPC(), false);
226 case TO_SPR(0, 17): /* SR */
227 return cpu_get_sr(env
);
229 case TO_SPR(0, 18): /* PPC */
230 cpu_restore_state(cs
, GETPC(), false);
233 case TO_SPR(0, 32): /* EPCR */
236 case TO_SPR(0, 48): /* EEAR */
239 case TO_SPR(0, 64): /* ESR */
242 case TO_SPR(0, 128): /* COREID */
243 return cpu
->parent_obj
.cpu_index
;
245 case TO_SPR(0, 129): /* NUMCORES */
246 return ms
->smp
.max_cpus
;
248 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
250 return env
->shadow_gpr
[idx
/ 32][idx
% 32];
252 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE
- 1): /* DTLBW0MR 0-127 */
253 idx
= spr
- TO_SPR(1, 512);
254 return env
->tlb
.dtlb
[idx
].mr
;
256 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE
- 1): /* DTLBW0TR 0-127 */
257 idx
= spr
- TO_SPR(1, 640);
258 return env
->tlb
.dtlb
[idx
].tr
;
260 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
261 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
262 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
263 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
264 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
265 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
268 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE
- 1): /* ITLBW0MR 0-127 */
269 idx
= spr
- TO_SPR(2, 512);
270 return env
->tlb
.itlb
[idx
].mr
;
272 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE
- 1): /* ITLBW0TR 0-127 */
273 idx
= spr
- TO_SPR(2, 640);
274 return env
->tlb
.itlb
[idx
].tr
;
276 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
277 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
278 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
279 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
280 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
281 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
284 case TO_SPR(5, 1): /* MACLO */
285 return (uint32_t)env
->mac
;
287 case TO_SPR(5, 2): /* MACHI */
288 return env
->mac
>> 32;
291 case TO_SPR(8, 0): /* PMR */
294 case TO_SPR(9, 0): /* PICMR */
297 case TO_SPR(9, 2): /* PICSR */
300 case TO_SPR(10, 0): /* TTMR */
303 case TO_SPR(10, 1): /* TTCR */
304 cpu_openrisc_count_update(cpu
);
305 return cpu_openrisc_count_get(cpu
);
312 /* for rd is passed in, if rd unchanged, just keep it back. */